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// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of rs_cfg_fe1
//
// Generated
// by: lutscher
// on: Wed Dec 14 16:43:30 2005
// cmd: /home/lutscher/work/MIX/mix_0.pl -strip -nodelta ../../reg_shell.sxc
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: lutscher $
// $Id: rs_cfg_fe1.v,v 1.8 2005/12/14 15:43:47 lutscher Exp $
// $Date: 2005/12/14 15:43:47 $
// $Log: rs_cfg_fe1.v,v $
// Revision 1.8 2005/12/14 15:43:47 lutscher
// updated
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.43 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of rs_cfg_fe1
//
// No user `defines in this module
`define tie0_1_c 1'b0
module rs_cfg_fe1
//
// Generated module rs_cfg_fe1_i
//
(
input wire clk_f20,
input wire res_f20_n_i,
input wire test_i,
input wire [13:0] addr_i,
input wire trans_start,
input wire [31:0] wr_data_i,
input wire rd_wr_i,
output wire [31:0] rd_data_o,
output wire rd_err_o,
output wire trans_done_o,
output wire Cvbsdetect_par_o,
input wire Cvbsdetect_set_p_i,
input wire ycdetect_par_i,
input wire usr_r_test_par_i,
input wire usr_r_test_trans_done_p_i,
output reg usr_r_test_rd_p_o,
input wire [7:0] sha_r_test_par_i,
output wire [4:0] mvstart_par_o,
output reg [5:0] mvstop_par_o,
output wire [3:0] usr_rw_test_par_o,
input wire [3:0] usr_rw_test_par_i,
input wire usr_rw_test_trans_done_p_i,
output reg usr_rw_test_rd_p_o,
output reg usr_rw_test_wr_p_o,
output reg [31:0] sha_rw2_par_o,
output wire [15:0] wd_16_test_par_o,
output wire [7:0] wd_16_test2_par_o,
input wire upd_rw_en_i,
input wire upd_rw_force_i,
input wire upd_rw_i,
input wire upd_r_en_i,
input wire upd_r_force_i,
input wire upd_r_i
);
// Module parameters:
parameter sync = 0;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire int_upd_r_p;
wire int_upd_rw_p;
wire tie0_1;
wire u4_sync_generic_i_trans_start_p;
wire u5_sync_rst_i_int_rst_n;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign tie0_1 = `tie0_1_c;
/*
Generator information:
used package Micronas::Reg is version 1.16
this module is version 1.20
*/
/*
local definitions
*/
`define REG_00_OFFS 0 // reg_0x0
`define REG_04_OFFS 1 // reg_0x4
`define REG_08_OFFS 2 // reg_0x8
`define REG_0C_OFFS 3 // reg_0xC
`define REG_10_OFFS 4 // reg_0x10
`define REG_14_OFFS 5 // reg_0x14
`define REG_18_OFFS 6 // reg_0x18
`define REG_1C_OFFS 7 // reg_0x1C
`define REG_20_OFFS 8 // reg_0x20
`define REG_28_OFFS 10 // reg_0x28
/*
local wire or register declarations
*/
reg [31:0] REG_00;
reg [31:0] REG_04;
reg [31:0] REG_08;
reg [7:0] sha_r_test_shdw;
reg [31:0] REG_0C;
wire [5:0] mvstop_shdw;
reg [31:0] REG_10;
reg [31:0] REG_14;
wire [31:0] sha_rw2_shdw;
reg [31:0] REG_18;
reg [31:0] REG_1C;
reg [31:0] REG_20;
reg [31:0] REG_28;
reg int_upd_rw;
reg int_upd_r;
wire wr_p;
wire rd_p;
reg int_trans_done;
wire [3:0] iaddr;
wire addr_overshoot;
wire trans_done_p;
reg rd_done_p;
reg wr_done_p;
reg fwd_txn;
wire [1:0] fwd_decode_vec;
wire [1:0] fwd_done_vec;
reg [31:0] mux_rd_data;
reg mux_rd_err;
/*
local wire and output assignments
*/
assign Cvbsdetect_par_o = REG_04[0];
assign mvstop_shdw = REG_0C[10:5];
assign mvstart_par_o = REG_0C[4:0];
assign sha_rw2_shdw = REG_14;
assign wd_16_test_par_o = REG_18[15:0];
assign wd_16_test2_par_o = REG_1C[7:0];
assign usr_rw_test_par_o = wr_data_i[14:11];
// clip address to decoded range
assign iaddr = addr_i[5:2];
assign addr_overshoot = |addr_i[13:6];
// write txn start pulse
assign wr_p = ~rd_wr_i & u4_sync_generic_i_trans_start_p;
// read txn start pulse
assign rd_p = rd_wr_i & u4_sync_generic_i_trans_start_p;
/*
generate txn done signals
*/
assign fwd_done_vec = {usr_r_test_trans_done_p_i, usr_rw_test_trans_done_p_i}; // ack for forwarded txns
assign trans_done_p = ((wr_done_p | rd_done_p) & ~fwd_txn) | ((fwd_done_vec != 0) & fwd_txn);
always @(posedge clk_f20 or negedge u5_sync_rst_i_int_rst_n) begin
if (~u5_sync_rst_i_int_rst_n) begin
int_trans_done <= 0;
wr_done_p <= 0;
rd_done_p <= 0;
end
else begin
wr_done_p <= wr_p;
rd_done_p <= rd_p;
if (trans_done_p)
int_trans_done <= ~int_trans_done;
end
end
assign trans_done_o = int_trans_done;
/*
write process
*/
always @(posedge clk_f20 or negedge u5_sync_rst_i_int_rst_n) begin
if (~u5_sync_rst_i_int_rst_n) begin
REG_0C[10:5] <= 'hc;
REG_0C[4:0] <= 'h7;
REG_14 <= 'h0;
REG_18[15:0] <= 'ha;
REG_1C[7:0] <= 'hff;
end
else begin
if (wr_p)
case (iaddr)
`REG_0C_OFFS: begin
REG_0C[10:5] <= wr_data_i[10:5];
REG_0C[4:0] <= wr_data_i[4:0];
end
`REG_14_OFFS: begin
REG_14 <= wr_data_i;
end
`REG_18_OFFS: begin
REG_18[15:0] <= wr_data_i[15:0];
end
`REG_1C_OFFS: begin
REG_1C[7:0] <= wr_data_i[7:0];
end
endcase
end
end
/*
write process for status registers
*/
always @(posedge clk_f20 or negedge u5_sync_rst_i_int_rst_n) begin
if (~u5_sync_rst_i_int_rst_n) begin
REG_04[0] <= 'h0;
end
else begin
if (Cvbsdetect_set_p_i)
REG_04[0] <= 1;
else if (wr_p && iaddr == `REG_04_OFFS)
REG_04[0] <= REG_04[0] & ~wr_data_i[0];
end
end
/*
txn forwarding process
*/
// decode addresses of USR registers and read/write
assign fwd_decode_vec = {(iaddr == `REG_08_OFFS) & rd_wr_i, (iaddr == `REG_10_OFFS)};
always @(posedge clk_f20 or negedge u5_sync_rst_i_int_rst_n) begin
if (~u5_sync_rst_i_int_rst_n) begin
fwd_txn <= 0;
usr_r_test_rd_p_o <= 0;
usr_rw_test_rd_p_o <= 0;
usr_rw_test_wr_p_o <= 0;
end
else begin
usr_r_test_rd_p_o <= 0;
usr_rw_test_rd_p_o <= 0;
usr_rw_test_wr_p_o <= 0;
if (u4_sync_generic_i_trans_start_p) begin
fwd_txn <= |fwd_decode_vec; // set flag for forwarded txn
usr_r_test_rd_p_o <= fwd_decode_vec[1] & rd_wr_i;
usr_rw_test_rd_p_o <= fwd_decode_vec[0] & rd_wr_i;
usr_rw_test_wr_p_o <= fwd_decode_vec[0] & ~rd_wr_i;
end
else if (trans_done_p)
fwd_txn <= 0; // reset flag for forwarded transaction
end
end
/*
shadowing for update signal 'upd_rw'
*/
// generate internal update signal
always @(posedge clk_f20 or negedge u5_sync_rst_i_int_rst_n) begin
if (~u5_sync_rst_i_int_rst_n)
int_upd_rw <= 1;
else
int_upd_rw <= (int_upd_rw_p & upd_rw_en_i) | upd_rw_force_i;
end
// shadow process
always @(posedge clk_f20) begin
if (int_upd_rw) begin
mvstop_par_o <= mvstop_shdw;
sha_rw2_par_o <= sha_rw2_shdw;
end
end
/*
shadowing for update signal 'upd_r'
*/
// generate internal update signal
always @(posedge clk_f20 or negedge u5_sync_rst_i_int_rst_n) begin
if (~u5_sync_rst_i_int_rst_n)
int_upd_r <= 1;
else
int_upd_r <= (int_upd_r_p & upd_r_en_i) | upd_r_force_i;
end
// shadow process
always @(posedge clk_f20) begin
if (int_upd_r) begin
sha_r_test_shdw <= sha_r_test_par_i;
end
end
/*
read logic and mux process
*/
assign rd_data_o = mux_rd_data;
assign rd_err_o = mux_rd_err | addr_overshoot;
always @(REG_04 or REG_0C or REG_18 or iaddr or mvstop_shdw or sha_r_test_shdw or sha_rw2_shdw or usr_r_test_par_i or usr_rw_test_par_i or ycdetect_par_i) begin
mux_rd_err <= 0;
mux_rd_data <= 0;
case (iaddr)
`REG_04_OFFS : begin
mux_rd_data[0] <= REG_04[0];
end
`REG_08_OFFS : begin
mux_rd_data[1] <= ycdetect_par_i;
mux_rd_data[2] <= usr_r_test_par_i;
mux_rd_data[10:3] <= sha_r_test_shdw;
end
`REG_0C_OFFS : begin
mux_rd_data[4:0] <= REG_0C[4:0];
mux_rd_data[10:5] <= mvstop_shdw;
end
`REG_10_OFFS : begin
mux_rd_data[14:11] <= usr_rw_test_par_i;
end
`REG_14_OFFS : begin
mux_rd_data <= sha_rw2_shdw;
end
`REG_18_OFFS : begin
mux_rd_data[15:0] <= REG_18[15:0];
end
default: begin
mux_rd_err <= 1; // no decode
end
endcase
end
/*
checking code
*/
`ifdef ASSERT_ON
property p_pos_pulse_check (sig); // check for positive pulse
@(posedge clk_f20) disable iff (~u5_sync_rst_i_int_rst_n)
sig |=> ~sig;
endproperty
assert property(p_pos_pulse_check(Cvbsdetect_set_p_i));
assert property(p_pos_pulse_check(usr_r_test_trans_done_p_i));
assert property(p_pos_pulse_check(usr_rw_test_trans_done_p_i));
p_fwd_done_expected: assert property
(
@(posedge clk_f20) disable iff (~u5_sync_rst_i_int_rst_n)
usr_r_test_trans_done_p_i || usr_rw_test_trans_done_p_i |-> fwd_txn
);
p_fwd_done_onehot: assert property
(
@(posedge clk_f20) disable iff (~u5_sync_rst_i_int_rst_n)
usr_r_test_trans_done_p_i || usr_rw_test_trans_done_p_i |-> onehot(fwd_done_vec)
);
p_fwd_done_only_when_fwd_txn: assert property
(
@(posedge clk_f20) disable iff (~u5_sync_rst_i_int_rst_n)
fwd_done_vec != 0 |-> fwd_txn
);
function onehot (input [1:0] vec); // not built-in to SV yet
integer i,j;
begin
j = 0;
for (i=0; i<2; i=i+1) j = j + vec[i] ? 1 : 0;
onehot = (j==1) ? 1 : 0;
end
endfunction
`endif
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for u4_sync_generic_i
sync_generic #(
.act(1),
.kind(2),
.rstact(0),
.rstval(0),
.sync(0)
) u4_sync_generic_i ( // Synchronizer for trans_done signal
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(u4_sync_generic_i_trans_start_p),
.rst_r(res_f20_n_i),
.rst_s(tie0_1),
.snd_i(trans_start)
);
// End of Generated Instance Port Map for u4_sync_generic_i
// Generated Instance Port Map for u5_sync_rst_i
sync_rst #(
.act(0),
.sync(0)
) u5_sync_rst_i ( // Reset synchronizer
.clk_r(clk_f20),
.rst_i(res_f20_n_i),
.rst_o(u5_sync_rst_i_int_rst_n)
);
// End of Generated Instance Port Map for u5_sync_rst_i
// Generated Instance Port Map for u6_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u6_sync_generic_i ( // Synchronizer for update-signal upd_rw
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(int_upd_rw_p),
.rst_r(res_f20_n_i),
.rst_s(tie0_1),
.snd_i(upd_rw_i)
);
// End of Generated Instance Port Map for u6_sync_generic_i
// Generated Instance Port Map for u7_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u7_sync_generic_i ( // Synchronizer for update-signal upd_r
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(int_upd_r_p),
.rst_r(res_f20_n_i),
.rst_s(tie0_1),
.snd_i(upd_r_i)
);
// End of Generated Instance Port Map for u7_sync_generic_i
endmodule
//
// End of Generated Module rtl of rs_cfg_fe1
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_2_V
`define SKY130_FD_SC_LS__O41A_2_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o41a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41a_2 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41a_2 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_2_V
|
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ecc_encoder_decoder_wrapper #
( parameter
CFG_LOCAL_DATA_WIDTH = 80,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_DWIDTH_RATIO = 2,
CFG_MEM_IF_DQ_WIDTH = 40,
CFG_MEM_IF_DQS_WIDTH = 5,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_MULTIPLES = 1,
CFG_ECC_ENC_REG = 0,
CFG_ECC_DEC_REG = 0,
CFG_ECC_RDATA_REG = 0,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_GEN_SBE = 1,
CFG_PORT_WIDTH_GEN_DBE = 1,
CFG_PORT_WIDTH_ENABLE_INTR = 1,
CFG_PORT_WIDTH_MASK_SBE_INTR = 1,
CFG_PORT_WIDTH_MASK_DBE_INTR = 1,
CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1,
CFG_PORT_WIDTH_CLR_INTR = 1,
STS_PORT_WIDTH_SBE_ERROR = 1,
STS_PORT_WIDTH_DBE_ERROR = 1,
STS_PORT_WIDTH_SBE_COUNT = 8,
STS_PORT_WIDTH_DBE_COUNT = 8,
STS_PORT_WIDTH_CORR_DROP_ERROR = 1,
STS_PORT_WIDTH_CORR_DROP_COUNT = 8
)
(
ctl_clk,
ctl_reset_n,
// MMR Interface
cfg_interface_width,
cfg_enable_ecc,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
// Wdata & Rdata Interface Inputs
wdatap_dm,
wdatap_data,
wdatap_rmw_partial_data,
wdatap_rmw_correct_data,
wdatap_rmw_partial,
wdatap_rmw_correct,
wdatap_ecc_code,
wdatap_ecc_code_overwrite,
rdatap_rcvd_addr,
rdatap_rcvd_cmd,
rdatap_rcvd_corr_dropped,
// AFI Interface Inputs
afi_rdata,
afi_rdata_valid,
// Wdata & Rdata Interface Outputs
ecc_rdata,
ecc_rdata_valid,
// AFI Inteface Outputs
ecc_dm,
ecc_wdata,
// ECC Error Information
ecc_sbe,
ecc_dbe,
ecc_code,
ecc_interrupt,
// MMR ECC Information
sts_sbe_error,
sts_dbe_error,
sts_sbe_count,
sts_dbe_count,
sts_err_addr,
sts_corr_dropped,
sts_corr_dropped_count,
sts_corr_dropped_addr
);
//--------------------------------------------------------------------------------------------------------
//
// Important Note:
//
// This block is coded with the following consideration in mind
// - Parameter
// - maximum LOCAL_DATA_WIDTH will be (40 * DWIDTH_RATIO)
// - maximum ECC_DATA_WIDTH will be (40 * DWIDTH_RATIO)
// - MMR configuration
// - ECC option disabled:
// - maximum DQ width is 40
// - maximum LOCAL_DATA width is (40 * DWIDTH_RATIO)
// - WDATAP_DATA and ECC_DATA size will match (no ECC code)
// - ECC option enabled:
// - maximum DQ width is 40
// - maximum LOCAL_DATA width is (32 * DWIDTH_RATIO)
// - WDATAP_DATA width will be (8 * DWIDTH_RATIO) lesser than ECC_DATA (ECC code)
//
// Block level diagram
// -----------------------------------
// Write Data Path (Per DRATE)
// -----------------------------------
// __________ ___________ ___________
// | | | | | |
// Local Write Data | Data | | | | |
// ---- 40 bits ---->| Mask |---- 32 bits ---->| Encoder |---- 40 bits ---->| ECC MUX |---- 40 bits ---->
// | | | | | | |
// | |__________| |___________| |___________|
// | ^
// |---------------------------------- 40 bits ---------------------------|
//
//
// -----------------------------------
// Read Data Path (Per DRATE)
// -----------------------------------
// __________ ___________ ___________
// | | | | | |
// AFI Read Data | Data | | | | |
// ---- 40 bits ---->| Mask |---- 40 bits ---->| Decoder |---- 32 bits ---->| ECC MUX |---- 40 bits ---->
// | | | | | | |
// | |__________| |___________| |___________|
// | ^
// |---------------------------------- 40 bits ---------------------------|
//
//--------------------------------------------------------------------------------------------------------
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_ECC_DATA_WIDTH = CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO;
localparam CFG_LOCAL_DM_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_ECC_DM_WIDTH = CFG_ECC_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_LOCAL_DATA_PER_WORD_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_LOCAL_DM_PER_WORD_WIDTH = CFG_LOCAL_DM_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_ECC_DATA_PER_WORD_WIDTH = CFG_ECC_DATA_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_ECC_DM_PER_WORD_WIDTH = CFG_ECC_DM_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_MMR_DRAM_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_LOCAL_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_DRAM_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2; // Minus 3 because byte enable will be divided by 4/8
localparam CFG_MMR_LOCAL_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2; // Minus 3 because byte enable will be divided by 4/8
// The following 2 parameters should match!
localparam CFG_ENCODER_DATA_WIDTH = CFG_ECC_DATA_PER_WORD_WIDTH; // supports only 24, 40 and 72
localparam CFG_DECODER_DATA_WIDTH = CFG_ECC_DATA_PER_WORD_WIDTH; // supports only 24, 40 and 72
input ctl_clk;
input ctl_reset_n;
// MMR Interface
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] cfg_gen_sbe;
input [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] cfg_gen_dbe;
input [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] cfg_enable_intr;
input [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] cfg_mask_sbe_intr;
input [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] cfg_mask_dbe_intr;
input [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] cfg_mask_corr_dropped_intr;
input [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] cfg_clr_intr;
// Wdata & Rdata Interface Inputs
input [CFG_LOCAL_DM_WIDTH - 1 : 0] wdatap_dm;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_data;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_partial_data;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_correct_data;
input wdatap_rmw_partial;
input wdatap_rmw_correct;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
input [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] rdatap_rcvd_addr;
input rdatap_rcvd_cmd;
input rdatap_rcvd_corr_dropped;
// AFI Interface Inputs
input [CFG_ECC_DATA_WIDTH - 1 : 0] afi_rdata;
input [CFG_DWIDTH_RATIO / 2 - 1 : 0] afi_rdata_valid;
// Wdata & Rdata Interface Outputs
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
output ecc_rdata_valid;
// AFI Inteface Outputs
output [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
output [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
// ECC Error Information
output [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
output [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
output ecc_interrupt;
// MMR ECC Information
output [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
output [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
output [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
output [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
output [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
output [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// Output registers
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
reg ecc_rdata_valid;
reg [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
reg [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
reg [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
reg [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
reg ecc_interrupt;
reg [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
reg [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
reg [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
reg [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
reg [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
reg [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
// Common
reg [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
reg [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_local_data_width;
reg [CFG_MMR_DRAM_DM_WIDTH - 1 : 0] cfg_dram_dm_width;
reg [CFG_MMR_LOCAL_DM_WIDTH - 1 : 0] cfg_local_dm_width;
// Input Logic
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_data;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_rmw_partial_data;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_rmw_correct_data;
reg int_encoder_input_rmw_partial;
reg int_encoder_input_rmw_correct;
reg wdatap_rmw_partial_r;
reg wdatap_rmw_correct_r;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg int_decoder_input_data_valid;
// Output Logic
reg [CFG_ECC_MULTIPLES - 1 : 0] int_sbe;
reg [CFG_ECC_MULTIPLES - 1 : 0] int_dbe;
reg [CFG_ECC_DM_WIDTH - 1 : 0] int_encoder_output_dm;
reg [CFG_ECC_DM_WIDTH - 1 : 0] int_encoder_output_dm_r;
wire [CFG_ECC_MULTIPLES - 1 : 0] int_decoder_output_data_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_encoder_output_data;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_encoder_output_data_r;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_decoder_output_data;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] int_ecc_code;
// ECC specific logic
reg [1 : 0] inject_data_error;
reg int_sbe_detected;
reg int_dbe_detected;
wire int_be_detected;
reg int_sbe_store;
reg int_dbe_store;
reg int_sbe_valid;
reg int_dbe_valid;
reg int_sbe_valid_r;
reg int_dbe_valid_r;
reg int_ecc_interrupt;
wire int_interruptable_error_detected;
reg [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] int_sbe_error;
reg [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] int_dbe_error;
reg [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] int_sbe_count;
reg [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] int_dbe_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_err_addr ;
reg [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] int_corr_dropped;
reg [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] int_corr_dropped_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_corr_dropped_addr ;
reg int_corr_dropped_detected;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// DRAM and local data width
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_data_width <= 0;
end
else
begin
cfg_dram_data_width <= cfg_interface_width;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_local_data_width <= 0;
end
else
begin
// Important note, if we set memory interface width (DQ width) to 8 and enable_ecc to 1,
// this will result in local data width of 0, this case is not supported
// this must be checked with assertion so that this case will not happen in regression
if (cfg_enable_ecc)
begin
cfg_local_data_width <= cfg_interface_width - CFG_ECC_CODE_WIDTH;
end
else
begin
cfg_local_data_width <= cfg_interface_width;
end
end
end
//----------------------------------------------------------------------------------------------------
// DRAM and local be width
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_dm_width <= 0;
end
else
begin
cfg_dram_dm_width <= cfg_dram_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_local_dm_width <= 0;
end
else
begin
cfg_local_dm_width <= cfg_local_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_rmw_partial_r <= 1'b0;
wdatap_rmw_correct_r <= 1'b0;
end
else
begin
wdatap_rmw_partial_r <= wdatap_rmw_partial;
wdatap_rmw_correct_r <= wdatap_rmw_correct;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_encoder_output_data_r <= 0;
int_encoder_output_dm_r <= 0;
end
else
begin
int_encoder_output_data_r <= int_encoder_output_data;
int_encoder_output_dm_r <= int_encoder_output_dm;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [ENC] Common
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Input Logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Write data & byte enable from wdata_path
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
int_encoder_input_data = wdatap_data;
int_encoder_input_rmw_partial_data = wdatap_rmw_partial_data;
int_encoder_input_rmw_correct_data = wdatap_rmw_correct_data;
if (CFG_ECC_ENC_REG)
begin
int_encoder_input_rmw_partial = wdatap_rmw_partial_r;
int_encoder_input_rmw_correct = wdatap_rmw_correct_r;
end
else
begin
int_encoder_input_rmw_partial = wdatap_rmw_partial;
int_encoder_input_rmw_correct = wdatap_rmw_correct;
end
end
generate
genvar i_drate;
for (i_drate = 0;i_drate < CFG_ECC_MULTIPLES;i_drate = i_drate + 1)
begin : encoder_input_dm_mux_per_dm_drate
wire [CFG_LOCAL_DM_PER_WORD_WIDTH-1:0] int_encoder_input_dm = wdatap_dm [(i_drate + 1) * CFG_LOCAL_DM_PER_WORD_WIDTH - 1 : i_drate * CFG_LOCAL_DM_PER_WORD_WIDTH];
wire int_encoder_input_dm_all_zeros = ~(|int_encoder_input_dm);
always @ (*)
begin
if (cfg_enable_ecc)
begin
if (int_encoder_input_dm_all_zeros)
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b0}},int_encoder_input_dm};
end
else
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b1}},int_encoder_input_dm};
end
end
else
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b0}},int_encoder_input_dm};
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Read data & read data valid from AFI
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
int_decoder_input_data = afi_rdata;
end
always @ (*)
begin
int_decoder_input_data_valid = afi_rdata_valid [0];
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Input Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Output Logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Write data & byte enable to AFI interface
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
ecc_wdata = int_encoder_output_data;
end
always @ (*)
begin
if (CFG_ECC_ENC_REG)
begin
ecc_dm = int_encoder_output_dm_r;
end
else
begin
ecc_dm = int_encoder_output_dm;
end
end
//----------------------------------------------------------------------------------------------------
// Read data to rdata_path
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
ecc_rdata = int_decoder_output_data;
end
always @ (*)
begin
ecc_rdata_valid = |int_decoder_output_data_valid;
end
//----------------------------------------------------------------------------------------------------
// ECC specific logic
//----------------------------------------------------------------------------------------------------
// Single bit error
always @ (*)
begin
if (cfg_enable_ecc)
ecc_sbe = int_sbe;
else
ecc_sbe = 0;
end
// Double bit error
always @ (*)
begin
if (cfg_enable_ecc)
ecc_dbe = int_dbe;
else
ecc_dbe = 0;
end
// ECC code
always @ (*)
begin
if (cfg_enable_ecc)
ecc_code = int_ecc_code;
else
ecc_code = 0;
end
// Interrupt signal
always @ (*)
begin
ecc_interrupt = int_ecc_interrupt;
end
//----------------------------------------------------------------------------------------------------
// MMR ECC specific logic
//----------------------------------------------------------------------------------------------------
// Single bit error
always @ (*)
begin
sts_sbe_error = int_sbe_error;
end
// Double bit error
always @ (*)
begin
sts_dbe_error = int_dbe_error;
end
// Single bit error count
always @ (*)
begin
sts_sbe_count = int_sbe_count;
end
// Double bit error count
always @ (*)
begin
sts_dbe_count = int_dbe_count;
end
// Error address
always @ (*)
begin
sts_err_addr = int_err_addr;
end
// Correctable Error dropped
always @ (*)
begin
sts_corr_dropped = int_corr_dropped;
end
// Single bit error count
always @ (*)
begin
sts_corr_dropped_count = int_corr_dropped_count;
end
// Correctable Error dropped address
always @ (*)
begin
sts_corr_dropped_addr = int_corr_dropped_addr;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Output Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Encoder / Decoder Instantiation
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Encoder
//----------------------------------------------------------------------------------------------------
generate
genvar m_drate;
for (m_drate = 0;m_drate < CFG_ECC_MULTIPLES;m_drate = m_drate + 1)
begin : encoder_inst_per_drate
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_rmw_partial_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_rmw_partial_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_rmw_correct_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_rmw_correct_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code = wdatap_ecc_code [(m_drate + 1) * CFG_ECC_CODE_WIDTH - 1 : m_drate * CFG_ECC_CODE_WIDTH];
wire input_ecc_code_overwrite = wdatap_ecc_code_overwrite [m_drate];
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_data;
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_rmw_partial_data;
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_rmw_correct_data;
always @ (*)
begin
if (int_encoder_input_rmw_partial)
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_rmw_partial_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_rmw_partial_data [1 : 0] ^ inject_data_error [1 : 0])};
end
else if (int_encoder_input_rmw_correct)
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_rmw_correct_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_rmw_correct_data [1 : 0] ^ inject_data_error [1 : 0])};
end
else
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_data [1 : 0] ^ inject_data_error [1 : 0])};
end
end
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (1'b0 ), // ECC code overwrite feature is only needed during RMW correct phase
.output_data (output_data )
);
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
rmw_partial_encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_rmw_partial_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (1'b0 ), // ECC code overwrite feature is only needed during RMW correct phase
.output_data (output_rmw_partial_data )
);
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
rmw_correct_encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_rmw_correct_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (input_ecc_code_overwrite ),
.output_data (output_rmw_correct_data )
);
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Decoder
//----------------------------------------------------------------------------------------------------
generate
genvar n_drate;
for (n_drate = 0;n_drate < CFG_ECC_MULTIPLES;n_drate = n_drate + 1)
begin : decoder_inst_per_drate
wire err_corrected;
wire err_detected;
wire err_fatal;
wire err_sbe;
wire [CFG_DECODER_DATA_WIDTH - 1 : 0] input_data = {{CFG_DECODER_DATA_WIDTH - CFG_ECC_DATA_PER_WORD_WIDTH{1'b0}}, int_decoder_input_data [(n_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : n_drate * CFG_ECC_DATA_PER_WORD_WIDTH]};
wire input_data_valid = int_decoder_input_data_valid;
wire [CFG_DECODER_DATA_WIDTH - 1 : 0] output_data;
wire output_data_valid;
wire [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
assign int_decoder_output_data [(n_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : n_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH] = output_data [CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : 0];
assign int_ecc_code [(n_drate + 1) * CFG_ECC_CODE_WIDTH - 1 : n_drate * CFG_ECC_CODE_WIDTH ] = output_ecc_code;
assign int_decoder_output_data_valid [n_drate] = output_data_valid;
alt_mem_ddrx_ecc_decoder #
(
.CFG_DATA_WIDTH (CFG_DECODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_DEC_REG (CFG_ECC_DEC_REG ),
.CFG_ECC_RDATA_REG (CFG_ECC_RDATA_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
decoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_data ),
.input_data_valid (input_data_valid ),
.output_data (output_data ),
.output_data_valid (output_data_valid ),
.output_ecc_code (output_ecc_code ),
.err_corrected (err_corrected ),
.err_detected (err_detected ),
.err_fatal (err_fatal ),
.err_sbe (err_sbe )
);
// Error detection
always @ (*)
begin
if (err_detected || err_sbe)
begin
if (err_corrected || err_sbe)
begin
int_sbe [n_drate] = 1'b1;
int_dbe [n_drate] = 1'b0;
end
else if (err_fatal)
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b1;
end
else
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b0;
end
end
else
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b0;
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Encoder / Decoder Instantiation
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] ECC Specific Logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Common Logic
//----------------------------------------------------------------------------------------------------
// Below information valid on same clock, when rdatap_rcvd_cmd is asserted (at end of every dram command)
// - int_sbe_detected
// - int_dbe_detected
// - int_be_detected
// - int_corr_dropped_detected
// - rdatap_rcvd_addr
//
// see SPR:362993
always @ (*)
begin
int_sbe_valid = |int_sbe & ecc_rdata_valid;
int_dbe_valid = |int_dbe & ecc_rdata_valid;
int_sbe_detected = ( int_sbe_store | int_sbe_valid_r ) & rdatap_rcvd_cmd;
int_dbe_detected = ( int_dbe_store | int_dbe_valid_r ) & rdatap_rcvd_cmd;
int_corr_dropped_detected = rdatap_rcvd_corr_dropped;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_sbe_valid_r <= 0;
int_dbe_valid_r <= 0;
int_sbe_store <= 0;
int_dbe_store <= 0;
end
else
begin
int_sbe_valid_r <= int_sbe_valid;
int_dbe_valid_r <= int_dbe_valid;
int_sbe_store <= (int_sbe_store | int_sbe_valid_r) & ~rdatap_rcvd_cmd;
int_dbe_store <= (int_dbe_store | int_dbe_valid_r) & ~rdatap_rcvd_cmd;
end
end
//----------------------------------------------------------------------------------------------------
// Error Innjection Logic
//----------------------------------------------------------------------------------------------------
// Data error injection, this will cause output data to be injected with single/double bit error
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
inject_data_error <= 0;
end
else
begin
// Put DBE 1st so that when user sets both gen_sbe and gen_dbe, DBE will have higher priority
if (cfg_gen_dbe)
inject_data_error <= 2'b11;
else if (cfg_gen_sbe)
inject_data_error <= 2'b01;
else
inject_data_error <= 2'b00;
end
end
//----------------------------------------------------------------------------------------------------
// Single bit error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_sbe_error <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_sbe_detected)
int_sbe_error <= 1'b1;
else if (cfg_clr_intr)
int_sbe_error <= 1'b0;
end
else
begin
int_sbe_error <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// Single bit error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_sbe_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_sbe_detected)
int_sbe_count <= 1;
else
int_sbe_count <= 0;
else if (int_sbe_detected)
int_sbe_count <= int_sbe_count + 1'b1;
end
else
begin
int_sbe_count <= {STS_PORT_WIDTH_SBE_COUNT{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Double bit error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dbe_error <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_dbe_detected)
int_dbe_error <= 1'b1;
else if (cfg_clr_intr)
int_dbe_error <= 1'b0;
end
else
begin
int_dbe_error <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// Double bit error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dbe_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_dbe_detected)
int_dbe_count <= 1;
else
int_dbe_count <= 0;
else if (int_dbe_detected)
int_dbe_count <= int_dbe_count + 1'b1;
end
else
begin
int_dbe_count <= {STS_PORT_WIDTH_DBE_COUNT{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Error address
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_err_addr <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_be_detected)
int_err_addr <= rdatap_rcvd_addr;
else if (cfg_clr_intr)
int_err_addr <= 0;
end
else
begin
int_err_addr <= {CFG_LOCAL_ADDR_WIDTH{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Dropped Correctable Error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_corr_dropped_detected)
int_corr_dropped <= 1'b1;
else if (cfg_clr_intr)
int_corr_dropped <= 1'b0;
end
else
begin
int_corr_dropped <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// Dropped Correctable Error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_corr_dropped_detected)
int_corr_dropped_count <= 1;
else
int_corr_dropped_count <= 0;
else if (int_corr_dropped_detected)
int_corr_dropped_count <= int_corr_dropped_count + 1'b1;
end
else
begin
int_corr_dropped_count <= {STS_PORT_WIDTH_CORR_DROP_COUNT{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Dropped Correctable Error address
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped_addr <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_corr_dropped_detected)
int_corr_dropped_addr <= rdatap_rcvd_addr;
else if (cfg_clr_intr)
int_corr_dropped_addr <= 0;
end
else
begin
int_corr_dropped_addr <= {CFG_LOCAL_ADDR_WIDTH{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Interrupt logic
//----------------------------------------------------------------------------------------------------
assign int_interruptable_error_detected = (int_sbe_detected & ~cfg_mask_sbe_intr) | (int_dbe_detected & ~cfg_mask_dbe_intr) | (int_corr_dropped_detected & ~cfg_mask_corr_dropped_intr);
assign int_be_detected = int_sbe_detected | int_dbe_detected;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_interrupt <= 1'b0;
end
else
begin
if (cfg_enable_ecc && cfg_enable_intr)
begin
if (int_interruptable_error_detected)
int_ecc_interrupt <= 1'b1;
else if (cfg_clr_intr)
int_ecc_interrupt <= 1'b0;
end
else
begin
int_ecc_interrupt <= 1'b0;
end
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] ECC Specific Logic
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__HA_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__HA_PP_BLACKBOX_V
/**
* ha: Half adder.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__HA_PP_BLACKBOX_V
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Stratix IV" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 11.0SP1 cbx_altiobuf_out 2011:07:03:21:10:33:SJ cbx_mgl 2011:07:03:21:11:41:SJ cbx_stratixiii 2011:07:03:21:10:33:SJ cbx_stratixv 2011:07:03:21:10:33:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = stratixiv_io_obuf 2 stratixiv_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module ddr3_s4_uniphy_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] oe_b;
wire [0:0] oe_w;
stratixiv_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(oe_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({14{1'b0}}),
.seriesterminationcontrol({14{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "stratixiv_io_obuf";
stratixiv_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(oe_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({14{1'b0}}),
.seriesterminationcontrol({14{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.shift_series_termination_control = "false",
obufa_0.lpm_type = "stratixiv_io_obuf";
stratixiv_pseudo_diff_out pseudo_diffa_0
(
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]));
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_b = 1'b1,
oe_w = 1'b1;
endmodule //ddr3_s4_uniphy_p0_clock_pair_generator
//VALID FILE
|
module fpalu(
input [0:39] t,
input [0:39] c,
input faa,
input fab,
input fra,
input frb,
input p_16,
input p_32,
input p_40,
output fp0_,
output fp16_,
output p32_,
output [0:39] sum
);
wor __NC;
wire g0a, g1a, g2a, g3a;
wire p0a, p1a, p2a, p3a;
alu181 M52(
.a(t[0:3]),
.b(c[0:3]),
.m(1'b0),
.c_(p4_),
.s({faa, fab, fab, faa}),
.f(sum[0:3]),
.g(g3a),
.p(p3a),
.co_(fp0_),
.eq(__NC)
);
alu181 M53(
.a(t[4:7]),
.b(c[4:7]),
.m(1'b0),
.c_(p8_),
.s({faa, fab, fab, faa}),
.f(sum[4:7]),
.g(g2a),
.p(p2a),
.co_(__NC),
.eq(__NC)
);
wire p12_, p8_, p4_;
carry182 M42(
.c_(~p_16),
.g({g3a, g2a, g1a, g0a}),
.p({p3a, p2a, p1a, p0a}),
.c1_(p12_),
.c2_(p8_),
.c3_(p4_),
.op(__NC),
.og(__NC)
);
alu181 M54(
.a(t[8:11]),
.b(c[8:11]),
.m(1'b0),
.c_(p12_),
.s({faa, fab, fab, faa}),
.f(sum[8:11]),
.g(g1a),
.p(p1a),
.co_(__NC),
.eq(__NC)
);
alu181 M55(
.a(t[12:15]),
.b(c[12:15]),
.m(1'b0),
.c_(~p_16),
.s({faa, fab, fab, faa}),
.f(sum[12:15]),
.g(g0a),
.p(p0a),
.co_(__NC),
.eq(__NC)
);
alu181 M56(
.a(t[16:19]),
.b(c[16:19]),
.m(1'b0),
.c_(p21_),
.s({fra, frb, frb, fra}),
.f(sum[16:19]),
.g(g3b),
.p(p3b),
.co_(fp16_),
.eq(__NC)
);
alu181 M57(
.a(t[20:23]),
.b(c[20:23]),
.m(1'b0),
.c_(p24_),
.s({fra, frb, frb, fra}),
.f(sum[20:23]),
.g(g2b),
.p(p2b),
.co_(__NC),
.eq(__NC)
);
wire p21_, p24_, p28_;
wire g3b, g2b, g1b, g0b;
wire p3b, p2b, p1b, p0b;
carry182 M47(
.c_(~p_32),
.g({g3b, g2b, g1b, g0b}),
.p({p3b, p2b, p1b, p0b}),
.c1_(p28_),
.c2_(p24_),
.c3_(p21_),
.op(__NC),
.og(__NC)
);
alu181 M58(
.a(t[24:27]),
.b(c[24:27]),
.m(1'b0),
.c_(p28_),
.s({fra, frb, frb, fra}),
.f(sum[24:27]),
.g(g1b),
.p(p1b),
.co_(__NC),
.eq(__NC)
);
alu181 M59(
.a(t[28:31]),
.b(c[28:31]),
.m(1'b0),
.c_(~p_32),
.s({fra, frb, frb, fra}),
.f(sum[28:31]),
.g(g0b),
.p(p0b),
.co_(__NC),
.eq(__NC)
);
wire p36_;
alu181 M60(
.a(t[32:35]),
.b(c[32:35]),
.m(1'b0),
.c_(p36_),
.s({fra, frb, frb, fra}),
.f(sum[32:35]),
.g(__NC),
.p(__NC),
.co_(p32_),
.eq(__NC)
);
alu181 M61(
.a(t[36:39]),
.b(c[36:39]),
.m(1'b0),
.c_(~p_40),
.s({fra, frb, frb, fra}),
.f(sum[36:39]),
.g(__NC),
.p(__NC),
.co_(p36_),
.eq(__NC)
);
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
`include "defines.v"
module data_ram(
input wire clk,
input wire ce,
input wire we,
input wire[`DataAddrBus] addr,
input wire[3:0] sel,
input wire[`DataBus] data_i,
output reg[`DataBus] data_o,
output wire[`DataBus] check,
input wire[2:0] direction,
output wire signal,
output reg[15:0] point,
input wire[7:0] AppleX,
input wire[7:0] AppleY,
inout wire[1:0] gamestatus,
output [7:0] snake
);
reg[`ByteWidth] data_mem0[0:`DataMemNum-1];
reg[`ByteWidth] data_mem1[0:`DataMemNum-1];
reg[`ByteWidth] data_mem2[0:`DataMemNum-1];
reg[`ByteWidth] data_mem3[0:`DataMemNum-1];
always @ (posedge clk) begin
if (ce == `ChipDisable) begin
//data_o <= ZeroWord;
end else if(we == `WriteEnable) begin
if(addr[`DataMemNumLog2+1:2] == 0) begin
data_mem3[0] <= 8'b0;
data_mem2[0] <= 8'b0;
data_mem1[0] <= 8'b0;
data_mem0[0] <= direction;
end
else if(addr[`DataMemNumLog2+1:2] == 22) begin
data_mem3[22] <= 8'b0;
data_mem2[22] <= 8'b0;
data_mem1[22] <= 8'b0;
data_mem0[22] <= AppleX;
end
else if(addr[`DataMemNumLog2+1:2] == 23) begin
data_mem3[23] <= 8'b0;
data_mem2[23] <= 8'b0;
data_mem1[23] <= 8'b0;
data_mem0[23] <= AppleY;
end
else begin
if (sel[3] == 1'b1) begin
data_mem3[addr[`DataMemNumLog2+1:2]] <= data_i[31:24];
end
if (sel[2] == 1'b1) begin
data_mem2[addr[`DataMemNumLog2+1:2]] <= data_i[23:16];
end
if (sel[1] == 1'b1) begin
data_mem1[addr[`DataMemNumLog2+1:2]] <= data_i[15:8];
end
if (sel[0] == 1'b1) begin
data_mem0[addr[`DataMemNumLog2+1:2]] <= data_i[7:0];
end
end
end
end
always @ (*) begin
if (ce == `ChipDisable) begin
data_o <= `ZeroWord;
end else if(we == `WriteDisable) begin
data_o <= {data_mem3[addr[`DataMemNumLog2+1:2]],
data_mem2[addr[`DataMemNumLog2+1:2]],
data_mem1[addr[`DataMemNumLog2+1:2]],
data_mem0[addr[`DataMemNumLog2+1:2]]};
point <= {data_mem1[24], data_mem0[24]} - 16'd3;
end else begin
data_o <= `ZeroWord;
end
end
assign snake = data_mem0[28];
assign gamestatus = 2'b01;
assign signal = (data_mem0[25] == 0) ? 0 : 1;
assign check = {data_mem3[0], data_mem2[0], data_mem1[0], data_mem0[0]};
endmodule |
module umult8(reg_A, reg_B, result);
// INPUTS
input [0:7] reg_A, reg_B;
// OUTPUTS
output [0:15] result;
// REGISTERS
reg [0:15] p8a_0;
reg [0:15] p8b_0;
reg [0:15] pt;
reg [0:15] result;
// INTEGERS (contols for loops)
integer i;
always @ (reg_A or reg_B)
begin
// reg_B
// x reg_A
// -------
// result
p8a_0=16'b0;
p8b_0=16'b0;
pt=16'b0;
// extend operand B
p8b_0={{8{1'b0}},reg_B[0:7]};
// extend operand A
p8a_0={{8{1'b0}},reg_A[0:7]};
// compute sum due to partial products
/*
// not using for loop
pt=pt+(p8a_0[15]?(p8b_0):16'b0);
pt=pt+(p8a_0[14]?(p8b_0<<8'd1):16'b0);
pt=pt+(p8a_0[13]?(p8b_0<<8'd2):16'b0);
pt=pt+(p8a_0[12]?(p8b_0<<8'd3):16'b0);
pt=pt+(p8a_0[11]?(p8b_0<<8'd4):16'b0);
pt=pt+(p8a_0[10]?(p8b_0<<8'd5):16'b0);
pt=pt+(p8a_0[9]?(p8b_0<<8'd6):16'b0);
pt=pt+(p8a_0[8]?(p8b_0<<8'd7):16'b0);
*/
// same computation as above, but using for loop
for (i=15; i>7; i=i-1)
begin
pt=pt+(p8a_0[i]?(p8b_0<<(8'd15-i)):16'b0);
end
// store sum as result
result<=pt;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_TB_V
`define SKY130_FD_SC_LS__O2BB2A_TB_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2bb2a.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_ls__o2bb2a dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_TB_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_4_data_stream_2_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_4_data_stream_2_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_4_data_stream_2_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_4_data_stream_2_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9434_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
adc_pn_type);
// adc interface
input adc_clk;
input [47:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input adc_pn_type;
// internal registers
reg [47:0] adc_pn_data = 'd0;
reg [ 6:0] adc_pn_oos_count = 'd0;
reg adc_pn_oos = 'd0;
reg adc_pn_err = 'd0;
// internal signals
wire [47:0] adc_pn_data_in_s;
wire adc_pn_match_d_s;
wire adc_pn_match_z_s;
wire adc_pn_match_s;
wire [47:0] adc_pn_data_s;
wire adc_pn_update_s;
wire adc_pn_err_s;
// PN23 function
function [47:0] pn23;
input [47:0] din;
reg [47:0] dout;
begin
dout[47] = din[22] ^ din[17];
dout[46] = din[21] ^ din[16];
dout[45] = din[20] ^ din[15];
dout[44] = din[19] ^ din[14];
dout[43] = din[18] ^ din[13];
dout[42] = din[17] ^ din[12];
dout[41] = din[16] ^ din[11];
dout[40] = din[15] ^ din[10];
dout[39] = din[14] ^ din[ 9];
dout[38] = din[13] ^ din[ 8];
dout[37] = din[12] ^ din[ 7];
dout[36] = din[11] ^ din[ 6];
dout[35] = din[10] ^ din[ 5];
dout[34] = din[ 9] ^ din[ 4];
dout[33] = din[ 8] ^ din[ 3];
dout[32] = din[ 7] ^ din[ 2];
dout[31] = din[ 6] ^ din[ 1];
dout[30] = din[ 5] ^ din[ 0];
dout[29] = din[ 4] ^ din[22] ^ din[17];
dout[28] = din[ 3] ^ din[21] ^ din[16];
dout[27] = din[ 2] ^ din[20] ^ din[15];
dout[26] = din[ 1] ^ din[19] ^ din[14];
dout[25] = din[ 0] ^ din[18] ^ din[13];
dout[24] = din[22] ^ din[12];
dout[23] = din[21] ^ din[11];
dout[22] = din[20] ^ din[10];
dout[21] = din[19] ^ din[ 9];
dout[20] = din[18] ^ din[ 8];
dout[19] = din[17] ^ din[ 7];
dout[18] = din[16] ^ din[ 6];
dout[17] = din[15] ^ din[ 5];
dout[16] = din[14] ^ din[ 4];
dout[15] = din[13] ^ din[ 3];
dout[14] = din[12] ^ din[ 2];
dout[13] = din[11] ^ din[ 1];
dout[12] = din[10] ^ din[ 0];
dout[11] = din[ 9] ^ din[22] ^ din[17];
dout[10] = din[ 8] ^ din[21] ^ din[16];
dout[ 9] = din[ 7] ^ din[20] ^ din[15];
dout[ 8] = din[ 6] ^ din[19] ^ din[14];
dout[ 7] = din[ 5] ^ din[18] ^ din[13];
dout[ 6] = din[ 4] ^ din[17] ^ din[12];
dout[ 5] = din[ 3] ^ din[16] ^ din[11];
dout[ 4] = din[ 2] ^ din[15] ^ din[10];
dout[ 3] = din[ 1] ^ din[14] ^ din[ 9];
dout[ 2] = din[ 0] ^ din[13] ^ din[ 8];
dout[ 1] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
dout[ 0] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
pn23 = dout;
end
endfunction
// PN9 function
function [47:0] pn9;
input [47:0] din;
reg [47:0] dout;
begin
dout[47] = din[ 8] ^ din[ 4];
dout[46] = din[ 7] ^ din[ 3];
dout[45] = din[ 6] ^ din[ 2];
dout[44] = din[ 5] ^ din[ 1];
dout[43] = din[ 4] ^ din[ 0];
dout[42] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[41] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[40] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[39] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[38] = din[ 8] ^ din[ 0];
dout[37] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[36] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[35] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[34] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[33] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[32] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[31] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[30] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[29] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[28] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[27] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[26] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[25] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[24] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[23] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[22] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[21] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[20] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[19] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[18] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[17] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[16] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
dout[15] = din[ 3] ^ din[ 5] ^ din[ 6] ^ din[ 2];
dout[14] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[13] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 0];
dout[12] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[11] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3];
dout[10] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[ 9] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[ 8] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 1] ^ din[ 3] ^ din[ 0];
dout[ 7] = din[ 6] ^ din[ 7] ^ din[ 0] ^ din[ 2] ^ din[ 8];
dout[ 6] = din[ 5] ^ din[ 6] ^ din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 7];
dout[ 5] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 6];
dout[ 4] = din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 5];
dout[ 3] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 1];
dout[ 2] = din[ 1] ^ din[ 4] ^ din[ 3] ^ din[ 6] ^ din[ 0];
dout[ 1] = din[ 0] ^ din[ 3] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4];
dout[ 0] = din[ 8] ^ din[ 2] ^ din[ 1] ^ din[ 7] ^ din[ 3];
pn9 = dout;
end
endfunction
// pn sequence checking algorithm is commonly used in most applications.
// if oos is asserted (pn is out of sync):
// the next sequence is generated from the incoming data.
// if 16 sequences match consecutively, oos is cleared (de-asserted).
// if oos is de-asserted (pn is in sync)
// the next sequence is generated from the current sequence.
// if 64 sequences mismatch consecutively, oos is set (asserted).
// if oos is de-asserted, any spurious mismatches sets the error register.
// ideally, processor should make sure both oos == 0x0 and err == 0x0.
assign adc_pn_data_in_s = {adc_data[11:0], adc_data[23:12], adc_data[35:24], adc_data[47:36]};
assign adc_pn_match_d_s = (adc_pn_data_in_s == adc_pn_data) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_pn_data_in_s == 48'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_pn_match_d_s & adc_pn_match_z_s;
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in_s : adc_pn_data;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
// pn running sequence
always @(posedge adc_clk) begin
if (adc_pn_type == 1'b0) begin
adc_pn_data <= pn9(adc_pn_data_s);
end else begin
adc_pn_data <= pn23(adc_pn_data_s);
end
end
// pn oos and counters (64 to clear and set).
always @(posedge adc_clk) begin
if (adc_pn_update_s == 1'b1) begin
if (adc_pn_oos_count >= 16) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= ~adc_pn_oos;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
adc_pn_oos <= adc_pn_oos;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= adc_pn_oos;
end
adc_pn_err <= adc_pn_err_s;
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [0 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [0 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [0 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [0 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WID" *)
output wire [0 : 0] m_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [3 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(1),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Audio Processing Unit.
***************************************************************************************************/
module apu
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire [ 3:0] mute_in, // disable specific audio channels
input wire [15:0] a_in, // addr input bus
input wire [ 7:0] d_in, // data input bus
input wire r_nw_in, // read/write select
output wire audio_out, // pwm audio output
output wire [ 5:0] dac_audio_out,
output wire [ 7:0] d_out // data output bus
);
localparam [15:0] PULSE0_CHANNEL_CNTL_MMR_ADDR = 16'h4000;
localparam [15:0] PULSE1_CHANNEL_CNTL_MMR_ADDR = 16'h4004;
localparam [15:0] TRIANGLE_CHANNEL_CNTL_MMR_ADDR = 16'h4008;
localparam [15:0] NOISE_CHANNEL_CNTL_MMR_ADDR = 16'h400C;
localparam [15:0] STATUS_MMR_ADDR = 16'h4015;
localparam [15:0] FRAME_COUNTER_CNTL_MMR_ADDR = 16'h4017;
// CPU cycle pulse. Ideally this would be generated in rp2a03 and shared by the apu and cpu.
reg [5:0] q_clk_cnt;
wire [5:0] d_clk_cnt;
wire cpu_cycle_pulse;
wire apu_cycle_pulse;
wire e_pulse;
wire l_pulse;
wire f_pulse;
reg q_pulse0_en;
wire d_pulse0_en;
reg q_pulse1_en;
wire d_pulse1_en;
reg q_triangle_en;
wire d_triangle_en;
reg q_noise_en;
wire d_noise_en;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_clk_cnt <= 6'h00;
q_pulse0_en <= 1'b0;
q_pulse1_en <= 1'b0;
q_triangle_en <= 1'b0;
q_noise_en <= 1'b0;
end
else
begin
q_clk_cnt <= d_clk_cnt;
q_pulse0_en <= d_pulse0_en;
q_pulse1_en <= d_pulse1_en;
q_triangle_en <= d_triangle_en;
q_noise_en <= d_noise_en;
end
end
assign d_clk_cnt = (q_clk_cnt == 6'h37) ? 6'h00 : q_clk_cnt + 6'h01;
assign d_pulse0_en = (~r_nw_in && (a_in == STATUS_MMR_ADDR)) ? d_in[0] : q_pulse0_en;
assign d_pulse1_en = (~r_nw_in && (a_in == STATUS_MMR_ADDR)) ? d_in[1] : q_pulse1_en;
assign d_triangle_en = (~r_nw_in && (a_in == STATUS_MMR_ADDR)) ? d_in[2] : q_triangle_en;
assign d_noise_en = (~r_nw_in && (a_in == STATUS_MMR_ADDR)) ? d_in[3] : q_noise_en;
assign cpu_cycle_pulse = (q_clk_cnt == 6'h00);
apu_div #(.PERIOD_BITS(1)) apu_pulse_gen(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(cpu_cycle_pulse),
.reload_in(1'b0),
.period_in(1'b1),
.pulse_out(apu_cycle_pulse)
);
//
// Frame counter.
//
wire frame_counter_mode_wr;
apu_frame_counter apu_frame_counter_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.cpu_cycle_pulse_in(cpu_cycle_pulse),
.apu_cycle_pulse_in(apu_cycle_pulse),
.mode_in(d_in[7:6]),
.mode_wr_in(frame_counter_mode_wr),
.e_pulse_out(e_pulse),
.l_pulse_out(l_pulse),
.f_pulse_out(f_pulse)
);
assign frame_counter_mode_wr = ~r_nw_in && (a_in == FRAME_COUNTER_CNTL_MMR_ADDR);
//
// Pulse 0 channel.
//
wire [3:0] pulse0_out;
wire pulse0_active;
wire pulse0_wr;
apu_pulse #(.CHANNEL(0)) apu_pulse0_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(q_pulse0_en),
.cpu_cycle_pulse_in(cpu_cycle_pulse),
.lc_pulse_in(l_pulse),
.eg_pulse_in(e_pulse),
.a_in(a_in[1:0]),
.d_in(d_in),
.wr_in(pulse0_wr),
.pulse_out(pulse0_out),
.active_out(pulse0_active)
);
assign pulse0_wr = ~r_nw_in && (a_in[15:2] == PULSE0_CHANNEL_CNTL_MMR_ADDR[15:2]);
//
// Pulse 1 channel.
//
wire [3:0] pulse1_out;
wire pulse1_active;
wire pulse1_wr;
apu_pulse #(.CHANNEL(1)) apu_pulse1_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(q_pulse1_en),
.cpu_cycle_pulse_in(cpu_cycle_pulse),
.lc_pulse_in(l_pulse),
.eg_pulse_in(e_pulse),
.a_in(a_in[1:0]),
.d_in(d_in),
.wr_in(pulse1_wr),
.pulse_out(pulse1_out),
.active_out(pulse1_active)
);
assign pulse1_wr = ~r_nw_in && (a_in[15:2] == PULSE1_CHANNEL_CNTL_MMR_ADDR[15:2]);
//
// Triangle channel.
//
wire [3:0] triangle_out;
wire triangle_active;
wire triangle_wr;
apu_triangle apu_triangle_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(q_triangle_en),
.cpu_cycle_pulse_in(cpu_cycle_pulse),
.lc_pulse_in(l_pulse),
.eg_pulse_in(e_pulse),
.a_in(a_in[1:0]),
.d_in(d_in),
.wr_in(triangle_wr),
.triangle_out(triangle_out),
.active_out(triangle_active)
);
assign triangle_wr = ~r_nw_in && (a_in[15:2] == TRIANGLE_CHANNEL_CNTL_MMR_ADDR[15:2]);
//
// Noise channel.
//
wire [3:0] noise_out;
wire noise_active;
wire noise_wr;
apu_noise apu_noise_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(q_noise_en),
.apu_cycle_pulse_in(apu_cycle_pulse),
.lc_pulse_in(l_pulse),
.eg_pulse_in(e_pulse),
.a_in(a_in[1:0]),
.d_in(d_in),
.wr_in(noise_wr),
.noise_out(noise_out),
.active_out(noise_active)
);
assign noise_wr = ~r_nw_in && (a_in[15:2] == NOISE_CHANNEL_CNTL_MMR_ADDR[15:2]);
//
// Mixer.
//
apu_mixer apu_mixer_blk(
.clk_in(clk_in),
.rst_in(rst_in),
.mute_in(mute_in),
.pulse0_in(pulse0_out),
.pulse1_in(pulse1_out),
.triangle_in(triangle_out),
.noise_in(noise_out),
.audio_out(audio_out),
.dac_audio_out(dac_audio_out)
);
assign d_out = (r_nw_in && (a_in == STATUS_MMR_ADDR)) ?
{ 4'b0000, noise_active, triangle_active, pulse1_active, pulse0_active } : 8'h00;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_receiver.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_receiver.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.31 2004/06/18 14:46:15 tadejm
// Brandl Tobias repaired a bug regarding frame error in receiver when brake is received.
//
// Revision 1.29 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.28 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.27 2001/12/30 20:39:13 mohor
// More than one character was stored in case of break. End of the break
// was not detected correctly.
//
// Revision 1.26 2001/12/20 13:28:27 mohor
// Missing declaration of rf_push_q fixed.
//
// Revision 1.25 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.24 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.23 2001/12/19 07:33:54 mohor
// Synplicity was having troubles with the comment.
//
// Revision 1.22 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.21 2001/12/13 10:31:16 mohor
// timeout irq must be set regardless of the rda irq (rda irq does not reset the
// timeout counter).
//
// Revision 1.20 2001/12/10 19:52:05 gorban
// Igor fixed break condition bugs
//
// Revision 1.19 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.18 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.17 2001/11/28 19:36:39 gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
// Revision 1.16 2001/11/27 22:17:09 gorban
// Fixed bug that prevented synthesis in uart_receiver.v
//
// Revision 1.15 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.14 2001/11/10 12:43:21 gorban
// Logic Synthesis bugs fixed. Some other minor changes
//
// Revision 1.13 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.12 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.11 2001/10/31 15:19:22 gorban
// Fixes to break and timeout conditions
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5 2001/06/02 14:28:14 gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.1 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
input clk;
input wb_rst_i;
input [7:0] lcr;
input rf_pop;
input srx_pad_i;
input enable;
input rx_reset;
input lsr_mask;
output [9:0] counter_t;
output [`UART_FIFO_COUNTER_W-1:0] rf_count;
output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
output rf_overrun;
output rf_error_bit;
output [3:0] rstate;
output rf_push_pulse;
reg [3:0] rstate;
reg [3:0] rcounter16;
reg [2:0] rbit_counter;
reg [7:0] rshift; // receiver shift register
reg rparity; // received parity
reg rparity_error;
reg rframing_error; // framing error flag
reg rbit_in;
reg rparity_xor;
reg [7:0] counter_b; // counts the 0 (low) signals
reg rf_push_q;
// RX FIFO signals
reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_push_pulse;
reg rf_push;
wire rf_pop;
wire rf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire break_error = (counter_b == 0);
// RX FIFO instance
uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
.clk( clk ),
.wb_rst_i( wb_rst_i ),
.data_in( rf_data_in ),
.data_out( rf_data_out ),
.push( rf_push_pulse ),
.pop( rf_pop ),
.overrun( rf_overrun ),
.count( rf_count ),
.error_bit( rf_error_bit ),
.fifo_reset( rx_reset ),
.reset_status(lsr_mask)
);
wire rcounter16_eq_7 = (rcounter16 == 4'd7);
wire rcounter16_eq_0 = (rcounter16 == 4'd0);
wire rcounter16_eq_1 = (rcounter16 == 4'd1);
wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1;
parameter sr_idle = 4'd0;
parameter sr_rec_start = 4'd1;
parameter sr_rec_bit = 4'd2;
parameter sr_rec_parity = 4'd3;
parameter sr_rec_stop = 4'd4;
parameter sr_check_parity = 4'd5;
parameter sr_rec_prepare = 4'd6;
parameter sr_end_bit = 4'd7;
parameter sr_ca_lc_parity = 4'd8;
parameter sr_wait1 = 4'd9;
parameter sr_push = 4'd10;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
rstate <= #1 sr_idle;
rbit_in <= #1 1'b0;
rcounter16 <= #1 0;
rbit_counter <= #1 0;
rparity_xor <= #1 1'b0;
rframing_error <= #1 1'b0;
rparity_error <= #1 1'b0;
rparity <= #1 1'b0;
rshift <= #1 0;
rf_push <= #1 1'b0;
rf_data_in <= #1 0;
end
else
if (enable)
begin
case (rstate)
sr_idle : begin
rf_push <= #1 1'b0;
rf_data_in <= #1 0;
rcounter16 <= #1 4'b1110;
if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?)
begin
rstate <= #1 sr_rec_start;
end
end
sr_rec_start : begin
rf_push <= #1 1'b0;
if (rcounter16_eq_7) // check the pulse
if (srx_pad_i==1'b1) // no start bit
rstate <= #1 sr_idle;
else // start bit detected
rstate <= #1 sr_rec_prepare;
rcounter16 <= #1 rcounter16_minus_1;
end
sr_rec_prepare:begin
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
2'b00 : rbit_counter <= #1 3'b100;
2'b01 : rbit_counter <= #1 3'b101;
2'b10 : rbit_counter <= #1 3'b110;
2'b11 : rbit_counter <= #1 3'b111;
endcase
if (rcounter16_eq_0)
begin
rstate <= #1 sr_rec_bit;
rcounter16 <= #1 4'b1110;
rshift <= #1 0;
end
else
rstate <= #1 sr_rec_prepare;
rcounter16 <= #1 rcounter16_minus_1;
end
sr_rec_bit : begin
if (rcounter16_eq_0)
rstate <= #1 sr_end_bit;
if (rcounter16_eq_7) // read the bit
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
2'b00 : rshift[4:0] <= #1 {srx_pad_i, rshift[4:1]};
2'b01 : rshift[5:0] <= #1 {srx_pad_i, rshift[5:1]};
2'b10 : rshift[6:0] <= #1 {srx_pad_i, rshift[6:1]};
2'b11 : rshift[7:0] <= #1 {srx_pad_i, rshift[7:1]};
endcase
rcounter16 <= #1 rcounter16_minus_1;
end
sr_end_bit : begin
if (rbit_counter==3'b0) // no more bits in word
if (lcr[`UART_LC_PE]) // choose state based on parity
rstate <= #1 sr_rec_parity;
else
begin
rstate <= #1 sr_rec_stop;
rparity_error <= #1 1'b0; // no parity - no error :)
end
else // else we have more bits to read
begin
rstate <= #1 sr_rec_bit;
rbit_counter <= #1 rbit_counter - 1'b1;
end
rcounter16 <= #1 4'b1110;
end
sr_rec_parity: begin
if (rcounter16_eq_7) // read the parity
begin
rparity <= #1 srx_pad_i;
rstate <= #1 sr_ca_lc_parity;
end
rcounter16 <= #1 rcounter16_minus_1;
end
sr_ca_lc_parity : begin // rcounter equals 6
rcounter16 <= #1 rcounter16_minus_1;
rparity_xor <= #1 ^{rshift,rparity}; // calculate parity on all incoming data
rstate <= #1 sr_check_parity;
end
sr_check_parity: begin // rcounter equals 5
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
2'b00: rparity_error <= #1 rparity_xor == 0; // no error if parity 1
2'b01: rparity_error <= #1 ~rparity; // parity should sticked to 1
2'b10: rparity_error <= #1 rparity_xor == 1; // error if parity is odd
2'b11: rparity_error <= #1 rparity; // parity should be sticked to 0
endcase
rcounter16 <= #1 rcounter16_minus_1;
rstate <= #1 sr_wait1;
end
sr_wait1 : if (rcounter16_eq_0)
begin
rstate <= #1 sr_rec_stop;
rcounter16 <= #1 4'b1110;
end
else
rcounter16 <= #1 rcounter16_minus_1;
sr_rec_stop : begin
if (rcounter16_eq_7) // read the parity
begin
rframing_error <= #1 !srx_pad_i; // no framing error if input is 1 (stop bit)
rstate <= #1 sr_push;
end
rcounter16 <= #1 rcounter16_minus_1;
end
sr_push : begin
///////////////////////////////////////
// $display($time, ": received: %b", rf_data_in);
if(srx_pad_i | break_error)
begin
if(break_error)
rf_data_in <= #1 {8'b0, 3'b100}; // break input (empty character) to receiver FIFO
else
rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error};
rf_push <= #1 1'b1;
rstate <= #1 sr_idle;
end
else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i
begin
rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error};
rf_push <= #1 1'b1;
rcounter16 <= #1 4'b1110;
rstate <= #1 sr_rec_start;
end
end
default : rstate <= #1 sr_idle;
endcase
end // if (enable)
end // always of receiver
always @ (posedge clk or posedge wb_rst_i)
begin
if(wb_rst_i)
rf_push_q <= 0;
else
rf_push_q <= #1 rf_push;
end
assign rf_push_pulse = rf_push & ~rf_push_q;
//
// Break condition detection.
// Works in conjuction with the receiver state machine
reg [9:0] toc_value; // value to be set to timeout counter
always @(lcr)
case (lcr[3:0])
4'b0000 : toc_value = 447; // 7 bits
4'b0100 : toc_value = 479; // 7.5 bits
4'b0001, 4'b1000 : toc_value = 511; // 8 bits
4'b1100 : toc_value = 543; // 8.5 bits
4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits
4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits
4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits
4'b1111 : toc_value = 767; // 12 bits
endcase // case(lcr[3:0])
wire [7:0] brc_value; // value to be set to break counter
assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
counter_b <= #1 8'd159;
else
if (srx_pad_i)
counter_b <= #1 brc_value; // character time length - 1
else
if(enable & counter_b != 8'b0) // only work on enable times break not reached.
counter_b <= #1 counter_b - 1; // decrement break counter
end // always of break condition detection
///
/// Timeout condition detection
reg [9:0] counter_t; // counts the timeout condition clocks
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
counter_t <= #1 10'd639; // 10 bits for the default 8N1
else
if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level
counter_t <= #1 toc_value;
else
if (enable && counter_t != 10'b0) // we don't want to underflow
counter_t <= #1 counter_t - 1;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/03 15:17:56
// Design Name:
// Module Name: lab3_15s_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab3_15s_tb(
);
reg INPUT,Clk, reset;
parameter DELAY=7.5;
parameter TIME=150;
wire OUT;
integer i;
lab3_15s DUT (.INPUT(INPUT), .Clk(Clk), .OUT(OUT), .reset(reset));
initial
begin
#TIME $finish;
end
initial begin
Clk = 0;
for (i = 0; i < (TIME/DELAY); i = i + 1) begin
#DELAY Clk = ~Clk;
end
end
initial
begin
reset = 1; INPUT = 0;
#(2*DELAY) reset = 0;
#DELAY INPUT=1;
#(2*DELAY) INPUT=1;
#(2*DELAY) INPUT=0;
#(2*DELAY) INPUT=1;
#(2*DELAY) INPUT=0;
#(2*DELAY) INPUT=0;
#(2*DELAY) INPUT=0;
#DELAY;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O41AI_PP_BLACKBOX_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41AI_PP_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: iodelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// This module instantiates the IDELAYCTRL primitive, which continously
// calibrates the IODELAY elements in the region to account for varying
// environmental conditions. A 200MHz or 300MHz reference clock (depending
// on the desired IODELAY tap resolution) must be supplied
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $
**$Date: 2011/06/02 08:34:56 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_iodelay_ctrl #
(
parameter TCQ = 100,
// clk->out delay (sim only)
parameter IODELAY_GRP = "IODELAY_MIG",
// May be assigned unique name when
// multiple IP cores used in design
parameter REFCLK_TYPE = "DIFFERENTIAL",
// Reference clock type
// "DIFFERENTIAL","SINGLE_ENDED"
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
// DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
parameter RST_ACT_LOW = 1,
// Reset input polarity
// (0 = active high, 1 = active low)
parameter DIFF_TERM_REFCLK = "TRUE"
// Differential Termination
)
(
input clk_ref_p,
input clk_ref_n,
input clk_ref_i,
input sys_rst,
output clk_ref,
output sys_rst_o,
output iodelay_ctrl_rdy,
output rst_tmp_idelay,
output rst_ref,
input pll_locked
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
//localparam RST_SYNC_NUM = 25;
wire clk_ref_bufg;
wire clk_ref_ibufg;
wire rst_ref;
(* keep = "true", max_fanout = 10 *) reg [RST_SYNC_NUM-1:0] rst_ref_sync_r /* synthesis syn_maxfan = 10 */;
// wire rst_tmp_idelay;
wire sys_rst_act_hi;
//***************************************************************************
// If the pin is selected for sys_rst in GUI, IBUF will be instantiated.
// If the pin is not selected in GUI, sys_rst signal is expected to be
// driven internally.
generate
if (SYS_RST_PORT == "TRUE")
IBUF u_sys_rst_ibuf
(
.I (sys_rst),
.O (sys_rst_o)
);
else
assign sys_rst_o = sys_rst;
endgenerate
// Possible inversion of system reset as appropriate
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_o: sys_rst_o;
//***************************************************************************
// 1) Input buffer for IDELAYCTRL reference clock - handle either a
// differential or single-ended input. Global clock buffer is used to
// drive the rest of FPGA logic.
// 2) For NO_BUFFER option, Reference clock will be driven from internal
// clock i.e., clock is driven from fabric. Input buffers and Global
// clock buffers will not be instaitaed.
// 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used
// as the input reference clock. Global clock buffer is used to drive
// the rest of FPGA logic.
//***************************************************************************
generate
if (REFCLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_REFCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_p),
.IB (clk_ref_n),
.O (clk_ref_ibufg)
);
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_ibufg)
);
end else if (REFCLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_i),
.O (clk_ref_ibufg)
);
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_ibufg)
);
end else if ((REFCLK_TYPE == "NO_BUFFER") ||
(REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE == "NO_BUFFER")) begin : clk_ref_noibuf_nobuf
assign clk_ref_bufg = clk_ref_i;
end else if (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER") begin : clk_ref_noibuf
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_i)
);
end
endgenerate
//***************************************************************************
// Global clock buffer for IDELAY reference clock
//***************************************************************************
assign clk_ref = clk_ref_bufg;
//*****************************************************************
// IDELAYCTRL reset
// This assumes an external clock signal driving the IDELAYCTRL
// blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL
// lock signal will need to be incorporated in this.
//*****************************************************************
// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi | (~pll_locked);
always @(posedge clk_ref_bufg or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r <= #TCQ rst_ref_sync_r << 1;
assign rst_ref = rst_ref_sync_r[RST_SYNC_NUM-1];
//*****************************************************************
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
(
.RDY (iodelay_ctrl_rdy),
.REFCLK (clk_ref_bufg),
.RST (rst_ref)
);
//wire [35:0] CONTROL0;
//ddr3_icon ddr3_icon_inst (
// .CONTROL0(CONTROL0) // INOUT BUS [35:0]
//);
//
//ddr3_ila ddr3_ila_inst (
// .CONTROL(CONTROL0), // INOUT BUS [35:0]
// .CLK(clk_ref_bufg), // IN
// .TRIG0({
// rst_ref_sync_r,
// sys_rst_act_hi,
// rst_tmp_idelay,
// iodelay_ctrl_rdy,
// rst_ref,
// pll_locked
// }) // IN BUS [31:0]
//);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__OR3_PP_BLACKBOX_V
/**
* or3: 3-input OR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_PP_BLACKBOX_V
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SD_CMD (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
)
;
inout bidir_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire bidir_port;
wire clk_en;
reg data_dir;
wire data_in;
reg data_out;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 1)}} & data_dir);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {{{32 - 1}{1'b0}},read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign bidir_port = data_dir ? data_out : 1'bZ;
assign data_in = bidir_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_dir <= 0;
else if (chipselect && ~write_n && (address == 1))
data_dir <= writedata;
end
endmodule
|
/*
* Copyright (c) Atomic Rules LLC, Auburn NH., 2009-2010
*
* Atomic Rules LLC
* 287 Chester Road
* Auburn, NH 03032
* United States of America
* Telephone 603-483-0994
*
* This file is part of OpenCPI (www.opencpi.org).
* ____ __________ ____
* / __ \____ ___ ____ / ____/ __ \ / _/ ____ _________ _
* / / / / __ \/ _ \/ __ \/ / / /_/ / / / / __ \/ ___/ __ `/
* / /_/ / /_/ / __/ / / / /___/ ____/_/ / _/ /_/ / / / /_/ /
* \____/ .___/\___/_/ /_/\____/_/ /___/(_)____/_/ \__, /
* /_/ /____/
*
* OpenCPI is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* OpenCPI is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with OpenCPI. If not, see <http://www.gnu.org/licenses/>.
*/
// ddrOutput2.v
// Serializes four 12b lanes at sdr125 to one lane at ddr250 (500M)
// 2010-01-14 ssiegel Creation
// 2010-01-15 ssiegel Specialaized for Slave-Drive role
// 2010-01-18 ssiegel Improved OSERDES Reset Synchronizer
// 2010-01-25 ssiegel Tweaked DCM_ADV parameters after reviewing TRCE results
module ddrOutput2#(
parameter nbo = 12,
parameter i2o = 4,
parameter nbi = nbo*i2o)
( input ddrClk, // SE DAC DDR clock 250MHz (ddr500) input_clock ddr
input dcmResetN, // DCM Reset async active-low
output dcmLocked, // DCM Locked
output[nbo-1:0] dap,dan, // DIFF DDR data ddr500 Bit#(12) Action
output[nbo-1:0] dbp,dbn, // DIFF DDR data ddr500 Bit#(12) Action
output[nbo-1:0] dcp,dcn, // DIFF DDR data ddr500 Bit#(12) Action
output[nbo-1:0] ddp,ddn, // DIFF DDR data ddr500 Bit#(12) Action
output sdrClk, // SDR clock output sdr125 Clock sdrClk out
input [nbo-1:0] sdrData0, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrData1, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrData2, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrData3, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrData4, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrData5, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrData6, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrData7, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrData8, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrData9, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrDataA, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrDataB, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrDataC, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrDataD, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrDataE, // SDR Data sdr125 0th Bit#(12) Value
input [nbo-1:0] sdrDataF // SDR Data sdr125 0th Bit#(12) Value
);
// DCM and BUFGs...
DCM_ADV #(
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5...
.CLKFX_DIVIDE(4), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(2), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
//.CLKIN_PERIOD(4.0), // 250 MHz: Specify period of input clock in ns from 1.25 to 1000.00
.CLKIN_PERIOD(16.0), // 61.25 MHz: Specify period of input clock in ns from 1.25 to 1000.00
.CLKOUT_PHASE_SHIFT("FIXED"), // Phaseshift of NONE,FIXED,VARIABLE_POSITIVE,VARIABLE_CENTER,DIRECT
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
//.DFS_FREQUENCY_MODE("HIGH"), // HIGH or LOW frequency mode for frequency synthesis
//.DLL_FREQUENCY_MODE("HIGH"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, "TRUE"/"FALSE"
.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16’hf0f0
.PHASE_SHIFT(-32), // Amount of fixed phase shift from -255 to 1023
.SIM_DEVICE("VIRTEX5"), // Set target device, "VIRTEX4" or "VIRTEX5"
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE"
) DCM_ADV_inst (
.CLK0(dcm_out), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(dcm_div), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.DO(), // 16-bit data output for Dynamic Reconfiguration Port (DRP)
.DRDY(), // Ready output signal from the DRP
.LOCKED(dcmLocked), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.CLKFB(outClk), // DCM clock feedback
.CLKIN(ddrClk), // Clock input (from IBUFG, BUFG or DCM)
.DADDR(7'h00), // 7-bit address for the DRP
.DCLK(1'b0), // Clock for the DRP
.DEN(1'b0), // Enable input for the DRP
.DI(16'h0000), // 16-bit data input for the DRP
.DWE(1'b0), // Active high allows for writing configuration memory
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
.RST(!dcmResetN) // DCM asynchronous reset input (active high)
);
BUFG bufg_i_ddrClk(.O(outClk),.I(dcm_out)); // BUFG driving the OSERDES out typ: 250MHz (DDR500)
BUFG bufg_i_sdrClk(.O(sdrClk),.I(dcm_div)); // BUFG driving the OSERDES in typ: 125MHz
wire rstSerdes;
FDRSE#(.INIT(1'b0))
FRDSE_inst (.Q(rstSerdes), .C(sdrClk), .CE(1'b1), .D(!dcmLocked), .R(1'b0), .S(1'b0));
// The SDR/DDR Output Datapath...
wire da[nbo-1:0], db[nbo-1:0], dc[nbo-1:0], dd[nbo-1:0];
genvar i; generate
for (i=0;i<nbo;i=i+1) begin : DDR_g
OSERDES #(
.DATA_RATE_OQ("DDR"), // Specify data rate to "DDR" or "SDR"
.DATA_RATE_TQ("DDR"), // Specify data rate to "DDR", "SDR", or "BUF"
.DATA_WIDTH(4), // Specify data width - For DDR: 4,6,8, or 10
.INIT_OQ(1'b0), // INIT for OQ register - 1’b1 or 1’b0
.INIT_TQ(1'b0), // INIT for OQ register - 1’b1 or 1’b0
.SERDES_MODE("MASTER"), // Set SERDES mode to "MASTER" or "SLAVE"
.SRVAL_OQ(1'b0), // Define OQ output value upon SR assertion - 1’b1 or 1’b0
.SRVAL_TQ(1'b0), // Define TQ output value upon SR assertion - 1’b1 or 1’b0
.TRISTATE_WIDTH(4) // Specify parallel to serial converter width When DATA_RATE_TQ = DDR: 2 or 4
) OSERDES_inst_a (
.OQ(da[i]), // 1-bit data path output
.SHIFTOUT1(), // 1-bit data expansion output
.SHIFTOUT2(), // 1-bit data expansion output
.TQ(), // 1-bit 3-state control output
.CLK(outClk), // 1-bit clock input
.CLKDIV(sdrClk), // 1-bit divided clock input
.D1(sdrData0[i]), // 1-bit parallel data input
.D2(sdrData4[i]), // 1-bit parallel data input
.D3(sdrData8[i]), // 1-bit parallel data input
.D4(sdrDataC[i]), // 1-bit parallel data input
.D5(1'b0), // 1-bit parallel data input
.D6(1'b0), // 1-bit parallel data input
.OCE(1'b1), // 1-bit clock enable input
.REV(1'b0), // Must be tied to logic zero
.SHIFTIN1(1'b0), // 1-bit data expansion input
.SHIFTIN2(1'b0), // 1-bit data expansion input
.SR(rstSerdes), // 1-bit set/reset input
.T1(1'b0), // 1-bit parallel 3-state input
.T2(1'b0), // 1-bit parallel 3-state input
.T3(1'b0), // 1-bit parallel 3-state input
.T4(1'b0), // 1-bit parallel 3-state input
.TCE(1'b0) // 1-bit 3-state signal clock enable input
);
OBUFDS#(.IOSTANDARD("LVDS_25")) obufds_i_a(.O(dap[i]),.OB(dan[i]),.I(da[i]));
OSERDES #(
.DATA_RATE_OQ("DDR"), // Specify data rate to "DDR" or "SDR"
.DATA_RATE_TQ("DDR"), // Specify data rate to "DDR", "SDR", or "BUF"
.DATA_WIDTH(4), // Specify data width - For DDR: 4,6,8, or 10
.INIT_OQ(1'b0), // INIT for OQ register - 1’b1 or 1’b0
.INIT_TQ(1'b0), // INIT for OQ register - 1’b1 or 1’b0
.SERDES_MODE("MASTER"), // Set SERDES mode to "MASTER" or "SLAVE"
.SRVAL_OQ(1'b0), // Define OQ output value upon SR assertion - 1’b1 or 1’b0
.SRVAL_TQ(1'b0), // Define TQ output value upon SR assertion - 1’b1 or 1’b0
.TRISTATE_WIDTH(4) // Specify parallel to serial converter width When DATA_RATE_TQ = DDR: 2 or 4
) OSERDES_inst_b (
.OQ(db[i]), // 1-bit data path output
.SHIFTOUT1(), // 1-bit data expansion output
.SHIFTOUT2(), // 1-bit data expansion output
.TQ(), // 1-bit 3-state control output
.CLK(outClk), // 1-bit clock input
.CLKDIV(sdrClk), // 1-bit divided clock input
.D1(sdrData1[i]), // 1-bit parallel data input
.D2(sdrData5[i]), // 1-bit parallel data input
.D3(sdrData9[i]), // 1-bit parallel data input
.D4(sdrDataD[i]), // 1-bit parallel data input
.D5(1'b0), // 1-bit parallel data input
.D6(1'b0), // 1-bit parallel data input
.OCE(1'b1), // 1-bit clock enable input
.REV(1'b0), // Must be tied to logic zero
.SHIFTIN1(1'b0), // 1-bit data expansion input
.SHIFTIN2(1'b0), // 1-bit data expansion input
.SR(rstSerdes), // 1-bit set/reset input
.T1(1'b0), // 1-bit parallel 3-state input
.T2(1'b0), // 1-bit parallel 3-state input
.T3(1'b0), // 1-bit parallel 3-state input
.T4(1'b0), // 1-bit parallel 3-state input
.TCE(1'b0) // 1-bit 3-state signal clock enable input
);
OBUFDS#(.IOSTANDARD("LVDS_25")) obufds_i_b(.O(dbp[i]),.OB(dbn[i]),.I(db[i]));
OSERDES #(
.DATA_RATE_OQ("DDR"), // Specify data rate to "DDR" or "SDR"
.DATA_RATE_TQ("DDR"), // Specify data rate to "DDR", "SDR", or "BUF"
.DATA_WIDTH(4), // Specify data width - For DDR: 4,6,8, or 10
.INIT_OQ(1'b0), // INIT for OQ register - 1’b1 or 1’b0
.INIT_TQ(1'b0), // INIT for OQ register - 1’b1 or 1’b0
.SERDES_MODE("MASTER"), // Set SERDES mode to "MASTER" or "SLAVE"
.SRVAL_OQ(1'b0), // Define OQ output value upon SR assertion - 1’b1 or 1’b0
.SRVAL_TQ(1'b0), // Define TQ output value upon SR assertion - 1’b1 or 1’b0
.TRISTATE_WIDTH(4) // Specify parallel to serial converter width When DATA_RATE_TQ = DDR: 2 or 4
) OSERDES_inst_c (
.OQ(dc[i]), // 1-bit data path output
.SHIFTOUT1(), // 1-bit data expansion output
.SHIFTOUT2(), // 1-bit data expansion output
.TQ(), // 1-bit 3-state control output
.CLK(outClk), // 1-bit clock input
.CLKDIV(sdrClk), // 1-bit divided clock input
.D1(sdrData2[i]), // 1-bit parallel data input
.D2(sdrData6[i]), // 1-bit parallel data input
.D3(sdrDataA[i]), // 1-bit parallel data input
.D4(sdrDataE[i]), // 1-bit parallel data input
.D5(1'b0), // 1-bit parallel data input
.D6(1'b0), // 1-bit parallel data input
.OCE(1'b1), // 1-bit clock enable input
.REV(1'b0), // Must be tied to logic zero
.SHIFTIN1(1'b0), // 1-bit data expansion input
.SHIFTIN2(1'b0), // 1-bit data expansion input
.SR(rstSerdes), // 1-bit set/reset input
.T1(1'b0), // 1-bit parallel 3-state input
.T2(1'b0), // 1-bit parallel 3-state input
.T3(1'b0), // 1-bit parallel 3-state input
.T4(1'b0), // 1-bit parallel 3-state input
.TCE(1'b0) // 1-bit 3-state signal clock enable input
);
OBUFDS#(.IOSTANDARD("LVDS_25")) obufds_i_c(.O(dcp[i]),.OB(dcn[i]),.I(dc[i]));
OSERDES #(
.DATA_RATE_OQ("DDR"), // Specify data rate to "DDR" or "SDR"
.DATA_RATE_TQ("DDR"), // Specify data rate to "DDR", "SDR", or "BUF"
.DATA_WIDTH(4), // Specify data width - For DDR: 4,6,8, or 10
.INIT_OQ(1'b0), // INIT for OQ register - 1’b1 or 1’b0
.INIT_TQ(1'b0), // INIT for OQ register - 1’b1 or 1’b0
.SERDES_MODE("MASTER"), // Set SERDES mode to "MASTER" or "SLAVE"
.SRVAL_OQ(1'b0), // Define OQ output value upon SR assertion - 1’b1 or 1’b0
.SRVAL_TQ(1'b0), // Define TQ output value upon SR assertion - 1’b1 or 1’b0
.TRISTATE_WIDTH(4) // Specify parallel to serial converter width When DATA_RATE_TQ = DDR: 2 or 4
) OSERDES_inst_d (
.OQ(dd[i]), // 1-bit data path output
.SHIFTOUT1(), // 1-bit data expansion output
.SHIFTOUT2(), // 1-bit data expansion output
.TQ(), // 1-bit 3-state control output
.CLK(outClk), // 1-bit clock input
.CLKDIV(sdrClk), // 1-bit divided clock input
.D1(sdrData3[i]), // 1-bit parallel data input
.D2(sdrData7[i]), // 1-bit parallel data input
.D3(sdrDataB[i]), // 1-bit parallel data input
.D4(sdrDataF[i]), // 1-bit parallel data input
.D5(1'b0), // 1-bit parallel data input
.D6(1'b0), // 1-bit parallel data input
.OCE(1'b1), // 1-bit clock enable input
.REV(1'b0), // Must be tied to logic zero
.SHIFTIN1(1'b0), // 1-bit data expansion input
.SHIFTIN2(1'b0), // 1-bit data expansion input
.SR(rstSerdes), // 1-bit set/reset input
.T1(1'b0), // 1-bit parallel 3-state input
.T2(1'b0), // 1-bit parallel 3-state input
.T3(1'b0), // 1-bit parallel 3-state input
.T4(1'b0), // 1-bit parallel 3-state input
.TCE(1'b0) // 1-bit 3-state signal clock enable input
);
OBUFDS#(.IOSTANDARD("LVDS_25")) obufds_i_d(.O(ddp[i]),.OB(ddn[i]),.I(dd[i]));
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/22/2015 09:35:04 AM
// Design Name:
// Module Name: pwm
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Enable signal is assumed to synchronous; if enable transitions low during pwm pulse,
// pulse will gracefully complete
//
//////////////////////////////////////////////////////////////////////////////////
module pwm #(CLK_PERIOD = 1000)(
input clk,
input enable,
input [31:0] pwm_period,
output out
);
reg clk_out=1'b0;
reg [31:0] counter = 32'b0;
always @(posedge clk)
begin
if (enable == 1'b1)
begin
if (counter < pwm_period)
begin
clk_out <= 1'b1;
counter <= counter + 32'b1;
end
else
begin
if (counter < (CLK_PERIOD-1))
begin
clk_out <= 1'b0;
counter <= counter + 32'b1;
end
else
begin
clk_out <= 1'b0;
counter <= 32'b0;
end
end //end if counter < pwm_period
end //end if(enable)
else
begin
if ((counter > 0) && (counter < pwm_period) ) //gracefully end the last pwm if it has begun
begin
clk_out <= 1'b1;
counter <= counter + 32'b1;
end
else
begin
clk_out <= 1'b0;
counter <= 32'b0;
end
end
end
assign out = clk_out;
endmodule
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:05:32 EST 2014
//
//
// Ports:
// Name I/O size props
// RDY_s_request_put O 1
// s_response_get O 153
// RDY_s_response_get O 1
// c0_request_get O 153
// RDY_c0_request_get O 1
// RDY_c0_response_put O 1
// c1_request_get O 153
// RDY_c1_request_get O 1
// RDY_c1_response_put O 1
// pfk I 14
// CLK I 1 clock
// RST_N I 1 reset
// s_request_put I 153
// c0_response_put I 153
// c1_response_put I 153
// EN_s_request_put I 1
// EN_c0_response_put I 1
// EN_c1_response_put I 1
// EN_s_response_get I 1
// EN_c0_request_get I 1
// EN_c1_request_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkTLPSM(pfk,
CLK,
RST_N,
s_request_put,
EN_s_request_put,
RDY_s_request_put,
EN_s_response_get,
s_response_get,
RDY_s_response_get,
EN_c0_request_get,
c0_request_get,
RDY_c0_request_get,
c0_response_put,
EN_c0_response_put,
RDY_c0_response_put,
EN_c1_request_get,
c1_request_get,
RDY_c1_request_get,
c1_response_put,
EN_c1_response_put,
RDY_c1_response_put);
input [13 : 0] pfk;
input CLK;
input RST_N;
// action method s_request_put
input [152 : 0] s_request_put;
input EN_s_request_put;
output RDY_s_request_put;
// actionvalue method s_response_get
input EN_s_response_get;
output [152 : 0] s_response_get;
output RDY_s_response_get;
// actionvalue method c0_request_get
input EN_c0_request_get;
output [152 : 0] c0_request_get;
output RDY_c0_request_get;
// action method c0_response_put
input [152 : 0] c0_response_put;
input EN_c0_response_put;
output RDY_c0_response_put;
// actionvalue method c1_request_get
input EN_c1_request_get;
output [152 : 0] c1_request_get;
output RDY_c1_request_get;
// action method c1_response_put
input [152 : 0] c1_response_put;
input EN_c1_response_put;
output RDY_c1_response_put;
// signals for module outputs
wire [152 : 0] c0_request_get, c1_request_get, s_response_get;
wire RDY_c0_request_get,
RDY_c0_response_put,
RDY_c1_request_get,
RDY_c1_response_put,
RDY_s_request_put,
RDY_s_response_get;
// ports of submodule pktFork
wire [152 : 0] pktFork_iport_put, pktFork_oport0_get, pktFork_oport1_get;
wire pktFork_EN_iport_put,
pktFork_EN_oport0_get,
pktFork_EN_oport1_get,
pktFork_RDY_iport_put,
pktFork_RDY_oport0_get,
pktFork_RDY_oport1_get;
// ports of submodule pktMerge
wire [152 : 0] pktMerge_iport0_put, pktMerge_iport1_put, pktMerge_oport_get;
wire pktMerge_EN_iport0_put,
pktMerge_EN_iport1_put,
pktMerge_EN_oport_get,
pktMerge_RDY_iport0_put,
pktMerge_RDY_iport1_put,
pktMerge_RDY_oport_get;
// remaining internal signals
reg [1 : 0] CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1;
wire [13 : 0] x__h110;
// action method s_request_put
assign RDY_s_request_put = pktFork_RDY_iport_put ;
// actionvalue method s_response_get
assign s_response_get = pktMerge_oport_get ;
assign RDY_s_response_get = pktMerge_RDY_oport_get ;
// actionvalue method c0_request_get
assign c0_request_get = pktFork_oport0_get ;
assign RDY_c0_request_get = pktFork_RDY_oport0_get ;
// action method c0_response_put
assign RDY_c0_response_put = pktMerge_RDY_iport0_put ;
// actionvalue method c1_request_get
assign c1_request_get = pktFork_oport1_get ;
assign RDY_c1_request_get = pktFork_RDY_oport1_get ;
// action method c1_response_put
assign RDY_c1_response_put = pktMerge_RDY_iport1_put ;
// submodule pktFork
mkPktFork pktFork(.pfk(x__h110),
.CLK(CLK),
.RST_N(RST_N),
.iport_put(pktFork_iport_put),
.EN_iport_put(pktFork_EN_iport_put),
.EN_oport0_get(pktFork_EN_oport0_get),
.EN_oport1_get(pktFork_EN_oport1_get),
.RDY_iport_put(pktFork_RDY_iport_put),
.oport0_get(pktFork_oport0_get),
.RDY_oport0_get(pktFork_RDY_oport0_get),
.oport1_get(pktFork_oport1_get),
.RDY_oport1_get(pktFork_RDY_oport1_get));
// submodule pktMerge
mkPktMerge pktMerge(.CLK(CLK),
.RST_N(RST_N),
.iport0_put(pktMerge_iport0_put),
.iport1_put(pktMerge_iport1_put),
.EN_iport0_put(pktMerge_EN_iport0_put),
.EN_iport1_put(pktMerge_EN_iport1_put),
.EN_oport_get(pktMerge_EN_oport_get),
.RDY_iport0_put(pktMerge_RDY_iport0_put),
.RDY_iport1_put(pktMerge_RDY_iport1_put),
.oport_get(pktMerge_oport_get),
.RDY_oport_get(pktMerge_RDY_oport_get));
// submodule pktFork
assign pktFork_iport_put = s_request_put ;
assign pktFork_EN_iport_put = EN_s_request_put ;
assign pktFork_EN_oport0_get = EN_c0_request_get ;
assign pktFork_EN_oport1_get = EN_c1_request_get ;
// submodule pktMerge
assign pktMerge_iport0_put = c0_response_put ;
assign pktMerge_iport1_put = c1_response_put ;
assign pktMerge_EN_iport0_put = EN_c0_response_put ;
assign pktMerge_EN_iport1_put = EN_c1_response_put ;
assign pktMerge_EN_oport_get = EN_s_response_get ;
// remaining internal signals
assign x__h110 =
{ CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1,
pfk[11:0] } ;
always@(pfk)
begin
case (pfk[13:12])
2'd0, 2'd1, 2'd2:
CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = pfk[13:12];
2'd3: CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = 2'd3;
endcase
end
endmodule // mkTLPSM
|
`include "../spi_ctl.v"
module test;
reg nss;
reg mosi;
reg sck;
wire miso;
wire [6:0] address_bus;
wire [7:0] data_bus;
wire read_n;
wire write_n;
spi_ctl s1(nss, mosi, sck, miso, address_bus, data_bus, read_n, write_n);
// There are no devices connected to the bus for this test
// bench so here we use write_data_bus to drive the bus
// when read cycle is enabled.
reg [7:0] write_data_bus;
assign data_bus = (~read_n) ? write_data_bus : 8'bz;
// data to be written to the slave
reg [7:0] w_mosi;
reg [4:0] i;
initial begin
$dumpfile("spi_ctl-test.vcd");
$dumpvars(0,test);
sck = 0;
mosi = 0;
nss = 1; // disabled
// This value will be read during a read from the bus.
// Used along with the assign = data_bus above.
write_data_bus = 8'hAA;
//write_data_bus = 8'h53; // 0 1 0 1 0 0 1 1
#2;
/*
* Given below are examples of a read cycle and a write cycle.
* Either or both can be uncommented to test their functionality.
* Each section contains comments that describe what
* values to look for (in Gtkwave) if it is operating properly.
*/
// *** EXAMPLE #1: WRITE CYCLE ***
#1 nss = 0; // enabled
//
// At the START of the FIRST byte you should see the following:
//
// both 'read_n' and 'write_n' high.
//
// At the END of the FIRST byte you should see the following:
//
// both 'read_n' and 'write_n' high.
//
// At the END of the SECOND byte you should see the following:
//
// 'read_n' high, 'write_n' LOW
//
// The value to be written (0xF3 in this example) driven
// to the data bus.
//
// And finally when NSS goes high (disabled) both 'read_n'
// and 'write_n' should go high (disabled).
// And the data bus should go high z.
//
w_mosi = 8'h01; // WRITE address 0x01
SPI_once();
w_mosi = 8'hF3; // value to be written
SPI_once();
#1 nss = 1; // disabled
// *** END EXAMPLE #1 ***
// *** EXAMPLE #2: READ CYCLE ***
/*
#1 nss = 0; // enabled
// What to look for?
//
// Refer to the figure in the documentation (doc/)
// title "Timing diagram of SPI read cycle".
// This should approximately match that diagram.
//
// At the START of the first byte you should see the following:
//
// 'count' set to 1 at the first SAMPLE edge of sck
//
// At the END of the first byte should see the following:
//
// The address should be on the 'address_bus'.
// In this case 0x85 (read 0x05) would result in 0x05
// If 0x84 was sent 0x04 would result.
//
// The value to read (in this case 0xAA in write_data_bus) should
// be on the 'data_bus'.
//
// 'rw' should be 1 for a read
//
// 'read_n' should go low (enabled) during the sample when
// count changes from 7 to 8.
//
// 'write_n' should remain high (disabled.
//
//w_mosi = 8'hD5; // READ address 0x55
w_mosi = 8'h85; // READ address 0x05
//w_mosi = 8'h84;
SPI_once();
//
// During the second cycle the MISO should reflect
// the value transferred to the master.
// (this value is not stored in this test bench so
// it is not easy to view).
// For example, if r_reg is loaded with 0xAA (change this
// value using 'write_bus_data'), the follwing values
// should be seen on the MISO pin during each SPI sample
// (remember that 0xA == 1010_b).
//
// t=n t=(n+A) (n+A > n)
// ---------------------
// MISO 1 0 1 0 1 0 1 0
//
w_mosi = 8'h33; // form feed, value is ignored
SPI_once();
#1 nss = 1; // disabled
// *** END EXAMPLE #2 ***
*/
#3 $finish;
end
// {{{ SPI_once()
/*
* SPI_once()
*
* Perform a single 8-bit SPI cycle.
*
* It mutates the global variables: mosi, sck
* And it writes to mosi whatever value is in w_mosi.
*
* It does not mutate nss, this is left to the controlling
* block.
*/
task SPI_once;
begin
// enable SPI and assign the first value
mosi = w_mosi[7];
// and finish the remaining 7 bits
i = 7;
repeat (7) begin
i = i - 1;
#1;
// sample
sck = 1;
#1;
// propagate
sck = 0;
mosi = w_mosi[i];
end
#1 sck = 1;
#1 sck = 0; // CPOL = 0
end
endtask
// }}}
endmodule
// vim:foldmethod=marker
|
//-----------------------------------------------------------------
// USB CDC Device
// V0.1
// Ultra-Embedded.com
// Copyright 2014-2019
//
// Email: [email protected]
//
// License: LGPL
//-----------------------------------------------------------------
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module usb_cdc_core
(
// Inputs
input clk_i
,input rst_i
,input enable_i
,input [ 7:0] utmi_data_in_i
,input utmi_txready_i
,input utmi_rxvalid_i
,input utmi_rxactive_i
,input utmi_rxerror_i
,input [ 1:0] utmi_linestate_i
,input inport_valid_i
,input [ 7:0] inport_data_i
,input outport_accept_i
// Outputs
,output [ 7:0] utmi_data_out_o
,output utmi_txvalid_o
,output [ 1:0] utmi_op_mode_o
,output [ 1:0] utmi_xcvrselect_o
,output utmi_termselect_o
,output utmi_dppulldown_o
,output utmi_dmpulldown_o
,output inport_accept_o
,output outport_valid_o
,output [ 7:0] outport_data_o
);
parameter USB_SPEED_HS = "False"; // True or False
//-----------------------------------------------------------------
// Defines
//-----------------------------------------------------------------
// Device class
`define DEV_CLASS_RESERVED 8'h00
`define DEV_CLASS_AUDIO 8'h01
`define DEV_CLASS_COMMS 8'h02
`define DEV_CLASS_HID 8'h03
`define DEV_CLASS_MONITOR 8'h04
`define DEV_CLASS_PHY_IF 8'h05
`define DEV_CLASS_POWER 8'h06
`define DEV_CLASS_PRINTER 8'h07
`define DEV_CLASS_STORAGE 8'h08
`define DEV_CLASS_HUB 8'h09
`define DEV_CLASS_TMC 8'hFE
`define DEV_CLASS_VENDOR_CUSTOM 8'hFF
// Standard requests (via SETUP packets)
`define REQ_GET_STATUS 8'h00
`define REQ_CLEAR_FEATURE 8'h01
`define REQ_SET_FEATURE 8'h03
`define REQ_SET_ADDRESS 8'h05
`define REQ_GET_DESCRIPTOR 8'h06
`define REQ_SET_DESCRIPTOR 8'h07
`define REQ_GET_CONFIGURATION 8'h08
`define REQ_SET_CONFIGURATION 8'h09
`define REQ_GET_INTERFACE 8'h0A
`define REQ_SET_INTERFACE 8'h0B
`define REQ_SYNC_FRAME 8'h0C
// Descriptor types
`define DESC_DEVICE 8'h01
`define DESC_CONFIGURATION 8'h02
`define DESC_STRING 8'h03
`define DESC_INTERFACE 8'h04
`define DESC_ENDPOINT 8'h05
`define DESC_DEV_QUALIFIER 8'h06
`define DESC_OTHER_SPEED_CONF 8'h07
`define DESC_IF_POWER 8'h08
// Endpoints
`define ENDPOINT_DIR_MASK 8'h80
`define ENDPOINT_DIR_R 7
`define ENDPOINT_DIR_IN 1'b1
`define ENDPOINT_DIR_OUT 1'b0
`define ENDPOINT_ADDR_MASK 8'h7F
`define ENDPOINT_TYPE_MASK 8'h3
`define ENDPOINT_TYPE_CONTROL 0
`define ENDPOINT_TYPE_ISO 1
`define ENDPOINT_TYPE_BULK 2
`define ENDPOINT_TYPE_INTERRUPT 3
// Device Requests (bmRequestType)
`define USB_RECIPIENT_MASK 8'h1F
`define USB_RECIPIENT_DEVICE 8'h00
`define USB_RECIPIENT_INTERFACE 8'h01
`define USB_RECIPIENT_ENDPOINT 8'h02
`define USB_REQUEST_TYPE_MASK 8'h60
`define USB_STANDARD_REQUEST 8'h00
`define USB_CLASS_REQUEST 8'h20
`define USB_VENDOR_REQUEST 8'h40
// USB device addresses are 7-bits
`define USB_ADDRESS_MASK 8'h7F
// USB Feature Selectors
`define USB_FEATURE_ENDPOINT_STATE 16'h0000
`define USB_FEATURE_REMOTE_WAKEUP 16'h0001
`define USB_FEATURE_TEST_MODE 16'h0002
// String Descriptors
`define UNICODE_LANGUAGE_STR_ID 8'd0
`define MANUFACTURER_STR_ID 8'd1
`define PRODUCT_NAME_STR_ID 8'd2
`define SERIAL_NUM_STR_ID 8'd3
`define CDC_ENDPOINT_BULK_OUT 1
`define CDC_ENDPOINT_BULK_IN 2
`define CDC_ENDPOINT_INTR_IN 3
`define CDC_SEND_ENCAPSULATED_COMMAND 8'h00
`define CDC_GET_ENCAPSULATED_RESPONSE 8'h01
`define CDC_GET_LINE_CODING 8'h21
`define CDC_SET_LINE_CODING 8'h20
`define CDC_SET_CONTROL_LINE_STATE 8'h22
`define CDC_SEND_BREAK 8'h23
// Descriptor ROM offsets / sizes
`define ROM_DESC_DEVICE_ADDR 8'd0
`define ROM_DESC_DEVICE_SIZE 16'd18
`define ROM_DESC_CONF_ADDR 8'd18
`define ROM_DESC_CONF_SIZE 16'd67
`define ROM_DESC_STR_LANG_ADDR 8'd85
`define ROM_DESC_STR_LANG_SIZE 16'd4
`define ROM_DESC_STR_MAN_ADDR 8'd89
`define ROM_DESC_STR_MAN_SIZE 16'd30
`define ROM_DESC_STR_PROD_ADDR 8'd119
`define ROM_DESC_STR_PROD_SIZE 16'd30
`define ROM_DESC_STR_SERIAL_ADDR 8'd149
`define ROM_DESC_STR_SERIAL_SIZE 16'd14
`define ROM_CDC_LINE_CODING_ADDR 8'd163
`define ROM_CDC_LINE_CODING_SIZE 16'd7
//-----------------------------------------------------------------
// Wires
//-----------------------------------------------------------------
wire usb_reset_w;
reg [6:0] device_addr_q;
wire usb_ep0_tx_rd_w;
wire [7:0] usb_ep0_tx_data_w;
wire usb_ep0_tx_empty_w;
wire usb_ep0_rx_wr_w;
wire [7:0] usb_ep0_rx_data_w;
wire usb_ep0_rx_full_w;
wire usb_ep1_tx_rd_w;
wire [7:0] usb_ep1_tx_data_w;
wire usb_ep1_tx_empty_w;
wire usb_ep1_rx_wr_w;
wire [7:0] usb_ep1_rx_data_w;
wire usb_ep1_rx_full_w;
wire usb_ep2_tx_rd_w;
wire [7:0] usb_ep2_tx_data_w;
wire usb_ep2_tx_empty_w;
wire usb_ep2_rx_wr_w;
wire [7:0] usb_ep2_rx_data_w;
wire usb_ep2_rx_full_w;
wire usb_ep3_tx_rd_w;
wire [7:0] usb_ep3_tx_data_w;
wire usb_ep3_tx_empty_w;
wire usb_ep3_rx_wr_w;
wire [7:0] usb_ep3_rx_data_w;
wire usb_ep3_rx_full_w;
// Rx SIE Interface (shared)
wire rx_strb_w;
wire [7:0] rx_data_w;
wire rx_last_w;
wire rx_crc_err_w;
// EP0 Rx SIE Interface
wire ep0_rx_space_w;
wire ep0_rx_valid_w;
wire ep0_rx_setup_w;
// EP0 Tx SIE Interface
wire ep0_tx_ready_w;
wire ep0_tx_data_valid_w;
wire ep0_tx_data_strb_w;
wire [7:0] ep0_tx_data_w;
wire ep0_tx_data_last_w;
wire ep0_tx_data_accept_w;
wire ep0_tx_stall_w;
// EP1 Rx SIE Interface
wire ep1_rx_space_w;
wire ep1_rx_valid_w;
wire ep1_rx_setup_w;
// EP1 Tx SIE Interface
wire ep1_tx_ready_w;
wire ep1_tx_data_valid_w;
wire ep1_tx_data_strb_w;
wire [7:0] ep1_tx_data_w;
wire ep1_tx_data_last_w;
wire ep1_tx_data_accept_w;
wire ep1_tx_stall_w;
// EP2 Rx SIE Interface
wire ep2_rx_space_w;
wire ep2_rx_valid_w;
wire ep2_rx_setup_w;
// EP2 Tx SIE Interface
wire ep2_tx_ready_w;
wire ep2_tx_data_valid_w;
wire ep2_tx_data_strb_w;
wire [7:0] ep2_tx_data_w;
wire ep2_tx_data_last_w;
wire ep2_tx_data_accept_w;
wire ep2_tx_stall_w;
// EP3 Rx SIE Interface
wire ep3_rx_space_w;
wire ep3_rx_valid_w;
wire ep3_rx_setup_w;
// EP3 Tx SIE Interface
wire ep3_tx_ready_w;
wire ep3_tx_data_valid_w;
wire ep3_tx_data_strb_w;
wire [7:0] ep3_tx_data_w;
wire ep3_tx_data_last_w;
wire ep3_tx_data_accept_w;
wire ep3_tx_stall_w;
wire utmi_chirp_en_w;
wire usb_hs_w;
//-----------------------------------------------------------------
// Transceiver Control (high speed)
//-----------------------------------------------------------------
generate
if (USB_SPEED_HS == "True")
begin
localparam STATE_W = 3;
localparam STATE_IDLE = 3'd0;
localparam STATE_WAIT_RST = 3'd1;
localparam STATE_SEND_CHIRP_K = 3'd2;
localparam STATE_WAIT_CHIRP_JK = 3'd3;
localparam STATE_FULLSPEED = 3'd4;
localparam STATE_HIGHSPEED = 3'd5;
reg [STATE_W-1:0] state_q;
reg [STATE_W-1:0] next_state_r;
// 60MHz clock rate
`define USB_RST_W 20
reg [`USB_RST_W-1:0] usb_rst_time_q;
reg [7:0] chirp_count_q;
reg [1:0] last_linestate_q;
localparam DETACH_TIME = 20'd60000; // 1ms -> T0
localparam ATTACH_FS_TIME = 20'd180000; // T0 + 3ms = T1
localparam CHIRPK_TIME = 20'd246000; // T1 + ~1ms
localparam HS_RESET_TIME = 20'd600000; // T0 + 10ms = T9
localparam HS_CHIRP_COUNT = 8'd5;
reg [ 1:0] utmi_op_mode_r;
reg [ 1:0] utmi_xcvrselect_r;
reg utmi_termselect_r;
reg utmi_dppulldown_r;
reg utmi_dmpulldown_r;
always @ *
begin
next_state_r = state_q;
// Default - disconnect
utmi_op_mode_r = 2'd1;
utmi_xcvrselect_r = 2'd0;
utmi_termselect_r = 1'b0;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
case (state_q)
STATE_IDLE:
begin
// Detached
if (enable_i && usb_rst_time_q >= DETACH_TIME)
next_state_r = STATE_WAIT_RST;
end
STATE_WAIT_RST:
begin
// Assert FS mode, check for SE0 (T0)
utmi_op_mode_r = 2'd0;
utmi_xcvrselect_r = 2'd1;
utmi_termselect_r = 1'b1;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
// Wait for SE0 (T1), send device chirp K
if (usb_rst_time_q >= ATTACH_FS_TIME)
next_state_r = STATE_SEND_CHIRP_K;
end
STATE_SEND_CHIRP_K:
begin
// Send chirp K
utmi_op_mode_r = 2'd2;
utmi_xcvrselect_r = 2'd0;
utmi_termselect_r = 1'b1;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
// End of device chirp K (T2)
if (usb_rst_time_q >= CHIRPK_TIME)
next_state_r = STATE_WAIT_CHIRP_JK;
end
STATE_WAIT_CHIRP_JK:
begin
// Stop sending chirp K and wait for downstream port chirps
utmi_op_mode_r = 2'd2;
utmi_xcvrselect_r = 2'd0;
utmi_termselect_r = 1'b1;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
// Required number of chirps detected, move to HS mode (T7)
if (chirp_count_q >= HS_CHIRP_COUNT)
next_state_r = STATE_HIGHSPEED;
// Time out waiting for chirps, fallback to FS mode
else if (usb_rst_time_q >= HS_RESET_TIME)
next_state_r = STATE_FULLSPEED;
end
STATE_FULLSPEED:
begin
utmi_op_mode_r = 2'd0;
utmi_xcvrselect_r = 2'd1;
utmi_termselect_r = 1'b1;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
// USB reset detected...
if (usb_rst_time_q >= HS_RESET_TIME && usb_reset_w)
next_state_r = STATE_WAIT_RST;
end
STATE_HIGHSPEED:
begin
// Enter HS mode
utmi_op_mode_r = 2'd0;
utmi_xcvrselect_r = 2'd0;
utmi_termselect_r = 1'b0;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
// Long SE0 - could be reset or suspend
// TODO: Should revert to FS mode and check...
if (usb_rst_time_q >= HS_RESET_TIME && usb_reset_w)
next_state_r = STATE_WAIT_RST;
end
default:
;
endcase
end
// Update state
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
state_q <= STATE_IDLE;
else
state_q <= next_state_r;
// Time since T0 (start of HS reset)
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_rst_time_q <= `USB_RST_W'b0;
// Entering wait for reset state
else if (next_state_r == STATE_WAIT_RST && state_q != STATE_WAIT_RST)
usb_rst_time_q <= `USB_RST_W'b0;
// Waiting for reset, reset count on line state toggle
else if (state_q == STATE_WAIT_RST && (utmi_linestate_i != 2'b00))
usb_rst_time_q <= `USB_RST_W'b0;
else if (usb_rst_time_q != {(`USB_RST_W){1'b1}})
usb_rst_time_q <= usb_rst_time_q + `USB_RST_W'd1;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
last_linestate_q <= 2'b0;
else
last_linestate_q <= utmi_linestate_i;
// Chirp counter
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
chirp_count_q <= 8'b0;
else if (state_q == STATE_SEND_CHIRP_K)
chirp_count_q <= 8'b0;
else if (state_q == STATE_WAIT_CHIRP_JK && (last_linestate_q != utmi_linestate_i) && chirp_count_q != 8'hFF)
chirp_count_q <= chirp_count_q + 8'd1;
assign utmi_op_mode_o = utmi_op_mode_r;
assign utmi_xcvrselect_o = utmi_xcvrselect_r;
assign utmi_termselect_o = utmi_termselect_r;
assign utmi_dppulldown_o = utmi_dppulldown_r;
assign utmi_dmpulldown_o = utmi_dmpulldown_r;
assign utmi_chirp_en_w = (state_q == STATE_SEND_CHIRP_K);
assign usb_hs_w = (state_q == STATE_HIGHSPEED);
end
else
begin
//-----------------------------------------------------------------
// Transceiver Control
//-----------------------------------------------------------------
reg [ 1:0] utmi_op_mode_r;
reg [ 1:0] utmi_xcvrselect_r;
reg utmi_termselect_r;
reg utmi_dppulldown_r;
reg utmi_dmpulldown_r;
always @ *
begin
if (enable_i)
begin
utmi_op_mode_r = 2'd0;
utmi_xcvrselect_r = 2'd1;
utmi_termselect_r = 1'b1;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
end
else
begin
utmi_op_mode_r = 2'd1;
utmi_xcvrselect_r = 2'd0;
utmi_termselect_r = 1'b0;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
end
end
assign utmi_op_mode_o = utmi_op_mode_r;
assign utmi_xcvrselect_o = utmi_xcvrselect_r;
assign utmi_termselect_o = utmi_termselect_r;
assign utmi_dppulldown_o = utmi_dppulldown_r;
assign utmi_dmpulldown_o = utmi_dmpulldown_r;
assign utmi_chirp_en_w = 1'b0;
assign usb_hs_w = 1'b0;
end
endgenerate
//-----------------------------------------------------------------
// Core
//-----------------------------------------------------------------
usbf_device_core
u_core
(
.clk_i(clk_i),
.rst_i(rst_i),
.intr_o(),
// UTMI interface
.utmi_data_o(utmi_data_out_o),
.utmi_data_i(utmi_data_in_i),
.utmi_txvalid_o(utmi_txvalid_o),
.utmi_txready_i(utmi_txready_i),
.utmi_rxvalid_i(utmi_rxvalid_i),
.utmi_rxactive_i(utmi_rxactive_i),
.utmi_rxerror_i(utmi_rxerror_i),
.utmi_linestate_i(utmi_linestate_i),
.reg_chirp_en_i(utmi_chirp_en_w),
.reg_int_en_sof_i(1'b0),
.reg_dev_addr_i(device_addr_q),
// Rx SIE Interface (shared)
.rx_strb_o(rx_strb_w),
.rx_data_o(rx_data_w),
.rx_last_o(rx_last_w),
.rx_crc_err_o(rx_crc_err_w),
// EP0 Config
.ep0_iso_i(1'b0),
.ep0_stall_i(ep0_tx_stall_w),
.ep0_cfg_int_rx_i(1'b0),
.ep0_cfg_int_tx_i(1'b0),
// EP0 Rx SIE Interface
.ep0_rx_setup_o(ep0_rx_setup_w),
.ep0_rx_valid_o(ep0_rx_valid_w),
.ep0_rx_space_i(ep0_rx_space_w),
// EP0 Tx SIE Interface
.ep0_tx_ready_i(ep0_tx_ready_w),
.ep0_tx_data_valid_i(ep0_tx_data_valid_w),
.ep0_tx_data_strb_i(ep0_tx_data_strb_w),
.ep0_tx_data_i(ep0_tx_data_w),
.ep0_tx_data_last_i(ep0_tx_data_last_w),
.ep0_tx_data_accept_o(ep0_tx_data_accept_w),
// EP1 Config
.ep1_iso_i(1'b0),
.ep1_stall_i(ep1_tx_stall_w),
.ep1_cfg_int_rx_i(1'b0),
.ep1_cfg_int_tx_i(1'b0),
// EP1 Rx SIE Interface
.ep1_rx_setup_o(ep1_rx_setup_w),
.ep1_rx_valid_o(ep1_rx_valid_w),
.ep1_rx_space_i(ep1_rx_space_w),
// EP1 Tx SIE Interface
.ep1_tx_ready_i(ep1_tx_ready_w),
.ep1_tx_data_valid_i(ep1_tx_data_valid_w),
.ep1_tx_data_strb_i(ep1_tx_data_strb_w),
.ep1_tx_data_i(ep1_tx_data_w),
.ep1_tx_data_last_i(ep1_tx_data_last_w),
.ep1_tx_data_accept_o(ep1_tx_data_accept_w),
// EP2 Config
.ep2_iso_i(1'b0),
.ep2_stall_i(ep2_tx_stall_w),
.ep2_cfg_int_rx_i(1'b0),
.ep2_cfg_int_tx_i(1'b0),
// EP2 Rx SIE Interface
.ep2_rx_setup_o(ep2_rx_setup_w),
.ep2_rx_valid_o(ep2_rx_valid_w),
.ep2_rx_space_i(ep2_rx_space_w),
// EP2 Tx SIE Interface
.ep2_tx_ready_i(ep2_tx_ready_w),
.ep2_tx_data_valid_i(ep2_tx_data_valid_w),
.ep2_tx_data_strb_i(ep2_tx_data_strb_w),
.ep2_tx_data_i(ep2_tx_data_w),
.ep2_tx_data_last_i(ep2_tx_data_last_w),
.ep2_tx_data_accept_o(ep2_tx_data_accept_w),
// EP3 Config
.ep3_iso_i(1'b0),
.ep3_stall_i(ep3_tx_stall_w),
.ep3_cfg_int_rx_i(1'b0),
.ep3_cfg_int_tx_i(1'b0),
// EP3 Rx SIE Interface
.ep3_rx_setup_o(ep3_rx_setup_w),
.ep3_rx_valid_o(ep3_rx_valid_w),
.ep3_rx_space_i(ep3_rx_space_w),
// EP3 Tx SIE Interface
.ep3_tx_ready_i(ep3_tx_ready_w),
.ep3_tx_data_valid_i(ep3_tx_data_valid_w),
.ep3_tx_data_strb_i(ep3_tx_data_strb_w),
.ep3_tx_data_i(ep3_tx_data_w),
.ep3_tx_data_last_i(ep3_tx_data_last_w),
.ep3_tx_data_accept_o(ep3_tx_data_accept_w),
// Status
.reg_sts_rst_clr_i(1'b1),
.reg_sts_rst_o(usb_reset_w),
.reg_sts_frame_num_o()
);
assign ep0_rx_space_w = 1'b1;
//-----------------------------------------------------------------
// USB: Setup packet capture (limited to 8 bytes for USB-FS)
//-----------------------------------------------------------------
reg [7:0] setup_packet_q[0:7];
reg [2:0] setup_wr_idx_q;
reg setup_frame_q;
reg setup_valid_q;
reg status_ready_q; // STATUS response received
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
setup_packet_q[0] <= 8'b0;
setup_packet_q[1] <= 8'b0;
setup_packet_q[2] <= 8'b0;
setup_packet_q[3] <= 8'b0;
setup_packet_q[4] <= 8'b0;
setup_packet_q[5] <= 8'b0;
setup_packet_q[6] <= 8'b0;
setup_packet_q[7] <= 8'b0;
setup_wr_idx_q <= 3'b0;
setup_valid_q <= 1'b0;
setup_frame_q <= 1'b0;
status_ready_q <= 1'b0;
end
// SETUP token received
else if (ep0_rx_setup_w)
begin
setup_packet_q[0] <= 8'b0;
setup_packet_q[1] <= 8'b0;
setup_packet_q[2] <= 8'b0;
setup_packet_q[3] <= 8'b0;
setup_packet_q[4] <= 8'b0;
setup_packet_q[5] <= 8'b0;
setup_packet_q[6] <= 8'b0;
setup_packet_q[7] <= 8'b0;
setup_wr_idx_q <= 3'b0;
setup_valid_q <= 1'b0;
setup_frame_q <= 1'b1;
status_ready_q <= 1'b0;
end
// Valid DATA for setup frame
else if (ep0_rx_valid_w && rx_strb_w)
begin
setup_packet_q[setup_wr_idx_q] <= rx_data_w;
setup_wr_idx_q <= setup_wr_idx_q + 3'd1;
setup_valid_q <= setup_frame_q && rx_last_w;
if (rx_last_w)
setup_frame_q <= 1'b0;
end
// Detect STATUS stage (ACK for SETUP GET requests)
// TODO: Not quite correct ....
else if (ep0_rx_valid_w && !rx_strb_w && rx_last_w)
begin
setup_valid_q <= 1'b0;
status_ready_q <= 1'b1;
end
else
setup_valid_q <= 1'b0;
//-----------------------------------------------------------------
// SETUP request decode
//-----------------------------------------------------------------
wire [7:0] bmRequestType_w = setup_packet_q[0];
wire [7:0] bRequest_w = setup_packet_q[1];
wire [15:0] wValue_w = {setup_packet_q[3], setup_packet_q[2]};
wire [15:0] wIndex_w = {setup_packet_q[5], setup_packet_q[4]};
wire [15:0] wLength = {setup_packet_q[7], setup_packet_q[6]};
wire setup_get_w = setup_valid_q && (bmRequestType_w[`ENDPOINT_DIR_R] == `ENDPOINT_DIR_IN);
wire setup_set_w = setup_valid_q && (bmRequestType_w[`ENDPOINT_DIR_R] == `ENDPOINT_DIR_OUT);
wire setup_no_data_w = setup_set_w && (wLength == 16'b0);
// For REQ_GET_DESCRIPTOR
wire [7:0] bDescriptorType_w = setup_packet_q[3];
wire [7:0] bDescriptorIndex_w = setup_packet_q[2];
//-----------------------------------------------------------------
// Process setup request
//-----------------------------------------------------------------
reg ctrl_stall_r; // Send STALL
reg ctrl_ack_r; // Send STATUS (ZLP)
reg [15:0] ctrl_get_len_r;
reg [7:0] desc_addr_r;
reg addressed_q;
reg addressed_r;
reg [6:0] device_addr_r;
reg configured_q;
reg configured_r;
always @ *
begin
ctrl_stall_r = 1'b0;
ctrl_get_len_r = 16'b0;
ctrl_ack_r = 1'b0;
desc_addr_r = 8'b0;
device_addr_r = device_addr_q;
addressed_r = addressed_q;
configured_r = configured_q;
if (setup_valid_q)
begin
case (bmRequestType_w & `USB_REQUEST_TYPE_MASK)
`USB_STANDARD_REQUEST:
begin
case (bRequest_w)
`REQ_GET_STATUS:
begin
$display("GET_STATUS");
end
`REQ_CLEAR_FEATURE:
begin
$display("CLEAR_FEATURE");
ctrl_ack_r = setup_set_w && setup_no_data_w;
end
`REQ_SET_FEATURE:
begin
$display("SET_FEATURE");
ctrl_ack_r = setup_set_w && setup_no_data_w;
end
`REQ_SET_ADDRESS:
begin
$display("SET_ADDRESS: Set device address %d", wValue_w[6:0]);
ctrl_ack_r = setup_set_w && setup_no_data_w;
device_addr_r = wValue_w[6:0];
addressed_r = 1'b1;
end
`REQ_GET_DESCRIPTOR:
begin
$display("GET_DESCRIPTOR: Type %d", bDescriptorType_w);
case (bDescriptorType_w)
`DESC_DEVICE:
begin
desc_addr_r = `ROM_DESC_DEVICE_ADDR;
ctrl_get_len_r = `ROM_DESC_DEVICE_SIZE;
end
`DESC_CONFIGURATION:
begin
desc_addr_r = `ROM_DESC_CONF_ADDR;
ctrl_get_len_r = `ROM_DESC_CONF_SIZE;
end
`DESC_STRING:
begin
case (bDescriptorIndex_w)
`UNICODE_LANGUAGE_STR_ID:
begin
desc_addr_r = `ROM_DESC_STR_LANG_ADDR;
ctrl_get_len_r = `ROM_DESC_STR_LANG_SIZE;
end
`MANUFACTURER_STR_ID:
begin
desc_addr_r = `ROM_DESC_STR_MAN_ADDR;
ctrl_get_len_r = `ROM_DESC_STR_MAN_SIZE;
end
`PRODUCT_NAME_STR_ID:
begin
desc_addr_r = `ROM_DESC_STR_PROD_ADDR;
ctrl_get_len_r = `ROM_DESC_STR_PROD_SIZE;
end
`SERIAL_NUM_STR_ID:
begin
desc_addr_r = `ROM_DESC_STR_SERIAL_ADDR;
ctrl_get_len_r = `ROM_DESC_STR_SERIAL_SIZE;
end
default:
;
endcase
end
default:
;
endcase
end
`REQ_GET_CONFIGURATION:
begin
$display("GET_CONF");
end
`REQ_SET_CONFIGURATION:
begin
$display("SET_CONF: Configuration %x", wValue_w);
if (wValue_w == 16'd0)
begin
configured_r = 1'b0;
ctrl_ack_r = setup_set_w && setup_no_data_w;
end
// Only support one configuration for now
else if (wValue_w == 16'd1)
begin
configured_r = 1'b1;
ctrl_ack_r = setup_set_w && setup_no_data_w;
end
else
ctrl_stall_r = 1'b1;
end
`REQ_GET_INTERFACE:
begin
$display("GET_INTERFACE");
ctrl_stall_r = 1'b1;
end
`REQ_SET_INTERFACE:
begin
$display("SET_INTERFACE: %x %x", wValue_w, wIndex_w);
if (wValue_w == 16'd0 && wIndex_w == 16'd0)
ctrl_ack_r = setup_set_w && setup_no_data_w;
else
ctrl_stall_r = 1'b1;
end
default:
begin
ctrl_stall_r = 1'b1;
end
endcase
end
`USB_VENDOR_REQUEST:
begin
// None supported
ctrl_stall_r = 1'b1;
end
`USB_CLASS_REQUEST:
begin
case (bRequest_w)
`CDC_GET_LINE_CODING:
begin
$display("CDC_GET_LINE_CODING");
desc_addr_r = `ROM_CDC_LINE_CODING_ADDR;
ctrl_get_len_r = `ROM_CDC_LINE_CODING_SIZE;
end
default:
ctrl_ack_r = setup_set_w && setup_no_data_w;
endcase
end
default:
begin
ctrl_stall_r = 1'b1;
end
endcase
end
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
device_addr_q <= 7'b0;
addressed_q <= 1'b0;
configured_q <= 1'b0;
end
else if (usb_reset_w)
begin
device_addr_q <= 7'b0;
addressed_q <= 1'b0;
configured_q <= 1'b0;
end
else
begin
device_addr_q <= device_addr_r;
addressed_q <= addressed_r;
configured_q <= configured_r;
end
//-----------------------------------------------------------------
// SETUP response
//-----------------------------------------------------------------
reg ctrl_sending_q;
reg [15:0] ctrl_send_idx_q;
reg [15:0] ctrl_send_len_q;
wire ctrl_send_zlp_w = ctrl_sending_q && (ctrl_send_len_q != wLength);
reg ctrl_sending_r;
reg [15:0] ctrl_send_idx_r;
reg [15:0] ctrl_send_len_r;
reg ctrl_txvalid_q;
reg [7:0] ctrl_txdata_q;
reg ctrl_txstrb_q;
reg ctrl_txlast_q;
reg ctrl_txstall_q;
reg ctrl_txvalid_r;
reg [7:0] ctrl_txdata_r;
reg ctrl_txstrb_r;
reg ctrl_txlast_r;
reg ctrl_txstall_r;
wire ctrl_send_accept_w = ep0_tx_data_accept_w || !ep0_tx_data_valid_w;
reg [7:0] desc_addr_q;
wire[7:0] desc_data_w;
always @ *
begin
ctrl_sending_r = ctrl_sending_q;
ctrl_send_idx_r = ctrl_send_idx_q;
ctrl_send_len_r = ctrl_send_len_q;
ctrl_txvalid_r = ctrl_txvalid_q;
ctrl_txdata_r = ctrl_txdata_q;
ctrl_txstrb_r = ctrl_txstrb_q;
ctrl_txlast_r = ctrl_txlast_q;
ctrl_txstall_r = ctrl_txstall_q;
// New SETUP request
if (setup_valid_q)
begin
// Send STALL
if (ctrl_stall_r)
begin
ctrl_txvalid_r = 1'b1;
ctrl_txstrb_r = 1'b0;
ctrl_txlast_r = 1'b1;
ctrl_txstall_r = 1'b1;
end
// Send STATUS response (ZLP)
else if (ctrl_ack_r)
begin
ctrl_txvalid_r = 1'b1;
ctrl_txstrb_r = 1'b0;
ctrl_txlast_r = 1'b1;
ctrl_txstall_r = 1'b0;
end
else
begin
ctrl_sending_r = setup_get_w && !ctrl_stall_r;
ctrl_send_idx_r = 16'b0;
ctrl_send_len_r = ctrl_get_len_r;
ctrl_txstall_r = 1'b0;
end
end
// Abort control send when STATUS received
else if (status_ready_q)
begin
ctrl_sending_r = 1'b0;
ctrl_send_idx_r = 16'b0;
ctrl_send_len_r = 16'b0;
ctrl_txvalid_r = 1'b0;
end
else if (ctrl_sending_r && ctrl_send_accept_w)
begin
// TODO: Send ZLP on exact multiple lengths...
ctrl_txvalid_r = 1'b1;
ctrl_txdata_r = desc_data_w;
ctrl_txstrb_r = 1'b1;
ctrl_txlast_r = usb_hs_w ? (ctrl_send_idx_r[5:0] == 6'b111111) : (ctrl_send_idx_r[2:0] == 3'b111);
// Increment send index
ctrl_send_idx_r = ctrl_send_idx_r + 16'd1;
// TODO: Detect need for ZLP
if (ctrl_send_idx_r == wLength)
begin
ctrl_sending_r = 1'b0;
ctrl_txlast_r = 1'b1;
end
end
else if (ctrl_send_accept_w)
ctrl_txvalid_r = 1'b0;
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
ctrl_sending_q <= 1'b0;
ctrl_send_idx_q <= 16'b0;
ctrl_send_len_q <= 16'b0;
ctrl_txvalid_q <= 1'b0;
ctrl_txdata_q <= 8'b0;
ctrl_txstrb_q <= 1'b0;
ctrl_txlast_q <= 1'b0;
ctrl_txstall_q <= 1'b0;
desc_addr_q <= 8'b0;
end
else if (usb_reset_w)
begin
ctrl_sending_q <= 1'b0;
ctrl_send_idx_q <= 16'b0;
ctrl_send_len_q <= 16'b0;
ctrl_txvalid_q <= 1'b0;
ctrl_txdata_q <= 8'b0;
ctrl_txstrb_q <= 1'b0;
ctrl_txlast_q <= 1'b0;
ctrl_txstall_q <= 1'b0;
desc_addr_q <= 8'b0;
end
else
begin
ctrl_sending_q <= ctrl_sending_r;
ctrl_send_idx_q <= ctrl_send_idx_r;
ctrl_send_len_q <= ctrl_send_len_r;
ctrl_txvalid_q <= ctrl_txvalid_r;
ctrl_txdata_q <= ctrl_txdata_r;
ctrl_txstrb_q <= ctrl_txstrb_r;
ctrl_txlast_q <= ctrl_txlast_r;
ctrl_txstall_q <= ctrl_txstall_r;
if (setup_valid_q)
desc_addr_q <= desc_addr_r;
else if (ctrl_sending_r && ctrl_send_accept_w)
desc_addr_q <= desc_addr_q + 8'd1;
end
assign ep0_tx_ready_w = ctrl_txvalid_q;
assign ep0_tx_data_valid_w = ctrl_txvalid_q;
assign ep0_tx_data_strb_w = ctrl_txstrb_q;
assign ep0_tx_data_w = ctrl_txdata_q;
assign ep0_tx_data_last_w = ctrl_txlast_q;
assign ep0_tx_stall_w = ctrl_txstall_q;
//-----------------------------------------------------------------
// Descriptor ROM
//-----------------------------------------------------------------
usb_desc_rom
u_rom
(
.hs_i(usb_hs_w),
.addr_i(desc_addr_q),
.data_o(desc_data_w)
);
//-----------------------------------------------------------------
// Unused Endpoints
//-----------------------------------------------------------------
assign ep1_tx_ready_w = 1'b0;
assign ep1_tx_data_valid_w = 1'b0;
assign ep1_tx_data_strb_w = 1'b0;
assign ep1_tx_data_w = 8'b0;
assign ep1_tx_data_last_w = 1'b0;
assign ep1_tx_stall_w = 1'b0;
assign ep3_tx_ready_w = 1'b0;
assign ep3_tx_data_valid_w = 1'b0;
assign ep3_tx_data_strb_w = 1'b0;
assign ep3_tx_data_w = 8'b0;
assign ep3_tx_data_last_w = 1'b0;
assign ep3_tx_stall_w = 1'b0;
assign ep2_rx_space_w = 1'b0;
assign ep3_rx_space_w = 1'b0;
//-----------------------------------------------------------------
// Stream I/O
//-----------------------------------------------------------------
reg inport_valid_q;
reg [7:0] inport_data_q;
wire inport_last_w = !inport_valid_i;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
inport_valid_q <= 1'b0;
inport_data_q <= 8'b0;
end
else if (inport_accept_o)
begin
inport_valid_q <= inport_valid_i;
inport_data_q <= inport_data_i;
end
assign ep2_tx_data_valid_w = inport_valid_q;
assign ep2_tx_data_w = inport_data_q;
assign ep2_tx_ready_w = ep2_tx_data_valid_w;
assign ep2_tx_data_strb_w = ep2_tx_data_valid_w;
assign ep2_tx_data_last_w = inport_last_w;
assign inport_accept_o = !inport_valid_q | ep2_tx_data_accept_w;
assign outport_valid_o = ep1_rx_valid_w && rx_strb_w;
assign outport_data_o = rx_data_w;
assign ep1_rx_space_w = outport_accept_i;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S2S_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLYMETAL6S2S_PP_BLACKBOX_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlymetal6s2s (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S2S_PP_BLACKBOX_V
|
`timescale 1ns / 100ps
module ecg_top_stim;
reg [15:0] data_in;
reg clk, nReset;
wire [15:0] q_peak_ref,q_peak_pos_ref,r_peak_ref,r_peak_pos_ref,
s_peak_ref,s_peak_pos_ref,start_qrs_fin_2,end_qrs_fin_2,
p_begin,p_end,p_peak,p_peak_pos,t_begin,t_end,t_peak,t_peak_pos;
ecg_top top (q_peak_ref,q_peak_pos_ref,r_peak_ref,r_peak_pos_ref,
s_peak_ref,s_peak_pos_ref,start_qrs_fin_2,end_qrs_fin_2,p_begin,p_end,p_peak,p_peak_pos,t_begin,t_end,t_peak,
t_peak_pos, data_in,clk,nReset);
always
begin
clk = 0;
#500000 clk = 1;
#500000 clk = 0;
end
initial
begin
nReset= 0;
data_in = 9;
#250000 nReset= 1;
#2200000 data_in = 9;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 17 ;
#1000000 data_in = 17 ;
#1000000 data_in = 17 ;
#1000000 data_in = 17 ;
#1000000 data_in = 17 ;
#1000000 data_in = 17 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 43 ;
#1000000 data_in = 43 ;
#1000000 data_in = 43 ;
#1000000 data_in = 43 ;
#1000000 data_in = 51 ;
#1000000 data_in = 51 ;
#1000000 data_in = 51 ;
#1000000 data_in = 51 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 85 ;
#1000000 data_in = 85 ;
#1000000 data_in = 93 ;
#1000000 data_in = 93 ;
#1000000 data_in = 101 ;
#1000000 data_in = 110 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 127 ;
#1000000 data_in = 135 ;
#1000000 data_in = 144 ;
#1000000 data_in = 144 ;
#1000000 data_in = 152 ;
#1000000 data_in = 152 ;
#1000000 data_in = 152 ;
#1000000 data_in = 152 ;
#1000000 data_in = 152 ;
#1000000 data_in = 152 ;
#1000000 data_in = 144 ;
#1000000 data_in = 144 ;
#1000000 data_in = 135 ;
#1000000 data_in = 135 ;
#1000000 data_in = 127 ;
#1000000 data_in = 118 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 101 ;
#1000000 data_in = 93 ;
#1000000 data_in = 93 ;
#1000000 data_in = 85 ;
#1000000 data_in = 85 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 51 ;
#1000000 data_in = 51 ;
#1000000 data_in = 51 ;
#1000000 data_in = 51 ;
#1000000 data_in = 51 ;
#1000000 data_in = 43 ;
#1000000 data_in = 43 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 17 ;
#1000000 data_in = 17 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 0 ;
#1000000 data_in = 0 ;
#1000000 data_in = 0 ;
#1000000 data_in = -7 ;
#1000000 data_in = -7 ;
#1000000 data_in = -7 ;
#1000000 data_in = -7 ;
#1000000 data_in = 0 ;
#1000000 data_in = 0 ;
#1000000 data_in = 0 ;
#1000000 data_in = 0 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 0 ;
#1000000 data_in = 0 ;
#1000000 data_in = 0 ;
#1000000 data_in = 0 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 0 ;
#1000000 data_in = 0 ;
#1000000 data_in = 0 ;
#1000000 data_in = 0 ;
#1000000 data_in = 0 ;
#1000000 data_in = 0 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 17 ;
#1000000 data_in = 17 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 26 ;
#1000000 data_in = 17 ;
#1000000 data_in = 0 ;
#1000000 data_in = -15 ;
#1000000 data_in = -49 ;
#1000000 data_in = -83 ;
#1000000 data_in = -133 ;
#1000000 data_in = -184 ;
#1000000 data_in = -243 ;
#1000000 data_in = -310 ;
#1000000 data_in = -378 ;
#1000000 data_in = -453 ;
#1000000 data_in = -521 ;
#1000000 data_in = -596 ;
#1000000 data_in = -664 ;
#1000000 data_in = -731 ;
#1000000 data_in = -790 ;
#1000000 data_in = -849 ;
#1000000 data_in = -900 ;
#1000000 data_in = -942 ;
#1000000 data_in = -984 ;
#1000000 data_in = -1018 ;
#1000000 data_in = -1043 ;
#1000000 data_in = -1068 ;
#1000000 data_in = -1093 ;
#1000000 data_in = -1110 ;
#1000000 data_in = -1135 ;
#1000000 data_in = -1152 ;
#1000000 data_in = -1178 ;
#1000000 data_in = -1194 ;
#1000000 data_in = -1220 ;
#1000000 data_in = -1253 ;
#1000000 data_in = -1279 ;
#1000000 data_in = -1321 ;
#1000000 data_in = -1354 ;
#1000000 data_in = -1396 ;
#1000000 data_in = -1439 ;
#1000000 data_in = -1489 ;
#1000000 data_in = -1531 ;
#1000000 data_in = -1573 ;
#1000000 data_in = -1615 ;
#1000000 data_in = -1649 ;
#1000000 data_in = -1683 ;
#1000000 data_in = -1708 ;
#1000000 data_in = -1716 ;
#1000000 data_in = -1725 ;
#1000000 data_in = -1725 ;
#1000000 data_in = -1708 ;
#1000000 data_in = -1683 ;
#1000000 data_in = -1641 ;
#1000000 data_in = -1590 ;
#1000000 data_in = -1531 ;
#1000000 data_in = -1464 ;
#1000000 data_in = -1388 ;
#1000000 data_in = -1312 ;
#1000000 data_in = -1220 ;
#1000000 data_in = -1127 ;
#1000000 data_in = -1043 ;
#1000000 data_in = -950 ;
#1000000 data_in = -866 ;
#1000000 data_in = -782 ;
#1000000 data_in = -706 ;
#1000000 data_in = -639 ;
#1000000 data_in = -580 ;
#1000000 data_in = -521 ;
#1000000 data_in = -470 ;
#1000000 data_in = -428 ;
#1000000 data_in = -386 ;
#1000000 data_in = -344 ;
#1000000 data_in = -310 ;
#1000000 data_in = -276 ;
#1000000 data_in = -243 ;
#1000000 data_in = -209 ;
#1000000 data_in = -175 ;
#1000000 data_in = -142 ;
#1000000 data_in = -108 ;
#1000000 data_in = -74 ;
#1000000 data_in = -49 ;
#1000000 data_in = -24 ;
#1000000 data_in = 0 ;
#1000000 data_in = 17 ;
#1000000 data_in = 34 ;
#1000000 data_in = 51 ;
#1000000 data_in = 59 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 85 ;
#1000000 data_in = 85 ;
#1000000 data_in = 93 ;
#1000000 data_in = 93 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 93 ;
#1000000 data_in = 93 ;
#1000000 data_in = 93 ;
#1000000 data_in = 93 ;
#1000000 data_in = 93 ;
#1000000 data_in = 93 ;
#1000000 data_in = 85 ;
#1000000 data_in = 85 ;
#1000000 data_in = 85 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 51 ;
#1000000 data_in = 51 ;
#1000000 data_in = 51 ;
#1000000 data_in = 51 ;
#1000000 data_in = 51 ;
#1000000 data_in = 51 ;
#1000000 data_in = 43 ;
#1000000 data_in = 43 ;
#1000000 data_in = 43 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 26 ;
#1000000 data_in = 17 ;
#1000000 data_in = 17 ;
#1000000 data_in = 9 ;
#1000000 data_in = 0 ;
#1000000 data_in = -7 ;
#1000000 data_in = -7 ;
#1000000 data_in = -15 ;
#1000000 data_in = -15 ;
#1000000 data_in = -24 ;
#1000000 data_in = -24 ;
#1000000 data_in = -32 ;
#1000000 data_in = -32 ;
#1000000 data_in = -41 ;
#1000000 data_in = -41 ;
#1000000 data_in = -41 ;
#1000000 data_in = -49 ;
#1000000 data_in = -49 ;
#1000000 data_in = -58 ;
#1000000 data_in = -58 ;
#1000000 data_in = -66 ;
#1000000 data_in = -74 ;
#1000000 data_in = -83 ;
#1000000 data_in = -83 ;
#1000000 data_in = -91 ;
#1000000 data_in = -100 ;
#1000000 data_in = -108 ;
#1000000 data_in = -116 ;
#1000000 data_in = -125 ;
#1000000 data_in = -133 ;
#1000000 data_in = -142 ;
#1000000 data_in = -150 ;
#1000000 data_in = -159 ;
#1000000 data_in = -167 ;
#1000000 data_in = -175 ;
#1000000 data_in = -184 ;
#1000000 data_in = -192 ;
#1000000 data_in = -201 ;
#1000000 data_in = -209 ;
#1000000 data_in = -218 ;
#1000000 data_in = -234 ;
#1000000 data_in = -243 ;
#1000000 data_in = -251 ;
#1000000 data_in = -260 ;
#1000000 data_in = -268 ;
#1000000 data_in = -285 ;
#1000000 data_in = -293 ;
#1000000 data_in = -302 ;
#1000000 data_in = -319 ;
#1000000 data_in = -327 ;
#1000000 data_in = -344 ;
#1000000 data_in = -361 ;
#1000000 data_in = -369 ;
#1000000 data_in = -386 ;
#1000000 data_in = -403 ;
#1000000 data_in = -420 ;
#1000000 data_in = -428 ;
#1000000 data_in = -445 ;
#1000000 data_in = -462 ;
#1000000 data_in = -470 ;
#1000000 data_in = -487 ;
#1000000 data_in = -504 ;
#1000000 data_in = -512 ;
#1000000 data_in = -529 ;
#1000000 data_in = -546 ;
#1000000 data_in = -563 ;
#1000000 data_in = -588 ;
#1000000 data_in = -605 ;
#1000000 data_in = -630 ;
#1000000 data_in = -647 ;
#1000000 data_in = -672 ;
#1000000 data_in = -698 ;
#1000000 data_in = -714 ;
#1000000 data_in = -740 ;
#1000000 data_in = -765 ;
#1000000 data_in = -790 ;
#1000000 data_in = -807 ;
#1000000 data_in = -832 ;
#1000000 data_in = -858 ;
#1000000 data_in = -874 ;
#1000000 data_in = -891 ;
#1000000 data_in = -908 ;
#1000000 data_in = -933 ;
#1000000 data_in = -950 ;
#1000000 data_in = -967 ;
#1000000 data_in = -984 ;
#1000000 data_in = -1001 ;
#1000000 data_in = -1018 ;
#1000000 data_in = -1034 ;
#1000000 data_in = -1060 ;
#1000000 data_in = -1076 ;
#1000000 data_in = -1093 ;
#1000000 data_in = -1119 ;
#1000000 data_in = -1135 ;
#1000000 data_in = -1161 ;
#1000000 data_in = -1186 ;
#1000000 data_in = -1203 ;
#1000000 data_in = -1228 ;
#1000000 data_in = -1245 ;
#1000000 data_in = -1270 ;
#1000000 data_in = -1287 ;
#1000000 data_in = -1304 ;
#1000000 data_in = -1329 ;
#1000000 data_in = -1346 ;
#1000000 data_in = -1363 ;
#1000000 data_in = -1371 ;
#1000000 data_in = -1388 ;
#1000000 data_in = -1405 ;
#1000000 data_in = -1413 ;
#1000000 data_in = -1430 ;
#1000000 data_in = -1439 ;
#1000000 data_in = -1447 ;
#1000000 data_in = -1455 ;
#1000000 data_in = -1472 ;
#1000000 data_in = -1481 ;
#1000000 data_in = -1489 ;
#1000000 data_in = -1498 ;
#1000000 data_in = -1506 ;
#1000000 data_in = -1514 ;
#1000000 data_in = -1523 ;
#1000000 data_in = -1531 ;
#1000000 data_in = -1540 ;
#1000000 data_in = -1548 ;
#1000000 data_in = -1556 ;
#1000000 data_in = -1556 ;
#1000000 data_in = -1565 ;
#1000000 data_in = -1565 ;
#1000000 data_in = -1565 ;
#1000000 data_in = -1565 ;
#1000000 data_in = -1565 ;
#1000000 data_in = -1565 ;
#1000000 data_in = -1565 ;
#1000000 data_in = -1565 ;
#1000000 data_in = -1565 ;
#1000000 data_in = -1556 ;
#1000000 data_in = -1556 ;
#1000000 data_in = -1556 ;
#1000000 data_in = -1548 ;
#1000000 data_in = -1540 ;
#1000000 data_in = -1540 ;
#1000000 data_in = -1531 ;
#1000000 data_in = -1523 ;
#1000000 data_in = -1506 ;
#1000000 data_in = -1498 ;
#1000000 data_in = -1489 ;
#1000000 data_in = -1472 ;
#1000000 data_in = -1455 ;
#1000000 data_in = -1439 ;
#1000000 data_in = -1413 ;
#1000000 data_in = -1396 ;
#1000000 data_in = -1371 ;
#1000000 data_in = -1354 ;
#1000000 data_in = -1329 ;
#1000000 data_in = -1304 ;
#1000000 data_in = -1279 ;
#1000000 data_in = -1253 ;
#1000000 data_in = -1220 ;
#1000000 data_in = -1194 ;
#1000000 data_in = -1169 ;
#1000000 data_in = -1144 ;
#1000000 data_in = -1110 ;
#1000000 data_in = -1085 ;
#1000000 data_in = -1060 ;
#1000000 data_in = -1026 ;
#1000000 data_in = -1001 ;
#1000000 data_in = -975 ;
#1000000 data_in = -942 ;
#1000000 data_in = -916 ;
#1000000 data_in = -891 ;
#1000000 data_in = -866 ;
#1000000 data_in = -841 ;
#1000000 data_in = -815 ;
#1000000 data_in = -799 ;
#1000000 data_in = -773 ;
#1000000 data_in = -748 ;
#1000000 data_in = -723 ;
#1000000 data_in = -698 ;
#1000000 data_in = -664 ;
#1000000 data_in = -639 ;
#1000000 data_in = -613 ;
#1000000 data_in = -580 ;
#1000000 data_in = -554 ;
#1000000 data_in = -521 ;
#1000000 data_in = -495 ;
#1000000 data_in = -470 ;
#1000000 data_in = -445 ;
#1000000 data_in = -420 ;
#1000000 data_in = -394 ;
#1000000 data_in = -378 ;
#1000000 data_in = -352 ;
#1000000 data_in = -335 ;
#1000000 data_in = -319 ;
#1000000 data_in = -302 ;
#1000000 data_in = -285 ;
#1000000 data_in = -276 ;
#1000000 data_in = -260 ;
#1000000 data_in = -243 ;
#1000000 data_in = -226 ;
#1000000 data_in = -218 ;
#1000000 data_in = -201 ;
#1000000 data_in = -184 ;
#1000000 data_in = -175 ;
#1000000 data_in = -159 ;
#1000000 data_in = -142 ;
#1000000 data_in = -133 ;
#1000000 data_in = -125 ;
#1000000 data_in = -108 ;
#1000000 data_in = -100 ;
#1000000 data_in = -91 ;
#1000000 data_in = -83 ;
#1000000 data_in = -74 ;
#1000000 data_in = -74 ;
#1000000 data_in = -66 ;
#1000000 data_in = -58 ;
#1000000 data_in = -49 ;
#1000000 data_in = -49 ;
#1000000 data_in = -41 ;
#1000000 data_in = -32 ;
#1000000 data_in = -24 ;
#1000000 data_in = -24 ;
#1000000 data_in = -15 ;
#1000000 data_in = -7 ;
#1000000 data_in = -7 ;
#1000000 data_in = 0 ;
#1000000 data_in = 0 ;
#1000000 data_in = 9 ;
#1000000 data_in = 9 ;
#1000000 data_in = 17 ;
#1000000 data_in = 17 ;
#1000000 data_in = 26 ;
#1000000 data_in = 26 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 34 ;
#1000000 data_in = 43 ;
#1000000 data_in = 43 ;
#1000000 data_in = 51 ;
#1000000 data_in = 51 ;
#1000000 data_in = 59 ;
#1000000 data_in = 59 ;
#1000000 data_in = 68 ;
#1000000 data_in = 68 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 76 ;
#1000000 data_in = 85 ;
#1000000 data_in = 85 ;
#1000000 data_in = 93 ;
#1000000 data_in = 93 ;
#1000000 data_in = 93 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 101 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 110 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 118 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 127 ;
#1000000 data_in = 135 ;
#1000000 data_in = 135 ;
#1050000 data_in = 1 ;
#1000000 data_in = 30 ;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 08 17:41:40 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_vga_color_test_0_0 -prefix
// system_vga_color_test_0_0_ system_vga_color_test_0_0_sim_netlist.v
// Design : system_vga_color_test_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_color_test_0_0,vga_color_test,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_color_test,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_color_test_0_0
(clk_25,
xaddr,
yaddr,
rgb);
input clk_25;
input [9:0]xaddr;
input [9:0]yaddr;
output [23:0]rgb;
wire clk_25;
wire [23:3]\^rgb ;
wire [9:0]xaddr;
wire [9:0]yaddr;
assign rgb[23:22] = \^rgb [23:22];
assign rgb[21] = \^rgb [20];
assign rgb[20] = \^rgb [20];
assign rgb[19] = \^rgb [20];
assign rgb[18] = \^rgb [20];
assign rgb[17] = \^rgb [20];
assign rgb[16] = \^rgb [20];
assign rgb[15:14] = \^rgb [15:14];
assign rgb[13] = \^rgb [12];
assign rgb[12] = \^rgb [12];
assign rgb[11] = \^rgb [12];
assign rgb[10] = \^rgb [12];
assign rgb[9] = \^rgb [12];
assign rgb[8] = \^rgb [12];
assign rgb[7:5] = \^rgb [7:5];
assign rgb[4] = \^rgb [3];
assign rgb[3] = \^rgb [3];
assign rgb[2] = \^rgb [3];
assign rgb[1] = \^rgb [3];
assign rgb[0] = \^rgb [3];
system_vga_color_test_0_0_vga_color_test U0
(.clk_25(clk_25),
.rgb({\^rgb [23:22],\^rgb [20],\^rgb [15:14],\^rgb [12],\^rgb [7:5],\^rgb [3]}),
.xaddr(xaddr),
.yaddr(yaddr[9:3]));
endmodule
module system_vga_color_test_0_0_vga_color_test
(rgb,
yaddr,
xaddr,
clk_25);
output [9:0]rgb;
input [6:0]yaddr;
input [9:0]xaddr;
input clk_25;
wire clk_25;
wire [9:0]rgb;
wire \rgb[13]_i_1_n_0 ;
wire \rgb[14]_i_1_n_0 ;
wire \rgb[14]_i_2_n_0 ;
wire \rgb[14]_i_3_n_0 ;
wire \rgb[14]_i_4_n_0 ;
wire \rgb[14]_i_5_n_0 ;
wire \rgb[14]_i_6_n_0 ;
wire \rgb[15]_i_1_n_0 ;
wire \rgb[15]_i_2_n_0 ;
wire \rgb[15]_i_3_n_0 ;
wire \rgb[15]_i_4_n_0 ;
wire \rgb[15]_i_5_n_0 ;
wire \rgb[15]_i_6_n_0 ;
wire \rgb[15]_i_7_n_0 ;
wire \rgb[21]_i_1_n_0 ;
wire \rgb[22]_i_10_n_0 ;
wire \rgb[22]_i_11_n_0 ;
wire \rgb[22]_i_1_n_0 ;
wire \rgb[22]_i_2_n_0 ;
wire \rgb[22]_i_3_n_0 ;
wire \rgb[22]_i_4_n_0 ;
wire \rgb[22]_i_5_n_0 ;
wire \rgb[22]_i_6_n_0 ;
wire \rgb[22]_i_7_n_0 ;
wire \rgb[22]_i_8_n_0 ;
wire \rgb[22]_i_9_n_0 ;
wire \rgb[23]_i_10_n_0 ;
wire \rgb[23]_i_11_n_0 ;
wire \rgb[23]_i_12_n_0 ;
wire \rgb[23]_i_13_n_0 ;
wire \rgb[23]_i_14_n_0 ;
wire \rgb[23]_i_15_n_0 ;
wire \rgb[23]_i_16_n_0 ;
wire \rgb[23]_i_17_n_0 ;
wire \rgb[23]_i_18_n_0 ;
wire \rgb[23]_i_1_n_0 ;
wire \rgb[23]_i_2_n_0 ;
wire \rgb[23]_i_3_n_0 ;
wire \rgb[23]_i_4_n_0 ;
wire \rgb[23]_i_5_n_0 ;
wire \rgb[23]_i_6_n_0 ;
wire \rgb[23]_i_7_n_0 ;
wire \rgb[23]_i_8_n_0 ;
wire \rgb[23]_i_9_n_0 ;
wire \rgb[4]_i_1_n_0 ;
wire \rgb[4]_i_2_n_0 ;
wire \rgb[5]_i_1_n_0 ;
wire \rgb[5]_i_2_n_0 ;
wire \rgb[6]_i_1_n_0 ;
wire \rgb[6]_i_2_n_0 ;
wire \rgb[6]_i_3_n_0 ;
wire \rgb[6]_i_4_n_0 ;
wire \rgb[6]_i_5_n_0 ;
wire \rgb[7]_i_1_n_0 ;
wire \rgb[7]_i_2_n_0 ;
wire \rgb[7]_i_3_n_0 ;
wire \rgb[7]_i_4_n_0 ;
wire \rgb[7]_i_5_n_0 ;
wire \rgb[7]_i_6_n_0 ;
wire [9:0]xaddr;
wire [6:0]yaddr;
LUT5 #(
.INIT(32'h5555FF02))
\rgb[13]_i_1
(.I0(\rgb[15]_i_4_n_0 ),
.I1(\rgb[14]_i_2_n_0 ),
.I2(\rgb[14]_i_3_n_0 ),
.I3(\rgb[22]_i_2_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.O(\rgb[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'h55555555FFFFFF02))
\rgb[14]_i_1
(.I0(\rgb[15]_i_4_n_0 ),
.I1(\rgb[14]_i_2_n_0 ),
.I2(\rgb[14]_i_3_n_0 ),
.I3(\rgb[22]_i_3_n_0 ),
.I4(\rgb[22]_i_2_n_0 ),
.I5(\rgb[23]_i_6_n_0 ),
.O(\rgb[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'h02F20202))
\rgb[14]_i_2
(.I0(\rgb[14]_i_4_n_0 ),
.I1(\rgb[23]_i_11_n_0 ),
.I2(xaddr[9]),
.I3(\rgb[14]_i_5_n_0 ),
.I4(\rgb[23]_i_10_n_0 ),
.O(\rgb[14]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'hE))
\rgb[14]_i_3
(.I0(\rgb[14]_i_6_n_0 ),
.I1(yaddr[6]),
.O(\rgb[14]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFEFEFEFEFEFEFEEE))
\rgb[14]_i_4
(.I0(xaddr[4]),
.I1(xaddr[5]),
.I2(xaddr[3]),
.I3(xaddr[0]),
.I4(xaddr[1]),
.I5(xaddr[2]),
.O(\rgb[14]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFF8))
\rgb[14]_i_5
(.I0(xaddr[2]),
.I1(xaddr[5]),
.I2(xaddr[7]),
.I3(xaddr[6]),
.I4(xaddr[8]),
.O(\rgb[14]_i_5_n_0 ));
LUT6 #(
.INIT(64'hA888A888A8888888))
\rgb[14]_i_6
(.I0(yaddr[5]),
.I1(yaddr[4]),
.I2(yaddr[2]),
.I3(yaddr[3]),
.I4(yaddr[1]),
.I5(yaddr[0]),
.O(\rgb[14]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000FFFF55455545))
\rgb[15]_i_1
(.I0(\rgb[23]_i_4_n_0 ),
.I1(\rgb[22]_i_2_n_0 ),
.I2(\rgb[15]_i_2_n_0 ),
.I3(\rgb[15]_i_3_n_0 ),
.I4(\rgb[15]_i_4_n_0 ),
.I5(\rgb[23]_i_6_n_0 ),
.O(\rgb[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h7))
\rgb[15]_i_2
(.I0(\rgb[22]_i_8_n_0 ),
.I1(\rgb[23]_i_12_n_0 ),
.O(\rgb[15]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hAAA88888))
\rgb[15]_i_3
(.I0(\rgb[14]_i_3_n_0 ),
.I1(xaddr[9]),
.I2(xaddr[6]),
.I3(xaddr[7]),
.I4(xaddr[8]),
.O(\rgb[15]_i_3_n_0 ));
LUT6 #(
.INIT(64'hECEEEEEEECECECEC))
\rgb[15]_i_4
(.I0(xaddr[8]),
.I1(xaddr[9]),
.I2(xaddr[7]),
.I3(\rgb[15]_i_5_n_0 ),
.I4(\rgb[15]_i_6_n_0 ),
.I5(\rgb[15]_i_7_n_0 ),
.O(\rgb[15]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h1F))
\rgb[15]_i_5
(.I0(xaddr[0]),
.I1(xaddr[1]),
.I2(xaddr[2]),
.O(\rgb[15]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h7))
\rgb[15]_i_6
(.I0(xaddr[5]),
.I1(xaddr[4]),
.O(\rgb[15]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h8880))
\rgb[15]_i_7
(.I0(xaddr[6]),
.I1(xaddr[5]),
.I2(xaddr[4]),
.I3(xaddr[3]),
.O(\rgb[15]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFFBF0FB))
\rgb[21]_i_1
(.I0(\rgb[22]_i_2_n_0 ),
.I1(\rgb[22]_i_4_n_0 ),
.I2(\rgb[23]_i_2_n_0 ),
.I3(\rgb[23]_i_6_n_0 ),
.I4(\rgb[23]_i_7_n_0 ),
.O(\rgb[21]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEFFF00FFEF))
\rgb[22]_i_1
(.I0(\rgb[22]_i_2_n_0 ),
.I1(\rgb[22]_i_3_n_0 ),
.I2(\rgb[22]_i_4_n_0 ),
.I3(\rgb[23]_i_2_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[23]_i_7_n_0 ),
.O(\rgb[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h01))
\rgb[22]_i_10
(.I0(xaddr[9]),
.I1(xaddr[6]),
.I2(xaddr[7]),
.O(\rgb[22]_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0070))
\rgb[22]_i_11
(.I0(xaddr[3]),
.I1(xaddr[4]),
.I2(xaddr[8]),
.I3(xaddr[5]),
.O(\rgb[22]_i_11_n_0 ));
LUT6 #(
.INIT(64'h00000000AAABABAB))
\rgb[22]_i_2
(.I0(\rgb[22]_i_5_n_0 ),
.I1(xaddr[8]),
.I2(xaddr[9]),
.I3(xaddr[6]),
.I4(xaddr[7]),
.I5(\rgb[22]_i_6_n_0 ),
.O(\rgb[22]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000FD0000))
\rgb[22]_i_3
(.I0(\rgb[23]_i_15_n_0 ),
.I1(xaddr[4]),
.I2(xaddr[5]),
.I3(\rgb[22]_i_7_n_0 ),
.I4(xaddr[9]),
.I5(\rgb[22]_i_6_n_0 ),
.O(\rgb[22]_i_3_n_0 ));
LUT4 #(
.INIT(16'hFFAE))
\rgb[22]_i_4
(.I0(\rgb[23]_i_7_n_0 ),
.I1(\rgb[22]_i_8_n_0 ),
.I2(\rgb[23]_i_8_n_0 ),
.I3(\rgb[14]_i_3_n_0 ),
.O(\rgb[22]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000200030003))
\rgb[22]_i_5
(.I0(\rgb[15]_i_5_n_0 ),
.I1(xaddr[9]),
.I2(xaddr[8]),
.I3(xaddr[5]),
.I4(xaddr[3]),
.I5(xaddr[4]),
.O(\rgb[22]_i_5_n_0 ));
LUT6 #(
.INIT(64'h111111111111111F))
\rgb[22]_i_6
(.I0(\rgb[14]_i_6_n_0 ),
.I1(yaddr[6]),
.I2(\rgb[22]_i_9_n_0 ),
.I3(xaddr[7]),
.I4(xaddr[8]),
.I5(xaddr[9]),
.O(\rgb[22]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFFEFEFEFFFFFFFF))
\rgb[22]_i_7
(.I0(xaddr[8]),
.I1(xaddr[6]),
.I2(xaddr[7]),
.I3(xaddr[5]),
.I4(xaddr[2]),
.I5(\rgb[23]_i_10_n_0 ),
.O(\rgb[22]_i_7_n_0 ));
LUT6 #(
.INIT(64'h5515551555151515))
\rgb[22]_i_8
(.I0(\rgb[23]_i_14_n_0 ),
.I1(\rgb[22]_i_10_n_0 ),
.I2(\rgb[22]_i_11_n_0 ),
.I3(xaddr[4]),
.I4(xaddr[1]),
.I5(xaddr[2]),
.O(\rgb[22]_i_8_n_0 ));
LUT6 #(
.INIT(64'hCCCC000088800000))
\rgb[22]_i_9
(.I0(xaddr[3]),
.I1(xaddr[6]),
.I2(xaddr[2]),
.I3(xaddr[1]),
.I4(xaddr[5]),
.I5(xaddr[4]),
.O(\rgb[22]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAAEAAAEAAAE))
\rgb[23]_i_1
(.I0(\rgb[23]_i_2_n_0 ),
.I1(\rgb[23]_i_3_n_0 ),
.I2(\rgb[23]_i_4_n_0 ),
.I3(\rgb[23]_i_5_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[23]_i_7_n_0 ),
.O(\rgb[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h1F))
\rgb[23]_i_10
(.I0(xaddr[3]),
.I1(xaddr[4]),
.I2(xaddr[5]),
.O(\rgb[23]_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h7F))
\rgb[23]_i_11
(.I0(xaddr[8]),
.I1(xaddr[6]),
.I2(xaddr[7]),
.O(\rgb[23]_i_11_n_0 ));
LUT2 #(
.INIT(4'h1))
\rgb[23]_i_12
(.I0(yaddr[6]),
.I1(\rgb[14]_i_6_n_0 ),
.O(\rgb[23]_i_12_n_0 ));
LUT6 #(
.INIT(64'h0515555515155555))
\rgb[23]_i_13
(.I0(\rgb[23]_i_18_n_0 ),
.I1(xaddr[4]),
.I2(xaddr[5]),
.I3(\rgb[23]_i_17_n_0 ),
.I4(xaddr[6]),
.I5(xaddr[3]),
.O(\rgb[23]_i_13_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h1))
\rgb[23]_i_14
(.I0(xaddr[9]),
.I1(xaddr[8]),
.O(\rgb[23]_i_14_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h15))
\rgb[23]_i_15
(.I0(xaddr[3]),
.I1(xaddr[1]),
.I2(xaddr[2]),
.O(\rgb[23]_i_15_n_0 ));
LUT2 #(
.INIT(4'hE))
\rgb[23]_i_16
(.I0(xaddr[7]),
.I1(xaddr[6]),
.O(\rgb[23]_i_16_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'hE))
\rgb[23]_i_17
(.I0(xaddr[2]),
.I1(xaddr[1]),
.O(\rgb[23]_i_17_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hFE))
\rgb[23]_i_18
(.I0(xaddr[7]),
.I1(xaddr[8]),
.I2(xaddr[9]),
.O(\rgb[23]_i_18_n_0 ));
LUT6 #(
.INIT(64'h0000000000022222))
\rgb[23]_i_2
(.I0(\rgb[15]_i_4_n_0 ),
.I1(yaddr[6]),
.I2(yaddr[4]),
.I3(yaddr[3]),
.I4(yaddr[5]),
.I5(\rgb[23]_i_8_n_0 ),
.O(\rgb[23]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAAFFFB))
\rgb[23]_i_3
(.I0(\rgb[14]_i_3_n_0 ),
.I1(\rgb[15]_i_4_n_0 ),
.I2(\rgb[23]_i_9_n_0 ),
.I3(xaddr[9]),
.I4(\rgb[23]_i_7_n_0 ),
.O(\rgb[23]_i_3_n_0 ));
LUT5 #(
.INIT(32'h00004440))
\rgb[23]_i_4
(.I0(xaddr[9]),
.I1(\rgb[23]_i_9_n_0 ),
.I2(\rgb[23]_i_10_n_0 ),
.I3(\rgb[23]_i_11_n_0 ),
.I4(\rgb[23]_i_12_n_0 ),
.O(\rgb[23]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0057FFFF00570057))
\rgb[23]_i_5
(.I0(yaddr[5]),
.I1(yaddr[3]),
.I2(yaddr[4]),
.I3(yaddr[6]),
.I4(\rgb[23]_i_12_n_0 ),
.I5(\rgb[23]_i_13_n_0 ),
.O(\rgb[23]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0155))
\rgb[23]_i_6
(.I0(yaddr[6]),
.I1(yaddr[4]),
.I2(yaddr[3]),
.I3(yaddr[5]),
.O(\rgb[23]_i_6_n_0 ));
LUT6 #(
.INIT(64'h40CC44CC44CC44CC))
\rgb[23]_i_7
(.I0(xaddr[6]),
.I1(\rgb[23]_i_14_n_0 ),
.I2(\rgb[23]_i_15_n_0 ),
.I3(xaddr[7]),
.I4(xaddr[4]),
.I5(xaddr[5]),
.O(\rgb[23]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFD500000000))
\rgb[23]_i_8
(.I0(\rgb[23]_i_10_n_0 ),
.I1(xaddr[2]),
.I2(xaddr[5]),
.I3(\rgb[23]_i_16_n_0 ),
.I4(xaddr[8]),
.I5(xaddr[9]),
.O(\rgb[23]_i_8_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFFFFE0))
\rgb[23]_i_9
(.I0(\rgb[23]_i_17_n_0 ),
.I1(xaddr[0]),
.I2(xaddr[3]),
.I3(xaddr[5]),
.I4(xaddr[4]),
.I5(\rgb[23]_i_11_n_0 ),
.O(\rgb[23]_i_9_n_0 ));
LUT5 #(
.INIT(32'h04770404))
\rgb[4]_i_1
(.I0(\rgb[6]_i_2_n_0 ),
.I1(\rgb[23]_i_6_n_0 ),
.I2(\rgb[23]_i_7_n_0 ),
.I3(\rgb[4]_i_2_n_0 ),
.I4(\rgb[5]_i_2_n_0 ),
.O(\rgb[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF2F2FFFFF202F))
\rgb[4]_i_2
(.I0(\rgb[22]_i_8_n_0 ),
.I1(\rgb[15]_i_4_n_0 ),
.I2(\rgb[23]_i_12_n_0 ),
.I3(\rgb[6]_i_5_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[23]_i_13_n_0 ),
.O(\rgb[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAFEAAAAAAAA))
\rgb[5]_i_1
(.I0(\rgb[7]_i_4_n_0 ),
.I1(\rgb[15]_i_2_n_0 ),
.I2(\rgb[15]_i_4_n_0 ),
.I3(\rgb[15]_i_3_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[5]_i_2_n_0 ),
.O(\rgb[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h7F7F0F7F))
\rgb[5]_i_2
(.I0(\rgb[14]_i_2_n_0 ),
.I1(\rgb[22]_i_8_n_0 ),
.I2(\rgb[23]_i_12_n_0 ),
.I3(\rgb[23]_i_7_n_0 ),
.I4(\rgb[7]_i_3_n_0 ),
.O(\rgb[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000F000FFFFF0045))
\rgb[6]_i_1
(.I0(\rgb[14]_i_3_n_0 ),
.I1(\rgb[7]_i_3_n_0 ),
.I2(\rgb[23]_i_7_n_0 ),
.I3(\rgb[6]_i_2_n_0 ),
.I4(\rgb[6]_i_3_n_0 ),
.I5(\rgb[23]_i_6_n_0 ),
.O(\rgb[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hEA))
\rgb[6]_i_2
(.I0(\rgb[14]_i_2_n_0 ),
.I1(\rgb[22]_i_8_n_0 ),
.I2(\rgb[7]_i_6_n_0 ),
.O(\rgb[6]_i_2_n_0 ));
LUT5 #(
.INIT(32'h00FF0002))
\rgb[6]_i_3
(.I0(xaddr[9]),
.I1(\rgb[22]_i_7_n_0 ),
.I2(\rgb[6]_i_4_n_0 ),
.I3(\rgb[22]_i_6_n_0 ),
.I4(\rgb[6]_i_5_n_0 ),
.O(\rgb[6]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00000007))
\rgb[6]_i_4
(.I0(xaddr[2]),
.I1(xaddr[1]),
.I2(xaddr[3]),
.I3(xaddr[4]),
.I4(xaddr[5]),
.O(\rgb[6]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0057))
\rgb[6]_i_5
(.I0(xaddr[8]),
.I1(xaddr[7]),
.I2(xaddr[6]),
.I3(xaddr[9]),
.O(\rgb[6]_i_5_n_0 ));
LUT5 #(
.INIT(32'h0000222A))
\rgb[7]_i_1
(.I0(\rgb[7]_i_3_n_0 ),
.I1(yaddr[5]),
.I2(yaddr[3]),
.I3(yaddr[4]),
.I4(yaddr[6]),
.O(\rgb[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF000000FB))
\rgb[7]_i_2
(.I0(\rgb[7]_i_3_n_0 ),
.I1(\rgb[23]_i_7_n_0 ),
.I2(\rgb[14]_i_3_n_0 ),
.I3(\rgb[23]_i_4_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[7]_i_4_n_0 ),
.O(\rgb[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h0000000D))
\rgb[7]_i_3
(.I0(xaddr[6]),
.I1(\rgb[7]_i_5_n_0 ),
.I2(xaddr[9]),
.I3(xaddr[8]),
.I4(xaddr[7]),
.O(\rgb[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00000444))
\rgb[7]_i_4
(.I0(\rgb[23]_i_7_n_0 ),
.I1(\rgb[23]_i_6_n_0 ),
.I2(\rgb[7]_i_6_n_0 ),
.I3(\rgb[22]_i_8_n_0 ),
.I4(\rgb[14]_i_2_n_0 ),
.O(\rgb[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h1515155515155555))
\rgb[7]_i_5
(.I0(xaddr[5]),
.I1(xaddr[3]),
.I2(xaddr[4]),
.I3(xaddr[0]),
.I4(xaddr[2]),
.I5(xaddr[1]),
.O(\rgb[7]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000007F55))
\rgb[7]_i_6
(.I0(\rgb[15]_i_7_n_0 ),
.I1(xaddr[4]),
.I2(xaddr[5]),
.I3(\rgb[15]_i_5_n_0 ),
.I4(xaddr[7]),
.I5(xaddr[9]),
.O(\rgb[7]_i_6_n_0 ));
FDRE \rgb_reg[13]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[13]_i_1_n_0 ),
.Q(rgb[4]),
.R(1'b0));
FDRE \rgb_reg[14]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[14]_i_1_n_0 ),
.Q(rgb[5]),
.R(1'b0));
FDRE \rgb_reg[15]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[15]_i_1_n_0 ),
.Q(rgb[6]),
.R(1'b0));
FDRE \rgb_reg[21]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[21]_i_1_n_0 ),
.Q(rgb[7]),
.R(1'b0));
FDRE \rgb_reg[22]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[22]_i_1_n_0 ),
.Q(rgb[8]),
.R(1'b0));
FDRE \rgb_reg[23]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[23]_i_1_n_0 ),
.Q(rgb[9]),
.R(1'b0));
FDSE \rgb_reg[4]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[4]_i_1_n_0 ),
.Q(rgb[0]),
.S(\rgb[7]_i_1_n_0 ));
FDSE \rgb_reg[5]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[5]_i_1_n_0 ),
.Q(rgb[1]),
.S(\rgb[7]_i_1_n_0 ));
FDSE \rgb_reg[6]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[6]_i_1_n_0 ),
.Q(rgb[2]),
.S(\rgb[7]_i_1_n_0 ));
FDSE \rgb_reg[7]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[7]_i_2_n_0 ),
.Q(rgb[3]),
.S(\rgb[7]_i_1_n_0 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3B_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NOR3B_BEHAVIORAL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nor3b (
Y ,
A ,
B ,
C_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, C_N, nor0_out );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3B_BEHAVIORAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp0.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp0(/*AUTOARG*/
// Outputs
scan_out, pcx_scache0_data_px_l,
// Inputs
shiftenable, scan_in, rclk, arbpc0_pcxdp_shift_px,
arbpc0_pcxdp_qsel1_pa, arbpc0_pcxdp_qsel0_pa,
arbpc0_pcxdp_q0_hold_pa, arbpc0_pcxdp_grant_pa, spc0_pcx_data_pa,
spc1_pcx_data_pa, spc2_pcx_data_pa, spc3_pcx_data_pa,
spc4_pcx_data_pa, spc5_pcx_data_pa, spc6_pcx_data_pa,
spc7_pcx_data_pa
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [7:0] scan_out; // From mac0 of pcx_dp_maca_r.v, ...
// End of automatics
output [`PCX_WIDTH-1:0] pcx_scache0_data_px_l; // From mac3 of pcx_dp_macc.v
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0] arbpc0_pcxdp_grant_pa; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc0_pcxdp_q0_hold_pa;// To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc0_pcxdp_qsel0_pa; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc0_pcxdp_qsel1_pa; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc0_pcxdp_shift_px; // To mac0 of pcx_dp_maca_r.v, ...
input rclk; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] scan_in; // To mac0 of pcx_dp_maca_r.v, ...
input shiftenable; // To mac7 of pcx_dp_maca_l.v
// End of automatics
input [`PCX_WIDTH-1:0] spc0_pcx_data_pa; // To mac0 of pcx_dp_maca.v
input [`PCX_WIDTH-1:0] spc1_pcx_data_pa; // To mac1 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc2_pcx_data_pa; // To mac2 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc3_pcx_data_pa; // To mac3 of pcx_dp_macc.v
input [`PCX_WIDTH-1:0] spc4_pcx_data_pa; // To mac4 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc5_pcx_data_pa; // To mac5 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc6_pcx_data_pa; // To mac6 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc7_pcx_data_pa; // To mac7 of pcx_dp_maca.v
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [129:0] pcx_col0_data_px_l; // From mac0 of pcx_dp_maca_r.v
wire [129:0] pcx_col1_data_px_l; // From mac1 of pcx_dp_macb_r.v
wire [129:0] pcx_col2_data_px_l; // From mac2 of pcx_dp_macb_r.v
wire [129:0] pcx_col4_data_px_l; // From mac4 of pcx_dp_macb_l.v
wire [129:0] pcx_col5_data_px_l; // From mac5 of pcx_dp_macb_l.v
wire [129:0] pcx_col6_data_px_l; // From mac6 of pcx_dp_macb_l.v
wire [129:0] pcx_col7_data_px_l; // From mac7 of pcx_dp_maca_l.v
wire [7:1] shiftenable_buf; // From mac1 of pcx_dp_macb_r.v, ...
// End of automatics
wire [5:0] unused;
/*
// DATAPATH ORGANISATION(pcx_dp0)
sparc0 sparc1 sparc2 sparc3 sparc4 sparc5 sparc6 sparc7
| | | | | | | |
v v v v v v v v
mac0 -> mac1 ->mac2 ->mac3 <- mac4 <- mac5 <- mac6 <- mac7
(new)ar br br cr bl bl bl al
(old)a b b c b b b a
|
------buf------
|
v
to sctag0
*/
/*
pcx_dp_maca_r AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc0_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_maca_r mac0(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col0_data_px_l[129:0]), // Templated
.scan_out (scan_out[0]), // Templated
.shiftenable_buf (), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[0]), // Templated
.arb_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[0]), // Templated
.arb_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[0]), // Templated
.arb_pcxdp_shift_px(arbpc0_pcxdp_shift_px[0]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[0]), // Templated
.src_pcx_data_pa ({6'b000000,spc0_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.rclk (rclk),
.scan_in (scan_in[0]), // Templated
.shiftenable (shiftenable_buf[1])); // Templated
/*
pcx_dp_macb_r AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc0_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.data_prev_px_l (pcx_col@"(- @ 1)"_data_px_l[129:0]),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_macb_r mac1(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col1_data_px_l[129:0]), // Templated
.scan_out (scan_out[1]), // Templated
.shiftenable_buf (shiftenable_buf[1]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[1]), // Templated
.arb_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[1]), // Templated
.arb_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[1]), // Templated
.arb_pcxdp_shift_px(arbpc0_pcxdp_shift_px[1]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[1]), // Templated
.src_pcx_data_pa ({6'b000000,spc1_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col0_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[1]), // Templated
.shiftenable (shiftenable_buf[2])); // Templated // Templated // Templated // Templated
pcx_dp_macb_r mac2(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col2_data_px_l[129:0]), // Templated
.scan_out (scan_out[2]), // Templated
.shiftenable_buf (shiftenable_buf[2]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[2]), // Templated
.arb_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[2]), // Templated
.arb_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[2]), // Templated
.arb_pcxdp_shift_px(arbpc0_pcxdp_shift_px[2]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[2]), // Templated
.src_pcx_data_pa ({6'b000000,spc2_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col1_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[2]), // Templated
.shiftenable (shiftenable_buf[3])); // Templated
/*
pcx_dp_macc_r AUTO_TEMPLATE(
// Outputs
.data_out_px_l ({unused[5:0],pcx_scache0_data_px_l[`PCX_WIDTH-1:0]}),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc0_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.data_crit_px_l (pcx_col@"(+ @ 1)"_data_px_l[129:0]),
.data_ncrit_px_l(pcx_col@"(- @ 1)"_data_px_l[129:0]),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_macc_r mac3(/*AUTOINST*/
// Outputs
.data_out_px_l ({unused[5:0],pcx_scache0_data_px_l[`PCX_WIDTH-1:0]}), // Templated
.scan_out (scan_out[3]), // Templated
.shiftenable_buf (shiftenable_buf[3]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[3]), // Templated
.arb_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[3]), // Templated
.arb_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[3]), // Templated
.arb_pcxdp_shift_px(arbpc0_pcxdp_shift_px[3]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[3]), // Templated
.src_pcx_data_pa ({6'b000000,spc3_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_crit_px_l (pcx_col4_data_px_l[129:0]), // Templated
.data_ncrit_px_l (pcx_col2_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[3]), // Templated
.shiftenable (shiftenable_buf[4])); // Templated
/*
pcx_dp_macb_l AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc0_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.data_prev_px_l (pcx_col@"(+ @ 1)"_data_px_l[129:0]),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_macb_l mac4(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col4_data_px_l[129:0]), // Templated
.scan_out (scan_out[4]), // Templated
.shiftenable_buf (shiftenable_buf[4]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[4]), // Templated
.arb_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[4]), // Templated
.arb_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[4]), // Templated
.arb_pcxdp_shift_px(arbpc0_pcxdp_shift_px[4]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[4]), // Templated
.src_pcx_data_pa ({6'b000000,spc4_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col5_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[4]), // Templated
.shiftenable (shiftenable_buf[5])); // Templated
pcx_dp_macb_l mac5(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col5_data_px_l[129:0]), // Templated
.scan_out (scan_out[5]), // Templated
.shiftenable_buf (shiftenable_buf[5]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[5]), // Templated
.arb_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[5]), // Templated
.arb_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[5]), // Templated
.arb_pcxdp_shift_px(arbpc0_pcxdp_shift_px[5]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[5]), // Templated
.src_pcx_data_pa ({6'b000000,spc5_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col6_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[5]), // Templated
.shiftenable (shiftenable_buf[6])); // Templated
pcx_dp_macb_l mac6(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col6_data_px_l[129:0]), // Templated
.scan_out (scan_out[6]), // Templated
.shiftenable_buf (shiftenable_buf[6]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[6]), // Templated
.arb_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[6]), // Templated
.arb_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[6]), // Templated
.arb_pcxdp_shift_px(arbpc0_pcxdp_shift_px[6]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[6]), // Templated
.src_pcx_data_pa ({6'b000000,spc6_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col7_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[6]), // Templated
.shiftenable (shiftenable_buf[7])); // Templated
/*
pcx_dp_maca_l AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc0_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable));
*/
pcx_dp_maca_l mac7(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col7_data_px_l[129:0]), // Templated
.scan_out (scan_out[7]), // Templated
.shiftenable_buf (shiftenable_buf[7]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[7]), // Templated
.arb_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[7]), // Templated
.arb_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[7]), // Templated
.arb_pcxdp_shift_px(arbpc0_pcxdp_shift_px[7]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[7]), // Templated
.src_pcx_data_pa ({6'b000000,spc7_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.rclk (rclk),
.scan_in (scan_in[7]), // Templated
.shiftenable (shiftenable)); // Templated
// Code start here
//
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl")
// End:
endmodule
|
`include "simulation_includes.vh"
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07/31/2015 10:08:26 PM
// Design Name:
// Module Name: testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "timescale.v"
module soc_testbench;
`include "test_management.v"
reg [31:0] read_word;
//
// Display
//
wire [3:0] anode; // From dut of display.v
wire [7:0] cathode; // From dut of display.v
wire [15:0] leds;
reg [15:0] switches_reg = 16'h0000;
wire [15:0] switches = switches_reg;
reg [3:0] push_buttons_regs = 4'h0;
wire [3:0] push_buttons = push_buttons_regs;
wire sck_o;
wire ncs_o;
wire mosi_o;
wire miso_i;
wire wb_clk = clk;
wire wb_rst = reset;
soc dut(
// Outputs
.leds(leds),
.TX(TX),
.anode(anode),
.cathode(cathode),
.sck_o(sck_o),
.ncs_o(ncs_o),
.mosi_o(mosi_o),
// Inputs
.miso_i(miso_i),
.int1(int1),
.int2(int2),
.clk_in(clk),
.reset_in(reset),
.switches(switches),
.push_buttons(push_buttons),
.RX(1'b0)
);
/****************************************************************************
UART 0
The WB UART16550 from opencores is used here to simulate a UART on the other end
of the cable. It will allow us to send/receive characters to the NGMCU firmware
***************************************************************************/
wire [31:0] uart0_adr;
wire [31:0] uart0_dat_o;
wire [31:0] uart0_dat_i;
wire [3:0] uart0_sel;
wire uart0_cyc;
wire uart0_stb;
wire uart0_we;
wire uart0_ack;
wire uart0_int;
assign uart0_dat_o[31:8] = 'b0;
uart_top uart0(
.wb_clk_i(clk),
.wb_rst_i(reset),
.wb_adr_i(uart0_adr[4:0]),
.wb_dat_o(uart0_dat_o),
.wb_dat_i(uart0_dat_i),
.wb_sel_i(uart0_sel),
.wb_cyc_i(uart0_cyc),
.wb_stb_i(uart0_stb),
.wb_we_i(uart0_we),
.wb_ack_o(uart0_ack),
.int_o(uart0_int),
.stx_pad_o(RX),
.srx_pad_i(TX),
.rts_pad_o(),
.cts_pad_i(1'b0),
.dtr_pad_o(),
.dsr_pad_i(1'b0),
.ri_pad_i(1'b0),
.dcd_pad_i(1'b0),
.baud_o()
);
wb_mast uart_master0(
.clk (clk),
.rst (reset),
.adr (uart0_adr),
.din (uart0_dat_o),
.dout(uart0_dat_i),
.cyc (uart0_cyc),
.stb (uart0_stb),
.sel (uart0_sel),
.we (uart0_we ),
.ack (uart0_ack),
.err (1'b0),
.rty (1'b0)
);
uart_tasks uart_tasks();
/****************************************************************************
ADXL362 SPI Accelerometer
***************************************************************************/
adxl362 adxl362(
.SCLK(sck_o),
.MOSI(mosi_o),
.nCS(ncs_o),
.MISO(miso_i),
.INT1(int1),
.INT2(int2)
);
/****************************************************************************
TEST SUPPORT
***************************************************************************/
glbl glbl();
//
// Tasks used to interface with ADXL362
//
spi_tasks spi_tasks();
//
// Tasks used to help test cases
//
test_tasks test_tasks();
//
// The actual test cases that are being tested
//
test_case test_case();
initial begin
@(posedge reset);
@(negedge reset);
#100;
`UART_CONFIG;
end // initial begin
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_2_V
`define SKY130_FD_SC_LP__CLKINV_2_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_2_V
|
module tty(
input wire clk,
input wire reset,
/* IO bus */
input wire iobus_iob_poweron,
input wire iobus_iob_reset,
input wire iobus_datao_clear,
input wire iobus_datao_set,
input wire iobus_cono_clear,
input wire iobus_cono_set,
input wire iobus_iob_fm_datai,
input wire iobus_iob_fm_status,
input wire iobus_rdi_pulse, // unused on 6
input wire [3:9] iobus_ios,
input wire [0:35] iobus_iob_in,
output wire [1:7] iobus_pi_req,
output wire [0:35] iobus_iob_out,
output wire iobus_dr_split,
output wire iobus_rdi_data, // unused on 6
/* UART pins */
input wire rx,
output wire tx,
/* Panel */
output wire [7:0] tti_ind,
output wire [6:0] status_ind
);
assign iobus_dr_split = 0;
assign iobus_rdi_data = 0;
wire clk2;
clk14khz clock2(.inclk(clk),
.outclk(clk2));
wire tti_clock, tto_clock;
clk16div ttidiv(.clk(clk),
.inclk(clk2),
.outclk(tti_clock));
clk4div ttodiv(.clk(clk),
.inclk(tti_clock),
.outclk(tto_clock));
wire tty_sel = iobus_ios == 7'b001_010_0;
wire tty_data_clr;
wire tty_data_set;
wire tty_ic_clr;
wire tty_ic_set;
wire tty_reset;
wire tty_datai = tty_sel & iobus_iob_fm_datai;
wire tty_status = tty_sel & iobus_iob_fm_status;
pg tty_pg0(.clk(clk), .reset(reset),
.in(tty_sel & iobus_datao_clear),
.p(tty_data_clr));
pg tty_pg1(.clk(clk), .reset(reset),
.in(tty_sel & iobus_datao_set),
.p(tty_data_set));
pg tty_pg2(.clk(clk), .reset(reset),
.in(tty_sel & iobus_cono_clear | iobus_iob_reset),
.p(tty_ic_clr));
pg tty_pg3(.clk(clk), .reset(reset),
.in(tty_sel & iobus_cono_set),
.p(tty_ic_set));
pg tty_pg4(.clk(clk), .reset(reset),
.in(iobus_iob_reset),
.p(tty_reset));
assign iobus_iob_out =
tty_datai ? { 28'b0, tti_ind } :
tty_status ? { 29'b0, tti_busy, tti_flag, tto_busy, tto_flag, tty_pia } :
36'b0;
wire [0:7] tty_req = { tti_flag | tto_flag, 7'b0 } >> tty_pia;
assign iobus_pi_req = tty_req[1:7];
reg [33:35] tty_pia = 0;
reg tti_busy = 0;
reg tti_flag = 0;
reg tto_busy = 0;
reg tto_flag = 0;
wire tto_done;
reg tto_done0;
wire tti_done;
reg tti_done0;
wire tti_active;
reg tti_active0;
assign status_ind = { tti_busy, tti_flag, tto_busy, tto_flag, tty_pia };
always @(posedge clk) begin
tti_done0 <= tti_done;
tto_done0 <= tto_done;
tti_active0 <= tti_active;
if(tty_ic_clr)
tty_pia <= 0;
if(tty_reset) begin
tto_busy <= 0;
tto_flag <= 0;
tti_busy <= 0;
tti_flag <= 0;
end
if(tty_ic_set) begin
tty_pia <= iobus_iob_in[33:35];
if(iobus_iob_in[25])
tti_busy <= 0;
if(iobus_iob_in[26])
tti_flag <= 0;
if(iobus_iob_in[27])
tto_busy <= 0;
if(iobus_iob_in[28])
tto_flag <= 0;
if(iobus_iob_in[29])
tti_busy <= 1;
if(iobus_iob_in[30])
tti_flag <= 1;
if(iobus_iob_in[31])
tto_busy <= 1;
if(iobus_iob_in[32])
tto_flag <= 1;
end
if(tty_data_clr) begin
tto_flag <= 0;
tto_busy <= 1;
end
if(~tto_done0 & tto_done) begin
tto_flag <= 1;
tto_busy <= 0;
end
if(tty_datai)
tti_flag <= 0;
if(~tti_active0 & tti_active)
tti_busy <= 1;
if(~tti_done0 & tti_done) begin
tti_flag <= 1;
tti_busy <= 0;
end
end
wire [8:1] iob;
tti tti0(.clk(clk),
.tti_clock(tti_clock),
.rx(rx),
.iob(iob),
.tti_active(tti_active),
.tti_done(tti_done),
.tti(tti_ind));
tto tto0(.clk(clk),
.tto_clock(tto_clock),
.iob(iobus_iob_in[28:35]),
.tty_data_clr(tty_data_clr),
.tty_data_set(tty_data_set),
.tx(tx),
.tto_done(tto_done));
endmodule
module tto(input wire clk,
input wire tto_clock,
input wire [8:1] iob,
input wire tty_data_clr,
input wire tty_data_set,
output wire tx,
output reg tto_done = 0
);
reg [8:1] tto;
reg tto_out_line;
reg tto_enable = 0;
reg tto_active = 0;
reg tto_active0;
reg tto_div2 = 0;
reg tto_div20;
wire tto_4count;
wire tto_shift = tto_div20 & ~tto_div2;
count4 c(.clk(clk),
.reset(tto_active0 & ~tto_active),
.enable(tto_clock),
.out(tto_4count));
always @(posedge clk) begin
tto_active0 <= tto_active;
tto_div20 <= tto_div2;
if(tty_data_clr) begin
tto_done <= 0;
end
if(tty_data_set) begin
tto <= iob;
tto_enable <= 1;
end
if(tto_clock) begin
if(tto_active)
tto_div2 <= ~tto_div2;
if(tto_4count & tto_enable)
tto_active <= 1;
end
if(tto_shift) begin
tto_enable <= 0;
{ tto, tto_out_line } <= { tto_enable, tto };
if(~tto_enable & tto[8:2] == 0) begin
tto_active <= 0;
tto_done <= 1;
end
end
if(~tto_active)
tto_out_line <= 1;
else
if(~tto_active0)
tto_out_line <= 0;
end
assign tx = tto_out_line;
endmodule
module tti(input wire clk,
input wire tti_clock,
input wire rx,
output wire [8:1] iob,
output reg tti_active = 0,
output reg tti_done = 0,
output reg [8:1] tti = 0
);
assign iob = tti;
wire tti_shift = tti_4count_rise & ~tti_last_unit;
reg tti_last_unit = 0;
reg tti_active0;
wire tti_4count;
reg tti_4count0;
wire tti_space = ~rx;
wire tti_4count_rise = ~tti_4count0 & tti_4count;
wire tti_set = ~tti_active0 & tti_active;
div8 d(.clk(clk),
.reset(tti_set),
.enable(tti_clock & tti_active),
.out(tti_4count));
always @(posedge clk) begin
tti_4count0 <= tti_4count;
tti_active0 <= tti_active;
if(tti_set) begin
tti <= 8'o377;
tti_last_unit <= 0;
end
if(tti_4count_rise & tti_last_unit)
tti_active <= 0;
if(tti_shift) begin
tti <= { rx, tti[8:2] };
if(~tti[1]) begin
tti_last_unit <= 1;
tti_done <= 1;
end
if(tti[1])
tti_done <= 0;
if(~tti_space & (& tti))
tti_active <= 0;
end
if(tti_clock)
if(~tti_active & tti_space)
tti_active <= 1;
end
endmodule
module clk14khz(input wire inclk,
output wire outclk);
reg [11:0] cnt = 0;
assign outclk = cnt == 3551;
always @(posedge inclk)
if(outclk)
cnt <= 0;
else
cnt <= cnt + 12'b1;
endmodule
module clk16div(input wire clk,
input wire inclk,
output wire outclk
);
reg [4:0] cnt = 0;
assign outclk = cnt == 16;
always @(posedge clk)
if(outclk)
cnt <= 0;
else if(inclk)
cnt <= cnt + 5'b1;
endmodule
module div8(
input wire clk,
input wire reset,
input wire enable,
output wire out
);
reg [2:0] cnt = 4;
always @(posedge clk)
if(reset)
cnt <= 0;
else if(enable)
cnt <= cnt + 3'b1;
assign out = cnt[2];
endmodule
module count4(
input wire clk,
input wire reset,
input wire enable,
output wire out
);
reg [1:0] cnt = 0;
always @(posedge clk)
if(reset)
cnt <= 0;
else if(enable && cnt != 3)
cnt <= cnt + 2'b1;
assign out = cnt == 3;
endmodule
module clk4div(input wire clk,
input wire inclk,
output wire outclk
);
reg [2:0] cnt = 0;
assign outclk = cnt == 4;
always @(posedge clk)
if(outclk)
cnt <= 0;
else if(inclk)
cnt <= cnt + 3'b1;
endmodule
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1
// RDY_set_verbosity O 1 const
// v_from_masters_0_awready O 1 reg
// v_from_masters_0_wready O 1 reg
// v_from_masters_0_bvalid O 1 reg
// v_from_masters_0_bid O 16 reg
// v_from_masters_0_bresp O 2 reg
// v_from_masters_0_arready O 1 reg
// v_from_masters_0_rvalid O 1 reg
// v_from_masters_0_rid O 16 reg
// v_from_masters_0_rdata O 64 reg
// v_from_masters_0_rresp O 2 reg
// v_from_masters_0_rlast O 1 reg
// v_from_masters_1_awready O 1 reg
// v_from_masters_1_wready O 1 reg
// v_from_masters_1_bvalid O 1 reg
// v_from_masters_1_bid O 16 reg
// v_from_masters_1_bresp O 2 reg
// v_from_masters_1_arready O 1 reg
// v_from_masters_1_rvalid O 1 reg
// v_from_masters_1_rid O 16 reg
// v_from_masters_1_rdata O 64 reg
// v_from_masters_1_rresp O 2 reg
// v_from_masters_1_rlast O 1 reg
// v_to_slaves_0_awvalid O 1 reg
// v_to_slaves_0_awid O 16 reg
// v_to_slaves_0_awaddr O 64 reg
// v_to_slaves_0_awlen O 8 reg
// v_to_slaves_0_awsize O 3 reg
// v_to_slaves_0_awburst O 2 reg
// v_to_slaves_0_awlock O 1 reg
// v_to_slaves_0_awcache O 4 reg
// v_to_slaves_0_awprot O 3 reg
// v_to_slaves_0_awqos O 4 reg
// v_to_slaves_0_awregion O 4 reg
// v_to_slaves_0_wvalid O 1 reg
// v_to_slaves_0_wdata O 64 reg
// v_to_slaves_0_wstrb O 8 reg
// v_to_slaves_0_wlast O 1 reg
// v_to_slaves_0_bready O 1 reg
// v_to_slaves_0_arvalid O 1 reg
// v_to_slaves_0_arid O 16 reg
// v_to_slaves_0_araddr O 64 reg
// v_to_slaves_0_arlen O 8 reg
// v_to_slaves_0_arsize O 3 reg
// v_to_slaves_0_arburst O 2 reg
// v_to_slaves_0_arlock O 1 reg
// v_to_slaves_0_arcache O 4 reg
// v_to_slaves_0_arprot O 3 reg
// v_to_slaves_0_arqos O 4 reg
// v_to_slaves_0_arregion O 4 reg
// v_to_slaves_0_rready O 1 reg
// v_to_slaves_1_awvalid O 1 reg
// v_to_slaves_1_awid O 16 reg
// v_to_slaves_1_awaddr O 64 reg
// v_to_slaves_1_awlen O 8 reg
// v_to_slaves_1_awsize O 3 reg
// v_to_slaves_1_awburst O 2 reg
// v_to_slaves_1_awlock O 1 reg
// v_to_slaves_1_awcache O 4 reg
// v_to_slaves_1_awprot O 3 reg
// v_to_slaves_1_awqos O 4 reg
// v_to_slaves_1_awregion O 4 reg
// v_to_slaves_1_wvalid O 1 reg
// v_to_slaves_1_wdata O 64 reg
// v_to_slaves_1_wstrb O 8 reg
// v_to_slaves_1_wlast O 1 reg
// v_to_slaves_1_bready O 1 reg
// v_to_slaves_1_arvalid O 1 reg
// v_to_slaves_1_arid O 16 reg
// v_to_slaves_1_araddr O 64 reg
// v_to_slaves_1_arlen O 8 reg
// v_to_slaves_1_arsize O 3 reg
// v_to_slaves_1_arburst O 2 reg
// v_to_slaves_1_arlock O 1 reg
// v_to_slaves_1_arcache O 4 reg
// v_to_slaves_1_arprot O 3 reg
// v_to_slaves_1_arqos O 4 reg
// v_to_slaves_1_arregion O 4 reg
// v_to_slaves_1_rready O 1 reg
// v_to_slaves_2_awvalid O 1 reg
// v_to_slaves_2_awid O 16 reg
// v_to_slaves_2_awaddr O 64 reg
// v_to_slaves_2_awlen O 8 reg
// v_to_slaves_2_awsize O 3 reg
// v_to_slaves_2_awburst O 2 reg
// v_to_slaves_2_awlock O 1 reg
// v_to_slaves_2_awcache O 4 reg
// v_to_slaves_2_awprot O 3 reg
// v_to_slaves_2_awqos O 4 reg
// v_to_slaves_2_awregion O 4 reg
// v_to_slaves_2_wvalid O 1 reg
// v_to_slaves_2_wdata O 64 reg
// v_to_slaves_2_wstrb O 8 reg
// v_to_slaves_2_wlast O 1 reg
// v_to_slaves_2_bready O 1 reg
// v_to_slaves_2_arvalid O 1 reg
// v_to_slaves_2_arid O 16 reg
// v_to_slaves_2_araddr O 64 reg
// v_to_slaves_2_arlen O 8 reg
// v_to_slaves_2_arsize O 3 reg
// v_to_slaves_2_arburst O 2 reg
// v_to_slaves_2_arlock O 1 reg
// v_to_slaves_2_arcache O 4 reg
// v_to_slaves_2_arprot O 3 reg
// v_to_slaves_2_arqos O 4 reg
// v_to_slaves_2_arregion O 4 reg
// v_to_slaves_2_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// v_from_masters_0_awvalid I 1
// v_from_masters_0_awid I 16 reg
// v_from_masters_0_awaddr I 64 reg
// v_from_masters_0_awlen I 8 reg
// v_from_masters_0_awsize I 3 reg
// v_from_masters_0_awburst I 2 reg
// v_from_masters_0_awlock I 1 reg
// v_from_masters_0_awcache I 4 reg
// v_from_masters_0_awprot I 3 reg
// v_from_masters_0_awqos I 4 reg
// v_from_masters_0_awregion I 4 reg
// v_from_masters_0_wvalid I 1
// v_from_masters_0_wdata I 64 reg
// v_from_masters_0_wstrb I 8 reg
// v_from_masters_0_wlast I 1 reg
// v_from_masters_0_bready I 1
// v_from_masters_0_arvalid I 1
// v_from_masters_0_arid I 16 reg
// v_from_masters_0_araddr I 64 reg
// v_from_masters_0_arlen I 8 reg
// v_from_masters_0_arsize I 3 reg
// v_from_masters_0_arburst I 2 reg
// v_from_masters_0_arlock I 1 reg
// v_from_masters_0_arcache I 4 reg
// v_from_masters_0_arprot I 3 reg
// v_from_masters_0_arqos I 4 reg
// v_from_masters_0_arregion I 4 reg
// v_from_masters_0_rready I 1
// v_from_masters_1_awvalid I 1
// v_from_masters_1_awid I 16 reg
// v_from_masters_1_awaddr I 64 reg
// v_from_masters_1_awlen I 8 reg
// v_from_masters_1_awsize I 3 reg
// v_from_masters_1_awburst I 2 reg
// v_from_masters_1_awlock I 1 reg
// v_from_masters_1_awcache I 4 reg
// v_from_masters_1_awprot I 3 reg
// v_from_masters_1_awqos I 4 reg
// v_from_masters_1_awregion I 4 reg
// v_from_masters_1_wvalid I 1
// v_from_masters_1_wdata I 64 reg
// v_from_masters_1_wstrb I 8 reg
// v_from_masters_1_wlast I 1 reg
// v_from_masters_1_bready I 1
// v_from_masters_1_arvalid I 1
// v_from_masters_1_arid I 16 reg
// v_from_masters_1_araddr I 64 reg
// v_from_masters_1_arlen I 8 reg
// v_from_masters_1_arsize I 3 reg
// v_from_masters_1_arburst I 2 reg
// v_from_masters_1_arlock I 1 reg
// v_from_masters_1_arcache I 4 reg
// v_from_masters_1_arprot I 3 reg
// v_from_masters_1_arqos I 4 reg
// v_from_masters_1_arregion I 4 reg
// v_from_masters_1_rready I 1
// v_to_slaves_0_awready I 1
// v_to_slaves_0_wready I 1
// v_to_slaves_0_bvalid I 1
// v_to_slaves_0_bid I 16 reg
// v_to_slaves_0_bresp I 2 reg
// v_to_slaves_0_arready I 1
// v_to_slaves_0_rvalid I 1
// v_to_slaves_0_rid I 16 reg
// v_to_slaves_0_rdata I 64 reg
// v_to_slaves_0_rresp I 2 reg
// v_to_slaves_0_rlast I 1 reg
// v_to_slaves_1_awready I 1
// v_to_slaves_1_wready I 1
// v_to_slaves_1_bvalid I 1
// v_to_slaves_1_bid I 16 reg
// v_to_slaves_1_bresp I 2 reg
// v_to_slaves_1_arready I 1
// v_to_slaves_1_rvalid I 1
// v_to_slaves_1_rid I 16 reg
// v_to_slaves_1_rdata I 64 reg
// v_to_slaves_1_rresp I 2 reg
// v_to_slaves_1_rlast I 1 reg
// v_to_slaves_2_awready I 1
// v_to_slaves_2_wready I 1
// v_to_slaves_2_bvalid I 1
// v_to_slaves_2_bid I 16 reg
// v_to_slaves_2_bresp I 2 reg
// v_to_slaves_2_arready I 1
// v_to_slaves_2_rvalid I 1
// v_to_slaves_2_rid I 16 reg
// v_to_slaves_2_rdata I 64 reg
// v_to_slaves_2_rresp I 2 reg
// v_to_slaves_2_rlast I 1 reg
// EN_reset I 1
// EN_set_verbosity I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFabric_AXI4(CLK,
RST_N,
EN_reset,
RDY_reset,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
v_from_masters_0_awvalid,
v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion,
v_from_masters_0_awready,
v_from_masters_0_wvalid,
v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast,
v_from_masters_0_wready,
v_from_masters_0_bvalid,
v_from_masters_0_bid,
v_from_masters_0_bresp,
v_from_masters_0_bready,
v_from_masters_0_arvalid,
v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion,
v_from_masters_0_arready,
v_from_masters_0_rvalid,
v_from_masters_0_rid,
v_from_masters_0_rdata,
v_from_masters_0_rresp,
v_from_masters_0_rlast,
v_from_masters_0_rready,
v_from_masters_1_awvalid,
v_from_masters_1_awid,
v_from_masters_1_awaddr,
v_from_masters_1_awlen,
v_from_masters_1_awsize,
v_from_masters_1_awburst,
v_from_masters_1_awlock,
v_from_masters_1_awcache,
v_from_masters_1_awprot,
v_from_masters_1_awqos,
v_from_masters_1_awregion,
v_from_masters_1_awready,
v_from_masters_1_wvalid,
v_from_masters_1_wdata,
v_from_masters_1_wstrb,
v_from_masters_1_wlast,
v_from_masters_1_wready,
v_from_masters_1_bvalid,
v_from_masters_1_bid,
v_from_masters_1_bresp,
v_from_masters_1_bready,
v_from_masters_1_arvalid,
v_from_masters_1_arid,
v_from_masters_1_araddr,
v_from_masters_1_arlen,
v_from_masters_1_arsize,
v_from_masters_1_arburst,
v_from_masters_1_arlock,
v_from_masters_1_arcache,
v_from_masters_1_arprot,
v_from_masters_1_arqos,
v_from_masters_1_arregion,
v_from_masters_1_arready,
v_from_masters_1_rvalid,
v_from_masters_1_rid,
v_from_masters_1_rdata,
v_from_masters_1_rresp,
v_from_masters_1_rlast,
v_from_masters_1_rready,
v_to_slaves_0_awvalid,
v_to_slaves_0_awid,
v_to_slaves_0_awaddr,
v_to_slaves_0_awlen,
v_to_slaves_0_awsize,
v_to_slaves_0_awburst,
v_to_slaves_0_awlock,
v_to_slaves_0_awcache,
v_to_slaves_0_awprot,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_0_awready,
v_to_slaves_0_wvalid,
v_to_slaves_0_wdata,
v_to_slaves_0_wstrb,
v_to_slaves_0_wlast,
v_to_slaves_0_wready,
v_to_slaves_0_bvalid,
v_to_slaves_0_bid,
v_to_slaves_0_bresp,
v_to_slaves_0_bready,
v_to_slaves_0_arvalid,
v_to_slaves_0_arid,
v_to_slaves_0_araddr,
v_to_slaves_0_arlen,
v_to_slaves_0_arsize,
v_to_slaves_0_arburst,
v_to_slaves_0_arlock,
v_to_slaves_0_arcache,
v_to_slaves_0_arprot,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_arready,
v_to_slaves_0_rvalid,
v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast,
v_to_slaves_0_rready,
v_to_slaves_1_awvalid,
v_to_slaves_1_awid,
v_to_slaves_1_awaddr,
v_to_slaves_1_awlen,
v_to_slaves_1_awsize,
v_to_slaves_1_awburst,
v_to_slaves_1_awlock,
v_to_slaves_1_awcache,
v_to_slaves_1_awprot,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_1_awready,
v_to_slaves_1_wvalid,
v_to_slaves_1_wdata,
v_to_slaves_1_wstrb,
v_to_slaves_1_wlast,
v_to_slaves_1_wready,
v_to_slaves_1_bvalid,
v_to_slaves_1_bid,
v_to_slaves_1_bresp,
v_to_slaves_1_bready,
v_to_slaves_1_arvalid,
v_to_slaves_1_arid,
v_to_slaves_1_araddr,
v_to_slaves_1_arlen,
v_to_slaves_1_arsize,
v_to_slaves_1_arburst,
v_to_slaves_1_arlock,
v_to_slaves_1_arcache,
v_to_slaves_1_arprot,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_arready,
v_to_slaves_1_rvalid,
v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast,
v_to_slaves_1_rready,
v_to_slaves_2_awvalid,
v_to_slaves_2_awid,
v_to_slaves_2_awaddr,
v_to_slaves_2_awlen,
v_to_slaves_2_awsize,
v_to_slaves_2_awburst,
v_to_slaves_2_awlock,
v_to_slaves_2_awcache,
v_to_slaves_2_awprot,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion,
v_to_slaves_2_awready,
v_to_slaves_2_wvalid,
v_to_slaves_2_wdata,
v_to_slaves_2_wstrb,
v_to_slaves_2_wlast,
v_to_slaves_2_wready,
v_to_slaves_2_bvalid,
v_to_slaves_2_bid,
v_to_slaves_2_bresp,
v_to_slaves_2_bready,
v_to_slaves_2_arvalid,
v_to_slaves_2_arid,
v_to_slaves_2_araddr,
v_to_slaves_2_arlen,
v_to_slaves_2_arsize,
v_to_slaves_2_arburst,
v_to_slaves_2_arlock,
v_to_slaves_2_arcache,
v_to_slaves_2_arprot,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_arready,
v_to_slaves_2_rvalid,
v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast,
v_to_slaves_2_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method v_from_masters_0_m_awvalid
input v_from_masters_0_awvalid;
input [15 : 0] v_from_masters_0_awid;
input [63 : 0] v_from_masters_0_awaddr;
input [7 : 0] v_from_masters_0_awlen;
input [2 : 0] v_from_masters_0_awsize;
input [1 : 0] v_from_masters_0_awburst;
input v_from_masters_0_awlock;
input [3 : 0] v_from_masters_0_awcache;
input [2 : 0] v_from_masters_0_awprot;
input [3 : 0] v_from_masters_0_awqos;
input [3 : 0] v_from_masters_0_awregion;
// value method v_from_masters_0_m_awready
output v_from_masters_0_awready;
// action method v_from_masters_0_m_wvalid
input v_from_masters_0_wvalid;
input [63 : 0] v_from_masters_0_wdata;
input [7 : 0] v_from_masters_0_wstrb;
input v_from_masters_0_wlast;
// value method v_from_masters_0_m_wready
output v_from_masters_0_wready;
// value method v_from_masters_0_m_bvalid
output v_from_masters_0_bvalid;
// value method v_from_masters_0_m_bid
output [15 : 0] v_from_masters_0_bid;
// value method v_from_masters_0_m_bresp
output [1 : 0] v_from_masters_0_bresp;
// value method v_from_masters_0_m_buser
// action method v_from_masters_0_m_bready
input v_from_masters_0_bready;
// action method v_from_masters_0_m_arvalid
input v_from_masters_0_arvalid;
input [15 : 0] v_from_masters_0_arid;
input [63 : 0] v_from_masters_0_araddr;
input [7 : 0] v_from_masters_0_arlen;
input [2 : 0] v_from_masters_0_arsize;
input [1 : 0] v_from_masters_0_arburst;
input v_from_masters_0_arlock;
input [3 : 0] v_from_masters_0_arcache;
input [2 : 0] v_from_masters_0_arprot;
input [3 : 0] v_from_masters_0_arqos;
input [3 : 0] v_from_masters_0_arregion;
// value method v_from_masters_0_m_arready
output v_from_masters_0_arready;
// value method v_from_masters_0_m_rvalid
output v_from_masters_0_rvalid;
// value method v_from_masters_0_m_rid
output [15 : 0] v_from_masters_0_rid;
// value method v_from_masters_0_m_rdata
output [63 : 0] v_from_masters_0_rdata;
// value method v_from_masters_0_m_rresp
output [1 : 0] v_from_masters_0_rresp;
// value method v_from_masters_0_m_rlast
output v_from_masters_0_rlast;
// value method v_from_masters_0_m_ruser
// action method v_from_masters_0_m_rready
input v_from_masters_0_rready;
// action method v_from_masters_1_m_awvalid
input v_from_masters_1_awvalid;
input [15 : 0] v_from_masters_1_awid;
input [63 : 0] v_from_masters_1_awaddr;
input [7 : 0] v_from_masters_1_awlen;
input [2 : 0] v_from_masters_1_awsize;
input [1 : 0] v_from_masters_1_awburst;
input v_from_masters_1_awlock;
input [3 : 0] v_from_masters_1_awcache;
input [2 : 0] v_from_masters_1_awprot;
input [3 : 0] v_from_masters_1_awqos;
input [3 : 0] v_from_masters_1_awregion;
// value method v_from_masters_1_m_awready
output v_from_masters_1_awready;
// action method v_from_masters_1_m_wvalid
input v_from_masters_1_wvalid;
input [63 : 0] v_from_masters_1_wdata;
input [7 : 0] v_from_masters_1_wstrb;
input v_from_masters_1_wlast;
// value method v_from_masters_1_m_wready
output v_from_masters_1_wready;
// value method v_from_masters_1_m_bvalid
output v_from_masters_1_bvalid;
// value method v_from_masters_1_m_bid
output [15 : 0] v_from_masters_1_bid;
// value method v_from_masters_1_m_bresp
output [1 : 0] v_from_masters_1_bresp;
// value method v_from_masters_1_m_buser
// action method v_from_masters_1_m_bready
input v_from_masters_1_bready;
// action method v_from_masters_1_m_arvalid
input v_from_masters_1_arvalid;
input [15 : 0] v_from_masters_1_arid;
input [63 : 0] v_from_masters_1_araddr;
input [7 : 0] v_from_masters_1_arlen;
input [2 : 0] v_from_masters_1_arsize;
input [1 : 0] v_from_masters_1_arburst;
input v_from_masters_1_arlock;
input [3 : 0] v_from_masters_1_arcache;
input [2 : 0] v_from_masters_1_arprot;
input [3 : 0] v_from_masters_1_arqos;
input [3 : 0] v_from_masters_1_arregion;
// value method v_from_masters_1_m_arready
output v_from_masters_1_arready;
// value method v_from_masters_1_m_rvalid
output v_from_masters_1_rvalid;
// value method v_from_masters_1_m_rid
output [15 : 0] v_from_masters_1_rid;
// value method v_from_masters_1_m_rdata
output [63 : 0] v_from_masters_1_rdata;
// value method v_from_masters_1_m_rresp
output [1 : 0] v_from_masters_1_rresp;
// value method v_from_masters_1_m_rlast
output v_from_masters_1_rlast;
// value method v_from_masters_1_m_ruser
// action method v_from_masters_1_m_rready
input v_from_masters_1_rready;
// value method v_to_slaves_0_m_awvalid
output v_to_slaves_0_awvalid;
// value method v_to_slaves_0_m_awid
output [15 : 0] v_to_slaves_0_awid;
// value method v_to_slaves_0_m_awaddr
output [63 : 0] v_to_slaves_0_awaddr;
// value method v_to_slaves_0_m_awlen
output [7 : 0] v_to_slaves_0_awlen;
// value method v_to_slaves_0_m_awsize
output [2 : 0] v_to_slaves_0_awsize;
// value method v_to_slaves_0_m_awburst
output [1 : 0] v_to_slaves_0_awburst;
// value method v_to_slaves_0_m_awlock
output v_to_slaves_0_awlock;
// value method v_to_slaves_0_m_awcache
output [3 : 0] v_to_slaves_0_awcache;
// value method v_to_slaves_0_m_awprot
output [2 : 0] v_to_slaves_0_awprot;
// value method v_to_slaves_0_m_awqos
output [3 : 0] v_to_slaves_0_awqos;
// value method v_to_slaves_0_m_awregion
output [3 : 0] v_to_slaves_0_awregion;
// value method v_to_slaves_0_m_awuser
// action method v_to_slaves_0_m_awready
input v_to_slaves_0_awready;
// value method v_to_slaves_0_m_wvalid
output v_to_slaves_0_wvalid;
// value method v_to_slaves_0_m_wdata
output [63 : 0] v_to_slaves_0_wdata;
// value method v_to_slaves_0_m_wstrb
output [7 : 0] v_to_slaves_0_wstrb;
// value method v_to_slaves_0_m_wlast
output v_to_slaves_0_wlast;
// value method v_to_slaves_0_m_wuser
// action method v_to_slaves_0_m_wready
input v_to_slaves_0_wready;
// action method v_to_slaves_0_m_bvalid
input v_to_slaves_0_bvalid;
input [15 : 0] v_to_slaves_0_bid;
input [1 : 0] v_to_slaves_0_bresp;
// value method v_to_slaves_0_m_bready
output v_to_slaves_0_bready;
// value method v_to_slaves_0_m_arvalid
output v_to_slaves_0_arvalid;
// value method v_to_slaves_0_m_arid
output [15 : 0] v_to_slaves_0_arid;
// value method v_to_slaves_0_m_araddr
output [63 : 0] v_to_slaves_0_araddr;
// value method v_to_slaves_0_m_arlen
output [7 : 0] v_to_slaves_0_arlen;
// value method v_to_slaves_0_m_arsize
output [2 : 0] v_to_slaves_0_arsize;
// value method v_to_slaves_0_m_arburst
output [1 : 0] v_to_slaves_0_arburst;
// value method v_to_slaves_0_m_arlock
output v_to_slaves_0_arlock;
// value method v_to_slaves_0_m_arcache
output [3 : 0] v_to_slaves_0_arcache;
// value method v_to_slaves_0_m_arprot
output [2 : 0] v_to_slaves_0_arprot;
// value method v_to_slaves_0_m_arqos
output [3 : 0] v_to_slaves_0_arqos;
// value method v_to_slaves_0_m_arregion
output [3 : 0] v_to_slaves_0_arregion;
// value method v_to_slaves_0_m_aruser
// action method v_to_slaves_0_m_arready
input v_to_slaves_0_arready;
// action method v_to_slaves_0_m_rvalid
input v_to_slaves_0_rvalid;
input [15 : 0] v_to_slaves_0_rid;
input [63 : 0] v_to_slaves_0_rdata;
input [1 : 0] v_to_slaves_0_rresp;
input v_to_slaves_0_rlast;
// value method v_to_slaves_0_m_rready
output v_to_slaves_0_rready;
// value method v_to_slaves_1_m_awvalid
output v_to_slaves_1_awvalid;
// value method v_to_slaves_1_m_awid
output [15 : 0] v_to_slaves_1_awid;
// value method v_to_slaves_1_m_awaddr
output [63 : 0] v_to_slaves_1_awaddr;
// value method v_to_slaves_1_m_awlen
output [7 : 0] v_to_slaves_1_awlen;
// value method v_to_slaves_1_m_awsize
output [2 : 0] v_to_slaves_1_awsize;
// value method v_to_slaves_1_m_awburst
output [1 : 0] v_to_slaves_1_awburst;
// value method v_to_slaves_1_m_awlock
output v_to_slaves_1_awlock;
// value method v_to_slaves_1_m_awcache
output [3 : 0] v_to_slaves_1_awcache;
// value method v_to_slaves_1_m_awprot
output [2 : 0] v_to_slaves_1_awprot;
// value method v_to_slaves_1_m_awqos
output [3 : 0] v_to_slaves_1_awqos;
// value method v_to_slaves_1_m_awregion
output [3 : 0] v_to_slaves_1_awregion;
// value method v_to_slaves_1_m_awuser
// action method v_to_slaves_1_m_awready
input v_to_slaves_1_awready;
// value method v_to_slaves_1_m_wvalid
output v_to_slaves_1_wvalid;
// value method v_to_slaves_1_m_wdata
output [63 : 0] v_to_slaves_1_wdata;
// value method v_to_slaves_1_m_wstrb
output [7 : 0] v_to_slaves_1_wstrb;
// value method v_to_slaves_1_m_wlast
output v_to_slaves_1_wlast;
// value method v_to_slaves_1_m_wuser
// action method v_to_slaves_1_m_wready
input v_to_slaves_1_wready;
// action method v_to_slaves_1_m_bvalid
input v_to_slaves_1_bvalid;
input [15 : 0] v_to_slaves_1_bid;
input [1 : 0] v_to_slaves_1_bresp;
// value method v_to_slaves_1_m_bready
output v_to_slaves_1_bready;
// value method v_to_slaves_1_m_arvalid
output v_to_slaves_1_arvalid;
// value method v_to_slaves_1_m_arid
output [15 : 0] v_to_slaves_1_arid;
// value method v_to_slaves_1_m_araddr
output [63 : 0] v_to_slaves_1_araddr;
// value method v_to_slaves_1_m_arlen
output [7 : 0] v_to_slaves_1_arlen;
// value method v_to_slaves_1_m_arsize
output [2 : 0] v_to_slaves_1_arsize;
// value method v_to_slaves_1_m_arburst
output [1 : 0] v_to_slaves_1_arburst;
// value method v_to_slaves_1_m_arlock
output v_to_slaves_1_arlock;
// value method v_to_slaves_1_m_arcache
output [3 : 0] v_to_slaves_1_arcache;
// value method v_to_slaves_1_m_arprot
output [2 : 0] v_to_slaves_1_arprot;
// value method v_to_slaves_1_m_arqos
output [3 : 0] v_to_slaves_1_arqos;
// value method v_to_slaves_1_m_arregion
output [3 : 0] v_to_slaves_1_arregion;
// value method v_to_slaves_1_m_aruser
// action method v_to_slaves_1_m_arready
input v_to_slaves_1_arready;
// action method v_to_slaves_1_m_rvalid
input v_to_slaves_1_rvalid;
input [15 : 0] v_to_slaves_1_rid;
input [63 : 0] v_to_slaves_1_rdata;
input [1 : 0] v_to_slaves_1_rresp;
input v_to_slaves_1_rlast;
// value method v_to_slaves_1_m_rready
output v_to_slaves_1_rready;
// value method v_to_slaves_2_m_awvalid
output v_to_slaves_2_awvalid;
// value method v_to_slaves_2_m_awid
output [15 : 0] v_to_slaves_2_awid;
// value method v_to_slaves_2_m_awaddr
output [63 : 0] v_to_slaves_2_awaddr;
// value method v_to_slaves_2_m_awlen
output [7 : 0] v_to_slaves_2_awlen;
// value method v_to_slaves_2_m_awsize
output [2 : 0] v_to_slaves_2_awsize;
// value method v_to_slaves_2_m_awburst
output [1 : 0] v_to_slaves_2_awburst;
// value method v_to_slaves_2_m_awlock
output v_to_slaves_2_awlock;
// value method v_to_slaves_2_m_awcache
output [3 : 0] v_to_slaves_2_awcache;
// value method v_to_slaves_2_m_awprot
output [2 : 0] v_to_slaves_2_awprot;
// value method v_to_slaves_2_m_awqos
output [3 : 0] v_to_slaves_2_awqos;
// value method v_to_slaves_2_m_awregion
output [3 : 0] v_to_slaves_2_awregion;
// value method v_to_slaves_2_m_awuser
// action method v_to_slaves_2_m_awready
input v_to_slaves_2_awready;
// value method v_to_slaves_2_m_wvalid
output v_to_slaves_2_wvalid;
// value method v_to_slaves_2_m_wdata
output [63 : 0] v_to_slaves_2_wdata;
// value method v_to_slaves_2_m_wstrb
output [7 : 0] v_to_slaves_2_wstrb;
// value method v_to_slaves_2_m_wlast
output v_to_slaves_2_wlast;
// value method v_to_slaves_2_m_wuser
// action method v_to_slaves_2_m_wready
input v_to_slaves_2_wready;
// action method v_to_slaves_2_m_bvalid
input v_to_slaves_2_bvalid;
input [15 : 0] v_to_slaves_2_bid;
input [1 : 0] v_to_slaves_2_bresp;
// value method v_to_slaves_2_m_bready
output v_to_slaves_2_bready;
// value method v_to_slaves_2_m_arvalid
output v_to_slaves_2_arvalid;
// value method v_to_slaves_2_m_arid
output [15 : 0] v_to_slaves_2_arid;
// value method v_to_slaves_2_m_araddr
output [63 : 0] v_to_slaves_2_araddr;
// value method v_to_slaves_2_m_arlen
output [7 : 0] v_to_slaves_2_arlen;
// value method v_to_slaves_2_m_arsize
output [2 : 0] v_to_slaves_2_arsize;
// value method v_to_slaves_2_m_arburst
output [1 : 0] v_to_slaves_2_arburst;
// value method v_to_slaves_2_m_arlock
output v_to_slaves_2_arlock;
// value method v_to_slaves_2_m_arcache
output [3 : 0] v_to_slaves_2_arcache;
// value method v_to_slaves_2_m_arprot
output [2 : 0] v_to_slaves_2_arprot;
// value method v_to_slaves_2_m_arqos
output [3 : 0] v_to_slaves_2_arqos;
// value method v_to_slaves_2_m_arregion
output [3 : 0] v_to_slaves_2_arregion;
// value method v_to_slaves_2_m_aruser
// action method v_to_slaves_2_m_arready
input v_to_slaves_2_arready;
// action method v_to_slaves_2_m_rvalid
input v_to_slaves_2_rvalid;
input [15 : 0] v_to_slaves_2_rid;
input [63 : 0] v_to_slaves_2_rdata;
input [1 : 0] v_to_slaves_2_rresp;
input v_to_slaves_2_rlast;
// value method v_to_slaves_2_m_rready
output v_to_slaves_2_rready;
// signals for module outputs
wire [63 : 0] v_from_masters_0_rdata,
v_from_masters_1_rdata,
v_to_slaves_0_araddr,
v_to_slaves_0_awaddr,
v_to_slaves_0_wdata,
v_to_slaves_1_araddr,
v_to_slaves_1_awaddr,
v_to_slaves_1_wdata,
v_to_slaves_2_araddr,
v_to_slaves_2_awaddr,
v_to_slaves_2_wdata;
wire [15 : 0] v_from_masters_0_bid,
v_from_masters_0_rid,
v_from_masters_1_bid,
v_from_masters_1_rid,
v_to_slaves_0_arid,
v_to_slaves_0_awid,
v_to_slaves_1_arid,
v_to_slaves_1_awid,
v_to_slaves_2_arid,
v_to_slaves_2_awid;
wire [7 : 0] v_to_slaves_0_arlen,
v_to_slaves_0_awlen,
v_to_slaves_0_wstrb,
v_to_slaves_1_arlen,
v_to_slaves_1_awlen,
v_to_slaves_1_wstrb,
v_to_slaves_2_arlen,
v_to_slaves_2_awlen,
v_to_slaves_2_wstrb;
wire [3 : 0] v_to_slaves_0_arcache,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_awcache,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_1_arcache,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_awcache,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_2_arcache,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_awcache,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion;
wire [2 : 0] v_to_slaves_0_arprot,
v_to_slaves_0_arsize,
v_to_slaves_0_awprot,
v_to_slaves_0_awsize,
v_to_slaves_1_arprot,
v_to_slaves_1_arsize,
v_to_slaves_1_awprot,
v_to_slaves_1_awsize,
v_to_slaves_2_arprot,
v_to_slaves_2_arsize,
v_to_slaves_2_awprot,
v_to_slaves_2_awsize;
wire [1 : 0] v_from_masters_0_bresp,
v_from_masters_0_rresp,
v_from_masters_1_bresp,
v_from_masters_1_rresp,
v_to_slaves_0_arburst,
v_to_slaves_0_awburst,
v_to_slaves_1_arburst,
v_to_slaves_1_awburst,
v_to_slaves_2_arburst,
v_to_slaves_2_awburst;
wire RDY_reset,
RDY_set_verbosity,
v_from_masters_0_arready,
v_from_masters_0_awready,
v_from_masters_0_bvalid,
v_from_masters_0_rlast,
v_from_masters_0_rvalid,
v_from_masters_0_wready,
v_from_masters_1_arready,
v_from_masters_1_awready,
v_from_masters_1_bvalid,
v_from_masters_1_rlast,
v_from_masters_1_rvalid,
v_from_masters_1_wready,
v_to_slaves_0_arlock,
v_to_slaves_0_arvalid,
v_to_slaves_0_awlock,
v_to_slaves_0_awvalid,
v_to_slaves_0_bready,
v_to_slaves_0_rready,
v_to_slaves_0_wlast,
v_to_slaves_0_wvalid,
v_to_slaves_1_arlock,
v_to_slaves_1_arvalid,
v_to_slaves_1_awlock,
v_to_slaves_1_awvalid,
v_to_slaves_1_bready,
v_to_slaves_1_rready,
v_to_slaves_1_wlast,
v_to_slaves_1_wvalid,
v_to_slaves_2_arlock,
v_to_slaves_2_arvalid,
v_to_slaves_2_awlock,
v_to_slaves_2_awvalid,
v_to_slaves_2_bready,
v_to_slaves_2_rready,
v_to_slaves_2_wlast,
v_to_slaves_2_wvalid;
// register fabric_cfg_verbosity
reg [3 : 0] fabric_cfg_verbosity;
wire [3 : 0] fabric_cfg_verbosity$D_IN;
wire fabric_cfg_verbosity$EN;
// register fabric_rg_reset
reg fabric_rg_reset;
wire fabric_rg_reset$D_IN, fabric_rg_reset$EN;
// register fabric_v_rg_r_beat_count_0
reg [7 : 0] fabric_v_rg_r_beat_count_0;
reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN;
wire fabric_v_rg_r_beat_count_0$EN;
// register fabric_v_rg_r_beat_count_1
reg [7 : 0] fabric_v_rg_r_beat_count_1;
reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN;
wire fabric_v_rg_r_beat_count_1$EN;
// register fabric_v_rg_r_beat_count_2
reg [7 : 0] fabric_v_rg_r_beat_count_2;
reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN;
wire fabric_v_rg_r_beat_count_2$EN;
// register fabric_v_rg_r_err_beat_count_0
reg [7 : 0] fabric_v_rg_r_err_beat_count_0;
wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN;
wire fabric_v_rg_r_err_beat_count_0$EN;
// register fabric_v_rg_r_err_beat_count_1
reg [7 : 0] fabric_v_rg_r_err_beat_count_1;
wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN;
wire fabric_v_rg_r_err_beat_count_1$EN;
// register fabric_v_rg_wd_beat_count_0
reg [7 : 0] fabric_v_rg_wd_beat_count_0;
wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN;
wire fabric_v_rg_wd_beat_count_0$EN;
// register fabric_v_rg_wd_beat_count_1
reg [7 : 0] fabric_v_rg_wd_beat_count_1;
wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN;
wire fabric_v_rg_wd_beat_count_1$EN;
// ports of submodule fabric_v_f_rd_err_info_0
wire [23 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT;
wire fabric_v_f_rd_err_info_0$CLR,
fabric_v_f_rd_err_info_0$DEQ,
fabric_v_f_rd_err_info_0$EMPTY_N,
fabric_v_f_rd_err_info_0$ENQ,
fabric_v_f_rd_err_info_0$FULL_N;
// ports of submodule fabric_v_f_rd_err_info_1
wire [23 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT;
wire fabric_v_f_rd_err_info_1$CLR,
fabric_v_f_rd_err_info_1$DEQ,
fabric_v_f_rd_err_info_1$EMPTY_N,
fabric_v_f_rd_err_info_1$ENQ,
fabric_v_f_rd_err_info_1$FULL_N;
// ports of submodule fabric_v_f_rd_mis_0
wire [9 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT;
wire fabric_v_f_rd_mis_0$CLR,
fabric_v_f_rd_mis_0$DEQ,
fabric_v_f_rd_mis_0$EMPTY_N,
fabric_v_f_rd_mis_0$ENQ,
fabric_v_f_rd_mis_0$FULL_N;
// ports of submodule fabric_v_f_rd_mis_1
wire [9 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT;
wire fabric_v_f_rd_mis_1$CLR,
fabric_v_f_rd_mis_1$DEQ,
fabric_v_f_rd_mis_1$EMPTY_N,
fabric_v_f_rd_mis_1$ENQ,
fabric_v_f_rd_mis_1$FULL_N;
// ports of submodule fabric_v_f_rd_mis_2
wire [9 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT;
wire fabric_v_f_rd_mis_2$CLR,
fabric_v_f_rd_mis_2$DEQ,
fabric_v_f_rd_mis_2$EMPTY_N,
fabric_v_f_rd_mis_2$ENQ,
fabric_v_f_rd_mis_2$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_0
reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT;
wire fabric_v_f_rd_sjs_0$CLR,
fabric_v_f_rd_sjs_0$DEQ,
fabric_v_f_rd_sjs_0$EMPTY_N,
fabric_v_f_rd_sjs_0$ENQ,
fabric_v_f_rd_sjs_0$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_1
reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT;
wire fabric_v_f_rd_sjs_1$CLR,
fabric_v_f_rd_sjs_1$DEQ,
fabric_v_f_rd_sjs_1$EMPTY_N,
fabric_v_f_rd_sjs_1$ENQ,
fabric_v_f_rd_sjs_1$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_0
reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT;
wire fabric_v_f_wd_tasks_0$CLR,
fabric_v_f_wd_tasks_0$DEQ,
fabric_v_f_wd_tasks_0$EMPTY_N,
fabric_v_f_wd_tasks_0$ENQ,
fabric_v_f_wd_tasks_0$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_1
reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT;
wire fabric_v_f_wd_tasks_1$CLR,
fabric_v_f_wd_tasks_1$DEQ,
fabric_v_f_wd_tasks_1$EMPTY_N,
fabric_v_f_wd_tasks_1$ENQ,
fabric_v_f_wd_tasks_1$FULL_N;
// ports of submodule fabric_v_f_wr_err_info_0
wire [15 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT;
wire fabric_v_f_wr_err_info_0$CLR,
fabric_v_f_wr_err_info_0$DEQ,
fabric_v_f_wr_err_info_0$EMPTY_N,
fabric_v_f_wr_err_info_0$ENQ,
fabric_v_f_wr_err_info_0$FULL_N;
// ports of submodule fabric_v_f_wr_err_info_1
wire [15 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT;
wire fabric_v_f_wr_err_info_1$CLR,
fabric_v_f_wr_err_info_1$DEQ,
fabric_v_f_wr_err_info_1$EMPTY_N,
fabric_v_f_wr_err_info_1$ENQ,
fabric_v_f_wr_err_info_1$FULL_N;
// ports of submodule fabric_v_f_wr_mis_0
wire [1 : 0] fabric_v_f_wr_mis_0$D_IN, fabric_v_f_wr_mis_0$D_OUT;
wire fabric_v_f_wr_mis_0$CLR,
fabric_v_f_wr_mis_0$DEQ,
fabric_v_f_wr_mis_0$EMPTY_N,
fabric_v_f_wr_mis_0$ENQ,
fabric_v_f_wr_mis_0$FULL_N;
// ports of submodule fabric_v_f_wr_mis_1
wire [1 : 0] fabric_v_f_wr_mis_1$D_IN, fabric_v_f_wr_mis_1$D_OUT;
wire fabric_v_f_wr_mis_1$CLR,
fabric_v_f_wr_mis_1$DEQ,
fabric_v_f_wr_mis_1$EMPTY_N,
fabric_v_f_wr_mis_1$ENQ,
fabric_v_f_wr_mis_1$FULL_N;
// ports of submodule fabric_v_f_wr_mis_2
wire [1 : 0] fabric_v_f_wr_mis_2$D_IN, fabric_v_f_wr_mis_2$D_OUT;
wire fabric_v_f_wr_mis_2$CLR,
fabric_v_f_wr_mis_2$DEQ,
fabric_v_f_wr_mis_2$EMPTY_N,
fabric_v_f_wr_mis_2$ENQ,
fabric_v_f_wr_mis_2$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_0
reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT;
wire fabric_v_f_wr_sjs_0$CLR,
fabric_v_f_wr_sjs_0$DEQ,
fabric_v_f_wr_sjs_0$EMPTY_N,
fabric_v_f_wr_sjs_0$ENQ,
fabric_v_f_wr_sjs_0$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_1
reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT;
wire fabric_v_f_wr_sjs_1$CLR,
fabric_v_f_wr_sjs_1$DEQ,
fabric_v_f_wr_sjs_1$EMPTY_N,
fabric_v_f_wr_sjs_1$ENQ,
fabric_v_f_wr_sjs_1$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_addr
wire [108 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN,
fabric_xactors_from_masters_0_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_addr$CLR,
fabric_xactors_from_masters_0_f_rd_addr$DEQ,
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_addr$ENQ,
fabric_xactors_from_masters_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_data
reg [82 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN;
wire [82 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_data$CLR,
fabric_xactors_from_masters_0_f_rd_data$DEQ,
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_data$ENQ,
fabric_xactors_from_masters_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_addr
wire [108 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN,
fabric_xactors_from_masters_0_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_addr$CLR,
fabric_xactors_from_masters_0_f_wr_addr$DEQ,
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_addr$ENQ,
fabric_xactors_from_masters_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN,
fabric_xactors_from_masters_0_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_data$CLR,
fabric_xactors_from_masters_0_f_wr_data$DEQ,
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_data$ENQ,
fabric_xactors_from_masters_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_resp
reg [17 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN;
wire [17 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_resp$CLR,
fabric_xactors_from_masters_0_f_wr_resp$DEQ,
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_resp$ENQ,
fabric_xactors_from_masters_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_rd_addr
wire [108 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN,
fabric_xactors_from_masters_1_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_1_f_rd_addr$CLR,
fabric_xactors_from_masters_1_f_rd_addr$DEQ,
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_1_f_rd_addr$ENQ,
fabric_xactors_from_masters_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_rd_data
reg [82 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN;
wire [82 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_1_f_rd_data$CLR,
fabric_xactors_from_masters_1_f_rd_data$DEQ,
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_1_f_rd_data$ENQ,
fabric_xactors_from_masters_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_addr
wire [108 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN,
fabric_xactors_from_masters_1_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_addr$CLR,
fabric_xactors_from_masters_1_f_wr_addr$DEQ,
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_addr$ENQ,
fabric_xactors_from_masters_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN,
fabric_xactors_from_masters_1_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_data$CLR,
fabric_xactors_from_masters_1_f_wr_data$DEQ,
fabric_xactors_from_masters_1_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_data$ENQ,
fabric_xactors_from_masters_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_resp
reg [17 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN;
wire [17 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_resp$CLR,
fabric_xactors_from_masters_1_f_wr_resp$DEQ,
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_resp$ENQ,
fabric_xactors_from_masters_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN,
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_addr$CLR,
fabric_xactors_to_slaves_0_f_rd_addr$DEQ,
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_addr$ENQ,
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_data$CLR,
fabric_xactors_to_slaves_0_f_rd_data$DEQ,
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_data$ENQ,
fabric_xactors_to_slaves_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN,
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_addr$CLR,
fabric_xactors_to_slaves_0_f_wr_addr$DEQ,
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_addr$ENQ,
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN,
fabric_xactors_to_slaves_0_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_data$CLR,
fabric_xactors_to_slaves_0_f_wr_data$DEQ,
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_data$ENQ,
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN,
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_resp$CLR,
fabric_xactors_to_slaves_0_f_wr_resp$DEQ,
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_resp$ENQ,
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN,
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_addr$CLR,
fabric_xactors_to_slaves_1_f_rd_addr$DEQ,
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_addr$ENQ,
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_data$CLR,
fabric_xactors_to_slaves_1_f_rd_data$DEQ,
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_data$ENQ,
fabric_xactors_to_slaves_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN,
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_addr$CLR,
fabric_xactors_to_slaves_1_f_wr_addr$DEQ,
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_addr$ENQ,
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN,
fabric_xactors_to_slaves_1_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_data$CLR,
fabric_xactors_to_slaves_1_f_wr_data$DEQ,
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_data$ENQ,
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN,
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_resp$CLR,
fabric_xactors_to_slaves_1_f_wr_resp$DEQ,
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_resp$ENQ,
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN,
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_addr$CLR,
fabric_xactors_to_slaves_2_f_rd_addr$DEQ,
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_addr$ENQ,
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_data$CLR,
fabric_xactors_to_slaves_2_f_rd_data$DEQ,
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_data$ENQ,
fabric_xactors_to_slaves_2_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN,
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_addr$CLR,
fabric_xactors_to_slaves_2_f_wr_addr$DEQ,
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_addr$ENQ,
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN,
fabric_xactors_to_slaves_2_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_data$CLR,
fabric_xactors_to_slaves_2_f_wr_data$DEQ,
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_data$ENQ,
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN,
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_resp$CLR,
fabric_xactors_to_slaves_2_f_wr_resp$DEQ,
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_resp$ENQ,
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5,
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave,
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1,
CAN_FIRE_RL_fabric_rl_reset,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1,
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave,
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1,
CAN_FIRE_reset,
CAN_FIRE_set_verbosity,
CAN_FIRE_v_from_masters_0_m_arvalid,
CAN_FIRE_v_from_masters_0_m_awvalid,
CAN_FIRE_v_from_masters_0_m_bready,
CAN_FIRE_v_from_masters_0_m_rready,
CAN_FIRE_v_from_masters_0_m_wvalid,
CAN_FIRE_v_from_masters_1_m_arvalid,
CAN_FIRE_v_from_masters_1_m_awvalid,
CAN_FIRE_v_from_masters_1_m_bready,
CAN_FIRE_v_from_masters_1_m_rready,
CAN_FIRE_v_from_masters_1_m_wvalid,
CAN_FIRE_v_to_slaves_0_m_arready,
CAN_FIRE_v_to_slaves_0_m_awready,
CAN_FIRE_v_to_slaves_0_m_bvalid,
CAN_FIRE_v_to_slaves_0_m_rvalid,
CAN_FIRE_v_to_slaves_0_m_wready,
CAN_FIRE_v_to_slaves_1_m_arready,
CAN_FIRE_v_to_slaves_1_m_awready,
CAN_FIRE_v_to_slaves_1_m_bvalid,
CAN_FIRE_v_to_slaves_1_m_rvalid,
CAN_FIRE_v_to_slaves_1_m_wready,
CAN_FIRE_v_to_slaves_2_m_arready,
CAN_FIRE_v_to_slaves_2_m_awready,
CAN_FIRE_v_to_slaves_2_m_bvalid,
CAN_FIRE_v_to_slaves_2_m_rvalid,
CAN_FIRE_v_to_slaves_2_m_wready,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5,
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave,
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1,
WILL_FIRE_RL_fabric_rl_reset,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1,
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave,
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1,
WILL_FIRE_reset,
WILL_FIRE_set_verbosity,
WILL_FIRE_v_from_masters_0_m_arvalid,
WILL_FIRE_v_from_masters_0_m_awvalid,
WILL_FIRE_v_from_masters_0_m_bready,
WILL_FIRE_v_from_masters_0_m_rready,
WILL_FIRE_v_from_masters_0_m_wvalid,
WILL_FIRE_v_from_masters_1_m_arvalid,
WILL_FIRE_v_from_masters_1_m_awvalid,
WILL_FIRE_v_from_masters_1_m_bready,
WILL_FIRE_v_from_masters_1_m_rready,
WILL_FIRE_v_from_masters_1_m_wvalid,
WILL_FIRE_v_to_slaves_0_m_arready,
WILL_FIRE_v_to_slaves_0_m_awready,
WILL_FIRE_v_to_slaves_0_m_bvalid,
WILL_FIRE_v_to_slaves_0_m_rvalid,
WILL_FIRE_v_to_slaves_0_m_wready,
WILL_FIRE_v_to_slaves_1_m_arready,
WILL_FIRE_v_to_slaves_1_m_awready,
WILL_FIRE_v_to_slaves_1_m_bvalid,
WILL_FIRE_v_to_slaves_1_m_rvalid,
WILL_FIRE_v_to_slaves_1_m_wready,
WILL_FIRE_v_to_slaves_2_m_arready,
WILL_FIRE_v_to_slaves_2_m_awready,
WILL_FIRE_v_to_slaves_2_m_bvalid,
WILL_FIRE_v_to_slaves_2_m_rvalid,
WILL_FIRE_v_to_slaves_2_m_wready;
// inputs to muxes for submodule ports
wire [82 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4,
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4;
wire [17 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4,
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4;
wire [9 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1,
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4;
wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_3,
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_3,
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2;
wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1,
MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1,
MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h8252;
reg [31 : 0] v__h8630;
reg [31 : 0] v__h9008;
reg [31 : 0] v__h9449;
reg [31 : 0] v__h9821;
reg [31 : 0] v__h10193;
reg [31 : 0] v__h10545;
reg [31 : 0] v__h10867;
reg [31 : 0] v__h11225;
reg [31 : 0] v__h11472;
reg [31 : 0] v__h11826;
reg [31 : 0] v__h12073;
reg [31 : 0] v__h12430;
reg [31 : 0] v__h12700;
reg [31 : 0] v__h12970;
reg [31 : 0] v__h13244;
reg [31 : 0] v__h13488;
reg [31 : 0] v__h13732;
reg [31 : 0] v__h13966;
reg [31 : 0] v__h14176;
reg [31 : 0] v__h14607;
reg [31 : 0] v__h14972;
reg [31 : 0] v__h15337;
reg [31 : 0] v__h15756;
reg [31 : 0] v__h16097;
reg [31 : 0] v__h16438;
reg [31 : 0] v__h16765;
reg [31 : 0] v__h17056;
reg [31 : 0] v__h17450;
reg [31 : 0] v__h17731;
reg [31 : 0] v__h18099;
reg [31 : 0] v__h18370;
reg [31 : 0] v__h18738;
reg [31 : 0] v__h19009;
reg [31 : 0] v__h19357;
reg [31 : 0] v__h19638;
reg [31 : 0] v__h19961;
reg [31 : 0] v__h20232;
reg [31 : 0] v__h20555;
reg [31 : 0] v__h20826;
reg [31 : 0] v__h21306;
reg [31 : 0] v__h21688;
reg [31 : 0] v__h5557;
reg [31 : 0] v__h5551;
reg [31 : 0] v__h8246;
reg [31 : 0] v__h8624;
reg [31 : 0] v__h9002;
reg [31 : 0] v__h9443;
reg [31 : 0] v__h9815;
reg [31 : 0] v__h10187;
reg [31 : 0] v__h10539;
reg [31 : 0] v__h10861;
reg [31 : 0] v__h11219;
reg [31 : 0] v__h11466;
reg [31 : 0] v__h11820;
reg [31 : 0] v__h12067;
reg [31 : 0] v__h12424;
reg [31 : 0] v__h12694;
reg [31 : 0] v__h12964;
reg [31 : 0] v__h13238;
reg [31 : 0] v__h13482;
reg [31 : 0] v__h13726;
reg [31 : 0] v__h13960;
reg [31 : 0] v__h14170;
reg [31 : 0] v__h14601;
reg [31 : 0] v__h14966;
reg [31 : 0] v__h15331;
reg [31 : 0] v__h15750;
reg [31 : 0] v__h16091;
reg [31 : 0] v__h16432;
reg [31 : 0] v__h16759;
reg [31 : 0] v__h17050;
reg [31 : 0] v__h17444;
reg [31 : 0] v__h17725;
reg [31 : 0] v__h18093;
reg [31 : 0] v__h18364;
reg [31 : 0] v__h18732;
reg [31 : 0] v__h19003;
reg [31 : 0] v__h19351;
reg [31 : 0] v__h19632;
reg [31 : 0] v__h19955;
reg [31 : 0] v__h20226;
reg [31 : 0] v__h20549;
reg [31 : 0] v__h20820;
reg [31 : 0] v__h21300;
reg [31 : 0] v__h21682;
// synopsys translate_on
// remaining internal signals
reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1,
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2;
wire [7 : 0] x__h11374,
x__h11975,
x__h17614,
x__h18263,
x__h18902,
x__h21243,
x__h21625;
wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_ETC___d465,
IF_fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_ETC___d500,
IF_fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_ETC___d535,
x1_avValue_rresp__h17592,
x1_avValue_rresp__h18241,
x1_avValue_rresp__h18880;
wire NOT_fabric_xactors_from_masters_0_f_rd_addr_fi_ETC___d358,
NOT_fabric_xactors_from_masters_0_f_wr_addr_fi_ETC___d67,
NOT_fabric_xactors_from_masters_1_f_rd_addr_fi_ETC___d407,
NOT_fabric_xactors_from_masters_1_f_wr_addr_fi_ETC___d121,
_dor1fabric_v_f_rd_mis_0$EN_deq,
_dor1fabric_v_f_rd_mis_1$EN_deq,
_dor1fabric_v_f_rd_mis_2$EN_deq,
fabric_v_f_wd_tasks_0_i_notEmpty__51_AND_fabri_ETC___d160,
fabric_v_f_wd_tasks_1_i_notEmpty__83_AND_fabri_ETC___d189,
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449,
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484,
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519,
fabric_v_rg_r_err_beat_count_0_82_EQ_fabric_v__ETC___d584,
fabric_v_rg_r_err_beat_count_1_00_EQ_fabric_v__ETC___d602,
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176,
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d314,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d315,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d318,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d320,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d351,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d353,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d417,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d133,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d24,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d60,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d62,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d369,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d370,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d373,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d375,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d400,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d402,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d428,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d114,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d116,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d145,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d82,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d86,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88;
// action method reset
assign RDY_reset = !fabric_rg_reset ;
assign CAN_FIRE_reset = !fabric_rg_reset ;
assign WILL_FIRE_reset = EN_reset ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method v_from_masters_0_m_awvalid
assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
// value method v_from_masters_0_m_awready
assign v_from_masters_0_awready =
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
// action method v_from_masters_0_m_wvalid
assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
// value method v_from_masters_0_m_wready
assign v_from_masters_0_wready =
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
// value method v_from_masters_0_m_bvalid
assign v_from_masters_0_bvalid =
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
// value method v_from_masters_0_m_bid
assign v_from_masters_0_bid =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[17:2] ;
// value method v_from_masters_0_m_bresp
assign v_from_masters_0_bresp =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_0_m_bready
assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ;
// action method v_from_masters_0_m_arvalid
assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
// value method v_from_masters_0_m_arready
assign v_from_masters_0_arready =
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
// value method v_from_masters_0_m_rvalid
assign v_from_masters_0_rvalid =
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
// value method v_from_masters_0_m_rid
assign v_from_masters_0_rid =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[82:67] ;
// value method v_from_masters_0_m_rdata
assign v_from_masters_0_rdata =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_0_m_rresp
assign v_from_masters_0_rresp =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_0_m_rlast
assign v_from_masters_0_rlast =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ;
// action method v_from_masters_0_m_rready
assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ;
// action method v_from_masters_1_m_awvalid
assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ;
// value method v_from_masters_1_m_awready
assign v_from_masters_1_awready =
fabric_xactors_from_masters_1_f_wr_addr$FULL_N ;
// action method v_from_masters_1_m_wvalid
assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ;
// value method v_from_masters_1_m_wready
assign v_from_masters_1_wready =
fabric_xactors_from_masters_1_f_wr_data$FULL_N ;
// value method v_from_masters_1_m_bvalid
assign v_from_masters_1_bvalid =
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ;
// value method v_from_masters_1_m_bid
assign v_from_masters_1_bid =
fabric_xactors_from_masters_1_f_wr_resp$D_OUT[17:2] ;
// value method v_from_masters_1_m_bresp
assign v_from_masters_1_bresp =
fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_1_m_bready
assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ;
// action method v_from_masters_1_m_arvalid
assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ;
// value method v_from_masters_1_m_arready
assign v_from_masters_1_arready =
fabric_xactors_from_masters_1_f_rd_addr$FULL_N ;
// value method v_from_masters_1_m_rvalid
assign v_from_masters_1_rvalid =
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ;
// value method v_from_masters_1_m_rid
assign v_from_masters_1_rid =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[82:67] ;
// value method v_from_masters_1_m_rdata
assign v_from_masters_1_rdata =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_1_m_rresp
assign v_from_masters_1_rresp =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_1_m_rlast
assign v_from_masters_1_rlast =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ;
// action method v_from_masters_1_m_rready
assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ;
// value method v_to_slaves_0_m_awvalid
assign v_to_slaves_0_awvalid =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_0_m_awid
assign v_to_slaves_0_awid =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_0_m_awaddr
assign v_to_slaves_0_awaddr =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_awlen
assign v_to_slaves_0_awlen =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_awsize
assign v_to_slaves_0_awsize =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_awburst
assign v_to_slaves_0_awburst =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_awlock
assign v_to_slaves_0_awlock =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_awcache
assign v_to_slaves_0_awcache =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_awprot
assign v_to_slaves_0_awprot =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_awqos
assign v_to_slaves_0_awqos =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_awregion
assign v_to_slaves_0_awregion =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_awready
assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
// value method v_to_slaves_0_m_wvalid
assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ;
// value method v_to_slaves_0_m_wdata
assign v_to_slaves_0_wdata =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_0_m_wstrb
assign v_to_slaves_0_wstrb =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_0_m_wlast
assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_0_m_wready
assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
// action method v_to_slaves_0_m_bvalid
assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
// value method v_to_slaves_0_m_bready
assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
// value method v_to_slaves_0_m_arvalid
assign v_to_slaves_0_arvalid =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_0_m_arid
assign v_to_slaves_0_arid =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_0_m_araddr
assign v_to_slaves_0_araddr =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_arlen
assign v_to_slaves_0_arlen =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_arsize
assign v_to_slaves_0_arsize =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_arburst
assign v_to_slaves_0_arburst =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_arlock
assign v_to_slaves_0_arlock =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_arcache
assign v_to_slaves_0_arcache =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_arprot
assign v_to_slaves_0_arprot =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_arqos
assign v_to_slaves_0_arqos =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_arregion
assign v_to_slaves_0_arregion =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_arready
assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
// action method v_to_slaves_0_m_rvalid
assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
// value method v_to_slaves_0_m_rready
assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
// value method v_to_slaves_1_m_awvalid
assign v_to_slaves_1_awvalid =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_1_m_awid
assign v_to_slaves_1_awid =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_1_m_awaddr
assign v_to_slaves_1_awaddr =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_awlen
assign v_to_slaves_1_awlen =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_awsize
assign v_to_slaves_1_awsize =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_awburst
assign v_to_slaves_1_awburst =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_awlock
assign v_to_slaves_1_awlock =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_awcache
assign v_to_slaves_1_awcache =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_awprot
assign v_to_slaves_1_awprot =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_awqos
assign v_to_slaves_1_awqos =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_awregion
assign v_to_slaves_1_awregion =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_awready
assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
// value method v_to_slaves_1_m_wvalid
assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ;
// value method v_to_slaves_1_m_wdata
assign v_to_slaves_1_wdata =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_1_m_wstrb
assign v_to_slaves_1_wstrb =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_1_m_wlast
assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_1_m_wready
assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
// action method v_to_slaves_1_m_bvalid
assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
// value method v_to_slaves_1_m_bready
assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
// value method v_to_slaves_1_m_arvalid
assign v_to_slaves_1_arvalid =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_1_m_arid
assign v_to_slaves_1_arid =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_1_m_araddr
assign v_to_slaves_1_araddr =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_arlen
assign v_to_slaves_1_arlen =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_arsize
assign v_to_slaves_1_arsize =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_arburst
assign v_to_slaves_1_arburst =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_arlock
assign v_to_slaves_1_arlock =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_arcache
assign v_to_slaves_1_arcache =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_arprot
assign v_to_slaves_1_arprot =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_arqos
assign v_to_slaves_1_arqos =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_arregion
assign v_to_slaves_1_arregion =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_arready
assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
// action method v_to_slaves_1_m_rvalid
assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
// value method v_to_slaves_1_m_rready
assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
// value method v_to_slaves_2_m_awvalid
assign v_to_slaves_2_awvalid =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_2_m_awid
assign v_to_slaves_2_awid =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_2_m_awaddr
assign v_to_slaves_2_awaddr =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_awlen
assign v_to_slaves_2_awlen =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_awsize
assign v_to_slaves_2_awsize =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_awburst
assign v_to_slaves_2_awburst =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_awlock
assign v_to_slaves_2_awlock =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_awcache
assign v_to_slaves_2_awcache =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_awprot
assign v_to_slaves_2_awprot =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_awqos
assign v_to_slaves_2_awqos =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_awregion
assign v_to_slaves_2_awregion =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_awready
assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
// value method v_to_slaves_2_m_wvalid
assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ;
// value method v_to_slaves_2_m_wdata
assign v_to_slaves_2_wdata =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_2_m_wstrb
assign v_to_slaves_2_wstrb =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_2_m_wlast
assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_2_m_wready
assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
// action method v_to_slaves_2_m_bvalid
assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
// value method v_to_slaves_2_m_bready
assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
// value method v_to_slaves_2_m_arvalid
assign v_to_slaves_2_arvalid =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_2_m_arid
assign v_to_slaves_2_arid =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_2_m_araddr
assign v_to_slaves_2_araddr =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_arlen
assign v_to_slaves_2_arlen =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_arsize
assign v_to_slaves_2_arsize =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_arburst
assign v_to_slaves_2_arburst =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_arlock
assign v_to_slaves_2_arlock =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_arcache
assign v_to_slaves_2_arcache =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_arprot
assign v_to_slaves_2_arprot =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_arqos
assign v_to_slaves_2_arqos =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_arregion
assign v_to_slaves_2_arregion =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_arready
assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
// action method v_to_slaves_2_m_rvalid
assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
// value method v_to_slaves_2_m_rready
assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
// submodule fabric_v_f_rd_err_info_0
SizedFIFO #(.p1width(32'd24),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_0$D_IN),
.ENQ(fabric_v_f_rd_err_info_0$ENQ),
.DEQ(fabric_v_f_rd_err_info_0$DEQ),
.CLR(fabric_v_f_rd_err_info_0$CLR),
.D_OUT(fabric_v_f_rd_err_info_0$D_OUT),
.FULL_N(fabric_v_f_rd_err_info_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N));
// submodule fabric_v_f_rd_err_info_1
SizedFIFO #(.p1width(32'd24),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_1$D_IN),
.ENQ(fabric_v_f_rd_err_info_1$ENQ),
.DEQ(fabric_v_f_rd_err_info_1$DEQ),
.CLR(fabric_v_f_rd_err_info_1$CLR),
.D_OUT(fabric_v_f_rd_err_info_1$D_OUT),
.FULL_N(fabric_v_f_rd_err_info_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_0
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_0$D_IN),
.ENQ(fabric_v_f_rd_mis_0$ENQ),
.DEQ(fabric_v_f_rd_mis_0$DEQ),
.CLR(fabric_v_f_rd_mis_0$CLR),
.D_OUT(fabric_v_f_rd_mis_0$D_OUT),
.FULL_N(fabric_v_f_rd_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_1
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_1$D_IN),
.ENQ(fabric_v_f_rd_mis_1$ENQ),
.DEQ(fabric_v_f_rd_mis_1$DEQ),
.CLR(fabric_v_f_rd_mis_1$CLR),
.D_OUT(fabric_v_f_rd_mis_1$D_OUT),
.FULL_N(fabric_v_f_rd_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_2
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_2$D_IN),
.ENQ(fabric_v_f_rd_mis_2$ENQ),
.DEQ(fabric_v_f_rd_mis_2$DEQ),
.CLR(fabric_v_f_rd_mis_2$CLR),
.D_OUT(fabric_v_f_rd_mis_2$D_OUT),
.FULL_N(fabric_v_f_rd_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N));
// submodule fabric_v_f_rd_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_0$D_IN),
.ENQ(fabric_v_f_rd_sjs_0$ENQ),
.DEQ(fabric_v_f_rd_sjs_0$DEQ),
.CLR(fabric_v_f_rd_sjs_0$CLR),
.D_OUT(fabric_v_f_rd_sjs_0$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N));
// submodule fabric_v_f_rd_sjs_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_1$D_IN),
.ENQ(fabric_v_f_rd_sjs_1$ENQ),
.DEQ(fabric_v_f_rd_sjs_1$DEQ),
.CLR(fabric_v_f_rd_sjs_1$CLR),
.D_OUT(fabric_v_f_rd_sjs_1$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N));
// submodule fabric_v_f_wd_tasks_0
FIFO2 #(.width(32'd10), .guarded(1'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_0$D_IN),
.ENQ(fabric_v_f_wd_tasks_0$ENQ),
.DEQ(fabric_v_f_wd_tasks_0$DEQ),
.CLR(fabric_v_f_wd_tasks_0$CLR),
.D_OUT(fabric_v_f_wd_tasks_0$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_0$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N));
// submodule fabric_v_f_wd_tasks_1
FIFO2 #(.width(32'd10), .guarded(1'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_1$D_IN),
.ENQ(fabric_v_f_wd_tasks_1$ENQ),
.DEQ(fabric_v_f_wd_tasks_1$DEQ),
.CLR(fabric_v_f_wd_tasks_1$CLR),
.D_OUT(fabric_v_f_wd_tasks_1$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_1$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N));
// submodule fabric_v_f_wr_err_info_0
SizedFIFO #(.p1width(32'd16),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_0$D_IN),
.ENQ(fabric_v_f_wr_err_info_0$ENQ),
.DEQ(fabric_v_f_wr_err_info_0$DEQ),
.CLR(fabric_v_f_wr_err_info_0$CLR),
.D_OUT(fabric_v_f_wr_err_info_0$D_OUT),
.FULL_N(fabric_v_f_wr_err_info_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N));
// submodule fabric_v_f_wr_err_info_1
SizedFIFO #(.p1width(32'd16),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_1$D_IN),
.ENQ(fabric_v_f_wr_err_info_1$ENQ),
.DEQ(fabric_v_f_wr_err_info_1$DEQ),
.CLR(fabric_v_f_wr_err_info_1$CLR),
.D_OUT(fabric_v_f_wr_err_info_1$D_OUT),
.FULL_N(fabric_v_f_wr_err_info_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_0$D_IN),
.ENQ(fabric_v_f_wr_mis_0$ENQ),
.DEQ(fabric_v_f_wr_mis_0$DEQ),
.CLR(fabric_v_f_wr_mis_0$CLR),
.D_OUT(fabric_v_f_wr_mis_0$D_OUT),
.FULL_N(fabric_v_f_wr_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_1$D_IN),
.ENQ(fabric_v_f_wr_mis_1$ENQ),
.DEQ(fabric_v_f_wr_mis_1$DEQ),
.CLR(fabric_v_f_wr_mis_1$CLR),
.D_OUT(fabric_v_f_wr_mis_1$D_OUT),
.FULL_N(fabric_v_f_wr_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_2
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_2$D_IN),
.ENQ(fabric_v_f_wr_mis_2$ENQ),
.DEQ(fabric_v_f_wr_mis_2$DEQ),
.CLR(fabric_v_f_wr_mis_2$CLR),
.D_OUT(fabric_v_f_wr_mis_2$D_OUT),
.FULL_N(fabric_v_f_wr_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N));
// submodule fabric_v_f_wr_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_0$D_IN),
.ENQ(fabric_v_f_wr_sjs_0$ENQ),
.DEQ(fabric_v_f_wr_sjs_0$DEQ),
.CLR(fabric_v_f_wr_sjs_0$CLR),
.D_OUT(fabric_v_f_wr_sjs_0$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N));
// submodule fabric_v_f_wr_sjs_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_1$D_IN),
.ENQ(fabric_v_f_wr_sjs_1$ENQ),
.DEQ(fabric_v_f_wr_sjs_1$DEQ),
.CLR(fabric_v_f_wr_sjs_1$CLR),
.D_OUT(fabric_v_f_wr_sjs_1$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N));
// rule RL_fabric_rl_wr_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
(fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) &&
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d24 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
NOT_fabric_xactors_from_masters_0_f_wr_addr_fi_ETC___d67 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_3
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 =
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
(fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d82 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) &&
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d86 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_4
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 =
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d82 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_5
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 =
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
NOT_fabric_xactors_from_masters_1_f_wr_addr_fi_ETC___d121 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_no_such_slave
assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_v_f_wr_err_info_0$FULL_N &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d133 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave =
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ;
// rule RL_fabric_rl_wr_xaction_no_such_slave_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 =
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
fabric_v_f_wr_err_info_1$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d145 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_0_i_notEmpty__51_AND_fabri_ETC___d160 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 =
fabric_xactors_from_masters_1_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_1_i_notEmpty__83_AND_fabri_ETC___d189 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_0$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
// rule RL_fabric_rl_wr_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_mis_1$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_mis_2$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_3
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 =
fabric_v_f_wr_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_0$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_4
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 =
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_5
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 =
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ;
// rule RL_fabric_rl_wr_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_0$EMPTY_N &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
// rule RL_fabric_rl_wr_resp_err_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 =
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_1$EMPTY_N &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
(fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d314 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d315) &&
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d318 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d320 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d314 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d315 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
NOT_fabric_xactors_from_masters_0_f_rd_addr_fi_ETC___d358 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_3
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 =
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
(fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d369 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d370) &&
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d373 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d375 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_4
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 =
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d369 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d370 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_5
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 =
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
NOT_fabric_xactors_from_masters_1_f_rd_addr_fi_ETC___d407 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_xaction_no_such_slave
assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_v_f_rd_err_info_0$FULL_N &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d417 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave =
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ;
// rule RL_fabric_rl_rd_xaction_no_such_slave_1
assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 =
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
fabric_v_f_rd_err_info_1$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d428 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 =
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ;
// rule RL_fabric_rl_rd_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_0$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
// rule RL_fabric_rl_rd_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_1$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_2$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_3
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_0$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_4
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 =
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_1$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_5
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 =
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_2$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ;
// rule RL_fabric_rl_rd_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master =
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_0$EMPTY_N &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// rule RL_fabric_rl_rd_resp_err_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 =
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_1$EMPTY_N &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
// rule RL_fabric_rl_reset
assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
// inputs to muxes for submodule ports
assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ;
assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ;
assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ;
assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 =
{ 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 =
{ 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_3 =
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 ?
8'd0 :
x__h17614 ;
assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 =
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 ?
8'd0 :
x__h18263 ;
assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_3 =
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 ?
8'd0 :
x__h18902 ;
assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 ?
8'd0 :
x__h11374 ;
assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 ?
8'd0 :
x__h11975 ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 =
{ fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_ETC___d465,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 =
{ fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_ETC___d500,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 =
{ fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_ETC___d535,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_0$D_OUT[15:0],
66'd3,
fabric_v_rg_r_err_beat_count_0_82_EQ_fabric_v__ETC___d584 } ;
assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ;
assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_1$D_OUT[15:0],
66'd3,
fabric_v_rg_r_err_beat_count_1_00_EQ_fabric_v__ETC___d602 } ;
assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ;
// register fabric_cfg_verbosity
assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign fabric_cfg_verbosity$EN = EN_set_verbosity ;
// register fabric_rg_reset
assign fabric_rg_reset$D_IN = !fabric_rg_reset ;
assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ;
// register fabric_v_rg_r_beat_count_0
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3:
fabric_v_rg_r_beat_count_0$D_IN =
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_v_rg_r_beat_count_0$D_IN =
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_3;
default: fabric_v_rg_r_beat_count_0$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_1
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4:
fabric_v_rg_r_beat_count_1$D_IN =
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_v_rg_r_beat_count_1$D_IN =
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_1$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_2
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5:
fabric_v_rg_r_beat_count_2$D_IN =
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_v_rg_r_beat_count_2$D_IN =
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_3;
default: fabric_v_rg_r_beat_count_2$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_2$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
fabric_rg_reset ;
// register fabric_v_rg_r_err_beat_count_0
assign fabric_v_rg_r_err_beat_count_0$D_IN =
fabric_v_rg_r_err_beat_count_0_82_EQ_fabric_v__ETC___d584 ?
8'd0 :
x__h21243 ;
assign fabric_v_rg_r_err_beat_count_0$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// register fabric_v_rg_r_err_beat_count_1
assign fabric_v_rg_r_err_beat_count_1$D_IN =
fabric_v_rg_r_err_beat_count_1_00_EQ_fabric_v__ETC___d602 ?
8'd0 :
x__h21625 ;
assign fabric_v_rg_r_err_beat_count_1$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
// register fabric_v_rg_wd_beat_count_0
assign fabric_v_rg_wd_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ||
fabric_rg_reset ;
// register fabric_v_rg_wd_beat_count_1
assign fabric_v_rg_wd_beat_count_1$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ||
fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_0
assign fabric_v_f_rd_err_info_0$D_IN =
{ fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21],
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93] } ;
assign fabric_v_f_rd_err_info_0$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ;
assign fabric_v_f_rd_err_info_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_82_EQ_fabric_v__ETC___d584 ;
assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_1
assign fabric_v_f_rd_err_info_1$D_IN =
{ fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21],
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[108:93] } ;
assign fabric_v_f_rd_err_info_1$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ;
assign fabric_v_f_rd_err_info_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_v_rg_r_err_beat_count_1_00_EQ_fabric_v__ETC___d602 ;
assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_0
assign fabric_v_f_rd_mis_0$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_v_f_rd_mis_0$DEQ =
_dor1fabric_v_f_rd_mis_0$EN_deq &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 ;
assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_1
assign fabric_v_f_rd_mis_1$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_1$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ;
assign fabric_v_f_rd_mis_1$DEQ =
_dor1fabric_v_f_rd_mis_1$EN_deq &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 ;
assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_2
assign fabric_v_f_rd_mis_2$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_2$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_v_f_rd_mis_2$DEQ =
_dor1fabric_v_f_rd_mis_2$EN_deq &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 ;
assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_0
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave:
fabric_v_f_rd_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1:
fabric_v_f_rd_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2:
fabric_v_f_rd_sjs_0$D_IN = 2'd2;
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave:
fabric_v_f_rd_sjs_0$D_IN = 2'd3;
default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ;
assign fabric_v_f_rd_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_82_EQ_fabric_v__ETC___d584 ;
assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_1
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3:
fabric_v_f_rd_sjs_1$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4:
fabric_v_f_rd_sjs_1$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5:
fabric_v_f_rd_sjs_1$D_IN = 2'd2;
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1:
fabric_v_f_rd_sjs_1$D_IN = 2'd3;
default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_1$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ;
assign fabric_v_f_rd_sjs_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_v_rg_r_err_beat_count_1_00_EQ_fabric_v__ETC___d602 ;
assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4;
default: fabric_v_f_wd_tasks_0$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ;
assign fabric_v_f_wd_tasks_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 ;
assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_1
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4;
default: fabric_v_f_wd_tasks_1$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ;
assign fabric_v_f_wd_tasks_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 ;
assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_0
assign fabric_v_f_wr_err_info_0$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93] ;
assign fabric_v_f_wr_err_info_0$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ;
assign fabric_v_f_wr_err_info_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_1
assign fabric_v_f_wr_err_info_1$D_IN =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[108:93] ;
assign fabric_v_f_wr_err_info_1$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ;
assign fabric_v_f_wr_err_info_1$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_0
assign fabric_v_f_wr_mis_0$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? 2'd0 : 2'd1 ;
assign fabric_v_f_wr_mis_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_v_f_wr_mis_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_1
assign fabric_v_f_wr_mis_1$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ?
2'd0 :
2'd1 ;
assign fabric_v_f_wr_mis_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ;
assign fabric_v_f_wr_mis_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_2
assign fabric_v_f_wr_mis_2$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ?
2'd0 :
2'd1 ;
assign fabric_v_f_wr_mis_2$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wr_mis_2$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wr_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wr_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wr_sjs_0$D_IN = 2'd2;
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave:
fabric_v_f_wr_sjs_0$D_IN = 2'd3;
default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ;
assign fabric_v_f_wr_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_1
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3:
fabric_v_f_wr_sjs_1$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4:
fabric_v_f_wr_sjs_1$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5:
fabric_v_f_wr_sjs_1$D_IN = 2'd2;
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1:
fabric_v_f_wr_sjs_1$D_IN = 2'd3;
default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ;
assign fabric_v_f_wr_sjs_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ;
assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_addr
assign fabric_xactors_from_masters_0_f_rd_addr$D_IN =
{ v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion } ;
assign fabric_xactors_from_masters_0_f_rd_addr$ENQ =
v_from_masters_0_arvalid &&
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_rd_data$D_IN =
83'h2AAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_rd_data$DEQ =
v_from_masters_0_rready &&
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_addr
assign fabric_xactors_from_masters_0_f_wr_addr$D_IN =
{ v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion } ;
assign fabric_xactors_from_masters_0_f_wr_addr$ENQ =
v_from_masters_0_awvalid &&
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_data
assign fabric_xactors_from_masters_0_f_wr_data$D_IN =
{ v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast } ;
assign fabric_xactors_from_masters_0_f_wr_data$ENQ =
v_from_masters_0_wvalid &&
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_data$DEQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_wr_resp$D_IN =
18'b101010101010101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_wr_resp$DEQ =
v_from_masters_0_bready &&
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_rd_addr
assign fabric_xactors_from_masters_1_f_rd_addr$D_IN =
{ v_from_masters_1_arid,
v_from_masters_1_araddr,
v_from_masters_1_arlen,
v_from_masters_1_arsize,
v_from_masters_1_arburst,
v_from_masters_1_arlock,
v_from_masters_1_arcache,
v_from_masters_1_arprot,
v_from_masters_1_arqos,
v_from_masters_1_arregion } ;
assign fabric_xactors_from_masters_1_f_rd_addr$ENQ =
v_from_masters_1_arvalid &&
fabric_xactors_from_masters_1_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_1_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_1_f_rd_data$D_IN =
83'h2AAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_1_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
assign fabric_xactors_from_masters_1_f_rd_data$DEQ =
v_from_masters_1_rready &&
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_addr
assign fabric_xactors_from_masters_1_f_wr_addr$D_IN =
{ v_from_masters_1_awid,
v_from_masters_1_awaddr,
v_from_masters_1_awlen,
v_from_masters_1_awsize,
v_from_masters_1_awburst,
v_from_masters_1_awlock,
v_from_masters_1_awcache,
v_from_masters_1_awprot,
v_from_masters_1_awqos,
v_from_masters_1_awregion } ;
assign fabric_xactors_from_masters_1_f_wr_addr$ENQ =
v_from_masters_1_awvalid &&
fabric_xactors_from_masters_1_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_1_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_data
assign fabric_xactors_from_masters_1_f_wr_data$D_IN =
{ v_from_masters_1_wdata,
v_from_masters_1_wstrb,
v_from_masters_1_wlast } ;
assign fabric_xactors_from_masters_1_f_wr_data$ENQ =
v_from_masters_1_wvalid &&
fabric_xactors_from_masters_1_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_1_f_wr_data$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ;
assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_1_f_wr_resp$D_IN =
18'b101010101010101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_1_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
assign fabric_xactors_from_masters_1_f_wr_resp$DEQ =
v_from_masters_1_bready &&
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_addr
assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N &&
v_to_slaves_0_arready ;
assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_data
assign fabric_xactors_to_slaves_0_f_rd_data$D_IN =
{ v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast } ;
assign fabric_xactors_to_slaves_0_f_rd_data$ENQ =
v_to_slaves_0_rvalid &&
fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_0_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_addr
assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N &&
v_to_slaves_0_awready ;
assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_data
assign fabric_xactors_to_slaves_0_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ;
assign fabric_xactors_to_slaves_0_f_wr_data$DEQ =
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N &&
v_to_slaves_0_wready ;
assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_resp
assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN =
{ v_to_slaves_0_bid, v_to_slaves_0_bresp } ;
assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ =
v_to_slaves_0_bvalid &&
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_addr
assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ;
assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N &&
v_to_slaves_1_arready ;
assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_data
assign fabric_xactors_to_slaves_1_f_rd_data$D_IN =
{ v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast } ;
assign fabric_xactors_to_slaves_1_f_rd_data$ENQ =
v_to_slaves_1_rvalid &&
fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_1_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_addr
assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ;
assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N &&
v_to_slaves_1_awready ;
assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_data
assign fabric_xactors_to_slaves_1_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ;
assign fabric_xactors_to_slaves_1_f_wr_data$DEQ =
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N &&
v_to_slaves_1_wready ;
assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_resp
assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN =
{ v_to_slaves_1_bid, v_to_slaves_1_bresp } ;
assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ =
v_to_slaves_1_bvalid &&
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_addr
assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N &&
v_to_slaves_2_arready ;
assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_data
assign fabric_xactors_to_slaves_2_f_rd_data$D_IN =
{ v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast } ;
assign fabric_xactors_to_slaves_2_f_rd_data$ENQ =
v_to_slaves_2_rvalid &&
fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_2_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_addr
assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N &&
v_to_slaves_2_awready ;
assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_data
assign fabric_xactors_to_slaves_2_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ;
assign fabric_xactors_to_slaves_2_f_wr_data$DEQ =
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N &&
v_to_slaves_2_wready ;
assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_resp
assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN =
{ v_to_slaves_2_bid, v_to_slaves_2_bresp } ;
assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ =
v_to_slaves_2_bvalid &&
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ;
// remaining internal signals
assign IF_fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_ETC___d465 =
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 ?
x1_avValue_rresp__h17592 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_ETC___d500 =
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 ?
x1_avValue_rresp__h18241 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_ETC___d535 =
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 ?
x1_avValue_rresp__h18880 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign NOT_fabric_xactors_from_masters_0_f_rd_addr_fi_ETC___d358 =
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d351 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d353 &&
(fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d314 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d315) &&
(fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d318 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d320) ;
assign NOT_fabric_xactors_from_masters_0_f_wr_addr_fi_ETC___d67 =
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d60 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d62 &&
(fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) &&
(fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d24) ;
assign NOT_fabric_xactors_from_masters_1_f_rd_addr_fi_ETC___d407 =
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d400 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d402 &&
(fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d369 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d370) &&
(fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d373 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d375) ;
assign NOT_fabric_xactors_from_masters_1_f_wr_addr_fi_ETC___d121 =
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d114 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d116 &&
(fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d82 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) &&
(fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d86 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ;
assign _dor1fabric_v_f_rd_mis_0$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign _dor1fabric_v_f_rd_mis_1$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign _dor1fabric_v_f_rd_mis_2$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_v_f_wd_tasks_0_i_notEmpty__51_AND_fabri_ETC___d160 =
fabric_v_f_wd_tasks_0$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ;
assign fabric_v_f_wd_tasks_1_i_notEmpty__83_AND_fabri_ETC___d189 =
fabric_v_f_wd_tasks_1$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ;
assign fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 =
fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 =
fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 =
fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ;
assign fabric_v_rg_r_err_beat_count_0_82_EQ_fabric_v__ETC___d584 =
fabric_v_rg_r_err_beat_count_0 ==
fabric_v_f_rd_err_info_0$D_OUT[23:16] ;
assign fabric_v_rg_r_err_beat_count_1_00_EQ_fabric_v__ETC___d602 =
fabric_v_rg_r_err_beat_count_1 ==
fabric_v_f_rd_err_info_1$D_OUT[23:16] ;
assign fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 =
fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ;
assign fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 =
fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d314 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
64'h0000000080000000 ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d315 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
64'h0000000090000000 ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d318 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
64'h0000000000001000 ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d320 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] < 64'd8192 ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d351 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
64'h00000000C0000000 ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d353 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
64'h00000000C0000080 ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d417 =
(fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d314 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d315) &&
(fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d318 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d320) &&
(fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d351 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d353) ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d133 =
(fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) &&
(fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d24) &&
(fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d60 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d62) ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
64'h0000000080000000 ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
64'h0000000090000000 ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
64'h0000000000001000 ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d24 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] < 64'd8192 ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d60 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
64'h00000000C0000000 ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d62 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
64'h00000000C0000080 ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d369 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
64'h0000000080000000 ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d370 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
64'h0000000090000000 ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d373 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
64'h0000000000001000 ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d375 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] < 64'd8192 ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d400 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
64'h00000000C0000000 ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d402 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
64'h00000000C0000080 ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d428 =
(fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d369 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d370) &&
(fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d373 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d375) &&
(fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d400 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d402) ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d114 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
64'h00000000C0000000 ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d116 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
64'h00000000C0000080 ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d145 =
(fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d82 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) &&
(fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d86 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) &&
(fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d114 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d116) ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d82 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
64'h0000000080000000 ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
64'h0000000090000000 ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d86 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
64'h0000000000001000 ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] < 64'd8192 ;
assign x1_avValue_rresp__h17592 =
(fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h18241 =
(fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h18880 =
(fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign x__h11374 = fabric_v_rg_wd_beat_count_0 + 8'd1 ;
assign x__h11975 = fabric_v_rg_wd_beat_count_1 + 8'd1 ;
assign x__h17614 = fabric_v_rg_r_beat_count_0 + 8'd1 ;
assign x__h18263 = fabric_v_rg_r_beat_count_1 + 8'd1 ;
assign x__h18902 = fabric_v_rg_r_beat_count_2 + 8'd1 ;
assign x__h21243 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ;
assign x__h21625 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ;
always@(fabric_v_f_wd_tasks_0$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_0$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1;
endcase
end
always@(fabric_v_f_wd_tasks_1$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_1$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (fabric_cfg_verbosity$EN)
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
fabric_cfg_verbosity$D_IN;
if (fabric_rg_reset$EN)
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN;
if (fabric_v_rg_r_beat_count_0$EN)
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_0$D_IN;
if (fabric_v_rg_r_beat_count_1$EN)
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_1$D_IN;
if (fabric_v_rg_r_beat_count_2$EN)
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_2$D_IN;
if (fabric_v_rg_r_err_beat_count_0$EN)
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_0$D_IN;
if (fabric_v_rg_r_err_beat_count_1$EN)
fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_1$D_IN;
if (fabric_v_rg_wd_beat_count_0$EN)
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_0$D_IN;
if (fabric_v_rg_wd_beat_count_1$EN)
fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_1$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
fabric_cfg_verbosity = 4'hA;
fabric_rg_reset = 1'h0;
fabric_v_rg_r_beat_count_0 = 8'hAA;
fabric_v_rg_r_beat_count_1 = 8'hAA;
fabric_v_rg_r_beat_count_2 = 8'hAA;
fabric_v_rg_r_err_beat_count_0 = 8'hAA;
fabric_v_rg_r_err_beat_count_1 = 8'hAA;
fabric_v_rg_wd_beat_count_0 = 8'hAA;
fabric_v_rg_wd_beat_count_1 = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8252 = $stime;
#0;
end
v__h8246 = v__h8252 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h8246,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8630 = $stime;
#0;
end
v__h8624 = v__h8630 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h8624,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9008 = $stime;
#0;
end
v__h9002 = v__h9008 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9002,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9449 = $stime;
#0;
end
v__h9443 = v__h9449 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9443,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9821 = $stime;
#0;
end
v__h9815 = v__h9821 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9815,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10193 = $stime;
#0;
end
v__h10187 = v__h10193 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h10187,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10545 = $stime;
#0;
end
v__h10539 = v__h10545 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?",
v__h10539,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10867 = $stime;
#0;
end
v__h10861 = v__h10867 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?",
v__h10861,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11225 = $stime;
#0;
end
v__h11219 = v__h11225 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
v__h11219,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8],
fabric_v_rg_wd_beat_count_0,
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
begin
v__h11472 = $stime;
#0;
end
v__h11466 = v__h11472 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h11466,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_68_EQ_fabric_v_f_w_ETC___d176 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11826 = $stime;
#0;
end
v__h11820 = v__h11826 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
v__h11820,
$signed(32'd1),
fabric_v_f_wd_tasks_1$D_OUT[9:8],
fabric_v_rg_wd_beat_count_1,
fabric_v_f_wd_tasks_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
begin
v__h12073 = $stime;
#0;
end
v__h12067 = v__h12073 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h12067,
$signed(32'd1),
fabric_v_f_wd_tasks_1$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_97_EQ_fabric_v_f_w_ETC___d205 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12430 = $stime;
#0;
end
v__h12424 = v__h12430 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h12424,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12700 = $stime;
#0;
end
v__h12694 = v__h12700 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h12694,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12970 = $stime;
#0;
end
v__h12964 = v__h12970 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h12964,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13244 = $stime;
#0;
end
v__h13238 = v__h13244 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13238,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13488 = $stime;
#0;
end
v__h13482 = v__h13488 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13482,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13732 = $stime;
#0;
end
v__h13726 = v__h13732 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13726,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13966 = $stime;
#0;
end
v__h13960 = v__h13966 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h13960,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_0$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14176 = $stime;
#0;
end
v__h14170 = v__h14176 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h14170,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_1$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14607 = $stime;
#0;
end
v__h14601 = v__h14607 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h14601,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14972 = $stime;
#0;
end
v__h14966 = v__h14972 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h14966,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15337 = $stime;
#0;
end
v__h15331 = v__h15337 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15331,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15756 = $stime;
#0;
end
v__h15750 = v__h15756 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15750,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h16097 = $stime;
#0;
end
v__h16091 = v__h16097 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h16091,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h16438 = $stime;
#0;
end
v__h16432 = v__h16438 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h16432,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h16765 = $stime;
#0;
end
v__h16759 = v__h16765 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?",
v__h16759,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h17056 = $stime;
#0;
end
v__h17050 = v__h17056 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?",
v__h17050,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h17450 = $stime;
#0;
end
v__h17444 = v__h17450 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h17444,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h17731 = $stime;
#0;
end
v__h17725 = v__h17731 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h17725,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_ETC___d465);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h18099 = $stime;
#0;
end
v__h18093 = v__h18099 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h18093,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h18370 = $stime;
#0;
end
v__h18364 = v__h18370 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h18364,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_ETC___d500);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h18738 = $stime;
#0;
end
v__h18732 = v__h18738 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h18732,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h19009 = $stime;
#0;
end
v__h19003 = v__h19009 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h19003,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_ETC___d535);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h19357 = $stime;
#0;
end
v__h19351 = v__h19357 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h19351,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_rd_ETC___d449 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h19638 = $stime;
#0;
end
v__h19632 = v__h19638 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h19632,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_47_EQ_fabric_v_f_ETC___d465);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h19961 = $stime;
#0;
end
v__h19955 = v__h19961 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h19955,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_rd_ETC___d484 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h20232 = $stime;
#0;
end
v__h20226 = v__h20232 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h20226,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_82_EQ_fabric_v_f_ETC___d500);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h20555 = $stime;
#0;
end
v__h20549 = v__h20555 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h20549,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_rd_ETC___d519 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h20826 = $stime;
#0;
end
v__h20820 = v__h20826 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h20820,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_17_EQ_fabric_v_f_ETC___d535);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21306 = $stime;
#0;
end
v__h21300 = v__h21306 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h21300,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[15:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_0_82_EQ_fabric_v__ETC___d584)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_0_82_EQ_fabric_v__ETC___d584)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21688 = $stime;
#0;
end
v__h21682 = v__h21688 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h21682,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[15:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_1_00_EQ_fabric_v__ETC___d602)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_1_00_EQ_fabric_v__ETC___d602)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
begin
v__h5557 = $stime;
#0;
end
v__h5551 = v__h5557 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_reset", v__h5551);
end
// synopsys translate_on
endmodule // mkFabric_AXI4
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2016.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / RXTX_BITSLICE
// /___/ /\ Filename : RXTX_BITSLICE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RXTX_BITSLICE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter ENABLE_PRE_EMPHASIS = "FALSE",
parameter FIFO_SYNC_MODE = "FALSE",
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_RX_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RX_RST_DLY_INVERTED = 1'b0,
parameter [0:0] IS_RX_RST_INVERTED = 1'b0,
parameter [0:0] IS_TX_CLK_INVERTED = 1'b0,
parameter [0:0] IS_TX_RST_DLY_INVERTED = 1'b0,
parameter [0:0] IS_TX_RST_INVERTED = 1'b0,
parameter LOOPBACK = "FALSE",
parameter NATIVE_ODELAY_BYPASS = "FALSE",
parameter RX_DATA_TYPE = "DATA",
parameter integer RX_DATA_WIDTH = 8,
parameter RX_DELAY_FORMAT = "TIME",
parameter RX_DELAY_TYPE = "FIXED",
parameter integer RX_DELAY_VALUE = 0,
parameter real RX_REFCLK_FREQUENCY = 300.0,
parameter RX_UPDATE_MODE = "ASYNC",
parameter SIM_DEVICE = "ULTRASCALE",
parameter real SIM_VERSION = 2.0,
parameter TBYTE_CTL = "TBYTE_IN",
parameter integer TX_DATA_WIDTH = 8,
parameter TX_DELAY_FORMAT = "TIME",
parameter TX_DELAY_TYPE = "FIXED",
parameter integer TX_DELAY_VALUE = 0,
parameter TX_OUTPUT_PHASE_90 = "FALSE",
parameter real TX_REFCLK_FREQUENCY = 300.0,
parameter TX_UPDATE_MODE = "ASYNC"
)(
output FIFO_EMPTY,
output FIFO_WRCLK_OUT,
output O,
output [7:0] Q,
output [39:0] RX_BIT_CTRL_OUT,
output [8:0] RX_CNTVALUEOUT,
output [39:0] TX_BIT_CTRL_OUT,
output [8:0] TX_CNTVALUEOUT,
output T_OUT,
input [7:0] D,
input DATAIN,
input FIFO_RD_CLK,
input FIFO_RD_EN,
input [39:0] RX_BIT_CTRL_IN,
input RX_CE,
input RX_CLK,
input [8:0] RX_CNTVALUEIN,
input RX_EN_VTC,
input RX_INC,
input RX_LOAD,
input RX_RST,
input RX_RST_DLY,
input T,
input TBYTE_IN,
input [39:0] TX_BIT_CTRL_IN,
input TX_CE,
input TX_CLK,
input [8:0] TX_CNTVALUEIN,
input TX_EN_VTC,
input TX_INC,
input TX_LOAD,
input TX_RST,
input TX_RST_DLY
);
// define constants
localparam MODULE_NAME = "RXTX_BITSLICE";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
reg warning_flag = 1'b1;
`ifdef XIL_DR
`include "RXTX_BITSLICE_dr.v"
`else
localparam [40:1] ENABLE_PRE_EMPHASIS_REG = ENABLE_PRE_EMPHASIS;
localparam [40:1] FIFO_SYNC_MODE_REG = FIFO_SYNC_MODE;
localparam [0:0] INIT_REG = INIT;
localparam [0:0] IS_RX_CLK_INVERTED_REG = IS_RX_CLK_INVERTED;
localparam [0:0] IS_RX_RST_DLY_INVERTED_REG = IS_RX_RST_DLY_INVERTED;
localparam [0:0] IS_RX_RST_INVERTED_REG = IS_RX_RST_INVERTED;
localparam [0:0] IS_TX_CLK_INVERTED_REG = IS_TX_CLK_INVERTED;
localparam [0:0] IS_TX_RST_DLY_INVERTED_REG = IS_TX_RST_DLY_INVERTED;
localparam [0:0] IS_TX_RST_INVERTED_REG = IS_TX_RST_INVERTED;
localparam [40:1] LOOPBACK_REG = LOOPBACK;
localparam [40:1] NATIVE_ODELAY_BYPASS_REG = NATIVE_ODELAY_BYPASS;
localparam [112:1] RX_DATA_TYPE_REG = RX_DATA_TYPE;
localparam [31:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH;
localparam [40:1] RX_DELAY_FORMAT_REG = RX_DELAY_FORMAT;
localparam [64:1] RX_DELAY_TYPE_REG = RX_DELAY_TYPE;
localparam [31:0] RX_DELAY_VALUE_REG = RX_DELAY_VALUE;
localparam real RX_REFCLK_FREQUENCY_REG = RX_REFCLK_FREQUENCY;
localparam [48:1] RX_UPDATE_MODE_REG = RX_UPDATE_MODE;
localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE;
localparam real SIM_VERSION_REG = SIM_VERSION;
localparam [64:1] TBYTE_CTL_REG = TBYTE_CTL;
localparam [31:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH;
localparam [40:1] TX_DELAY_FORMAT_REG = TX_DELAY_FORMAT;
localparam [64:1] TX_DELAY_TYPE_REG = TX_DELAY_TYPE;
localparam [31:0] TX_DELAY_VALUE_REG = TX_DELAY_VALUE;
localparam [40:1] TX_OUTPUT_PHASE_90_REG = TX_OUTPUT_PHASE_90;
localparam real TX_REFCLK_FREQUENCY_REG = TX_REFCLK_FREQUENCY;
localparam [48:1] TX_UPDATE_MODE_REG = TX_UPDATE_MODE;
`endif
localparam [40:1] DDR_DIS_DQS_REG = "TRUE";
localparam [40:1] FIFO_ENABLE_REG = "TRUE";
localparam [5:0] SPARE_REG = 6'b000000;
localparam [0:0] RX_DC_ADJ_EN_REG = 1'b0;
localparam [2:0] RX_FDLY_REG = 3'b010;
localparam [40:1] RX_Q4_ROUTETHRU_REG = "FALSE";
localparam [40:1] RX_Q5_ROUTETHRU_REG = "FALSE";
localparam [40:1] TXRX_LOOPBACK_REG = "FALSE";
localparam [0:0] TX_DC_ADJ_EN_REG = 1'b0;
localparam [2:0] TX_FDLY_REG = 3'b010;
localparam [40:1] TX_Q_ROUTETHRU_REG = "FALSE";
localparam [40:1] TX_T_OUT_ROUTETHRU_REG = "FALSE";
localparam [40:1] XIPHY_BITSLICE_MODE_REG = "TRUE";
wire IS_RX_CLK_INVERTED_BIN;
wire IS_RX_RST_DLY_INVERTED_BIN;
wire IS_RX_RST_INVERTED_BIN;
wire IS_TX_CLK_INVERTED_BIN;
wire IS_TX_RST_DLY_INVERTED_BIN;
wire IS_TX_RST_INVERTED_BIN;
wire [63:0] RX_REFCLK_FREQUENCY_BIN;
wire [63:0] SIM_VERSION_BIN;
wire [63:0] TX_REFCLK_FREQUENCY_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire IDELAY_DATAIN0_out;
wire IDELAY_DATAOUT_out;
wire ODELAY_DATAIN0_out;
wire ODELAY_DATAOUT_out;
wire FIFO_EMPTY_out;
wire FIFO_WRCLK_OUT_out;
wire O_out;
wire TX2RX_CASC_OUT_out;
wire T_OUT_out;
wire [39:0] RX_BIT_CTRL_OUT_out;
wire [39:0] TX_BIT_CTRL_OUT_out;
wire [7:0] Q_out;
wire [8:0] RX_CNTVALUEOUT_out;
wire [8:0] TX_CNTVALUEOUT_out;
wire FIFO_EMPTY_delay;
wire FIFO_WRCLK_OUT_delay;
wire O_delay;
wire T_OUT_delay;
wire [39:0] RX_BIT_CTRL_OUT_delay;
wire [39:0] TX_BIT_CTRL_OUT_delay;
wire [7:0] Q_delay;
wire [8:0] RX_CNTVALUEOUT_delay;
wire [8:0] TX_CNTVALUEOUT_delay;
wire DATAIN_in;
wire FIFO_RD_CLK_in;
wire FIFO_RD_EN_in;
wire IFD_CE_in;
wire OFD_CE_in;
wire RX2TX_CASC_RETURN_IN_in;
wire RX_CE_in;
wire RX_CLKDIV_in;
wire RX_CLK_C_B_in;
wire RX_CLK_C_in;
wire RX_CLK_in;
wire RX_DATAIN1_in;
wire RX_EN_VTC_in;
wire RX_INC_in;
wire RX_LOAD_in;
wire RX_RST_DLY_in;
wire RX_RST_in;
wire TBYTE_IN_in;
wire TX2RX_CASC_IN_in;
wire TX_CE_in;
wire TX_CLK_in;
wire TX_EN_VTC_in;
wire TX_INC_in;
wire TX_LOAD_in;
wire TX_OCLKDIV_in;
wire TX_OCLK_in;
wire TX_RST_DLY_in;
wire TX_RST_in;
wire T_in;
wire [39:0] RX_BIT_CTRL_IN_in;
wire [39:0] TX_BIT_CTRL_IN_in;
wire [7:0] D_in;
wire [8:0] RX_CNTVALUEIN_in;
wire [8:0] TX_CNTVALUEIN_in;
wire DATAIN_delay;
wire FIFO_RD_CLK_delay;
wire FIFO_RD_EN_delay;
wire RX_CE_delay;
wire RX_CLK_delay;
wire RX_EN_VTC_delay;
wire RX_INC_delay;
wire RX_LOAD_delay;
wire RX_RST_DLY_delay;
wire RX_RST_delay;
wire TBYTE_IN_delay;
wire TX_CE_delay;
wire TX_CLK_delay;
wire TX_EN_VTC_delay;
wire TX_INC_delay;
wire TX_LOAD_delay;
wire TX_RST_DLY_delay;
wire TX_RST_delay;
wire T_delay;
wire [39:0] RX_BIT_CTRL_IN_delay;
wire [39:0] TX_BIT_CTRL_IN_delay;
wire [7:0] D_delay;
wire [8:0] RX_CNTVALUEIN_delay;
wire [8:0] TX_CNTVALUEIN_delay;
assign #(out_delay) FIFO_EMPTY = FIFO_EMPTY_delay;
assign #(out_delay) FIFO_WRCLK_OUT = FIFO_WRCLK_OUT_delay;
assign #(out_delay) O = O_delay;
assign #(out_delay) Q = Q_delay;
assign #(out_delay) RX_BIT_CTRL_OUT = RX_BIT_CTRL_OUT_delay;
assign #(out_delay) RX_CNTVALUEOUT = (RX_EN_VTC_in === 1'b1) ? 9'bxxxxxxxxx : RX_CNTVALUEOUT_delay;
assign #(out_delay) TX_BIT_CTRL_OUT = TX_BIT_CTRL_OUT_delay;
assign #(out_delay) TX_CNTVALUEOUT = (TX_EN_VTC_in === 1'b1) ? 9'bxxxxxxxxx : TX_CNTVALUEOUT_delay;
assign #(out_delay) T_OUT = T_OUT_delay;
`ifdef XIL_TIMING
reg notifier;
`endif
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) FIFO_RD_CLK_delay = FIFO_RD_CLK;
assign #(inclk_delay) RX_CLK_delay = RX_CLK;
assign #(inclk_delay) TX_CLK_delay = TX_CLK;
assign #(in_delay) D_delay = D;
assign #(in_delay) FIFO_RD_EN_delay = FIFO_RD_EN;
assign #(in_delay) RX_CE_delay = RX_CE;
assign #(in_delay) RX_CNTVALUEIN_delay = RX_CNTVALUEIN;
assign #(in_delay) RX_INC_delay = RX_INC;
assign #(in_delay) RX_LOAD_delay = RX_LOAD;
assign #(in_delay) TX_CE_delay = TX_CE;
assign #(in_delay) TX_CNTVALUEIN_delay = TX_CNTVALUEIN;
assign #(in_delay) TX_INC_delay = TX_INC;
assign #(in_delay) TX_LOAD_delay = TX_LOAD;
assign #(in_delay) TX_BIT_CTRL_IN_delay[25] = TX_BIT_CTRL_IN[25];
assign #(in_delay) TX_BIT_CTRL_IN_delay[26] = TX_BIT_CTRL_IN[26];
`endif
// inputs with no timing checks
assign #(in_delay) DATAIN_delay = DATAIN;
assign #(in_delay) RX_BIT_CTRL_IN_delay = RX_BIT_CTRL_IN;
assign #(in_delay) RX_EN_VTC_delay = RX_EN_VTC;
assign #(in_delay) RX_RST_DLY_delay = RX_RST_DLY;
assign #(in_delay) RX_RST_delay = RX_RST;
assign #(in_delay) TBYTE_IN_delay = TBYTE_IN;
assign #(in_delay) TX_BIT_CTRL_IN_delay[0] = TX_BIT_CTRL_IN[0];
assign #(in_delay) TX_BIT_CTRL_IN_delay[1] = TX_BIT_CTRL_IN[1];
assign #(in_delay) TX_BIT_CTRL_IN_delay[2] = TX_BIT_CTRL_IN[2];
assign #(in_delay) TX_BIT_CTRL_IN_delay[3] = TX_BIT_CTRL_IN[3];
assign #(in_delay) TX_BIT_CTRL_IN_delay[4] = TX_BIT_CTRL_IN[4];
assign #(in_delay) TX_BIT_CTRL_IN_delay[5] = TX_BIT_CTRL_IN[5];
assign #(in_delay) TX_BIT_CTRL_IN_delay[6] = TX_BIT_CTRL_IN[6];
assign #(in_delay) TX_BIT_CTRL_IN_delay[7] = TX_BIT_CTRL_IN[7];
assign #(in_delay) TX_BIT_CTRL_IN_delay[8] = TX_BIT_CTRL_IN[8];
assign #(in_delay) TX_BIT_CTRL_IN_delay[9] = TX_BIT_CTRL_IN[9];
assign #(in_delay) TX_BIT_CTRL_IN_delay[10] = TX_BIT_CTRL_IN[10];
assign #(in_delay) TX_BIT_CTRL_IN_delay[11] = TX_BIT_CTRL_IN[11];
assign #(in_delay) TX_BIT_CTRL_IN_delay[12] = TX_BIT_CTRL_IN[12];
assign #(in_delay) TX_BIT_CTRL_IN_delay[13] = TX_BIT_CTRL_IN[13];
assign #(in_delay) TX_BIT_CTRL_IN_delay[14] = TX_BIT_CTRL_IN[14];
assign #(in_delay) TX_BIT_CTRL_IN_delay[15] = TX_BIT_CTRL_IN[15];
assign #(in_delay) TX_BIT_CTRL_IN_delay[16] = TX_BIT_CTRL_IN[16];
assign #(in_delay) TX_BIT_CTRL_IN_delay[17] = TX_BIT_CTRL_IN[17];
assign #(in_delay) TX_BIT_CTRL_IN_delay[18] = TX_BIT_CTRL_IN[18];
assign #(in_delay) TX_BIT_CTRL_IN_delay[19] = TX_BIT_CTRL_IN[19];
assign #(in_delay) TX_BIT_CTRL_IN_delay[20] = TX_BIT_CTRL_IN[20];
assign #(in_delay) TX_BIT_CTRL_IN_delay[21] = TX_BIT_CTRL_IN[21];
assign #(in_delay) TX_BIT_CTRL_IN_delay[22] = TX_BIT_CTRL_IN[22];
assign #(in_delay) TX_BIT_CTRL_IN_delay[23] = TX_BIT_CTRL_IN[23];
assign #(in_delay) TX_BIT_CTRL_IN_delay[24] = TX_BIT_CTRL_IN[24];
assign #(in_delay) TX_BIT_CTRL_IN_delay[27] = TX_BIT_CTRL_IN[27];
assign #(in_delay) TX_BIT_CTRL_IN_delay[28] = TX_BIT_CTRL_IN[28];
assign #(in_delay) TX_BIT_CTRL_IN_delay[29] = TX_BIT_CTRL_IN[29];
assign #(in_delay) TX_BIT_CTRL_IN_delay[30] = TX_BIT_CTRL_IN[30];
assign #(in_delay) TX_BIT_CTRL_IN_delay[31] = TX_BIT_CTRL_IN[31];
assign #(in_delay) TX_BIT_CTRL_IN_delay[32] = TX_BIT_CTRL_IN[32];
assign #(in_delay) TX_BIT_CTRL_IN_delay[33] = TX_BIT_CTRL_IN[33];
assign #(in_delay) TX_BIT_CTRL_IN_delay[34] = TX_BIT_CTRL_IN[34];
assign #(in_delay) TX_BIT_CTRL_IN_delay[35] = TX_BIT_CTRL_IN[35];
assign #(in_delay) TX_BIT_CTRL_IN_delay[36] = TX_BIT_CTRL_IN[36];
assign #(in_delay) TX_BIT_CTRL_IN_delay[37] = TX_BIT_CTRL_IN[37];
assign #(in_delay) TX_BIT_CTRL_IN_delay[38] = TX_BIT_CTRL_IN[38];
assign #(in_delay) TX_BIT_CTRL_IN_delay[39] = TX_BIT_CTRL_IN[39];
assign #(in_delay) TX_EN_VTC_delay = TX_EN_VTC;
assign #(in_delay) TX_RST_DLY_delay = TX_RST_DLY;
assign #(in_delay) TX_RST_delay = TX_RST;
assign #(in_delay) T_delay = T;
assign FIFO_EMPTY_delay = FIFO_EMPTY_out;
assign FIFO_WRCLK_OUT_delay = FIFO_WRCLK_OUT_out;
assign O_delay = O_out;
assign Q_delay = Q_out;
assign RX_BIT_CTRL_OUT_delay = RX_BIT_CTRL_OUT_out;
assign RX_CNTVALUEOUT_delay = RX_CNTVALUEOUT_out;
assign TX_BIT_CTRL_OUT_delay = TX_BIT_CTRL_OUT_out;
assign TX_CNTVALUEOUT_delay = TX_CNTVALUEOUT_out;
assign T_OUT_delay = T_OUT_out;
assign DATAIN_in = DATAIN_delay;
assign D_in = D_delay;
assign FIFO_RD_CLK_in = FIFO_RD_CLK_delay;
assign FIFO_RD_EN_in = FIFO_RD_EN_delay;
assign RX_BIT_CTRL_IN_in = RX_BIT_CTRL_IN_delay;
assign RX_CE_in = RX_CE_delay;
assign RX_CLK_in = RX_CLK_delay ^ IS_RX_CLK_INVERTED_BIN;
assign RX_CNTVALUEIN_in = RX_CNTVALUEIN_delay;
assign RX_EN_VTC_in = RX_EN_VTC_delay;
assign RX_INC_in = RX_INC_delay;
assign RX_LOAD_in = RX_LOAD_delay;
assign RX_RST_DLY_in = RX_RST_DLY_delay ^ IS_RX_RST_DLY_INVERTED_BIN;
assign RX_RST_in = RX_RST_delay ^ IS_RX_RST_INVERTED_BIN;
assign TBYTE_IN_in = TBYTE_IN_delay;
assign TX_BIT_CTRL_IN_in = TX_BIT_CTRL_IN_delay;
assign TX_CE_in = TX_CE_delay;
assign TX_CLK_in = TX_CLK_delay ^ IS_TX_CLK_INVERTED_BIN;
assign TX_CNTVALUEIN_in = TX_CNTVALUEIN_delay;
assign TX_EN_VTC_in = TX_EN_VTC_delay;
assign TX_INC_in = TX_INC_delay;
assign TX_LOAD_in = TX_LOAD_delay;
assign TX_RST_DLY_in = TX_RST_DLY_delay ^ IS_TX_RST_DLY_INVERTED_BIN;
assign TX_RST_in = TX_RST_delay ^ IS_TX_RST_INVERTED_BIN;
assign T_in = T_delay;
assign IS_RX_CLK_INVERTED_BIN = IS_RX_CLK_INVERTED_REG;
assign IS_RX_RST_DLY_INVERTED_BIN = IS_RX_RST_DLY_INVERTED_REG;
assign IS_RX_RST_INVERTED_BIN = IS_RX_RST_INVERTED_REG;
assign IS_TX_CLK_INVERTED_BIN = IS_TX_CLK_INVERTED_REG;
assign IS_TX_RST_DLY_INVERTED_BIN = IS_TX_RST_DLY_INVERTED_REG;
assign IS_TX_RST_INVERTED_BIN = IS_TX_RST_INVERTED_REG;
assign RX_REFCLK_FREQUENCY_BIN = RX_REFCLK_FREQUENCY_REG * 1000;
assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000;
assign TX_REFCLK_FREQUENCY_BIN = TX_REFCLK_FREQUENCY_REG * 1000;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @(RX_EN_VTC_in or TX_EN_VTC_in) begin
if ((RX_EN_VTC_in ===0 || TX_EN_VTC_in ===0 )&& (RX_DELAY_FORMAT_REG == "TIME" || TX_DELAY_FORMAT_REG == "TIME") && warning_flag == 1'b1 ) begin
$display("Warning: [Unisim %s-1] BISC Calibration : DELAY_FORMAT set to TIME with RX_EN_VTC/TX_EN_VTC signal set to 0. In hardware, when the RX_EN_VTC/TX_EN_VTC signal is low during the initial calibration process, the BISC will never complete and the DLY_RDY and VTC_RDY status signals from the BITSLICE_CONTROL remain low. Simulation will not reflect this behavior. In simulation, the DLY_RDY and VTC_RDY from the BITSLICE_CONTROL will assert high. You should ensure the RX_EN_VTC/TX_EN_VTC signal is held high during initial BISC self calibration to ensure BISC completes in hardware. See Select IO Userguide UG571 for more information.Instance: %m", MODULE_NAME);
warning_flag = 1'b0;
end
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((ENABLE_PRE_EMPHASIS_REG != "FALSE") &&
(ENABLE_PRE_EMPHASIS_REG != "TRUE"))) begin
$display("Error: [Unisim %s-102] ENABLE_PRE_EMPHASIS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ENABLE_PRE_EMPHASIS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FIFO_SYNC_MODE_REG != "FALSE") &&
(FIFO_SYNC_MODE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-103] FIFO_SYNC_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FIFO_SYNC_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOPBACK_REG != "FALSE") &&
(LOOPBACK_REG != "TRUE"))) begin
$display("Error: [Unisim %s-111] LOOPBACK attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LOOPBACK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((NATIVE_ODELAY_BYPASS_REG != "FALSE") &&
(NATIVE_ODELAY_BYPASS_REG != "TRUE"))) begin
$display("Error: [Unisim %s-112] NATIVE_ODELAY_BYPASS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, NATIVE_ODELAY_BYPASS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DATA_TYPE_REG != "DATA") &&
(RX_DATA_TYPE_REG != "CLOCK") &&
(RX_DATA_TYPE_REG != "DATA_AND_CLOCK") &&
(RX_DATA_TYPE_REG != "SERIAL"))) begin
$display("Error: [Unisim %s-113] RX_DATA_TYPE attribute is set to %s. Legal values for this attribute are DATA, CLOCK, DATA_AND_CLOCK or SERIAL. Instance: %m", MODULE_NAME, RX_DATA_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DATA_WIDTH_REG != 8) &&
(RX_DATA_WIDTH_REG != 4))) begin
$display("Error: [Unisim %s-114] RX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 8 or 4. Instance: %m", MODULE_NAME, RX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DELAY_FORMAT_REG != "TIME") &&
(RX_DELAY_FORMAT_REG != "COUNT"))) begin
$display("Error: [Unisim %s-116] RX_DELAY_FORMAT attribute is set to %s. Legal values for this attribute are TIME or COUNT. Instance: %m", MODULE_NAME, RX_DELAY_FORMAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DELAY_TYPE_REG != "FIXED") &&
(RX_DELAY_TYPE_REG != "VAR_LOAD") &&
(RX_DELAY_TYPE_REG != "VARIABLE"))) begin
$display("Error: [Unisim %s-117] RX_DELAY_TYPE attribute is set to %s. Legal values for this attribute are FIXED, VAR_LOAD or VARIABLE. Instance: %m", MODULE_NAME, RX_DELAY_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(SIM_DEVICE_REG == "ULTRASCALE" && ((RX_DELAY_VALUE_REG < 0) || (RX_DELAY_VALUE_REG > 1250)))) begin
$display("Error: [Unisim %s-118] RX_DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, RX_DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(SIM_DEVICE_REG != "ULTRASCALE" && ((RX_DELAY_VALUE_REG < 0) || (RX_DELAY_VALUE_REG > 1100)))) begin
$display("Error: [Unisim %s-118] RX_DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1100. Instance: %m", MODULE_NAME, RX_DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(RX_DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG != "ULTRASCALE" && (RX_REFCLK_FREQUENCY_REG < 300.0 || RX_REFCLK_FREQUENCY_REG > 2667.0))) begin
$display("Error: [Unisim %s-122] RX_REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 300.0 to 2667.0. Instance: %m", MODULE_NAME, RX_REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(RX_DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG == "ULTRASCALE" && (RX_REFCLK_FREQUENCY_REG < 200.0 || RX_REFCLK_FREQUENCY_REG > 2400.0))) begin
$display("Error: [Unisim %s-122] RX_REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 200.0 to 2400.0. Instance: %m", MODULE_NAME, RX_REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_UPDATE_MODE_REG != "ASYNC") &&
(RX_UPDATE_MODE_REG != "MANUAL") &&
(RX_UPDATE_MODE_REG != "SYNC"))) begin
$display("Error: [Unisim %s-123] RX_UPDATE_MODE attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, RX_UPDATE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_DEVICE_REG != "ULTRASCALE") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin
$display("Error: [Unisim %s-124] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_VERSION_REG != 2.0) &&
(SIM_VERSION_REG != 1.0))) begin
$display("Error: [Unisim %s-125] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TBYTE_CTL_REG != "TBYTE_IN") &&
(TBYTE_CTL_REG != "T"))) begin
$display("Error: [Unisim %s-126] TBYTE_CTL attribute is set to %s. Legal values for this attribute are TBYTE_IN or T. Instance: %m", MODULE_NAME, TBYTE_CTL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DATA_WIDTH_REG != 8) &&
(TX_DATA_WIDTH_REG != 4))) begin
$display("Error: [Unisim %s-128] TX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 8 or 4. Instance: %m", MODULE_NAME, TX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DELAY_FORMAT_REG != "TIME") &&
(TX_DELAY_FORMAT_REG != "COUNT"))) begin
$display("Error: [Unisim %s-130] TX_DELAY_FORMAT attribute is set to %s. Legal values for this attribute are TIME or COUNT. Instance: %m", MODULE_NAME, TX_DELAY_FORMAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DELAY_TYPE_REG != "FIXED") &&
(TX_DELAY_TYPE_REG != "VAR_LOAD") &&
(TX_DELAY_TYPE_REG != "VARIABLE"))) begin
$display("Error: [Unisim %s-131] TX_DELAY_TYPE attribute is set to %s. Legal values for this attribute are FIXED, VAR_LOAD or VARIABLE. Instance: %m", MODULE_NAME, TX_DELAY_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(SIM_DEVICE_REG == "ULTRASCALE" && ((TX_DELAY_VALUE_REG < 0) || (TX_DELAY_VALUE_REG > 1250)))) begin
$display("Error: [Unisim %s-132] TX_DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, TX_DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(SIM_DEVICE_REG != "ULTRASCALE" && ((TX_DELAY_VALUE_REG < 0) || (TX_DELAY_VALUE_REG > 1100)))) begin
$display("Error: [Unisim %s-132] TX_DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1100. Instance: %m", MODULE_NAME, TX_DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_OUTPUT_PHASE_90_REG != "FALSE") &&
(TX_OUTPUT_PHASE_90_REG != "TRUE"))) begin
$display("Error: [Unisim %s-134] TX_OUTPUT_PHASE_90 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TX_OUTPUT_PHASE_90_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(TX_DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG != "ULTRASCALE" && (TX_REFCLK_FREQUENCY_REG < 300.0 || TX_REFCLK_FREQUENCY_REG > 2667.0))) begin
$display("Error: [Unisim %s-136] TX_REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 300.0 to 2667.0. Instance: %m", MODULE_NAME, TX_REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(TX_DELAY_FORMAT_REG != "COUNT" && SIM_DEVICE_REG == "ULTRASCALE" && (TX_REFCLK_FREQUENCY_REG < 200.0 || TX_REFCLK_FREQUENCY_REG > 2400.0))) begin
$display("Error: [Unisim %s-136] TX_REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 200.0 to 2400.0. Instance: %m", MODULE_NAME, TX_REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_UPDATE_MODE_REG != "ASYNC") &&
(TX_UPDATE_MODE_REG != "MANUAL") &&
(TX_UPDATE_MODE_REG != "SYNC"))) begin
$display("Error: [Unisim %s-138] TX_UPDATE_MODE attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, TX_UPDATE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(TX_DELAY_FORMAT_REG != RX_DELAY_FORMAT_REG)) begin
$display("Error: [Unisim %s-139] TX_DELAY_FORMAT = %s is not same as RX_DELAY_FORMAT = %s. [RX/TX]_DELAY_FORMAT attributes must be set to same value. Instance: %m", MODULE_NAME, TX_DELAY_FORMAT_REG, RX_DELAY_FORMAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(RX_DELAY_FORMAT_REG == TX_DELAY_FORMAT_REG && TX_DELAY_FORMAT_REG == "TIME" && TX_DELAY_VALUE_REG != RX_DELAY_VALUE_REG)) begin
$display("Error: [Unisim %s-140] [RX/TX]_DELAY_FORMAT is set to TIME and TX_DELAY_VALUE is set to %d is and RX_DELAY_VALUE is set to %d. Both RX_DELAY_VALUE and TX_DELAY_VALUE must be set to same value when [RX/TX]_DELAY_FORMAT is set to TIME. Instance: %m", MODULE_NAME, TX_DELAY_VALUE_REG, RX_DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(TX_REFCLK_FREQUENCY_REG != RX_REFCLK_FREQUENCY_REG)) begin
$display("Error: [Unisim %s-141] TX_REFCLK_FREQUENCY = %f is not same as RX_REFCLK_FREQUENCY = %f. [RX/TX]_REFCLK_FREQUENCY attributes must be set to same value. Instance: %m", MODULE_NAME, TX_REFCLK_FREQUENCY_REG, RX_REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(TX_DATA_WIDTH_REG != RX_DATA_WIDTH_REG)) begin
$display("Error: [Unisim %s-142] TX_DATA_WIDTH is set to %d and RX_DATA_WIDTH is set to %d. Both RX_DATA_WIDTH and TX_DATA_WIDTH attributes must be set to same value. Instance: %m", MODULE_NAME, TX_DATA_WIDTH_REG, RX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
assign RX_CLKDIV_in = 1'b1; // tie off
assign RX_CLK_C_B_in = 1'b1; // tie off
assign RX_CLK_C_in = 1'b1; // tie off
assign TX_OCLKDIV_in = 1'b1; // tie off
assign TX_OCLK_in = 1'b1; // tie off
assign IFD_CE_in = 1'b0; // tie off
assign OFD_CE_in = 1'b0; // tie off
assign RX2TX_CASC_RETURN_IN_in = 1'b1; // tie off
assign RX_DATAIN1_in = 1'b0; // tie off
assign TX2RX_CASC_IN_in = 1'b1; // tie off
generate
if ((SIM_DEVICE == "ULTRASCALE_PLUS") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES1") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES2")) begin : generate_block1
SIP_RXTX_BITSLICE_D1 SIP_RXTX_BITSLICE_INST (
.DDR_DIS_DQS (DDR_DIS_DQS_REG),
.ENABLE_PRE_EMPHASIS (ENABLE_PRE_EMPHASIS_REG),
.FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG),
.FIFO_ENABLE (FIFO_ENABLE_REG),
.SPARE (SPARE_REG),
.INIT (INIT_REG),
.LOOPBACK (LOOPBACK_REG),
.NATIVE_ODELAY_BYPASS (NATIVE_ODELAY_BYPASS_REG),
.RX_DATA_TYPE (RX_DATA_TYPE_REG),
.RX_DATA_WIDTH (RX_DATA_WIDTH_REG),
.RX_DC_ADJ_EN (RX_DC_ADJ_EN_REG),
.RX_DELAY_FORMAT (RX_DELAY_FORMAT_REG),
.RX_DELAY_TYPE (RX_DELAY_TYPE_REG),
.RX_DELAY_VALUE (RX_DELAY_VALUE_REG),
.RX_FDLY (RX_FDLY_REG),
.RX_Q4_ROUTETHRU (RX_Q4_ROUTETHRU_REG),
.RX_Q5_ROUTETHRU (RX_Q5_ROUTETHRU_REG),
.RX_REFCLK_FREQUENCY (RX_REFCLK_FREQUENCY_BIN),
.RX_UPDATE_MODE (RX_UPDATE_MODE_REG),
.TBYTE_CTL (TBYTE_CTL_REG),
.TXRX_LOOPBACK (TXRX_LOOPBACK_REG),
.TX_DATA_WIDTH (TX_DATA_WIDTH_REG),
.TX_DC_ADJ_EN (TX_DC_ADJ_EN_REG),
.TX_DELAY_FORMAT (TX_DELAY_FORMAT_REG),
.TX_DELAY_TYPE (TX_DELAY_TYPE_REG),
.TX_DELAY_VALUE (TX_DELAY_VALUE_REG),
.TX_FDLY (TX_FDLY_REG),
.TX_OUTPUT_PHASE_90 (TX_OUTPUT_PHASE_90_REG),
.TX_Q_ROUTETHRU (TX_Q_ROUTETHRU_REG),
.TX_REFCLK_FREQUENCY (TX_REFCLK_FREQUENCY_BIN),
.TX_T_OUT_ROUTETHRU (TX_T_OUT_ROUTETHRU_REG),
.TX_UPDATE_MODE (TX_UPDATE_MODE_REG),
.XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG),
.FIFO_EMPTY (FIFO_EMPTY_out),
.FIFO_WRCLK_OUT (FIFO_WRCLK_OUT_out),
.O (O_out),
.Q (Q_out),
.RX_BIT_CTRL_OUT (RX_BIT_CTRL_OUT_out),
.RX_CNTVALUEOUT (RX_CNTVALUEOUT_out),
.TX2RX_CASC_OUT (TX2RX_CASC_OUT_out),
.TX_BIT_CTRL_OUT (TX_BIT_CTRL_OUT_out),
.TX_CNTVALUEOUT (TX_CNTVALUEOUT_out),
.T_OUT (T_OUT_out),
.D (D_in),
.DATAIN (DATAIN_in),
.FIFO_RD_CLK (FIFO_RD_CLK_in),
.FIFO_RD_EN (FIFO_RD_EN_in),
.IFD_CE (IFD_CE_in),
.OFD_CE (OFD_CE_in),
.RX2TX_CASC_RETURN_IN (RX2TX_CASC_RETURN_IN_in),
.RX_BIT_CTRL_IN (RX_BIT_CTRL_IN_in),
.RX_CE (RX_CE_in),
.RX_CLK (RX_CLK_in),
.RX_CLKDIV (RX_CLKDIV_in),
.RX_CLK_C (RX_CLK_C_in),
.RX_CLK_C_B (RX_CLK_C_B_in),
.RX_CNTVALUEIN (RX_CNTVALUEIN_in),
.RX_DATAIN1 (RX_DATAIN1_in),
.RX_EN_VTC (RX_EN_VTC_in),
.RX_INC (RX_INC_in),
.RX_LOAD (RX_LOAD_in),
.RX_RST (RX_RST_in),
.RX_RST_DLY (RX_RST_DLY_in),
.T (T_in),
.TBYTE_IN (TBYTE_IN_in),
.TX2RX_CASC_IN (TX2RX_CASC_IN_in),
.TX_BIT_CTRL_IN (TX_BIT_CTRL_IN_in),
.TX_CE (TX_CE_in),
.TX_CLK (TX_CLK_in),
.TX_CNTVALUEIN (TX_CNTVALUEIN_in),
.TX_EN_VTC (TX_EN_VTC_in),
.TX_INC (TX_INC_in),
.TX_LOAD (TX_LOAD_in),
.TX_OCLK (TX_OCLK_in),
.TX_OCLKDIV (TX_OCLKDIV_in),
.TX_RST (TX_RST_in),
.TX_RST_DLY (TX_RST_DLY_in),
.SIM_IDELAY_DATAIN0(IDELAY_DATAIN0_out),
.SIM_IDELAY_DATAOUT(IDELAY_DATAOUT_out),
.SIM_ODELAY_DATAIN0(ODELAY_DATAIN0_out),
.SIM_ODELAY_DATAOUT(ODELAY_DATAOUT_out),
.GSR (glblGSR)
);
end else if (SIM_DEVICE == "ULTRASCALE") begin : generate_block1
SIP_RXTX_BITSLICE_K2 SIP_RXTX_BITSLICE_INST (
.DDR_DIS_DQS (DDR_DIS_DQS_REG),
.ENABLE_PRE_EMPHASIS (ENABLE_PRE_EMPHASIS_REG),
.FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG),
.INIT (INIT_REG),
.LOOPBACK (LOOPBACK_REG),
.NATIVE_ODELAY_BYPASS (NATIVE_ODELAY_BYPASS_REG),
.RX_DATA_TYPE (RX_DATA_TYPE_REG),
.RX_DATA_WIDTH (RX_DATA_WIDTH_REG),
.RX_DC_ADJ_EN (RX_DC_ADJ_EN_REG),
.RX_DELAY_FORMAT (RX_DELAY_FORMAT_REG),
.RX_DELAY_TYPE (RX_DELAY_TYPE_REG),
.RX_DELAY_VALUE (RX_DELAY_VALUE_REG),
.RX_FDLY (RX_FDLY_REG),
.RX_Q4_ROUTETHRU (RX_Q4_ROUTETHRU_REG),
.RX_Q5_ROUTETHRU (RX_Q5_ROUTETHRU_REG),
.RX_REFCLK_FREQUENCY (RX_REFCLK_FREQUENCY_BIN),
.RX_UPDATE_MODE (RX_UPDATE_MODE_REG),
.SIM_VERSION (SIM_VERSION_BIN),
.TBYTE_CTL (TBYTE_CTL_REG),
.TXRX_LOOPBACK (TXRX_LOOPBACK_REG),
.TX_DATA_WIDTH (TX_DATA_WIDTH_REG),
.TX_DC_ADJ_EN (TX_DC_ADJ_EN_REG),
.TX_DELAY_FORMAT (TX_DELAY_FORMAT_REG),
.TX_DELAY_TYPE (TX_DELAY_TYPE_REG),
.TX_DELAY_VALUE (TX_DELAY_VALUE_REG),
.TX_FDLY (TX_FDLY_REG),
.TX_OUTPUT_PHASE_90 (TX_OUTPUT_PHASE_90_REG),
.TX_Q_ROUTETHRU (TX_Q_ROUTETHRU_REG),
.TX_REFCLK_FREQUENCY (TX_REFCLK_FREQUENCY_BIN),
.TX_T_OUT_ROUTETHRU (TX_T_OUT_ROUTETHRU_REG),
.TX_UPDATE_MODE (TX_UPDATE_MODE_REG),
.XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG),
.FIFO_EMPTY (FIFO_EMPTY_out),
.FIFO_WRCLK_OUT (FIFO_WRCLK_OUT_out),
.O (O_out),
.Q (Q_out),
.RX_BIT_CTRL_OUT (RX_BIT_CTRL_OUT_out),
.RX_CNTVALUEOUT (RX_CNTVALUEOUT_out),
.TX2RX_CASC_OUT (TX2RX_CASC_OUT_out),
.TX_BIT_CTRL_OUT (TX_BIT_CTRL_OUT_out),
.TX_CNTVALUEOUT (TX_CNTVALUEOUT_out),
.T_OUT (T_OUT_out),
.D (D_in),
.DATAIN (DATAIN_in),
.FIFO_RD_CLK (FIFO_RD_CLK_in),
.FIFO_RD_EN (FIFO_RD_EN_in),
.IFD_CE (IFD_CE_in),
.OFD_CE (OFD_CE_in),
.RX2TX_CASC_RETURN_IN (RX2TX_CASC_RETURN_IN_in),
.RX_BIT_CTRL_IN (RX_BIT_CTRL_IN_in),
.RX_CE (RX_CE_in),
.RX_CLK (RX_CLK_in),
.RX_CLKDIV (RX_CLKDIV_in),
.RX_CLK_C (RX_CLK_C_in),
.RX_CLK_C_B (RX_CLK_C_B_in),
.RX_CNTVALUEIN (RX_CNTVALUEIN_in),
.RX_DATAIN1 (RX_DATAIN1_in),
.RX_EN_VTC (RX_EN_VTC_in),
.RX_INC (RX_INC_in),
.RX_LOAD (RX_LOAD_in),
.RX_RST (RX_RST_in),
.RX_RST_DLY (RX_RST_DLY_in),
.T (T_in),
.TBYTE_IN (TBYTE_IN_in),
.TX2RX_CASC_IN (TX2RX_CASC_IN_in),
.TX_BIT_CTRL_IN (TX_BIT_CTRL_IN_in),
.TX_CE (TX_CE_in),
.TX_CLK (TX_CLK_in),
.TX_CNTVALUEIN (TX_CNTVALUEIN_in),
.TX_EN_VTC (TX_EN_VTC_in),
.TX_INC (TX_INC_in),
.TX_LOAD (TX_LOAD_in),
.TX_OCLK (TX_OCLK_in),
.TX_OCLKDIV (TX_OCLKDIV_in),
.TX_RST (TX_RST_in),
.TX_RST_DLY (TX_RST_DLY_in),
.SIM_IDELAY_DATAIN0(IDELAY_DATAIN0_out),
.SIM_IDELAY_DATAOUT(IDELAY_DATAOUT_out),
.SIM_ODELAY_DATAIN0(ODELAY_DATAIN0_out),
.SIM_ODELAY_DATAOUT(ODELAY_DATAOUT_out),
.GSR (glblGSR)
);
end
endgenerate
`ifdef XIL_TIMING
wire rx_clk_en_n;
wire rx_clk_en_p;
wire tx_clk_en_n;
wire tx_clk_en_p;
assign rx_clk_en_n = IS_RX_CLK_INVERTED_BIN;
assign rx_clk_en_p = ~IS_RX_CLK_INVERTED_BIN;
assign tx_clk_en_n = IS_TX_CLK_INVERTED_BIN;
assign tx_clk_en_p = ~IS_TX_CLK_INVERTED_BIN;
`endif
specify
(DATAIN => Q[4]) = (0:0:0, 0:0:0);
(DATAIN => Q[5]) = (0:0:0, 0:0:0);
(DATAIN => RX_BIT_CTRL_OUT[9]) = (0:0:0, 0:0:0);
(D[0] => O) = (0:0:0, 0:0:0);
(D[1] => T_OUT) = (0:0:0, 0:0:0);
(FIFO_RD_CLK => FIFO_EMPTY) = (100:100:100, 100:100:100);
(FIFO_RD_CLK => Q[0]) = (100:100:100, 100:100:100);
(FIFO_RD_CLK => Q[1]) = (100:100:100, 100:100:100);
(FIFO_RD_CLK => Q[2]) = (100:100:100, 100:100:100);
(FIFO_RD_CLK => Q[3]) = (100:100:100, 100:100:100);
(FIFO_RD_CLK => Q[4]) = (100:100:100, 100:100:100);
(FIFO_RD_CLK => Q[5]) = (100:100:100, 100:100:100);
(FIFO_RD_CLK => Q[6]) = (100:100:100, 100:100:100);
(FIFO_RD_CLK => Q[7]) = (100:100:100, 100:100:100);
(RX_BIT_CTRL_IN[20] => FIFO_WRCLK_OUT) = (0:0:0, 0:0:0);
(RX_CLK => RX_CNTVALUEOUT[0]) = (100:100:100, 100:100:100);
(RX_CLK => RX_CNTVALUEOUT[1]) = (100:100:100, 100:100:100);
(RX_CLK => RX_CNTVALUEOUT[2]) = (100:100:100, 100:100:100);
(RX_CLK => RX_CNTVALUEOUT[3]) = (100:100:100, 100:100:100);
(RX_CLK => RX_CNTVALUEOUT[4]) = (100:100:100, 100:100:100);
(RX_CLK => RX_CNTVALUEOUT[5]) = (100:100:100, 100:100:100);
(RX_CLK => RX_CNTVALUEOUT[6]) = (100:100:100, 100:100:100);
(RX_CLK => RX_CNTVALUEOUT[7]) = (100:100:100, 100:100:100);
(RX_CLK => RX_CNTVALUEOUT[8]) = (100:100:100, 100:100:100);
(TX_CLK => TX_CNTVALUEOUT[0]) = (100:100:100, 100:100:100);
(TX_CLK => TX_CNTVALUEOUT[1]) = (100:100:100, 100:100:100);
(TX_CLK => TX_CNTVALUEOUT[2]) = (100:100:100, 100:100:100);
(TX_CLK => TX_CNTVALUEOUT[3]) = (100:100:100, 100:100:100);
(TX_CLK => TX_CNTVALUEOUT[4]) = (100:100:100, 100:100:100);
(TX_CLK => TX_CNTVALUEOUT[5]) = (100:100:100, 100:100:100);
(TX_CLK => TX_CNTVALUEOUT[6]) = (100:100:100, 100:100:100);
(TX_CLK => TX_CNTVALUEOUT[7]) = (100:100:100, 100:100:100);
(TX_CLK => TX_CNTVALUEOUT[8]) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge FIFO_RD_CLK, 0:0:0, notifier);
$period (negedge RX_BIT_CTRL_IN[20], 0:0:0, notifier);
$period (negedge RX_CLK, 0:0:0, notifier);
$period (negedge TX_BIT_CTRL_IN[25], 0:0:0, notifier);
$period (negedge TX_BIT_CTRL_IN[26], 0:0:0, notifier);
$period (negedge TX_CLK, 0:0:0, notifier);
$period (posedge FIFO_RD_CLK, 0:0:0, notifier);
$period (posedge RX_BIT_CTRL_IN[20], 0:0:0, notifier);
$period (posedge RX_CLK, 0:0:0, notifier);
$period (posedge TX_BIT_CTRL_IN[25], 0:0:0, notifier);
$period (posedge TX_BIT_CTRL_IN[26], 0:0:0, notifier);
$period (posedge TX_CLK, 0:0:0, notifier);
$setuphold (negedge RX_CLK, negedge RX_CE, 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CE_delay);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[0]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[1]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[2]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[3]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[4]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[5]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[6]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[7]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[8]);
$setuphold (negedge RX_CLK, negedge RX_INC, 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_INC_delay);
$setuphold (negedge RX_CLK, negedge RX_LOAD, 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_LOAD_delay);
$setuphold (negedge RX_CLK, posedge RX_CE, 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CE_delay);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[0]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[1]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[2]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[3]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[4]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[5]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[6]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[7]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_CNTVALUEIN_delay[8]);
$setuphold (negedge RX_CLK, posedge RX_INC, 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_INC_delay);
$setuphold (negedge RX_CLK, posedge RX_LOAD, 0:0:0, 0:0:0, notifier, rx_clk_en_n, rx_clk_en_n, RX_CLK_delay, RX_LOAD_delay);
$setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[0], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[0]);
$setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[1], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[1]);
$setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[2], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[2]);
$setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[3], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[3]);
$setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[0], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[0]);
$setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[1], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[1]);
$setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[2], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[2]);
$setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[3], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[25], D_delay[3]);
$setuphold (negedge TX_CLK, negedge TX_CE, 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CE_delay);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[0]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[1]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[2]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[3]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[4]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[5]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[6]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[7]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[8]);
$setuphold (negedge TX_CLK, negedge TX_INC, 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_INC_delay);
$setuphold (negedge TX_CLK, negedge TX_LOAD, 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_LOAD_delay);
$setuphold (negedge TX_CLK, posedge TX_CE, 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CE_delay);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[0]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[1]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[2]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[3]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[4]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[5]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[6]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[7]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_CNTVALUEIN_delay[8]);
$setuphold (negedge TX_CLK, posedge TX_INC, 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_INC_delay);
$setuphold (negedge TX_CLK, posedge TX_LOAD, 0:0:0, 0:0:0, notifier, tx_clk_en_n, tx_clk_en_n, TX_CLK_delay, TX_LOAD_delay);
$setuphold (posedge FIFO_RD_CLK, negedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier, , , FIFO_RD_CLK_delay, FIFO_RD_EN_delay);
$setuphold (posedge FIFO_RD_CLK, posedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier, , , FIFO_RD_CLK_delay, FIFO_RD_EN_delay);
$setuphold (posedge RX_CLK, negedge RX_CE, 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CE_delay);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[0]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[1]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[2]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[3]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[4]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[5]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[6]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[7]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[8]);
$setuphold (posedge RX_CLK, negedge RX_INC, 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_INC_delay);
$setuphold (posedge RX_CLK, negedge RX_LOAD, 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_LOAD_delay);
$setuphold (posedge RX_CLK, posedge RX_CE, 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CE_delay);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[0]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[1]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[2]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[3]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[4]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[5]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[6]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[7]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_CNTVALUEIN_delay[8]);
$setuphold (posedge RX_CLK, posedge RX_INC, 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_INC_delay);
$setuphold (posedge RX_CLK, posedge RX_LOAD, 0:0:0, 0:0:0, notifier, rx_clk_en_p, rx_clk_en_p, RX_CLK_delay, RX_LOAD_delay);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[0], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[0]);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[1], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[1]);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[2], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[2]);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[3], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[3]);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[4], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[4]);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[5], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[5]);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[6], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[6]);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[7], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[7]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[0], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[0]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[1], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[1]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[2], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[2]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[3], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[3]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[4], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[4]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[5], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[5]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[6], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[6]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[7], 0:0:0, 0:0:0, notifier, , , TX_BIT_CTRL_IN_delay[26], D_delay[7]);
$setuphold (posedge TX_CLK, negedge TX_CE, 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CE_delay);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[0]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[2]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[3]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[4]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[5]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[6]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[7]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[8]);
$setuphold (posedge TX_CLK, negedge TX_INC, 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_INC_delay);
$setuphold (posedge TX_CLK, negedge TX_LOAD, 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_LOAD_delay);
$setuphold (posedge TX_CLK, posedge TX_CE, 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CE_delay);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[0]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[2]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[3]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[4]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[5]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[6]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[7]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_CNTVALUEIN_delay[8]);
$setuphold (posedge TX_CLK, posedge TX_INC, 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_INC_delay);
$setuphold (posedge TX_CLK, posedge TX_LOAD, 0:0:0, 0:0:0, notifier, tx_clk_en_p, tx_clk_en_p, TX_CLK_delay, TX_LOAD_delay);
$width (negedge FIFO_RD_CLK, 0:0:0, 0, notifier);
$width (negedge RX_BIT_CTRL_IN[20], 0:0:0, 0, notifier);
$width (negedge RX_CLK, 0:0:0, 0, notifier);
$width (negedge TX_BIT_CTRL_IN[25], 0:0:0, 0, notifier);
$width (negedge TX_BIT_CTRL_IN[26], 0:0:0, 0, notifier);
$width (negedge TX_CLK, 0:0:0, 0, notifier);
$width (posedge FIFO_RD_CLK, 0:0:0, 0, notifier);
$width (posedge RX_BIT_CTRL_IN[20], 0:0:0, 0, notifier);
$width (posedge RX_CLK, 0:0:0, 0, notifier);
$width (posedge TX_BIT_CTRL_IN[25], 0:0:0, 0, notifier);
$width (posedge TX_BIT_CTRL_IN[26], 0:0:0, 0, notifier);
$width (posedge TX_CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
`include "verilated.v"
`define STRINGIFY(x) `"x`"
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [63:0] crc;
integer fd;
integer fdtmp;
t_case_write2_tasks tasks ();
integer cyc; initial cyc=0;
always @ (posedge clk) begin
$fwrite(fd, "[%0d] crc=%x ", cyc, crc);
tasks.big_case(fd, crc[31:0]);
$fwrite(fd, "\n");
end
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==1) begin
crc <= 64'h00000000_00000097;
$write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log\n"});
fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log"}, "w");
fd <= fdtmp;
end
if (cyc==90) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Convert_Data_Type1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Convert_Data_Type1
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/Convert_Data_Type1
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Convert_Data_Type1
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En24
output signed [35:0] Out1; // sfix36_En23
wire signed [35:0] Data_Type_Conversion_out1; // sfix36_En23
// <S10>/Data Type Conversion
assign Data_Type_Conversion_out1 = {In1[35], In1[35:1]};
assign Out1 = Data_Type_Conversion_out1;
endmodule // velocityControlHdl_Convert_Data_Type1
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NAND4BB_FUNCTIONAL_PP_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand4bb (
VPWR,
VGND,
Y ,
A_N ,
B_N ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
// Local signals
wire D nand0_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4BB_FUNCTIONAL_PP_V |
module test;
reg [0:0] io_in_valid;
reg [31:0] io_in_bits;
reg [0:0] io_out_ready;
reg [0:0] io_pcIn_valid;
reg [0:0] io_pcIn_bits_request;
reg [15:0] io_pcIn_bits_moduleId;
reg [7:0] io_pcIn_bits_portId;
reg [15:0] io_pcIn_bits_pcValue;
reg [3:0] io_pcIn_bits_pcType;
wire [0:0] io_in_ready;
wire [0:0] io_out_valid;
wire [31:0] io_out_bits;
wire [0:0] io_pcOut_valid;
wire [0:0] io_pcOut_bits_request;
wire [15:0] io_pcOut_bits_moduleId;
wire [7:0] io_pcOut_bits_portId;
wire [15:0] io_pcOut_bits_pcValue;
wire [3:0] io_pcOut_bits_pcType;
reg clk = 0;
reg reset = 1;
initial begin
reset = 1;
#250 reset = 0;
end
always #100 clk = ~clk;
Offloaded
Offloaded(
.clk(clk),
.reset(reset),
.io_in_valid(io_in_valid),
.io_in_bits(io_in_bits),
.io_out_ready(io_out_ready),
.io_pcIn_valid(io_pcIn_valid),
.io_pcIn_bits_request(io_pcIn_bits_request),
.io_pcIn_bits_moduleId(io_pcIn_bits_moduleId),
.io_pcIn_bits_portId(io_pcIn_bits_portId),
.io_pcIn_bits_pcValue(io_pcIn_bits_pcValue),
.io_pcIn_bits_pcType(io_pcIn_bits_pcType),
.io_in_ready(io_in_ready),
.io_out_valid(io_out_valid),
.io_out_bits(io_out_bits),
.io_pcOut_valid(io_pcOut_valid),
.io_pcOut_bits_request(io_pcOut_bits_request),
.io_pcOut_bits_moduleId(io_pcOut_bits_moduleId),
.io_pcOut_bits_portId(io_pcOut_bits_portId),
.io_pcOut_bits_pcValue(io_pcOut_bits_pcValue),
.io_pcOut_bits_pcType(io_pcOut_bits_pcType)
);
integer count;
always @(negedge clk) begin;
#50;
// if (!reset) count = $fscanf('h80000000, "%x %x %x %x %x %x %x %x %x", io_in_valid, io_in_bits, io_out_ready, io_pcIn_valid, io_pcIn_bits_request, io_pcIn_bits_moduleId, io_pcIn_bits_portId, io_pcIn_bits_pcValue, io_pcIn_bits_pcType);
// if (count == -1) $finish(1);
io_in_valid = 1;
io_in_bits = 1;
io_out_ready = 1;
end
always @(posedge clk) begin
if (!reset) $display("0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", io_in_ready, io_out_valid, io_out_bits, io_pcOut_valid, io_pcOut_bits_request, io_pcOut_bits_moduleId, io_pcOut_bits_portId, io_pcOut_bits_pcValue, io_pcOut_bits_pcType);
end
endmodule
|
/******************************************************************************
* File Name : encode_ctl.v
* Version : 0.1
* Date : 2008 02 27
* Description: encode control module
* Dependencies:
*
*
* Company: Beijing Soul
*
* BUG:
*
*****************************************************************************/
module encode_ctl(/*AUTOARG*/
// Outputs
hraddr, cnt_output_enable, cnt_len, cnt_output,
cnt_finish,
// Inputs
clk, rst, data_valid, data_empty, hash_data, hash_data1,
data_d1, data_d2, hash_ref, iidx, hdata, data, hash_d1,
hash_data_d1
);
parameter LZF_WIDTH = 20;
input clk, rst;
input data_valid;
input data_empty;
input [7:0] hash_data, hash_data1, data_d1, data_d2;
input [LZF_WIDTH-1:0] hash_ref, iidx;
input [7:0] hdata, data, hash_d1;
output [10:0] hraddr;
input hash_data_d1;
/*AUTOREG*/
reg off_valid;
reg iidx_window;
always @(posedge clk or posedge rst)
begin
if (rst)
iidx_window <= #1 0;
else if (iidx[11]) /* 2048 */
iidx_window <= #1 1;
end
reg [LZF_WIDTH-1:0] min_off, max_off;
always @(posedge clk or posedge rst)
begin
if (rst)
min_off <= #1 0;
else if (data_valid && iidx_window)
min_off <= #1 min_off + 1;
end
always @(posedge clk)
begin
if (data_valid)
max_off <= #1 iidx;
end
always @(/*AS*/hash_ref or max_off or min_off)
begin
if (hash_ref > min_off && hash_ref < max_off)
off_valid = 1;
else
off_valid = 0;
end
reg [10:0] off;
always @(/*AS*/hash_ref or max_off)
begin
off = max_off - hash_ref;
end
parameter [2:0]
S_IDLE = 3'h0,
S_SEARCH = 3'h1,
S_TR = 3'h2,
S_MATCH = 3'h3,
S_DELAY = 3'h4,
S_END = 3'h5,
S_DONE = 3'h6,
S_STOP = 3'h7;
reg [2:0] state, state_next;
always @(posedge clk or posedge rst)
begin
if (rst)
state <= #1 S_IDLE;
else
state <= #1 state_next;
end
reg [3:0] cnt, cnt_next;
always @(posedge clk)
begin
cnt <= #1 cnt_next;
end
reg cnt_count, cnt_load;
reg rallow;
reg [10:0] raddr_plus_one;
reg [10:0] raddr_reg;
assign hraddr = rallow ? raddr_plus_one : raddr_reg;
always @(/*AS*/cnt_count or cnt_load)
begin
if (cnt_load || cnt_count)
rallow = 1;
else
rallow = 0;
end
reg [LZF_WIDTH-1:0] hash_ref_plus_one;
always @(/*AS*/hash_ref)
hash_ref_plus_one = hash_ref + 1'b1;
always @(posedge clk)
begin
if (cnt_load)
raddr_plus_one <= #1 hash_ref_plus_one + 1'b1;
else if (cnt_count)
raddr_plus_one <= #1 raddr_plus_one + 1'b1;
end
always @(posedge clk)
begin
if (cnt_load)
raddr_reg <= #1 hash_ref_plus_one;
else if (cnt_count)
raddr_reg <= #1 raddr_plus_one;
end
reg cnt_big7, cnt_big7_next;
always @(posedge clk)
begin
cnt_big7 <= #1 cnt_big7_next;
end
always @(/*AS*/cnt or cnt_big7 or cnt_count or cnt_load)
begin
cnt_next = 0;
cnt_big7_next = 0;
if (cnt_load) begin
cnt_next = 2;
cnt_big7_next = 0;
end else if (cnt_count) begin
cnt_next = cnt + 1;
if (cnt_big7 == 0) begin
if (cnt == 4'h7) begin
cnt_big7_next = 1;
cnt_next = 0;
end else
cnt_big7_next = 0;
end else begin
cnt_big7_next = 1;
end
if (cnt == 4'hf)
cnt_next = 1;
end else begin
cnt_next = cnt;
cnt_big7_next = cnt_big7;
end
end // always @ (...
output cnt_output_enable;
output [3:0] cnt_len;
output [12:0] cnt_output;
output cnt_finish;
reg [2:0] dummy_cnt;
always @(posedge clk or posedge rst)
begin
if (rst)
dummy_cnt <= #1 0;
else if (state == S_DONE)
dummy_cnt <= #1 dummy_cnt + 1'b1;
end
reg cnt_finish;
reg cnt_output_enable, cnt_output_enable_next;
reg [12:0] cnt_output, cnt_output_next;
reg [3:0] cnt_len, cnt_len_next;
always @(/*AS*/cnt or cnt_big7 or data_d1 or data_d2
or data_empty or data_valid or dummy_cnt
or hash_data or hash_data_d1 or hdata
or off_valid or state)
begin
state_next = S_IDLE; // state
cnt_output_enable_next = 0; // will output the length data
cnt_load = 0;
cnt_count = 0;
case (state)
S_IDLE: begin
if (data_valid)
state_next = S_DELAY;
else
state_next = S_IDLE;
end
S_DELAY: begin
if (data_valid)
state_next = S_SEARCH;
else
state_next = S_DELAY;
end
S_SEARCH: begin /* cmp d2 with hash data */
if (data_valid) begin
if (data_d2 == hash_data && off_valid) begin
state_next = S_TR;
cnt_load = 1;
cnt_output_enable_next = 1;
end else begin
cnt_output_enable_next = 1;
state_next = S_SEARCH;
end
end else if (data_empty) begin
cnt_output_enable_next = 1;
state_next = S_END;
end else
state_next = S_SEARCH;
end // case: S_SEARCH
S_TR: begin // driver the history memory
if (data_valid && hash_data_d1) begin
cnt_count = 1;
state_next = S_MATCH;
end else if (data_valid) begin
state_next = S_SEARCH;
cnt_output_enable_next = 1;
end else if (data_empty) begin
cnt_output_enable_next = 1;
state_next = S_END;
end else begin
state_next = S_TR;
end
end
S_MATCH: begin /* cmp d2 with history */
if (data_valid) begin
if (data_d1 == hdata) begin
state_next = S_MATCH;
cnt_count = 1;
if (cnt == 4'h7 && cnt_big7 == 0)
cnt_output_enable_next = 1;
else if (cnt == 4'hf)
cnt_output_enable_next = 1;
end else begin // if (prev_data == history_do)
state_next = S_SEARCH;
cnt_output_enable_next = 1;
end
end else if (data_empty) begin // if (stream_valid)
state_next = S_END;
cnt_output_enable_next = 1;
end else
state_next = S_MATCH;
end // case: S_MATCH
S_END: begin /* output end mark */
state_next = S_DONE;
cnt_output_enable_next = 1;
end
S_DONE: begin /* output fake data */
state_next = S_DONE;
cnt_output_enable_next = 1;
if (&dummy_cnt) /* 4 X F = 64 */
state_next = S_STOP;
end
S_STOP: begin
state_next = S_STOP;
end
endcase // case(state)
end // always @ (...
always @(posedge clk)
begin
cnt_output <= #1 cnt_output_next;
cnt_len <= #1 cnt_len_next;
end
always @(posedge clk or posedge rst)
begin
if (rst)
cnt_output_enable <= #1 0;
else
cnt_output_enable <= #1 cnt_output_enable_next;
end
always @(/*AS*/state)
cnt_finish = state == S_STOP;
/* state == S_SEARCH lit char with offset */
reg [3:0] encode_len_s;
reg [12:0] encode_data_s;
/* state == S_MATCH */
reg [3:0] encode_len_m;
reg [12:0] encode_data_m;
/* length package */
reg [3:0] encode_len;
reg [12:0] encode_data;
always @(/*AS*/cnt_output_enable_next or encode_data_m
or encode_data_s or encode_len_m or encode_len_s
or state)
begin
cnt_output_next = 0;
cnt_len_next= 0;
if (cnt_output_enable_next && state == S_SEARCH) begin
/* output offset and liter data */
cnt_output_next = encode_data_s;
cnt_len_next = encode_len_s;
end else if (cnt_output_enable_next && state == S_END) begin
/* output end marker */
cnt_output_next = 9'b110000000;
cnt_len_next = 4'h9;
end else if (cnt_output_enable_next && state == S_DONE) begin
/* output flush data */
cnt_output_next = 9'b000000000;
cnt_len_next = 4'hf;
end else begin
cnt_output_next = encode_data_m;
cnt_len_next = encode_len_m;
end
end // always @ (...
always @(/*AS*/cnt or cnt_big7 or cnt_count
or encode_data or encode_len)
begin
if (cnt_big7 == 0) begin
if (cnt_count) begin
encode_data_m = 4'hf;
encode_len_m = 4'h4;
end else begin
encode_data_m = encode_data;
encode_len_m = encode_len;
end
end else begin
if (cnt == 4'hf && cnt_count == 0) begin
encode_data_m = {4'hf, 4'h0};
encode_len_m = 4'h8;
end else begin
encode_data_m = cnt;
encode_len_m = 4'h4;
end
end // else: !if(cnt_big7 == 0)
end
always @(/*AS*/cnt_load or data_d2 or off)
begin
encode_len_s = 0;
encode_data_s = 0;
if (cnt_load) begin /* offset */
if (off[10:07] == 0) begin /* < 128 */
encode_len_s = 4'h9;
encode_data_s = {2'b11, off[6:0]};
end else begin
encode_len_s = 4'hd;
encode_data_s = {2'b10, off[10:0]};
end
end else begin
encode_len_s = 4'h9;
encode_data_s = data_d2;
end // else: !if(cnt_load)
end
always @(/*AS*/cnt)
begin
encode_len = 0;
encode_data = 0;
case (cnt[2:0])
3'h2: {encode_data, encode_len} = {2'b00, 4'h2};
3'h3: {encode_data, encode_len} = {2'b01, 4'h2};
3'h4: {encode_data, encode_len} = {2'b10, 4'h2};
3'h5: {encode_data, encode_len} = {2'b11, 2'b00, 4'h4};
3'h6: {encode_data, encode_len} = {2'b11, 2'b01, 4'h4};
3'h7: {encode_data, encode_len} = {2'b11, 2'b10, 4'h4};
endcase
end // always @ (...
/*
* cnt_output_enable
* cnt_big7
* cnt
*
* big7 finish
* 0 1 <= 7 output encode(data/_len)
* 1 1 > 7 output 4 bit cnt
* 1 0 if big7==0 && cnt==7+1 output 4'hf and set big7=1
* then big7==1 && cnt=4'hf output 4'hf
*
*/
endmodule // encode_ctl
// Local Variables:
// verilog-library-directories:("." "../../../../common/" "../../encode/src" "../../encode_ctl/src/" "../../encode_out/src/" "../../encode_dp/src/")
// verilog-library-files:("")
// verilog-library-extensions:(".v" ".h")
// End:
|
module DoubleRegisters(
clk,
bus_in, bus_out1, bus_out2,
num1, num2,
cs_h_in, cs_l_in, cs_16_in,
cs_h_out1, cs_l_out1, cs_16_out1,
cs_h_out2, cs_l_out2, cs_16_out2);
input [15:0] bus_in;
output reg [15:0] bus_out1, bus_out2;
input [1:0] num1, num2;
input cs_h_in, cs_l_in, cs_16_in;
input cs_h_out1, cs_l_out1, cs_16_out1;
input cs_h_out2, cs_l_out2, cs_16_out2;
input clk;
(* ram_style="block" *)
reg [7:0] store_h[3:0] /* verilator public_flat */;
(* ram_style="block" *)
reg [7:0] store_l[3:0] /* verilator public_flat */;
always @ (posedge clk)
if (cs_h_out1)
bus_out1 <= {8'h00, store_h[num1]};
else if (cs_l_out1)
bus_out1 <= {8'h00, store_l[num1]};
else if (cs_16_out1)
bus_out1 <= {store_h[num1], store_l[num1]};
else
bus_out1 <= 16'bz;
always @ (posedge clk)
if (cs_h_out2)
bus_out2 <= {8'h00, store_h[num2]};
else if (cs_l_out2)
bus_out2 <= {8'h00, store_l[num2]};
else if (cs_16_out2)
bus_out2 <= {store_h[num2], store_l[num2]};
else
bus_out2 <= 16'bz;
always @(posedge clk)
if (cs_h_in)
store_h[num1] <= bus_in[7:0];
else if (cs_16_in) begin
store_h[num1] <= bus_in[15:8];
end
always @(posedge clk)
if (cs_l_in)
store_l[num1] <= bus_in[7:0];
else if (cs_16_in) begin
store_l[num1] <= bus_in[7:0];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NOR3B_FUNCTIONAL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor3b (
VPWR,
VGND,
Y ,
A ,
B ,
C_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C_N ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_FUNCTIONAL_V |
module processor_test (input wire clk,
input wire pc_reset,
input wire pc_enable
);
// Step 1
wire [31:0] pc_in;
wire [31:0] pc_out;
// Step 2
wire [31:0] pc_plus_four;
wire [31:0] add0_in1;
assign add0_in1 = 32'd4;
// Step 3
wire [31:0] alu_data_output;
wire [31:0] readData2;
wire [31:0] mem_data_out;
wire [31:0] instr;
// Step 4
wire reg_dst, jump, branch, mem_to_reg, ctrl_mem_read_wire, ctrl_mem_write_wire, alu_src, reg_write;
wire [1:0] alu_op;
//************************ STEP 1 - PC ************************************
pc pc0(
.in (pc_in), //32 bits
.clk,
.rst (pc_reset),
.en (pc_enable),
.out (pc_out) //32 bits
);
//******************** STEP 2 - PC + 4 ADDER ********************************
Adder_32b pc_adder(
.clk,
.input0 (pc_out),
.input1 (add0_in1),
.out (pc_plus_four)
);
//******************* STEP 3 - INSTRUCTION MEM *******************************
Memory mem0(
.inst_addr (pc_out), //32 bits
.instr, //32 bits
.data_addr (alu_data_output), //32 bits
.data_in (readData2), //32 bits
.mem_read (ctrl_mem_read_wire),
.mem_write (ctrl_mem_write_wire),
.data_out (mem_data_out) //32 bits
);
//******************* STEP 4 - CONTROL *******************************
/*
Control ctrl0(
.clk,
.opcode (instr[31:26]), //6 bits
.reg_dst,
.jump,
.branch,
.ctrl_mem_read(ctrl_mem_read_wire),
.mem_to_reg,
.ctrl_mem_write(ctrl_mem_write_wire),
.alu_src,
.reg_write,
.alu_op //2 bits
);
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_4_V
`define SKY130_FD_SC_HD__O221AI_4_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o221ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o221ai_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_4_V
|
// ik_swift_mm_interconnect_0.v
// This file was auto-generated from altera_merlin_interconnect_wrapper_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1.1 166 at 2014.05.05.12:42:32
`timescale 1 ps / 1 ps
module ik_swift_mm_interconnect_0 (
input wire [11:0] hps_0_h2f_lw_axi_master_awid, // hps_0_h2f_lw_axi_master.awid
input wire [20:0] hps_0_h2f_lw_axi_master_awaddr, // .awaddr
input wire [3:0] hps_0_h2f_lw_axi_master_awlen, // .awlen
input wire [2:0] hps_0_h2f_lw_axi_master_awsize, // .awsize
input wire [1:0] hps_0_h2f_lw_axi_master_awburst, // .awburst
input wire [1:0] hps_0_h2f_lw_axi_master_awlock, // .awlock
input wire [3:0] hps_0_h2f_lw_axi_master_awcache, // .awcache
input wire [2:0] hps_0_h2f_lw_axi_master_awprot, // .awprot
input wire hps_0_h2f_lw_axi_master_awvalid, // .awvalid
output wire hps_0_h2f_lw_axi_master_awready, // .awready
input wire [11:0] hps_0_h2f_lw_axi_master_wid, // .wid
input wire [31:0] hps_0_h2f_lw_axi_master_wdata, // .wdata
input wire [3:0] hps_0_h2f_lw_axi_master_wstrb, // .wstrb
input wire hps_0_h2f_lw_axi_master_wlast, // .wlast
input wire hps_0_h2f_lw_axi_master_wvalid, // .wvalid
output wire hps_0_h2f_lw_axi_master_wready, // .wready
output wire [11:0] hps_0_h2f_lw_axi_master_bid, // .bid
output wire [1:0] hps_0_h2f_lw_axi_master_bresp, // .bresp
output wire hps_0_h2f_lw_axi_master_bvalid, // .bvalid
input wire hps_0_h2f_lw_axi_master_bready, // .bready
input wire [11:0] hps_0_h2f_lw_axi_master_arid, // .arid
input wire [20:0] hps_0_h2f_lw_axi_master_araddr, // .araddr
input wire [3:0] hps_0_h2f_lw_axi_master_arlen, // .arlen
input wire [2:0] hps_0_h2f_lw_axi_master_arsize, // .arsize
input wire [1:0] hps_0_h2f_lw_axi_master_arburst, // .arburst
input wire [1:0] hps_0_h2f_lw_axi_master_arlock, // .arlock
input wire [3:0] hps_0_h2f_lw_axi_master_arcache, // .arcache
input wire [2:0] hps_0_h2f_lw_axi_master_arprot, // .arprot
input wire hps_0_h2f_lw_axi_master_arvalid, // .arvalid
output wire hps_0_h2f_lw_axi_master_arready, // .arready
output wire [11:0] hps_0_h2f_lw_axi_master_rid, // .rid
output wire [31:0] hps_0_h2f_lw_axi_master_rdata, // .rdata
output wire [1:0] hps_0_h2f_lw_axi_master_rresp, // .rresp
output wire hps_0_h2f_lw_axi_master_rlast, // .rlast
output wire hps_0_h2f_lw_axi_master_rvalid, // .rvalid
input wire hps_0_h2f_lw_axi_master_rready, // .rready
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
input wire ik_driver_0_reset_sink_reset_bridge_in_reset_reset, // ik_driver_0_reset_sink_reset_bridge_in_reset.reset
input wire master_0_clk_reset_reset_bridge_in_reset_reset, // master_0_clk_reset_reset_bridge_in_reset.reset
input wire [31:0] master_0_master_address, // master_0_master.address
output wire master_0_master_waitrequest, // .waitrequest
input wire [3:0] master_0_master_byteenable, // .byteenable
input wire master_0_master_read, // .read
output wire [31:0] master_0_master_readdata, // .readdata
output wire master_0_master_readdatavalid, // .readdatavalid
input wire master_0_master_write, // .write
input wire [31:0] master_0_master_writedata, // .writedata
output wire [4:0] ik_driver_0_avalon_slave_0_address, // ik_driver_0_avalon_slave_0.address
output wire ik_driver_0_avalon_slave_0_write, // .write
output wire [31:0] ik_driver_0_avalon_slave_0_writedata, // .writedata
output wire ik_driver_0_avalon_slave_0_chipselect // .chipselect
);
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> hps_0_h2f_lw_axi_master_agent:write_rp_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_startofpacket
wire [122:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> hps_0_h2f_lw_axi_master_agent:write_rp_data
wire [2:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> hps_0_h2f_lw_axi_master_agent:write_rp_channel
wire rsp_xbar_mux_src_ready; // hps_0_h2f_lw_axi_master_agent:write_rp_ready -> rsp_xbar_mux:src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> hps_0_h2f_lw_axi_master_agent:read_rp_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_startofpacket
wire [122:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> hps_0_h2f_lw_axi_master_agent:read_rp_data
wire [2:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> hps_0_h2f_lw_axi_master_agent:read_rp_channel
wire rsp_xbar_mux_001_src_ready; // hps_0_h2f_lw_axi_master_agent:read_rp_ready -> rsp_xbar_mux_001:src_ready
wire master_0_master_translator_avalon_universal_master_0_waitrequest; // master_0_master_translator_avalon_universal_master_0_agent:av_waitrequest -> master_0_master_translator:uav_waitrequest
wire [2:0] master_0_master_translator_avalon_universal_master_0_burstcount; // master_0_master_translator:uav_burstcount -> master_0_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] master_0_master_translator_avalon_universal_master_0_writedata; // master_0_master_translator:uav_writedata -> master_0_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] master_0_master_translator_avalon_universal_master_0_address; // master_0_master_translator:uav_address -> master_0_master_translator_avalon_universal_master_0_agent:av_address
wire master_0_master_translator_avalon_universal_master_0_lock; // master_0_master_translator:uav_lock -> master_0_master_translator_avalon_universal_master_0_agent:av_lock
wire master_0_master_translator_avalon_universal_master_0_write; // master_0_master_translator:uav_write -> master_0_master_translator_avalon_universal_master_0_agent:av_write
wire master_0_master_translator_avalon_universal_master_0_read; // master_0_master_translator:uav_read -> master_0_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] master_0_master_translator_avalon_universal_master_0_readdata; // master_0_master_translator_avalon_universal_master_0_agent:av_readdata -> master_0_master_translator:uav_readdata
wire master_0_master_translator_avalon_universal_master_0_debugaccess; // master_0_master_translator:uav_debugaccess -> master_0_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] master_0_master_translator_avalon_universal_master_0_byteenable; // master_0_master_translator:uav_byteenable -> master_0_master_translator_avalon_universal_master_0_agent:av_byteenable
wire master_0_master_translator_avalon_universal_master_0_readdatavalid; // master_0_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> master_0_master_translator:uav_readdatavalid
wire rsp_xbar_mux_002_src_endofpacket; // rsp_xbar_mux_002:src_endofpacket -> master_0_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_mux_002_src_valid; // rsp_xbar_mux_002:src_valid -> master_0_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_mux_002_src_startofpacket; // rsp_xbar_mux_002:src_startofpacket -> master_0_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [122:0] rsp_xbar_mux_002_src_data; // rsp_xbar_mux_002:src_data -> master_0_master_translator_avalon_universal_master_0_agent:rp_data
wire [2:0] rsp_xbar_mux_002_src_channel; // rsp_xbar_mux_002:src_channel -> master_0_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_mux_002_src_ready; // master_0_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_002:src_ready
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // ik_driver_0_avalon_slave_0_translator:uav_waitrequest -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> ik_driver_0_avalon_slave_0_translator:uav_burstcount
wire [31:0] ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> ik_driver_0_avalon_slave_0_translator:uav_writedata
wire [31:0] ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> ik_driver_0_avalon_slave_0_translator:uav_address
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> ik_driver_0_avalon_slave_0_translator:uav_write
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> ik_driver_0_avalon_slave_0_translator:uav_lock
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> ik_driver_0_avalon_slave_0_translator:uav_read
wire [31:0] ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata; // ik_driver_0_avalon_slave_0_translator:uav_readdata -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // ik_driver_0_avalon_slave_0_translator:uav_readdatavalid -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> ik_driver_0_avalon_slave_0_translator:uav_debugaccess
wire [3:0] ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> ik_driver_0_avalon_slave_0_translator:uav_byteenable
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [123:0] ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [123:0] ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
wire [33:0] ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
wire hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_endofpacket -> addr_router:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_write_cp_valid; // hps_0_h2f_lw_axi_master_agent:write_cp_valid -> addr_router:sink_valid
wire hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_startofpacket -> addr_router:sink_startofpacket
wire [122:0] hps_0_h2f_lw_axi_master_agent_write_cp_data; // hps_0_h2f_lw_axi_master_agent:write_cp_data -> addr_router:sink_data
wire hps_0_h2f_lw_axi_master_agent_write_cp_ready; // addr_router:sink_ready -> hps_0_h2f_lw_axi_master_agent:write_cp_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [122:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data
wire [2:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel
wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready
wire hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_endofpacket -> addr_router_001:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_read_cp_valid; // hps_0_h2f_lw_axi_master_agent:read_cp_valid -> addr_router_001:sink_valid
wire hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_startofpacket -> addr_router_001:sink_startofpacket
wire [122:0] hps_0_h2f_lw_axi_master_agent_read_cp_data; // hps_0_h2f_lw_axi_master_agent:read_cp_data -> addr_router_001:sink_data
wire hps_0_h2f_lw_axi_master_agent_read_cp_ready; // addr_router_001:sink_ready -> hps_0_h2f_lw_axi_master_agent:read_cp_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [122:0] addr_router_001_src_data; // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data
wire [2:0] addr_router_001_src_channel; // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel
wire addr_router_001_src_ready; // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready
wire master_0_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // master_0_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
wire master_0_master_translator_avalon_universal_master_0_agent_cp_valid; // master_0_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
wire master_0_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // master_0_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
wire [122:0] master_0_master_translator_avalon_universal_master_0_agent_cp_data; // master_0_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
wire master_0_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_002:sink_ready -> master_0_master_translator_avalon_universal_master_0_agent:cp_ready
wire addr_router_002_src_endofpacket; // addr_router_002:src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
wire addr_router_002_src_valid; // addr_router_002:src_valid -> cmd_xbar_demux_002:sink_valid
wire addr_router_002_src_startofpacket; // addr_router_002:src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
wire [122:0] addr_router_002_src_data; // addr_router_002:src_data -> cmd_xbar_demux_002:sink_data
wire [2:0] addr_router_002_src_channel; // addr_router_002:src_channel -> cmd_xbar_demux_002:sink_channel
wire addr_router_002_src_ready; // cmd_xbar_demux_002:sink_ready -> addr_router_002:src_ready
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [122:0] ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [122:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [2:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> burst_adapter:sink0_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> burst_adapter:sink0_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> burst_adapter:sink0_startofpacket
wire [122:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> burst_adapter:sink0_data
wire [2:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> burst_adapter:sink0_channel
wire cmd_xbar_mux_src_ready; // burst_adapter:sink0_ready -> cmd_xbar_mux:src_ready
wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [122:0] burst_adapter_source0_data; // burst_adapter:source0_data -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_source0_ready; // ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
wire [2:0] burst_adapter_source0_channel; // burst_adapter:source0_channel -> ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [122:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [2:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
wire [122:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
wire [2:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
wire cmd_xbar_demux_002_src0_endofpacket; // cmd_xbar_demux_002:src0_endofpacket -> cmd_xbar_mux:sink2_endofpacket
wire cmd_xbar_demux_002_src0_valid; // cmd_xbar_demux_002:src0_valid -> cmd_xbar_mux:sink2_valid
wire cmd_xbar_demux_002_src0_startofpacket; // cmd_xbar_demux_002:src0_startofpacket -> cmd_xbar_mux:sink2_startofpacket
wire [122:0] cmd_xbar_demux_002_src0_data; // cmd_xbar_demux_002:src0_data -> cmd_xbar_mux:sink2_data
wire [2:0] cmd_xbar_demux_002_src0_channel; // cmd_xbar_demux_002:src0_channel -> cmd_xbar_mux:sink2_channel
wire cmd_xbar_demux_002_src0_ready; // cmd_xbar_mux:sink2_ready -> cmd_xbar_demux_002:src0_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [122:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [2:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [122:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
wire [2:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
wire rsp_xbar_demux_src2_endofpacket; // rsp_xbar_demux:src2_endofpacket -> rsp_xbar_mux_002:sink0_endofpacket
wire rsp_xbar_demux_src2_valid; // rsp_xbar_demux:src2_valid -> rsp_xbar_mux_002:sink0_valid
wire rsp_xbar_demux_src2_startofpacket; // rsp_xbar_demux:src2_startofpacket -> rsp_xbar_mux_002:sink0_startofpacket
wire [122:0] rsp_xbar_demux_src2_data; // rsp_xbar_demux:src2_data -> rsp_xbar_mux_002:sink0_data
wire [2:0] rsp_xbar_demux_src2_channel; // rsp_xbar_demux:src2_channel -> rsp_xbar_mux_002:sink0_channel
wire rsp_xbar_demux_src2_ready; // rsp_xbar_mux_002:sink0_ready -> rsp_xbar_demux:src2_ready
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) master_0_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (ik_driver_0_reset_sink_reset_bridge_in_reset_reset), // reset.reset
.uav_address (master_0_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (master_0_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (master_0_master_translator_avalon_universal_master_0_read), // .read
.uav_write (master_0_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (master_0_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (master_0_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (master_0_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (master_0_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (master_0_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (master_0_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (master_0_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (master_0_master_address), // avalon_anti_master_0.address
.av_waitrequest (master_0_master_waitrequest), // .waitrequest
.av_byteenable (master_0_master_byteenable), // .byteenable
.av_read (master_0_master_read), // .read
.av_readdata (master_0_master_readdata), // .readdata
.av_readdatavalid (master_0_master_readdatavalid), // .readdatavalid
.av_write (master_0_master_write), // .write
.av_writedata (master_0_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (5),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) ik_driver_0_avalon_slave_0_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (ik_driver_0_reset_sink_reset_bridge_in_reset_reset), // reset.reset
.uav_address (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (ik_driver_0_avalon_slave_0_address), // avalon_anti_slave_0.address
.av_write (ik_driver_0_avalon_slave_0_write), // .write
.av_writedata (ik_driver_0_avalon_slave_0_writedata), // .writedata
.av_chipselect (ik_driver_0_avalon_slave_0_chipselect), // .chipselect
.av_read (), // (terminated)
.av_readdata (32'b11011110101011011101111010101101), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (21),
.RDATA_WIDTH (32),
.WDATA_WIDTH (32),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (95),
.PKT_CACHE_H (117),
.PKT_CACHE_L (114),
.PKT_ADDR_SIDEBAND_H (93),
.PKT_ADDR_SIDEBAND_L (93),
.PKT_PROTECTION_H (113),
.PKT_PROTECTION_L (111),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_BURST_TYPE_H (92),
.PKT_BURST_TYPE_L (91),
.PKT_RESPONSE_STATUS_L (118),
.PKT_RESPONSE_STATUS_H (119),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (97),
.PKT_DEST_ID_H (98),
.PKT_DEST_ID_L (98),
.PKT_THREAD_ID_H (110),
.PKT_THREAD_ID_L (99),
.PKT_QOS_L (96),
.PKT_QOS_H (96),
.PKT_ORI_BURST_SIZE_L (120),
.PKT_ORI_BURST_SIZE_H (122),
.PKT_DATA_SIDEBAND_H (94),
.PKT_DATA_SIDEBAND_L (94),
.ST_DATA_W (123),
.ST_CHANNEL_W (3),
.ID (0)
) hps_0_h2f_lw_axi_master_agent (
.aclk (clk_0_clk_clk), // clk.clk
.aresetn (~hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (rsp_xbar_mux_src_valid), // write_rp.valid
.write_rp_data (rsp_xbar_mux_src_data), // .data
.write_rp_channel (rsp_xbar_mux_src_channel), // .channel
.write_rp_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.write_rp_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.write_rp_ready (rsp_xbar_mux_src_ready), // .ready
.read_cp_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (rsp_xbar_mux_001_src_valid), // read_rp.valid
.read_rp_data (rsp_xbar_mux_001_src_data), // .data
.read_rp_channel (rsp_xbar_mux_001_src_channel), // .channel
.read_rp_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.read_rp_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.read_rp_ready (rsp_xbar_mux_001_src_ready), // .ready
.awid (hps_0_h2f_lw_axi_master_awid), // altera_axi_slave.awid
.awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.awready (hps_0_h2f_lw_axi_master_awready), // .awready
.wid (hps_0_h2f_lw_axi_master_wid), // .wid
.wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.wready (hps_0_h2f_lw_axi_master_wready), // .wready
.bid (hps_0_h2f_lw_axi_master_bid), // .bid
.bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.bready (hps_0_h2f_lw_axi_master_bready), // .bready
.arid (hps_0_h2f_lw_axi_master_arid), // .arid
.araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.arready (hps_0_h2f_lw_axi_master_arready), // .arready
.rid (hps_0_h2f_lw_axi_master_rid), // .rid
.rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.rready (hps_0_h2f_lw_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (8'b00000000), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (113),
.PKT_PROTECTION_L (111),
.PKT_BEGIN_BURST (95),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_BURST_TYPE_H (92),
.PKT_BURST_TYPE_L (91),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (97),
.PKT_DEST_ID_H (98),
.PKT_DEST_ID_L (98),
.PKT_THREAD_ID_H (110),
.PKT_THREAD_ID_L (99),
.PKT_CACHE_H (117),
.PKT_CACHE_L (114),
.PKT_DATA_SIDEBAND_H (94),
.PKT_DATA_SIDEBAND_L (94),
.PKT_QOS_H (96),
.PKT_QOS_L (96),
.PKT_ADDR_SIDEBAND_H (93),
.PKT_ADDR_SIDEBAND_L (93),
.PKT_RESPONSE_STATUS_H (119),
.PKT_RESPONSE_STATUS_L (118),
.PKT_ORI_BURST_SIZE_L (120),
.PKT_ORI_BURST_SIZE_H (122),
.ST_DATA_W (123),
.ST_CHANNEL_W (3),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (127),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) master_0_master_translator_avalon_universal_master_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (ik_driver_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (master_0_master_translator_avalon_universal_master_0_address), // av.address
.av_write (master_0_master_translator_avalon_universal_master_0_write), // .write
.av_read (master_0_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (master_0_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (master_0_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (master_0_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (master_0_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (master_0_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (master_0_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (master_0_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (master_0_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (master_0_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (master_0_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (master_0_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (master_0_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (master_0_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_mux_002_src_valid), // rp.valid
.rp_data (rsp_xbar_mux_002_src_data), // .data
.rp_channel (rsp_xbar_mux_002_src_channel), // .channel
.rp_startofpacket (rsp_xbar_mux_002_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_mux_002_src_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_mux_002_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (95),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (97),
.PKT_SRC_ID_L (97),
.PKT_DEST_ID_H (98),
.PKT_DEST_ID_L (98),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (113),
.PKT_PROTECTION_L (111),
.PKT_RESPONSE_STATUS_H (119),
.PKT_RESPONSE_STATUS_L (118),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_ORI_BURST_SIZE_L (120),
.PKT_ORI_BURST_SIZE_H (122),
.ST_CHANNEL_W (3),
.ST_DATA_W (123),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (ik_driver_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_source0_ready), // cp.ready
.cp_valid (burst_adapter_source0_valid), // .valid
.cp_data (burst_adapter_source0_data), // .data
.cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_source0_channel), // .channel
.rf_sink_ready (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (124),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (ik_driver_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (ik_driver_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
ik_swift_mm_interconnect_0_addr_router addr_router (
.sink_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
ik_swift_mm_interconnect_0_addr_router addr_router_001 (
.sink_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
ik_swift_mm_interconnect_0_addr_router addr_router_002 (
.sink_ready (master_0_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (master_0_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (master_0_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (master_0_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (master_0_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (ik_driver_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_002_src_ready), // src.ready
.src_valid (addr_router_002_src_valid), // .valid
.src_data (addr_router_002_src_data), // .data
.src_channel (addr_router_002_src_channel), // .channel
.src_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_002_src_endofpacket) // .endofpacket
);
ik_swift_mm_interconnect_0_id_router id_router (
.sink_ready (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (ik_driver_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (ik_driver_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (95),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_BURST_TYPE_H (92),
.PKT_BURST_TYPE_L (91),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (123),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (87),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0)
) burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (ik_driver_0_reset_sink_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_xbar_mux_src_valid), // sink0.valid
.sink0_data (cmd_xbar_mux_src_data), // .data
.sink0_channel (cmd_xbar_mux_src_channel), // .channel
.sink0_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_mux_src_ready), // .ready
.source0_valid (burst_adapter_source0_valid), // source0.valid
.source0_data (burst_adapter_source0_data), // .data
.source0_channel (burst_adapter_source0_channel), // .channel
.source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_source0_ready) // .ready
);
ik_swift_mm_interconnect_0_cmd_xbar_demux cmd_xbar_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (addr_router_src_ready), // sink.ready
.sink_channel (addr_router_src_channel), // .channel
.sink_data (addr_router_src_data), // .data
.sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.sink_valid (addr_router_src_valid), // .valid
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket) // .endofpacket
);
ik_swift_mm_interconnect_0_cmd_xbar_demux cmd_xbar_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (addr_router_001_src_ready), // sink.ready
.sink_channel (addr_router_001_src_channel), // .channel
.sink_data (addr_router_001_src_data), // .data
.sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.sink_valid (addr_router_001_src_valid), // .valid
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
);
ik_swift_mm_interconnect_0_cmd_xbar_demux cmd_xbar_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (ik_driver_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (addr_router_002_src_ready), // sink.ready
.sink_channel (addr_router_002_src_channel), // .channel
.sink_data (addr_router_002_src_data), // .data
.sink_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_002_src_endofpacket), // .endofpacket
.sink_valid (addr_router_002_src_valid), // .valid
.src0_ready (cmd_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_002_src0_valid), // .valid
.src0_data (cmd_xbar_demux_002_src0_data), // .data
.src0_channel (cmd_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_002_src0_endofpacket) // .endofpacket
);
ik_swift_mm_interconnect_0_cmd_xbar_mux cmd_xbar_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (ik_driver_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (cmd_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (cmd_xbar_demux_002_src0_valid), // .valid
.sink2_channel (cmd_xbar_demux_002_src0_channel), // .channel
.sink2_data (cmd_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_xbar_demux_002_src0_endofpacket) // .endofpacket
);
ik_swift_mm_interconnect_0_rsp_xbar_demux rsp_xbar_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (ik_driver_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
.src1_data (rsp_xbar_demux_src1_data), // .data
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.src2_ready (rsp_xbar_demux_src2_ready), // src2.ready
.src2_valid (rsp_xbar_demux_src2_valid), // .valid
.src2_data (rsp_xbar_demux_src2_data), // .data
.src2_channel (rsp_xbar_demux_src2_channel), // .channel
.src2_startofpacket (rsp_xbar_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_xbar_demux_src2_endofpacket) // .endofpacket
);
ik_swift_mm_interconnect_0_rsp_xbar_mux rsp_xbar_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket) // .endofpacket
);
ik_swift_mm_interconnect_0_rsp_xbar_mux rsp_xbar_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src1_valid), // .valid
.sink0_channel (rsp_xbar_demux_src1_channel), // .channel
.sink0_data (rsp_xbar_demux_src1_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket
);
ik_swift_mm_interconnect_0_rsp_xbar_mux rsp_xbar_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (ik_driver_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_002_src_ready), // src.ready
.src_valid (rsp_xbar_mux_002_src_valid), // .valid
.src_data (rsp_xbar_mux_002_src_data), // .data
.src_channel (rsp_xbar_mux_002_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src2_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src2_valid), // .valid
.sink0_channel (rsp_xbar_demux_src2_channel), // .channel
.sink0_data (rsp_xbar_demux_src2_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src2_endofpacket) // .endofpacket
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_TB_V
`define SKY130_FD_SC_LP__NAND3_TB_V
/**
* nand3: 3-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_lp__nand3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_0_V
`define SKY130_FD_SC_LP__A41O_0_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a41o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41o_0 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41o_0 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_0_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module sync_master(
input wire clk, // clock input
input wire clk_2x, // clock 90 input
input wire datain, // data inputs
input wire rst, // reset input
output wire useaout, // useA output for cascade
output wire usebout, // useB output for cascade
output wire usecout, // useC output for cascade
output wire usedout, // useD output for cascade
output wire [1:0] ctrlout, // ctrl outputs for cascade
output reg sdataout // data out
);
wire aa0 ;
wire bb0 ;
wire cc0 ;
wire dd0 ;
reg usea ;
reg useb ;
reg usec ;
reg used ;
reg useaint ;
reg usebint ;
reg usecint ;
reg usedint ;
reg [1:0] ctrlint;
wire sdataa ;
wire sdatab ;
wire sdatac ;
wire sdatad ;
wire [1:0] az ;
wire [1:0] bz ;
wire [1:0] cz ;
wire [1:0] dz ;
reg aap, bbp, ccp, ddp, az2, bz2, cz2, dz2 ;
reg aan, bbn, ccn, ddn ;
reg pipe_ce0 ;
assign useaout = useaint ;
assign usebout = usebint ;
assign usecout = usecint ;
assign usedout = usedint ;
assign ctrlout = ctrlint ;
assign sdataa = {(aa0 && useaint)} ;
assign sdatab = {(bb0 && usebint)} ;
assign sdatac = {(cc0 && usecint)} ;
assign sdatad = {(dd0 && usedint)} ;
//SRL16 saa0(.D(az2), .CLK(clk), .A0(ctrlint[0]), .A1(ctrlint[1]), .A2(1'b0), .A3(1'b0), .Q(aa0));
//SRL16 sbb0(.D(bz2), .CLK(clk), .A0(ctrlint[0]), .A1(ctrlint[1]), .A2(1'b0), .A3(1'b0), .Q(bb0));
//SRL16 scc0(.D(cz2), .CLK(clk), .A0(ctrlint[0]), .A1(ctrlint[1]), .A2(1'b0), .A3(1'b0), .Q(cc0));
//SRL16 sdd0(.D(dz2), .CLK(clk), .A0(ctrlint[0]), .A1(ctrlint[1]), .A2(1'b0), .A3(1'b0), .Q(dd0));
reg [3:0] data_az2;
always@(posedge clk)
data_az2[3:0] <= {data_az2[2:0], az2};
assign aa0 = data_az2[ctrlint];
reg [3:0] data_bz2;
always@(posedge clk)
data_bz2[3:0] <= {data_bz2[2:0], bz2};
assign bb0 = data_bz2[ctrlint];
reg [3:0] data_cz2;
always@(posedge clk)
data_cz2[3:0] <= {data_cz2[2:0], cz2};
assign cc0 = data_cz2[ctrlint];
reg [3:0] data_dz2;
always@(posedge clk)
data_dz2[3:0] <= {data_dz2[2:0], dz2};
assign dd0 = data_dz2[ctrlint];
always @ (posedge clk or posedge rst) begin
if (rst) begin
ctrlint <= 2'b10 ;
useaint <= 1'b0 ; usebint <= 1'b0 ; usecint <= 1'b0 ; usedint <= 1'b0 ;
usea <= 1'b0 ; useb <= 1'b0 ; usec <= 1'b0 ; used <= 1'b0 ;
pipe_ce0 <= 1'b0 ; sdataout <= 1'b1 ;
aap <= 1'b0 ; bbp <= 1'b0 ; ccp <= 1'b0 ; ddp <= 1'b0 ;
aan <= 1'b0 ; bbn <= 1'b0 ; ccn <= 1'b0 ; ddn <= 1'b0 ;
az2 <= 1'b0 ; bz2 <= 1'b0 ; cz2 <= 1'b0 ; dz2 <= 1'b0 ;
end
else begin
az2 <= az[1] ; bz2 <= bz[1] ; cz2 <= cz[1] ; dz2 <= dz[1] ;
aap <= (az ^ az[1]) & ~az[1] ; // find positive edges
bbp <= (bz ^ bz[1]) & ~bz[1] ;
ccp <= (cz ^ cz[1]) & ~cz[1] ;
ddp <= (dz ^ dz[1]) & ~dz[1] ;
aan <= (az ^ az[1]) & az[1] ; // find negative edges
bbn <= (bz ^ bz[1]) & bz[1] ;
ccn <= (cz ^ cz[1]) & cz[1] ;
ddn <= (dz ^ dz[1]) & dz[1] ;
// aap <= (az[1] ^ az2) & ~az2; // find positive edges
// bbp <= (bz[1] ^ bz2) & ~bz2;
// ccp <= (cz[1] ^ cz2) & ~cz2;
// ddp <= (dz[1] ^ dz2) & ~dz2;
// aan <= (az[1] ^ az2) & az2; // find negative edges
// bbn <= (bz[1] ^ bz2) & bz2;
// ccn <= (cz[1] ^ cz2) & cz2;
// ddn <= (dz[1] ^ dz2) & dz2;
usea <= (bbp & ~ccp & ~ddp & aap) | (bbn & ~ccn & ~ddn & aan) ;
useb <= (ccp & ~ddp & aap & bbp) | (ccn & ~ddn & aan & bbn) ;
usec <= (ddp & aap & bbp & ccp) | (ddn & aan & bbn & ccn) ;
used <= (aap & ~bbp & ~ccp & ~ddp) | (aan & ~bbn & ~ccn & ~ddn) ;
if (usea | useb | usec | used) begin
pipe_ce0 <= 1'b1 ;
useaint <= usea ;
usebint <= useb ;
usecint <= usec ;
usedint <= used ;
end
if (pipe_ce0)
sdataout <= sdataa | sdatab | sdatac | sdatad ;
if (usedint & usea) // 'd' going to 'a'
ctrlint <= ctrlint - 1 ;
else if (useaint & used) // 'a' going to 'd'
ctrlint <= ctrlint + 1 ;
end
end
// 320MHz clock domain
// *** do not touch code below ***
wire [1:0] DDRQ;
IDDR IDDR_inst (
.Q1(DDRQ[1]), // 1-bit output for positive edge of clock
.Q2(DDRQ[0]), // 1-bit output for negative edge of clock
.C(clk_2x), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D(datain), // 1-bit DDR data input
.R(1'b0), // 1-bit reset
.S(1'b0) // 1-bit set
);
reg [1:0] DDRQ_DLY;
always@(posedge clk_2x)
DDRQ_DLY[1:0] <= DDRQ[1:0];
reg [3:0] DDRQ_DATA;
always@(posedge clk_2x)
DDRQ_DATA[3:0] <= {DDRQ_DLY[1:0], DDRQ[1:0]};
// *** do not touch code above ***
// 160MHz clock domain
reg [3:0] DATA_IN;
always@(posedge clk)
DATA_IN[3:0] <= {DDRQ_DATA[3:0]};
reg [3:0] DATA_IN_DLY;
always@(posedge clk)
DATA_IN_DLY[3:0] <= {DATA_IN[3:0]};
assign az[0] = DATA_IN[3];
assign bz[0] = DATA_IN[2];
assign cz[0] = DATA_IN[1];
assign dz[0] = DATA_IN[0];
assign az[1] = DATA_IN_DLY[3];
assign bz[1] = DATA_IN_DLY[2];
assign cz[1] = DATA_IN_DLY[1];
assign dz[1] = DATA_IN_DLY[0];
//FDC ff_az0(.D(datain), .C(clk), .CLR(rst), .Q(az[0]))/*synthesis rloc = "x0y0" */;
//FDC ff_az1(.D(az[0]), .C(clk), .CLR(rst), .Q(az[1]))/*synthesis rloc = "x2y0" */;
//FDC ff_bz0(.D(datain), .C(clk90), .CLR(rst), .Q(bz[0]))/*synthesis rloc = "x1y0" */;
//FDC ff_bz1(.D(bz[0]), .C(clk), .CLR(rst), .Q(bz[1]))/*synthesis rloc = "x4y0" */;
//FDC ff_cz0(.D(datain), .C(notclk), .CLR(rst), .Q(cz[0]))/*synthesis rloc = "x1y1" */;
//FDC ff_cz1(.D(cz[0]), .C(clk), .CLR(rst), .Q(cz[1]))/*synthesis rloc = "x2y0" */;
//FDC ff_dz0(.D(datain), .C(notclk90), .CLR(rst), .Q(dz[0]))/*synthesis rloc = "x0y1" */;
//FDC ff_dz1(.D(dz[0]), .C(clk90), .CLR(rst), .Q(dz[1]))/*synthesis rloc = "x3y0" */;
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: DES Node
-- Description: Top level de un nodo de la red en-chip. Vale la pena notar
que las interfaces fuera del modulo son las mismas que las
de un router de red, la razon de esto es que el puerto del
elemento de procesamiento de cada nodo solo tiene acceso
exterior por medio de un canal del router.
-- Dependencies: -- system.vh
-- router.v
-- data_path.v
-- Parameters: -- X_LOCAL: Direccion en dimension "x" del nodo
en la red.
-- Y_LOCAL: Direccion en dimension "y" del nodo
en la red.
-- PE: Elemento de procesamiento. Este
parametro representa una cadena de
texto con el nombre del RTL de la
unida funcional del nodo.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- 05 de Junio 2015: Creacion
-- 11 de Junio 2015: Actualizacion de instancias de camino de
datos y camino de control.
-- 14 de Junio 2015: Actualizacion de instancias de camino de
datos y camino de control.
*/
`include "system.vh"
module des_node #(
parameter X_LOCAL = 2,
parameter Y_LOCAL = 2
)
(
input wire clk,
input wire reset,
// -- puertos de entrada ------------------------------------- >>>>>
output wire credit_out_xpos_dout,
input wire [`CHANNEL_WIDTH-1:0] channel_xpos_din,
output wire credit_out_ypos_dout,
input wire [`CHANNEL_WIDTH-1:0] channel_ypos_din,
output wire credit_out_xneg_dout,
input wire [`CHANNEL_WIDTH-1:0] channel_xneg_din,
output wire credit_out_yneg_dout,
input wire [`CHANNEL_WIDTH-1:0] channel_yneg_din,
// -- puertos de salida -------------------------------------- >>>>>
input wire credit_in_xpos_din,
output wire [`CHANNEL_WIDTH-1:0] channel_xpos_dout,
input wire credit_in_ypos_din,
output wire [`CHANNEL_WIDTH-1:0] channel_ypos_dout,
input wire credit_in_xneg_din,
output wire [`CHANNEL_WIDTH-1:0] channel_xneg_dout,
input wire credit_in_yneg_din,
output wire [`CHANNEL_WIDTH-1:0] channel_yneg_dout
/* -- Salida de bit de paridad para Llave de encriptacion ---- >>>>>
Descripcion: Activar para tener acceso al bit de paridad
generado a partir de la llave de encriptacion
de DES.
*/
//output wire parity_check_dout
);
/*
-- Instancia :: Router
-- Descripcion: Elemento de distribucion de informacion para el nodo.
Todos lso router son homogeneos, es decir tienen 4
canales bidireccionales de comunicacion para
interconectarse con hasta 4 vecinos en las direcciones
* x+
* x-
* y+
* y-
El router presenta un quinto canal para enlazarse a
una unidad funcional por medio de una interfaz de red.
Para una lista completa de dependencias es necesario
consultar el archivo router.v.
*/
// -- Declaracion temparana de Señales -------------------------- >>>>>>
wire credit_out_pe;
wire [`CHANNEL_WIDTH-1:0] channel_pe_in;
wire credit_in_pe;
wire [`CHANNEL_WIDTH-1:0] channel_pe_out;
// -- Instancia del modulo router ------------------------------- >>>>>>
router
#(
.X_LOCAL(X_LOCAL),
.Y_LOCAL(Y_LOCAL)
)
des_router
(
.clk (clk),
.reset (reset),
// -- puertos de entrada ------------------------------------- >>>>>
.credit_out_xpos_dout (credit_out_xpos_dout),
.channel_xpos_din (channel_xpos_din),
.credit_out_ypos_dout (credit_out_ypos_dout),
.channel_ypos_din (channel_ypos_din),
.credit_out_xneg_dout (credit_out_xneg_dout),
.channel_xneg_din (channel_xneg_din),
.credit_out_yneg_dout (credit_out_yneg_dout),
.channel_yneg_din (channel_yneg_din),
.credit_out_pe_dout (credit_out_pe),
.channel_pe_din (channel_pe_in),
// -- puertos de salida -------------------------------------- >>>>>
.credit_in_xpos_din (credit_in_xpos_din),
.channel_xpos_dout (channel_xpos_dout),
.credit_in_ypos_din (credit_in_ypos_din),
.channel_ypos_dout (channel_ypos_dout),
.credit_in_xneg_din (credit_in_xneg_din),
.channel_xneg_dout (channel_xneg_dout),
.credit_in_yneg_din (credit_in_yneg_din),
.channel_yneg_dout (channel_yneg_dout),
.credit_in_pe_din (credit_in_pe),
.channel_pe_dout (channel_pe_out)
);
/*
-- Instancia :: Interfaz de red
-- Descripcion: Elemento de interconexion entre router y elemento de
procesamiento del nodo. La interfaz esta encargada de
recibir paquetes de la red y decodificarlos para la
extracion y presentacion de datos de trabajo en un
formato compatible con los requerimientos del elemento
de procesamiento.
De igual forma, la interfaz de red toma paquetes del
elemento de procesamiento y los empaqueta en flits
para su distribucion a traves de la red por medio del
router del nodo.
*/
// -- Declaracion temprana de señales ------------------------ >>>>>
wire start_strobe;
wire [(2 * `CHANNEL_WIDTH)-1:0] plaintext;
wire [(2 * `CHANNEL_WIDTH)-1:0] key;
wire done_strobe_din;
wire active_des_engine_din;
wire [(2 * `CHANNEL_WIDTH)-1:0] ciphertext;
des_network_interface interfaz_de_red
(
.clk (clk),
.reset (reset),
// -- input port --------------------------------------------- >>>>>
.credit_out_dout (credit_in_pe),
.input_channel_din (channel_pe_out),
// -- output port -------------------------------------------- >>>>>
.credit_in_din (credit_out_pe),
.output_channel_dout (channel_pe_in),
// -- interfaz :: processing node ---------------------------- >>>>>
.start_strobe_dout (start_strobe),
.plaintext_dout (plaintext),
.key_dout (key),
.done_strobe_din (done_strobe),
.active_des_engine_din (active_des_engine),
.ciphertext_din (ciphertext)
);
/*
-- Instancia :: Encriptador DES
-- Descripcion: Elemento funcional del nodo de red. Este es particular
para cada tarea que se desea acelerar, en este caso
particular la encriptacion de bloques de 64 bits.
*/
wire parity_check;
des_core des_engine
(
.clk (clk),
.reset (reset),
// -- input -------------------------------------------------- >>>>>
.start_strobe_din (start_strobe),
.plaintext_din (plaintext),
.key_din (key),
// -- output ------------------------------------------------- >>>>>
.done_strobe_dout (done_strobe),
.active_des_engine_dout (active_des_engine),
.parity_check_dout (parity_check),
.ciphertext_dout (ciphertext)
);
endmodule
/* -- Plantilla de instancia ------------------------------------- >>>>>
des_node
#(
.X_LOCAL (X_LOCAL),
.Y_LOCAL (Y_LOCAL)
)
des_node
.clk (clk),
.reset (reset),
// -- puertos de entrada --------------------------------- >>>>>
.credit_out_xpos_dout (credit_out_xpos_dout),
.channel_xpos_din (channel_xpos_din),
.credit_out_ypos_dout (credit_out_ypos_dout),
.channel_ypos_din (channel_ypos_din),
.credit_out_xneg_dout (credit_out_xneg_dout),
.channel_xneg_din (channel_xneg_din),
.credit_out_yneg_dout (credit_out_yneg_dout),
.channel_yneg_din (channel_yneg_din),
// -- puertos de salida ---------------------------------- >>>>>
.credit_in_xpos_din (credit_in_xpos_din),
.channel_xpos_dout (channel_xpos_dout),
.credit_in_ypos_din (credit_in_ypos_din),
.channel_ypos_dout (channel_ypos_dout),
.credit_in_xneg_din (credit_in_xneg_din),
.channel_xneg_dout (channel_xneg_dout),
.credit_in_yneg_din (credit_in_yneg_din),
.channel_yneg_dout (channel_yneg_dout)
);
*/ |
//----------------------------------------------------------------------------
//-- Asynchronous serial receiver Unit
//------------------------------------------
//-- (C) BQ. December 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Tested at all the standard baudrates:
//--
//----------------------------------------------------------------------------
//-- Although this transmitter has been written from the scratch, it has been
//-- inspired by the one developed in the swapforth proyect by James Bowman
//--
//-- https://github.com/jamesbowman/swapforth
//--
//----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//-- Serial receiver unit module
module uart_rx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire clk, //-- System clock (12MHz in the ICEstick)
input wire rstn, //-- Reset (Active low)
input wire rx, //-- Serial data input
output reg rcv, //-- Data is available (1)
output reg [7:0] data //-- Data received
);
//-- Transmission clock
wire clk_baud;
//-- Control signals
reg bauden; //-- Enable the baud generator
reg clear; //-- Clear the bit counter
reg load; //-- Load the received character into the data register
//-------------------------------------------------------------------
//-- DATAPATH
//-------------------------------------------------------------------
//-- The serial input is registered in order to follow the
//-- synchronous design rules
reg rx_r;
always @(posedge clk)
rx_r <= rx;
//-- Baud generator
baudgen_rx #(BAUDRATE)
baudgen0 (
.rstn(rstn),
.clk(clk),
.clk_ena(bauden),
.clk_out(clk_baud)
);
//-- Bit counter
reg [3:0] bitc;
always @(posedge clk)
if (clear)
bitc <= 4'd0;
else if (clear == 0 && clk_baud == 1)
bitc <= bitc + 1;
//-- Shift register for storing the received bits
reg [9:0] raw_data;
always @(posedge clk)
if (clk_baud == 1) begin
raw_data <= {rx_r, raw_data[9:1]};
end
//-- Data register. Store the character received
always @(posedge clk)
if (rstn == 0)
data <= 0;
else if (load)
data <= raw_data[8:1];
//-------------------------------------------
//-- CONTROLLER (Finite state machine)
//-------------------------------------------
//-- Receiver states
localparam IDLE = 2'd0; //-- IDLEde reposo
localparam RECV = 2'd1; //-- Receiving data
localparam LOAD = 2'd2; //-- Storing the character received
localparam DAV = 2'd3; //-- Data is available
//-- fsm states
reg [1:0] state;
reg [1:0] next_state;
//-- Transition between states
always @(posedge clk)
if (!rstn)
state <= IDLE;
else
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
bauden = 0;
clear = 0;
load = 0;
case(state)
//-- Idle state
//-- Remain in this state until a start bit is received in rx_r
IDLE: begin
clear = 1;
rcv = 0;
if (rx_r == 0)
next_state = RECV;
end
//-- Receiving state
//-- Turn on the baud generator and wait for the serial package to be received
RECV: begin
bauden = 1;
rcv = 0;
if (bitc == 4'd10)
next_state = LOAD;
end
//-- Store the received character in the data register (1 cycle)
LOAD: begin
load = 1;
rcv = 0;
next_state = DAV;
end
//-- Data Available (1 cycle)
DAV: begin
rcv = 1;
next_state = IDLE;
end
default:
rcv = 0;
endcase
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 9
(* X_CORE_INFO = "axi_crossbar_v2_1_9_axi_crossbar,Vivado 2016.1" *)
(* CHECK_LICENSE_TYPE = "design_1_xbar_0,axi_crossbar_v2_1_9_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "design_1_xbar_0,axi_crossbar_v2_1_9_axi_crossbar,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=5,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=0,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x000000004280000000000000400000000000000043c100000000000043c000000000000040400000,C_M_AXI_ADDR_WIDTH=0x000000100000000d000\
000100000001000000010,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_WIDTH=0x0000000c,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x0000000100000001000000010000000100000001,C_M_AXI_READ_CONNECTIVITY=0x0000000100000001000000010000000100000001,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x00000000,C_S_AXI_WRITE_ACCEPTANCE=0x00000008,C_S_AXI_READ_ACCEPTANCE=0x00000008,C_M_AXI_WRITE_ISSUING=0x00\
00000800000008000000080000000800000008,C_M_AXI_READ_ISSUING=0x0000000800000008000000080000000800000008,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x0000000000000000000000000000000000000000,C_CONNECTIVITY_MODE=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xbar_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *)
input wire [0 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *)
output wire [0 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI AWID [11:0] [35:24], xilinx.com:interface:aximm:1.0 M03_AXI AWID [11:0] [47:36], xilinx.com:interface:aximm:1.0 M04_AXI AWID [11:0] [59:48]" *)
output wire [59 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128]" *)
output wire [159 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI AWLEN [7:0] [31:24], xilinx.com:interface:aximm:1.0 M04_AXI AWLEN [7:0] [39:32]" *)
output wire [39 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWSIZE [2:0] [14:12]" *)
output wire [14 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI AWBURST [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI AWBURST [1:0] [9:8]" *)
output wire [9 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWLOCK [0:0] [4:4]" *)
output wire [4 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI AWCACHE [3:0] [19:16]" *)
output wire [19 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12]" *)
output wire [14 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWREGION [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI AWREGION [3:0] [19:16]" *)
output wire [19 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWQOS [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI AWQOS [3:0] [19:16]" *)
output wire [19 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4]" *)
output wire [4 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4]" *)
input wire [4 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128]" *)
output wire [159 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16]" *)
output wire [19 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WLAST [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WLAST [0:0] [4:4]" *)
output wire [4 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4]" *)
output wire [4 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4]" *)
input wire [4 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI BID [11:0] [35:24], xilinx.com:interface:aximm:1.0 M03_AXI BID [11:0] [47:36], xilinx.com:interface:aximm:1.0 M04_AXI BID [11:0] [59:48]" *)
input wire [59 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8]" *)
input wire [9 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4]" *)
input wire [4 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4]" *)
output wire [4 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI ARID [11:0] [35:24], xilinx.com:interface:aximm:1.0 M03_AXI ARID [11:0] [47:36], xilinx.com:interface:aximm:1.0 M04_AXI ARID [11:0] [59:48]" *)
output wire [59 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128]" *)
output wire [159 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI ARLEN [7:0] [31:24], xilinx.com:interface:aximm:1.0 M04_AXI ARLEN [7:0] [39:32]" *)
output wire [39 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARSIZE [2:0] [14:12]" *)
output wire [14 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI ARBURST [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI ARBURST [1:0] [9:8]" *)
output wire [9 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARLOCK [0:0] [4:4]" *)
output wire [4 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI ARCACHE [3:0] [19:16]" *)
output wire [19 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12]" *)
output wire [14 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARREGION [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI ARREGION [3:0] [19:16]" *)
output wire [19 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARQOS [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI ARQOS [3:0] [19:16]" *)
output wire [19 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4]" *)
output wire [4 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4]" *)
input wire [4 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI RID [11:0] [35:24], xilinx.com:interface:aximm:1.0 M03_AXI RID [11:0] [47:36], xilinx.com:interface:aximm:1.0 M04_AXI RID [11:0] [59:48]" *)
input wire [59 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128]" *)
input wire [159 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8]" *)
input wire [9 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RLAST [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RLAST [0:0] [4:4]" *)
input wire [4 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4]" *)
input wire [4 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4]" *)
output wire [4 : 0] m_axi_rready;
axi_crossbar_v2_1_9_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(5),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(320'H000000004280000000000000400000000000000043c100000000000043c000000000000040400000),
.C_M_AXI_ADDR_WIDTH(160'H000000100000000d000000100000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H0000000c),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(160'H0000000100000001000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(160'H0000000100000001000000010000000100000001),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(32'H00000000),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000008),
.C_S_AXI_READ_ACCEPTANCE(32'H00000008),
.C_M_AXI_WRITE_ISSUING(160'H0000000800000008000000080000000800000008),
.C_M_AXI_READ_ISSUING(160'H0000000800000008000000080000000800000008),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(160'H0000000000000000000000000000000000000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(12'H000),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(5'H00),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(5'H00),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_SYMBOL_V
/**
* udp_dff$P_pp$PG: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$P_pp$PG (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2B_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NAND2B_FUNCTIONAL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand2b (
VPWR,
VGND,
Y ,
A_N ,
B
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B ;
// Local signals
wire Y not0_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y , not0_out, A_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2B_FUNCTIONAL_V |
`timescale 1ns / 1ps
/*
-- Module Name: Arbiter
-- Description: Implementacion de algoritmo de arbitraje entre multiples
peticiones. En particular este modulo implementa el
algoritmo round-robin de 4 bits.
Despues de un reset, el modulo da priorida en orden
descendiente a las peticiones de: {PE, x+, y+, x-, y-}.
Despues de seleccionar un ganador, la maxima prioridad
durante el siguiente proceso de arbitraje se otorga al
puerto inmediato inferior al ganador de la ronda
anterior.
Ej. Si el ganador durante la ronda anterior fue la
peticion proveniente de 'x+', la siguiente ronda
las peticiones de 'y+' tendran la maxima
prioridad.
-- Dependencies: -- system.vh
-- Parameters: -- RQSX: Codificacion 'One-Hot' de peticiones.
Ej. Si los puertos validos para hacer
una peticion son: {x+, y+, x-, y-},
RQS0 tendria el valot 4'b0001
-- PTY_NEXT_RQSX: Codificacion en binario natural
de los numeros 3 a 0.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- 05 de Junio 2015: Creacion
-- 14 de Junio 2015: - Constantes RQSX y PTY_NEXT_RQSX pasan a
ser parametros locales en lugar de
`define en system.vh.
- rqs_priority_next pasa a tener longitud de
2 dos bits en lugar de 4.
- Se agrega un registro dedicado al
seguimiento de la prioridad siguiente.
- El algoritmo de RR utiliza la señal
registrada de rqs_priority_reg
*/
`include "system.vh"
module arbiter
(
input wire clk,
// -- inputs ------------------------------------------------- >>>>>
input wire [3:0] port_request_din,
input wire arbiter_strobe_din,
input wire clear_arbiter_din,
// -- output ------------------------------------------------- >>>>>
output wire [3:0] xbar_conf_vector_dout
);
// -- Parametros locales ----------------------------------------- >>>>>
localparam RQS0 = 4'b0001;
localparam RQS1 = 4'b0010;
localparam RQS2 = 4'b0100;
localparam RQS3 = 4'b1000;
localparam PTY_NEXT_RQS1 = 2'b01;
localparam PTY_NEXT_RQS2 = 2'b10;
localparam PTY_NEXT_RQS3 = 2'b11;
localparam PTY_NEXT_RQS0 = 2'b00;
// -- Declaracion Temprana de Señales ---------------------------- >>>>>
reg [3:0] xbar_conf_vector_reg = 4'b0000;
/*
-- Priority Encoder
-- Descripcion: Codificador de prioridad para la siguiente ronda de
arbitraje. Dependiendo de la peticion ganadora
(xbar_conf_vector_reg) se otorga prioridad para el
proximo proceso de arbitraje a la entrada inferior
inmediada en la jeraraquia.
Ej. jerarquia por default de puertos {PE, x+, y+, x-,
y-}. Si la ronda anterior la peticion de 'y+'
resulto ganadora, la siguiente ronda las peticiones
de 'x-' tienen la maxima prioridad.
La prioridad esta codificada en binario naturas
rqs_priority_reg.
*/
reg [1:0] rqs_priority_reg = 2'b00;
reg [1:0] rqs_priority_next;
// -- Elemento de memoria ------------------------------------ >>>>>
always @(posedge clk)
if (clear_arbiter_din)
rqs_priority_reg <= rqs_priority_next;
// -- Elemento de logica del siguiente estado ---------------- >>>>>
always @(*)
begin
rqs_priority_next = 2'b00;
case (xbar_conf_vector_reg)
RQS0: rqs_priority_next = PTY_NEXT_RQS1;
RQS1: rqs_priority_next = PTY_NEXT_RQS2;
RQS2: rqs_priority_next = PTY_NEXT_RQS3;
RQS3: rqs_priority_next = PTY_NEXT_RQS0;
endcase
end //(*)
/*
-- Round Robin
-- Descripcion: Codificacion de algoritmo Round Robin por medio de
tabla de verdad. Cada bit de 'grant_vector' es
mutuamente excluyente de sus vecinos.
*/
wire [3:0] grant_vector;
// -- Combinational RR ----------------------------------------------- >>>>>
assign grant_vector[0] = (port_request_din[0] & ~rqs_priority_reg[1] & ~rqs_priority_reg[0]) |
(port_request_din[0] & ~rqs_priority_reg[1] & rqs_priority_reg[0] & ~port_request_din[3] & ~port_request_din[2] & ~port_request_din[1]) |
(port_request_din[0] & rqs_priority_reg[1] & ~rqs_priority_reg[0] & ~port_request_din[3] & ~port_request_din[2]) |
(port_request_din[0] & rqs_priority_reg[1] & rqs_priority_reg[0] & ~port_request_din[3]);
assign grant_vector[1] = (port_request_din[1] & ~rqs_priority_reg[1] & ~rqs_priority_reg[0] & ~port_request_din[0]) |
(port_request_din[1] & ~rqs_priority_reg[1] & rqs_priority_reg[0]) |
(port_request_din[1] & rqs_priority_reg[1] & ~rqs_priority_reg[0] & ~port_request_din[3] & ~port_request_din[2] & ~port_request_din[0]) |
(port_request_din[1] & rqs_priority_reg[1] & rqs_priority_reg[0] & ~port_request_din[3] & ~port_request_din[0]);
assign grant_vector[2] = (port_request_din[2] & ~rqs_priority_reg[1] & ~rqs_priority_reg[0] & ~port_request_din[1] & ~port_request_din[0]) |
(port_request_din[2] & ~rqs_priority_reg[1] & rqs_priority_reg[0] & ~port_request_din[1]) |
(port_request_din[2] & rqs_priority_reg[1] & ~rqs_priority_reg[0] ) |
(port_request_din[2] & rqs_priority_reg[1] & rqs_priority_reg[0] & ~port_request_din[3] & ~port_request_din[1] & ~port_request_din[0]);
assign grant_vector[3] = (port_request_din[3] & ~rqs_priority_reg[1] & ~rqs_priority_reg[0] & ~port_request_din[2] & ~port_request_din[1] & ~port_request_din[0]) |
(port_request_din[3] & ~rqs_priority_reg[1] & rqs_priority_reg[0] & ~port_request_din[2] & ~port_request_din[1]) |
(port_request_din[3] & rqs_priority_reg[1] & ~rqs_priority_reg[0] & ~port_request_din[2]) |
(port_request_din[3] & rqs_priority_reg[1] & rqs_priority_reg[0]);
// -- Registro de control para Crossbar -------------------------- >>>>>
always @(posedge clk)
if (clear_arbiter_din)
xbar_conf_vector_reg <= {4{1'b0}};
else
if (arbiter_strobe_din)
xbar_conf_vector_reg <= grant_vector;
// -- Salida de Modulo ------------------------------------------- >>>>>
assign xbar_conf_vector_dout = xbar_conf_vector_reg;
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
wire [3:0] xbar_conf_vector;
arbiter arbitro_round_robin
(
.clk(clk),
// -- inputs --------------------------------------------- >>>>>
.port_request_din (port_request_din),
.arbiter_strobe_din (arbiter_strobe_din),
.clear_arbiter_din (clear_arbiter_din)
// -- output --------------------------------------------- >>>>>
.xbar_conf_vector_dout (xbar_conf_vector)
);
*/ |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 21:06:44 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_1_0/system_clock_splitter_1_0_stub.v
// Design : system_clock_splitter_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "clock_splitter,Vivado 2016.4" *)
module system_clock_splitter_1_0(clk_in, latch_edge, clk_out)
/* synthesis syn_black_box black_box_pad_pin="clk_in,latch_edge,clk_out" */;
input clk_in;
input latch_edge;
output clk_out;
endmodule
|
/*
* Read rotary/quadrature encoder using the clock
*
*/
module quadrature_decoder(
CLOCK,
RESET,
A,
B,
COUNT_ENABLE,
DIRECTION,
SPEED
);
input CLOCK, RESET, A, B;
output COUNT_ENABLE;
output DIRECTION;
output [3:0] SPEED;
reg [2:0] A_delayed;
reg [2:0] B_delayed;
always @(posedge CLOCK or posedge RESET) begin
if (RESET) begin
A_delayed <= 0;
end else begin
A_delayed <= {A_delayed[1:0], A};
end
end
always @(posedge CLOCK or posedge RESET) begin
if (RESET) begin
B_delayed <= 0;
end else begin
B_delayed <= {B_delayed[1:0], B};
end
end
assign COUNT_ENABLE = A_delayed[1] ^ A_delayed[2] ^ B_delayed[1] ^ B_delayed[2];
assign DIRECTION = A_delayed[1] ^ B_delayed[2];
assign SPEED = 4'd0;
/*
wire count_enable = A_delayed[1] ^ A_delayed[2] ^ B_delayed[1] ^ B_delayed[2];
wire count_direction = A_delayed[1] ^ B_delayed[2];
reg [31:0] total;
always @(posedge CLOCK or posedge RESET) begin
if (RESET) begin
total <= 0;
end
else if (count_enable) begin
// only want a final count between 0 & 27 (x4 for the clicks)
if (count_direction && total < 109) begin
total <= total+1;
end
else if (total > 0) begin
total <= total-1;
end
end
end
wire [31:0] clicks;
assign clicks = total >> 2; // divide by 4 as the encoder has 4 edges per "click"
assign COUNT = clicks[7:0];
*/
endmodule
|
//======================================================================
//
// pseudo_entropy.v
// ----------------
// Fake pseudo entropy source. This module SHOULD ONLY be used
// during simulation of the Cryptech True Random Number Generator
// (trng). The module DOES NOT provide any real entropy.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module pseudo_entropy(
input wire clk,
input wire reset_n,
input wire enable,
output wire [31 : 0] raw_entropy,
output wire [31 : 0] stats,
output wire enabled,
output wire entropy_syn,
output wire [31 : 0] entropy_data,
input wire entropy_ack
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign enabled = enable;
assign raw_entropy = enable ? 32'h00ff00ff : 32'h00000000;
assign stats = enable ? 32'hff00ff00 : 32'h00000000;
assign entropy_syn = enable;
assign entropy_data = enable ? 32'hf1e2d3c4 : 32'h00000000;
endmodule // pseudo_entropy
//======================================================================
// EOF pseudo_entropy.v
//======================================================================
|
/*
Copyright (c) 2020-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
input wire uart_rts,
output wire uart_cts,
/*
* Ethernet: SFP+
*/
input wire sfp0_rx_p,
input wire sfp0_rx_n,
output wire sfp0_tx_p,
output wire sfp0_tx_n,
input wire sfp1_rx_p,
input wire sfp1_rx_n,
output wire sfp1_tx_p,
output wire sfp1_tx_n,
input wire sfp_mgt_refclk_0_p,
input wire sfp_mgt_refclk_0_n,
output wire sfp0_tx_disable_b,
output wire sfp1_tx_disable_b
);
// Clock and reset
wire clk_125mhz_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_125mhz_ibufg_inst (
.O (clk_125mhz_ibufg),
.I (clk_125mhz_p),
.IB (clk_125mhz_n)
);
// MMCM instance
// 125 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 8, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME4_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(8),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_125mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(8),
.RATE(156000)
)
debounce_switch_inst (
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_rts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_156mhz_int),
.in({uart_rxd, uart_rts}),
.out({uart_rxd_int, uart_rts_int})
);
// XGMII 10G PHY
assign sfp0_tx_disable_b = 1'b1;
assign sfp1_tx_disable_b = 1'b1;
wire sfp0_tx_clk_int;
wire sfp0_tx_rst_int;
wire [63:0] sfp0_txd_int;
wire [7:0] sfp0_txc_int;
wire sfp0_rx_clk_int;
wire sfp0_rx_rst_int;
wire [63:0] sfp0_rxd_int;
wire [7:0] sfp0_rxc_int;
wire sfp1_tx_clk_int;
wire sfp1_tx_rst_int;
wire [63:0] sfp1_txd_int;
wire [7:0] sfp1_txc_int;
wire sfp1_rx_clk_int;
wire sfp1_rx_rst_int;
wire [63:0] sfp1_rxd_int;
wire [7:0] sfp1_rxc_int;
assign clk_156mhz_int = sfp0_tx_clk_int;
assign rst_156mhz_int = sfp0_tx_rst_int;
wire sfp0_rx_block_lock;
wire sfp1_rx_block_lock;
wire sfp_mgt_refclk_0;
IBUFDS_GTE4 ibufds_gte4_sfp_mgt_refclk_0_inst (
.I (sfp_mgt_refclk_0_p),
.IB (sfp_mgt_refclk_0_n),
.CEB (1'b0),
.O (sfp_mgt_refclk_0),
.ODIV2 ()
);
wire sfp_qpll0lock;
wire sfp_qpll0outclk;
wire sfp_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
sfp0_phy_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(sfp_mgt_refclk_0),
.xcvr_qpll0lock_out(sfp_qpll0lock),
.xcvr_qpll0outclk_out(sfp_qpll0outclk),
.xcvr_qpll0outrefclk_out(sfp_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(sfp0_tx_p),
.xcvr_txn(sfp0_tx_n),
.xcvr_rxp(sfp0_rx_p),
.xcvr_rxn(sfp0_rx_n),
// PHY connections
.phy_tx_clk(sfp0_tx_clk_int),
.phy_tx_rst(sfp0_tx_rst_int),
.phy_xgmii_txd(sfp0_txd_int),
.phy_xgmii_txc(sfp0_txc_int),
.phy_rx_clk(sfp0_rx_clk_int),
.phy_rx_rst(sfp0_rx_rst_int),
.phy_xgmii_rxd(sfp0_rxd_int),
.phy_xgmii_rxc(sfp0_rxc_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp0_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
sfp1_phy_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(sfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(sfp_qpll0outclk),
.xcvr_qpll0refclk_in(sfp_qpll0outrefclk),
// Serial data
.xcvr_txp(sfp1_tx_p),
.xcvr_txn(sfp1_tx_n),
.xcvr_rxp(sfp1_rx_p),
.xcvr_rxn(sfp1_rx_n),
// PHY connections
.phy_tx_clk(sfp1_tx_clk_int),
.phy_tx_rst(sfp1_tx_rst_int),
.phy_xgmii_txd(sfp1_txd_int),
.phy_xgmii_txc(sfp1_txc_int),
.phy_rx_clk(sfp1_rx_clk_int),
.phy_rx_rst(sfp1_rx_rst_int),
.phy_xgmii_rxd(sfp1_rxd_int),
.phy_xgmii_rxc(sfp1_rxc_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp1_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts),
/*
* Ethernet: SFP+
*/
.sfp0_tx_clk(sfp0_tx_clk_int),
.sfp0_tx_rst(sfp0_tx_rst_int),
.sfp0_txd(sfp0_txd_int),
.sfp0_txc(sfp0_txc_int),
.sfp0_rx_clk(sfp0_rx_clk_int),
.sfp0_rx_rst(sfp0_rx_rst_int),
.sfp0_rxd(sfp0_rxd_int),
.sfp0_rxc(sfp0_rxc_int),
.sfp1_tx_clk(sfp1_tx_clk_int),
.sfp1_tx_rst(sfp1_tx_rst_int),
.sfp1_txd(sfp1_txd_int),
.sfp1_txc(sfp1_txc_int),
.sfp1_rx_clk(sfp1_rx_clk_int),
.sfp1_rx_rst(sfp1_rx_rst_int),
.sfp1_rxd(sfp1_rxd_int),
.sfp1_rxc(sfp1_rxc_int)
);
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_TB_V
/**
* udp_dff$PS_pp$PG: Positive edge triggered D flip-flop with active
* high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_ps_pp_pg.v"
module top();
// Inputs are registered
reg D;
reg SET;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SET = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 SET = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 SET = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 SET = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 SET = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$PS_pp$PG dut (.D(D), .SET(SET), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_BEHAVIORAL_PP_V |
// outputs H for one clock period once edge detected
module edge_detector(
clk,
reset_n,
in, // detector input
out, // detector output
edge_detect // spcifies whether rising or falling edge it to detect
);
`include "parameters_global.v"
input clk;
input reset_n;
input in;
input edge_detect;
output reg out;
reg latch;
always @(posedge clk or negedge reset_n) begin
if (~reset_n)
begin
out <= #`DEL 1'b0;
latch <= #`DEL 1'b0;
end
else
begin
// update latch permanently with in
latch <= #`DEL in;
if (edge_detect == edge_rising)
// detect rising edge
begin
if (latch == 0 && in == 1)
out <= #`DEL 1'b1;
else
out <= #`DEL 1'b0;
end
else
// detect falling edge
begin
if (latch == 1 && in == 0)
out <= #`DEL 1'b1;
else
out <= #`DEL 1'b0;
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 00:51:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_clk_wiz_0_0 -prefix
// system_clk_wiz_0_0_ system_clk_wiz_0_0_stub.v
// Design : system_clk_wiz_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_clk_wiz_0_0(clk_out1, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_in1" */;
output clk_out1;
input clk_in1;
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.3
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="convolve_kernel,hls_ip_2017_3,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=3.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.384000,HLS_SYN_LAT=5467,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=117,HLS_SYN_FF=72137,HLS_SYN_LUT=50295}" *)
module convolve_kernel (
ap_clk,
ap_rst_n,
bufw_0_Addr_A,
bufw_0_EN_A,
bufw_0_WEN_A,
bufw_0_Din_A,
bufw_0_Dout_A,
bufw_0_Clk_A,
bufw_0_Rst_A,
bufw_0_Addr_B,
bufw_0_EN_B,
bufw_0_WEN_B,
bufw_0_Din_B,
bufw_0_Dout_B,
bufw_0_Clk_B,
bufw_0_Rst_B,
bufw_1_Addr_A,
bufw_1_EN_A,
bufw_1_WEN_A,
bufw_1_Din_A,
bufw_1_Dout_A,
bufw_1_Clk_A,
bufw_1_Rst_A,
bufw_1_Addr_B,
bufw_1_EN_B,
bufw_1_WEN_B,
bufw_1_Din_B,
bufw_1_Dout_B,
bufw_1_Clk_B,
bufw_1_Rst_B,
bufw_2_Addr_A,
bufw_2_EN_A,
bufw_2_WEN_A,
bufw_2_Din_A,
bufw_2_Dout_A,
bufw_2_Clk_A,
bufw_2_Rst_A,
bufw_2_Addr_B,
bufw_2_EN_B,
bufw_2_WEN_B,
bufw_2_Din_B,
bufw_2_Dout_B,
bufw_2_Clk_B,
bufw_2_Rst_B,
bufw_3_Addr_A,
bufw_3_EN_A,
bufw_3_WEN_A,
bufw_3_Din_A,
bufw_3_Dout_A,
bufw_3_Clk_A,
bufw_3_Rst_A,
bufw_3_Addr_B,
bufw_3_EN_B,
bufw_3_WEN_B,
bufw_3_Din_B,
bufw_3_Dout_B,
bufw_3_Clk_B,
bufw_3_Rst_B,
bufw_4_Addr_A,
bufw_4_EN_A,
bufw_4_WEN_A,
bufw_4_Din_A,
bufw_4_Dout_A,
bufw_4_Clk_A,
bufw_4_Rst_A,
bufw_4_Addr_B,
bufw_4_EN_B,
bufw_4_WEN_B,
bufw_4_Din_B,
bufw_4_Dout_B,
bufw_4_Clk_B,
bufw_4_Rst_B,
bufw_5_Addr_A,
bufw_5_EN_A,
bufw_5_WEN_A,
bufw_5_Din_A,
bufw_5_Dout_A,
bufw_5_Clk_A,
bufw_5_Rst_A,
bufw_5_Addr_B,
bufw_5_EN_B,
bufw_5_WEN_B,
bufw_5_Din_B,
bufw_5_Dout_B,
bufw_5_Clk_B,
bufw_5_Rst_B,
bufw_6_Addr_A,
bufw_6_EN_A,
bufw_6_WEN_A,
bufw_6_Din_A,
bufw_6_Dout_A,
bufw_6_Clk_A,
bufw_6_Rst_A,
bufw_6_Addr_B,
bufw_6_EN_B,
bufw_6_WEN_B,
bufw_6_Din_B,
bufw_6_Dout_B,
bufw_6_Clk_B,
bufw_6_Rst_B,
bufw_7_Addr_A,
bufw_7_EN_A,
bufw_7_WEN_A,
bufw_7_Din_A,
bufw_7_Dout_A,
bufw_7_Clk_A,
bufw_7_Rst_A,
bufw_7_Addr_B,
bufw_7_EN_B,
bufw_7_WEN_B,
bufw_7_Din_B,
bufw_7_Dout_B,
bufw_7_Clk_B,
bufw_7_Rst_B,
bufw_8_Addr_A,
bufw_8_EN_A,
bufw_8_WEN_A,
bufw_8_Din_A,
bufw_8_Dout_A,
bufw_8_Clk_A,
bufw_8_Rst_A,
bufw_8_Addr_B,
bufw_8_EN_B,
bufw_8_WEN_B,
bufw_8_Din_B,
bufw_8_Dout_B,
bufw_8_Clk_B,
bufw_8_Rst_B,
bufw_9_Addr_A,
bufw_9_EN_A,
bufw_9_WEN_A,
bufw_9_Din_A,
bufw_9_Dout_A,
bufw_9_Clk_A,
bufw_9_Rst_A,
bufw_9_Addr_B,
bufw_9_EN_B,
bufw_9_WEN_B,
bufw_9_Din_B,
bufw_9_Dout_B,
bufw_9_Clk_B,
bufw_9_Rst_B,
bufw_10_Addr_A,
bufw_10_EN_A,
bufw_10_WEN_A,
bufw_10_Din_A,
bufw_10_Dout_A,
bufw_10_Clk_A,
bufw_10_Rst_A,
bufw_10_Addr_B,
bufw_10_EN_B,
bufw_10_WEN_B,
bufw_10_Din_B,
bufw_10_Dout_B,
bufw_10_Clk_B,
bufw_10_Rst_B,
bufw_11_Addr_A,
bufw_11_EN_A,
bufw_11_WEN_A,
bufw_11_Din_A,
bufw_11_Dout_A,
bufw_11_Clk_A,
bufw_11_Rst_A,
bufw_11_Addr_B,
bufw_11_EN_B,
bufw_11_WEN_B,
bufw_11_Din_B,
bufw_11_Dout_B,
bufw_11_Clk_B,
bufw_11_Rst_B,
bufw_12_Addr_A,
bufw_12_EN_A,
bufw_12_WEN_A,
bufw_12_Din_A,
bufw_12_Dout_A,
bufw_12_Clk_A,
bufw_12_Rst_A,
bufw_12_Addr_B,
bufw_12_EN_B,
bufw_12_WEN_B,
bufw_12_Din_B,
bufw_12_Dout_B,
bufw_12_Clk_B,
bufw_12_Rst_B,
bufi_0_Addr_A,
bufi_0_EN_A,
bufi_0_WEN_A,
bufi_0_Din_A,
bufi_0_Dout_A,
bufi_0_Clk_A,
bufi_0_Rst_A,
bufi_0_Addr_B,
bufi_0_EN_B,
bufi_0_WEN_B,
bufi_0_Din_B,
bufi_0_Dout_B,
bufi_0_Clk_B,
bufi_0_Rst_B,
bufi_1_Addr_A,
bufi_1_EN_A,
bufi_1_WEN_A,
bufi_1_Din_A,
bufi_1_Dout_A,
bufi_1_Clk_A,
bufi_1_Rst_A,
bufi_1_Addr_B,
bufi_1_EN_B,
bufi_1_WEN_B,
bufi_1_Din_B,
bufi_1_Dout_B,
bufi_1_Clk_B,
bufi_1_Rst_B,
bufi_2_Addr_A,
bufi_2_EN_A,
bufi_2_WEN_A,
bufi_2_Din_A,
bufi_2_Dout_A,
bufi_2_Clk_A,
bufi_2_Rst_A,
bufi_2_Addr_B,
bufi_2_EN_B,
bufi_2_WEN_B,
bufi_2_Din_B,
bufi_2_Dout_B,
bufi_2_Clk_B,
bufi_2_Rst_B,
bufo_Addr_A,
bufo_EN_A,
bufo_WEN_A,
bufo_Din_A,
bufo_Dout_A,
bufo_Clk_A,
bufo_Rst_A,
bufo_Addr_B,
bufo_EN_B,
bufo_WEN_B,
bufo_Din_B,
bufo_Dout_B,
bufo_Clk_B,
bufo_Rst_B,
s_axi_control_AWVALID,
s_axi_control_AWREADY,
s_axi_control_AWADDR,
s_axi_control_WVALID,
s_axi_control_WREADY,
s_axi_control_WDATA,
s_axi_control_WSTRB,
s_axi_control_ARVALID,
s_axi_control_ARREADY,
s_axi_control_ARADDR,
s_axi_control_RVALID,
s_axi_control_RREADY,
s_axi_control_RDATA,
s_axi_control_RRESP,
s_axi_control_BVALID,
s_axi_control_BREADY,
s_axi_control_BRESP,
interrupt
);
parameter ap_ST_fsm_state1 = 10'd1;
parameter ap_ST_fsm_pp0_stage0 = 10'd2;
parameter ap_ST_fsm_pp0_stage1 = 10'd4;
parameter ap_ST_fsm_pp0_stage2 = 10'd8;
parameter ap_ST_fsm_pp0_stage3 = 10'd16;
parameter ap_ST_fsm_pp0_stage4 = 10'd32;
parameter ap_ST_fsm_pp0_stage5 = 10'd64;
parameter ap_ST_fsm_pp0_stage6 = 10'd128;
parameter ap_ST_fsm_pp0_stage7 = 10'd256;
parameter ap_ST_fsm_state76 = 10'd512;
parameter C_S_AXI_CONTROL_DATA_WIDTH = 32;
parameter C_S_AXI_CONTROL_ADDR_WIDTH = 4;
parameter C_S_AXI_DATA_WIDTH = 32;
parameter C_S_AXI_CONTROL_WSTRB_WIDTH = (32 / 8);
parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
input ap_clk;
input ap_rst_n;
output [31:0] bufw_0_Addr_A;
output bufw_0_EN_A;
output [3:0] bufw_0_WEN_A;
output [31:0] bufw_0_Din_A;
input [31:0] bufw_0_Dout_A;
output bufw_0_Clk_A;
output bufw_0_Rst_A;
output [31:0] bufw_0_Addr_B;
output bufw_0_EN_B;
output [3:0] bufw_0_WEN_B;
output [31:0] bufw_0_Din_B;
input [31:0] bufw_0_Dout_B;
output bufw_0_Clk_B;
output bufw_0_Rst_B;
output [31:0] bufw_1_Addr_A;
output bufw_1_EN_A;
output [3:0] bufw_1_WEN_A;
output [31:0] bufw_1_Din_A;
input [31:0] bufw_1_Dout_A;
output bufw_1_Clk_A;
output bufw_1_Rst_A;
output [31:0] bufw_1_Addr_B;
output bufw_1_EN_B;
output [3:0] bufw_1_WEN_B;
output [31:0] bufw_1_Din_B;
input [31:0] bufw_1_Dout_B;
output bufw_1_Clk_B;
output bufw_1_Rst_B;
output [31:0] bufw_2_Addr_A;
output bufw_2_EN_A;
output [3:0] bufw_2_WEN_A;
output [31:0] bufw_2_Din_A;
input [31:0] bufw_2_Dout_A;
output bufw_2_Clk_A;
output bufw_2_Rst_A;
output [31:0] bufw_2_Addr_B;
output bufw_2_EN_B;
output [3:0] bufw_2_WEN_B;
output [31:0] bufw_2_Din_B;
input [31:0] bufw_2_Dout_B;
output bufw_2_Clk_B;
output bufw_2_Rst_B;
output [31:0] bufw_3_Addr_A;
output bufw_3_EN_A;
output [3:0] bufw_3_WEN_A;
output [31:0] bufw_3_Din_A;
input [31:0] bufw_3_Dout_A;
output bufw_3_Clk_A;
output bufw_3_Rst_A;
output [31:0] bufw_3_Addr_B;
output bufw_3_EN_B;
output [3:0] bufw_3_WEN_B;
output [31:0] bufw_3_Din_B;
input [31:0] bufw_3_Dout_B;
output bufw_3_Clk_B;
output bufw_3_Rst_B;
output [31:0] bufw_4_Addr_A;
output bufw_4_EN_A;
output [3:0] bufw_4_WEN_A;
output [31:0] bufw_4_Din_A;
input [31:0] bufw_4_Dout_A;
output bufw_4_Clk_A;
output bufw_4_Rst_A;
output [31:0] bufw_4_Addr_B;
output bufw_4_EN_B;
output [3:0] bufw_4_WEN_B;
output [31:0] bufw_4_Din_B;
input [31:0] bufw_4_Dout_B;
output bufw_4_Clk_B;
output bufw_4_Rst_B;
output [31:0] bufw_5_Addr_A;
output bufw_5_EN_A;
output [3:0] bufw_5_WEN_A;
output [31:0] bufw_5_Din_A;
input [31:0] bufw_5_Dout_A;
output bufw_5_Clk_A;
output bufw_5_Rst_A;
output [31:0] bufw_5_Addr_B;
output bufw_5_EN_B;
output [3:0] bufw_5_WEN_B;
output [31:0] bufw_5_Din_B;
input [31:0] bufw_5_Dout_B;
output bufw_5_Clk_B;
output bufw_5_Rst_B;
output [31:0] bufw_6_Addr_A;
output bufw_6_EN_A;
output [3:0] bufw_6_WEN_A;
output [31:0] bufw_6_Din_A;
input [31:0] bufw_6_Dout_A;
output bufw_6_Clk_A;
output bufw_6_Rst_A;
output [31:0] bufw_6_Addr_B;
output bufw_6_EN_B;
output [3:0] bufw_6_WEN_B;
output [31:0] bufw_6_Din_B;
input [31:0] bufw_6_Dout_B;
output bufw_6_Clk_B;
output bufw_6_Rst_B;
output [31:0] bufw_7_Addr_A;
output bufw_7_EN_A;
output [3:0] bufw_7_WEN_A;
output [31:0] bufw_7_Din_A;
input [31:0] bufw_7_Dout_A;
output bufw_7_Clk_A;
output bufw_7_Rst_A;
output [31:0] bufw_7_Addr_B;
output bufw_7_EN_B;
output [3:0] bufw_7_WEN_B;
output [31:0] bufw_7_Din_B;
input [31:0] bufw_7_Dout_B;
output bufw_7_Clk_B;
output bufw_7_Rst_B;
output [31:0] bufw_8_Addr_A;
output bufw_8_EN_A;
output [3:0] bufw_8_WEN_A;
output [31:0] bufw_8_Din_A;
input [31:0] bufw_8_Dout_A;
output bufw_8_Clk_A;
output bufw_8_Rst_A;
output [31:0] bufw_8_Addr_B;
output bufw_8_EN_B;
output [3:0] bufw_8_WEN_B;
output [31:0] bufw_8_Din_B;
input [31:0] bufw_8_Dout_B;
output bufw_8_Clk_B;
output bufw_8_Rst_B;
output [31:0] bufw_9_Addr_A;
output bufw_9_EN_A;
output [3:0] bufw_9_WEN_A;
output [31:0] bufw_9_Din_A;
input [31:0] bufw_9_Dout_A;
output bufw_9_Clk_A;
output bufw_9_Rst_A;
output [31:0] bufw_9_Addr_B;
output bufw_9_EN_B;
output [3:0] bufw_9_WEN_B;
output [31:0] bufw_9_Din_B;
input [31:0] bufw_9_Dout_B;
output bufw_9_Clk_B;
output bufw_9_Rst_B;
output [31:0] bufw_10_Addr_A;
output bufw_10_EN_A;
output [3:0] bufw_10_WEN_A;
output [31:0] bufw_10_Din_A;
input [31:0] bufw_10_Dout_A;
output bufw_10_Clk_A;
output bufw_10_Rst_A;
output [31:0] bufw_10_Addr_B;
output bufw_10_EN_B;
output [3:0] bufw_10_WEN_B;
output [31:0] bufw_10_Din_B;
input [31:0] bufw_10_Dout_B;
output bufw_10_Clk_B;
output bufw_10_Rst_B;
output [31:0] bufw_11_Addr_A;
output bufw_11_EN_A;
output [3:0] bufw_11_WEN_A;
output [31:0] bufw_11_Din_A;
input [31:0] bufw_11_Dout_A;
output bufw_11_Clk_A;
output bufw_11_Rst_A;
output [31:0] bufw_11_Addr_B;
output bufw_11_EN_B;
output [3:0] bufw_11_WEN_B;
output [31:0] bufw_11_Din_B;
input [31:0] bufw_11_Dout_B;
output bufw_11_Clk_B;
output bufw_11_Rst_B;
output [31:0] bufw_12_Addr_A;
output bufw_12_EN_A;
output [3:0] bufw_12_WEN_A;
output [31:0] bufw_12_Din_A;
input [31:0] bufw_12_Dout_A;
output bufw_12_Clk_A;
output bufw_12_Rst_A;
output [31:0] bufw_12_Addr_B;
output bufw_12_EN_B;
output [3:0] bufw_12_WEN_B;
output [31:0] bufw_12_Din_B;
input [31:0] bufw_12_Dout_B;
output bufw_12_Clk_B;
output bufw_12_Rst_B;
output [31:0] bufi_0_Addr_A;
output bufi_0_EN_A;
output [3:0] bufi_0_WEN_A;
output [31:0] bufi_0_Din_A;
input [31:0] bufi_0_Dout_A;
output bufi_0_Clk_A;
output bufi_0_Rst_A;
output [31:0] bufi_0_Addr_B;
output bufi_0_EN_B;
output [3:0] bufi_0_WEN_B;
output [31:0] bufi_0_Din_B;
input [31:0] bufi_0_Dout_B;
output bufi_0_Clk_B;
output bufi_0_Rst_B;
output [31:0] bufi_1_Addr_A;
output bufi_1_EN_A;
output [3:0] bufi_1_WEN_A;
output [31:0] bufi_1_Din_A;
input [31:0] bufi_1_Dout_A;
output bufi_1_Clk_A;
output bufi_1_Rst_A;
output [31:0] bufi_1_Addr_B;
output bufi_1_EN_B;
output [3:0] bufi_1_WEN_B;
output [31:0] bufi_1_Din_B;
input [31:0] bufi_1_Dout_B;
output bufi_1_Clk_B;
output bufi_1_Rst_B;
output [31:0] bufi_2_Addr_A;
output bufi_2_EN_A;
output [3:0] bufi_2_WEN_A;
output [31:0] bufi_2_Din_A;
input [31:0] bufi_2_Dout_A;
output bufi_2_Clk_A;
output bufi_2_Rst_A;
output [31:0] bufi_2_Addr_B;
output bufi_2_EN_B;
output [3:0] bufi_2_WEN_B;
output [31:0] bufi_2_Din_B;
input [31:0] bufi_2_Dout_B;
output bufi_2_Clk_B;
output bufi_2_Rst_B;
output [31:0] bufo_Addr_A;
output bufo_EN_A;
output [63:0] bufo_WEN_A;
output [511:0] bufo_Din_A;
input [511:0] bufo_Dout_A;
output bufo_Clk_A;
output bufo_Rst_A;
output [31:0] bufo_Addr_B;
output bufo_EN_B;
output [63:0] bufo_WEN_B;
output [511:0] bufo_Din_B;
input [511:0] bufo_Dout_B;
output bufo_Clk_B;
output bufo_Rst_B;
input s_axi_control_AWVALID;
output s_axi_control_AWREADY;
input [C_S_AXI_CONTROL_ADDR_WIDTH - 1:0] s_axi_control_AWADDR;
input s_axi_control_WVALID;
output s_axi_control_WREADY;
input [C_S_AXI_CONTROL_DATA_WIDTH - 1:0] s_axi_control_WDATA;
input [C_S_AXI_CONTROL_WSTRB_WIDTH - 1:0] s_axi_control_WSTRB;
input s_axi_control_ARVALID;
output s_axi_control_ARREADY;
input [C_S_AXI_CONTROL_ADDR_WIDTH - 1:0] s_axi_control_ARADDR;
output s_axi_control_RVALID;
input s_axi_control_RREADY;
output [C_S_AXI_CONTROL_DATA_WIDTH - 1:0] s_axi_control_RDATA;
output [1:0] s_axi_control_RRESP;
output s_axi_control_BVALID;
input s_axi_control_BREADY;
output [1:0] s_axi_control_BRESP;
output interrupt;
reg bufw_0_EN_A;
reg bufw_0_EN_B;
reg bufw_1_EN_A;
reg bufw_1_EN_B;
reg bufw_2_EN_A;
reg bufw_2_EN_B;
reg bufw_3_EN_A;
reg bufw_3_EN_B;
reg bufw_4_EN_A;
reg bufw_4_EN_B;
reg bufw_5_EN_A;
reg bufw_5_EN_B;
reg bufw_6_EN_A;
reg bufw_6_EN_B;
reg bufw_7_EN_A;
reg bufw_7_EN_B;
reg bufw_8_EN_A;
reg bufw_8_EN_B;
reg bufw_9_EN_A;
reg bufw_9_EN_B;
reg bufw_10_EN_A;
reg bufw_10_EN_B;
reg bufw_11_EN_A;
reg bufw_11_EN_B;
reg bufw_12_EN_A;
reg bufw_12_EN_B;
reg bufi_0_EN_A;
reg bufi_0_EN_B;
reg bufi_1_EN_A;
reg bufi_1_EN_B;
reg bufi_2_EN_A;
reg bufi_2_EN_B;
reg bufo_EN_A;
reg[63:0] bufo_WEN_A;
reg[511:0] bufo_Din_A;
reg bufo_EN_B;
reg[63:0] bufo_WEN_B;
reg[511:0] bufo_Din_B;
reg ap_rst_n_inv;
wire ap_start;
reg ap_done;
reg ap_idle;
(* fsm_encoding = "none" *) reg [9:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_ready;
reg [9:0] indvar_flatten1_reg_885;
reg [2:0] i_reg_896;
reg [7:0] indvar_flatten_reg_908;
reg [2:0] j_reg_919;
reg [4:0] row_b_reg_931;
wire [2:0] tmp_12_1_fu_1499_p2;
reg [2:0] tmp_12_1_reg_3141;
wire ap_CS_fsm_pp0_stage0;
wire ap_block_state2_pp0_stage0_iter0;
wire ap_block_state10_pp0_stage0_iter1;
wire ap_block_state18_pp0_stage0_iter2;
wire ap_block_state26_pp0_stage0_iter3;
wire ap_block_state34_pp0_stage0_iter4;
wire ap_block_state42_pp0_stage0_iter5;
wire ap_block_state50_pp0_stage0_iter6;
wire ap_block_state58_pp0_stage0_iter7;
wire ap_block_state66_pp0_stage0_iter8;
wire ap_block_state74_pp0_stage0_iter9;
wire ap_block_pp0_stage0_11001;
wire [2:0] tmp_12_2_fu_1505_p2;
reg [2:0] tmp_12_2_reg_3146;
wire [2:0] tmp_12_3_fu_1511_p2;
reg [2:0] tmp_12_3_reg_3151;
wire [3:0] tmp_12_4_fu_1517_p2;
reg [3:0] tmp_12_4_reg_3156;
wire [3:0] tmp_12_5_fu_1523_p2;
reg [3:0] tmp_12_5_reg_3161;
wire [3:0] tmp_12_6_fu_1529_p2;
reg [3:0] tmp_12_6_reg_3166;
wire [3:0] tmp_12_7_fu_1535_p2;
reg [3:0] tmp_12_7_reg_3171;
wire [0:0] exitcond_flatten1_fu_1541_p2;
reg [0:0] exitcond_flatten1_reg_3176;
reg [0:0] ap_reg_pp0_iter1_exitcond_flatten1_reg_3176;
reg [0:0] ap_reg_pp0_iter2_exitcond_flatten1_reg_3176;
reg [0:0] ap_reg_pp0_iter3_exitcond_flatten1_reg_3176;
reg [0:0] ap_reg_pp0_iter4_exitcond_flatten1_reg_3176;
reg [0:0] ap_reg_pp0_iter5_exitcond_flatten1_reg_3176;
reg [0:0] ap_reg_pp0_iter6_exitcond_flatten1_reg_3176;
reg [0:0] ap_reg_pp0_iter7_exitcond_flatten1_reg_3176;
reg [0:0] ap_reg_pp0_iter8_exitcond_flatten1_reg_3176;
reg [0:0] ap_reg_pp0_iter9_exitcond_flatten1_reg_3176;
wire [9:0] indvar_flatten_next1_fu_1547_p2;
reg [9:0] indvar_flatten_next1_reg_3180;
reg ap_enable_reg_pp0_iter0;
wire [2:0] i_1_fu_1553_p2;
reg [2:0] i_1_reg_3185;
wire [0:0] exitcond_flatten_fu_1559_p2;
reg [0:0] exitcond_flatten_reg_3190;
wire [0:0] tmp_5_fu_1565_p2;
reg [0:0] tmp_5_reg_3206;
wire [7:0] indvar_flatten_op_fu_1571_p2;
reg [7:0] indvar_flatten_op_reg_3211;
wire [2:0] j_mid_fu_1577_p3;
reg [2:0] j_mid_reg_3216;
wire ap_CS_fsm_pp0_stage1;
wire ap_block_state3_pp0_stage1_iter0;
wire ap_block_state11_pp0_stage1_iter1;
wire ap_block_state19_pp0_stage1_iter2;
wire ap_block_state27_pp0_stage1_iter3;
wire ap_block_state35_pp0_stage1_iter4;
wire ap_block_state43_pp0_stage1_iter5;
wire ap_block_state51_pp0_stage1_iter6;
wire ap_block_state59_pp0_stage1_iter7;
wire ap_block_state67_pp0_stage1_iter8;
wire ap_block_state75_pp0_stage1_iter9;
wire ap_block_pp0_stage1_11001;
wire [2:0] tmp_1_mid2_v_fu_1584_p3;
reg [2:0] tmp_1_mid2_v_reg_3225;
wire [0:0] tmp_7_mid_fu_1595_p2;
reg [0:0] tmp_7_mid_reg_3233;
wire [4:0] row_b_mid2_fu_1605_p3;
reg [4:0] row_b_mid2_reg_3245;
reg [4:0] ap_reg_pp0_iter1_row_b_mid2_reg_3245;
wire [7:0] indvar_flatten_next_fu_1613_p3;
reg [7:0] indvar_flatten_next_reg_3252;
wire [5:0] tmp_1_fu_1633_p2;
reg [5:0] tmp_1_reg_3257;
wire ap_CS_fsm_pp0_stage2;
wire ap_block_state4_pp0_stage2_iter0;
wire ap_block_state12_pp0_stage2_iter1;
wire ap_block_state20_pp0_stage2_iter2;
wire ap_block_state28_pp0_stage2_iter3;
wire ap_block_state36_pp0_stage2_iter4;
wire ap_block_state44_pp0_stage2_iter5;
wire ap_block_state52_pp0_stage2_iter6;
wire ap_block_state60_pp0_stage2_iter7;
wire ap_block_state68_pp0_stage2_iter8;
wire ap_block_pp0_stage2_11001;
wire [2:0] j_1_fu_1642_p2;
reg [2:0] j_1_reg_3264;
wire [4:0] tmp_s_fu_1647_p2;
reg [4:0] tmp_s_reg_3270;
wire [4:0] row_b_1_fu_1652_p2;
reg [4:0] row_b_1_reg_3276;
wire [5:0] tmp_2_fu_1657_p2;
reg [5:0] tmp_2_reg_3281;
wire ap_CS_fsm_pp0_stage3;
wire ap_block_state5_pp0_stage3_iter0;
wire ap_block_state13_pp0_stage3_iter1;
wire ap_block_state21_pp0_stage3_iter2;
wire ap_block_state29_pp0_stage3_iter3;
wire ap_block_state37_pp0_stage3_iter4;
wire ap_block_state45_pp0_stage3_iter5;
wire ap_block_state53_pp0_stage3_iter6;
wire ap_block_state61_pp0_stage3_iter7;
wire ap_block_state69_pp0_stage3_iter8;
wire ap_block_pp0_stage3_11001;
wire [2:0] tmp_5_mid2_fu_1662_p3;
reg [2:0] tmp_5_mid2_reg_3286;
wire [2:0] tmp_12_1_mid1_fu_1667_p2;
reg [2:0] tmp_12_1_mid1_reg_3294;
wire [9:0] tmp_90_fu_1694_p2;
reg [9:0] tmp_90_reg_3299;
wire [6:0] tmp_3_fu_1706_p2;
reg [6:0] tmp_3_reg_3311;
wire ap_CS_fsm_pp0_stage4;
wire ap_block_state6_pp0_stage4_iter0;
wire ap_block_state14_pp0_stage4_iter1;
wire ap_block_state22_pp0_stage4_iter2;
wire ap_block_state30_pp0_stage4_iter3;
wire ap_block_state38_pp0_stage4_iter4;
wire ap_block_state46_pp0_stage4_iter5;
wire ap_block_state54_pp0_stage4_iter6;
wire ap_block_state62_pp0_stage4_iter7;
wire ap_block_state70_pp0_stage4_iter8;
wire ap_block_pp0_stage4_11001;
wire [6:0] tmp_5_mid2_cast2_fu_1721_p1;
reg [6:0] tmp_5_mid2_cast2_reg_3316;
wire [5:0] tmp_6_fu_1727_p2;
reg [5:0] tmp_6_reg_3321;
wire [6:0] tmp_8_fu_1732_p2;
reg [6:0] tmp_8_reg_3326;
wire [2:0] tmp_12_2_mid1_fu_1748_p2;
reg [2:0] tmp_12_2_mid1_reg_3331;
wire [9:0] tmp_130_fu_1753_p2;
reg [9:0] tmp_130_reg_3336;
wire [9:0] tmp_170_fu_1758_p2;
reg [9:0] tmp_170_reg_3341;
wire ap_CS_fsm_pp0_stage5;
wire ap_block_state7_pp0_stage5_iter0;
wire ap_block_state15_pp0_stage5_iter1;
wire ap_block_state23_pp0_stage5_iter2;
wire ap_block_state31_pp0_stage5_iter3;
wire ap_block_state39_pp0_stage5_iter4;
wire ap_block_state47_pp0_stage5_iter5;
wire ap_block_state55_pp0_stage5_iter6;
wire ap_block_state63_pp0_stage5_iter7;
wire ap_block_state71_pp0_stage5_iter8;
wire ap_block_pp0_stage5_11001;
wire [6:0] tmp_7_fu_1807_p2;
reg [6:0] tmp_7_reg_3356;
wire [3:0] tmp_12_4_mid1_fu_1840_p2;
reg [3:0] tmp_12_4_mid1_reg_3481;
wire [3:0] tmp_12_5_mid1_fu_1846_p2;
reg [3:0] tmp_12_5_mid1_reg_3486;
wire [3:0] tmp_12_6_mid1_fu_1852_p2;
reg [3:0] tmp_12_6_mid1_reg_3491;
wire [3:0] tmp_12_7_mid1_fu_1858_p2;
reg [3:0] tmp_12_7_mid1_reg_3496;
wire [9:0] tmp_210_fu_1876_p2;
reg [9:0] tmp_210_reg_3511;
wire [9:0] tmp_250_fu_1881_p2;
reg [9:0] tmp_250_reg_3516;
wire ap_CS_fsm_pp0_stage6;
wire ap_block_state8_pp0_stage6_iter0;
wire ap_block_state16_pp0_stage6_iter1;
wire ap_block_state24_pp0_stage6_iter2;
wire ap_block_state32_pp0_stage6_iter3;
wire ap_block_state40_pp0_stage6_iter4;
wire ap_block_state48_pp0_stage6_iter5;
wire ap_block_state56_pp0_stage6_iter6;
wire ap_block_state64_pp0_stage6_iter7;
wire ap_block_state72_pp0_stage6_iter8;
wire ap_block_pp0_stage6_11001;
wire [9:0] tmp_290_fu_1978_p2;
reg [9:0] tmp_290_reg_3616;
wire [9:0] tmp_330_fu_1983_p2;
reg [9:0] tmp_330_reg_3621;
wire [9:0] tmp_331_fu_1988_p2;
reg [9:0] tmp_331_reg_3626;
wire [9:0] tmp_332_fu_1993_p2;
reg [9:0] tmp_332_reg_3631;
wire ap_CS_fsm_pp0_stage7;
wire ap_block_state9_pp0_stage7_iter0;
wire ap_block_state17_pp0_stage7_iter1;
wire ap_block_state25_pp0_stage7_iter2;
wire ap_block_state33_pp0_stage7_iter3;
wire ap_block_state41_pp0_stage7_iter4;
wire ap_block_state49_pp0_stage7_iter5;
wire ap_block_state57_pp0_stage7_iter6;
wire ap_block_state65_pp0_stage7_iter7;
wire ap_block_state73_pp0_stage7_iter8;
wire ap_block_pp0_stage7_11001;
reg [31:0] bufw_0_load_reg_3686;
reg [31:0] bufi_0_load_reg_3693;
reg [31:0] bufw_0_load_1_reg_3710;
reg [31:0] bufi_1_load_reg_3718;
reg [31:0] bufi_2_load_reg_3735;
reg [31:0] bufw_1_load_reg_3752;
reg [31:0] bufw_1_load_1_reg_3759;
reg [31:0] bufw_2_load_reg_3767;
reg [31:0] bufw_2_load_1_reg_3774;
reg [31:0] bufw_3_load_reg_3782;
reg [31:0] bufw_3_load_1_reg_3789;
reg [31:0] bufw_4_load_reg_3797;
reg [31:0] bufw_4_load_1_reg_3804;
reg [31:0] bufw_5_load_reg_3812;
reg [31:0] bufw_5_load_1_reg_3819;
reg [31:0] bufw_6_load_reg_3827;
reg [31:0] bufw_6_load_1_reg_3834;
reg [31:0] bufw_7_load_reg_3842;
reg [31:0] bufw_7_load_1_reg_3849;
reg [31:0] bufw_8_load_reg_3857;
reg [31:0] bufw_8_load_1_reg_3864;
reg [31:0] bufw_9_load_reg_3872;
reg [31:0] bufw_9_load_1_reg_3879;
reg [31:0] bufw_10_load_reg_3887;
reg [31:0] bufw_10_load_1_reg_3894;
reg [31:0] bufw_11_load_reg_3902;
reg [31:0] bufw_11_load_1_reg_3909;
reg [31:0] bufw_12_load_reg_3917;
reg [31:0] bufw_12_load_1_reg_3924;
reg [31:0] bufi_0_load_1_reg_3931;
reg [31:0] bufi_1_load_1_reg_3948;
reg [31:0] bufi_2_load_1_reg_3965;
reg [31:0] bufw_0_load_2_reg_4012;
reg ap_enable_reg_pp0_iter1;
reg [31:0] bufw_1_load_2_reg_4019;
reg [31:0] bufw_2_load_2_reg_4026;
reg [31:0] bufw_3_load_2_reg_4033;
reg [31:0] bufw_4_load_2_reg_4040;
reg [31:0] bufw_5_load_2_reg_4047;
reg [31:0] bufw_6_load_2_reg_4054;
reg [31:0] bufw_7_load_2_reg_4061;
reg [31:0] bufw_8_load_2_reg_4068;
reg [31:0] bufw_9_load_2_reg_4075;
reg [31:0] bufw_10_load_2_reg_4082;
reg [31:0] bufw_11_load_2_reg_4089;
reg [31:0] bufw_12_load_2_reg_4096;
reg [31:0] bufi_0_load_2_reg_4103;
reg [31:0] bufi_1_load_2_reg_4120;
reg [31:0] bufi_2_load_2_reg_4137;
reg [31:0] bufi_0_load_3_reg_4154;
reg [31:0] bufi_1_load_3_reg_4171;
reg [31:0] bufi_2_load_3_reg_4188;
reg [31:0] bufi_0_load_4_reg_4205;
reg [31:0] bufi_1_load_4_reg_4222;
reg [31:0] bufi_2_load_4_reg_4239;
reg [31:0] bufi_0_load_5_reg_4256;
reg [31:0] bufi_1_load_5_reg_4273;
reg [31:0] bufi_2_load_5_reg_4290;
wire [7:0] tmp_333_fu_2022_p3;
reg [7:0] tmp_333_reg_4307;
reg [7:0] bufo_addr_reg_4317;
reg [7:0] ap_reg_pp0_iter2_bufo_addr_reg_4317;
reg [7:0] ap_reg_pp0_iter3_bufo_addr_reg_4317;
reg [7:0] ap_reg_pp0_iter4_bufo_addr_reg_4317;
reg [7:0] ap_reg_pp0_iter5_bufo_addr_reg_4317;
reg [7:0] ap_reg_pp0_iter6_bufo_addr_reg_4317;
reg [7:0] ap_reg_pp0_iter7_bufo_addr_reg_4317;
reg [7:0] bufo_addr_1_reg_4322;
reg [7:0] ap_reg_pp0_iter2_bufo_addr_1_reg_4322;
reg [7:0] ap_reg_pp0_iter3_bufo_addr_1_reg_4322;
reg [7:0] ap_reg_pp0_iter4_bufo_addr_1_reg_4322;
reg [7:0] ap_reg_pp0_iter5_bufo_addr_1_reg_4322;
reg [7:0] ap_reg_pp0_iter6_bufo_addr_1_reg_4322;
reg [7:0] ap_reg_pp0_iter7_bufo_addr_1_reg_4322;
reg [31:0] bufi_0_load_6_reg_4327;
reg [31:0] bufi_1_load_6_reg_4344;
reg [31:0] bufi_2_load_6_reg_4361;
reg [31:0] bufi_0_load_7_reg_4378;
reg [31:0] bufi_1_load_7_reg_4395;
reg [31:0] bufi_2_load_7_reg_4412;
reg [7:0] bufo_addr_2_reg_4429;
reg [7:0] ap_reg_pp0_iter2_bufo_addr_2_reg_4429;
reg [7:0] ap_reg_pp0_iter3_bufo_addr_2_reg_4429;
reg [7:0] ap_reg_pp0_iter4_bufo_addr_2_reg_4429;
reg [7:0] ap_reg_pp0_iter5_bufo_addr_2_reg_4429;
reg [7:0] ap_reg_pp0_iter6_bufo_addr_2_reg_4429;
reg [7:0] ap_reg_pp0_iter7_bufo_addr_2_reg_4429;
reg [7:0] bufo_addr_3_reg_4434;
reg [7:0] ap_reg_pp0_iter2_bufo_addr_3_reg_4434;
reg [7:0] ap_reg_pp0_iter3_bufo_addr_3_reg_4434;
reg [7:0] ap_reg_pp0_iter4_bufo_addr_3_reg_4434;
reg [7:0] ap_reg_pp0_iter5_bufo_addr_3_reg_4434;
reg [7:0] ap_reg_pp0_iter6_bufo_addr_3_reg_4434;
reg [7:0] ap_reg_pp0_iter7_bufo_addr_3_reg_4434;
reg [7:0] bufo_addr_4_reg_4439;
reg [7:0] ap_reg_pp0_iter2_bufo_addr_4_reg_4439;
reg [7:0] ap_reg_pp0_iter3_bufo_addr_4_reg_4439;
reg [7:0] ap_reg_pp0_iter4_bufo_addr_4_reg_4439;
reg [7:0] ap_reg_pp0_iter5_bufo_addr_4_reg_4439;
reg [7:0] ap_reg_pp0_iter6_bufo_addr_4_reg_4439;
reg [7:0] ap_reg_pp0_iter7_bufo_addr_4_reg_4439;
reg [7:0] bufo_addr_5_reg_4444;
reg [7:0] ap_reg_pp0_iter2_bufo_addr_5_reg_4444;
reg [7:0] ap_reg_pp0_iter3_bufo_addr_5_reg_4444;
reg [7:0] ap_reg_pp0_iter4_bufo_addr_5_reg_4444;
reg [7:0] ap_reg_pp0_iter5_bufo_addr_5_reg_4444;
reg [7:0] ap_reg_pp0_iter6_bufo_addr_5_reg_4444;
reg [7:0] ap_reg_pp0_iter7_bufo_addr_5_reg_4444;
wire [31:0] tmp_350_fu_2105_p1;
reg [31:0] tmp_350_reg_4449;
reg [31:0] tmp_13_reg_4454;
reg [31:0] tmp_16_reg_4459;
reg [31:0] tmp_19_reg_4464;
reg [31:0] tmp_22_reg_4469;
reg [31:0] tmp_25_reg_4474;
reg [31:0] tmp_28_reg_4479;
reg [31:0] tmp_31_reg_4484;
reg [31:0] tmp_34_reg_4489;
reg [31:0] tmp_37_reg_4494;
reg [31:0] tmp_40_reg_4499;
reg [31:0] tmp_43_reg_4504;
reg [31:0] tmp_46_reg_4509;
wire [31:0] tmp_352_fu_2109_p1;
reg [31:0] tmp_352_reg_4514;
reg [31:0] tmp_53_reg_4519;
reg [31:0] tmp_56_reg_4524;
reg [31:0] tmp_59_reg_4529;
reg [31:0] tmp_62_reg_4534;
reg [31:0] tmp_65_reg_4539;
reg [31:0] tmp_68_reg_4544;
reg [31:0] tmp_71_reg_4549;
reg [31:0] tmp_74_reg_4554;
reg [31:0] tmp_77_reg_4559;
reg [31:0] tmp_80_reg_4564;
reg [31:0] tmp_83_reg_4569;
reg [31:0] tmp_86_reg_4574;
reg [7:0] bufo_addr_6_reg_4579;
reg [7:0] ap_reg_pp0_iter2_bufo_addr_6_reg_4579;
reg [7:0] ap_reg_pp0_iter3_bufo_addr_6_reg_4579;
reg [7:0] ap_reg_pp0_iter4_bufo_addr_6_reg_4579;
reg [7:0] ap_reg_pp0_iter5_bufo_addr_6_reg_4579;
reg [7:0] ap_reg_pp0_iter6_bufo_addr_6_reg_4579;
reg [7:0] ap_reg_pp0_iter7_bufo_addr_6_reg_4579;
reg [7:0] ap_reg_pp0_iter8_bufo_addr_6_reg_4579;
reg [7:0] bufo_addr_7_reg_4584;
reg [7:0] ap_reg_pp0_iter2_bufo_addr_7_reg_4584;
reg [7:0] ap_reg_pp0_iter3_bufo_addr_7_reg_4584;
reg [7:0] ap_reg_pp0_iter4_bufo_addr_7_reg_4584;
reg [7:0] ap_reg_pp0_iter5_bufo_addr_7_reg_4584;
reg [7:0] ap_reg_pp0_iter6_bufo_addr_7_reg_4584;
reg [7:0] ap_reg_pp0_iter7_bufo_addr_7_reg_4584;
reg [7:0] ap_reg_pp0_iter8_bufo_addr_7_reg_4584;
wire [31:0] tmp_353_fu_2141_p1;
reg [31:0] tmp_353_reg_4589;
reg [31:0] tmp_93_reg_4594;
reg [31:0] tmp_96_reg_4599;
reg [31:0] tmp_99_reg_4604;
reg [31:0] tmp_102_reg_4609;
reg [31:0] tmp_105_reg_4614;
reg [31:0] tmp_108_reg_4619;
reg [31:0] tmp_111_reg_4624;
reg [31:0] tmp_114_reg_4629;
reg [31:0] tmp_117_reg_4634;
reg [31:0] tmp_120_reg_4639;
reg [31:0] tmp_123_reg_4644;
reg [31:0] tmp_126_reg_4649;
wire [31:0] tmp_354_fu_2145_p1;
reg [31:0] tmp_354_reg_4654;
reg [31:0] tmp_133_reg_4659;
reg [31:0] tmp_136_reg_4664;
reg [31:0] tmp_139_reg_4669;
reg [31:0] tmp_142_reg_4674;
reg [31:0] tmp_145_reg_4679;
reg [31:0] tmp_148_reg_4684;
reg [31:0] tmp_151_reg_4689;
reg [31:0] tmp_154_reg_4694;
reg [31:0] tmp_157_reg_4699;
reg [31:0] tmp_160_reg_4704;
reg [31:0] tmp_163_reg_4709;
reg [31:0] tmp_166_reg_4714;
wire [31:0] tmp_355_fu_2149_p1;
reg [31:0] tmp_355_reg_4719;
reg [31:0] tmp_173_reg_4724;
reg [31:0] tmp_176_reg_4729;
reg [31:0] tmp_179_reg_4734;
reg [31:0] tmp_182_reg_4739;
reg [31:0] tmp_185_reg_4744;
reg [31:0] tmp_188_reg_4749;
reg [31:0] tmp_191_reg_4754;
reg [31:0] tmp_194_reg_4759;
reg [31:0] tmp_197_reg_4764;
reg [31:0] tmp_200_reg_4769;
reg [31:0] tmp_203_reg_4774;
reg [31:0] tmp_206_reg_4779;
wire [31:0] tmp_356_fu_2153_p1;
reg [31:0] tmp_356_reg_4784;
reg [31:0] tmp_213_reg_4789;
reg [31:0] tmp_216_reg_4794;
reg [31:0] tmp_219_reg_4799;
reg [31:0] tmp_222_reg_4804;
reg [31:0] tmp_225_reg_4809;
reg [31:0] tmp_228_reg_4814;
reg [31:0] tmp_231_reg_4819;
reg [31:0] tmp_234_reg_4824;
reg [31:0] tmp_237_reg_4829;
reg [31:0] tmp_240_reg_4834;
reg [31:0] tmp_243_reg_4839;
reg [31:0] tmp_246_reg_4844;
wire [31:0] grp_fu_1099_p2;
reg [31:0] tmp_349_reg_4849;
wire [31:0] grp_fu_1103_p2;
reg [31:0] tmp_19_0_0_1_reg_4854;
reg [31:0] ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854;
wire [31:0] grp_fu_1107_p2;
reg [31:0] tmp_19_0_1_reg_4859;
wire [31:0] grp_fu_1111_p2;
reg [31:0] tmp_19_0_1_1_reg_4864;
reg [31:0] ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864;
wire [31:0] grp_fu_1115_p2;
reg [31:0] tmp_19_0_2_reg_4869;
wire [31:0] grp_fu_1119_p2;
reg [31:0] tmp_19_0_2_1_reg_4874;
reg [31:0] ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874;
wire [31:0] grp_fu_1123_p2;
reg [31:0] tmp_19_0_3_reg_4879;
wire [31:0] grp_fu_1127_p2;
reg [31:0] tmp_19_0_3_1_reg_4884;
reg [31:0] ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884;
wire [31:0] grp_fu_1131_p2;
reg [31:0] tmp_19_0_4_reg_4889;
wire [31:0] grp_fu_1135_p2;
reg [31:0] tmp_19_0_4_1_reg_4894;
reg [31:0] ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894;
wire [31:0] grp_fu_1139_p2;
reg [31:0] tmp_19_0_5_reg_4899;
wire [31:0] grp_fu_1143_p2;
reg [31:0] tmp_19_0_5_1_reg_4904;
reg [31:0] ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904;
wire [31:0] grp_fu_1147_p2;
reg [31:0] tmp_19_0_6_reg_4909;
wire [31:0] grp_fu_1151_p2;
reg [31:0] tmp_19_0_6_1_reg_4914;
reg [31:0] ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914;
wire [31:0] grp_fu_1155_p2;
reg [31:0] tmp_19_0_7_reg_4919;
wire [31:0] grp_fu_1159_p2;
reg [31:0] tmp_19_0_7_1_reg_4924;
reg [31:0] ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924;
wire [31:0] grp_fu_1163_p2;
reg [31:0] tmp_19_0_8_reg_4929;
wire [31:0] grp_fu_1167_p2;
reg [31:0] tmp_19_0_8_1_reg_4934;
reg [31:0] ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934;
wire [31:0] grp_fu_1171_p2;
reg [31:0] tmp_19_0_9_reg_4939;
wire [31:0] grp_fu_1175_p2;
reg [31:0] tmp_19_0_9_1_reg_4944;
reg [31:0] ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944;
wire [31:0] grp_fu_1179_p2;
reg [31:0] tmp_19_0_s_reg_4949;
wire [31:0] grp_fu_1183_p2;
reg [31:0] tmp_19_0_10_1_reg_4954;
reg [31:0] ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954;
wire [31:0] grp_fu_1187_p2;
reg [31:0] tmp_19_0_10_reg_4959;
wire [31:0] grp_fu_1191_p2;
reg [31:0] tmp_19_0_11_1_reg_4964;
reg [31:0] ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964;
wire [31:0] grp_fu_1195_p2;
reg [31:0] tmp_19_0_11_reg_4969;
wire [31:0] grp_fu_1199_p2;
reg [31:0] tmp_19_0_12_1_reg_4974;
reg [31:0] ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974;
wire [31:0] grp_fu_1203_p2;
reg [31:0] tmp_19_1_reg_4979;
wire [31:0] grp_fu_1207_p2;
reg [31:0] tmp_19_1_1_reg_4984;
wire [31:0] grp_fu_1211_p2;
reg [31:0] tmp_19_1_2_reg_4989;
wire [31:0] grp_fu_1215_p2;
reg [31:0] tmp_19_1_3_reg_4994;
wire [31:0] grp_fu_1219_p2;
reg [31:0] tmp_19_1_4_reg_4999;
wire [31:0] grp_fu_1223_p2;
reg [31:0] tmp_19_1_5_reg_5004;
wire [31:0] grp_fu_1227_p2;
reg [31:0] tmp_19_1_6_reg_5009;
wire [31:0] grp_fu_1231_p2;
reg [31:0] tmp_19_1_7_reg_5014;
wire [31:0] grp_fu_1235_p2;
reg [31:0] tmp_19_1_8_reg_5019;
wire [31:0] grp_fu_1239_p2;
reg [31:0] tmp_19_1_9_reg_5024;
wire [31:0] grp_fu_1243_p2;
reg [31:0] tmp_19_1_s_reg_5029;
wire [31:0] grp_fu_1247_p2;
reg [31:0] tmp_19_1_10_reg_5034;
wire [31:0] grp_fu_1251_p2;
reg [31:0] tmp_19_1_11_reg_5039;
wire [31:0] tmp_357_fu_2157_p1;
reg [31:0] tmp_357_reg_5044;
reg [31:0] tmp_253_reg_5049;
reg [31:0] tmp_256_reg_5054;
reg [31:0] tmp_259_reg_5059;
reg [31:0] tmp_262_reg_5064;
reg [31:0] tmp_265_reg_5069;
reg [31:0] tmp_268_reg_5074;
reg [31:0] tmp_271_reg_5079;
reg [31:0] tmp_274_reg_5084;
reg [31:0] tmp_277_reg_5089;
reg [31:0] tmp_280_reg_5094;
reg [31:0] tmp_283_reg_5099;
reg [31:0] tmp_286_reg_5104;
wire [31:0] tmp_358_fu_2161_p1;
reg [31:0] tmp_358_reg_5109;
reg [31:0] tmp_293_reg_5114;
reg [31:0] tmp_296_reg_5119;
reg [31:0] tmp_299_reg_5124;
reg [31:0] tmp_302_reg_5129;
reg [31:0] tmp_305_reg_5134;
reg [31:0] tmp_308_reg_5139;
reg [31:0] tmp_311_reg_5144;
reg [31:0] tmp_314_reg_5149;
reg [31:0] tmp_317_reg_5154;
reg [31:0] tmp_320_reg_5159;
reg [31:0] tmp_323_reg_5164;
reg [31:0] tmp_326_reg_5169;
wire [31:0] tmp_11_fu_2165_p1;
wire [31:0] tmp_14_fu_2169_p1;
wire [31:0] tmp_17_fu_2173_p1;
wire [31:0] tmp_20_fu_2177_p1;
wire [31:0] tmp_23_fu_2181_p1;
wire [31:0] tmp_26_fu_2185_p1;
wire [31:0] tmp_29_fu_2189_p1;
wire [31:0] tmp_32_fu_2193_p1;
wire [31:0] tmp_35_fu_2197_p1;
wire [31:0] tmp_38_fu_2201_p1;
wire [31:0] tmp_41_fu_2205_p1;
wire [31:0] tmp_44_fu_2209_p1;
wire [31:0] tmp_47_fu_2213_p1;
wire [31:0] tmp_51_fu_2217_p1;
reg [31:0] tmp_19_1_0_1_reg_5244;
reg ap_enable_reg_pp0_iter2;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244;
wire [31:0] tmp_54_fu_2221_p1;
reg [31:0] tmp_19_1_1_1_reg_5254;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254;
wire [31:0] tmp_57_fu_2225_p1;
reg [31:0] tmp_19_1_2_1_reg_5264;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264;
wire [31:0] tmp_60_fu_2229_p1;
reg [31:0] tmp_19_1_3_1_reg_5274;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274;
wire [31:0] tmp_63_fu_2233_p1;
reg [31:0] tmp_19_1_4_1_reg_5284;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284;
wire [31:0] tmp_66_fu_2237_p1;
reg [31:0] tmp_19_1_5_1_reg_5294;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294;
wire [31:0] tmp_69_fu_2241_p1;
reg [31:0] tmp_19_1_6_1_reg_5304;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304;
wire [31:0] tmp_72_fu_2245_p1;
reg [31:0] tmp_19_1_7_1_reg_5314;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314;
wire [31:0] tmp_75_fu_2249_p1;
reg [31:0] tmp_19_1_8_1_reg_5324;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324;
wire [31:0] tmp_78_fu_2253_p1;
reg [31:0] tmp_19_1_9_1_reg_5334;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334;
wire [31:0] tmp_81_fu_2257_p1;
reg [31:0] tmp_19_1_10_1_reg_5344;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344;
wire [31:0] tmp_84_fu_2261_p1;
reg [31:0] tmp_19_1_11_1_reg_5354;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354;
wire [31:0] tmp_87_fu_2265_p1;
reg [31:0] tmp_19_1_12_1_reg_5364;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364;
reg [31:0] tmp_19_2_reg_5369;
reg [31:0] tmp_19_2_1_reg_5374;
reg [31:0] tmp_19_2_2_reg_5379;
reg [31:0] tmp_19_2_3_reg_5384;
reg [31:0] tmp_19_2_4_reg_5389;
reg [31:0] tmp_19_2_5_reg_5394;
reg [31:0] tmp_19_2_6_reg_5399;
reg [31:0] tmp_19_2_7_reg_5404;
reg [31:0] tmp_19_2_8_reg_5409;
reg [31:0] tmp_19_2_9_reg_5414;
reg [31:0] tmp_19_2_s_reg_5419;
reg [31:0] tmp_19_2_10_reg_5424;
reg [31:0] tmp_19_2_11_reg_5429;
reg [31:0] tmp_19_3_reg_5434;
reg [31:0] tmp_19_3_1_reg_5439;
reg [31:0] tmp_19_3_2_reg_5444;
reg [31:0] tmp_19_3_3_reg_5449;
reg [31:0] tmp_19_3_4_reg_5454;
reg [31:0] tmp_19_3_5_reg_5459;
reg [31:0] tmp_19_3_6_reg_5464;
reg [31:0] tmp_19_3_7_reg_5469;
reg [31:0] tmp_19_3_8_reg_5474;
reg [31:0] tmp_19_3_9_reg_5479;
reg [31:0] tmp_19_3_s_reg_5484;
reg [31:0] tmp_19_3_10_reg_5489;
reg [31:0] tmp_19_3_11_reg_5494;
wire [31:0] tmp_91_fu_2269_p1;
reg [31:0] tmp_19_2_0_1_reg_5504;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504;
wire [31:0] tmp_94_fu_2273_p1;
reg [31:0] tmp_19_2_1_1_reg_5514;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514;
wire [31:0] tmp_97_fu_2277_p1;
reg [31:0] tmp_19_2_2_1_reg_5524;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524;
wire [31:0] tmp_100_fu_2281_p1;
reg [31:0] tmp_19_2_3_1_reg_5534;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534;
wire [31:0] tmp_103_fu_2285_p1;
reg [31:0] tmp_19_2_4_1_reg_5544;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544;
wire [31:0] tmp_106_fu_2289_p1;
reg [31:0] tmp_19_2_5_1_reg_5554;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554;
wire [31:0] tmp_109_fu_2293_p1;
reg [31:0] tmp_19_2_6_1_reg_5564;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564;
wire [31:0] tmp_112_fu_2297_p1;
reg [31:0] tmp_19_2_7_1_reg_5574;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574;
wire [31:0] tmp_115_fu_2301_p1;
reg [31:0] tmp_19_2_8_1_reg_5584;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584;
wire [31:0] tmp_118_fu_2305_p1;
reg [31:0] tmp_19_2_9_1_reg_5594;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594;
wire [31:0] tmp_121_fu_2309_p1;
reg [31:0] tmp_19_2_10_1_reg_5604;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604;
wire [31:0] tmp_124_fu_2313_p1;
reg [31:0] tmp_19_2_11_1_reg_5614;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614;
wire [31:0] tmp_127_fu_2317_p1;
reg [31:0] tmp_19_2_12_1_reg_5624;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624;
wire [31:0] tmp_131_fu_2321_p1;
wire [31:0] tmp_134_fu_2325_p1;
wire [31:0] tmp_137_fu_2329_p1;
wire [31:0] tmp_140_fu_2333_p1;
wire [31:0] tmp_143_fu_2337_p1;
wire [31:0] tmp_146_fu_2341_p1;
wire [31:0] tmp_149_fu_2345_p1;
wire [31:0] tmp_152_fu_2349_p1;
wire [31:0] tmp_155_fu_2353_p1;
wire [31:0] tmp_158_fu_2357_p1;
wire [31:0] tmp_161_fu_2361_p1;
wire [31:0] tmp_164_fu_2365_p1;
wire [31:0] tmp_167_fu_2369_p1;
reg [31:0] tmp_19_4_reg_5694;
reg [31:0] tmp_19_4_1_reg_5699;
reg [31:0] tmp_19_4_2_reg_5704;
reg [31:0] tmp_19_4_3_reg_5709;
reg [31:0] tmp_19_4_4_reg_5714;
reg [31:0] tmp_19_4_5_reg_5719;
reg [31:0] tmp_19_4_6_reg_5724;
reg [31:0] tmp_19_4_7_reg_5729;
reg [31:0] tmp_19_4_8_reg_5734;
reg [31:0] tmp_19_4_9_reg_5739;
reg [31:0] tmp_19_4_s_reg_5744;
reg [31:0] tmp_19_4_10_reg_5749;
reg [31:0] tmp_19_4_11_reg_5754;
reg [31:0] tmp_19_5_reg_5759;
reg [31:0] tmp_19_5_1_reg_5764;
reg [31:0] tmp_19_5_2_reg_5769;
reg [31:0] tmp_19_5_3_reg_5774;
reg [31:0] tmp_19_5_4_reg_5779;
reg [31:0] tmp_19_5_5_reg_5784;
reg [31:0] tmp_19_5_6_reg_5789;
reg [31:0] tmp_19_5_7_reg_5794;
reg [31:0] tmp_19_5_8_reg_5799;
reg [31:0] tmp_19_5_9_reg_5804;
reg [31:0] tmp_19_5_s_reg_5809;
reg [31:0] tmp_19_5_10_reg_5814;
reg [31:0] tmp_19_5_11_reg_5819;
reg [31:0] tmp_19_3_0_1_reg_5824;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824;
reg [31:0] tmp_19_3_1_1_reg_5829;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829;
reg [31:0] tmp_19_3_2_1_reg_5834;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834;
reg [31:0] tmp_19_3_3_1_reg_5839;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839;
reg [31:0] tmp_19_3_4_1_reg_5844;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844;
reg [31:0] tmp_19_3_5_1_reg_5849;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849;
reg [31:0] tmp_19_3_6_1_reg_5854;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854;
reg [31:0] tmp_19_3_7_1_reg_5859;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859;
reg [31:0] tmp_19_3_8_1_reg_5864;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864;
reg [31:0] tmp_19_3_9_1_reg_5869;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869;
reg [31:0] tmp_19_3_10_1_reg_5874;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874;
reg [31:0] tmp_19_3_11_1_reg_5879;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879;
reg [31:0] tmp_19_3_12_1_reg_5884;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884;
wire [31:0] tmp_171_fu_2373_p1;
wire [31:0] tmp_174_fu_2377_p1;
wire [31:0] tmp_177_fu_2381_p1;
wire [31:0] tmp_180_fu_2385_p1;
wire [31:0] tmp_183_fu_2389_p1;
wire [31:0] tmp_186_fu_2393_p1;
wire [31:0] tmp_189_fu_2397_p1;
wire [31:0] tmp_192_fu_2401_p1;
wire [31:0] tmp_195_fu_2405_p1;
wire [31:0] tmp_198_fu_2409_p1;
wire [31:0] tmp_201_fu_2413_p1;
wire [31:0] tmp_204_fu_2417_p1;
wire [31:0] tmp_207_fu_2421_p1;
wire [31:0] tmp_211_fu_2425_p1;
wire [31:0] tmp_214_fu_2429_p1;
wire [31:0] tmp_217_fu_2433_p1;
wire [31:0] tmp_220_fu_2437_p1;
wire [31:0] tmp_223_fu_2441_p1;
wire [31:0] tmp_226_fu_2445_p1;
wire [31:0] tmp_229_fu_2449_p1;
wire [31:0] tmp_232_fu_2453_p1;
wire [31:0] tmp_235_fu_2457_p1;
wire [31:0] tmp_238_fu_2461_p1;
wire [31:0] tmp_241_fu_2465_p1;
wire [31:0] tmp_244_fu_2469_p1;
wire [31:0] tmp_247_fu_2473_p1;
reg [31:0] tmp_19_6_reg_6019;
reg [31:0] tmp_19_6_1_reg_6024;
reg [31:0] tmp_19_6_2_reg_6029;
reg [31:0] tmp_19_6_3_reg_6034;
reg [31:0] tmp_19_6_4_reg_6039;
reg [31:0] tmp_19_6_5_reg_6044;
reg [31:0] tmp_19_6_6_reg_6049;
reg [31:0] tmp_19_6_7_reg_6054;
reg [31:0] tmp_19_6_8_reg_6059;
reg [31:0] tmp_19_6_9_reg_6064;
reg [31:0] tmp_19_6_s_reg_6069;
reg [31:0] tmp_19_6_10_reg_6074;
reg [31:0] tmp_19_6_11_reg_6079;
reg [31:0] tmp_19_7_reg_6084;
reg [31:0] tmp_19_7_1_reg_6089;
reg [31:0] tmp_19_7_2_reg_6094;
reg [31:0] tmp_19_7_3_reg_6099;
reg [31:0] tmp_19_7_4_reg_6104;
reg [31:0] tmp_19_7_5_reg_6109;
reg [31:0] tmp_19_7_6_reg_6114;
reg [31:0] tmp_19_7_7_reg_6119;
reg [31:0] tmp_19_7_8_reg_6124;
reg [31:0] tmp_19_7_9_reg_6129;
reg [31:0] tmp_19_7_s_reg_6134;
reg [31:0] tmp_19_7_10_reg_6139;
reg [31:0] tmp_19_7_11_reg_6144;
reg [31:0] tmp_19_4_0_1_reg_6149;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149;
reg [31:0] tmp_19_4_1_1_reg_6154;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154;
reg [31:0] tmp_19_4_2_1_reg_6159;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159;
reg [31:0] tmp_19_4_3_1_reg_6164;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164;
reg [31:0] tmp_19_4_4_1_reg_6169;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169;
reg [31:0] tmp_19_4_5_1_reg_6174;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174;
reg [31:0] tmp_19_4_6_1_reg_6179;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179;
reg [31:0] tmp_19_4_7_1_reg_6184;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184;
reg [31:0] tmp_19_4_8_1_reg_6189;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189;
reg [31:0] tmp_19_4_9_1_reg_6194;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194;
reg [31:0] tmp_19_4_10_1_reg_6199;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199;
reg [31:0] tmp_19_4_11_1_reg_6204;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204;
reg [31:0] tmp_19_4_12_1_reg_6209;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209;
reg [31:0] tmp_19_5_0_1_reg_6214;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214;
reg [31:0] tmp_19_5_1_1_reg_6219;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219;
reg [31:0] tmp_19_5_2_1_reg_6224;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224;
reg [31:0] tmp_19_5_3_1_reg_6229;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229;
reg [31:0] tmp_19_5_4_1_reg_6234;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234;
reg [31:0] tmp_19_5_5_1_reg_6239;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239;
reg [31:0] tmp_19_5_6_1_reg_6244;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244;
reg [31:0] tmp_19_5_7_1_reg_6249;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249;
reg [31:0] tmp_19_5_8_1_reg_6254;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254;
reg [31:0] tmp_19_5_9_1_reg_6259;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259;
reg [31:0] tmp_19_5_10_1_reg_6264;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264;
reg [31:0] tmp_19_5_11_1_reg_6269;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269;
reg [31:0] tmp_19_5_12_1_reg_6274;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274;
wire [31:0] tmp_251_fu_2477_p1;
reg [31:0] tmp_19_6_0_1_reg_6284;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284;
wire [31:0] tmp_254_fu_2481_p1;
reg [31:0] tmp_19_6_1_1_reg_6294;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294;
wire [31:0] tmp_257_fu_2485_p1;
reg [31:0] tmp_19_6_2_1_reg_6304;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304;
wire [31:0] tmp_260_fu_2489_p1;
reg [31:0] tmp_19_6_3_1_reg_6314;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314;
wire [31:0] tmp_263_fu_2493_p1;
reg [31:0] tmp_19_6_4_1_reg_6324;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324;
wire [31:0] tmp_266_fu_2497_p1;
reg [31:0] tmp_19_6_5_1_reg_6334;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334;
wire [31:0] tmp_269_fu_2501_p1;
reg [31:0] tmp_19_6_6_1_reg_6344;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344;
wire [31:0] tmp_272_fu_2505_p1;
reg [31:0] tmp_19_6_7_1_reg_6354;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354;
wire [31:0] tmp_275_fu_2509_p1;
reg [31:0] tmp_19_6_8_1_reg_6364;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364;
wire [31:0] tmp_278_fu_2513_p1;
reg [31:0] tmp_19_6_9_1_reg_6374;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374;
wire [31:0] tmp_281_fu_2517_p1;
reg [31:0] tmp_19_6_10_1_reg_6384;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384;
wire [31:0] tmp_284_fu_2521_p1;
reg [31:0] tmp_19_6_11_1_reg_6394;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394;
wire [31:0] tmp_287_fu_2525_p1;
reg [31:0] tmp_19_6_12_1_reg_6404;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404;
wire [31:0] tmp_291_fu_2529_p1;
wire [31:0] tmp_294_fu_2533_p1;
wire [31:0] tmp_297_fu_2537_p1;
wire [31:0] tmp_300_fu_2541_p1;
wire [31:0] tmp_303_fu_2545_p1;
wire [31:0] tmp_306_fu_2549_p1;
wire [31:0] tmp_309_fu_2553_p1;
wire [31:0] tmp_312_fu_2557_p1;
wire [31:0] tmp_315_fu_2561_p1;
wire [31:0] tmp_318_fu_2565_p1;
wire [31:0] tmp_321_fu_2569_p1;
wire [31:0] tmp_324_fu_2573_p1;
wire [31:0] tmp_327_fu_2577_p1;
reg [31:0] tmp_19_0_0_2_reg_6474;
reg [31:0] ap_reg_pp0_iter3_tmp_19_0_0_2_reg_6474;
reg [31:0] ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474;
reg [31:0] tmp_19_0_1_2_reg_6479;
reg [31:0] ap_reg_pp0_iter3_tmp_19_0_1_2_reg_6479;
reg [31:0] ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479;
reg [31:0] tmp_19_0_2_2_reg_6484;
reg [31:0] ap_reg_pp0_iter3_tmp_19_0_2_2_reg_6484;
reg [31:0] ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484;
reg [31:0] tmp_19_0_3_2_reg_6489;
reg [31:0] ap_reg_pp0_iter3_tmp_19_0_3_2_reg_6489;
reg [31:0] ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489;
reg [31:0] tmp_19_0_4_2_reg_6494;
reg [31:0] ap_reg_pp0_iter3_tmp_19_0_4_2_reg_6494;
reg [31:0] ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494;
reg [31:0] tmp_19_0_5_2_reg_6499;
reg [31:0] ap_reg_pp0_iter3_tmp_19_0_5_2_reg_6499;
reg [31:0] ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499;
reg [31:0] tmp_19_0_6_2_reg_6504;
reg [31:0] ap_reg_pp0_iter3_tmp_19_0_6_2_reg_6504;
reg [31:0] ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504;
reg [31:0] tmp_19_0_7_2_reg_6509;
reg [31:0] ap_reg_pp0_iter3_tmp_19_0_7_2_reg_6509;
reg [31:0] ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509;
reg [31:0] tmp_19_0_8_2_reg_6514;
reg [31:0] ap_reg_pp0_iter3_tmp_19_0_8_2_reg_6514;
reg [31:0] ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514;
reg [31:0] tmp_19_0_9_2_reg_6519;
reg [31:0] ap_reg_pp0_iter3_tmp_19_0_9_2_reg_6519;
reg [31:0] ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519;
reg [31:0] tmp_19_0_10_2_reg_6524;
reg [31:0] ap_reg_pp0_iter3_tmp_19_0_10_2_reg_6524;
reg [31:0] ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524;
reg [31:0] tmp_19_0_11_2_reg_6529;
reg [31:0] ap_reg_pp0_iter3_tmp_19_0_11_2_reg_6529;
reg [31:0] ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529;
reg [31:0] tmp_19_0_12_2_reg_6534;
reg [31:0] ap_reg_pp0_iter3_tmp_19_0_12_2_reg_6534;
reg [31:0] ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534;
reg [31:0] tmp_19_1_0_2_reg_6539;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_0_2_reg_6539;
reg [31:0] ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539;
reg [31:0] tmp_19_1_1_2_reg_6544;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_1_2_reg_6544;
reg [31:0] ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544;
reg [31:0] tmp_19_1_2_2_reg_6549;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_2_2_reg_6549;
reg [31:0] ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549;
reg [31:0] tmp_19_1_3_2_reg_6554;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_3_2_reg_6554;
reg [31:0] ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554;
reg [31:0] tmp_19_1_4_2_reg_6559;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_4_2_reg_6559;
reg [31:0] ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559;
reg [31:0] tmp_19_1_5_2_reg_6564;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_5_2_reg_6564;
reg [31:0] ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564;
reg [31:0] tmp_19_1_6_2_reg_6569;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_6_2_reg_6569;
reg [31:0] ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569;
reg [31:0] tmp_19_1_7_2_reg_6574;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_7_2_reg_6574;
reg [31:0] ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574;
reg [31:0] tmp_19_1_8_2_reg_6579;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_8_2_reg_6579;
reg [31:0] ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579;
reg [31:0] tmp_19_1_9_2_reg_6584;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_9_2_reg_6584;
reg [31:0] ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584;
reg [31:0] tmp_19_1_10_2_reg_6589;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_10_2_reg_6589;
reg [31:0] ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589;
reg [31:0] tmp_19_1_11_2_reg_6594;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_11_2_reg_6594;
reg [31:0] ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594;
reg [31:0] tmp_19_1_12_2_reg_6599;
reg [31:0] ap_reg_pp0_iter3_tmp_19_1_12_2_reg_6599;
reg [31:0] ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599;
reg [31:0] tmp_19_7_0_1_reg_6604;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604;
reg [31:0] tmp_19_7_1_1_reg_6609;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609;
reg [31:0] tmp_19_7_2_1_reg_6614;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614;
reg [31:0] tmp_19_7_3_1_reg_6619;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619;
reg [31:0] tmp_19_7_4_1_reg_6624;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624;
reg [31:0] tmp_19_7_5_1_reg_6629;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629;
reg [31:0] tmp_19_7_6_1_reg_6634;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634;
reg [31:0] tmp_19_7_7_1_reg_6639;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639;
reg [31:0] tmp_19_7_8_1_reg_6644;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644;
reg [31:0] tmp_19_7_9_1_reg_6649;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649;
reg [31:0] tmp_19_7_10_1_reg_6654;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654;
reg [31:0] tmp_19_7_11_1_reg_6659;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659;
reg [31:0] tmp_19_7_12_1_reg_6664;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664;
reg [31:0] tmp_19_2_0_2_reg_6669;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_0_2_reg_6669;
reg [31:0] ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669;
reg [31:0] tmp_19_2_1_2_reg_6674;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_1_2_reg_6674;
reg [31:0] ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674;
reg [31:0] tmp_19_2_2_2_reg_6679;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_2_2_reg_6679;
reg [31:0] ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679;
reg [31:0] tmp_19_2_3_2_reg_6684;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_3_2_reg_6684;
reg [31:0] ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684;
reg [31:0] tmp_19_2_4_2_reg_6689;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_4_2_reg_6689;
reg [31:0] ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689;
reg [31:0] tmp_19_2_5_2_reg_6694;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_5_2_reg_6694;
reg [31:0] ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694;
reg [31:0] tmp_19_2_6_2_reg_6699;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_6_2_reg_6699;
reg [31:0] ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699;
reg [31:0] tmp_19_2_7_2_reg_6704;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_7_2_reg_6704;
reg [31:0] ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704;
reg [31:0] tmp_19_2_8_2_reg_6709;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_8_2_reg_6709;
reg [31:0] ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709;
reg [31:0] tmp_19_2_9_2_reg_6714;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_9_2_reg_6714;
reg [31:0] ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714;
reg [31:0] tmp_19_2_10_2_reg_6719;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_10_2_reg_6719;
reg [31:0] ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719;
reg [31:0] tmp_19_2_11_2_reg_6724;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_11_2_reg_6724;
reg [31:0] ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724;
reg [31:0] tmp_19_2_12_2_reg_6729;
reg [31:0] ap_reg_pp0_iter3_tmp_19_2_12_2_reg_6729;
reg [31:0] ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729;
reg [31:0] tmp_19_3_0_2_reg_6734;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_0_2_reg_6734;
reg [31:0] ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734;
reg [31:0] tmp_19_3_1_2_reg_6739;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_1_2_reg_6739;
reg [31:0] ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739;
reg [31:0] tmp_19_3_2_2_reg_6744;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_2_2_reg_6744;
reg [31:0] ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744;
reg [31:0] tmp_19_3_3_2_reg_6749;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_3_2_reg_6749;
reg [31:0] ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749;
reg [31:0] tmp_19_3_4_2_reg_6754;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_4_2_reg_6754;
reg [31:0] ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754;
reg [31:0] tmp_19_3_5_2_reg_6759;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_5_2_reg_6759;
reg [31:0] ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759;
reg [31:0] tmp_19_3_6_2_reg_6764;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_6_2_reg_6764;
reg [31:0] ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764;
reg [31:0] tmp_19_3_7_2_reg_6769;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_7_2_reg_6769;
reg [31:0] ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769;
reg [31:0] tmp_19_3_8_2_reg_6774;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_8_2_reg_6774;
reg [31:0] ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774;
reg [31:0] tmp_19_3_9_2_reg_6779;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_9_2_reg_6779;
reg [31:0] ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779;
reg [31:0] tmp_19_3_10_2_reg_6784;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_10_2_reg_6784;
reg [31:0] ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784;
reg [31:0] tmp_19_3_11_2_reg_6789;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_11_2_reg_6789;
reg [31:0] ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789;
reg [31:0] tmp_19_3_12_2_reg_6794;
reg [31:0] ap_reg_pp0_iter3_tmp_19_3_12_2_reg_6794;
reg [31:0] ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794;
reg [31:0] tmp_19_4_0_2_reg_6799;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_0_2_reg_6799;
reg [31:0] ap_reg_pp0_iter4_tmp_19_4_0_2_reg_6799;
reg [31:0] ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799;
reg [31:0] tmp_19_4_1_2_reg_6804;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_1_2_reg_6804;
reg [31:0] ap_reg_pp0_iter4_tmp_19_4_1_2_reg_6804;
reg [31:0] ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804;
reg [31:0] tmp_19_4_2_2_reg_6809;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_2_2_reg_6809;
reg [31:0] ap_reg_pp0_iter4_tmp_19_4_2_2_reg_6809;
reg [31:0] ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809;
reg [31:0] tmp_19_4_3_2_reg_6814;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_3_2_reg_6814;
reg [31:0] ap_reg_pp0_iter4_tmp_19_4_3_2_reg_6814;
reg [31:0] ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814;
reg [31:0] tmp_19_4_4_2_reg_6819;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_4_2_reg_6819;
reg [31:0] ap_reg_pp0_iter4_tmp_19_4_4_2_reg_6819;
reg [31:0] ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819;
reg [31:0] tmp_19_4_5_2_reg_6824;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_5_2_reg_6824;
reg [31:0] ap_reg_pp0_iter4_tmp_19_4_5_2_reg_6824;
reg [31:0] ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824;
reg [31:0] tmp_19_4_6_2_reg_6829;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_6_2_reg_6829;
reg [31:0] ap_reg_pp0_iter4_tmp_19_4_6_2_reg_6829;
reg [31:0] ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829;
reg [31:0] tmp_19_4_7_2_reg_6834;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_7_2_reg_6834;
reg [31:0] ap_reg_pp0_iter4_tmp_19_4_7_2_reg_6834;
reg [31:0] ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834;
reg [31:0] tmp_19_4_8_2_reg_6839;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_8_2_reg_6839;
reg [31:0] ap_reg_pp0_iter4_tmp_19_4_8_2_reg_6839;
reg [31:0] ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839;
reg [31:0] tmp_19_4_9_2_reg_6844;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_9_2_reg_6844;
reg [31:0] ap_reg_pp0_iter4_tmp_19_4_9_2_reg_6844;
reg [31:0] ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844;
reg [31:0] tmp_19_4_10_2_reg_6849;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_10_2_reg_6849;
reg [31:0] ap_reg_pp0_iter4_tmp_19_4_10_2_reg_6849;
reg [31:0] ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849;
reg [31:0] tmp_19_4_11_2_reg_6854;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_11_2_reg_6854;
reg [31:0] ap_reg_pp0_iter4_tmp_19_4_11_2_reg_6854;
reg [31:0] ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854;
reg [31:0] tmp_19_4_12_2_reg_6859;
reg [31:0] ap_reg_pp0_iter3_tmp_19_4_12_2_reg_6859;
reg [31:0] ap_reg_pp0_iter4_tmp_19_4_12_2_reg_6859;
reg [31:0] ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859;
reg [31:0] tmp_19_5_0_2_reg_6864;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_0_2_reg_6864;
reg [31:0] ap_reg_pp0_iter4_tmp_19_5_0_2_reg_6864;
reg [31:0] ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864;
reg [31:0] tmp_19_5_1_2_reg_6869;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_1_2_reg_6869;
reg [31:0] ap_reg_pp0_iter4_tmp_19_5_1_2_reg_6869;
reg [31:0] ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869;
reg [31:0] tmp_19_5_2_2_reg_6874;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_2_2_reg_6874;
reg [31:0] ap_reg_pp0_iter4_tmp_19_5_2_2_reg_6874;
reg [31:0] ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874;
reg [31:0] tmp_19_5_3_2_reg_6879;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_3_2_reg_6879;
reg [31:0] ap_reg_pp0_iter4_tmp_19_5_3_2_reg_6879;
reg [31:0] ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879;
reg [31:0] tmp_19_5_4_2_reg_6884;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_4_2_reg_6884;
reg [31:0] ap_reg_pp0_iter4_tmp_19_5_4_2_reg_6884;
reg [31:0] ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884;
reg [31:0] tmp_19_5_5_2_reg_6889;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_5_2_reg_6889;
reg [31:0] ap_reg_pp0_iter4_tmp_19_5_5_2_reg_6889;
reg [31:0] ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889;
reg [31:0] tmp_19_5_6_2_reg_6894;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_6_2_reg_6894;
reg [31:0] ap_reg_pp0_iter4_tmp_19_5_6_2_reg_6894;
reg [31:0] ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894;
reg [31:0] tmp_19_5_7_2_reg_6899;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_7_2_reg_6899;
reg [31:0] ap_reg_pp0_iter4_tmp_19_5_7_2_reg_6899;
reg [31:0] ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899;
reg [31:0] tmp_19_5_8_2_reg_6904;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_8_2_reg_6904;
reg [31:0] ap_reg_pp0_iter4_tmp_19_5_8_2_reg_6904;
reg [31:0] ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904;
reg [31:0] tmp_19_5_9_2_reg_6909;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_9_2_reg_6909;
reg [31:0] ap_reg_pp0_iter4_tmp_19_5_9_2_reg_6909;
reg [31:0] ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909;
reg [31:0] tmp_19_5_10_2_reg_6914;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_10_2_reg_6914;
reg [31:0] ap_reg_pp0_iter4_tmp_19_5_10_2_reg_6914;
reg [31:0] ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914;
reg [31:0] tmp_19_5_11_2_reg_6919;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_11_2_reg_6919;
reg [31:0] ap_reg_pp0_iter4_tmp_19_5_11_2_reg_6919;
reg [31:0] ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919;
reg [31:0] tmp_19_5_12_2_reg_6924;
reg [31:0] ap_reg_pp0_iter3_tmp_19_5_12_2_reg_6924;
reg [31:0] ap_reg_pp0_iter4_tmp_19_5_12_2_reg_6924;
reg [31:0] ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924;
reg [31:0] tmp_19_6_0_2_reg_6929;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_0_2_reg_6929;
reg [31:0] ap_reg_pp0_iter4_tmp_19_6_0_2_reg_6929;
reg [31:0] ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929;
reg [31:0] tmp_19_6_1_2_reg_6934;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_1_2_reg_6934;
reg [31:0] ap_reg_pp0_iter4_tmp_19_6_1_2_reg_6934;
reg [31:0] ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934;
reg [31:0] tmp_19_6_2_2_reg_6939;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_2_2_reg_6939;
reg [31:0] ap_reg_pp0_iter4_tmp_19_6_2_2_reg_6939;
reg [31:0] ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939;
reg [31:0] tmp_19_6_3_2_reg_6944;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_3_2_reg_6944;
reg [31:0] ap_reg_pp0_iter4_tmp_19_6_3_2_reg_6944;
reg [31:0] ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944;
reg [31:0] tmp_19_6_4_2_reg_6949;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_4_2_reg_6949;
reg [31:0] ap_reg_pp0_iter4_tmp_19_6_4_2_reg_6949;
reg [31:0] ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949;
reg [31:0] tmp_19_6_5_2_reg_6954;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_5_2_reg_6954;
reg [31:0] ap_reg_pp0_iter4_tmp_19_6_5_2_reg_6954;
reg [31:0] ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954;
reg [31:0] tmp_19_6_6_2_reg_6959;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_6_2_reg_6959;
reg [31:0] ap_reg_pp0_iter4_tmp_19_6_6_2_reg_6959;
reg [31:0] ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959;
reg [31:0] tmp_19_6_7_2_reg_6964;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_7_2_reg_6964;
reg [31:0] ap_reg_pp0_iter4_tmp_19_6_7_2_reg_6964;
reg [31:0] ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964;
reg [31:0] tmp_19_6_8_2_reg_6969;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_8_2_reg_6969;
reg [31:0] ap_reg_pp0_iter4_tmp_19_6_8_2_reg_6969;
reg [31:0] ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969;
reg [31:0] tmp_19_6_9_2_reg_6974;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_9_2_reg_6974;
reg [31:0] ap_reg_pp0_iter4_tmp_19_6_9_2_reg_6974;
reg [31:0] ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974;
reg [31:0] tmp_19_6_10_2_reg_6979;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_10_2_reg_6979;
reg [31:0] ap_reg_pp0_iter4_tmp_19_6_10_2_reg_6979;
reg [31:0] ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979;
reg [31:0] tmp_19_6_11_2_reg_6984;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_11_2_reg_6984;
reg [31:0] ap_reg_pp0_iter4_tmp_19_6_11_2_reg_6984;
reg [31:0] ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984;
reg [31:0] tmp_19_6_12_2_reg_6989;
reg [31:0] ap_reg_pp0_iter3_tmp_19_6_12_2_reg_6989;
reg [31:0] ap_reg_pp0_iter4_tmp_19_6_12_2_reg_6989;
reg [31:0] ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989;
reg [31:0] tmp_19_7_0_2_reg_6994;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_0_2_reg_6994;
reg [31:0] ap_reg_pp0_iter4_tmp_19_7_0_2_reg_6994;
reg [31:0] ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994;
reg [31:0] tmp_19_7_1_2_reg_6999;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_1_2_reg_6999;
reg [31:0] ap_reg_pp0_iter4_tmp_19_7_1_2_reg_6999;
reg [31:0] ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999;
reg [31:0] tmp_19_7_2_2_reg_7004;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_2_2_reg_7004;
reg [31:0] ap_reg_pp0_iter4_tmp_19_7_2_2_reg_7004;
reg [31:0] ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004;
reg [31:0] tmp_19_7_3_2_reg_7009;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_3_2_reg_7009;
reg [31:0] ap_reg_pp0_iter4_tmp_19_7_3_2_reg_7009;
reg [31:0] ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009;
reg [31:0] tmp_19_7_4_2_reg_7014;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_4_2_reg_7014;
reg [31:0] ap_reg_pp0_iter4_tmp_19_7_4_2_reg_7014;
reg [31:0] ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014;
reg [31:0] tmp_19_7_5_2_reg_7019;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_5_2_reg_7019;
reg [31:0] ap_reg_pp0_iter4_tmp_19_7_5_2_reg_7019;
reg [31:0] ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019;
reg [31:0] tmp_19_7_6_2_reg_7024;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_6_2_reg_7024;
reg [31:0] ap_reg_pp0_iter4_tmp_19_7_6_2_reg_7024;
reg [31:0] ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024;
reg [31:0] tmp_19_7_7_2_reg_7029;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_7_2_reg_7029;
reg [31:0] ap_reg_pp0_iter4_tmp_19_7_7_2_reg_7029;
reg [31:0] ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029;
reg [31:0] tmp_19_7_8_2_reg_7034;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_8_2_reg_7034;
reg [31:0] ap_reg_pp0_iter4_tmp_19_7_8_2_reg_7034;
reg [31:0] ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034;
reg [31:0] tmp_19_7_9_2_reg_7039;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_9_2_reg_7039;
reg [31:0] ap_reg_pp0_iter4_tmp_19_7_9_2_reg_7039;
reg [31:0] ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039;
reg [31:0] tmp_19_7_10_2_reg_7044;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_10_2_reg_7044;
reg [31:0] ap_reg_pp0_iter4_tmp_19_7_10_2_reg_7044;
reg [31:0] ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044;
reg [31:0] tmp_19_7_11_2_reg_7049;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_11_2_reg_7049;
reg [31:0] ap_reg_pp0_iter4_tmp_19_7_11_2_reg_7049;
reg [31:0] ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049;
reg [31:0] tmp_19_7_12_2_reg_7054;
reg [31:0] ap_reg_pp0_iter3_tmp_19_7_12_2_reg_7054;
reg [31:0] ap_reg_pp0_iter4_tmp_19_7_12_2_reg_7054;
reg [31:0] ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054;
wire [31:0] grp_fu_943_p2;
reg [31:0] tmp_351_reg_7059;
reg ap_enable_reg_pp0_iter3;
wire [31:0] grp_fu_947_p2;
reg [31:0] tmp_20_0_1_reg_7064;
wire [31:0] grp_fu_951_p2;
reg [31:0] tmp_20_0_2_reg_7069;
wire [31:0] grp_fu_955_p2;
reg [31:0] tmp_20_0_3_reg_7074;
wire [31:0] grp_fu_959_p2;
reg [31:0] tmp_20_0_4_reg_7079;
wire [31:0] grp_fu_963_p2;
reg [31:0] tmp_20_0_5_reg_7084;
wire [31:0] grp_fu_967_p2;
reg [31:0] tmp_20_0_6_reg_7089;
wire [31:0] grp_fu_971_p2;
reg [31:0] tmp_20_0_7_reg_7094;
wire [31:0] grp_fu_975_p2;
reg [31:0] tmp_20_0_8_reg_7099;
wire [31:0] grp_fu_979_p2;
reg [31:0] tmp_20_0_9_reg_7104;
wire [31:0] grp_fu_983_p2;
reg [31:0] tmp_20_0_s_reg_7109;
wire [31:0] grp_fu_987_p2;
reg [31:0] tmp_20_0_10_reg_7114;
wire [31:0] grp_fu_991_p2;
reg [31:0] tmp_20_0_11_reg_7119;
wire [31:0] grp_fu_995_p2;
reg [31:0] tmp_20_1_reg_7124;
wire [31:0] grp_fu_999_p2;
reg [31:0] tmp_20_1_1_reg_7129;
wire [31:0] grp_fu_1003_p2;
reg [31:0] tmp_20_1_2_reg_7134;
wire [31:0] grp_fu_1007_p2;
reg [31:0] tmp_20_1_3_reg_7139;
wire [31:0] grp_fu_1011_p2;
reg [31:0] tmp_20_1_4_reg_7144;
wire [31:0] grp_fu_1015_p2;
reg [31:0] tmp_20_1_5_reg_7149;
wire [31:0] grp_fu_1019_p2;
reg [31:0] tmp_20_1_6_reg_7154;
wire [31:0] grp_fu_1023_p2;
reg [31:0] tmp_20_1_7_reg_7159;
wire [31:0] grp_fu_1027_p2;
reg [31:0] tmp_20_1_8_reg_7164;
wire [31:0] grp_fu_1031_p2;
reg [31:0] tmp_20_1_9_reg_7169;
wire [31:0] grp_fu_1035_p2;
reg [31:0] tmp_20_1_s_reg_7174;
wire [31:0] grp_fu_1039_p2;
reg [31:0] tmp_20_1_10_reg_7179;
wire [31:0] grp_fu_1043_p2;
reg [31:0] tmp_20_1_11_reg_7184;
reg [31:0] tmp_20_2_reg_7189;
reg [31:0] tmp_20_2_1_reg_7194;
reg [31:0] tmp_20_2_2_reg_7199;
reg [31:0] tmp_20_2_3_reg_7204;
reg [31:0] tmp_20_2_4_reg_7209;
reg [31:0] tmp_20_2_5_reg_7214;
reg [31:0] tmp_20_2_6_reg_7219;
reg [31:0] tmp_20_2_7_reg_7224;
reg [31:0] tmp_20_2_8_reg_7229;
reg [31:0] tmp_20_2_9_reg_7234;
reg [31:0] tmp_20_2_s_reg_7239;
reg [31:0] tmp_20_2_10_reg_7244;
reg [31:0] tmp_20_2_11_reg_7249;
reg [31:0] tmp_20_3_reg_7254;
reg [31:0] tmp_20_3_1_reg_7259;
reg [31:0] tmp_20_3_2_reg_7264;
reg [31:0] tmp_20_3_3_reg_7269;
reg [31:0] tmp_20_3_4_reg_7274;
reg [31:0] tmp_20_3_5_reg_7279;
reg [31:0] tmp_20_3_6_reg_7284;
reg [31:0] tmp_20_3_7_reg_7289;
reg [31:0] tmp_20_3_8_reg_7294;
reg [31:0] tmp_20_3_9_reg_7299;
reg [31:0] tmp_20_3_s_reg_7304;
reg [31:0] tmp_20_3_10_reg_7309;
reg [31:0] tmp_20_3_11_reg_7314;
reg [31:0] tmp_20_4_reg_7319;
reg [31:0] tmp_20_4_1_reg_7324;
reg [31:0] tmp_20_4_2_reg_7329;
reg [31:0] tmp_20_4_3_reg_7334;
reg [31:0] tmp_20_4_4_reg_7339;
reg [31:0] tmp_20_4_5_reg_7344;
reg [31:0] tmp_20_4_6_reg_7349;
reg [31:0] tmp_20_4_7_reg_7354;
reg [31:0] tmp_20_4_8_reg_7359;
reg [31:0] tmp_20_4_9_reg_7364;
reg [31:0] tmp_20_4_s_reg_7369;
reg [31:0] tmp_20_4_10_reg_7374;
reg [31:0] tmp_20_4_11_reg_7379;
reg [31:0] tmp_20_5_reg_7384;
reg [31:0] tmp_20_5_1_reg_7389;
reg [31:0] tmp_20_5_2_reg_7394;
reg [31:0] tmp_20_5_3_reg_7399;
reg [31:0] tmp_20_5_4_reg_7404;
reg [31:0] tmp_20_5_5_reg_7409;
reg [31:0] tmp_20_5_6_reg_7414;
reg [31:0] tmp_20_5_7_reg_7419;
reg [31:0] tmp_20_5_8_reg_7424;
reg [31:0] tmp_20_5_9_reg_7429;
reg [31:0] tmp_20_5_s_reg_7434;
reg [31:0] tmp_20_5_10_reg_7439;
reg [31:0] tmp_20_5_11_reg_7444;
reg [31:0] tmp_20_6_reg_7449;
reg ap_enable_reg_pp0_iter4;
reg [31:0] tmp_20_6_1_reg_7454;
reg [31:0] tmp_20_6_2_reg_7459;
reg [31:0] tmp_20_6_3_reg_7464;
reg [31:0] tmp_20_6_4_reg_7469;
reg [31:0] tmp_20_6_5_reg_7474;
reg [31:0] tmp_20_6_6_reg_7479;
reg [31:0] tmp_20_6_7_reg_7484;
reg [31:0] tmp_20_6_8_reg_7489;
reg [31:0] tmp_20_6_9_reg_7494;
reg [31:0] tmp_20_6_s_reg_7499;
reg [31:0] tmp_20_6_10_reg_7504;
reg [31:0] tmp_20_6_11_reg_7509;
reg [31:0] tmp_20_7_reg_7514;
reg [31:0] tmp_20_7_1_reg_7519;
reg [31:0] tmp_20_7_2_reg_7524;
reg [31:0] tmp_20_7_3_reg_7529;
reg [31:0] tmp_20_7_4_reg_7534;
reg [31:0] tmp_20_7_5_reg_7539;
reg [31:0] tmp_20_7_6_reg_7544;
reg [31:0] tmp_20_7_7_reg_7549;
reg [31:0] tmp_20_7_8_reg_7554;
reg [31:0] tmp_20_7_9_reg_7559;
reg [31:0] tmp_20_7_s_reg_7564;
reg [31:0] tmp_20_7_10_reg_7569;
reg [31:0] tmp_20_7_11_reg_7574;
reg [31:0] tmp_20_0_0_1_reg_7579;
reg ap_enable_reg_pp0_iter5;
reg [31:0] tmp_20_0_1_1_reg_7584;
reg [31:0] tmp_20_0_2_1_reg_7589;
reg [31:0] tmp_20_0_3_1_reg_7594;
reg [31:0] tmp_20_0_4_1_reg_7599;
reg [31:0] tmp_20_0_5_1_reg_7604;
reg [31:0] tmp_20_0_6_1_reg_7609;
reg [31:0] tmp_20_0_7_1_reg_7614;
reg [31:0] tmp_20_0_8_1_reg_7619;
reg [31:0] tmp_20_0_9_1_reg_7624;
reg [31:0] tmp_20_0_10_1_reg_7629;
reg [31:0] tmp_20_0_11_1_reg_7634;
reg [31:0] tmp_20_0_12_1_reg_7639;
reg [31:0] tmp_20_1_0_1_reg_7644;
reg [31:0] tmp_20_1_1_1_reg_7649;
reg [31:0] tmp_20_1_2_1_reg_7654;
reg [31:0] tmp_20_1_3_1_reg_7659;
reg [31:0] tmp_20_1_4_1_reg_7664;
reg [31:0] tmp_20_1_5_1_reg_7669;
reg [31:0] tmp_20_1_6_1_reg_7674;
reg [31:0] tmp_20_1_7_1_reg_7679;
reg [31:0] tmp_20_1_8_1_reg_7684;
reg [31:0] tmp_20_1_9_1_reg_7689;
reg [31:0] tmp_20_1_10_1_reg_7694;
reg [31:0] tmp_20_1_11_1_reg_7699;
reg [31:0] tmp_20_1_12_1_reg_7704;
reg [31:0] tmp_20_2_0_1_reg_7709;
reg [31:0] tmp_20_2_1_1_reg_7714;
reg [31:0] tmp_20_2_2_1_reg_7719;
reg [31:0] tmp_20_2_3_1_reg_7724;
reg [31:0] tmp_20_2_4_1_reg_7729;
reg [31:0] tmp_20_2_5_1_reg_7734;
reg [31:0] tmp_20_2_6_1_reg_7739;
reg [31:0] tmp_20_2_7_1_reg_7744;
reg [31:0] tmp_20_2_8_1_reg_7749;
reg [31:0] tmp_20_2_9_1_reg_7754;
reg [31:0] tmp_20_2_10_1_reg_7759;
reg [31:0] tmp_20_2_11_1_reg_7764;
reg [31:0] tmp_20_2_12_1_reg_7769;
reg [31:0] tmp_20_3_0_1_reg_7774;
reg [31:0] tmp_20_3_1_1_reg_7779;
reg [31:0] tmp_20_3_2_1_reg_7784;
reg [31:0] tmp_20_3_3_1_reg_7789;
reg [31:0] tmp_20_3_4_1_reg_7794;
reg [31:0] tmp_20_3_5_1_reg_7799;
reg [31:0] tmp_20_3_6_1_reg_7804;
reg [31:0] tmp_20_3_7_1_reg_7809;
reg [31:0] tmp_20_3_8_1_reg_7814;
reg [31:0] tmp_20_3_9_1_reg_7819;
reg [31:0] tmp_20_3_10_1_reg_7824;
reg [31:0] tmp_20_3_11_1_reg_7829;
reg [31:0] tmp_20_3_12_1_reg_7834;
wire [31:0] grp_fu_1047_p2;
reg [31:0] tmp_20_4_0_1_reg_7839;
wire [31:0] grp_fu_1051_p2;
reg [31:0] tmp_20_4_1_1_reg_7844;
wire [31:0] grp_fu_1055_p2;
reg [31:0] tmp_20_4_2_1_reg_7849;
wire [31:0] grp_fu_1059_p2;
reg [31:0] tmp_20_4_3_1_reg_7854;
wire [31:0] grp_fu_1063_p2;
reg [31:0] tmp_20_4_4_1_reg_7859;
wire [31:0] grp_fu_1067_p2;
reg [31:0] tmp_20_4_5_1_reg_7864;
wire [31:0] grp_fu_1071_p2;
reg [31:0] tmp_20_4_6_1_reg_7869;
wire [31:0] grp_fu_1075_p2;
reg [31:0] tmp_20_4_7_1_reg_7874;
wire [31:0] grp_fu_1079_p2;
reg [31:0] tmp_20_4_8_1_reg_7879;
wire [31:0] grp_fu_1083_p2;
reg [31:0] tmp_20_4_9_1_reg_7884;
wire [31:0] grp_fu_1087_p2;
reg [31:0] tmp_20_4_10_1_reg_7889;
wire [31:0] grp_fu_1091_p2;
reg [31:0] tmp_20_4_11_1_reg_7894;
wire [31:0] grp_fu_1095_p2;
reg [31:0] tmp_20_4_12_1_reg_7899;
reg [31:0] tmp_20_5_0_1_reg_7904;
reg [31:0] tmp_20_5_1_1_reg_7909;
reg [31:0] tmp_20_5_2_1_reg_7914;
reg [31:0] tmp_20_5_3_1_reg_7919;
reg [31:0] tmp_20_5_4_1_reg_7924;
reg [31:0] tmp_20_5_5_1_reg_7929;
reg [31:0] tmp_20_5_6_1_reg_7934;
reg [31:0] tmp_20_5_7_1_reg_7939;
reg [31:0] tmp_20_5_8_1_reg_7944;
reg [31:0] tmp_20_5_9_1_reg_7949;
reg [31:0] tmp_20_5_10_1_reg_7954;
reg [31:0] tmp_20_5_11_1_reg_7959;
reg [31:0] tmp_20_5_12_1_reg_7964;
reg [31:0] tmp_20_6_0_1_reg_7969;
reg [31:0] tmp_20_6_1_1_reg_7974;
reg [31:0] tmp_20_6_2_1_reg_7979;
reg [31:0] tmp_20_6_3_1_reg_7984;
reg [31:0] tmp_20_6_4_1_reg_7989;
reg [31:0] tmp_20_6_5_1_reg_7994;
reg [31:0] tmp_20_6_6_1_reg_7999;
reg [31:0] tmp_20_6_7_1_reg_8004;
reg [31:0] tmp_20_6_8_1_reg_8009;
reg [31:0] tmp_20_6_9_1_reg_8014;
reg [31:0] tmp_20_6_10_1_reg_8019;
reg [31:0] tmp_20_6_11_1_reg_8024;
reg [31:0] tmp_20_6_12_1_reg_8029;
reg [31:0] tmp_20_7_0_1_reg_8034;
reg ap_enable_reg_pp0_iter6;
reg [31:0] tmp_20_7_1_1_reg_8039;
reg [31:0] tmp_20_7_2_1_reg_8044;
reg [31:0] tmp_20_7_3_1_reg_8049;
reg [31:0] tmp_20_7_4_1_reg_8054;
reg [31:0] tmp_20_7_5_1_reg_8059;
reg [31:0] tmp_20_7_6_1_reg_8064;
reg [31:0] tmp_20_7_7_1_reg_8069;
reg [31:0] tmp_20_7_8_1_reg_8074;
reg [31:0] tmp_20_7_9_1_reg_8079;
reg [31:0] tmp_20_7_10_1_reg_8084;
reg [31:0] tmp_20_7_11_1_reg_8089;
reg [31:0] tmp_20_7_12_1_reg_8094;
reg [31:0] tmp_20_0_0_2_reg_8099;
reg ap_enable_reg_pp0_iter7;
reg [31:0] tmp_20_0_1_2_reg_8104;
reg [31:0] tmp_20_0_2_2_reg_8109;
reg [31:0] tmp_20_0_3_2_reg_8114;
reg [31:0] tmp_20_0_4_2_reg_8119;
reg [31:0] tmp_20_0_5_2_reg_8124;
reg [31:0] tmp_20_0_6_2_reg_8129;
reg [31:0] tmp_20_0_7_2_reg_8134;
reg [31:0] tmp_20_0_8_2_reg_8139;
reg [31:0] tmp_20_0_9_2_reg_8144;
reg [31:0] tmp_20_0_10_2_reg_8149;
reg [31:0] tmp_20_0_11_2_reg_8154;
reg [31:0] tmp_20_0_12_2_reg_8159;
reg [31:0] tmp_20_1_0_2_reg_8164;
reg [31:0] tmp_20_1_1_2_reg_8169;
reg [31:0] tmp_20_1_2_2_reg_8174;
reg [31:0] tmp_20_1_3_2_reg_8179;
reg [31:0] tmp_20_1_4_2_reg_8184;
reg [31:0] tmp_20_1_5_2_reg_8189;
reg [31:0] tmp_20_1_6_2_reg_8194;
reg [31:0] tmp_20_1_7_2_reg_8199;
reg [31:0] tmp_20_1_8_2_reg_8204;
reg [31:0] tmp_20_1_9_2_reg_8209;
reg [31:0] tmp_20_1_10_2_reg_8214;
reg [31:0] tmp_20_1_11_2_reg_8219;
reg [31:0] tmp_20_1_12_2_reg_8224;
reg [31:0] tmp_20_2_0_2_reg_8229;
reg [31:0] tmp_20_2_1_2_reg_8234;
reg [31:0] tmp_20_2_2_2_reg_8239;
reg [31:0] tmp_20_2_3_2_reg_8244;
reg [31:0] tmp_20_2_4_2_reg_8249;
reg [31:0] tmp_20_2_5_2_reg_8254;
reg [31:0] tmp_20_2_6_2_reg_8259;
reg [31:0] tmp_20_2_7_2_reg_8264;
reg [31:0] tmp_20_2_8_2_reg_8269;
reg [31:0] tmp_20_2_9_2_reg_8274;
reg [31:0] tmp_20_2_10_2_reg_8279;
reg [31:0] tmp_20_2_11_2_reg_8284;
reg [31:0] tmp_20_2_12_2_reg_8289;
reg [31:0] tmp_20_3_0_2_reg_8294;
reg [31:0] tmp_20_3_1_2_reg_8299;
reg [31:0] tmp_20_3_2_2_reg_8304;
reg [31:0] tmp_20_3_3_2_reg_8309;
reg [31:0] tmp_20_3_4_2_reg_8314;
reg [31:0] tmp_20_3_5_2_reg_8319;
reg [31:0] tmp_20_3_6_2_reg_8324;
reg [31:0] tmp_20_3_7_2_reg_8329;
reg [31:0] tmp_20_3_8_2_reg_8334;
reg [31:0] tmp_20_3_9_2_reg_8339;
reg [31:0] tmp_20_3_10_2_reg_8344;
reg [31:0] tmp_20_3_11_2_reg_8349;
reg [31:0] tmp_20_3_12_2_reg_8354;
reg [31:0] tmp_20_4_0_2_reg_8359;
reg [31:0] tmp_20_4_1_2_reg_8364;
reg [31:0] tmp_20_4_2_2_reg_8369;
reg [31:0] tmp_20_4_3_2_reg_8374;
reg [31:0] tmp_20_4_4_2_reg_8379;
reg [31:0] tmp_20_4_5_2_reg_8384;
reg [31:0] tmp_20_4_6_2_reg_8389;
reg [31:0] tmp_20_4_7_2_reg_8394;
reg [31:0] tmp_20_4_8_2_reg_8399;
reg [31:0] tmp_20_4_9_2_reg_8404;
reg [31:0] tmp_20_4_10_2_reg_8409;
reg [31:0] tmp_20_4_11_2_reg_8414;
reg [31:0] tmp_20_4_12_2_reg_8419;
reg [31:0] tmp_20_5_0_2_reg_8424;
reg [31:0] tmp_20_5_1_2_reg_8429;
reg [31:0] tmp_20_5_2_2_reg_8434;
reg [31:0] tmp_20_5_3_2_reg_8439;
reg [31:0] tmp_20_5_4_2_reg_8444;
reg [31:0] tmp_20_5_5_2_reg_8449;
reg [31:0] tmp_20_5_6_2_reg_8454;
reg [31:0] tmp_20_5_7_2_reg_8459;
reg [31:0] tmp_20_5_8_2_reg_8464;
reg [31:0] tmp_20_5_9_2_reg_8469;
reg [31:0] tmp_20_5_10_2_reg_8474;
reg [31:0] tmp_20_5_11_2_reg_8479;
reg [31:0] tmp_20_5_12_2_reg_8484;
reg [31:0] tmp_20_6_0_2_reg_8489;
reg ap_enable_reg_pp0_iter8;
reg [31:0] tmp_20_6_1_2_reg_8494;
reg [31:0] tmp_20_6_2_2_reg_8499;
reg [31:0] tmp_20_6_3_2_reg_8504;
reg [31:0] tmp_20_6_4_2_reg_8509;
reg [31:0] tmp_20_6_5_2_reg_8514;
reg [31:0] tmp_20_6_6_2_reg_8519;
reg [31:0] tmp_20_6_7_2_reg_8524;
reg [31:0] tmp_20_6_8_2_reg_8529;
reg [31:0] tmp_20_6_9_2_reg_8534;
reg [31:0] tmp_20_6_10_2_reg_8539;
reg [31:0] tmp_20_6_11_2_reg_8544;
reg [31:0] tmp_20_6_12_2_reg_8549;
reg [31:0] tmp_20_7_0_2_reg_8554;
reg [31:0] tmp_20_7_1_2_reg_8559;
reg [31:0] tmp_20_7_2_2_reg_8564;
reg [31:0] tmp_20_7_3_2_reg_8569;
reg [31:0] tmp_20_7_4_2_reg_8574;
reg [31:0] tmp_20_7_5_2_reg_8579;
reg [31:0] tmp_20_7_6_2_reg_8584;
reg [31:0] tmp_20_7_7_2_reg_8589;
reg [31:0] tmp_20_7_8_2_reg_8594;
reg [31:0] tmp_20_7_9_2_reg_8599;
reg [31:0] tmp_20_7_10_2_reg_8604;
reg [31:0] tmp_20_7_11_2_reg_8609;
reg [31:0] tmp_20_7_12_2_reg_8614;
wire ap_block_pp0_stage0_subdone;
reg ap_condition_pp0_exit_iter0_state2;
wire ap_block_pp0_stage7_subdone;
wire ap_block_pp0_stage1_subdone;
reg ap_enable_reg_pp0_iter9;
reg [9:0] ap_phi_mux_indvar_flatten1_phi_fu_889_p4;
wire ap_block_pp0_stage0;
reg [2:0] ap_phi_mux_i_phi_fu_900_p4;
reg [7:0] ap_phi_mux_indvar_flatten_phi_fu_912_p4;
reg [2:0] ap_phi_mux_j_phi_fu_923_p4;
reg [4:0] ap_phi_mux_row_b_phi_fu_935_p4;
wire [63:0] tmp_6_cast_fu_1775_p1;
wire ap_block_pp0_stage5;
wire [63:0] tmp_8_cast_fu_1791_p1;
wire signed [63:0] tmp_334_cast_fu_1864_p1;
wire signed [63:0] tmp_335_cast_fu_1870_p1;
wire [63:0] tmp_330_cast_fu_1910_p1;
wire ap_block_pp0_stage6;
wire [63:0] tmp_336_cast_fu_1966_p1;
wire [63:0] tmp_337_cast_fu_1972_p1;
wire [63:0] tmp_338_cast_fu_1998_p1;
wire ap_block_pp0_stage7;
wire [63:0] tmp_339_cast_fu_2004_p1;
wire [63:0] tmp_340_cast_fu_2010_p1;
wire [63:0] tmp_341_cast_fu_2016_p1;
wire [63:0] tmp_334_fu_2029_p1;
wire ap_block_pp0_stage2;
wire [63:0] tmp_336_fu_2040_p3;
wire [63:0] tmp_338_fu_2054_p3;
wire ap_block_pp0_stage3;
wire [63:0] tmp_340_fu_2068_p3;
wire [63:0] tmp_342_fu_2082_p3;
wire ap_block_pp0_stage4;
wire [63:0] tmp_344_fu_2096_p3;
wire [63:0] tmp_346_fu_2118_p3;
wire [63:0] tmp_348_fu_2132_p3;
reg [31:0] bufw_0_Addr_A_orig;
wire [31:0] bufw_0_Addr_B_orig;
reg [31:0] bufi_0_Addr_A_orig;
reg [31:0] bufi_0_Addr_B_orig;
reg [31:0] bufi_1_Addr_A_orig;
reg [31:0] bufi_1_Addr_B_orig;
reg [31:0] bufi_2_Addr_A_orig;
reg [31:0] bufi_2_Addr_B_orig;
reg [31:0] bufw_1_Addr_A_orig;
wire [31:0] bufw_1_Addr_B_orig;
reg [31:0] bufw_2_Addr_A_orig;
wire [31:0] bufw_2_Addr_B_orig;
reg [31:0] bufw_3_Addr_A_orig;
wire [31:0] bufw_3_Addr_B_orig;
reg [31:0] bufw_4_Addr_A_orig;
wire [31:0] bufw_4_Addr_B_orig;
reg [31:0] bufw_5_Addr_A_orig;
wire [31:0] bufw_5_Addr_B_orig;
reg [31:0] bufw_6_Addr_A_orig;
wire [31:0] bufw_6_Addr_B_orig;
reg [31:0] bufw_7_Addr_A_orig;
wire [31:0] bufw_7_Addr_B_orig;
reg [31:0] bufw_8_Addr_A_orig;
wire [31:0] bufw_8_Addr_B_orig;
reg [31:0] bufw_9_Addr_A_orig;
wire [31:0] bufw_9_Addr_B_orig;
reg [31:0] bufw_10_Addr_A_orig;
wire [31:0] bufw_10_Addr_B_orig;
reg [31:0] bufw_11_Addr_A_orig;
wire [31:0] bufw_11_Addr_B_orig;
reg [31:0] bufw_12_Addr_A_orig;
wire [31:0] bufw_12_Addr_B_orig;
reg [31:0] bufo_Addr_A_orig;
reg [31:0] bufo_Addr_B_orig;
wire [415:0] tmp_49_fu_2620_p14;
wire [415:0] tmp_89_fu_2690_p14;
wire [415:0] tmp_129_fu_2760_p14;
wire [415:0] tmp_169_fu_2830_p14;
wire [415:0] tmp_209_fu_2900_p14;
wire [415:0] tmp_249_fu_2970_p14;
wire [415:0] tmp_289_fu_3040_p14;
wire ap_block_pp0_stage1;
wire [415:0] tmp_329_fu_3110_p14;
reg [31:0] grp_fu_943_p0;
reg [31:0] grp_fu_943_p1;
reg [31:0] grp_fu_947_p0;
reg [31:0] grp_fu_947_p1;
reg [31:0] grp_fu_951_p0;
reg [31:0] grp_fu_951_p1;
reg [31:0] grp_fu_955_p0;
reg [31:0] grp_fu_955_p1;
reg [31:0] grp_fu_959_p0;
reg [31:0] grp_fu_959_p1;
reg [31:0] grp_fu_963_p0;
reg [31:0] grp_fu_963_p1;
reg [31:0] grp_fu_967_p0;
reg [31:0] grp_fu_967_p1;
reg [31:0] grp_fu_971_p0;
reg [31:0] grp_fu_971_p1;
reg [31:0] grp_fu_975_p0;
reg [31:0] grp_fu_975_p1;
reg [31:0] grp_fu_979_p0;
reg [31:0] grp_fu_979_p1;
reg [31:0] grp_fu_983_p0;
reg [31:0] grp_fu_983_p1;
reg [31:0] grp_fu_987_p0;
reg [31:0] grp_fu_987_p1;
reg [31:0] grp_fu_991_p0;
reg [31:0] grp_fu_991_p1;
reg [31:0] grp_fu_995_p0;
reg [31:0] grp_fu_995_p1;
reg [31:0] grp_fu_999_p0;
reg [31:0] grp_fu_999_p1;
reg [31:0] grp_fu_1003_p0;
reg [31:0] grp_fu_1003_p1;
reg [31:0] grp_fu_1007_p0;
reg [31:0] grp_fu_1007_p1;
reg [31:0] grp_fu_1011_p0;
reg [31:0] grp_fu_1011_p1;
reg [31:0] grp_fu_1015_p0;
reg [31:0] grp_fu_1015_p1;
reg [31:0] grp_fu_1019_p0;
reg [31:0] grp_fu_1019_p1;
reg [31:0] grp_fu_1023_p0;
reg [31:0] grp_fu_1023_p1;
reg [31:0] grp_fu_1027_p0;
reg [31:0] grp_fu_1027_p1;
reg [31:0] grp_fu_1031_p0;
reg [31:0] grp_fu_1031_p1;
reg [31:0] grp_fu_1035_p0;
reg [31:0] grp_fu_1035_p1;
reg [31:0] grp_fu_1039_p0;
reg [31:0] grp_fu_1039_p1;
reg [31:0] grp_fu_1043_p0;
reg [31:0] grp_fu_1043_p1;
reg [31:0] grp_fu_1047_p0;
reg [31:0] grp_fu_1047_p1;
reg [31:0] grp_fu_1051_p0;
reg [31:0] grp_fu_1051_p1;
reg [31:0] grp_fu_1055_p0;
reg [31:0] grp_fu_1055_p1;
reg [31:0] grp_fu_1059_p0;
reg [31:0] grp_fu_1059_p1;
reg [31:0] grp_fu_1063_p0;
reg [31:0] grp_fu_1063_p1;
reg [31:0] grp_fu_1067_p0;
reg [31:0] grp_fu_1067_p1;
reg [31:0] grp_fu_1071_p0;
reg [31:0] grp_fu_1071_p1;
reg [31:0] grp_fu_1075_p0;
reg [31:0] grp_fu_1075_p1;
reg [31:0] grp_fu_1079_p0;
reg [31:0] grp_fu_1079_p1;
reg [31:0] grp_fu_1083_p0;
reg [31:0] grp_fu_1083_p1;
reg [31:0] grp_fu_1087_p0;
reg [31:0] grp_fu_1087_p1;
reg [31:0] grp_fu_1091_p0;
reg [31:0] grp_fu_1091_p1;
reg [31:0] grp_fu_1095_p0;
reg [31:0] grp_fu_1095_p1;
reg [31:0] grp_fu_1099_p0;
reg [31:0] grp_fu_1099_p1;
reg [31:0] grp_fu_1103_p0;
reg [31:0] grp_fu_1103_p1;
reg [31:0] grp_fu_1107_p0;
reg [31:0] grp_fu_1107_p1;
reg [31:0] grp_fu_1111_p0;
reg [31:0] grp_fu_1111_p1;
reg [31:0] grp_fu_1115_p0;
reg [31:0] grp_fu_1115_p1;
reg [31:0] grp_fu_1119_p0;
reg [31:0] grp_fu_1119_p1;
reg [31:0] grp_fu_1123_p0;
reg [31:0] grp_fu_1123_p1;
reg [31:0] grp_fu_1127_p0;
reg [31:0] grp_fu_1127_p1;
reg [31:0] grp_fu_1131_p0;
reg [31:0] grp_fu_1131_p1;
reg [31:0] grp_fu_1135_p0;
reg [31:0] grp_fu_1135_p1;
reg [31:0] grp_fu_1139_p0;
reg [31:0] grp_fu_1139_p1;
reg [31:0] grp_fu_1143_p0;
reg [31:0] grp_fu_1143_p1;
reg [31:0] grp_fu_1147_p0;
reg [31:0] grp_fu_1147_p1;
reg [31:0] grp_fu_1151_p0;
reg [31:0] grp_fu_1151_p1;
reg [31:0] grp_fu_1155_p0;
reg [31:0] grp_fu_1155_p1;
reg [31:0] grp_fu_1159_p0;
reg [31:0] grp_fu_1159_p1;
reg [31:0] grp_fu_1163_p0;
reg [31:0] grp_fu_1163_p1;
reg [31:0] grp_fu_1167_p0;
reg [31:0] grp_fu_1167_p1;
reg [31:0] grp_fu_1171_p0;
reg [31:0] grp_fu_1171_p1;
reg [31:0] grp_fu_1175_p0;
reg [31:0] grp_fu_1175_p1;
reg [31:0] grp_fu_1179_p0;
reg [31:0] grp_fu_1179_p1;
reg [31:0] grp_fu_1183_p0;
reg [31:0] grp_fu_1183_p1;
reg [31:0] grp_fu_1187_p0;
reg [31:0] grp_fu_1187_p1;
reg [31:0] grp_fu_1191_p0;
reg [31:0] grp_fu_1191_p1;
reg [31:0] grp_fu_1195_p0;
reg [31:0] grp_fu_1195_p1;
reg [31:0] grp_fu_1199_p0;
reg [31:0] grp_fu_1199_p1;
reg [31:0] grp_fu_1203_p0;
reg [31:0] grp_fu_1203_p1;
reg [31:0] grp_fu_1207_p0;
reg [31:0] grp_fu_1207_p1;
reg [31:0] grp_fu_1211_p0;
reg [31:0] grp_fu_1211_p1;
reg [31:0] grp_fu_1215_p0;
reg [31:0] grp_fu_1215_p1;
reg [31:0] grp_fu_1219_p0;
reg [31:0] grp_fu_1219_p1;
reg [31:0] grp_fu_1223_p0;
reg [31:0] grp_fu_1223_p1;
reg [31:0] grp_fu_1227_p0;
reg [31:0] grp_fu_1227_p1;
reg [31:0] grp_fu_1231_p0;
reg [31:0] grp_fu_1231_p1;
reg [31:0] grp_fu_1235_p0;
reg [31:0] grp_fu_1235_p1;
reg [31:0] grp_fu_1239_p0;
reg [31:0] grp_fu_1239_p1;
reg [31:0] grp_fu_1243_p0;
reg [31:0] grp_fu_1243_p1;
reg [31:0] grp_fu_1247_p0;
reg [31:0] grp_fu_1247_p1;
reg [31:0] grp_fu_1251_p0;
reg [31:0] grp_fu_1251_p1;
wire [415:0] grp_fu_1255_p1;
wire [415:0] grp_fu_1265_p1;
wire [415:0] grp_fu_1275_p1;
wire [415:0] grp_fu_1285_p1;
wire [415:0] grp_fu_1295_p1;
wire [415:0] grp_fu_1305_p1;
wire [415:0] grp_fu_1315_p1;
wire [415:0] grp_fu_1325_p1;
wire [415:0] grp_fu_1335_p1;
wire [415:0] grp_fu_1345_p1;
wire [415:0] grp_fu_1355_p1;
wire [415:0] grp_fu_1365_p1;
wire [415:0] grp_fu_1375_p1;
wire [415:0] grp_fu_1385_p1;
wire [415:0] grp_fu_1395_p1;
wire [415:0] grp_fu_1405_p1;
wire [415:0] grp_fu_1415_p1;
wire [415:0] grp_fu_1425_p1;
wire [415:0] grp_fu_1435_p1;
wire [415:0] grp_fu_1445_p1;
wire [415:0] grp_fu_1455_p1;
wire [415:0] grp_fu_1465_p1;
wire [415:0] grp_fu_1475_p1;
wire [415:0] grp_fu_1485_p1;
wire [3:0] tmp_6_cast2_fu_1495_p1;
wire [0:0] not_exitcond_flatten_fu_1590_p2;
wire [0:0] tmp_4_fu_1600_p2;
wire [4:0] tmp_fu_1622_p3;
wire [5:0] tmp_1_mid2_cast_fu_1619_p1;
wire [5:0] p_shl2_cast_fu_1629_p1;
wire [4:0] tmp_2_cast_mid2_fu_1639_p1;
wire [8:0] tmp_10_fu_1672_p3;
wire [6:0] tmp_50_fu_1683_p3;
wire [9:0] p_shl_cast_fu_1679_p1;
wire [9:0] p_shl1_cast_fu_1690_p1;
wire [6:0] tmp_1_cast_fu_1700_p1;
wire [5:0] tmp_5_mid2_cast_fu_1724_p1;
wire [6:0] tmp_2_cast_fu_1703_p1;
wire [2:0] tmp_13_1_mid_fu_1712_p3;
wire [2:0] tmp_13_1_mid2_fu_1738_p3;
wire [9:0] tmp_5_mid2_cast1_fu_1718_p1;
wire [9:0] tmp_13_1_mid2_cast_fu_1744_p1;
wire [2:0] tmp_13_2_mid_fu_1763_p3;
wire [2:0] tmp_13_2_mid2_fu_1814_p3;
wire [2:0] tmp_12_3_mid1_fu_1824_p2;
wire [2:0] tmp_13_3_mid_fu_1769_p3;
wire [2:0] tmp_13_3_mid2_fu_1829_p3;
wire [3:0] tmp_6_cast2_mid1_fu_1811_p1;
wire [9:0] tmp_13_2_mid2_cast_fu_1820_p1;
wire [9:0] tmp_13_3_mid2_cast_fu_1836_p1;
wire [3:0] tmp_13_4_mid_fu_1886_p3;
wire [3:0] tmp_13_4_mid2_fu_1926_p3;
wire [3:0] tmp_13_5_mid_fu_1892_p3;
wire [3:0] tmp_13_5_mid2_fu_1936_p3;
wire [3:0] tmp_13_6_mid_fu_1898_p3;
wire [3:0] tmp_13_6_mid2_fu_1946_p3;
wire [3:0] tmp_13_7_mid_fu_1904_p3;
wire [3:0] tmp_13_7_mid2_fu_1956_p3;
wire [9:0] tmp_13_4_mid2_cast_fu_1932_p1;
wire [9:0] tmp_13_5_mid2_cast_fu_1942_p1;
wire [9:0] tmp_13_6_mid2_cast_fu_1952_p1;
wire [9:0] tmp_13_7_mid2_cast_fu_1962_p1;
wire [7:0] tmp_335_fu_2034_p2;
wire [7:0] tmp_337_fu_2049_p2;
wire [7:0] tmp_339_fu_2063_p2;
wire [7:0] tmp_341_fu_2077_p2;
wire [7:0] tmp_343_fu_2091_p2;
wire [415:0] tmp_350_fu_2105_p0;
wire [415:0] tmp_352_fu_2109_p0;
wire [7:0] tmp_345_fu_2113_p2;
wire [7:0] tmp_347_fu_2127_p2;
wire [415:0] tmp_353_fu_2141_p0;
wire [415:0] tmp_354_fu_2145_p0;
wire [415:0] tmp_355_fu_2149_p0;
wire [415:0] tmp_356_fu_2153_p0;
wire [415:0] tmp_357_fu_2157_p0;
wire [415:0] tmp_358_fu_2161_p0;
wire [31:0] tmp_48_fu_2617_p1;
wire [31:0] tmp_45_fu_2614_p1;
wire [31:0] tmp_42_fu_2611_p1;
wire [31:0] tmp_39_fu_2608_p1;
wire [31:0] tmp_36_fu_2605_p1;
wire [31:0] tmp_33_fu_2602_p1;
wire [31:0] tmp_30_fu_2599_p1;
wire [31:0] tmp_27_fu_2596_p1;
wire [31:0] tmp_24_fu_2593_p1;
wire [31:0] tmp_21_fu_2590_p1;
wire [31:0] tmp_18_fu_2587_p1;
wire [31:0] tmp_15_fu_2584_p1;
wire [31:0] tmp_12_fu_2581_p1;
wire [31:0] tmp_88_fu_2687_p1;
wire [31:0] tmp_85_fu_2684_p1;
wire [31:0] tmp_82_fu_2681_p1;
wire [31:0] tmp_79_fu_2678_p1;
wire [31:0] tmp_76_fu_2675_p1;
wire [31:0] tmp_73_fu_2672_p1;
wire [31:0] tmp_70_fu_2669_p1;
wire [31:0] tmp_67_fu_2666_p1;
wire [31:0] tmp_64_fu_2663_p1;
wire [31:0] tmp_61_fu_2660_p1;
wire [31:0] tmp_58_fu_2657_p1;
wire [31:0] tmp_55_fu_2654_p1;
wire [31:0] tmp_52_fu_2651_p1;
wire [31:0] tmp_128_fu_2757_p1;
wire [31:0] tmp_125_fu_2754_p1;
wire [31:0] tmp_122_fu_2751_p1;
wire [31:0] tmp_119_fu_2748_p1;
wire [31:0] tmp_116_fu_2745_p1;
wire [31:0] tmp_113_fu_2742_p1;
wire [31:0] tmp_110_fu_2739_p1;
wire [31:0] tmp_107_fu_2736_p1;
wire [31:0] tmp_104_fu_2733_p1;
wire [31:0] tmp_101_fu_2730_p1;
wire [31:0] tmp_98_fu_2727_p1;
wire [31:0] tmp_95_fu_2724_p1;
wire [31:0] tmp_92_fu_2721_p1;
wire [31:0] tmp_168_fu_2827_p1;
wire [31:0] tmp_165_fu_2824_p1;
wire [31:0] tmp_162_fu_2821_p1;
wire [31:0] tmp_159_fu_2818_p1;
wire [31:0] tmp_156_fu_2815_p1;
wire [31:0] tmp_153_fu_2812_p1;
wire [31:0] tmp_150_fu_2809_p1;
wire [31:0] tmp_147_fu_2806_p1;
wire [31:0] tmp_144_fu_2803_p1;
wire [31:0] tmp_141_fu_2800_p1;
wire [31:0] tmp_138_fu_2797_p1;
wire [31:0] tmp_135_fu_2794_p1;
wire [31:0] tmp_132_fu_2791_p1;
wire [31:0] tmp_208_fu_2897_p1;
wire [31:0] tmp_205_fu_2894_p1;
wire [31:0] tmp_202_fu_2891_p1;
wire [31:0] tmp_199_fu_2888_p1;
wire [31:0] tmp_196_fu_2885_p1;
wire [31:0] tmp_193_fu_2882_p1;
wire [31:0] tmp_190_fu_2879_p1;
wire [31:0] tmp_187_fu_2876_p1;
wire [31:0] tmp_184_fu_2873_p1;
wire [31:0] tmp_181_fu_2870_p1;
wire [31:0] tmp_178_fu_2867_p1;
wire [31:0] tmp_175_fu_2864_p1;
wire [31:0] tmp_172_fu_2861_p1;
wire [31:0] tmp_248_fu_2967_p1;
wire [31:0] tmp_245_fu_2964_p1;
wire [31:0] tmp_242_fu_2961_p1;
wire [31:0] tmp_239_fu_2958_p1;
wire [31:0] tmp_236_fu_2955_p1;
wire [31:0] tmp_233_fu_2952_p1;
wire [31:0] tmp_230_fu_2949_p1;
wire [31:0] tmp_227_fu_2946_p1;
wire [31:0] tmp_224_fu_2943_p1;
wire [31:0] tmp_221_fu_2940_p1;
wire [31:0] tmp_218_fu_2937_p1;
wire [31:0] tmp_215_fu_2934_p1;
wire [31:0] tmp_212_fu_2931_p1;
wire [31:0] tmp_288_fu_3037_p1;
wire [31:0] tmp_285_fu_3034_p1;
wire [31:0] tmp_282_fu_3031_p1;
wire [31:0] tmp_279_fu_3028_p1;
wire [31:0] tmp_276_fu_3025_p1;
wire [31:0] tmp_273_fu_3022_p1;
wire [31:0] tmp_270_fu_3019_p1;
wire [31:0] tmp_267_fu_3016_p1;
wire [31:0] tmp_264_fu_3013_p1;
wire [31:0] tmp_261_fu_3010_p1;
wire [31:0] tmp_258_fu_3007_p1;
wire [31:0] tmp_255_fu_3004_p1;
wire [31:0] tmp_252_fu_3001_p1;
wire [31:0] tmp_328_fu_3107_p1;
wire [31:0] tmp_325_fu_3104_p1;
wire [31:0] tmp_322_fu_3101_p1;
wire [31:0] tmp_319_fu_3098_p1;
wire [31:0] tmp_316_fu_3095_p1;
wire [31:0] tmp_313_fu_3092_p1;
wire [31:0] tmp_310_fu_3089_p1;
wire [31:0] tmp_307_fu_3086_p1;
wire [31:0] tmp_304_fu_3083_p1;
wire [31:0] tmp_301_fu_3080_p1;
wire [31:0] tmp_298_fu_3077_p1;
wire [31:0] tmp_295_fu_3074_p1;
wire [31:0] tmp_292_fu_3071_p1;
wire ap_CS_fsm_state76;
reg [9:0] ap_NS_fsm;
wire ap_block_pp0_stage2_subdone;
wire ap_block_pp0_stage3_subdone;
wire ap_block_pp0_stage4_subdone;
wire ap_block_pp0_stage5_subdone;
wire ap_block_pp0_stage6_subdone;
reg ap_idle_pp0;
wire ap_enable_pp0;
// power-on initialization
initial begin
#0 ap_CS_fsm = 10'd1;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
#0 ap_enable_reg_pp0_iter5 = 1'b0;
#0 ap_enable_reg_pp0_iter6 = 1'b0;
#0 ap_enable_reg_pp0_iter7 = 1'b0;
#0 ap_enable_reg_pp0_iter8 = 1'b0;
#0 ap_enable_reg_pp0_iter9 = 1'b0;
end
convolve_kernel_control_s_axi #(
.C_S_AXI_ADDR_WIDTH( C_S_AXI_CONTROL_ADDR_WIDTH ),
.C_S_AXI_DATA_WIDTH( C_S_AXI_CONTROL_DATA_WIDTH ))
convolve_kernel_control_s_axi_U(
.AWVALID(s_axi_control_AWVALID),
.AWREADY(s_axi_control_AWREADY),
.AWADDR(s_axi_control_AWADDR),
.WVALID(s_axi_control_WVALID),
.WREADY(s_axi_control_WREADY),
.WDATA(s_axi_control_WDATA),
.WSTRB(s_axi_control_WSTRB),
.ARVALID(s_axi_control_ARVALID),
.ARREADY(s_axi_control_ARREADY),
.ARADDR(s_axi_control_ARADDR),
.RVALID(s_axi_control_RVALID),
.RREADY(s_axi_control_RREADY),
.RDATA(s_axi_control_RDATA),
.RRESP(s_axi_control_RRESP),
.BVALID(s_axi_control_BVALID),
.BREADY(s_axi_control_BREADY),
.BRESP(s_axi_control_BRESP),
.ACLK(ap_clk),
.ARESET(ap_rst_n_inv),
.ACLK_EN(1'b1),
.ap_start(ap_start),
.interrupt(interrupt),
.ap_ready(ap_ready),
.ap_done(ap_done),
.ap_idle(ap_idle)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U1(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_943_p0),
.din1(grp_fu_943_p1),
.ce(1'b1),
.dout(grp_fu_943_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U2(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_947_p0),
.din1(grp_fu_947_p1),
.ce(1'b1),
.dout(grp_fu_947_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U3(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_951_p0),
.din1(grp_fu_951_p1),
.ce(1'b1),
.dout(grp_fu_951_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U4(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_955_p0),
.din1(grp_fu_955_p1),
.ce(1'b1),
.dout(grp_fu_955_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U5(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_959_p0),
.din1(grp_fu_959_p1),
.ce(1'b1),
.dout(grp_fu_959_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U6(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_963_p0),
.din1(grp_fu_963_p1),
.ce(1'b1),
.dout(grp_fu_963_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U7(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_967_p0),
.din1(grp_fu_967_p1),
.ce(1'b1),
.dout(grp_fu_967_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U8(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_971_p0),
.din1(grp_fu_971_p1),
.ce(1'b1),
.dout(grp_fu_971_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U9(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_975_p0),
.din1(grp_fu_975_p1),
.ce(1'b1),
.dout(grp_fu_975_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U10(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_979_p0),
.din1(grp_fu_979_p1),
.ce(1'b1),
.dout(grp_fu_979_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U11(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_983_p0),
.din1(grp_fu_983_p1),
.ce(1'b1),
.dout(grp_fu_983_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U12(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_987_p0),
.din1(grp_fu_987_p1),
.ce(1'b1),
.dout(grp_fu_987_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U13(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_991_p0),
.din1(grp_fu_991_p1),
.ce(1'b1),
.dout(grp_fu_991_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U14(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_995_p0),
.din1(grp_fu_995_p1),
.ce(1'b1),
.dout(grp_fu_995_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U15(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_999_p0),
.din1(grp_fu_999_p1),
.ce(1'b1),
.dout(grp_fu_999_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U16(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1003_p0),
.din1(grp_fu_1003_p1),
.ce(1'b1),
.dout(grp_fu_1003_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U17(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1007_p0),
.din1(grp_fu_1007_p1),
.ce(1'b1),
.dout(grp_fu_1007_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U18(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1011_p0),
.din1(grp_fu_1011_p1),
.ce(1'b1),
.dout(grp_fu_1011_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U19(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1015_p0),
.din1(grp_fu_1015_p1),
.ce(1'b1),
.dout(grp_fu_1015_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U20(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1019_p0),
.din1(grp_fu_1019_p1),
.ce(1'b1),
.dout(grp_fu_1019_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U21(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1023_p0),
.din1(grp_fu_1023_p1),
.ce(1'b1),
.dout(grp_fu_1023_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U22(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1027_p0),
.din1(grp_fu_1027_p1),
.ce(1'b1),
.dout(grp_fu_1027_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U23(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1031_p0),
.din1(grp_fu_1031_p1),
.ce(1'b1),
.dout(grp_fu_1031_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U24(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1035_p0),
.din1(grp_fu_1035_p1),
.ce(1'b1),
.dout(grp_fu_1035_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U25(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1039_p0),
.din1(grp_fu_1039_p1),
.ce(1'b1),
.dout(grp_fu_1039_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U26(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1043_p0),
.din1(grp_fu_1043_p1),
.ce(1'b1),
.dout(grp_fu_1043_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U27(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1047_p0),
.din1(grp_fu_1047_p1),
.ce(1'b1),
.dout(grp_fu_1047_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U28(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1051_p0),
.din1(grp_fu_1051_p1),
.ce(1'b1),
.dout(grp_fu_1051_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U29(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1055_p0),
.din1(grp_fu_1055_p1),
.ce(1'b1),
.dout(grp_fu_1055_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U30(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1059_p0),
.din1(grp_fu_1059_p1),
.ce(1'b1),
.dout(grp_fu_1059_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U31(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1063_p0),
.din1(grp_fu_1063_p1),
.ce(1'b1),
.dout(grp_fu_1063_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U32(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1067_p0),
.din1(grp_fu_1067_p1),
.ce(1'b1),
.dout(grp_fu_1067_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U33(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1071_p0),
.din1(grp_fu_1071_p1),
.ce(1'b1),
.dout(grp_fu_1071_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U34(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1075_p0),
.din1(grp_fu_1075_p1),
.ce(1'b1),
.dout(grp_fu_1075_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U35(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1079_p0),
.din1(grp_fu_1079_p1),
.ce(1'b1),
.dout(grp_fu_1079_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U36(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1083_p0),
.din1(grp_fu_1083_p1),
.ce(1'b1),
.dout(grp_fu_1083_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U37(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1087_p0),
.din1(grp_fu_1087_p1),
.ce(1'b1),
.dout(grp_fu_1087_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U38(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1091_p0),
.din1(grp_fu_1091_p1),
.ce(1'b1),
.dout(grp_fu_1091_p2)
);
convolve_kernel_fbkb #(
.ID( 1 ),
.NUM_STAGE( 14 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fbkb_U39(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1095_p0),
.din1(grp_fu_1095_p1),
.ce(1'b1),
.dout(grp_fu_1095_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U40(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1099_p0),
.din1(grp_fu_1099_p1),
.ce(1'b1),
.dout(grp_fu_1099_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U41(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1103_p0),
.din1(grp_fu_1103_p1),
.ce(1'b1),
.dout(grp_fu_1103_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U42(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1107_p0),
.din1(grp_fu_1107_p1),
.ce(1'b1),
.dout(grp_fu_1107_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U43(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1111_p0),
.din1(grp_fu_1111_p1),
.ce(1'b1),
.dout(grp_fu_1111_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U44(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1115_p0),
.din1(grp_fu_1115_p1),
.ce(1'b1),
.dout(grp_fu_1115_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U45(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1119_p0),
.din1(grp_fu_1119_p1),
.ce(1'b1),
.dout(grp_fu_1119_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U46(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1123_p0),
.din1(grp_fu_1123_p1),
.ce(1'b1),
.dout(grp_fu_1123_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U47(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1127_p0),
.din1(grp_fu_1127_p1),
.ce(1'b1),
.dout(grp_fu_1127_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U48(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1131_p0),
.din1(grp_fu_1131_p1),
.ce(1'b1),
.dout(grp_fu_1131_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U49(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1135_p0),
.din1(grp_fu_1135_p1),
.ce(1'b1),
.dout(grp_fu_1135_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U50(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1139_p0),
.din1(grp_fu_1139_p1),
.ce(1'b1),
.dout(grp_fu_1139_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U51(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1143_p0),
.din1(grp_fu_1143_p1),
.ce(1'b1),
.dout(grp_fu_1143_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U52(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1147_p0),
.din1(grp_fu_1147_p1),
.ce(1'b1),
.dout(grp_fu_1147_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U53(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1151_p0),
.din1(grp_fu_1151_p1),
.ce(1'b1),
.dout(grp_fu_1151_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U54(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1155_p0),
.din1(grp_fu_1155_p1),
.ce(1'b1),
.dout(grp_fu_1155_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U55(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1159_p0),
.din1(grp_fu_1159_p1),
.ce(1'b1),
.dout(grp_fu_1159_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U56(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1163_p0),
.din1(grp_fu_1163_p1),
.ce(1'b1),
.dout(grp_fu_1163_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U57(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1167_p0),
.din1(grp_fu_1167_p1),
.ce(1'b1),
.dout(grp_fu_1167_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U58(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1171_p0),
.din1(grp_fu_1171_p1),
.ce(1'b1),
.dout(grp_fu_1171_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U59(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1175_p0),
.din1(grp_fu_1175_p1),
.ce(1'b1),
.dout(grp_fu_1175_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U60(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1179_p0),
.din1(grp_fu_1179_p1),
.ce(1'b1),
.dout(grp_fu_1179_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U61(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1183_p0),
.din1(grp_fu_1183_p1),
.ce(1'b1),
.dout(grp_fu_1183_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U62(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1187_p0),
.din1(grp_fu_1187_p1),
.ce(1'b1),
.dout(grp_fu_1187_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U63(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1191_p0),
.din1(grp_fu_1191_p1),
.ce(1'b1),
.dout(grp_fu_1191_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U64(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1195_p0),
.din1(grp_fu_1195_p1),
.ce(1'b1),
.dout(grp_fu_1195_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U65(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1199_p0),
.din1(grp_fu_1199_p1),
.ce(1'b1),
.dout(grp_fu_1199_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U66(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1203_p0),
.din1(grp_fu_1203_p1),
.ce(1'b1),
.dout(grp_fu_1203_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U67(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1207_p0),
.din1(grp_fu_1207_p1),
.ce(1'b1),
.dout(grp_fu_1207_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U68(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1211_p0),
.din1(grp_fu_1211_p1),
.ce(1'b1),
.dout(grp_fu_1211_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U69(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1215_p0),
.din1(grp_fu_1215_p1),
.ce(1'b1),
.dout(grp_fu_1215_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U70(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1219_p0),
.din1(grp_fu_1219_p1),
.ce(1'b1),
.dout(grp_fu_1219_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U71(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1223_p0),
.din1(grp_fu_1223_p1),
.ce(1'b1),
.dout(grp_fu_1223_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U72(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1227_p0),
.din1(grp_fu_1227_p1),
.ce(1'b1),
.dout(grp_fu_1227_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U73(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1231_p0),
.din1(grp_fu_1231_p1),
.ce(1'b1),
.dout(grp_fu_1231_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U74(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1235_p0),
.din1(grp_fu_1235_p1),
.ce(1'b1),
.dout(grp_fu_1235_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U75(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1239_p0),
.din1(grp_fu_1239_p1),
.ce(1'b1),
.dout(grp_fu_1239_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U76(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1243_p0),
.din1(grp_fu_1243_p1),
.ce(1'b1),
.dout(grp_fu_1243_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U77(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1247_p0),
.din1(grp_fu_1247_p1),
.ce(1'b1),
.dout(grp_fu_1247_p2)
);
convolve_kernel_fcud #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
convolve_kernel_fcud_U78(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.din0(grp_fu_1251_p0),
.din1(grp_fu_1251_p1),
.ce(1'b1),
.dout(grp_fu_1251_p2)
);
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else begin
if (((ap_block_pp0_stage0_subdone == 1'b0) & (1'b1 == ap_condition_pp0_exit_iter0_state2) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_enable_reg_pp0_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if (((ap_block_pp0_stage7_subdone == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
if ((1'b1 == ap_condition_pp0_exit_iter0_state2)) begin
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 ^ 1'b1);
end else if ((1'b1 == 1'b1)) begin
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if (((ap_block_pp0_stage7_subdone == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if (((ap_block_pp0_stage7_subdone == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end else begin
if (((ap_block_pp0_stage7_subdone == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter5 <= 1'b0;
end else begin
if (((ap_block_pp0_stage7_subdone == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter6 <= 1'b0;
end else begin
if (((ap_block_pp0_stage7_subdone == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter7 <= 1'b0;
end else begin
if (((ap_block_pp0_stage7_subdone == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter8 <= 1'b0;
end else begin
if (((ap_block_pp0_stage7_subdone == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter9 <= 1'b0;
end else begin
if ((((ap_block_pp0_stage7_subdone == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage1_subdone == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_enable_reg_pp0_iter9 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten1_reg_3176 == 1'd0) & (ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
i_reg_896 <= tmp_1_mid2_v_reg_3225;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
i_reg_896 <= 3'd0;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten1_reg_3176 == 1'd0) & (ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
indvar_flatten1_reg_885 <= indvar_flatten_next1_reg_3180;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
indvar_flatten1_reg_885 <= 10'd0;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten1_reg_3176 == 1'd0) & (ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
indvar_flatten_reg_908 <= indvar_flatten_next_reg_3252;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
indvar_flatten_reg_908 <= 8'd0;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten1_reg_3176 == 1'd0) & (ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
j_reg_919 <= tmp_5_mid2_reg_3286;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
j_reg_919 <= 3'd0;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten1_reg_3176 == 1'd0) & (ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
row_b_reg_931 <= row_b_1_reg_3276;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
row_b_reg_931 <= 5'd0;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 <= exitcond_flatten1_reg_3176;
ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter1_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter2_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244 <= tmp_19_1_0_1_reg_5244;
ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344 <= tmp_19_1_10_1_reg_5344;
ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354 <= tmp_19_1_11_1_reg_5354;
ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364 <= tmp_19_1_12_1_reg_5364;
ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254 <= tmp_19_1_1_1_reg_5254;
ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264 <= tmp_19_1_2_1_reg_5264;
ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274 <= tmp_19_1_3_1_reg_5274;
ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284 <= tmp_19_1_4_1_reg_5284;
ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294 <= tmp_19_1_5_1_reg_5294;
ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304 <= tmp_19_1_6_1_reg_5304;
ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314 <= tmp_19_1_7_1_reg_5314;
ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324 <= tmp_19_1_8_1_reg_5324;
ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334 <= tmp_19_1_9_1_reg_5334;
ap_reg_pp0_iter4_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter3_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter4_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter6_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter5_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter6_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter7_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter8_exitcond_flatten1_reg_3176;
exitcond_flatten1_reg_3176 <= exitcond_flatten1_fu_1541_p2;
tmp_12_1_reg_3141 <= tmp_12_1_fu_1499_p2;
tmp_12_2_reg_3146 <= tmp_12_2_fu_1505_p2;
tmp_12_3_reg_3151 <= tmp_12_3_fu_1511_p2;
tmp_12_4_reg_3156 <= tmp_12_4_fu_1517_p2;
tmp_12_5_reg_3161 <= tmp_12_5_fu_1523_p2;
tmp_12_6_reg_3166 <= tmp_12_6_fu_1529_p2;
tmp_12_7_reg_3171 <= tmp_12_7_fu_1535_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage1_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
ap_reg_pp0_iter1_row_b_mid2_reg_3245 <= row_b_mid2_reg_3245;
ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504 <= tmp_19_2_0_1_reg_5504;
ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604 <= tmp_19_2_10_1_reg_5604;
ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614 <= tmp_19_2_11_1_reg_5614;
ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624 <= tmp_19_2_12_1_reg_5624;
ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514 <= tmp_19_2_1_1_reg_5514;
ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524 <= tmp_19_2_2_1_reg_5524;
ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534 <= tmp_19_2_3_1_reg_5534;
ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544 <= tmp_19_2_4_1_reg_5544;
ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554 <= tmp_19_2_5_1_reg_5554;
ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564 <= tmp_19_2_6_1_reg_5564;
ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574 <= tmp_19_2_7_1_reg_5574;
ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584 <= tmp_19_2_8_1_reg_5584;
ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594 <= tmp_19_2_9_1_reg_5594;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage2_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
ap_reg_pp0_iter2_bufo_addr_1_reg_4322[7 : 3] <= bufo_addr_1_reg_4322[7 : 3];
ap_reg_pp0_iter2_bufo_addr_reg_4317[7 : 3] <= bufo_addr_reg_4317[7 : 3];
ap_reg_pp0_iter3_bufo_addr_1_reg_4322[7 : 3] <= ap_reg_pp0_iter2_bufo_addr_1_reg_4322[7 : 3];
ap_reg_pp0_iter3_bufo_addr_reg_4317[7 : 3] <= ap_reg_pp0_iter2_bufo_addr_reg_4317[7 : 3];
ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824 <= tmp_19_3_0_1_reg_5824;
ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874 <= tmp_19_3_10_1_reg_5874;
ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879 <= tmp_19_3_11_1_reg_5879;
ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884 <= tmp_19_3_12_1_reg_5884;
ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829 <= tmp_19_3_1_1_reg_5829;
ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834 <= tmp_19_3_2_1_reg_5834;
ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839 <= tmp_19_3_3_1_reg_5839;
ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844 <= tmp_19_3_4_1_reg_5844;
ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849 <= tmp_19_3_5_1_reg_5849;
ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854 <= tmp_19_3_6_1_reg_5854;
ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859 <= tmp_19_3_7_1_reg_5859;
ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864 <= tmp_19_3_8_1_reg_5864;
ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869 <= tmp_19_3_9_1_reg_5869;
ap_reg_pp0_iter4_bufo_addr_1_reg_4322[7 : 3] <= ap_reg_pp0_iter3_bufo_addr_1_reg_4322[7 : 3];
ap_reg_pp0_iter4_bufo_addr_reg_4317[7 : 3] <= ap_reg_pp0_iter3_bufo_addr_reg_4317[7 : 3];
ap_reg_pp0_iter5_bufo_addr_1_reg_4322[7 : 3] <= ap_reg_pp0_iter4_bufo_addr_1_reg_4322[7 : 3];
ap_reg_pp0_iter5_bufo_addr_reg_4317[7 : 3] <= ap_reg_pp0_iter4_bufo_addr_reg_4317[7 : 3];
ap_reg_pp0_iter6_bufo_addr_1_reg_4322[7 : 3] <= ap_reg_pp0_iter5_bufo_addr_1_reg_4322[7 : 3];
ap_reg_pp0_iter6_bufo_addr_reg_4317[7 : 3] <= ap_reg_pp0_iter5_bufo_addr_reg_4317[7 : 3];
ap_reg_pp0_iter7_bufo_addr_1_reg_4322[7 : 3] <= ap_reg_pp0_iter6_bufo_addr_1_reg_4322[7 : 3];
ap_reg_pp0_iter7_bufo_addr_reg_4317[7 : 3] <= ap_reg_pp0_iter6_bufo_addr_reg_4317[7 : 3];
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage3_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
ap_reg_pp0_iter2_bufo_addr_2_reg_4429[7 : 3] <= bufo_addr_2_reg_4429[7 : 3];
ap_reg_pp0_iter2_bufo_addr_3_reg_4434[7 : 3] <= bufo_addr_3_reg_4434[7 : 3];
ap_reg_pp0_iter3_bufo_addr_2_reg_4429[7 : 3] <= ap_reg_pp0_iter2_bufo_addr_2_reg_4429[7 : 3];
ap_reg_pp0_iter3_bufo_addr_3_reg_4434[7 : 3] <= ap_reg_pp0_iter2_bufo_addr_3_reg_4434[7 : 3];
ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149 <= tmp_19_4_0_1_reg_6149;
ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199 <= tmp_19_4_10_1_reg_6199;
ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204 <= tmp_19_4_11_1_reg_6204;
ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209 <= tmp_19_4_12_1_reg_6209;
ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154 <= tmp_19_4_1_1_reg_6154;
ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159 <= tmp_19_4_2_1_reg_6159;
ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164 <= tmp_19_4_3_1_reg_6164;
ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169 <= tmp_19_4_4_1_reg_6169;
ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174 <= tmp_19_4_5_1_reg_6174;
ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179 <= tmp_19_4_6_1_reg_6179;
ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184 <= tmp_19_4_7_1_reg_6184;
ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189 <= tmp_19_4_8_1_reg_6189;
ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194 <= tmp_19_4_9_1_reg_6194;
ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214 <= tmp_19_5_0_1_reg_6214;
ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264 <= tmp_19_5_10_1_reg_6264;
ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269 <= tmp_19_5_11_1_reg_6269;
ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274 <= tmp_19_5_12_1_reg_6274;
ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219 <= tmp_19_5_1_1_reg_6219;
ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224 <= tmp_19_5_2_1_reg_6224;
ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229 <= tmp_19_5_3_1_reg_6229;
ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234 <= tmp_19_5_4_1_reg_6234;
ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239 <= tmp_19_5_5_1_reg_6239;
ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244 <= tmp_19_5_6_1_reg_6244;
ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249 <= tmp_19_5_7_1_reg_6249;
ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254 <= tmp_19_5_8_1_reg_6254;
ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259 <= tmp_19_5_9_1_reg_6259;
ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284 <= tmp_19_6_0_1_reg_6284;
ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384 <= tmp_19_6_10_1_reg_6384;
ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394 <= tmp_19_6_11_1_reg_6394;
ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404 <= tmp_19_6_12_1_reg_6404;
ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294 <= tmp_19_6_1_1_reg_6294;
ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304 <= tmp_19_6_2_1_reg_6304;
ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314 <= tmp_19_6_3_1_reg_6314;
ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324 <= tmp_19_6_4_1_reg_6324;
ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334 <= tmp_19_6_5_1_reg_6334;
ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344 <= tmp_19_6_6_1_reg_6344;
ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354 <= tmp_19_6_7_1_reg_6354;
ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364 <= tmp_19_6_8_1_reg_6364;
ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374 <= tmp_19_6_9_1_reg_6374;
ap_reg_pp0_iter4_bufo_addr_2_reg_4429[7 : 3] <= ap_reg_pp0_iter3_bufo_addr_2_reg_4429[7 : 3];
ap_reg_pp0_iter4_bufo_addr_3_reg_4434[7 : 3] <= ap_reg_pp0_iter3_bufo_addr_3_reg_4434[7 : 3];
ap_reg_pp0_iter5_bufo_addr_2_reg_4429[7 : 3] <= ap_reg_pp0_iter4_bufo_addr_2_reg_4429[7 : 3];
ap_reg_pp0_iter5_bufo_addr_3_reg_4434[7 : 3] <= ap_reg_pp0_iter4_bufo_addr_3_reg_4434[7 : 3];
ap_reg_pp0_iter6_bufo_addr_2_reg_4429[7 : 3] <= ap_reg_pp0_iter5_bufo_addr_2_reg_4429[7 : 3];
ap_reg_pp0_iter6_bufo_addr_3_reg_4434[7 : 3] <= ap_reg_pp0_iter5_bufo_addr_3_reg_4434[7 : 3];
ap_reg_pp0_iter7_bufo_addr_2_reg_4429[7 : 3] <= ap_reg_pp0_iter6_bufo_addr_2_reg_4429[7 : 3];
ap_reg_pp0_iter7_bufo_addr_3_reg_4434[7 : 3] <= ap_reg_pp0_iter6_bufo_addr_3_reg_4434[7 : 3];
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage4_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
ap_reg_pp0_iter2_bufo_addr_4_reg_4439[7 : 3] <= bufo_addr_4_reg_4439[7 : 3];
ap_reg_pp0_iter2_bufo_addr_5_reg_4444[7 : 3] <= bufo_addr_5_reg_4444[7 : 3];
ap_reg_pp0_iter3_bufo_addr_4_reg_4439[7 : 3] <= ap_reg_pp0_iter2_bufo_addr_4_reg_4439[7 : 3];
ap_reg_pp0_iter3_bufo_addr_5_reg_4444[7 : 3] <= ap_reg_pp0_iter2_bufo_addr_5_reg_4444[7 : 3];
ap_reg_pp0_iter3_tmp_19_0_0_2_reg_6474 <= tmp_19_0_0_2_reg_6474;
ap_reg_pp0_iter3_tmp_19_0_10_2_reg_6524 <= tmp_19_0_10_2_reg_6524;
ap_reg_pp0_iter3_tmp_19_0_11_2_reg_6529 <= tmp_19_0_11_2_reg_6529;
ap_reg_pp0_iter3_tmp_19_0_12_2_reg_6534 <= tmp_19_0_12_2_reg_6534;
ap_reg_pp0_iter3_tmp_19_0_1_2_reg_6479 <= tmp_19_0_1_2_reg_6479;
ap_reg_pp0_iter3_tmp_19_0_2_2_reg_6484 <= tmp_19_0_2_2_reg_6484;
ap_reg_pp0_iter3_tmp_19_0_3_2_reg_6489 <= tmp_19_0_3_2_reg_6489;
ap_reg_pp0_iter3_tmp_19_0_4_2_reg_6494 <= tmp_19_0_4_2_reg_6494;
ap_reg_pp0_iter3_tmp_19_0_5_2_reg_6499 <= tmp_19_0_5_2_reg_6499;
ap_reg_pp0_iter3_tmp_19_0_6_2_reg_6504 <= tmp_19_0_6_2_reg_6504;
ap_reg_pp0_iter3_tmp_19_0_7_2_reg_6509 <= tmp_19_0_7_2_reg_6509;
ap_reg_pp0_iter3_tmp_19_0_8_2_reg_6514 <= tmp_19_0_8_2_reg_6514;
ap_reg_pp0_iter3_tmp_19_0_9_2_reg_6519 <= tmp_19_0_9_2_reg_6519;
ap_reg_pp0_iter3_tmp_19_1_0_2_reg_6539 <= tmp_19_1_0_2_reg_6539;
ap_reg_pp0_iter3_tmp_19_1_10_2_reg_6589 <= tmp_19_1_10_2_reg_6589;
ap_reg_pp0_iter3_tmp_19_1_11_2_reg_6594 <= tmp_19_1_11_2_reg_6594;
ap_reg_pp0_iter3_tmp_19_1_12_2_reg_6599 <= tmp_19_1_12_2_reg_6599;
ap_reg_pp0_iter3_tmp_19_1_1_2_reg_6544 <= tmp_19_1_1_2_reg_6544;
ap_reg_pp0_iter3_tmp_19_1_2_2_reg_6549 <= tmp_19_1_2_2_reg_6549;
ap_reg_pp0_iter3_tmp_19_1_3_2_reg_6554 <= tmp_19_1_3_2_reg_6554;
ap_reg_pp0_iter3_tmp_19_1_4_2_reg_6559 <= tmp_19_1_4_2_reg_6559;
ap_reg_pp0_iter3_tmp_19_1_5_2_reg_6564 <= tmp_19_1_5_2_reg_6564;
ap_reg_pp0_iter3_tmp_19_1_6_2_reg_6569 <= tmp_19_1_6_2_reg_6569;
ap_reg_pp0_iter3_tmp_19_1_7_2_reg_6574 <= tmp_19_1_7_2_reg_6574;
ap_reg_pp0_iter3_tmp_19_1_8_2_reg_6579 <= tmp_19_1_8_2_reg_6579;
ap_reg_pp0_iter3_tmp_19_1_9_2_reg_6584 <= tmp_19_1_9_2_reg_6584;
ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604 <= tmp_19_7_0_1_reg_6604;
ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654 <= tmp_19_7_10_1_reg_6654;
ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659 <= tmp_19_7_11_1_reg_6659;
ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664 <= tmp_19_7_12_1_reg_6664;
ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609 <= tmp_19_7_1_1_reg_6609;
ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614 <= tmp_19_7_2_1_reg_6614;
ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619 <= tmp_19_7_3_1_reg_6619;
ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624 <= tmp_19_7_4_1_reg_6624;
ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629 <= tmp_19_7_5_1_reg_6629;
ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634 <= tmp_19_7_6_1_reg_6634;
ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639 <= tmp_19_7_7_1_reg_6639;
ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644 <= tmp_19_7_8_1_reg_6644;
ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649 <= tmp_19_7_9_1_reg_6649;
ap_reg_pp0_iter4_bufo_addr_4_reg_4439[7 : 3] <= ap_reg_pp0_iter3_bufo_addr_4_reg_4439[7 : 3];
ap_reg_pp0_iter4_bufo_addr_5_reg_4444[7 : 3] <= ap_reg_pp0_iter3_bufo_addr_5_reg_4444[7 : 3];
ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474 <= ap_reg_pp0_iter3_tmp_19_0_0_2_reg_6474;
ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524 <= ap_reg_pp0_iter3_tmp_19_0_10_2_reg_6524;
ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529 <= ap_reg_pp0_iter3_tmp_19_0_11_2_reg_6529;
ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534 <= ap_reg_pp0_iter3_tmp_19_0_12_2_reg_6534;
ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479 <= ap_reg_pp0_iter3_tmp_19_0_1_2_reg_6479;
ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484 <= ap_reg_pp0_iter3_tmp_19_0_2_2_reg_6484;
ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489 <= ap_reg_pp0_iter3_tmp_19_0_3_2_reg_6489;
ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494 <= ap_reg_pp0_iter3_tmp_19_0_4_2_reg_6494;
ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499 <= ap_reg_pp0_iter3_tmp_19_0_5_2_reg_6499;
ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504 <= ap_reg_pp0_iter3_tmp_19_0_6_2_reg_6504;
ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509 <= ap_reg_pp0_iter3_tmp_19_0_7_2_reg_6509;
ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514 <= ap_reg_pp0_iter3_tmp_19_0_8_2_reg_6514;
ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519 <= ap_reg_pp0_iter3_tmp_19_0_9_2_reg_6519;
ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539 <= ap_reg_pp0_iter3_tmp_19_1_0_2_reg_6539;
ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589 <= ap_reg_pp0_iter3_tmp_19_1_10_2_reg_6589;
ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594 <= ap_reg_pp0_iter3_tmp_19_1_11_2_reg_6594;
ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599 <= ap_reg_pp0_iter3_tmp_19_1_12_2_reg_6599;
ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544 <= ap_reg_pp0_iter3_tmp_19_1_1_2_reg_6544;
ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549 <= ap_reg_pp0_iter3_tmp_19_1_2_2_reg_6549;
ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554 <= ap_reg_pp0_iter3_tmp_19_1_3_2_reg_6554;
ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559 <= ap_reg_pp0_iter3_tmp_19_1_4_2_reg_6559;
ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564 <= ap_reg_pp0_iter3_tmp_19_1_5_2_reg_6564;
ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569 <= ap_reg_pp0_iter3_tmp_19_1_6_2_reg_6569;
ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574 <= ap_reg_pp0_iter3_tmp_19_1_7_2_reg_6574;
ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579 <= ap_reg_pp0_iter3_tmp_19_1_8_2_reg_6579;
ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584 <= ap_reg_pp0_iter3_tmp_19_1_9_2_reg_6584;
ap_reg_pp0_iter5_bufo_addr_4_reg_4439[7 : 3] <= ap_reg_pp0_iter4_bufo_addr_4_reg_4439[7 : 3];
ap_reg_pp0_iter5_bufo_addr_5_reg_4444[7 : 3] <= ap_reg_pp0_iter4_bufo_addr_5_reg_4444[7 : 3];
ap_reg_pp0_iter6_bufo_addr_4_reg_4439[7 : 3] <= ap_reg_pp0_iter5_bufo_addr_4_reg_4439[7 : 3];
ap_reg_pp0_iter6_bufo_addr_5_reg_4444[7 : 3] <= ap_reg_pp0_iter5_bufo_addr_5_reg_4444[7 : 3];
ap_reg_pp0_iter7_bufo_addr_4_reg_4439[7 : 3] <= ap_reg_pp0_iter6_bufo_addr_4_reg_4439[7 : 3];
ap_reg_pp0_iter7_bufo_addr_5_reg_4444[7 : 3] <= ap_reg_pp0_iter6_bufo_addr_5_reg_4444[7 : 3];
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
ap_reg_pp0_iter2_bufo_addr_6_reg_4579[7 : 3] <= bufo_addr_6_reg_4579[7 : 3];
ap_reg_pp0_iter2_bufo_addr_7_reg_4584[7 : 3] <= bufo_addr_7_reg_4584[7 : 3];
ap_reg_pp0_iter3_bufo_addr_6_reg_4579[7 : 3] <= ap_reg_pp0_iter2_bufo_addr_6_reg_4579[7 : 3];
ap_reg_pp0_iter3_bufo_addr_7_reg_4584[7 : 3] <= ap_reg_pp0_iter2_bufo_addr_7_reg_4584[7 : 3];
ap_reg_pp0_iter3_tmp_19_2_0_2_reg_6669 <= tmp_19_2_0_2_reg_6669;
ap_reg_pp0_iter3_tmp_19_2_10_2_reg_6719 <= tmp_19_2_10_2_reg_6719;
ap_reg_pp0_iter3_tmp_19_2_11_2_reg_6724 <= tmp_19_2_11_2_reg_6724;
ap_reg_pp0_iter3_tmp_19_2_12_2_reg_6729 <= tmp_19_2_12_2_reg_6729;
ap_reg_pp0_iter3_tmp_19_2_1_2_reg_6674 <= tmp_19_2_1_2_reg_6674;
ap_reg_pp0_iter3_tmp_19_2_2_2_reg_6679 <= tmp_19_2_2_2_reg_6679;
ap_reg_pp0_iter3_tmp_19_2_3_2_reg_6684 <= tmp_19_2_3_2_reg_6684;
ap_reg_pp0_iter3_tmp_19_2_4_2_reg_6689 <= tmp_19_2_4_2_reg_6689;
ap_reg_pp0_iter3_tmp_19_2_5_2_reg_6694 <= tmp_19_2_5_2_reg_6694;
ap_reg_pp0_iter3_tmp_19_2_6_2_reg_6699 <= tmp_19_2_6_2_reg_6699;
ap_reg_pp0_iter3_tmp_19_2_7_2_reg_6704 <= tmp_19_2_7_2_reg_6704;
ap_reg_pp0_iter3_tmp_19_2_8_2_reg_6709 <= tmp_19_2_8_2_reg_6709;
ap_reg_pp0_iter3_tmp_19_2_9_2_reg_6714 <= tmp_19_2_9_2_reg_6714;
ap_reg_pp0_iter3_tmp_19_3_0_2_reg_6734 <= tmp_19_3_0_2_reg_6734;
ap_reg_pp0_iter3_tmp_19_3_10_2_reg_6784 <= tmp_19_3_10_2_reg_6784;
ap_reg_pp0_iter3_tmp_19_3_11_2_reg_6789 <= tmp_19_3_11_2_reg_6789;
ap_reg_pp0_iter3_tmp_19_3_12_2_reg_6794 <= tmp_19_3_12_2_reg_6794;
ap_reg_pp0_iter3_tmp_19_3_1_2_reg_6739 <= tmp_19_3_1_2_reg_6739;
ap_reg_pp0_iter3_tmp_19_3_2_2_reg_6744 <= tmp_19_3_2_2_reg_6744;
ap_reg_pp0_iter3_tmp_19_3_3_2_reg_6749 <= tmp_19_3_3_2_reg_6749;
ap_reg_pp0_iter3_tmp_19_3_4_2_reg_6754 <= tmp_19_3_4_2_reg_6754;
ap_reg_pp0_iter3_tmp_19_3_5_2_reg_6759 <= tmp_19_3_5_2_reg_6759;
ap_reg_pp0_iter3_tmp_19_3_6_2_reg_6764 <= tmp_19_3_6_2_reg_6764;
ap_reg_pp0_iter3_tmp_19_3_7_2_reg_6769 <= tmp_19_3_7_2_reg_6769;
ap_reg_pp0_iter3_tmp_19_3_8_2_reg_6774 <= tmp_19_3_8_2_reg_6774;
ap_reg_pp0_iter3_tmp_19_3_9_2_reg_6779 <= tmp_19_3_9_2_reg_6779;
ap_reg_pp0_iter3_tmp_19_4_0_2_reg_6799 <= tmp_19_4_0_2_reg_6799;
ap_reg_pp0_iter3_tmp_19_4_10_2_reg_6849 <= tmp_19_4_10_2_reg_6849;
ap_reg_pp0_iter3_tmp_19_4_11_2_reg_6854 <= tmp_19_4_11_2_reg_6854;
ap_reg_pp0_iter3_tmp_19_4_12_2_reg_6859 <= tmp_19_4_12_2_reg_6859;
ap_reg_pp0_iter3_tmp_19_4_1_2_reg_6804 <= tmp_19_4_1_2_reg_6804;
ap_reg_pp0_iter3_tmp_19_4_2_2_reg_6809 <= tmp_19_4_2_2_reg_6809;
ap_reg_pp0_iter3_tmp_19_4_3_2_reg_6814 <= tmp_19_4_3_2_reg_6814;
ap_reg_pp0_iter3_tmp_19_4_4_2_reg_6819 <= tmp_19_4_4_2_reg_6819;
ap_reg_pp0_iter3_tmp_19_4_5_2_reg_6824 <= tmp_19_4_5_2_reg_6824;
ap_reg_pp0_iter3_tmp_19_4_6_2_reg_6829 <= tmp_19_4_6_2_reg_6829;
ap_reg_pp0_iter3_tmp_19_4_7_2_reg_6834 <= tmp_19_4_7_2_reg_6834;
ap_reg_pp0_iter3_tmp_19_4_8_2_reg_6839 <= tmp_19_4_8_2_reg_6839;
ap_reg_pp0_iter3_tmp_19_4_9_2_reg_6844 <= tmp_19_4_9_2_reg_6844;
ap_reg_pp0_iter4_bufo_addr_6_reg_4579[7 : 3] <= ap_reg_pp0_iter3_bufo_addr_6_reg_4579[7 : 3];
ap_reg_pp0_iter4_bufo_addr_7_reg_4584[7 : 3] <= ap_reg_pp0_iter3_bufo_addr_7_reg_4584[7 : 3];
ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669 <= ap_reg_pp0_iter3_tmp_19_2_0_2_reg_6669;
ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719 <= ap_reg_pp0_iter3_tmp_19_2_10_2_reg_6719;
ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724 <= ap_reg_pp0_iter3_tmp_19_2_11_2_reg_6724;
ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729 <= ap_reg_pp0_iter3_tmp_19_2_12_2_reg_6729;
ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674 <= ap_reg_pp0_iter3_tmp_19_2_1_2_reg_6674;
ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679 <= ap_reg_pp0_iter3_tmp_19_2_2_2_reg_6679;
ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684 <= ap_reg_pp0_iter3_tmp_19_2_3_2_reg_6684;
ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689 <= ap_reg_pp0_iter3_tmp_19_2_4_2_reg_6689;
ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694 <= ap_reg_pp0_iter3_tmp_19_2_5_2_reg_6694;
ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699 <= ap_reg_pp0_iter3_tmp_19_2_6_2_reg_6699;
ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704 <= ap_reg_pp0_iter3_tmp_19_2_7_2_reg_6704;
ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709 <= ap_reg_pp0_iter3_tmp_19_2_8_2_reg_6709;
ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714 <= ap_reg_pp0_iter3_tmp_19_2_9_2_reg_6714;
ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734 <= ap_reg_pp0_iter3_tmp_19_3_0_2_reg_6734;
ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784 <= ap_reg_pp0_iter3_tmp_19_3_10_2_reg_6784;
ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789 <= ap_reg_pp0_iter3_tmp_19_3_11_2_reg_6789;
ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794 <= ap_reg_pp0_iter3_tmp_19_3_12_2_reg_6794;
ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739 <= ap_reg_pp0_iter3_tmp_19_3_1_2_reg_6739;
ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744 <= ap_reg_pp0_iter3_tmp_19_3_2_2_reg_6744;
ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749 <= ap_reg_pp0_iter3_tmp_19_3_3_2_reg_6749;
ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754 <= ap_reg_pp0_iter3_tmp_19_3_4_2_reg_6754;
ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759 <= ap_reg_pp0_iter3_tmp_19_3_5_2_reg_6759;
ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764 <= ap_reg_pp0_iter3_tmp_19_3_6_2_reg_6764;
ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769 <= ap_reg_pp0_iter3_tmp_19_3_7_2_reg_6769;
ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774 <= ap_reg_pp0_iter3_tmp_19_3_8_2_reg_6774;
ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779 <= ap_reg_pp0_iter3_tmp_19_3_9_2_reg_6779;
ap_reg_pp0_iter4_tmp_19_4_0_2_reg_6799 <= ap_reg_pp0_iter3_tmp_19_4_0_2_reg_6799;
ap_reg_pp0_iter4_tmp_19_4_10_2_reg_6849 <= ap_reg_pp0_iter3_tmp_19_4_10_2_reg_6849;
ap_reg_pp0_iter4_tmp_19_4_11_2_reg_6854 <= ap_reg_pp0_iter3_tmp_19_4_11_2_reg_6854;
ap_reg_pp0_iter4_tmp_19_4_12_2_reg_6859 <= ap_reg_pp0_iter3_tmp_19_4_12_2_reg_6859;
ap_reg_pp0_iter4_tmp_19_4_1_2_reg_6804 <= ap_reg_pp0_iter3_tmp_19_4_1_2_reg_6804;
ap_reg_pp0_iter4_tmp_19_4_2_2_reg_6809 <= ap_reg_pp0_iter3_tmp_19_4_2_2_reg_6809;
ap_reg_pp0_iter4_tmp_19_4_3_2_reg_6814 <= ap_reg_pp0_iter3_tmp_19_4_3_2_reg_6814;
ap_reg_pp0_iter4_tmp_19_4_4_2_reg_6819 <= ap_reg_pp0_iter3_tmp_19_4_4_2_reg_6819;
ap_reg_pp0_iter4_tmp_19_4_5_2_reg_6824 <= ap_reg_pp0_iter3_tmp_19_4_5_2_reg_6824;
ap_reg_pp0_iter4_tmp_19_4_6_2_reg_6829 <= ap_reg_pp0_iter3_tmp_19_4_6_2_reg_6829;
ap_reg_pp0_iter4_tmp_19_4_7_2_reg_6834 <= ap_reg_pp0_iter3_tmp_19_4_7_2_reg_6834;
ap_reg_pp0_iter4_tmp_19_4_8_2_reg_6839 <= ap_reg_pp0_iter3_tmp_19_4_8_2_reg_6839;
ap_reg_pp0_iter4_tmp_19_4_9_2_reg_6844 <= ap_reg_pp0_iter3_tmp_19_4_9_2_reg_6844;
ap_reg_pp0_iter5_bufo_addr_6_reg_4579[7 : 3] <= ap_reg_pp0_iter4_bufo_addr_6_reg_4579[7 : 3];
ap_reg_pp0_iter5_bufo_addr_7_reg_4584[7 : 3] <= ap_reg_pp0_iter4_bufo_addr_7_reg_4584[7 : 3];
ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799 <= ap_reg_pp0_iter4_tmp_19_4_0_2_reg_6799;
ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849 <= ap_reg_pp0_iter4_tmp_19_4_10_2_reg_6849;
ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854 <= ap_reg_pp0_iter4_tmp_19_4_11_2_reg_6854;
ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859 <= ap_reg_pp0_iter4_tmp_19_4_12_2_reg_6859;
ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804 <= ap_reg_pp0_iter4_tmp_19_4_1_2_reg_6804;
ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809 <= ap_reg_pp0_iter4_tmp_19_4_2_2_reg_6809;
ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814 <= ap_reg_pp0_iter4_tmp_19_4_3_2_reg_6814;
ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819 <= ap_reg_pp0_iter4_tmp_19_4_4_2_reg_6819;
ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824 <= ap_reg_pp0_iter4_tmp_19_4_5_2_reg_6824;
ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829 <= ap_reg_pp0_iter4_tmp_19_4_6_2_reg_6829;
ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834 <= ap_reg_pp0_iter4_tmp_19_4_7_2_reg_6834;
ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839 <= ap_reg_pp0_iter4_tmp_19_4_8_2_reg_6839;
ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844 <= ap_reg_pp0_iter4_tmp_19_4_9_2_reg_6844;
ap_reg_pp0_iter6_bufo_addr_6_reg_4579[7 : 3] <= ap_reg_pp0_iter5_bufo_addr_6_reg_4579[7 : 3];
ap_reg_pp0_iter6_bufo_addr_7_reg_4584[7 : 3] <= ap_reg_pp0_iter5_bufo_addr_7_reg_4584[7 : 3];
ap_reg_pp0_iter7_bufo_addr_6_reg_4579[7 : 3] <= ap_reg_pp0_iter6_bufo_addr_6_reg_4579[7 : 3];
ap_reg_pp0_iter7_bufo_addr_7_reg_4584[7 : 3] <= ap_reg_pp0_iter6_bufo_addr_7_reg_4584[7 : 3];
ap_reg_pp0_iter8_bufo_addr_6_reg_4579[7 : 3] <= ap_reg_pp0_iter7_bufo_addr_6_reg_4579[7 : 3];
ap_reg_pp0_iter8_bufo_addr_7_reg_4584[7 : 3] <= ap_reg_pp0_iter7_bufo_addr_7_reg_4584[7 : 3];
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854 <= tmp_19_0_0_1_reg_4854;
ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954 <= tmp_19_0_10_1_reg_4954;
ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964 <= tmp_19_0_11_1_reg_4964;
ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974 <= tmp_19_0_12_1_reg_4974;
ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864 <= tmp_19_0_1_1_reg_4864;
ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874 <= tmp_19_0_2_1_reg_4874;
ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884 <= tmp_19_0_3_1_reg_4884;
ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894 <= tmp_19_0_4_1_reg_4894;
ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904 <= tmp_19_0_5_1_reg_4904;
ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914 <= tmp_19_0_6_1_reg_4914;
ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924 <= tmp_19_0_7_1_reg_4924;
ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934 <= tmp_19_0_8_1_reg_4934;
ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944 <= tmp_19_0_9_1_reg_4944;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
ap_reg_pp0_iter3_tmp_19_5_0_2_reg_6864 <= tmp_19_5_0_2_reg_6864;
ap_reg_pp0_iter3_tmp_19_5_10_2_reg_6914 <= tmp_19_5_10_2_reg_6914;
ap_reg_pp0_iter3_tmp_19_5_11_2_reg_6919 <= tmp_19_5_11_2_reg_6919;
ap_reg_pp0_iter3_tmp_19_5_12_2_reg_6924 <= tmp_19_5_12_2_reg_6924;
ap_reg_pp0_iter3_tmp_19_5_1_2_reg_6869 <= tmp_19_5_1_2_reg_6869;
ap_reg_pp0_iter3_tmp_19_5_2_2_reg_6874 <= tmp_19_5_2_2_reg_6874;
ap_reg_pp0_iter3_tmp_19_5_3_2_reg_6879 <= tmp_19_5_3_2_reg_6879;
ap_reg_pp0_iter3_tmp_19_5_4_2_reg_6884 <= tmp_19_5_4_2_reg_6884;
ap_reg_pp0_iter3_tmp_19_5_5_2_reg_6889 <= tmp_19_5_5_2_reg_6889;
ap_reg_pp0_iter3_tmp_19_5_6_2_reg_6894 <= tmp_19_5_6_2_reg_6894;
ap_reg_pp0_iter3_tmp_19_5_7_2_reg_6899 <= tmp_19_5_7_2_reg_6899;
ap_reg_pp0_iter3_tmp_19_5_8_2_reg_6904 <= tmp_19_5_8_2_reg_6904;
ap_reg_pp0_iter3_tmp_19_5_9_2_reg_6909 <= tmp_19_5_9_2_reg_6909;
ap_reg_pp0_iter3_tmp_19_6_0_2_reg_6929 <= tmp_19_6_0_2_reg_6929;
ap_reg_pp0_iter3_tmp_19_6_10_2_reg_6979 <= tmp_19_6_10_2_reg_6979;
ap_reg_pp0_iter3_tmp_19_6_11_2_reg_6984 <= tmp_19_6_11_2_reg_6984;
ap_reg_pp0_iter3_tmp_19_6_12_2_reg_6989 <= tmp_19_6_12_2_reg_6989;
ap_reg_pp0_iter3_tmp_19_6_1_2_reg_6934 <= tmp_19_6_1_2_reg_6934;
ap_reg_pp0_iter3_tmp_19_6_2_2_reg_6939 <= tmp_19_6_2_2_reg_6939;
ap_reg_pp0_iter3_tmp_19_6_3_2_reg_6944 <= tmp_19_6_3_2_reg_6944;
ap_reg_pp0_iter3_tmp_19_6_4_2_reg_6949 <= tmp_19_6_4_2_reg_6949;
ap_reg_pp0_iter3_tmp_19_6_5_2_reg_6954 <= tmp_19_6_5_2_reg_6954;
ap_reg_pp0_iter3_tmp_19_6_6_2_reg_6959 <= tmp_19_6_6_2_reg_6959;
ap_reg_pp0_iter3_tmp_19_6_7_2_reg_6964 <= tmp_19_6_7_2_reg_6964;
ap_reg_pp0_iter3_tmp_19_6_8_2_reg_6969 <= tmp_19_6_8_2_reg_6969;
ap_reg_pp0_iter3_tmp_19_6_9_2_reg_6974 <= tmp_19_6_9_2_reg_6974;
ap_reg_pp0_iter3_tmp_19_7_0_2_reg_6994 <= tmp_19_7_0_2_reg_6994;
ap_reg_pp0_iter3_tmp_19_7_10_2_reg_7044 <= tmp_19_7_10_2_reg_7044;
ap_reg_pp0_iter3_tmp_19_7_11_2_reg_7049 <= tmp_19_7_11_2_reg_7049;
ap_reg_pp0_iter3_tmp_19_7_12_2_reg_7054 <= tmp_19_7_12_2_reg_7054;
ap_reg_pp0_iter3_tmp_19_7_1_2_reg_6999 <= tmp_19_7_1_2_reg_6999;
ap_reg_pp0_iter3_tmp_19_7_2_2_reg_7004 <= tmp_19_7_2_2_reg_7004;
ap_reg_pp0_iter3_tmp_19_7_3_2_reg_7009 <= tmp_19_7_3_2_reg_7009;
ap_reg_pp0_iter3_tmp_19_7_4_2_reg_7014 <= tmp_19_7_4_2_reg_7014;
ap_reg_pp0_iter3_tmp_19_7_5_2_reg_7019 <= tmp_19_7_5_2_reg_7019;
ap_reg_pp0_iter3_tmp_19_7_6_2_reg_7024 <= tmp_19_7_6_2_reg_7024;
ap_reg_pp0_iter3_tmp_19_7_7_2_reg_7029 <= tmp_19_7_7_2_reg_7029;
ap_reg_pp0_iter3_tmp_19_7_8_2_reg_7034 <= tmp_19_7_8_2_reg_7034;
ap_reg_pp0_iter3_tmp_19_7_9_2_reg_7039 <= tmp_19_7_9_2_reg_7039;
ap_reg_pp0_iter4_tmp_19_5_0_2_reg_6864 <= ap_reg_pp0_iter3_tmp_19_5_0_2_reg_6864;
ap_reg_pp0_iter4_tmp_19_5_10_2_reg_6914 <= ap_reg_pp0_iter3_tmp_19_5_10_2_reg_6914;
ap_reg_pp0_iter4_tmp_19_5_11_2_reg_6919 <= ap_reg_pp0_iter3_tmp_19_5_11_2_reg_6919;
ap_reg_pp0_iter4_tmp_19_5_12_2_reg_6924 <= ap_reg_pp0_iter3_tmp_19_5_12_2_reg_6924;
ap_reg_pp0_iter4_tmp_19_5_1_2_reg_6869 <= ap_reg_pp0_iter3_tmp_19_5_1_2_reg_6869;
ap_reg_pp0_iter4_tmp_19_5_2_2_reg_6874 <= ap_reg_pp0_iter3_tmp_19_5_2_2_reg_6874;
ap_reg_pp0_iter4_tmp_19_5_3_2_reg_6879 <= ap_reg_pp0_iter3_tmp_19_5_3_2_reg_6879;
ap_reg_pp0_iter4_tmp_19_5_4_2_reg_6884 <= ap_reg_pp0_iter3_tmp_19_5_4_2_reg_6884;
ap_reg_pp0_iter4_tmp_19_5_5_2_reg_6889 <= ap_reg_pp0_iter3_tmp_19_5_5_2_reg_6889;
ap_reg_pp0_iter4_tmp_19_5_6_2_reg_6894 <= ap_reg_pp0_iter3_tmp_19_5_6_2_reg_6894;
ap_reg_pp0_iter4_tmp_19_5_7_2_reg_6899 <= ap_reg_pp0_iter3_tmp_19_5_7_2_reg_6899;
ap_reg_pp0_iter4_tmp_19_5_8_2_reg_6904 <= ap_reg_pp0_iter3_tmp_19_5_8_2_reg_6904;
ap_reg_pp0_iter4_tmp_19_5_9_2_reg_6909 <= ap_reg_pp0_iter3_tmp_19_5_9_2_reg_6909;
ap_reg_pp0_iter4_tmp_19_6_0_2_reg_6929 <= ap_reg_pp0_iter3_tmp_19_6_0_2_reg_6929;
ap_reg_pp0_iter4_tmp_19_6_10_2_reg_6979 <= ap_reg_pp0_iter3_tmp_19_6_10_2_reg_6979;
ap_reg_pp0_iter4_tmp_19_6_11_2_reg_6984 <= ap_reg_pp0_iter3_tmp_19_6_11_2_reg_6984;
ap_reg_pp0_iter4_tmp_19_6_12_2_reg_6989 <= ap_reg_pp0_iter3_tmp_19_6_12_2_reg_6989;
ap_reg_pp0_iter4_tmp_19_6_1_2_reg_6934 <= ap_reg_pp0_iter3_tmp_19_6_1_2_reg_6934;
ap_reg_pp0_iter4_tmp_19_6_2_2_reg_6939 <= ap_reg_pp0_iter3_tmp_19_6_2_2_reg_6939;
ap_reg_pp0_iter4_tmp_19_6_3_2_reg_6944 <= ap_reg_pp0_iter3_tmp_19_6_3_2_reg_6944;
ap_reg_pp0_iter4_tmp_19_6_4_2_reg_6949 <= ap_reg_pp0_iter3_tmp_19_6_4_2_reg_6949;
ap_reg_pp0_iter4_tmp_19_6_5_2_reg_6954 <= ap_reg_pp0_iter3_tmp_19_6_5_2_reg_6954;
ap_reg_pp0_iter4_tmp_19_6_6_2_reg_6959 <= ap_reg_pp0_iter3_tmp_19_6_6_2_reg_6959;
ap_reg_pp0_iter4_tmp_19_6_7_2_reg_6964 <= ap_reg_pp0_iter3_tmp_19_6_7_2_reg_6964;
ap_reg_pp0_iter4_tmp_19_6_8_2_reg_6969 <= ap_reg_pp0_iter3_tmp_19_6_8_2_reg_6969;
ap_reg_pp0_iter4_tmp_19_6_9_2_reg_6974 <= ap_reg_pp0_iter3_tmp_19_6_9_2_reg_6974;
ap_reg_pp0_iter4_tmp_19_7_0_2_reg_6994 <= ap_reg_pp0_iter3_tmp_19_7_0_2_reg_6994;
ap_reg_pp0_iter4_tmp_19_7_10_2_reg_7044 <= ap_reg_pp0_iter3_tmp_19_7_10_2_reg_7044;
ap_reg_pp0_iter4_tmp_19_7_11_2_reg_7049 <= ap_reg_pp0_iter3_tmp_19_7_11_2_reg_7049;
ap_reg_pp0_iter4_tmp_19_7_12_2_reg_7054 <= ap_reg_pp0_iter3_tmp_19_7_12_2_reg_7054;
ap_reg_pp0_iter4_tmp_19_7_1_2_reg_6999 <= ap_reg_pp0_iter3_tmp_19_7_1_2_reg_6999;
ap_reg_pp0_iter4_tmp_19_7_2_2_reg_7004 <= ap_reg_pp0_iter3_tmp_19_7_2_2_reg_7004;
ap_reg_pp0_iter4_tmp_19_7_3_2_reg_7009 <= ap_reg_pp0_iter3_tmp_19_7_3_2_reg_7009;
ap_reg_pp0_iter4_tmp_19_7_4_2_reg_7014 <= ap_reg_pp0_iter3_tmp_19_7_4_2_reg_7014;
ap_reg_pp0_iter4_tmp_19_7_5_2_reg_7019 <= ap_reg_pp0_iter3_tmp_19_7_5_2_reg_7019;
ap_reg_pp0_iter4_tmp_19_7_6_2_reg_7024 <= ap_reg_pp0_iter3_tmp_19_7_6_2_reg_7024;
ap_reg_pp0_iter4_tmp_19_7_7_2_reg_7029 <= ap_reg_pp0_iter3_tmp_19_7_7_2_reg_7029;
ap_reg_pp0_iter4_tmp_19_7_8_2_reg_7034 <= ap_reg_pp0_iter3_tmp_19_7_8_2_reg_7034;
ap_reg_pp0_iter4_tmp_19_7_9_2_reg_7039 <= ap_reg_pp0_iter3_tmp_19_7_9_2_reg_7039;
ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864 <= ap_reg_pp0_iter4_tmp_19_5_0_2_reg_6864;
ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914 <= ap_reg_pp0_iter4_tmp_19_5_10_2_reg_6914;
ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919 <= ap_reg_pp0_iter4_tmp_19_5_11_2_reg_6919;
ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924 <= ap_reg_pp0_iter4_tmp_19_5_12_2_reg_6924;
ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869 <= ap_reg_pp0_iter4_tmp_19_5_1_2_reg_6869;
ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874 <= ap_reg_pp0_iter4_tmp_19_5_2_2_reg_6874;
ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879 <= ap_reg_pp0_iter4_tmp_19_5_3_2_reg_6879;
ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884 <= ap_reg_pp0_iter4_tmp_19_5_4_2_reg_6884;
ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889 <= ap_reg_pp0_iter4_tmp_19_5_5_2_reg_6889;
ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894 <= ap_reg_pp0_iter4_tmp_19_5_6_2_reg_6894;
ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899 <= ap_reg_pp0_iter4_tmp_19_5_7_2_reg_6899;
ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904 <= ap_reg_pp0_iter4_tmp_19_5_8_2_reg_6904;
ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909 <= ap_reg_pp0_iter4_tmp_19_5_9_2_reg_6909;
ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929 <= ap_reg_pp0_iter4_tmp_19_6_0_2_reg_6929;
ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979 <= ap_reg_pp0_iter4_tmp_19_6_10_2_reg_6979;
ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984 <= ap_reg_pp0_iter4_tmp_19_6_11_2_reg_6984;
ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989 <= ap_reg_pp0_iter4_tmp_19_6_12_2_reg_6989;
ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934 <= ap_reg_pp0_iter4_tmp_19_6_1_2_reg_6934;
ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939 <= ap_reg_pp0_iter4_tmp_19_6_2_2_reg_6939;
ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944 <= ap_reg_pp0_iter4_tmp_19_6_3_2_reg_6944;
ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949 <= ap_reg_pp0_iter4_tmp_19_6_4_2_reg_6949;
ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954 <= ap_reg_pp0_iter4_tmp_19_6_5_2_reg_6954;
ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959 <= ap_reg_pp0_iter4_tmp_19_6_6_2_reg_6959;
ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964 <= ap_reg_pp0_iter4_tmp_19_6_7_2_reg_6964;
ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969 <= ap_reg_pp0_iter4_tmp_19_6_8_2_reg_6969;
ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974 <= ap_reg_pp0_iter4_tmp_19_6_9_2_reg_6974;
ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994 <= ap_reg_pp0_iter4_tmp_19_7_0_2_reg_6994;
ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044 <= ap_reg_pp0_iter4_tmp_19_7_10_2_reg_7044;
ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049 <= ap_reg_pp0_iter4_tmp_19_7_11_2_reg_7049;
ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054 <= ap_reg_pp0_iter4_tmp_19_7_12_2_reg_7054;
ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999 <= ap_reg_pp0_iter4_tmp_19_7_1_2_reg_6999;
ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004 <= ap_reg_pp0_iter4_tmp_19_7_2_2_reg_7004;
ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009 <= ap_reg_pp0_iter4_tmp_19_7_3_2_reg_7009;
ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014 <= ap_reg_pp0_iter4_tmp_19_7_4_2_reg_7014;
ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019 <= ap_reg_pp0_iter4_tmp_19_7_5_2_reg_7019;
ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024 <= ap_reg_pp0_iter4_tmp_19_7_6_2_reg_7024;
ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029 <= ap_reg_pp0_iter4_tmp_19_7_7_2_reg_7029;
ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034 <= ap_reg_pp0_iter4_tmp_19_7_8_2_reg_7034;
ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039 <= ap_reg_pp0_iter4_tmp_19_7_9_2_reg_7039;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage7_11001 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_0_load_1_reg_3931 <= bufi_0_Dout_B;
bufi_0_load_reg_3693 <= bufi_0_Dout_A;
bufi_1_load_1_reg_3948 <= bufi_1_Dout_B;
bufi_1_load_reg_3718 <= bufi_1_Dout_A;
bufi_2_load_1_reg_3965 <= bufi_2_Dout_B;
bufi_2_load_reg_3735 <= bufi_2_Dout_A;
bufw_0_load_1_reg_3710 <= bufw_0_Dout_B;
bufw_0_load_reg_3686 <= bufw_0_Dout_A;
bufw_10_load_1_reg_3894 <= bufw_10_Dout_B;
bufw_10_load_reg_3887 <= bufw_10_Dout_A;
bufw_11_load_1_reg_3909 <= bufw_11_Dout_B;
bufw_11_load_reg_3902 <= bufw_11_Dout_A;
bufw_12_load_1_reg_3924 <= bufw_12_Dout_B;
bufw_12_load_reg_3917 <= bufw_12_Dout_A;
bufw_1_load_1_reg_3759 <= bufw_1_Dout_B;
bufw_1_load_reg_3752 <= bufw_1_Dout_A;
bufw_2_load_1_reg_3774 <= bufw_2_Dout_B;
bufw_2_load_reg_3767 <= bufw_2_Dout_A;
bufw_3_load_1_reg_3789 <= bufw_3_Dout_B;
bufw_3_load_reg_3782 <= bufw_3_Dout_A;
bufw_4_load_1_reg_3804 <= bufw_4_Dout_B;
bufw_4_load_reg_3797 <= bufw_4_Dout_A;
bufw_5_load_1_reg_3819 <= bufw_5_Dout_B;
bufw_5_load_reg_3812 <= bufw_5_Dout_A;
bufw_6_load_1_reg_3834 <= bufw_6_Dout_B;
bufw_6_load_reg_3827 <= bufw_6_Dout_A;
bufw_7_load_1_reg_3849 <= bufw_7_Dout_B;
bufw_7_load_reg_3842 <= bufw_7_Dout_A;
bufw_8_load_1_reg_3864 <= bufw_8_Dout_B;
bufw_8_load_reg_3857 <= bufw_8_Dout_A;
bufw_9_load_1_reg_3879 <= bufw_9_Dout_B;
bufw_9_load_reg_3872 <= bufw_9_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten1_reg_3176 == 1'd0) & (ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
bufi_0_load_2_reg_4103 <= bufi_0_Dout_A;
bufi_0_load_3_reg_4154 <= bufi_0_Dout_B;
bufi_1_load_2_reg_4120 <= bufi_1_Dout_A;
bufi_1_load_3_reg_4171 <= bufi_1_Dout_B;
bufi_2_load_2_reg_4137 <= bufi_2_Dout_A;
bufi_2_load_3_reg_4188 <= bufi_2_Dout_B;
bufw_0_load_2_reg_4012 <= bufw_0_Dout_A;
bufw_10_load_2_reg_4082 <= bufw_10_Dout_A;
bufw_11_load_2_reg_4089 <= bufw_11_Dout_A;
bufw_12_load_2_reg_4096 <= bufw_12_Dout_A;
bufw_1_load_2_reg_4019 <= bufw_1_Dout_A;
bufw_2_load_2_reg_4026 <= bufw_2_Dout_A;
bufw_3_load_2_reg_4033 <= bufw_3_Dout_A;
bufw_4_load_2_reg_4040 <= bufw_4_Dout_A;
bufw_5_load_2_reg_4047 <= bufw_5_Dout_A;
bufw_6_load_2_reg_4054 <= bufw_6_Dout_A;
bufw_7_load_2_reg_4061 <= bufw_7_Dout_A;
bufw_8_load_2_reg_4068 <= bufw_8_Dout_A;
bufw_9_load_2_reg_4075 <= bufw_9_Dout_A;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage1_11001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
bufi_0_load_4_reg_4205 <= bufi_0_Dout_A;
bufi_0_load_5_reg_4256 <= bufi_0_Dout_B;
bufi_1_load_4_reg_4222 <= bufi_1_Dout_A;
bufi_1_load_5_reg_4273 <= bufi_1_Dout_B;
bufi_2_load_4_reg_4239 <= bufi_2_Dout_A;
bufi_2_load_5_reg_4290 <= bufi_2_Dout_B;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage2_11001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
bufi_0_load_6_reg_4327 <= bufi_0_Dout_A;
bufi_0_load_7_reg_4378 <= bufi_0_Dout_B;
bufi_1_load_6_reg_4344 <= bufi_1_Dout_A;
bufi_1_load_7_reg_4395 <= bufi_1_Dout_B;
bufi_2_load_6_reg_4361 <= bufi_2_Dout_A;
bufi_2_load_7_reg_4412 <= bufi_2_Dout_B;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage2_11001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
bufo_addr_1_reg_4322[7 : 3] <= tmp_336_fu_2040_p3[7 : 3];
bufo_addr_reg_4317[7 : 3] <= tmp_334_fu_2029_p1[7 : 3];
tmp_333_reg_4307[7 : 3] <= tmp_333_fu_2022_p3[7 : 3];
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage3_11001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
bufo_addr_2_reg_4429[7 : 3] <= tmp_338_fu_2054_p3[7 : 3];
bufo_addr_3_reg_4434[7 : 3] <= tmp_340_fu_2068_p3[7 : 3];
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage4_11001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
bufo_addr_4_reg_4439[7 : 3] <= tmp_342_fu_2082_p3[7 : 3];
bufo_addr_5_reg_4444[7 : 3] <= tmp_344_fu_2096_p3[7 : 3];
tmp_350_reg_4449 <= tmp_350_fu_2105_p1;
tmp_352_reg_4514 <= tmp_352_fu_2109_p1;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage5_11001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufo_addr_6_reg_4579[7 : 3] <= tmp_346_fu_2118_p3[7 : 3];
bufo_addr_7_reg_4584[7 : 3] <= tmp_348_fu_2132_p3[7 : 3];
tmp_353_reg_4589 <= tmp_353_fu_2141_p1;
tmp_354_reg_4654 <= tmp_354_fu_2145_p1;
end
end
always @ (posedge ap_clk) begin
if (((exitcond_flatten1_fu_1541_p2 == 1'd0) & (ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
exitcond_flatten_reg_3190 <= exitcond_flatten_fu_1559_p2;
i_1_reg_3185 <= i_1_fu_1553_p2;
indvar_flatten_op_reg_3211 <= indvar_flatten_op_fu_1571_p2;
tmp_5_reg_3206 <= tmp_5_fu_1565_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
indvar_flatten_next1_reg_3180 <= indvar_flatten_next1_fu_1547_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage1_11001 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
indvar_flatten_next_reg_3252 <= indvar_flatten_next_fu_1613_p3;
tmp_1_mid2_v_reg_3225 <= tmp_1_mid2_v_fu_1584_p3;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage2_11001 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
j_1_reg_3264 <= j_1_fu_1642_p2;
tmp_1_reg_3257 <= tmp_1_fu_1633_p2;
tmp_s_reg_3270 <= tmp_s_fu_1647_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage1_11001 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
j_mid_reg_3216 <= j_mid_fu_1577_p3;
row_b_mid2_reg_3245 <= row_b_mid2_fu_1605_p3;
tmp_7_mid_reg_3233 <= tmp_7_mid_fu_1595_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage2_11001 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
row_b_1_reg_3276 <= row_b_1_fu_1652_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage5_11001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
tmp_102_reg_4609 <= {{grp_fu_1285_p1[159:128]}};
tmp_105_reg_4614 <= {{grp_fu_1295_p1[191:160]}};
tmp_108_reg_4619 <= {{grp_fu_1305_p1[223:192]}};
tmp_111_reg_4624 <= {{grp_fu_1315_p1[255:224]}};
tmp_114_reg_4629 <= {{grp_fu_1325_p1[287:256]}};
tmp_117_reg_4634 <= {{grp_fu_1335_p1[319:288]}};
tmp_120_reg_4639 <= {{grp_fu_1345_p1[351:320]}};
tmp_123_reg_4644 <= {{grp_fu_1355_p1[383:352]}};
tmp_126_reg_4649 <= {{grp_fu_1365_p1[415:384]}};
tmp_133_reg_4659 <= {{grp_fu_1375_p1[63:32]}};
tmp_136_reg_4664 <= {{grp_fu_1385_p1[95:64]}};
tmp_139_reg_4669 <= {{grp_fu_1395_p1[127:96]}};
tmp_142_reg_4674 <= {{grp_fu_1405_p1[159:128]}};
tmp_145_reg_4679 <= {{grp_fu_1415_p1[191:160]}};
tmp_148_reg_4684 <= {{grp_fu_1425_p1[223:192]}};
tmp_151_reg_4689 <= {{grp_fu_1435_p1[255:224]}};
tmp_154_reg_4694 <= {{grp_fu_1445_p1[287:256]}};
tmp_157_reg_4699 <= {{grp_fu_1455_p1[319:288]}};
tmp_160_reg_4704 <= {{grp_fu_1465_p1[351:320]}};
tmp_163_reg_4709 <= {{grp_fu_1475_p1[383:352]}};
tmp_166_reg_4714 <= {{grp_fu_1485_p1[415:384]}};
tmp_93_reg_4594 <= {{grp_fu_1255_p1[63:32]}};
tmp_96_reg_4599 <= {{grp_fu_1265_p1[95:64]}};
tmp_99_reg_4604 <= {{grp_fu_1275_p1[127:96]}};
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage3_11001 == 1'b0) & (tmp_7_mid_reg_3233 == 1'd1) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
tmp_12_1_mid1_reg_3294 <= tmp_12_1_mid1_fu_1667_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage4_11001 == 1'b0) & (tmp_7_mid_reg_3233 == 1'd1) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
tmp_12_2_mid1_reg_3331 <= tmp_12_2_mid1_fu_1748_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage5_11001 == 1'b0) & (tmp_7_mid_reg_3233 == 1'd1) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
tmp_12_4_mid1_reg_3481 <= tmp_12_4_mid1_fu_1840_p2;
tmp_12_5_mid1_reg_3486 <= tmp_12_5_mid1_fu_1846_p2;
tmp_12_6_mid1_reg_3491 <= tmp_12_6_mid1_fu_1852_p2;
tmp_12_7_mid1_reg_3496 <= tmp_12_7_mid1_fu_1858_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage4_11001 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
tmp_130_reg_3336 <= tmp_130_fu_1753_p2;
tmp_170_reg_3341 <= tmp_170_fu_1758_p2;
tmp_3_reg_3311 <= tmp_3_fu_1706_p2;
tmp_5_mid2_cast2_reg_3316[2 : 0] <= tmp_5_mid2_cast2_fu_1721_p1[2 : 0];
tmp_6_reg_3321 <= tmp_6_fu_1727_p2;
tmp_8_reg_3326 <= tmp_8_fu_1732_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage4_11001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
tmp_13_reg_4454 <= {{grp_fu_1255_p1[63:32]}};
tmp_16_reg_4459 <= {{grp_fu_1265_p1[95:64]}};
tmp_19_reg_4464 <= {{grp_fu_1275_p1[127:96]}};
tmp_22_reg_4469 <= {{grp_fu_1285_p1[159:128]}};
tmp_25_reg_4474 <= {{grp_fu_1295_p1[191:160]}};
tmp_28_reg_4479 <= {{grp_fu_1305_p1[223:192]}};
tmp_31_reg_4484 <= {{grp_fu_1315_p1[255:224]}};
tmp_34_reg_4489 <= {{grp_fu_1325_p1[287:256]}};
tmp_37_reg_4494 <= {{grp_fu_1335_p1[319:288]}};
tmp_40_reg_4499 <= {{grp_fu_1345_p1[351:320]}};
tmp_43_reg_4504 <= {{grp_fu_1355_p1[383:352]}};
tmp_46_reg_4509 <= {{grp_fu_1365_p1[415:384]}};
tmp_53_reg_4519 <= {{grp_fu_1375_p1[63:32]}};
tmp_56_reg_4524 <= {{grp_fu_1385_p1[95:64]}};
tmp_59_reg_4529 <= {{grp_fu_1395_p1[127:96]}};
tmp_62_reg_4534 <= {{grp_fu_1405_p1[159:128]}};
tmp_65_reg_4539 <= {{grp_fu_1415_p1[191:160]}};
tmp_68_reg_4544 <= {{grp_fu_1425_p1[223:192]}};
tmp_71_reg_4549 <= {{grp_fu_1435_p1[255:224]}};
tmp_74_reg_4554 <= {{grp_fu_1445_p1[287:256]}};
tmp_77_reg_4559 <= {{grp_fu_1455_p1[319:288]}};
tmp_80_reg_4564 <= {{grp_fu_1465_p1[351:320]}};
tmp_83_reg_4569 <= {{grp_fu_1475_p1[383:352]}};
tmp_86_reg_4574 <= {{grp_fu_1485_p1[415:384]}};
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage6_11001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
tmp_173_reg_4724 <= {{grp_fu_1255_p1[63:32]}};
tmp_176_reg_4729 <= {{grp_fu_1265_p1[95:64]}};
tmp_179_reg_4734 <= {{grp_fu_1275_p1[127:96]}};
tmp_182_reg_4739 <= {{grp_fu_1285_p1[159:128]}};
tmp_185_reg_4744 <= {{grp_fu_1295_p1[191:160]}};
tmp_188_reg_4749 <= {{grp_fu_1305_p1[223:192]}};
tmp_191_reg_4754 <= {{grp_fu_1315_p1[255:224]}};
tmp_194_reg_4759 <= {{grp_fu_1325_p1[287:256]}};
tmp_197_reg_4764 <= {{grp_fu_1335_p1[319:288]}};
tmp_200_reg_4769 <= {{grp_fu_1345_p1[351:320]}};
tmp_203_reg_4774 <= {{grp_fu_1355_p1[383:352]}};
tmp_206_reg_4779 <= {{grp_fu_1365_p1[415:384]}};
tmp_213_reg_4789 <= {{grp_fu_1375_p1[63:32]}};
tmp_216_reg_4794 <= {{grp_fu_1385_p1[95:64]}};
tmp_219_reg_4799 <= {{grp_fu_1395_p1[127:96]}};
tmp_222_reg_4804 <= {{grp_fu_1405_p1[159:128]}};
tmp_225_reg_4809 <= {{grp_fu_1415_p1[191:160]}};
tmp_228_reg_4814 <= {{grp_fu_1425_p1[223:192]}};
tmp_231_reg_4819 <= {{grp_fu_1435_p1[255:224]}};
tmp_234_reg_4824 <= {{grp_fu_1445_p1[287:256]}};
tmp_237_reg_4829 <= {{grp_fu_1455_p1[319:288]}};
tmp_240_reg_4834 <= {{grp_fu_1465_p1[351:320]}};
tmp_243_reg_4839 <= {{grp_fu_1475_p1[383:352]}};
tmp_246_reg_4844 <= {{grp_fu_1485_p1[415:384]}};
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage7_11001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
tmp_19_0_0_1_reg_4854 <= grp_fu_1103_p2;
tmp_19_0_10_1_reg_4954 <= grp_fu_1183_p2;
tmp_19_0_10_reg_4959 <= grp_fu_1187_p2;
tmp_19_0_11_1_reg_4964 <= grp_fu_1191_p2;
tmp_19_0_11_reg_4969 <= grp_fu_1195_p2;
tmp_19_0_12_1_reg_4974 <= grp_fu_1199_p2;
tmp_19_0_1_1_reg_4864 <= grp_fu_1111_p2;
tmp_19_0_1_reg_4859 <= grp_fu_1107_p2;
tmp_19_0_2_1_reg_4874 <= grp_fu_1119_p2;
tmp_19_0_2_reg_4869 <= grp_fu_1115_p2;
tmp_19_0_3_1_reg_4884 <= grp_fu_1127_p2;
tmp_19_0_3_reg_4879 <= grp_fu_1123_p2;
tmp_19_0_4_1_reg_4894 <= grp_fu_1135_p2;
tmp_19_0_4_reg_4889 <= grp_fu_1131_p2;
tmp_19_0_5_1_reg_4904 <= grp_fu_1143_p2;
tmp_19_0_5_reg_4899 <= grp_fu_1139_p2;
tmp_19_0_6_1_reg_4914 <= grp_fu_1151_p2;
tmp_19_0_6_reg_4909 <= grp_fu_1147_p2;
tmp_19_0_7_1_reg_4924 <= grp_fu_1159_p2;
tmp_19_0_7_reg_4919 <= grp_fu_1155_p2;
tmp_19_0_8_1_reg_4934 <= grp_fu_1167_p2;
tmp_19_0_8_reg_4929 <= grp_fu_1163_p2;
tmp_19_0_9_1_reg_4944 <= grp_fu_1175_p2;
tmp_19_0_9_reg_4939 <= grp_fu_1171_p2;
tmp_19_0_s_reg_4949 <= grp_fu_1179_p2;
tmp_19_1_10_reg_5034 <= grp_fu_1247_p2;
tmp_19_1_11_reg_5039 <= grp_fu_1251_p2;
tmp_19_1_1_reg_4984 <= grp_fu_1207_p2;
tmp_19_1_2_reg_4989 <= grp_fu_1211_p2;
tmp_19_1_3_reg_4994 <= grp_fu_1215_p2;
tmp_19_1_4_reg_4999 <= grp_fu_1219_p2;
tmp_19_1_5_reg_5004 <= grp_fu_1223_p2;
tmp_19_1_6_reg_5009 <= grp_fu_1227_p2;
tmp_19_1_7_reg_5014 <= grp_fu_1231_p2;
tmp_19_1_8_reg_5019 <= grp_fu_1235_p2;
tmp_19_1_9_reg_5024 <= grp_fu_1239_p2;
tmp_19_1_reg_4979 <= grp_fu_1203_p2;
tmp_19_1_s_reg_5029 <= grp_fu_1243_p2;
tmp_253_reg_5049 <= {{grp_fu_1255_p1[63:32]}};
tmp_256_reg_5054 <= {{grp_fu_1265_p1[95:64]}};
tmp_259_reg_5059 <= {{grp_fu_1275_p1[127:96]}};
tmp_262_reg_5064 <= {{grp_fu_1285_p1[159:128]}};
tmp_265_reg_5069 <= {{grp_fu_1295_p1[191:160]}};
tmp_268_reg_5074 <= {{grp_fu_1305_p1[223:192]}};
tmp_271_reg_5079 <= {{grp_fu_1315_p1[255:224]}};
tmp_274_reg_5084 <= {{grp_fu_1325_p1[287:256]}};
tmp_277_reg_5089 <= {{grp_fu_1335_p1[319:288]}};
tmp_280_reg_5094 <= {{grp_fu_1345_p1[351:320]}};
tmp_283_reg_5099 <= {{grp_fu_1355_p1[383:352]}};
tmp_286_reg_5104 <= {{grp_fu_1365_p1[415:384]}};
tmp_293_reg_5114 <= {{grp_fu_1375_p1[63:32]}};
tmp_296_reg_5119 <= {{grp_fu_1385_p1[95:64]}};
tmp_299_reg_5124 <= {{grp_fu_1395_p1[127:96]}};
tmp_302_reg_5129 <= {{grp_fu_1405_p1[159:128]}};
tmp_305_reg_5134 <= {{grp_fu_1415_p1[191:160]}};
tmp_308_reg_5139 <= {{grp_fu_1425_p1[223:192]}};
tmp_311_reg_5144 <= {{grp_fu_1435_p1[255:224]}};
tmp_314_reg_5149 <= {{grp_fu_1445_p1[287:256]}};
tmp_317_reg_5154 <= {{grp_fu_1455_p1[319:288]}};
tmp_320_reg_5159 <= {{grp_fu_1465_p1[351:320]}};
tmp_323_reg_5164 <= {{grp_fu_1475_p1[383:352]}};
tmp_326_reg_5169 <= {{grp_fu_1485_p1[415:384]}};
tmp_349_reg_4849 <= grp_fu_1099_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage4_11001 == 1'b0) & (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
tmp_19_0_0_2_reg_6474 <= grp_fu_1099_p2;
tmp_19_0_10_2_reg_6524 <= grp_fu_1139_p2;
tmp_19_0_11_2_reg_6529 <= grp_fu_1143_p2;
tmp_19_0_12_2_reg_6534 <= grp_fu_1147_p2;
tmp_19_0_1_2_reg_6479 <= grp_fu_1103_p2;
tmp_19_0_2_2_reg_6484 <= grp_fu_1107_p2;
tmp_19_0_3_2_reg_6489 <= grp_fu_1111_p2;
tmp_19_0_4_2_reg_6494 <= grp_fu_1115_p2;
tmp_19_0_5_2_reg_6499 <= grp_fu_1119_p2;
tmp_19_0_6_2_reg_6504 <= grp_fu_1123_p2;
tmp_19_0_7_2_reg_6509 <= grp_fu_1127_p2;
tmp_19_0_8_2_reg_6514 <= grp_fu_1131_p2;
tmp_19_0_9_2_reg_6519 <= grp_fu_1135_p2;
tmp_19_1_0_2_reg_6539 <= grp_fu_1151_p2;
tmp_19_1_10_2_reg_6589 <= grp_fu_1191_p2;
tmp_19_1_11_2_reg_6594 <= grp_fu_1195_p2;
tmp_19_1_12_2_reg_6599 <= grp_fu_1199_p2;
tmp_19_1_1_2_reg_6544 <= grp_fu_1155_p2;
tmp_19_1_2_2_reg_6549 <= grp_fu_1159_p2;
tmp_19_1_3_2_reg_6554 <= grp_fu_1163_p2;
tmp_19_1_4_2_reg_6559 <= grp_fu_1167_p2;
tmp_19_1_5_2_reg_6564 <= grp_fu_1171_p2;
tmp_19_1_6_2_reg_6569 <= grp_fu_1175_p2;
tmp_19_1_7_2_reg_6574 <= grp_fu_1179_p2;
tmp_19_1_8_2_reg_6579 <= grp_fu_1183_p2;
tmp_19_1_9_2_reg_6584 <= grp_fu_1187_p2;
tmp_19_7_0_1_reg_6604 <= grp_fu_1203_p2;
tmp_19_7_10_1_reg_6654 <= grp_fu_1243_p2;
tmp_19_7_11_1_reg_6659 <= grp_fu_1247_p2;
tmp_19_7_12_1_reg_6664 <= grp_fu_1251_p2;
tmp_19_7_1_1_reg_6609 <= grp_fu_1207_p2;
tmp_19_7_2_1_reg_6614 <= grp_fu_1211_p2;
tmp_19_7_3_1_reg_6619 <= grp_fu_1215_p2;
tmp_19_7_4_1_reg_6624 <= grp_fu_1219_p2;
tmp_19_7_5_1_reg_6629 <= grp_fu_1223_p2;
tmp_19_7_6_1_reg_6634 <= grp_fu_1227_p2;
tmp_19_7_7_1_reg_6639 <= grp_fu_1231_p2;
tmp_19_7_8_1_reg_6644 <= grp_fu_1235_p2;
tmp_19_7_9_1_reg_6649 <= grp_fu_1239_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 == 1'd0) & (ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
tmp_19_1_0_1_reg_5244 <= grp_fu_1099_p2;
tmp_19_1_10_1_reg_5344 <= grp_fu_1139_p2;
tmp_19_1_11_1_reg_5354 <= grp_fu_1143_p2;
tmp_19_1_12_1_reg_5364 <= grp_fu_1147_p2;
tmp_19_1_1_1_reg_5254 <= grp_fu_1103_p2;
tmp_19_1_2_1_reg_5264 <= grp_fu_1107_p2;
tmp_19_1_3_1_reg_5274 <= grp_fu_1111_p2;
tmp_19_1_4_1_reg_5284 <= grp_fu_1115_p2;
tmp_19_1_5_1_reg_5294 <= grp_fu_1119_p2;
tmp_19_1_6_1_reg_5304 <= grp_fu_1123_p2;
tmp_19_1_7_1_reg_5314 <= grp_fu_1127_p2;
tmp_19_1_8_1_reg_5324 <= grp_fu_1131_p2;
tmp_19_1_9_1_reg_5334 <= grp_fu_1135_p2;
tmp_19_2_10_reg_5424 <= grp_fu_1195_p2;
tmp_19_2_11_reg_5429 <= grp_fu_1199_p2;
tmp_19_2_1_reg_5374 <= grp_fu_1155_p2;
tmp_19_2_2_reg_5379 <= grp_fu_1159_p2;
tmp_19_2_3_reg_5384 <= grp_fu_1163_p2;
tmp_19_2_4_reg_5389 <= grp_fu_1167_p2;
tmp_19_2_5_reg_5394 <= grp_fu_1171_p2;
tmp_19_2_6_reg_5399 <= grp_fu_1175_p2;
tmp_19_2_7_reg_5404 <= grp_fu_1179_p2;
tmp_19_2_8_reg_5409 <= grp_fu_1183_p2;
tmp_19_2_9_reg_5414 <= grp_fu_1187_p2;
tmp_19_2_reg_5369 <= grp_fu_1151_p2;
tmp_19_2_s_reg_5419 <= grp_fu_1191_p2;
tmp_19_3_10_reg_5489 <= grp_fu_1247_p2;
tmp_19_3_11_reg_5494 <= grp_fu_1251_p2;
tmp_19_3_1_reg_5439 <= grp_fu_1207_p2;
tmp_19_3_2_reg_5444 <= grp_fu_1211_p2;
tmp_19_3_3_reg_5449 <= grp_fu_1215_p2;
tmp_19_3_4_reg_5454 <= grp_fu_1219_p2;
tmp_19_3_5_reg_5459 <= grp_fu_1223_p2;
tmp_19_3_6_reg_5464 <= grp_fu_1227_p2;
tmp_19_3_7_reg_5469 <= grp_fu_1231_p2;
tmp_19_3_8_reg_5474 <= grp_fu_1235_p2;
tmp_19_3_9_reg_5479 <= grp_fu_1239_p2;
tmp_19_3_reg_5434 <= grp_fu_1203_p2;
tmp_19_3_s_reg_5484 <= grp_fu_1243_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage1_11001 == 1'b0) & (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
tmp_19_2_0_1_reg_5504 <= grp_fu_1099_p2;
tmp_19_2_10_1_reg_5604 <= grp_fu_1139_p2;
tmp_19_2_11_1_reg_5614 <= grp_fu_1143_p2;
tmp_19_2_12_1_reg_5624 <= grp_fu_1147_p2;
tmp_19_2_1_1_reg_5514 <= grp_fu_1103_p2;
tmp_19_2_2_1_reg_5524 <= grp_fu_1107_p2;
tmp_19_2_3_1_reg_5534 <= grp_fu_1111_p2;
tmp_19_2_4_1_reg_5544 <= grp_fu_1115_p2;
tmp_19_2_5_1_reg_5554 <= grp_fu_1119_p2;
tmp_19_2_6_1_reg_5564 <= grp_fu_1123_p2;
tmp_19_2_7_1_reg_5574 <= grp_fu_1127_p2;
tmp_19_2_8_1_reg_5584 <= grp_fu_1131_p2;
tmp_19_2_9_1_reg_5594 <= grp_fu_1135_p2;
tmp_19_4_10_reg_5749 <= grp_fu_1195_p2;
tmp_19_4_11_reg_5754 <= grp_fu_1199_p2;
tmp_19_4_1_reg_5699 <= grp_fu_1155_p2;
tmp_19_4_2_reg_5704 <= grp_fu_1159_p2;
tmp_19_4_3_reg_5709 <= grp_fu_1163_p2;
tmp_19_4_4_reg_5714 <= grp_fu_1167_p2;
tmp_19_4_5_reg_5719 <= grp_fu_1171_p2;
tmp_19_4_6_reg_5724 <= grp_fu_1175_p2;
tmp_19_4_7_reg_5729 <= grp_fu_1179_p2;
tmp_19_4_8_reg_5734 <= grp_fu_1183_p2;
tmp_19_4_9_reg_5739 <= grp_fu_1187_p2;
tmp_19_4_reg_5694 <= grp_fu_1151_p2;
tmp_19_4_s_reg_5744 <= grp_fu_1191_p2;
tmp_19_5_10_reg_5814 <= grp_fu_1247_p2;
tmp_19_5_11_reg_5819 <= grp_fu_1251_p2;
tmp_19_5_1_reg_5764 <= grp_fu_1207_p2;
tmp_19_5_2_reg_5769 <= grp_fu_1211_p2;
tmp_19_5_3_reg_5774 <= grp_fu_1215_p2;
tmp_19_5_4_reg_5779 <= grp_fu_1219_p2;
tmp_19_5_5_reg_5784 <= grp_fu_1223_p2;
tmp_19_5_6_reg_5789 <= grp_fu_1227_p2;
tmp_19_5_7_reg_5794 <= grp_fu_1231_p2;
tmp_19_5_8_reg_5799 <= grp_fu_1235_p2;
tmp_19_5_9_reg_5804 <= grp_fu_1239_p2;
tmp_19_5_reg_5759 <= grp_fu_1203_p2;
tmp_19_5_s_reg_5809 <= grp_fu_1243_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage5_11001 == 1'b0) & (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
tmp_19_2_0_2_reg_6669 <= grp_fu_1099_p2;
tmp_19_2_10_2_reg_6719 <= grp_fu_1139_p2;
tmp_19_2_11_2_reg_6724 <= grp_fu_1143_p2;
tmp_19_2_12_2_reg_6729 <= grp_fu_1147_p2;
tmp_19_2_1_2_reg_6674 <= grp_fu_1103_p2;
tmp_19_2_2_2_reg_6679 <= grp_fu_1107_p2;
tmp_19_2_3_2_reg_6684 <= grp_fu_1111_p2;
tmp_19_2_4_2_reg_6689 <= grp_fu_1115_p2;
tmp_19_2_5_2_reg_6694 <= grp_fu_1119_p2;
tmp_19_2_6_2_reg_6699 <= grp_fu_1123_p2;
tmp_19_2_7_2_reg_6704 <= grp_fu_1127_p2;
tmp_19_2_8_2_reg_6709 <= grp_fu_1131_p2;
tmp_19_2_9_2_reg_6714 <= grp_fu_1135_p2;
tmp_19_3_0_2_reg_6734 <= grp_fu_1151_p2;
tmp_19_3_10_2_reg_6784 <= grp_fu_1191_p2;
tmp_19_3_11_2_reg_6789 <= grp_fu_1195_p2;
tmp_19_3_12_2_reg_6794 <= grp_fu_1199_p2;
tmp_19_3_1_2_reg_6739 <= grp_fu_1155_p2;
tmp_19_3_2_2_reg_6744 <= grp_fu_1159_p2;
tmp_19_3_3_2_reg_6749 <= grp_fu_1163_p2;
tmp_19_3_4_2_reg_6754 <= grp_fu_1167_p2;
tmp_19_3_5_2_reg_6759 <= grp_fu_1171_p2;
tmp_19_3_6_2_reg_6764 <= grp_fu_1175_p2;
tmp_19_3_7_2_reg_6769 <= grp_fu_1179_p2;
tmp_19_3_8_2_reg_6774 <= grp_fu_1183_p2;
tmp_19_3_9_2_reg_6779 <= grp_fu_1187_p2;
tmp_19_4_0_2_reg_6799 <= grp_fu_1203_p2;
tmp_19_4_10_2_reg_6849 <= grp_fu_1243_p2;
tmp_19_4_11_2_reg_6854 <= grp_fu_1247_p2;
tmp_19_4_12_2_reg_6859 <= grp_fu_1251_p2;
tmp_19_4_1_2_reg_6804 <= grp_fu_1207_p2;
tmp_19_4_2_2_reg_6809 <= grp_fu_1211_p2;
tmp_19_4_3_2_reg_6814 <= grp_fu_1215_p2;
tmp_19_4_4_2_reg_6819 <= grp_fu_1219_p2;
tmp_19_4_5_2_reg_6824 <= grp_fu_1223_p2;
tmp_19_4_6_2_reg_6829 <= grp_fu_1227_p2;
tmp_19_4_7_2_reg_6834 <= grp_fu_1231_p2;
tmp_19_4_8_2_reg_6839 <= grp_fu_1235_p2;
tmp_19_4_9_2_reg_6844 <= grp_fu_1239_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage2_11001 == 1'b0) & (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
tmp_19_3_0_1_reg_5824 <= grp_fu_1099_p2;
tmp_19_3_10_1_reg_5874 <= grp_fu_1139_p2;
tmp_19_3_11_1_reg_5879 <= grp_fu_1143_p2;
tmp_19_3_12_1_reg_5884 <= grp_fu_1147_p2;
tmp_19_3_1_1_reg_5829 <= grp_fu_1103_p2;
tmp_19_3_2_1_reg_5834 <= grp_fu_1107_p2;
tmp_19_3_3_1_reg_5839 <= grp_fu_1111_p2;
tmp_19_3_4_1_reg_5844 <= grp_fu_1115_p2;
tmp_19_3_5_1_reg_5849 <= grp_fu_1119_p2;
tmp_19_3_6_1_reg_5854 <= grp_fu_1123_p2;
tmp_19_3_7_1_reg_5859 <= grp_fu_1127_p2;
tmp_19_3_8_1_reg_5864 <= grp_fu_1131_p2;
tmp_19_3_9_1_reg_5869 <= grp_fu_1135_p2;
tmp_19_6_10_reg_6074 <= grp_fu_1195_p2;
tmp_19_6_11_reg_6079 <= grp_fu_1199_p2;
tmp_19_6_1_reg_6024 <= grp_fu_1155_p2;
tmp_19_6_2_reg_6029 <= grp_fu_1159_p2;
tmp_19_6_3_reg_6034 <= grp_fu_1163_p2;
tmp_19_6_4_reg_6039 <= grp_fu_1167_p2;
tmp_19_6_5_reg_6044 <= grp_fu_1171_p2;
tmp_19_6_6_reg_6049 <= grp_fu_1175_p2;
tmp_19_6_7_reg_6054 <= grp_fu_1179_p2;
tmp_19_6_8_reg_6059 <= grp_fu_1183_p2;
tmp_19_6_9_reg_6064 <= grp_fu_1187_p2;
tmp_19_6_reg_6019 <= grp_fu_1151_p2;
tmp_19_6_s_reg_6069 <= grp_fu_1191_p2;
tmp_19_7_10_reg_6139 <= grp_fu_1247_p2;
tmp_19_7_11_reg_6144 <= grp_fu_1251_p2;
tmp_19_7_1_reg_6089 <= grp_fu_1207_p2;
tmp_19_7_2_reg_6094 <= grp_fu_1211_p2;
tmp_19_7_3_reg_6099 <= grp_fu_1215_p2;
tmp_19_7_4_reg_6104 <= grp_fu_1219_p2;
tmp_19_7_5_reg_6109 <= grp_fu_1223_p2;
tmp_19_7_6_reg_6114 <= grp_fu_1227_p2;
tmp_19_7_7_reg_6119 <= grp_fu_1231_p2;
tmp_19_7_8_reg_6124 <= grp_fu_1235_p2;
tmp_19_7_9_reg_6129 <= grp_fu_1239_p2;
tmp_19_7_reg_6084 <= grp_fu_1203_p2;
tmp_19_7_s_reg_6134 <= grp_fu_1243_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage3_11001 == 1'b0) & (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
tmp_19_4_0_1_reg_6149 <= grp_fu_1099_p2;
tmp_19_4_10_1_reg_6199 <= grp_fu_1139_p2;
tmp_19_4_11_1_reg_6204 <= grp_fu_1143_p2;
tmp_19_4_12_1_reg_6209 <= grp_fu_1147_p2;
tmp_19_4_1_1_reg_6154 <= grp_fu_1103_p2;
tmp_19_4_2_1_reg_6159 <= grp_fu_1107_p2;
tmp_19_4_3_1_reg_6164 <= grp_fu_1111_p2;
tmp_19_4_4_1_reg_6169 <= grp_fu_1115_p2;
tmp_19_4_5_1_reg_6174 <= grp_fu_1119_p2;
tmp_19_4_6_1_reg_6179 <= grp_fu_1123_p2;
tmp_19_4_7_1_reg_6184 <= grp_fu_1127_p2;
tmp_19_4_8_1_reg_6189 <= grp_fu_1131_p2;
tmp_19_4_9_1_reg_6194 <= grp_fu_1135_p2;
tmp_19_5_0_1_reg_6214 <= grp_fu_1151_p2;
tmp_19_5_10_1_reg_6264 <= grp_fu_1191_p2;
tmp_19_5_11_1_reg_6269 <= grp_fu_1195_p2;
tmp_19_5_12_1_reg_6274 <= grp_fu_1199_p2;
tmp_19_5_1_1_reg_6219 <= grp_fu_1155_p2;
tmp_19_5_2_1_reg_6224 <= grp_fu_1159_p2;
tmp_19_5_3_1_reg_6229 <= grp_fu_1163_p2;
tmp_19_5_4_1_reg_6234 <= grp_fu_1167_p2;
tmp_19_5_5_1_reg_6239 <= grp_fu_1171_p2;
tmp_19_5_6_1_reg_6244 <= grp_fu_1175_p2;
tmp_19_5_7_1_reg_6249 <= grp_fu_1179_p2;
tmp_19_5_8_1_reg_6254 <= grp_fu_1183_p2;
tmp_19_5_9_1_reg_6259 <= grp_fu_1187_p2;
tmp_19_6_0_1_reg_6284 <= grp_fu_1203_p2;
tmp_19_6_10_1_reg_6384 <= grp_fu_1243_p2;
tmp_19_6_11_1_reg_6394 <= grp_fu_1247_p2;
tmp_19_6_12_1_reg_6404 <= grp_fu_1251_p2;
tmp_19_6_1_1_reg_6294 <= grp_fu_1207_p2;
tmp_19_6_2_1_reg_6304 <= grp_fu_1211_p2;
tmp_19_6_3_1_reg_6314 <= grp_fu_1215_p2;
tmp_19_6_4_1_reg_6324 <= grp_fu_1219_p2;
tmp_19_6_5_1_reg_6334 <= grp_fu_1223_p2;
tmp_19_6_6_1_reg_6344 <= grp_fu_1227_p2;
tmp_19_6_7_1_reg_6354 <= grp_fu_1231_p2;
tmp_19_6_8_1_reg_6364 <= grp_fu_1235_p2;
tmp_19_6_9_1_reg_6374 <= grp_fu_1239_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage6_11001 == 1'b0) & (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
tmp_19_5_0_2_reg_6864 <= grp_fu_1099_p2;
tmp_19_5_10_2_reg_6914 <= grp_fu_1139_p2;
tmp_19_5_11_2_reg_6919 <= grp_fu_1143_p2;
tmp_19_5_12_2_reg_6924 <= grp_fu_1147_p2;
tmp_19_5_1_2_reg_6869 <= grp_fu_1103_p2;
tmp_19_5_2_2_reg_6874 <= grp_fu_1107_p2;
tmp_19_5_3_2_reg_6879 <= grp_fu_1111_p2;
tmp_19_5_4_2_reg_6884 <= grp_fu_1115_p2;
tmp_19_5_5_2_reg_6889 <= grp_fu_1119_p2;
tmp_19_5_6_2_reg_6894 <= grp_fu_1123_p2;
tmp_19_5_7_2_reg_6899 <= grp_fu_1127_p2;
tmp_19_5_8_2_reg_6904 <= grp_fu_1131_p2;
tmp_19_5_9_2_reg_6909 <= grp_fu_1135_p2;
tmp_19_6_0_2_reg_6929 <= grp_fu_1151_p2;
tmp_19_6_10_2_reg_6979 <= grp_fu_1191_p2;
tmp_19_6_11_2_reg_6984 <= grp_fu_1195_p2;
tmp_19_6_12_2_reg_6989 <= grp_fu_1199_p2;
tmp_19_6_1_2_reg_6934 <= grp_fu_1155_p2;
tmp_19_6_2_2_reg_6939 <= grp_fu_1159_p2;
tmp_19_6_3_2_reg_6944 <= grp_fu_1163_p2;
tmp_19_6_4_2_reg_6949 <= grp_fu_1167_p2;
tmp_19_6_5_2_reg_6954 <= grp_fu_1171_p2;
tmp_19_6_6_2_reg_6959 <= grp_fu_1175_p2;
tmp_19_6_7_2_reg_6964 <= grp_fu_1179_p2;
tmp_19_6_8_2_reg_6969 <= grp_fu_1183_p2;
tmp_19_6_9_2_reg_6974 <= grp_fu_1187_p2;
tmp_19_7_0_2_reg_6994 <= grp_fu_1203_p2;
tmp_19_7_10_2_reg_7044 <= grp_fu_1243_p2;
tmp_19_7_11_2_reg_7049 <= grp_fu_1247_p2;
tmp_19_7_12_2_reg_7054 <= grp_fu_1251_p2;
tmp_19_7_1_2_reg_6999 <= grp_fu_1207_p2;
tmp_19_7_2_2_reg_7004 <= grp_fu_1211_p2;
tmp_19_7_3_2_reg_7009 <= grp_fu_1215_p2;
tmp_19_7_4_2_reg_7014 <= grp_fu_1219_p2;
tmp_19_7_5_2_reg_7019 <= grp_fu_1223_p2;
tmp_19_7_6_2_reg_7024 <= grp_fu_1227_p2;
tmp_19_7_7_2_reg_7029 <= grp_fu_1231_p2;
tmp_19_7_8_2_reg_7034 <= grp_fu_1235_p2;
tmp_19_7_9_2_reg_7039 <= grp_fu_1239_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage3_11001 == 1'b0) & (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
tmp_20_0_0_1_reg_7579 <= grp_fu_943_p2;
tmp_20_0_10_1_reg_7629 <= grp_fu_983_p2;
tmp_20_0_11_1_reg_7634 <= grp_fu_987_p2;
tmp_20_0_12_1_reg_7639 <= grp_fu_991_p2;
tmp_20_0_1_1_reg_7584 <= grp_fu_947_p2;
tmp_20_0_2_1_reg_7589 <= grp_fu_951_p2;
tmp_20_0_3_1_reg_7594 <= grp_fu_955_p2;
tmp_20_0_4_1_reg_7599 <= grp_fu_959_p2;
tmp_20_0_5_1_reg_7604 <= grp_fu_963_p2;
tmp_20_0_6_1_reg_7609 <= grp_fu_967_p2;
tmp_20_0_7_1_reg_7614 <= grp_fu_971_p2;
tmp_20_0_8_1_reg_7619 <= grp_fu_975_p2;
tmp_20_0_9_1_reg_7624 <= grp_fu_979_p2;
tmp_20_1_0_1_reg_7644 <= grp_fu_995_p2;
tmp_20_1_10_1_reg_7694 <= grp_fu_1035_p2;
tmp_20_1_11_1_reg_7699 <= grp_fu_1039_p2;
tmp_20_1_12_1_reg_7704 <= grp_fu_1043_p2;
tmp_20_1_1_1_reg_7649 <= grp_fu_999_p2;
tmp_20_1_2_1_reg_7654 <= grp_fu_1003_p2;
tmp_20_1_3_1_reg_7659 <= grp_fu_1007_p2;
tmp_20_1_4_1_reg_7664 <= grp_fu_1011_p2;
tmp_20_1_5_1_reg_7669 <= grp_fu_1015_p2;
tmp_20_1_6_1_reg_7674 <= grp_fu_1019_p2;
tmp_20_1_7_1_reg_7679 <= grp_fu_1023_p2;
tmp_20_1_8_1_reg_7684 <= grp_fu_1027_p2;
tmp_20_1_9_1_reg_7689 <= grp_fu_1031_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage1_11001 == 1'b0) & (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
tmp_20_0_0_2_reg_8099 <= grp_fu_943_p2;
tmp_20_0_10_2_reg_8149 <= grp_fu_983_p2;
tmp_20_0_11_2_reg_8154 <= grp_fu_987_p2;
tmp_20_0_12_2_reg_8159 <= grp_fu_991_p2;
tmp_20_0_1_2_reg_8104 <= grp_fu_947_p2;
tmp_20_0_2_2_reg_8109 <= grp_fu_951_p2;
tmp_20_0_3_2_reg_8114 <= grp_fu_955_p2;
tmp_20_0_4_2_reg_8119 <= grp_fu_959_p2;
tmp_20_0_5_2_reg_8124 <= grp_fu_963_p2;
tmp_20_0_6_2_reg_8129 <= grp_fu_967_p2;
tmp_20_0_7_2_reg_8134 <= grp_fu_971_p2;
tmp_20_0_8_2_reg_8139 <= grp_fu_975_p2;
tmp_20_0_9_2_reg_8144 <= grp_fu_979_p2;
tmp_20_1_0_2_reg_8164 <= grp_fu_995_p2;
tmp_20_1_10_2_reg_8214 <= grp_fu_1035_p2;
tmp_20_1_11_2_reg_8219 <= grp_fu_1039_p2;
tmp_20_1_12_2_reg_8224 <= grp_fu_1043_p2;
tmp_20_1_1_2_reg_8169 <= grp_fu_999_p2;
tmp_20_1_2_2_reg_8174 <= grp_fu_1003_p2;
tmp_20_1_3_2_reg_8179 <= grp_fu_1007_p2;
tmp_20_1_4_2_reg_8184 <= grp_fu_1011_p2;
tmp_20_1_5_2_reg_8189 <= grp_fu_1015_p2;
tmp_20_1_6_2_reg_8194 <= grp_fu_1019_p2;
tmp_20_1_7_2_reg_8199 <= grp_fu_1023_p2;
tmp_20_1_8_2_reg_8204 <= grp_fu_1027_p2;
tmp_20_1_9_2_reg_8209 <= grp_fu_1031_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage5_11001 == 1'b0) & (ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
tmp_20_0_10_reg_7114 <= grp_fu_987_p2;
tmp_20_0_11_reg_7119 <= grp_fu_991_p2;
tmp_20_0_1_reg_7064 <= grp_fu_947_p2;
tmp_20_0_2_reg_7069 <= grp_fu_951_p2;
tmp_20_0_3_reg_7074 <= grp_fu_955_p2;
tmp_20_0_4_reg_7079 <= grp_fu_959_p2;
tmp_20_0_5_reg_7084 <= grp_fu_963_p2;
tmp_20_0_6_reg_7089 <= grp_fu_967_p2;
tmp_20_0_7_reg_7094 <= grp_fu_971_p2;
tmp_20_0_8_reg_7099 <= grp_fu_975_p2;
tmp_20_0_9_reg_7104 <= grp_fu_979_p2;
tmp_20_0_s_reg_7109 <= grp_fu_983_p2;
tmp_20_1_10_reg_7179 <= grp_fu_1039_p2;
tmp_20_1_11_reg_7184 <= grp_fu_1043_p2;
tmp_20_1_1_reg_7129 <= grp_fu_999_p2;
tmp_20_1_2_reg_7134 <= grp_fu_1003_p2;
tmp_20_1_3_reg_7139 <= grp_fu_1007_p2;
tmp_20_1_4_reg_7144 <= grp_fu_1011_p2;
tmp_20_1_5_reg_7149 <= grp_fu_1015_p2;
tmp_20_1_6_reg_7154 <= grp_fu_1019_p2;
tmp_20_1_7_reg_7159 <= grp_fu_1023_p2;
tmp_20_1_8_reg_7164 <= grp_fu_1027_p2;
tmp_20_1_9_reg_7169 <= grp_fu_1031_p2;
tmp_20_1_reg_7124 <= grp_fu_995_p2;
tmp_20_1_s_reg_7174 <= grp_fu_1035_p2;
tmp_351_reg_7059 <= grp_fu_943_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage4_11001 == 1'b0) & (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
tmp_20_2_0_1_reg_7709 <= grp_fu_943_p2;
tmp_20_2_10_1_reg_7759 <= grp_fu_983_p2;
tmp_20_2_11_1_reg_7764 <= grp_fu_987_p2;
tmp_20_2_12_1_reg_7769 <= grp_fu_991_p2;
tmp_20_2_1_1_reg_7714 <= grp_fu_947_p2;
tmp_20_2_2_1_reg_7719 <= grp_fu_951_p2;
tmp_20_2_3_1_reg_7724 <= grp_fu_955_p2;
tmp_20_2_4_1_reg_7729 <= grp_fu_959_p2;
tmp_20_2_5_1_reg_7734 <= grp_fu_963_p2;
tmp_20_2_6_1_reg_7739 <= grp_fu_967_p2;
tmp_20_2_7_1_reg_7744 <= grp_fu_971_p2;
tmp_20_2_8_1_reg_7749 <= grp_fu_975_p2;
tmp_20_2_9_1_reg_7754 <= grp_fu_979_p2;
tmp_20_3_0_1_reg_7774 <= grp_fu_995_p2;
tmp_20_3_10_1_reg_7824 <= grp_fu_1035_p2;
tmp_20_3_11_1_reg_7829 <= grp_fu_1039_p2;
tmp_20_3_12_1_reg_7834 <= grp_fu_1043_p2;
tmp_20_3_1_1_reg_7779 <= grp_fu_999_p2;
tmp_20_3_2_1_reg_7784 <= grp_fu_1003_p2;
tmp_20_3_3_1_reg_7789 <= grp_fu_1007_p2;
tmp_20_3_4_1_reg_7794 <= grp_fu_1011_p2;
tmp_20_3_5_1_reg_7799 <= grp_fu_1015_p2;
tmp_20_3_6_1_reg_7804 <= grp_fu_1019_p2;
tmp_20_3_7_1_reg_7809 <= grp_fu_1023_p2;
tmp_20_3_8_1_reg_7814 <= grp_fu_1027_p2;
tmp_20_3_9_1_reg_7819 <= grp_fu_1031_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage2_11001 == 1'b0) & (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
tmp_20_2_0_2_reg_8229 <= grp_fu_943_p2;
tmp_20_2_10_2_reg_8279 <= grp_fu_983_p2;
tmp_20_2_11_2_reg_8284 <= grp_fu_987_p2;
tmp_20_2_12_2_reg_8289 <= grp_fu_991_p2;
tmp_20_2_1_2_reg_8234 <= grp_fu_947_p2;
tmp_20_2_2_2_reg_8239 <= grp_fu_951_p2;
tmp_20_2_3_2_reg_8244 <= grp_fu_955_p2;
tmp_20_2_4_2_reg_8249 <= grp_fu_959_p2;
tmp_20_2_5_2_reg_8254 <= grp_fu_963_p2;
tmp_20_2_6_2_reg_8259 <= grp_fu_967_p2;
tmp_20_2_7_2_reg_8264 <= grp_fu_971_p2;
tmp_20_2_8_2_reg_8269 <= grp_fu_975_p2;
tmp_20_2_9_2_reg_8274 <= grp_fu_979_p2;
tmp_20_3_0_2_reg_8294 <= grp_fu_995_p2;
tmp_20_3_10_2_reg_8344 <= grp_fu_1035_p2;
tmp_20_3_11_2_reg_8349 <= grp_fu_1039_p2;
tmp_20_3_12_2_reg_8354 <= grp_fu_1043_p2;
tmp_20_3_1_2_reg_8299 <= grp_fu_999_p2;
tmp_20_3_2_2_reg_8304 <= grp_fu_1003_p2;
tmp_20_3_3_2_reg_8309 <= grp_fu_1007_p2;
tmp_20_3_4_2_reg_8314 <= grp_fu_1011_p2;
tmp_20_3_5_2_reg_8319 <= grp_fu_1015_p2;
tmp_20_3_6_2_reg_8324 <= grp_fu_1019_p2;
tmp_20_3_7_2_reg_8329 <= grp_fu_1023_p2;
tmp_20_3_8_2_reg_8334 <= grp_fu_1027_p2;
tmp_20_3_9_2_reg_8339 <= grp_fu_1031_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage6_11001 == 1'b0) & (ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
tmp_20_2_10_reg_7244 <= grp_fu_987_p2;
tmp_20_2_11_reg_7249 <= grp_fu_991_p2;
tmp_20_2_1_reg_7194 <= grp_fu_947_p2;
tmp_20_2_2_reg_7199 <= grp_fu_951_p2;
tmp_20_2_3_reg_7204 <= grp_fu_955_p2;
tmp_20_2_4_reg_7209 <= grp_fu_959_p2;
tmp_20_2_5_reg_7214 <= grp_fu_963_p2;
tmp_20_2_6_reg_7219 <= grp_fu_967_p2;
tmp_20_2_7_reg_7224 <= grp_fu_971_p2;
tmp_20_2_8_reg_7229 <= grp_fu_975_p2;
tmp_20_2_9_reg_7234 <= grp_fu_979_p2;
tmp_20_2_reg_7189 <= grp_fu_943_p2;
tmp_20_2_s_reg_7239 <= grp_fu_983_p2;
tmp_20_3_10_reg_7309 <= grp_fu_1039_p2;
tmp_20_3_11_reg_7314 <= grp_fu_1043_p2;
tmp_20_3_1_reg_7259 <= grp_fu_999_p2;
tmp_20_3_2_reg_7264 <= grp_fu_1003_p2;
tmp_20_3_3_reg_7269 <= grp_fu_1007_p2;
tmp_20_3_4_reg_7274 <= grp_fu_1011_p2;
tmp_20_3_5_reg_7279 <= grp_fu_1015_p2;
tmp_20_3_6_reg_7284 <= grp_fu_1019_p2;
tmp_20_3_7_reg_7289 <= grp_fu_1023_p2;
tmp_20_3_8_reg_7294 <= grp_fu_1027_p2;
tmp_20_3_9_reg_7299 <= grp_fu_1031_p2;
tmp_20_3_reg_7254 <= grp_fu_995_p2;
tmp_20_3_s_reg_7304 <= grp_fu_1035_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage5_11001 == 1'b0) & (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
tmp_20_4_0_1_reg_7839 <= grp_fu_1047_p2;
tmp_20_4_10_1_reg_7889 <= grp_fu_1087_p2;
tmp_20_4_11_1_reg_7894 <= grp_fu_1091_p2;
tmp_20_4_12_1_reg_7899 <= grp_fu_1095_p2;
tmp_20_4_1_1_reg_7844 <= grp_fu_1051_p2;
tmp_20_4_2_1_reg_7849 <= grp_fu_1055_p2;
tmp_20_4_3_1_reg_7854 <= grp_fu_1059_p2;
tmp_20_4_4_1_reg_7859 <= grp_fu_1063_p2;
tmp_20_4_5_1_reg_7864 <= grp_fu_1067_p2;
tmp_20_4_6_1_reg_7869 <= grp_fu_1071_p2;
tmp_20_4_7_1_reg_7874 <= grp_fu_1075_p2;
tmp_20_4_8_1_reg_7879 <= grp_fu_1079_p2;
tmp_20_4_9_1_reg_7884 <= grp_fu_1083_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage3_11001 == 1'b0) & (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
tmp_20_4_0_2_reg_8359 <= grp_fu_1047_p2;
tmp_20_4_10_2_reg_8409 <= grp_fu_1087_p2;
tmp_20_4_11_2_reg_8414 <= grp_fu_1091_p2;
tmp_20_4_12_2_reg_8419 <= grp_fu_1095_p2;
tmp_20_4_1_2_reg_8364 <= grp_fu_1051_p2;
tmp_20_4_2_2_reg_8369 <= grp_fu_1055_p2;
tmp_20_4_3_2_reg_8374 <= grp_fu_1059_p2;
tmp_20_4_4_2_reg_8379 <= grp_fu_1063_p2;
tmp_20_4_5_2_reg_8384 <= grp_fu_1067_p2;
tmp_20_4_6_2_reg_8389 <= grp_fu_1071_p2;
tmp_20_4_7_2_reg_8394 <= grp_fu_1075_p2;
tmp_20_4_8_2_reg_8399 <= grp_fu_1079_p2;
tmp_20_4_9_2_reg_8404 <= grp_fu_1083_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage7_11001 == 1'b0) & (ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
tmp_20_4_10_reg_7374 <= grp_fu_987_p2;
tmp_20_4_11_reg_7379 <= grp_fu_991_p2;
tmp_20_4_1_reg_7324 <= grp_fu_947_p2;
tmp_20_4_2_reg_7329 <= grp_fu_951_p2;
tmp_20_4_3_reg_7334 <= grp_fu_955_p2;
tmp_20_4_4_reg_7339 <= grp_fu_959_p2;
tmp_20_4_5_reg_7344 <= grp_fu_963_p2;
tmp_20_4_6_reg_7349 <= grp_fu_967_p2;
tmp_20_4_7_reg_7354 <= grp_fu_971_p2;
tmp_20_4_8_reg_7359 <= grp_fu_975_p2;
tmp_20_4_9_reg_7364 <= grp_fu_979_p2;
tmp_20_4_reg_7319 <= grp_fu_943_p2;
tmp_20_4_s_reg_7369 <= grp_fu_983_p2;
tmp_20_5_10_reg_7439 <= grp_fu_1039_p2;
tmp_20_5_11_reg_7444 <= grp_fu_1043_p2;
tmp_20_5_1_reg_7389 <= grp_fu_999_p2;
tmp_20_5_2_reg_7394 <= grp_fu_1003_p2;
tmp_20_5_3_reg_7399 <= grp_fu_1007_p2;
tmp_20_5_4_reg_7404 <= grp_fu_1011_p2;
tmp_20_5_5_reg_7409 <= grp_fu_1015_p2;
tmp_20_5_6_reg_7414 <= grp_fu_1019_p2;
tmp_20_5_7_reg_7419 <= grp_fu_1023_p2;
tmp_20_5_8_reg_7424 <= grp_fu_1027_p2;
tmp_20_5_9_reg_7429 <= grp_fu_1031_p2;
tmp_20_5_reg_7384 <= grp_fu_995_p2;
tmp_20_5_s_reg_7434 <= grp_fu_1035_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage6_11001 == 1'b0) & (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
tmp_20_5_0_1_reg_7904 <= grp_fu_1047_p2;
tmp_20_5_10_1_reg_7954 <= grp_fu_1087_p2;
tmp_20_5_11_1_reg_7959 <= grp_fu_1091_p2;
tmp_20_5_12_1_reg_7964 <= grp_fu_1095_p2;
tmp_20_5_1_1_reg_7909 <= grp_fu_1051_p2;
tmp_20_5_2_1_reg_7914 <= grp_fu_1055_p2;
tmp_20_5_3_1_reg_7919 <= grp_fu_1059_p2;
tmp_20_5_4_1_reg_7924 <= grp_fu_1063_p2;
tmp_20_5_5_1_reg_7929 <= grp_fu_1067_p2;
tmp_20_5_6_1_reg_7934 <= grp_fu_1071_p2;
tmp_20_5_7_1_reg_7939 <= grp_fu_1075_p2;
tmp_20_5_8_1_reg_7944 <= grp_fu_1079_p2;
tmp_20_5_9_1_reg_7949 <= grp_fu_1083_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage4_11001 == 1'b0) & (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
tmp_20_5_0_2_reg_8424 <= grp_fu_1047_p2;
tmp_20_5_10_2_reg_8474 <= grp_fu_1087_p2;
tmp_20_5_11_2_reg_8479 <= grp_fu_1091_p2;
tmp_20_5_12_2_reg_8484 <= grp_fu_1095_p2;
tmp_20_5_1_2_reg_8429 <= grp_fu_1051_p2;
tmp_20_5_2_2_reg_8434 <= grp_fu_1055_p2;
tmp_20_5_3_2_reg_8439 <= grp_fu_1059_p2;
tmp_20_5_4_2_reg_8444 <= grp_fu_1063_p2;
tmp_20_5_5_2_reg_8449 <= grp_fu_1067_p2;
tmp_20_5_6_2_reg_8454 <= grp_fu_1071_p2;
tmp_20_5_7_2_reg_8459 <= grp_fu_1075_p2;
tmp_20_5_8_2_reg_8464 <= grp_fu_1079_p2;
tmp_20_5_9_2_reg_8469 <= grp_fu_1083_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage7_11001 == 1'b0) & (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
tmp_20_6_0_1_reg_7969 <= grp_fu_1047_p2;
tmp_20_6_10_1_reg_8019 <= grp_fu_1087_p2;
tmp_20_6_11_1_reg_8024 <= grp_fu_1091_p2;
tmp_20_6_12_1_reg_8029 <= grp_fu_1095_p2;
tmp_20_6_1_1_reg_7974 <= grp_fu_1051_p2;
tmp_20_6_2_1_reg_7979 <= grp_fu_1055_p2;
tmp_20_6_3_1_reg_7984 <= grp_fu_1059_p2;
tmp_20_6_4_1_reg_7989 <= grp_fu_1063_p2;
tmp_20_6_5_1_reg_7994 <= grp_fu_1067_p2;
tmp_20_6_6_1_reg_7999 <= grp_fu_1071_p2;
tmp_20_6_7_1_reg_8004 <= grp_fu_1075_p2;
tmp_20_6_8_1_reg_8009 <= grp_fu_1079_p2;
tmp_20_6_9_1_reg_8014 <= grp_fu_1083_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage1_11001 == 1'b0) & (ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
tmp_20_6_0_2_reg_8489 <= grp_fu_1047_p2;
tmp_20_6_10_2_reg_8539 <= grp_fu_1087_p2;
tmp_20_6_11_2_reg_8544 <= grp_fu_1091_p2;
tmp_20_6_12_2_reg_8549 <= grp_fu_1095_p2;
tmp_20_6_1_2_reg_8494 <= grp_fu_1051_p2;
tmp_20_6_2_2_reg_8499 <= grp_fu_1055_p2;
tmp_20_6_3_2_reg_8504 <= grp_fu_1059_p2;
tmp_20_6_4_2_reg_8509 <= grp_fu_1063_p2;
tmp_20_6_5_2_reg_8514 <= grp_fu_1067_p2;
tmp_20_6_6_2_reg_8519 <= grp_fu_1071_p2;
tmp_20_6_7_2_reg_8524 <= grp_fu_1075_p2;
tmp_20_6_8_2_reg_8529 <= grp_fu_1079_p2;
tmp_20_6_9_2_reg_8534 <= grp_fu_1083_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 == 1'd0) & (ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
tmp_20_6_10_reg_7504 <= grp_fu_987_p2;
tmp_20_6_11_reg_7509 <= grp_fu_991_p2;
tmp_20_6_1_reg_7454 <= grp_fu_947_p2;
tmp_20_6_2_reg_7459 <= grp_fu_951_p2;
tmp_20_6_3_reg_7464 <= grp_fu_955_p2;
tmp_20_6_4_reg_7469 <= grp_fu_959_p2;
tmp_20_6_5_reg_7474 <= grp_fu_963_p2;
tmp_20_6_6_reg_7479 <= grp_fu_967_p2;
tmp_20_6_7_reg_7484 <= grp_fu_971_p2;
tmp_20_6_8_reg_7489 <= grp_fu_975_p2;
tmp_20_6_9_reg_7494 <= grp_fu_979_p2;
tmp_20_6_reg_7449 <= grp_fu_943_p2;
tmp_20_6_s_reg_7499 <= grp_fu_983_p2;
tmp_20_7_10_reg_7569 <= grp_fu_1039_p2;
tmp_20_7_11_reg_7574 <= grp_fu_1043_p2;
tmp_20_7_1_reg_7519 <= grp_fu_999_p2;
tmp_20_7_2_reg_7524 <= grp_fu_1003_p2;
tmp_20_7_3_reg_7529 <= grp_fu_1007_p2;
tmp_20_7_4_reg_7534 <= grp_fu_1011_p2;
tmp_20_7_5_reg_7539 <= grp_fu_1015_p2;
tmp_20_7_6_reg_7544 <= grp_fu_1019_p2;
tmp_20_7_7_reg_7549 <= grp_fu_1023_p2;
tmp_20_7_8_reg_7554 <= grp_fu_1027_p2;
tmp_20_7_9_reg_7559 <= grp_fu_1031_p2;
tmp_20_7_reg_7514 <= grp_fu_995_p2;
tmp_20_7_s_reg_7564 <= grp_fu_1035_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 == 1'd0) & (ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter6) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
tmp_20_7_0_1_reg_8034 <= grp_fu_1047_p2;
tmp_20_7_10_1_reg_8084 <= grp_fu_1087_p2;
tmp_20_7_11_1_reg_8089 <= grp_fu_1091_p2;
tmp_20_7_12_1_reg_8094 <= grp_fu_1095_p2;
tmp_20_7_1_1_reg_8039 <= grp_fu_1051_p2;
tmp_20_7_2_1_reg_8044 <= grp_fu_1055_p2;
tmp_20_7_3_1_reg_8049 <= grp_fu_1059_p2;
tmp_20_7_4_1_reg_8054 <= grp_fu_1063_p2;
tmp_20_7_5_1_reg_8059 <= grp_fu_1067_p2;
tmp_20_7_6_1_reg_8064 <= grp_fu_1071_p2;
tmp_20_7_7_1_reg_8069 <= grp_fu_1075_p2;
tmp_20_7_8_1_reg_8074 <= grp_fu_1079_p2;
tmp_20_7_9_1_reg_8079 <= grp_fu_1083_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage2_11001 == 1'b0) & (ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
tmp_20_7_0_2_reg_8554 <= grp_fu_1047_p2;
tmp_20_7_10_2_reg_8604 <= grp_fu_1087_p2;
tmp_20_7_11_2_reg_8609 <= grp_fu_1091_p2;
tmp_20_7_12_2_reg_8614 <= grp_fu_1095_p2;
tmp_20_7_1_2_reg_8559 <= grp_fu_1051_p2;
tmp_20_7_2_2_reg_8564 <= grp_fu_1055_p2;
tmp_20_7_3_2_reg_8569 <= grp_fu_1059_p2;
tmp_20_7_4_2_reg_8574 <= grp_fu_1063_p2;
tmp_20_7_5_2_reg_8579 <= grp_fu_1067_p2;
tmp_20_7_6_2_reg_8584 <= grp_fu_1071_p2;
tmp_20_7_7_2_reg_8589 <= grp_fu_1075_p2;
tmp_20_7_8_2_reg_8594 <= grp_fu_1079_p2;
tmp_20_7_9_2_reg_8599 <= grp_fu_1083_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage5_11001 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
tmp_210_reg_3511 <= tmp_210_fu_1876_p2;
tmp_250_reg_3516 <= tmp_250_fu_1881_p2;
tmp_7_reg_3356 <= tmp_7_fu_1807_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage6_11001 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
tmp_290_reg_3616 <= tmp_290_fu_1978_p2;
tmp_330_reg_3621 <= tmp_330_fu_1983_p2;
tmp_331_reg_3626 <= tmp_331_fu_1988_p2;
tmp_332_reg_3631 <= tmp_332_fu_1993_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage3_11001 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
tmp_2_reg_3281 <= tmp_2_fu_1657_p2;
tmp_90_reg_3299[9 : 2] <= tmp_90_fu_1694_p2[9 : 2];
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage6_11001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
tmp_355_reg_4719 <= tmp_355_fu_2149_p1;
tmp_356_reg_4784 <= tmp_356_fu_2153_p1;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage7_11001 == 1'b0) & (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
tmp_357_reg_5044 <= tmp_357_fu_2157_p1;
tmp_358_reg_5109 <= tmp_358_fu_2161_p1;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage3_11001 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
tmp_5_mid2_reg_3286 <= tmp_5_mid2_fu_1662_p3;
end
end
always @ (*) begin
if ((exitcond_flatten1_fu_1541_p2 == 1'd1)) begin
ap_condition_pp0_exit_iter0_state2 = 1'b1;
end else begin
ap_condition_pp0_exit_iter0_state2 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state76)) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter9) & (1'b0 == ap_enable_reg_pp0_iter8) & (1'b0 == ap_enable_reg_pp0_iter7) & (1'b0 == ap_enable_reg_pp0_iter6) & (1'b0 == ap_enable_reg_pp0_iter5) & (1'b0 == ap_enable_reg_pp0_iter4) & (1'b0 == ap_enable_reg_pp0_iter3) & (1'b0 == ap_enable_reg_pp0_iter2))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_phi_mux_i_phi_fu_900_p4 = tmp_1_mid2_v_reg_3225;
end else begin
ap_phi_mux_i_phi_fu_900_p4 = i_reg_896;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_phi_mux_indvar_flatten1_phi_fu_889_p4 = indvar_flatten_next1_reg_3180;
end else begin
ap_phi_mux_indvar_flatten1_phi_fu_889_p4 = indvar_flatten1_reg_885;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_phi_mux_indvar_flatten_phi_fu_912_p4 = indvar_flatten_next_reg_3252;
end else begin
ap_phi_mux_indvar_flatten_phi_fu_912_p4 = indvar_flatten_reg_908;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_phi_mux_j_phi_fu_923_p4 = tmp_5_mid2_reg_3286;
end else begin
ap_phi_mux_j_phi_fu_923_p4 = j_reg_919;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0 == 1'b0) & (exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_phi_mux_row_b_phi_fu_935_p4 = row_b_1_reg_3276;
end else begin
ap_phi_mux_row_b_phi_fu_935_p4 = row_b_reg_931;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state76)) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
bufi_0_Addr_A_orig = tmp_340_cast_fu_2010_p1;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_0_Addr_A_orig = tmp_338_cast_fu_1998_p1;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_0_Addr_A_orig = tmp_336_cast_fu_1966_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_0_Addr_A_orig = tmp_334_cast_fu_1864_p1;
end else begin
bufi_0_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
bufi_0_Addr_B_orig = tmp_341_cast_fu_2016_p1;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_0_Addr_B_orig = tmp_339_cast_fu_2004_p1;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_0_Addr_B_orig = tmp_337_cast_fu_1972_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_0_Addr_B_orig = tmp_335_cast_fu_1870_p1;
end else begin
bufi_0_Addr_B_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage2_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufi_0_EN_A = 1'b1;
end else begin
bufi_0_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage2_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufi_0_EN_B = 1'b1;
end else begin
bufi_0_EN_B = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
bufi_1_Addr_A_orig = tmp_340_cast_fu_2010_p1;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_1_Addr_A_orig = tmp_338_cast_fu_1998_p1;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_1_Addr_A_orig = tmp_336_cast_fu_1966_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_1_Addr_A_orig = tmp_334_cast_fu_1864_p1;
end else begin
bufi_1_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
bufi_1_Addr_B_orig = tmp_341_cast_fu_2016_p1;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_1_Addr_B_orig = tmp_339_cast_fu_2004_p1;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_1_Addr_B_orig = tmp_337_cast_fu_1972_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_1_Addr_B_orig = tmp_335_cast_fu_1870_p1;
end else begin
bufi_1_Addr_B_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage2_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufi_1_EN_A = 1'b1;
end else begin
bufi_1_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage2_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufi_1_EN_B = 1'b1;
end else begin
bufi_1_EN_B = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
bufi_2_Addr_A_orig = tmp_340_cast_fu_2010_p1;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_2_Addr_A_orig = tmp_338_cast_fu_1998_p1;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_2_Addr_A_orig = tmp_336_cast_fu_1966_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_2_Addr_A_orig = tmp_334_cast_fu_1864_p1;
end else begin
bufi_2_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
bufi_2_Addr_B_orig = tmp_341_cast_fu_2016_p1;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_2_Addr_B_orig = tmp_339_cast_fu_2004_p1;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_2_Addr_B_orig = tmp_337_cast_fu_1972_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
bufi_2_Addr_B_orig = tmp_335_cast_fu_1870_p1;
end else begin
bufi_2_Addr_B_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage2_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufi_2_EN_A = 1'b1;
end else begin
bufi_2_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage2_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufi_2_EN_B = 1'b1;
end else begin
bufi_2_EN_B = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
bufo_Addr_A_orig = ap_reg_pp0_iter8_bufo_addr_6_reg_4579;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter8) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
bufo_Addr_A_orig = ap_reg_pp0_iter7_bufo_addr_4_reg_4439;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
bufo_Addr_A_orig = ap_reg_pp0_iter7_bufo_addr_2_reg_4429;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
bufo_Addr_A_orig = ap_reg_pp0_iter7_bufo_addr_reg_4317;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufo_Addr_A_orig = tmp_346_fu_2118_p3;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
bufo_Addr_A_orig = tmp_342_fu_2082_p3;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
bufo_Addr_A_orig = tmp_338_fu_2054_p3;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
bufo_Addr_A_orig = tmp_334_fu_2029_p1;
end else begin
bufo_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
bufo_Addr_B_orig = ap_reg_pp0_iter8_bufo_addr_7_reg_4584;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter8) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
bufo_Addr_B_orig = ap_reg_pp0_iter7_bufo_addr_5_reg_4444;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
bufo_Addr_B_orig = ap_reg_pp0_iter7_bufo_addr_3_reg_4434;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
bufo_Addr_B_orig = ap_reg_pp0_iter7_bufo_addr_1_reg_4322;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufo_Addr_B_orig = tmp_348_fu_2132_p3;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
bufo_Addr_B_orig = tmp_344_fu_2096_p3;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
bufo_Addr_B_orig = tmp_340_fu_2068_p3;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
bufo_Addr_B_orig = tmp_336_fu_2040_p3;
end else begin
bufo_Addr_B_orig = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
bufo_Din_A = tmp_289_fu_3040_p14;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter8) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
bufo_Din_A = tmp_209_fu_2900_p14;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
bufo_Din_A = tmp_129_fu_2760_p14;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
bufo_Din_A = tmp_49_fu_2620_p14;
end else begin
bufo_Din_A = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
bufo_Din_B = tmp_329_fu_3110_p14;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter8) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
bufo_Din_B = tmp_249_fu_2970_p14;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
bufo_Din_B = tmp_169_fu_2830_p14;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
bufo_Din_B = tmp_89_fu_2690_p14;
end else begin
bufo_Din_B = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter7)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter7)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter9)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter8) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufo_EN_A = 1'b1;
end else begin
bufo_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter7)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter7)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter9)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter8) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufo_EN_B = 1'b1;
end else begin
bufo_EN_B = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter7)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter7)) | ((ap_block_pp0_stage1_11001 == 1'b0) & (ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter9)) | ((ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 == 1'd0) & (ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter8) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufo_WEN_A = 64'd18446744073709551615;
end else begin
bufo_WEN_A = 64'd0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter7)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter7)) | ((ap_block_pp0_stage1_11001 == 1'b0) & (ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 == 1'd0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter9)) | ((ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 == 1'd0) & (ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter8) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufo_WEN_B = 64'd18446744073709551615;
end else begin
bufo_WEN_B = 64'd0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
bufw_0_Addr_A_orig = tmp_330_cast_fu_1910_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufw_0_Addr_A_orig = tmp_6_cast_fu_1775_p1;
end else begin
bufw_0_Addr_A_orig = 'bx;
end
end else begin
bufw_0_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufw_0_EN_A = 1'b1;
end else begin
bufw_0_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)))) begin
bufw_0_EN_B = 1'b1;
end else begin
bufw_0_EN_B = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
bufw_10_Addr_A_orig = tmp_330_cast_fu_1910_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufw_10_Addr_A_orig = tmp_6_cast_fu_1775_p1;
end else begin
bufw_10_Addr_A_orig = 'bx;
end
end else begin
bufw_10_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufw_10_EN_A = 1'b1;
end else begin
bufw_10_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)))) begin
bufw_10_EN_B = 1'b1;
end else begin
bufw_10_EN_B = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
bufw_11_Addr_A_orig = tmp_330_cast_fu_1910_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufw_11_Addr_A_orig = tmp_6_cast_fu_1775_p1;
end else begin
bufw_11_Addr_A_orig = 'bx;
end
end else begin
bufw_11_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufw_11_EN_A = 1'b1;
end else begin
bufw_11_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)))) begin
bufw_11_EN_B = 1'b1;
end else begin
bufw_11_EN_B = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
bufw_12_Addr_A_orig = tmp_330_cast_fu_1910_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufw_12_Addr_A_orig = tmp_6_cast_fu_1775_p1;
end else begin
bufw_12_Addr_A_orig = 'bx;
end
end else begin
bufw_12_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufw_12_EN_A = 1'b1;
end else begin
bufw_12_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)))) begin
bufw_12_EN_B = 1'b1;
end else begin
bufw_12_EN_B = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
bufw_1_Addr_A_orig = tmp_330_cast_fu_1910_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufw_1_Addr_A_orig = tmp_6_cast_fu_1775_p1;
end else begin
bufw_1_Addr_A_orig = 'bx;
end
end else begin
bufw_1_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufw_1_EN_A = 1'b1;
end else begin
bufw_1_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)))) begin
bufw_1_EN_B = 1'b1;
end else begin
bufw_1_EN_B = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
bufw_2_Addr_A_orig = tmp_330_cast_fu_1910_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufw_2_Addr_A_orig = tmp_6_cast_fu_1775_p1;
end else begin
bufw_2_Addr_A_orig = 'bx;
end
end else begin
bufw_2_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufw_2_EN_A = 1'b1;
end else begin
bufw_2_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)))) begin
bufw_2_EN_B = 1'b1;
end else begin
bufw_2_EN_B = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
bufw_3_Addr_A_orig = tmp_330_cast_fu_1910_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufw_3_Addr_A_orig = tmp_6_cast_fu_1775_p1;
end else begin
bufw_3_Addr_A_orig = 'bx;
end
end else begin
bufw_3_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufw_3_EN_A = 1'b1;
end else begin
bufw_3_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)))) begin
bufw_3_EN_B = 1'b1;
end else begin
bufw_3_EN_B = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
bufw_4_Addr_A_orig = tmp_330_cast_fu_1910_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufw_4_Addr_A_orig = tmp_6_cast_fu_1775_p1;
end else begin
bufw_4_Addr_A_orig = 'bx;
end
end else begin
bufw_4_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufw_4_EN_A = 1'b1;
end else begin
bufw_4_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)))) begin
bufw_4_EN_B = 1'b1;
end else begin
bufw_4_EN_B = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
bufw_5_Addr_A_orig = tmp_330_cast_fu_1910_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufw_5_Addr_A_orig = tmp_6_cast_fu_1775_p1;
end else begin
bufw_5_Addr_A_orig = 'bx;
end
end else begin
bufw_5_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufw_5_EN_A = 1'b1;
end else begin
bufw_5_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)))) begin
bufw_5_EN_B = 1'b1;
end else begin
bufw_5_EN_B = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
bufw_6_Addr_A_orig = tmp_330_cast_fu_1910_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufw_6_Addr_A_orig = tmp_6_cast_fu_1775_p1;
end else begin
bufw_6_Addr_A_orig = 'bx;
end
end else begin
bufw_6_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufw_6_EN_A = 1'b1;
end else begin
bufw_6_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)))) begin
bufw_6_EN_B = 1'b1;
end else begin
bufw_6_EN_B = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
bufw_7_Addr_A_orig = tmp_330_cast_fu_1910_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufw_7_Addr_A_orig = tmp_6_cast_fu_1775_p1;
end else begin
bufw_7_Addr_A_orig = 'bx;
end
end else begin
bufw_7_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufw_7_EN_A = 1'b1;
end else begin
bufw_7_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)))) begin
bufw_7_EN_B = 1'b1;
end else begin
bufw_7_EN_B = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
bufw_8_Addr_A_orig = tmp_330_cast_fu_1910_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufw_8_Addr_A_orig = tmp_6_cast_fu_1775_p1;
end else begin
bufw_8_Addr_A_orig = 'bx;
end
end else begin
bufw_8_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufw_8_EN_A = 1'b1;
end else begin
bufw_8_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)))) begin
bufw_8_EN_B = 1'b1;
end else begin
bufw_8_EN_B = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter0)) begin
if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
bufw_9_Addr_A_orig = tmp_330_cast_fu_1910_p1;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
bufw_9_Addr_A_orig = tmp_6_cast_fu_1775_p1;
end else begin
bufw_9_Addr_A_orig = 'bx;
end
end else begin
bufw_9_Addr_A_orig = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage0_11001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
bufw_9_EN_A = 1'b1;
end else begin
bufw_9_EN_A = 1'b0;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage6_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter0)) | ((ap_block_pp0_stage5_11001 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter0)))) begin
bufw_9_EN_B = 1'b1;
end else begin
bufw_9_EN_B = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1003_p0 = tmp_20_3_2_1_reg_7784;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1003_p0 = tmp_20_1_2_1_reg_7654;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1003_p0 = tmp_20_3_2_reg_7264;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1003_p0 = tmp_20_1_2_reg_7134;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1003_p0 = tmp_297_fu_2537_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1003_p0 = tmp_217_fu_2433_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1003_p0 = tmp_137_fu_2329_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1003_p0 = tmp_57_fu_2225_p1;
end else begin
grp_fu_1003_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1003_p1 = ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1003_p1 = ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1003_p1 = ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1003_p1 = ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1003_p1 = tmp_19_7_2_reg_6094;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1003_p1 = tmp_19_5_2_reg_5769;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1003_p1 = tmp_19_3_2_reg_5444;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1003_p1 = tmp_19_1_2_reg_4989;
end else begin
grp_fu_1003_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1007_p0 = tmp_20_3_3_1_reg_7789;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1007_p0 = tmp_20_1_3_1_reg_7659;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1007_p0 = tmp_20_3_3_reg_7269;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1007_p0 = tmp_20_1_3_reg_7139;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1007_p0 = tmp_300_fu_2541_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1007_p0 = tmp_220_fu_2437_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1007_p0 = tmp_140_fu_2333_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1007_p0 = tmp_60_fu_2229_p1;
end else begin
grp_fu_1007_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1007_p1 = ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1007_p1 = ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1007_p1 = ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1007_p1 = ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1007_p1 = tmp_19_7_3_reg_6099;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1007_p1 = tmp_19_5_3_reg_5774;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1007_p1 = tmp_19_3_3_reg_5449;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1007_p1 = tmp_19_1_3_reg_4994;
end else begin
grp_fu_1007_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1011_p0 = tmp_20_3_4_1_reg_7794;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1011_p0 = tmp_20_1_4_1_reg_7664;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1011_p0 = tmp_20_3_4_reg_7274;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1011_p0 = tmp_20_1_4_reg_7144;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1011_p0 = tmp_303_fu_2545_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1011_p0 = tmp_223_fu_2441_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1011_p0 = tmp_143_fu_2337_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1011_p0 = tmp_63_fu_2233_p1;
end else begin
grp_fu_1011_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1011_p1 = ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1011_p1 = ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1011_p1 = ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1011_p1 = ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1011_p1 = tmp_19_7_4_reg_6104;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1011_p1 = tmp_19_5_4_reg_5779;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1011_p1 = tmp_19_3_4_reg_5454;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1011_p1 = tmp_19_1_4_reg_4999;
end else begin
grp_fu_1011_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1015_p0 = tmp_20_3_5_1_reg_7799;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1015_p0 = tmp_20_1_5_1_reg_7669;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1015_p0 = tmp_20_3_5_reg_7279;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1015_p0 = tmp_20_1_5_reg_7149;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1015_p0 = tmp_306_fu_2549_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1015_p0 = tmp_226_fu_2445_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1015_p0 = tmp_146_fu_2341_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1015_p0 = tmp_66_fu_2237_p1;
end else begin
grp_fu_1015_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1015_p1 = ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1015_p1 = ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1015_p1 = ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1015_p1 = ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1015_p1 = tmp_19_7_5_reg_6109;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1015_p1 = tmp_19_5_5_reg_5784;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1015_p1 = tmp_19_3_5_reg_5459;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1015_p1 = tmp_19_1_5_reg_5004;
end else begin
grp_fu_1015_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1019_p0 = tmp_20_3_6_1_reg_7804;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1019_p0 = tmp_20_1_6_1_reg_7674;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1019_p0 = tmp_20_3_6_reg_7284;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1019_p0 = tmp_20_1_6_reg_7154;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1019_p0 = tmp_309_fu_2553_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1019_p0 = tmp_229_fu_2449_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1019_p0 = tmp_149_fu_2345_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1019_p0 = tmp_69_fu_2241_p1;
end else begin
grp_fu_1019_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1019_p1 = ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1019_p1 = ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1019_p1 = ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1019_p1 = ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1019_p1 = tmp_19_7_6_reg_6114;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1019_p1 = tmp_19_5_6_reg_5789;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1019_p1 = tmp_19_3_6_reg_5464;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1019_p1 = tmp_19_1_6_reg_5009;
end else begin
grp_fu_1019_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1023_p0 = tmp_20_3_7_1_reg_7809;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1023_p0 = tmp_20_1_7_1_reg_7679;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1023_p0 = tmp_20_3_7_reg_7289;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1023_p0 = tmp_20_1_7_reg_7159;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1023_p0 = tmp_312_fu_2557_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1023_p0 = tmp_232_fu_2453_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1023_p0 = tmp_152_fu_2349_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1023_p0 = tmp_72_fu_2245_p1;
end else begin
grp_fu_1023_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1023_p1 = ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1023_p1 = ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1023_p1 = ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1023_p1 = ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1023_p1 = tmp_19_7_7_reg_6119;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1023_p1 = tmp_19_5_7_reg_5794;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1023_p1 = tmp_19_3_7_reg_5469;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1023_p1 = tmp_19_1_7_reg_5014;
end else begin
grp_fu_1023_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1027_p0 = tmp_20_3_8_1_reg_7814;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1027_p0 = tmp_20_1_8_1_reg_7684;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1027_p0 = tmp_20_3_8_reg_7294;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1027_p0 = tmp_20_1_8_reg_7164;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1027_p0 = tmp_315_fu_2561_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1027_p0 = tmp_235_fu_2457_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1027_p0 = tmp_155_fu_2353_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1027_p0 = tmp_75_fu_2249_p1;
end else begin
grp_fu_1027_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1027_p1 = ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1027_p1 = ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1027_p1 = ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1027_p1 = ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1027_p1 = tmp_19_7_8_reg_6124;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1027_p1 = tmp_19_5_8_reg_5799;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1027_p1 = tmp_19_3_8_reg_5474;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1027_p1 = tmp_19_1_8_reg_5019;
end else begin
grp_fu_1027_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1031_p0 = tmp_20_3_9_1_reg_7819;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1031_p0 = tmp_20_1_9_1_reg_7689;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1031_p0 = tmp_20_3_9_reg_7299;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1031_p0 = tmp_20_1_9_reg_7169;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1031_p0 = tmp_318_fu_2565_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1031_p0 = tmp_238_fu_2461_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1031_p0 = tmp_158_fu_2357_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1031_p0 = tmp_78_fu_2253_p1;
end else begin
grp_fu_1031_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1031_p1 = ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1031_p1 = ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1031_p1 = ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1031_p1 = ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1031_p1 = tmp_19_7_9_reg_6129;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1031_p1 = tmp_19_5_9_reg_5804;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1031_p1 = tmp_19_3_9_reg_5479;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1031_p1 = tmp_19_1_9_reg_5024;
end else begin
grp_fu_1031_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1035_p0 = tmp_20_3_10_1_reg_7824;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1035_p0 = tmp_20_1_10_1_reg_7694;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1035_p0 = tmp_20_3_s_reg_7304;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1035_p0 = tmp_20_1_s_reg_7174;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1035_p0 = tmp_321_fu_2569_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1035_p0 = tmp_241_fu_2465_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1035_p0 = tmp_161_fu_2361_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1035_p0 = tmp_81_fu_2257_p1;
end else begin
grp_fu_1035_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1035_p1 = ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1035_p1 = ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1035_p1 = ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1035_p1 = ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1035_p1 = tmp_19_7_s_reg_6134;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1035_p1 = tmp_19_5_s_reg_5809;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1035_p1 = tmp_19_3_s_reg_5484;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1035_p1 = tmp_19_1_s_reg_5029;
end else begin
grp_fu_1035_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1039_p0 = tmp_20_3_11_1_reg_7829;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1039_p0 = tmp_20_1_11_1_reg_7699;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1039_p0 = tmp_20_3_10_reg_7309;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1039_p0 = tmp_20_1_10_reg_7179;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1039_p0 = tmp_324_fu_2573_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1039_p0 = tmp_244_fu_2469_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1039_p0 = tmp_164_fu_2365_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1039_p0 = tmp_84_fu_2261_p1;
end else begin
grp_fu_1039_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1039_p1 = ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1039_p1 = ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1039_p1 = ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1039_p1 = ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1039_p1 = tmp_19_7_10_reg_6139;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1039_p1 = tmp_19_5_10_reg_5814;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1039_p1 = tmp_19_3_10_reg_5489;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1039_p1 = tmp_19_1_10_reg_5034;
end else begin
grp_fu_1039_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1043_p0 = tmp_20_3_12_1_reg_7834;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1043_p0 = tmp_20_1_12_1_reg_7704;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1043_p0 = tmp_20_3_11_reg_7314;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1043_p0 = tmp_20_1_11_reg_7184;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1043_p0 = tmp_327_fu_2577_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1043_p0 = tmp_247_fu_2473_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1043_p0 = tmp_167_fu_2369_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1043_p0 = tmp_87_fu_2265_p1;
end else begin
grp_fu_1043_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1043_p1 = ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1043_p1 = ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1043_p1 = ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_1043_p1 = ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1043_p1 = tmp_19_7_11_reg_6144;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1043_p1 = tmp_19_5_11_reg_5819;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1043_p1 = tmp_19_3_11_reg_5494;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_1043_p1 = tmp_19_1_11_reg_5039;
end else begin
grp_fu_1043_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1047_p0 = tmp_20_7_0_1_reg_8034;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1047_p0 = tmp_20_6_0_1_reg_7969;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1047_p0 = tmp_20_5_0_1_reg_7904;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1047_p0 = tmp_20_4_0_1_reg_7839;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1047_p0 = tmp_20_7_reg_7514;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1047_p0 = tmp_20_6_reg_7449;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1047_p0 = tmp_20_5_reg_7384;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1047_p0 = tmp_20_4_reg_7319;
end else begin
grp_fu_1047_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1047_p1 = ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1047_p1 = ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1047_p1 = ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1047_p1 = ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1047_p1 = ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1047_p1 = ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1047_p1 = ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1047_p1 = ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149;
end else begin
grp_fu_1047_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1051_p0 = tmp_20_7_1_1_reg_8039;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1051_p0 = tmp_20_6_1_1_reg_7974;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1051_p0 = tmp_20_5_1_1_reg_7909;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1051_p0 = tmp_20_4_1_1_reg_7844;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1051_p0 = tmp_20_7_1_reg_7519;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1051_p0 = tmp_20_6_1_reg_7454;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1051_p0 = tmp_20_5_1_reg_7389;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1051_p0 = tmp_20_4_1_reg_7324;
end else begin
grp_fu_1051_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1051_p1 = ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1051_p1 = ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1051_p1 = ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1051_p1 = ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1051_p1 = ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1051_p1 = ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1051_p1 = ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1051_p1 = ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154;
end else begin
grp_fu_1051_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1055_p0 = tmp_20_7_2_1_reg_8044;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1055_p0 = tmp_20_6_2_1_reg_7979;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1055_p0 = tmp_20_5_2_1_reg_7914;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1055_p0 = tmp_20_4_2_1_reg_7849;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1055_p0 = tmp_20_7_2_reg_7524;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1055_p0 = tmp_20_6_2_reg_7459;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1055_p0 = tmp_20_5_2_reg_7394;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1055_p0 = tmp_20_4_2_reg_7329;
end else begin
grp_fu_1055_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1055_p1 = ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1055_p1 = ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1055_p1 = ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1055_p1 = ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1055_p1 = ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1055_p1 = ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1055_p1 = ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1055_p1 = ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159;
end else begin
grp_fu_1055_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1059_p0 = tmp_20_7_3_1_reg_8049;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1059_p0 = tmp_20_6_3_1_reg_7984;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1059_p0 = tmp_20_5_3_1_reg_7919;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1059_p0 = tmp_20_4_3_1_reg_7854;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1059_p0 = tmp_20_7_3_reg_7529;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1059_p0 = tmp_20_6_3_reg_7464;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1059_p0 = tmp_20_5_3_reg_7399;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1059_p0 = tmp_20_4_3_reg_7334;
end else begin
grp_fu_1059_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1059_p1 = ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1059_p1 = ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1059_p1 = ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1059_p1 = ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1059_p1 = ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1059_p1 = ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1059_p1 = ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1059_p1 = ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164;
end else begin
grp_fu_1059_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1063_p0 = tmp_20_7_4_1_reg_8054;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1063_p0 = tmp_20_6_4_1_reg_7989;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1063_p0 = tmp_20_5_4_1_reg_7924;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1063_p0 = tmp_20_4_4_1_reg_7859;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1063_p0 = tmp_20_7_4_reg_7534;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1063_p0 = tmp_20_6_4_reg_7469;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1063_p0 = tmp_20_5_4_reg_7404;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1063_p0 = tmp_20_4_4_reg_7339;
end else begin
grp_fu_1063_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1063_p1 = ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1063_p1 = ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1063_p1 = ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1063_p1 = ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1063_p1 = ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1063_p1 = ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1063_p1 = ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1063_p1 = ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169;
end else begin
grp_fu_1063_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1067_p0 = tmp_20_7_5_1_reg_8059;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1067_p0 = tmp_20_6_5_1_reg_7994;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1067_p0 = tmp_20_5_5_1_reg_7929;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1067_p0 = tmp_20_4_5_1_reg_7864;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1067_p0 = tmp_20_7_5_reg_7539;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1067_p0 = tmp_20_6_5_reg_7474;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1067_p0 = tmp_20_5_5_reg_7409;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1067_p0 = tmp_20_4_5_reg_7344;
end else begin
grp_fu_1067_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1067_p1 = ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1067_p1 = ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1067_p1 = ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1067_p1 = ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1067_p1 = ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1067_p1 = ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1067_p1 = ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1067_p1 = ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174;
end else begin
grp_fu_1067_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1071_p0 = tmp_20_7_6_1_reg_8064;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1071_p0 = tmp_20_6_6_1_reg_7999;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1071_p0 = tmp_20_5_6_1_reg_7934;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1071_p0 = tmp_20_4_6_1_reg_7869;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1071_p0 = tmp_20_7_6_reg_7544;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1071_p0 = tmp_20_6_6_reg_7479;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1071_p0 = tmp_20_5_6_reg_7414;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1071_p0 = tmp_20_4_6_reg_7349;
end else begin
grp_fu_1071_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1071_p1 = ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1071_p1 = ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1071_p1 = ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1071_p1 = ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1071_p1 = ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1071_p1 = ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1071_p1 = ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1071_p1 = ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179;
end else begin
grp_fu_1071_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1075_p0 = tmp_20_7_7_1_reg_8069;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1075_p0 = tmp_20_6_7_1_reg_8004;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1075_p0 = tmp_20_5_7_1_reg_7939;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1075_p0 = tmp_20_4_7_1_reg_7874;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1075_p0 = tmp_20_7_7_reg_7549;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1075_p0 = tmp_20_6_7_reg_7484;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1075_p0 = tmp_20_5_7_reg_7419;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1075_p0 = tmp_20_4_7_reg_7354;
end else begin
grp_fu_1075_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1075_p1 = ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1075_p1 = ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1075_p1 = ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1075_p1 = ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1075_p1 = ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1075_p1 = ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1075_p1 = ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1075_p1 = ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184;
end else begin
grp_fu_1075_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1079_p0 = tmp_20_7_8_1_reg_8074;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1079_p0 = tmp_20_6_8_1_reg_8009;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1079_p0 = tmp_20_5_8_1_reg_7944;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1079_p0 = tmp_20_4_8_1_reg_7879;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1079_p0 = tmp_20_7_8_reg_7554;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1079_p0 = tmp_20_6_8_reg_7489;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1079_p0 = tmp_20_5_8_reg_7424;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1079_p0 = tmp_20_4_8_reg_7359;
end else begin
grp_fu_1079_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1079_p1 = ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1079_p1 = ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1079_p1 = ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1079_p1 = ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1079_p1 = ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1079_p1 = ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1079_p1 = ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1079_p1 = ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189;
end else begin
grp_fu_1079_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1083_p0 = tmp_20_7_9_1_reg_8079;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1083_p0 = tmp_20_6_9_1_reg_8014;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1083_p0 = tmp_20_5_9_1_reg_7949;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1083_p0 = tmp_20_4_9_1_reg_7884;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1083_p0 = tmp_20_7_9_reg_7559;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1083_p0 = tmp_20_6_9_reg_7494;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1083_p0 = tmp_20_5_9_reg_7429;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1083_p0 = tmp_20_4_9_reg_7364;
end else begin
grp_fu_1083_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1083_p1 = ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1083_p1 = ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1083_p1 = ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1083_p1 = ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1083_p1 = ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1083_p1 = ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1083_p1 = ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1083_p1 = ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194;
end else begin
grp_fu_1083_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1087_p0 = tmp_20_7_10_1_reg_8084;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1087_p0 = tmp_20_6_10_1_reg_8019;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1087_p0 = tmp_20_5_10_1_reg_7954;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1087_p0 = tmp_20_4_10_1_reg_7889;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1087_p0 = tmp_20_7_s_reg_7564;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1087_p0 = tmp_20_6_s_reg_7499;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1087_p0 = tmp_20_5_s_reg_7434;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1087_p0 = tmp_20_4_s_reg_7369;
end else begin
grp_fu_1087_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1087_p1 = ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1087_p1 = ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1087_p1 = ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1087_p1 = ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1087_p1 = ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1087_p1 = ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1087_p1 = ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1087_p1 = ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199;
end else begin
grp_fu_1087_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1091_p0 = tmp_20_7_11_1_reg_8089;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1091_p0 = tmp_20_6_11_1_reg_8024;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1091_p0 = tmp_20_5_11_1_reg_7959;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1091_p0 = tmp_20_4_11_1_reg_7894;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1091_p0 = tmp_20_7_10_reg_7569;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1091_p0 = tmp_20_6_10_reg_7504;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1091_p0 = tmp_20_5_10_reg_7439;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1091_p0 = tmp_20_4_10_reg_7374;
end else begin
grp_fu_1091_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1091_p1 = ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1091_p1 = ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1091_p1 = ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1091_p1 = ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1091_p1 = ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1091_p1 = ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1091_p1 = ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1091_p1 = ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204;
end else begin
grp_fu_1091_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1095_p0 = tmp_20_7_12_1_reg_8094;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1095_p0 = tmp_20_6_12_1_reg_8029;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1095_p0 = tmp_20_5_12_1_reg_7964;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1095_p0 = tmp_20_4_12_1_reg_7899;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1095_p0 = tmp_20_7_11_reg_7574;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1095_p0 = tmp_20_6_11_reg_7509;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1095_p0 = tmp_20_5_11_reg_7444;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1095_p0 = tmp_20_4_11_reg_7379;
end else begin
grp_fu_1095_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1095_p1 = ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
grp_fu_1095_p1 = ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1095_p1 = ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_1095_p1 = ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1095_p1 = ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1095_p1 = ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1095_p1 = ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
grp_fu_1095_p1 = ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209;
end else begin
grp_fu_1095_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1099_p0 = bufw_0_load_2_reg_4012;
end else if ((((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1099_p0 = bufw_0_load_1_reg_3710;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1099_p0 = bufw_0_load_reg_3686;
end else begin
grp_fu_1099_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1099_p1 = bufi_2_load_5_reg_4290;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1099_p1 = bufi_2_load_2_reg_4137;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1099_p1 = bufi_2_load_reg_3735;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1099_p1 = bufi_1_load_4_reg_4222;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1099_p1 = bufi_1_load_3_reg_4171;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1099_p1 = bufi_1_load_2_reg_4120;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1099_p1 = bufi_1_load_1_reg_3948;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1099_p1 = bufi_0_load_reg_3693;
end else begin
grp_fu_1099_p1 = 'bx;
end
end else begin
grp_fu_1099_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1103_p0 = bufw_1_load_2_reg_4019;
end else if ((((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1103_p0 = bufw_1_load_1_reg_3759;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1103_p0 = bufw_0_load_1_reg_3710;
end else begin
grp_fu_1103_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1103_p1 = bufi_2_load_5_reg_4290;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1103_p1 = bufi_2_load_2_reg_4137;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1103_p1 = bufi_2_load_reg_3735;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1103_p1 = bufi_1_load_4_reg_4222;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1103_p1 = bufi_1_load_3_reg_4171;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1103_p1 = bufi_1_load_2_reg_4120;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1103_p1 = bufi_1_load_1_reg_3948;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1103_p1 = bufi_1_load_reg_3718;
end else begin
grp_fu_1103_p1 = 'bx;
end
end else begin
grp_fu_1103_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1107_p0 = bufw_2_load_2_reg_4026;
end else if ((((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1107_p0 = bufw_2_load_1_reg_3774;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1107_p0 = bufw_1_load_reg_3752;
end else begin
grp_fu_1107_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1107_p1 = bufi_2_load_5_reg_4290;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1107_p1 = bufi_2_load_2_reg_4137;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1107_p1 = bufi_2_load_reg_3735;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1107_p1 = bufi_1_load_4_reg_4222;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1107_p1 = bufi_1_load_3_reg_4171;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1107_p1 = bufi_1_load_2_reg_4120;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1107_p1 = bufi_1_load_1_reg_3948;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1107_p1 = bufi_0_load_reg_3693;
end else begin
grp_fu_1107_p1 = 'bx;
end
end else begin
grp_fu_1107_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1111_p0 = bufw_3_load_2_reg_4033;
end else if ((((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1111_p0 = bufw_3_load_1_reg_3789;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1111_p0 = bufw_1_load_1_reg_3759;
end else begin
grp_fu_1111_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1111_p1 = bufi_2_load_5_reg_4290;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1111_p1 = bufi_2_load_2_reg_4137;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1111_p1 = bufi_2_load_reg_3735;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1111_p1 = bufi_1_load_4_reg_4222;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1111_p1 = bufi_1_load_3_reg_4171;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1111_p1 = bufi_1_load_2_reg_4120;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1111_p1 = bufi_1_load_1_reg_3948;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1111_p1 = bufi_1_load_reg_3718;
end else begin
grp_fu_1111_p1 = 'bx;
end
end else begin
grp_fu_1111_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1115_p0 = bufw_4_load_2_reg_4040;
end else if ((((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1115_p0 = bufw_4_load_1_reg_3804;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1115_p0 = bufw_2_load_reg_3767;
end else begin
grp_fu_1115_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1115_p1 = bufi_2_load_5_reg_4290;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1115_p1 = bufi_2_load_2_reg_4137;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1115_p1 = bufi_2_load_reg_3735;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1115_p1 = bufi_1_load_4_reg_4222;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1115_p1 = bufi_1_load_3_reg_4171;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1115_p1 = bufi_1_load_2_reg_4120;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1115_p1 = bufi_1_load_1_reg_3948;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1115_p1 = bufi_0_load_reg_3693;
end else begin
grp_fu_1115_p1 = 'bx;
end
end else begin
grp_fu_1115_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1119_p0 = bufw_5_load_2_reg_4047;
end else if ((((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1119_p0 = bufw_5_load_1_reg_3819;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1119_p0 = bufw_2_load_1_reg_3774;
end else begin
grp_fu_1119_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1119_p1 = bufi_2_load_5_reg_4290;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1119_p1 = bufi_2_load_2_reg_4137;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1119_p1 = bufi_2_load_reg_3735;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1119_p1 = bufi_1_load_4_reg_4222;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1119_p1 = bufi_1_load_3_reg_4171;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1119_p1 = bufi_1_load_2_reg_4120;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1119_p1 = bufi_1_load_1_reg_3948;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1119_p1 = bufi_1_load_reg_3718;
end else begin
grp_fu_1119_p1 = 'bx;
end
end else begin
grp_fu_1119_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1123_p0 = bufw_6_load_2_reg_4054;
end else if ((((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1123_p0 = bufw_6_load_1_reg_3834;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1123_p0 = bufw_3_load_reg_3782;
end else begin
grp_fu_1123_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1123_p1 = bufi_2_load_5_reg_4290;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1123_p1 = bufi_2_load_2_reg_4137;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1123_p1 = bufi_2_load_reg_3735;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1123_p1 = bufi_1_load_4_reg_4222;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1123_p1 = bufi_1_load_3_reg_4171;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1123_p1 = bufi_1_load_2_reg_4120;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1123_p1 = bufi_1_load_1_reg_3948;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1123_p1 = bufi_0_load_reg_3693;
end else begin
grp_fu_1123_p1 = 'bx;
end
end else begin
grp_fu_1123_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1127_p0 = bufw_7_load_2_reg_4061;
end else if ((((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1127_p0 = bufw_7_load_1_reg_3849;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1127_p0 = bufw_3_load_1_reg_3789;
end else begin
grp_fu_1127_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1127_p1 = bufi_2_load_5_reg_4290;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1127_p1 = bufi_2_load_2_reg_4137;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1127_p1 = bufi_2_load_reg_3735;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1127_p1 = bufi_1_load_4_reg_4222;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1127_p1 = bufi_1_load_3_reg_4171;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1127_p1 = bufi_1_load_2_reg_4120;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1127_p1 = bufi_1_load_1_reg_3948;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1127_p1 = bufi_1_load_reg_3718;
end else begin
grp_fu_1127_p1 = 'bx;
end
end else begin
grp_fu_1127_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1131_p0 = bufw_8_load_2_reg_4068;
end else if ((((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1131_p0 = bufw_8_load_1_reg_3864;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1131_p0 = bufw_4_load_reg_3797;
end else begin
grp_fu_1131_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1131_p1 = bufi_2_load_5_reg_4290;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1131_p1 = bufi_2_load_2_reg_4137;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1131_p1 = bufi_2_load_reg_3735;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1131_p1 = bufi_1_load_4_reg_4222;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1131_p1 = bufi_1_load_3_reg_4171;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1131_p1 = bufi_1_load_2_reg_4120;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1131_p1 = bufi_1_load_1_reg_3948;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1131_p1 = bufi_0_load_reg_3693;
end else begin
grp_fu_1131_p1 = 'bx;
end
end else begin
grp_fu_1131_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1135_p0 = bufw_9_load_2_reg_4075;
end else if ((((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1135_p0 = bufw_9_load_1_reg_3879;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1135_p0 = bufw_4_load_1_reg_3804;
end else begin
grp_fu_1135_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1135_p1 = bufi_2_load_5_reg_4290;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1135_p1 = bufi_2_load_2_reg_4137;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1135_p1 = bufi_2_load_reg_3735;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1135_p1 = bufi_1_load_4_reg_4222;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1135_p1 = bufi_1_load_3_reg_4171;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1135_p1 = bufi_1_load_2_reg_4120;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1135_p1 = bufi_1_load_1_reg_3948;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1135_p1 = bufi_1_load_reg_3718;
end else begin
grp_fu_1135_p1 = 'bx;
end
end else begin
grp_fu_1135_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1139_p0 = bufw_10_load_2_reg_4082;
end else if ((((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1139_p0 = bufw_10_load_1_reg_3894;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1139_p0 = bufw_5_load_reg_3812;
end else begin
grp_fu_1139_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1139_p1 = bufi_2_load_5_reg_4290;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1139_p1 = bufi_2_load_2_reg_4137;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1139_p1 = bufi_2_load_reg_3735;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1139_p1 = bufi_1_load_4_reg_4222;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1139_p1 = bufi_1_load_3_reg_4171;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1139_p1 = bufi_1_load_2_reg_4120;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1139_p1 = bufi_1_load_1_reg_3948;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1139_p1 = bufi_0_load_reg_3693;
end else begin
grp_fu_1139_p1 = 'bx;
end
end else begin
grp_fu_1139_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1143_p0 = bufw_11_load_2_reg_4089;
end else if ((((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1143_p0 = bufw_11_load_1_reg_3909;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1143_p0 = bufw_5_load_1_reg_3819;
end else begin
grp_fu_1143_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1143_p1 = bufi_2_load_5_reg_4290;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1143_p1 = bufi_2_load_2_reg_4137;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1143_p1 = bufi_2_load_reg_3735;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1143_p1 = bufi_1_load_4_reg_4222;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1143_p1 = bufi_1_load_3_reg_4171;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1143_p1 = bufi_1_load_2_reg_4120;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1143_p1 = bufi_1_load_1_reg_3948;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1143_p1 = bufi_1_load_reg_3718;
end else begin
grp_fu_1143_p1 = 'bx;
end
end else begin
grp_fu_1143_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1147_p0 = bufw_12_load_2_reg_4096;
end else if ((((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1147_p0 = bufw_12_load_1_reg_3924;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1147_p0 = bufw_6_load_reg_3827;
end else begin
grp_fu_1147_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1147_p1 = bufi_2_load_5_reg_4290;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1147_p1 = bufi_2_load_2_reg_4137;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1147_p1 = bufi_2_load_reg_3735;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1147_p1 = bufi_1_load_4_reg_4222;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1147_p1 = bufi_1_load_3_reg_4171;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1147_p1 = bufi_1_load_2_reg_4120;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1147_p1 = bufi_1_load_1_reg_3948;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1147_p1 = bufi_0_load_reg_3693;
end else begin
grp_fu_1147_p1 = 'bx;
end
end else begin
grp_fu_1147_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1151_p0 = bufw_0_load_2_reg_4012;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1151_p0 = bufw_0_load_1_reg_3710;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1151_p0 = bufw_0_load_reg_3686;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1151_p0 = bufw_6_load_1_reg_3834;
end else begin
grp_fu_1151_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1151_p1 = bufi_2_load_6_reg_4361;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1151_p1 = bufi_2_load_3_reg_4188;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1151_p1 = bufi_2_load_1_reg_3965;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1151_p1 = bufi_1_load_5_reg_4273;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1151_p1 = bufi_0_load_6_reg_4327;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1151_p1 = bufi_0_load_4_reg_4205;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1151_p1 = bufi_0_load_2_reg_4103;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1151_p1 = bufi_1_load_reg_3718;
end else begin
grp_fu_1151_p1 = 'bx;
end
end else begin
grp_fu_1151_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1155_p0 = bufw_1_load_2_reg_4019;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1155_p0 = bufw_1_load_1_reg_3759;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1155_p0 = bufw_1_load_reg_3752;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1155_p0 = bufw_7_load_reg_3842;
end else begin
grp_fu_1155_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1155_p1 = bufi_2_load_6_reg_4361;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1155_p1 = bufi_2_load_3_reg_4188;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1155_p1 = bufi_2_load_1_reg_3965;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1155_p1 = bufi_1_load_5_reg_4273;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1155_p1 = bufi_0_load_6_reg_4327;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1155_p1 = bufi_0_load_4_reg_4205;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1155_p1 = bufi_0_load_2_reg_4103;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1155_p1 = bufi_0_load_reg_3693;
end else begin
grp_fu_1155_p1 = 'bx;
end
end else begin
grp_fu_1155_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1159_p0 = bufw_2_load_2_reg_4026;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1159_p0 = bufw_2_load_1_reg_3774;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1159_p0 = bufw_2_load_reg_3767;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1159_p0 = bufw_7_load_1_reg_3849;
end else begin
grp_fu_1159_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1159_p1 = bufi_2_load_6_reg_4361;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1159_p1 = bufi_2_load_3_reg_4188;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1159_p1 = bufi_2_load_1_reg_3965;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1159_p1 = bufi_1_load_5_reg_4273;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1159_p1 = bufi_0_load_6_reg_4327;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1159_p1 = bufi_0_load_4_reg_4205;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1159_p1 = bufi_0_load_2_reg_4103;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1159_p1 = bufi_1_load_reg_3718;
end else begin
grp_fu_1159_p1 = 'bx;
end
end else begin
grp_fu_1159_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1163_p0 = bufw_3_load_2_reg_4033;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1163_p0 = bufw_3_load_1_reg_3789;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1163_p0 = bufw_3_load_reg_3782;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1163_p0 = bufw_8_load_reg_3857;
end else begin
grp_fu_1163_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1163_p1 = bufi_2_load_6_reg_4361;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1163_p1 = bufi_2_load_3_reg_4188;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1163_p1 = bufi_2_load_1_reg_3965;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1163_p1 = bufi_1_load_5_reg_4273;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1163_p1 = bufi_0_load_6_reg_4327;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1163_p1 = bufi_0_load_4_reg_4205;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1163_p1 = bufi_0_load_2_reg_4103;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1163_p1 = bufi_0_load_reg_3693;
end else begin
grp_fu_1163_p1 = 'bx;
end
end else begin
grp_fu_1163_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1167_p0 = bufw_4_load_2_reg_4040;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1167_p0 = bufw_4_load_1_reg_3804;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1167_p0 = bufw_4_load_reg_3797;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1167_p0 = bufw_8_load_1_reg_3864;
end else begin
grp_fu_1167_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1167_p1 = bufi_2_load_6_reg_4361;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1167_p1 = bufi_2_load_3_reg_4188;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1167_p1 = bufi_2_load_1_reg_3965;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1167_p1 = bufi_1_load_5_reg_4273;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1167_p1 = bufi_0_load_6_reg_4327;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1167_p1 = bufi_0_load_4_reg_4205;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1167_p1 = bufi_0_load_2_reg_4103;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1167_p1 = bufi_1_load_reg_3718;
end else begin
grp_fu_1167_p1 = 'bx;
end
end else begin
grp_fu_1167_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1171_p0 = bufw_5_load_2_reg_4047;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1171_p0 = bufw_5_load_1_reg_3819;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1171_p0 = bufw_5_load_reg_3812;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1171_p0 = bufw_9_load_reg_3872;
end else begin
grp_fu_1171_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1171_p1 = bufi_2_load_6_reg_4361;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1171_p1 = bufi_2_load_3_reg_4188;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1171_p1 = bufi_2_load_1_reg_3965;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1171_p1 = bufi_1_load_5_reg_4273;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1171_p1 = bufi_0_load_6_reg_4327;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1171_p1 = bufi_0_load_4_reg_4205;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1171_p1 = bufi_0_load_2_reg_4103;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1171_p1 = bufi_0_load_reg_3693;
end else begin
grp_fu_1171_p1 = 'bx;
end
end else begin
grp_fu_1171_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1175_p0 = bufw_6_load_2_reg_4054;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1175_p0 = bufw_6_load_1_reg_3834;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1175_p0 = bufw_6_load_reg_3827;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1175_p0 = bufw_9_load_1_reg_3879;
end else begin
grp_fu_1175_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1175_p1 = bufi_2_load_6_reg_4361;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1175_p1 = bufi_2_load_3_reg_4188;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1175_p1 = bufi_2_load_1_reg_3965;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1175_p1 = bufi_1_load_5_reg_4273;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1175_p1 = bufi_0_load_6_reg_4327;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1175_p1 = bufi_0_load_4_reg_4205;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1175_p1 = bufi_0_load_2_reg_4103;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1175_p1 = bufi_1_load_reg_3718;
end else begin
grp_fu_1175_p1 = 'bx;
end
end else begin
grp_fu_1175_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1179_p0 = bufw_7_load_2_reg_4061;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1179_p0 = bufw_7_load_1_reg_3849;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1179_p0 = bufw_7_load_reg_3842;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1179_p0 = bufw_10_load_reg_3887;
end else begin
grp_fu_1179_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1179_p1 = bufi_2_load_6_reg_4361;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1179_p1 = bufi_2_load_3_reg_4188;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1179_p1 = bufi_2_load_1_reg_3965;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1179_p1 = bufi_1_load_5_reg_4273;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1179_p1 = bufi_0_load_6_reg_4327;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1179_p1 = bufi_0_load_4_reg_4205;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1179_p1 = bufi_0_load_2_reg_4103;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1179_p1 = bufi_0_load_reg_3693;
end else begin
grp_fu_1179_p1 = 'bx;
end
end else begin
grp_fu_1179_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1183_p0 = bufw_8_load_2_reg_4068;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1183_p0 = bufw_8_load_1_reg_3864;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1183_p0 = bufw_8_load_reg_3857;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1183_p0 = bufw_10_load_1_reg_3894;
end else begin
grp_fu_1183_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1183_p1 = bufi_2_load_6_reg_4361;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1183_p1 = bufi_2_load_3_reg_4188;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1183_p1 = bufi_2_load_1_reg_3965;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1183_p1 = bufi_1_load_5_reg_4273;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1183_p1 = bufi_0_load_6_reg_4327;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1183_p1 = bufi_0_load_4_reg_4205;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1183_p1 = bufi_0_load_2_reg_4103;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1183_p1 = bufi_1_load_reg_3718;
end else begin
grp_fu_1183_p1 = 'bx;
end
end else begin
grp_fu_1183_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1187_p0 = bufw_9_load_2_reg_4075;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1187_p0 = bufw_9_load_1_reg_3879;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1187_p0 = bufw_9_load_reg_3872;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1187_p0 = bufw_11_load_reg_3902;
end else begin
grp_fu_1187_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1187_p1 = bufi_2_load_6_reg_4361;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1187_p1 = bufi_2_load_3_reg_4188;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1187_p1 = bufi_2_load_1_reg_3965;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1187_p1 = bufi_1_load_5_reg_4273;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1187_p1 = bufi_0_load_6_reg_4327;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1187_p1 = bufi_0_load_4_reg_4205;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1187_p1 = bufi_0_load_2_reg_4103;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1187_p1 = bufi_0_load_reg_3693;
end else begin
grp_fu_1187_p1 = 'bx;
end
end else begin
grp_fu_1187_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1191_p0 = bufw_10_load_2_reg_4082;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1191_p0 = bufw_10_load_1_reg_3894;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1191_p0 = bufw_10_load_reg_3887;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1191_p0 = bufw_11_load_1_reg_3909;
end else begin
grp_fu_1191_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1191_p1 = bufi_2_load_6_reg_4361;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1191_p1 = bufi_2_load_3_reg_4188;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1191_p1 = bufi_2_load_1_reg_3965;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1191_p1 = bufi_1_load_5_reg_4273;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1191_p1 = bufi_0_load_6_reg_4327;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1191_p1 = bufi_0_load_4_reg_4205;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1191_p1 = bufi_0_load_2_reg_4103;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1191_p1 = bufi_1_load_reg_3718;
end else begin
grp_fu_1191_p1 = 'bx;
end
end else begin
grp_fu_1191_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1195_p0 = bufw_11_load_2_reg_4089;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1195_p0 = bufw_11_load_1_reg_3909;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1195_p0 = bufw_11_load_reg_3902;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1195_p0 = bufw_12_load_reg_3917;
end else begin
grp_fu_1195_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1195_p1 = bufi_2_load_6_reg_4361;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1195_p1 = bufi_2_load_3_reg_4188;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1195_p1 = bufi_2_load_1_reg_3965;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1195_p1 = bufi_1_load_5_reg_4273;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1195_p1 = bufi_0_load_6_reg_4327;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1195_p1 = bufi_0_load_4_reg_4205;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1195_p1 = bufi_0_load_2_reg_4103;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1195_p1 = bufi_0_load_reg_3693;
end else begin
grp_fu_1195_p1 = 'bx;
end
end else begin
grp_fu_1195_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)) | ((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)))) begin
grp_fu_1199_p0 = bufw_12_load_2_reg_4096;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)))) begin
grp_fu_1199_p0 = bufw_12_load_reg_3917;
end else if ((((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)) | ((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
grp_fu_1199_p0 = bufw_12_load_1_reg_3924;
end else begin
grp_fu_1199_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1199_p1 = bufi_2_load_6_reg_4361;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1199_p1 = bufi_2_load_3_reg_4188;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1199_p1 = bufi_2_load_1_reg_3965;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1199_p1 = bufi_1_load_5_reg_4273;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1199_p1 = bufi_0_load_6_reg_4327;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1199_p1 = bufi_0_load_4_reg_4205;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1199_p1 = bufi_0_load_2_reg_4103;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1199_p1 = bufi_1_load_reg_3718;
end else begin
grp_fu_1199_p1 = 'bx;
end
end else begin
grp_fu_1199_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin
grp_fu_1203_p0 = bufw_0_load_2_reg_4012;
end else if ((((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)))) begin
grp_fu_1203_p0 = bufw_0_load_1_reg_3710;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
grp_fu_1203_p0 = bufw_0_load_reg_3686;
end else begin
grp_fu_1203_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1203_p1 = bufi_2_load_7_reg_4412;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1203_p1 = bufi_2_load_4_reg_4239;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1203_p1 = bufi_1_load_7_reg_4395;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1203_p1 = bufi_1_load_6_reg_4344;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1203_p1 = bufi_0_load_7_reg_4378;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1203_p1 = bufi_0_load_5_reg_4256;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1203_p1 = bufi_0_load_3_reg_4154;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1203_p1 = bufi_0_load_1_reg_3931;
end else begin
grp_fu_1203_p1 = 'bx;
end
end else begin
grp_fu_1203_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin
grp_fu_1207_p0 = bufw_1_load_2_reg_4019;
end else if ((((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)))) begin
grp_fu_1207_p0 = bufw_1_load_1_reg_3759;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
grp_fu_1207_p0 = bufw_1_load_reg_3752;
end else begin
grp_fu_1207_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1207_p1 = bufi_2_load_7_reg_4412;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1207_p1 = bufi_2_load_4_reg_4239;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1207_p1 = bufi_1_load_7_reg_4395;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1207_p1 = bufi_1_load_6_reg_4344;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1207_p1 = bufi_0_load_7_reg_4378;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1207_p1 = bufi_0_load_5_reg_4256;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1207_p1 = bufi_0_load_3_reg_4154;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1207_p1 = bufi_0_load_1_reg_3931;
end else begin
grp_fu_1207_p1 = 'bx;
end
end else begin
grp_fu_1207_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin
grp_fu_1211_p0 = bufw_2_load_2_reg_4026;
end else if ((((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)))) begin
grp_fu_1211_p0 = bufw_2_load_1_reg_3774;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
grp_fu_1211_p0 = bufw_2_load_reg_3767;
end else begin
grp_fu_1211_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1211_p1 = bufi_2_load_7_reg_4412;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1211_p1 = bufi_2_load_4_reg_4239;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1211_p1 = bufi_1_load_7_reg_4395;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1211_p1 = bufi_1_load_6_reg_4344;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1211_p1 = bufi_0_load_7_reg_4378;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1211_p1 = bufi_0_load_5_reg_4256;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1211_p1 = bufi_0_load_3_reg_4154;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1211_p1 = bufi_0_load_1_reg_3931;
end else begin
grp_fu_1211_p1 = 'bx;
end
end else begin
grp_fu_1211_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin
grp_fu_1215_p0 = bufw_3_load_2_reg_4033;
end else if ((((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)))) begin
grp_fu_1215_p0 = bufw_3_load_1_reg_3789;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
grp_fu_1215_p0 = bufw_3_load_reg_3782;
end else begin
grp_fu_1215_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1215_p1 = bufi_2_load_7_reg_4412;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1215_p1 = bufi_2_load_4_reg_4239;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1215_p1 = bufi_1_load_7_reg_4395;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1215_p1 = bufi_1_load_6_reg_4344;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1215_p1 = bufi_0_load_7_reg_4378;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1215_p1 = bufi_0_load_5_reg_4256;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1215_p1 = bufi_0_load_3_reg_4154;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1215_p1 = bufi_0_load_1_reg_3931;
end else begin
grp_fu_1215_p1 = 'bx;
end
end else begin
grp_fu_1215_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin
grp_fu_1219_p0 = bufw_4_load_2_reg_4040;
end else if ((((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)))) begin
grp_fu_1219_p0 = bufw_4_load_1_reg_3804;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
grp_fu_1219_p0 = bufw_4_load_reg_3797;
end else begin
grp_fu_1219_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1219_p1 = bufi_2_load_7_reg_4412;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1219_p1 = bufi_2_load_4_reg_4239;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1219_p1 = bufi_1_load_7_reg_4395;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1219_p1 = bufi_1_load_6_reg_4344;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1219_p1 = bufi_0_load_7_reg_4378;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1219_p1 = bufi_0_load_5_reg_4256;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1219_p1 = bufi_0_load_3_reg_4154;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1219_p1 = bufi_0_load_1_reg_3931;
end else begin
grp_fu_1219_p1 = 'bx;
end
end else begin
grp_fu_1219_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin
grp_fu_1223_p0 = bufw_5_load_2_reg_4047;
end else if ((((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)))) begin
grp_fu_1223_p0 = bufw_5_load_1_reg_3819;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
grp_fu_1223_p0 = bufw_5_load_reg_3812;
end else begin
grp_fu_1223_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1223_p1 = bufi_2_load_7_reg_4412;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1223_p1 = bufi_2_load_4_reg_4239;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1223_p1 = bufi_1_load_7_reg_4395;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1223_p1 = bufi_1_load_6_reg_4344;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1223_p1 = bufi_0_load_7_reg_4378;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1223_p1 = bufi_0_load_5_reg_4256;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1223_p1 = bufi_0_load_3_reg_4154;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1223_p1 = bufi_0_load_1_reg_3931;
end else begin
grp_fu_1223_p1 = 'bx;
end
end else begin
grp_fu_1223_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin
grp_fu_1227_p0 = bufw_6_load_2_reg_4054;
end else if ((((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)))) begin
grp_fu_1227_p0 = bufw_6_load_1_reg_3834;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
grp_fu_1227_p0 = bufw_6_load_reg_3827;
end else begin
grp_fu_1227_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1227_p1 = bufi_2_load_7_reg_4412;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1227_p1 = bufi_2_load_4_reg_4239;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1227_p1 = bufi_1_load_7_reg_4395;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1227_p1 = bufi_1_load_6_reg_4344;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1227_p1 = bufi_0_load_7_reg_4378;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1227_p1 = bufi_0_load_5_reg_4256;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1227_p1 = bufi_0_load_3_reg_4154;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1227_p1 = bufi_0_load_1_reg_3931;
end else begin
grp_fu_1227_p1 = 'bx;
end
end else begin
grp_fu_1227_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin
grp_fu_1231_p0 = bufw_7_load_2_reg_4061;
end else if ((((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)))) begin
grp_fu_1231_p0 = bufw_7_load_1_reg_3849;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
grp_fu_1231_p0 = bufw_7_load_reg_3842;
end else begin
grp_fu_1231_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1231_p1 = bufi_2_load_7_reg_4412;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1231_p1 = bufi_2_load_4_reg_4239;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1231_p1 = bufi_1_load_7_reg_4395;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1231_p1 = bufi_1_load_6_reg_4344;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1231_p1 = bufi_0_load_7_reg_4378;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1231_p1 = bufi_0_load_5_reg_4256;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1231_p1 = bufi_0_load_3_reg_4154;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1231_p1 = bufi_0_load_1_reg_3931;
end else begin
grp_fu_1231_p1 = 'bx;
end
end else begin
grp_fu_1231_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin
grp_fu_1235_p0 = bufw_8_load_2_reg_4068;
end else if ((((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)))) begin
grp_fu_1235_p0 = bufw_8_load_1_reg_3864;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
grp_fu_1235_p0 = bufw_8_load_reg_3857;
end else begin
grp_fu_1235_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1235_p1 = bufi_2_load_7_reg_4412;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1235_p1 = bufi_2_load_4_reg_4239;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1235_p1 = bufi_1_load_7_reg_4395;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1235_p1 = bufi_1_load_6_reg_4344;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1235_p1 = bufi_0_load_7_reg_4378;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1235_p1 = bufi_0_load_5_reg_4256;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1235_p1 = bufi_0_load_3_reg_4154;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1235_p1 = bufi_0_load_1_reg_3931;
end else begin
grp_fu_1235_p1 = 'bx;
end
end else begin
grp_fu_1235_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin
grp_fu_1239_p0 = bufw_9_load_2_reg_4075;
end else if ((((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)))) begin
grp_fu_1239_p0 = bufw_9_load_1_reg_3879;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
grp_fu_1239_p0 = bufw_9_load_reg_3872;
end else begin
grp_fu_1239_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1239_p1 = bufi_2_load_7_reg_4412;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1239_p1 = bufi_2_load_4_reg_4239;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1239_p1 = bufi_1_load_7_reg_4395;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1239_p1 = bufi_1_load_6_reg_4344;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1239_p1 = bufi_0_load_7_reg_4378;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1239_p1 = bufi_0_load_5_reg_4256;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1239_p1 = bufi_0_load_3_reg_4154;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1239_p1 = bufi_0_load_1_reg_3931;
end else begin
grp_fu_1239_p1 = 'bx;
end
end else begin
grp_fu_1239_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin
grp_fu_1243_p0 = bufw_10_load_2_reg_4082;
end else if ((((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)))) begin
grp_fu_1243_p0 = bufw_10_load_1_reg_3894;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
grp_fu_1243_p0 = bufw_10_load_reg_3887;
end else begin
grp_fu_1243_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1243_p1 = bufi_2_load_7_reg_4412;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1243_p1 = bufi_2_load_4_reg_4239;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1243_p1 = bufi_1_load_7_reg_4395;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1243_p1 = bufi_1_load_6_reg_4344;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1243_p1 = bufi_0_load_7_reg_4378;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1243_p1 = bufi_0_load_5_reg_4256;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1243_p1 = bufi_0_load_3_reg_4154;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1243_p1 = bufi_0_load_1_reg_3931;
end else begin
grp_fu_1243_p1 = 'bx;
end
end else begin
grp_fu_1243_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin
grp_fu_1247_p0 = bufw_11_load_2_reg_4089;
end else if ((((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)))) begin
grp_fu_1247_p0 = bufw_11_load_1_reg_3909;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
grp_fu_1247_p0 = bufw_11_load_reg_3902;
end else begin
grp_fu_1247_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1247_p1 = bufi_2_load_7_reg_4412;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1247_p1 = bufi_2_load_4_reg_4239;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1247_p1 = bufi_1_load_7_reg_4395;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1247_p1 = bufi_1_load_6_reg_4344;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1247_p1 = bufi_0_load_7_reg_4378;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1247_p1 = bufi_0_load_5_reg_4256;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1247_p1 = bufi_0_load_3_reg_4154;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1247_p1 = bufi_0_load_1_reg_3931;
end else begin
grp_fu_1247_p1 = 'bx;
end
end else begin
grp_fu_1247_p1 = 'bx;
end
end
always @ (*) begin
if ((((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage7)) | ((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage6)))) begin
grp_fu_1251_p0 = bufw_12_load_2_reg_4096;
end else if ((((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage5)) | ((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage4)))) begin
grp_fu_1251_p0 = bufw_12_load_1_reg_3924;
end else if ((((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage3)) | ((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage2)) | ((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage1)) | ((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1) & (1'b1 == ap_CS_fsm_pp0_stage0)))) begin
grp_fu_1251_p0 = bufw_12_load_reg_3917;
end else begin
grp_fu_1251_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_enable_reg_pp0_iter1)) begin
if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7))) begin
grp_fu_1251_p1 = bufi_2_load_7_reg_4412;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6))) begin
grp_fu_1251_p1 = bufi_2_load_4_reg_4239;
end else if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5))) begin
grp_fu_1251_p1 = bufi_1_load_7_reg_4395;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4))) begin
grp_fu_1251_p1 = bufi_1_load_6_reg_4344;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3))) begin
grp_fu_1251_p1 = bufi_0_load_7_reg_4378;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2))) begin
grp_fu_1251_p1 = bufi_0_load_5_reg_4256;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1))) begin
grp_fu_1251_p1 = bufi_0_load_3_reg_4154;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
grp_fu_1251_p1 = bufi_0_load_1_reg_3931;
end else begin
grp_fu_1251_p1 = 'bx;
end
end else begin
grp_fu_1251_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_943_p0 = tmp_20_2_0_1_reg_7709;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_943_p0 = tmp_20_0_0_1_reg_7579;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_943_p0 = tmp_20_2_reg_7189;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_943_p0 = tmp_351_reg_7059;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_943_p0 = tmp_251_fu_2477_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_943_p0 = tmp_171_fu_2373_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_943_p0 = tmp_91_fu_2269_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_943_p0 = tmp_11_fu_2165_p1;
end else begin
grp_fu_943_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_943_p1 = ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_943_p1 = ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_943_p1 = ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_943_p1 = ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_943_p1 = tmp_19_6_reg_6019;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_943_p1 = tmp_19_4_reg_5694;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_943_p1 = tmp_19_2_reg_5369;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_943_p1 = tmp_349_reg_4849;
end else begin
grp_fu_943_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_947_p0 = tmp_20_2_1_1_reg_7714;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_947_p0 = tmp_20_0_1_1_reg_7584;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_947_p0 = tmp_20_2_1_reg_7194;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_947_p0 = tmp_20_0_1_reg_7064;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_947_p0 = tmp_254_fu_2481_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_947_p0 = tmp_174_fu_2377_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_947_p0 = tmp_94_fu_2273_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_947_p0 = tmp_14_fu_2169_p1;
end else begin
grp_fu_947_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_947_p1 = ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_947_p1 = ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_947_p1 = ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_947_p1 = ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_947_p1 = tmp_19_6_1_reg_6024;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_947_p1 = tmp_19_4_1_reg_5699;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_947_p1 = tmp_19_2_1_reg_5374;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_947_p1 = tmp_19_0_1_reg_4859;
end else begin
grp_fu_947_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_951_p0 = tmp_20_2_2_1_reg_7719;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_951_p0 = tmp_20_0_2_1_reg_7589;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_951_p0 = tmp_20_2_2_reg_7199;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_951_p0 = tmp_20_0_2_reg_7069;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_951_p0 = tmp_257_fu_2485_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_951_p0 = tmp_177_fu_2381_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_951_p0 = tmp_97_fu_2277_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_951_p0 = tmp_17_fu_2173_p1;
end else begin
grp_fu_951_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_951_p1 = ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_951_p1 = ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_951_p1 = ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_951_p1 = ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_951_p1 = tmp_19_6_2_reg_6029;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_951_p1 = tmp_19_4_2_reg_5704;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_951_p1 = tmp_19_2_2_reg_5379;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_951_p1 = tmp_19_0_2_reg_4869;
end else begin
grp_fu_951_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_955_p0 = tmp_20_2_3_1_reg_7724;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_955_p0 = tmp_20_0_3_1_reg_7594;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_955_p0 = tmp_20_2_3_reg_7204;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_955_p0 = tmp_20_0_3_reg_7074;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_955_p0 = tmp_260_fu_2489_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_955_p0 = tmp_180_fu_2385_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_955_p0 = tmp_100_fu_2281_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_955_p0 = tmp_20_fu_2177_p1;
end else begin
grp_fu_955_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_955_p1 = ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_955_p1 = ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_955_p1 = ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_955_p1 = ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_955_p1 = tmp_19_6_3_reg_6034;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_955_p1 = tmp_19_4_3_reg_5709;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_955_p1 = tmp_19_2_3_reg_5384;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_955_p1 = tmp_19_0_3_reg_4879;
end else begin
grp_fu_955_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_959_p0 = tmp_20_2_4_1_reg_7729;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_959_p0 = tmp_20_0_4_1_reg_7599;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_959_p0 = tmp_20_2_4_reg_7209;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_959_p0 = tmp_20_0_4_reg_7079;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_959_p0 = tmp_263_fu_2493_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_959_p0 = tmp_183_fu_2389_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_959_p0 = tmp_103_fu_2285_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_959_p0 = tmp_23_fu_2181_p1;
end else begin
grp_fu_959_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_959_p1 = ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_959_p1 = ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_959_p1 = ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_959_p1 = ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_959_p1 = tmp_19_6_4_reg_6039;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_959_p1 = tmp_19_4_4_reg_5714;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_959_p1 = tmp_19_2_4_reg_5389;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_959_p1 = tmp_19_0_4_reg_4889;
end else begin
grp_fu_959_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_963_p0 = tmp_20_2_5_1_reg_7734;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_963_p0 = tmp_20_0_5_1_reg_7604;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_963_p0 = tmp_20_2_5_reg_7214;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_963_p0 = tmp_20_0_5_reg_7084;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_963_p0 = tmp_266_fu_2497_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_963_p0 = tmp_186_fu_2393_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_963_p0 = tmp_106_fu_2289_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_963_p0 = tmp_26_fu_2185_p1;
end else begin
grp_fu_963_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_963_p1 = ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_963_p1 = ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_963_p1 = ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_963_p1 = ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_963_p1 = tmp_19_6_5_reg_6044;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_963_p1 = tmp_19_4_5_reg_5719;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_963_p1 = tmp_19_2_5_reg_5394;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_963_p1 = tmp_19_0_5_reg_4899;
end else begin
grp_fu_963_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_967_p0 = tmp_20_2_6_1_reg_7739;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_967_p0 = tmp_20_0_6_1_reg_7609;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_967_p0 = tmp_20_2_6_reg_7219;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_967_p0 = tmp_20_0_6_reg_7089;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_967_p0 = tmp_269_fu_2501_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_967_p0 = tmp_189_fu_2397_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_967_p0 = tmp_109_fu_2293_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_967_p0 = tmp_29_fu_2189_p1;
end else begin
grp_fu_967_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_967_p1 = ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_967_p1 = ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_967_p1 = ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_967_p1 = ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_967_p1 = tmp_19_6_6_reg_6049;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_967_p1 = tmp_19_4_6_reg_5724;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_967_p1 = tmp_19_2_6_reg_5399;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_967_p1 = tmp_19_0_6_reg_4909;
end else begin
grp_fu_967_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_971_p0 = tmp_20_2_7_1_reg_7744;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_971_p0 = tmp_20_0_7_1_reg_7614;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_971_p0 = tmp_20_2_7_reg_7224;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_971_p0 = tmp_20_0_7_reg_7094;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_971_p0 = tmp_272_fu_2505_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_971_p0 = tmp_192_fu_2401_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_971_p0 = tmp_112_fu_2297_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_971_p0 = tmp_32_fu_2193_p1;
end else begin
grp_fu_971_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_971_p1 = ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_971_p1 = ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_971_p1 = ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_971_p1 = ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_971_p1 = tmp_19_6_7_reg_6054;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_971_p1 = tmp_19_4_7_reg_5729;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_971_p1 = tmp_19_2_7_reg_5404;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_971_p1 = tmp_19_0_7_reg_4919;
end else begin
grp_fu_971_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_975_p0 = tmp_20_2_8_1_reg_7749;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_975_p0 = tmp_20_0_8_1_reg_7619;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_975_p0 = tmp_20_2_8_reg_7229;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_975_p0 = tmp_20_0_8_reg_7099;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_975_p0 = tmp_275_fu_2509_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_975_p0 = tmp_195_fu_2405_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_975_p0 = tmp_115_fu_2301_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_975_p0 = tmp_35_fu_2197_p1;
end else begin
grp_fu_975_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_975_p1 = ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_975_p1 = ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_975_p1 = ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_975_p1 = ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_975_p1 = tmp_19_6_8_reg_6059;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_975_p1 = tmp_19_4_8_reg_5734;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_975_p1 = tmp_19_2_8_reg_5409;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_975_p1 = tmp_19_0_8_reg_4929;
end else begin
grp_fu_975_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_979_p0 = tmp_20_2_9_1_reg_7754;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_979_p0 = tmp_20_0_9_1_reg_7624;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_979_p0 = tmp_20_2_9_reg_7234;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_979_p0 = tmp_20_0_9_reg_7104;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_979_p0 = tmp_278_fu_2513_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_979_p0 = tmp_198_fu_2409_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_979_p0 = tmp_118_fu_2305_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_979_p0 = tmp_38_fu_2201_p1;
end else begin
grp_fu_979_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_979_p1 = ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_979_p1 = ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_979_p1 = ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_979_p1 = ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_979_p1 = tmp_19_6_9_reg_6064;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_979_p1 = tmp_19_4_9_reg_5739;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_979_p1 = tmp_19_2_9_reg_5414;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_979_p1 = tmp_19_0_9_reg_4939;
end else begin
grp_fu_979_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_983_p0 = tmp_20_2_10_1_reg_7759;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_983_p0 = tmp_20_0_10_1_reg_7629;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_983_p0 = tmp_20_2_s_reg_7239;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_983_p0 = tmp_20_0_s_reg_7109;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_983_p0 = tmp_281_fu_2517_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_983_p0 = tmp_201_fu_2413_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_983_p0 = tmp_121_fu_2309_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_983_p0 = tmp_41_fu_2205_p1;
end else begin
grp_fu_983_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_983_p1 = ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_983_p1 = ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_983_p1 = ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_983_p1 = ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_983_p1 = tmp_19_6_s_reg_6069;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_983_p1 = tmp_19_4_s_reg_5744;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_983_p1 = tmp_19_2_s_reg_5419;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_983_p1 = tmp_19_0_s_reg_4949;
end else begin
grp_fu_983_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_987_p0 = tmp_20_2_11_1_reg_7764;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_987_p0 = tmp_20_0_11_1_reg_7634;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_987_p0 = tmp_20_2_10_reg_7244;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_987_p0 = tmp_20_0_10_reg_7114;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_987_p0 = tmp_284_fu_2521_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_987_p0 = tmp_204_fu_2417_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_987_p0 = tmp_124_fu_2313_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_987_p0 = tmp_44_fu_2209_p1;
end else begin
grp_fu_987_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_987_p1 = ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_987_p1 = ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_987_p1 = ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_987_p1 = ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_987_p1 = tmp_19_6_10_reg_6074;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_987_p1 = tmp_19_4_10_reg_5749;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_987_p1 = tmp_19_2_10_reg_5424;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_987_p1 = tmp_19_0_10_reg_4959;
end else begin
grp_fu_987_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_991_p0 = tmp_20_2_12_1_reg_7769;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_991_p0 = tmp_20_0_12_1_reg_7639;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_991_p0 = tmp_20_2_11_reg_7249;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_991_p0 = tmp_20_0_11_reg_7119;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_991_p0 = tmp_287_fu_2525_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_991_p0 = tmp_207_fu_2421_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_991_p0 = tmp_127_fu_2317_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_991_p0 = tmp_47_fu_2213_p1;
end else begin
grp_fu_991_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_991_p1 = ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_991_p1 = ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_991_p1 = ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_991_p1 = ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_991_p1 = tmp_19_6_11_reg_6079;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_991_p1 = tmp_19_4_11_reg_5754;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_991_p1 = tmp_19_2_11_reg_5429;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_991_p1 = tmp_19_0_11_reg_4969;
end else begin
grp_fu_991_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_995_p0 = tmp_20_3_0_1_reg_7774;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_995_p0 = tmp_20_1_0_1_reg_7644;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_995_p0 = tmp_20_3_reg_7254;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_995_p0 = tmp_20_1_reg_7124;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_995_p0 = tmp_291_fu_2529_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_995_p0 = tmp_211_fu_2425_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_995_p0 = tmp_131_fu_2321_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_995_p0 = tmp_51_fu_2217_p1;
end else begin
grp_fu_995_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_995_p1 = ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_995_p1 = ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_995_p1 = ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_995_p1 = ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_995_p1 = tmp_19_7_reg_6084;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_995_p1 = tmp_19_5_reg_5759;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_995_p1 = tmp_19_3_reg_5434;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_995_p1 = tmp_19_1_reg_4979;
end else begin
grp_fu_995_p1 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_999_p0 = tmp_20_3_1_1_reg_7779;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_999_p0 = tmp_20_1_1_1_reg_7649;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_999_p0 = tmp_20_3_1_reg_7259;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_999_p0 = tmp_20_1_1_reg_7129;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_999_p0 = tmp_294_fu_2533_p1;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_999_p0 = tmp_214_fu_2429_p1;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_999_p0 = tmp_134_fu_2325_p1;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_999_p0 = tmp_54_fu_2221_p1;
end else begin
grp_fu_999_p0 = 'bx;
end
end
always @ (*) begin
if (((ap_block_pp0_stage5 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage5) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_999_p1 = ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739;
end else if (((ap_block_pp0_stage4 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage4) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
grp_fu_999_p1 = ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544;
end else if (((ap_block_pp0_stage7 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage7) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_999_p1 = ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829;
end else if (((ap_block_pp0_stage6 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage6) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
grp_fu_999_p1 = ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254;
end else if (((ap_block_pp0_stage3 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage3) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_999_p1 = tmp_19_7_1_reg_6089;
end else if (((ap_block_pp0_stage2 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage2) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_999_p1 = tmp_19_5_1_reg_5764;
end else if (((ap_block_pp0_stage1 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_999_p1 = tmp_19_3_1_reg_5439;
end else if (((ap_block_pp0_stage0 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
grp_fu_999_p1 = tmp_19_1_1_reg_4984;
end else begin
grp_fu_999_p1 = 'bx;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_pp0_stage0 : begin
if ((~((ap_enable_reg_pp0_iter1 == 1'b0) & (exitcond_flatten1_fu_1541_p2 == 1'd1) & (ap_block_pp0_stage0_subdone == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter0)) & (ap_block_pp0_stage0_subdone == 1'b0))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage1;
end else if (((ap_enable_reg_pp0_iter1 == 1'b0) & (exitcond_flatten1_fu_1541_p2 == 1'd1) & (ap_block_pp0_stage0_subdone == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter0))) begin
ap_NS_fsm = ap_ST_fsm_state76;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_pp0_stage1 : begin
if ((~((ap_block_pp0_stage1_subdone == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter9)) & (ap_block_pp0_stage1_subdone == 1'b0))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage2;
end else if (((ap_block_pp0_stage1_subdone == 1'b0) & (ap_enable_reg_pp0_iter8 == 1'b0) & (1'b1 == ap_CS_fsm_pp0_stage1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
ap_NS_fsm = ap_ST_fsm_state76;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage1;
end
end
ap_ST_fsm_pp0_stage2 : begin
if ((ap_block_pp0_stage2_subdone == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage3;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage2;
end
end
ap_ST_fsm_pp0_stage3 : begin
if ((ap_block_pp0_stage3_subdone == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage4;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage3;
end
end
ap_ST_fsm_pp0_stage4 : begin
if ((ap_block_pp0_stage4_subdone == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage5;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage4;
end
end
ap_ST_fsm_pp0_stage5 : begin
if ((ap_block_pp0_stage5_subdone == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage6;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage5;
end
end
ap_ST_fsm_pp0_stage6 : begin
if ((ap_block_pp0_stage6_subdone == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage7;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage6;
end
end
ap_ST_fsm_pp0_stage7 : begin
if ((ap_block_pp0_stage7_subdone == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage7;
end
end
ap_ST_fsm_state76 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_pp0_stage1 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_pp0_stage2 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_pp0_stage3 = ap_CS_fsm[32'd4];
assign ap_CS_fsm_pp0_stage4 = ap_CS_fsm[32'd5];
assign ap_CS_fsm_pp0_stage5 = ap_CS_fsm[32'd6];
assign ap_CS_fsm_pp0_stage6 = ap_CS_fsm[32'd7];
assign ap_CS_fsm_pp0_stage7 = ap_CS_fsm[32'd8];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state76 = ap_CS_fsm[32'd9];
assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage1 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage1_11001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage1_subdone = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage2 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage2_11001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage2_subdone = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage3 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage3_11001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage3_subdone = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage4 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage4_11001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage4_subdone = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage5 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage5_11001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage5_subdone = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage6 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage6_11001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage6_subdone = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage7 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage7_11001 = ~(1'b1 == 1'b1);
assign ap_block_pp0_stage7_subdone = ~(1'b1 == 1'b1);
assign ap_block_state10_pp0_stage0_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state11_pp0_stage1_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state12_pp0_stage2_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state13_pp0_stage3_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state14_pp0_stage4_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state15_pp0_stage5_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state16_pp0_stage6_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state17_pp0_stage7_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state18_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state19_pp0_stage1_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state20_pp0_stage2_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state21_pp0_stage3_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state22_pp0_stage4_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state23_pp0_stage5_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state24_pp0_stage6_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state25_pp0_stage7_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state26_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state27_pp0_stage1_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state28_pp0_stage2_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state29_pp0_stage3_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state30_pp0_stage4_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state31_pp0_stage5_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state32_pp0_stage6_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state33_pp0_stage7_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state34_pp0_stage0_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state35_pp0_stage1_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state36_pp0_stage2_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state37_pp0_stage3_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state38_pp0_stage4_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state39_pp0_stage5_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state3_pp0_stage1_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state40_pp0_stage6_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state41_pp0_stage7_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state42_pp0_stage0_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state43_pp0_stage1_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state44_pp0_stage2_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state45_pp0_stage3_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state46_pp0_stage4_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state47_pp0_stage5_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state48_pp0_stage6_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state49_pp0_stage7_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state4_pp0_stage2_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state50_pp0_stage0_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state51_pp0_stage1_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state52_pp0_stage2_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state53_pp0_stage3_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state54_pp0_stage4_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state55_pp0_stage5_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state56_pp0_stage6_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state57_pp0_stage7_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state58_pp0_stage0_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state59_pp0_stage1_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state5_pp0_stage3_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state60_pp0_stage2_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state61_pp0_stage3_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state62_pp0_stage4_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state63_pp0_stage5_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state64_pp0_stage6_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state65_pp0_stage7_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state66_pp0_stage0_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state67_pp0_stage1_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state68_pp0_stage2_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state69_pp0_stage3_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state6_pp0_stage4_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state70_pp0_stage4_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state71_pp0_stage5_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state72_pp0_stage6_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state73_pp0_stage7_iter8 = ~(1'b1 == 1'b1);
assign ap_block_state74_pp0_stage0_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state75_pp0_stage1_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state7_pp0_stage5_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state8_pp0_stage6_iter0 = ~(1'b1 == 1'b1);
assign ap_block_state9_pp0_stage7_iter0 = ~(1'b1 == 1'b1);
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
always @ (*) begin
ap_rst_n_inv = ~ap_rst_n;
end
assign bufi_0_Addr_A = bufi_0_Addr_A_orig << 32'd2;
assign bufi_0_Addr_B = bufi_0_Addr_B_orig << 32'd2;
assign bufi_0_Clk_A = ap_clk;
assign bufi_0_Clk_B = ap_clk;
assign bufi_0_Din_A = 32'd0;
assign bufi_0_Din_B = 32'd0;
assign bufi_0_Rst_A = ap_rst_n_inv;
assign bufi_0_Rst_B = ap_rst_n_inv;
assign bufi_0_WEN_A = 4'd0;
assign bufi_0_WEN_B = 4'd0;
assign bufi_1_Addr_A = bufi_1_Addr_A_orig << 32'd2;
assign bufi_1_Addr_B = bufi_1_Addr_B_orig << 32'd2;
assign bufi_1_Clk_A = ap_clk;
assign bufi_1_Clk_B = ap_clk;
assign bufi_1_Din_A = 32'd0;
assign bufi_1_Din_B = 32'd0;
assign bufi_1_Rst_A = ap_rst_n_inv;
assign bufi_1_Rst_B = ap_rst_n_inv;
assign bufi_1_WEN_A = 4'd0;
assign bufi_1_WEN_B = 4'd0;
assign bufi_2_Addr_A = bufi_2_Addr_A_orig << 32'd2;
assign bufi_2_Addr_B = bufi_2_Addr_B_orig << 32'd2;
assign bufi_2_Clk_A = ap_clk;
assign bufi_2_Clk_B = ap_clk;
assign bufi_2_Din_A = 32'd0;
assign bufi_2_Din_B = 32'd0;
assign bufi_2_Rst_A = ap_rst_n_inv;
assign bufi_2_Rst_B = ap_rst_n_inv;
assign bufi_2_WEN_A = 4'd0;
assign bufi_2_WEN_B = 4'd0;
assign bufo_Addr_A = bufo_Addr_A_orig << 32'd6;
assign bufo_Addr_B = bufo_Addr_B_orig << 32'd6;
assign bufo_Clk_A = ap_clk;
assign bufo_Clk_B = ap_clk;
assign bufo_Rst_A = ap_rst_n_inv;
assign bufo_Rst_B = ap_rst_n_inv;
assign bufw_0_Addr_A = bufw_0_Addr_A_orig << 32'd2;
assign bufw_0_Addr_B = bufw_0_Addr_B_orig << 32'd2;
assign bufw_0_Addr_B_orig = tmp_8_cast_fu_1791_p1;
assign bufw_0_Clk_A = ap_clk;
assign bufw_0_Clk_B = ap_clk;
assign bufw_0_Din_A = 32'd0;
assign bufw_0_Din_B = 32'd0;
assign bufw_0_Rst_A = ap_rst_n_inv;
assign bufw_0_Rst_B = ap_rst_n_inv;
assign bufw_0_WEN_A = 4'd0;
assign bufw_0_WEN_B = 4'd0;
assign bufw_10_Addr_A = bufw_10_Addr_A_orig << 32'd2;
assign bufw_10_Addr_B = bufw_10_Addr_B_orig << 32'd2;
assign bufw_10_Addr_B_orig = tmp_8_cast_fu_1791_p1;
assign bufw_10_Clk_A = ap_clk;
assign bufw_10_Clk_B = ap_clk;
assign bufw_10_Din_A = 32'd0;
assign bufw_10_Din_B = 32'd0;
assign bufw_10_Rst_A = ap_rst_n_inv;
assign bufw_10_Rst_B = ap_rst_n_inv;
assign bufw_10_WEN_A = 4'd0;
assign bufw_10_WEN_B = 4'd0;
assign bufw_11_Addr_A = bufw_11_Addr_A_orig << 32'd2;
assign bufw_11_Addr_B = bufw_11_Addr_B_orig << 32'd2;
assign bufw_11_Addr_B_orig = tmp_8_cast_fu_1791_p1;
assign bufw_11_Clk_A = ap_clk;
assign bufw_11_Clk_B = ap_clk;
assign bufw_11_Din_A = 32'd0;
assign bufw_11_Din_B = 32'd0;
assign bufw_11_Rst_A = ap_rst_n_inv;
assign bufw_11_Rst_B = ap_rst_n_inv;
assign bufw_11_WEN_A = 4'd0;
assign bufw_11_WEN_B = 4'd0;
assign bufw_12_Addr_A = bufw_12_Addr_A_orig << 32'd2;
assign bufw_12_Addr_B = bufw_12_Addr_B_orig << 32'd2;
assign bufw_12_Addr_B_orig = tmp_8_cast_fu_1791_p1;
assign bufw_12_Clk_A = ap_clk;
assign bufw_12_Clk_B = ap_clk;
assign bufw_12_Din_A = 32'd0;
assign bufw_12_Din_B = 32'd0;
assign bufw_12_Rst_A = ap_rst_n_inv;
assign bufw_12_Rst_B = ap_rst_n_inv;
assign bufw_12_WEN_A = 4'd0;
assign bufw_12_WEN_B = 4'd0;
assign bufw_1_Addr_A = bufw_1_Addr_A_orig << 32'd2;
assign bufw_1_Addr_B = bufw_1_Addr_B_orig << 32'd2;
assign bufw_1_Addr_B_orig = tmp_8_cast_fu_1791_p1;
assign bufw_1_Clk_A = ap_clk;
assign bufw_1_Clk_B = ap_clk;
assign bufw_1_Din_A = 32'd0;
assign bufw_1_Din_B = 32'd0;
assign bufw_1_Rst_A = ap_rst_n_inv;
assign bufw_1_Rst_B = ap_rst_n_inv;
assign bufw_1_WEN_A = 4'd0;
assign bufw_1_WEN_B = 4'd0;
assign bufw_2_Addr_A = bufw_2_Addr_A_orig << 32'd2;
assign bufw_2_Addr_B = bufw_2_Addr_B_orig << 32'd2;
assign bufw_2_Addr_B_orig = tmp_8_cast_fu_1791_p1;
assign bufw_2_Clk_A = ap_clk;
assign bufw_2_Clk_B = ap_clk;
assign bufw_2_Din_A = 32'd0;
assign bufw_2_Din_B = 32'd0;
assign bufw_2_Rst_A = ap_rst_n_inv;
assign bufw_2_Rst_B = ap_rst_n_inv;
assign bufw_2_WEN_A = 4'd0;
assign bufw_2_WEN_B = 4'd0;
assign bufw_3_Addr_A = bufw_3_Addr_A_orig << 32'd2;
assign bufw_3_Addr_B = bufw_3_Addr_B_orig << 32'd2;
assign bufw_3_Addr_B_orig = tmp_8_cast_fu_1791_p1;
assign bufw_3_Clk_A = ap_clk;
assign bufw_3_Clk_B = ap_clk;
assign bufw_3_Din_A = 32'd0;
assign bufw_3_Din_B = 32'd0;
assign bufw_3_Rst_A = ap_rst_n_inv;
assign bufw_3_Rst_B = ap_rst_n_inv;
assign bufw_3_WEN_A = 4'd0;
assign bufw_3_WEN_B = 4'd0;
assign bufw_4_Addr_A = bufw_4_Addr_A_orig << 32'd2;
assign bufw_4_Addr_B = bufw_4_Addr_B_orig << 32'd2;
assign bufw_4_Addr_B_orig = tmp_8_cast_fu_1791_p1;
assign bufw_4_Clk_A = ap_clk;
assign bufw_4_Clk_B = ap_clk;
assign bufw_4_Din_A = 32'd0;
assign bufw_4_Din_B = 32'd0;
assign bufw_4_Rst_A = ap_rst_n_inv;
assign bufw_4_Rst_B = ap_rst_n_inv;
assign bufw_4_WEN_A = 4'd0;
assign bufw_4_WEN_B = 4'd0;
assign bufw_5_Addr_A = bufw_5_Addr_A_orig << 32'd2;
assign bufw_5_Addr_B = bufw_5_Addr_B_orig << 32'd2;
assign bufw_5_Addr_B_orig = tmp_8_cast_fu_1791_p1;
assign bufw_5_Clk_A = ap_clk;
assign bufw_5_Clk_B = ap_clk;
assign bufw_5_Din_A = 32'd0;
assign bufw_5_Din_B = 32'd0;
assign bufw_5_Rst_A = ap_rst_n_inv;
assign bufw_5_Rst_B = ap_rst_n_inv;
assign bufw_5_WEN_A = 4'd0;
assign bufw_5_WEN_B = 4'd0;
assign bufw_6_Addr_A = bufw_6_Addr_A_orig << 32'd2;
assign bufw_6_Addr_B = bufw_6_Addr_B_orig << 32'd2;
assign bufw_6_Addr_B_orig = tmp_8_cast_fu_1791_p1;
assign bufw_6_Clk_A = ap_clk;
assign bufw_6_Clk_B = ap_clk;
assign bufw_6_Din_A = 32'd0;
assign bufw_6_Din_B = 32'd0;
assign bufw_6_Rst_A = ap_rst_n_inv;
assign bufw_6_Rst_B = ap_rst_n_inv;
assign bufw_6_WEN_A = 4'd0;
assign bufw_6_WEN_B = 4'd0;
assign bufw_7_Addr_A = bufw_7_Addr_A_orig << 32'd2;
assign bufw_7_Addr_B = bufw_7_Addr_B_orig << 32'd2;
assign bufw_7_Addr_B_orig = tmp_8_cast_fu_1791_p1;
assign bufw_7_Clk_A = ap_clk;
assign bufw_7_Clk_B = ap_clk;
assign bufw_7_Din_A = 32'd0;
assign bufw_7_Din_B = 32'd0;
assign bufw_7_Rst_A = ap_rst_n_inv;
assign bufw_7_Rst_B = ap_rst_n_inv;
assign bufw_7_WEN_A = 4'd0;
assign bufw_7_WEN_B = 4'd0;
assign bufw_8_Addr_A = bufw_8_Addr_A_orig << 32'd2;
assign bufw_8_Addr_B = bufw_8_Addr_B_orig << 32'd2;
assign bufw_8_Addr_B_orig = tmp_8_cast_fu_1791_p1;
assign bufw_8_Clk_A = ap_clk;
assign bufw_8_Clk_B = ap_clk;
assign bufw_8_Din_A = 32'd0;
assign bufw_8_Din_B = 32'd0;
assign bufw_8_Rst_A = ap_rst_n_inv;
assign bufw_8_Rst_B = ap_rst_n_inv;
assign bufw_8_WEN_A = 4'd0;
assign bufw_8_WEN_B = 4'd0;
assign bufw_9_Addr_A = bufw_9_Addr_A_orig << 32'd2;
assign bufw_9_Addr_B = bufw_9_Addr_B_orig << 32'd2;
assign bufw_9_Addr_B_orig = tmp_8_cast_fu_1791_p1;
assign bufw_9_Clk_A = ap_clk;
assign bufw_9_Clk_B = ap_clk;
assign bufw_9_Din_A = 32'd0;
assign bufw_9_Din_B = 32'd0;
assign bufw_9_Rst_A = ap_rst_n_inv;
assign bufw_9_Rst_B = ap_rst_n_inv;
assign bufw_9_WEN_A = 4'd0;
assign bufw_9_WEN_B = 4'd0;
assign exitcond_flatten1_fu_1541_p2 = ((ap_phi_mux_indvar_flatten1_phi_fu_889_p4 == 10'd675) ? 1'b1 : 1'b0);
assign exitcond_flatten_fu_1559_p2 = ((ap_phi_mux_indvar_flatten_phi_fu_912_p4 == 8'd135) ? 1'b1 : 1'b0);
assign grp_fu_1255_p1 = bufo_Dout_A;
assign grp_fu_1265_p1 = bufo_Dout_A;
assign grp_fu_1275_p1 = bufo_Dout_A;
assign grp_fu_1285_p1 = bufo_Dout_A;
assign grp_fu_1295_p1 = bufo_Dout_A;
assign grp_fu_1305_p1 = bufo_Dout_A;
assign grp_fu_1315_p1 = bufo_Dout_A;
assign grp_fu_1325_p1 = bufo_Dout_A;
assign grp_fu_1335_p1 = bufo_Dout_A;
assign grp_fu_1345_p1 = bufo_Dout_A;
assign grp_fu_1355_p1 = bufo_Dout_A;
assign grp_fu_1365_p1 = bufo_Dout_A;
assign grp_fu_1375_p1 = bufo_Dout_B;
assign grp_fu_1385_p1 = bufo_Dout_B;
assign grp_fu_1395_p1 = bufo_Dout_B;
assign grp_fu_1405_p1 = bufo_Dout_B;
assign grp_fu_1415_p1 = bufo_Dout_B;
assign grp_fu_1425_p1 = bufo_Dout_B;
assign grp_fu_1435_p1 = bufo_Dout_B;
assign grp_fu_1445_p1 = bufo_Dout_B;
assign grp_fu_1455_p1 = bufo_Dout_B;
assign grp_fu_1465_p1 = bufo_Dout_B;
assign grp_fu_1475_p1 = bufo_Dout_B;
assign grp_fu_1485_p1 = bufo_Dout_B;
assign i_1_fu_1553_p2 = (3'd1 + ap_phi_mux_i_phi_fu_900_p4);
assign indvar_flatten_next1_fu_1547_p2 = (ap_phi_mux_indvar_flatten1_phi_fu_889_p4 + 10'd1);
assign indvar_flatten_next_fu_1613_p3 = ((exitcond_flatten_reg_3190[0:0] === 1'b1) ? 8'd1 : indvar_flatten_op_reg_3211);
assign indvar_flatten_op_fu_1571_p2 = (8'd1 + ap_phi_mux_indvar_flatten_phi_fu_912_p4);
assign j_1_fu_1642_p2 = (3'd1 + j_mid_reg_3216);
assign j_mid_fu_1577_p3 = ((exitcond_flatten_reg_3190[0:0] === 1'b1) ? 3'd0 : j_reg_919);
assign not_exitcond_flatten_fu_1590_p2 = (exitcond_flatten_reg_3190 ^ 1'd1);
assign p_shl1_cast_fu_1690_p1 = tmp_50_fu_1683_p3;
assign p_shl2_cast_fu_1629_p1 = tmp_fu_1622_p3;
assign p_shl_cast_fu_1679_p1 = tmp_10_fu_1672_p3;
assign row_b_1_fu_1652_p2 = (5'd1 + row_b_mid2_reg_3245);
assign row_b_mid2_fu_1605_p3 = ((tmp_4_fu_1600_p2[0:0] === 1'b1) ? 5'd0 : row_b_reg_931);
assign tmp_100_fu_2281_p1 = tmp_99_reg_4604;
assign tmp_101_fu_2730_p1 = tmp_20_2_3_2_reg_8244;
assign tmp_103_fu_2285_p1 = tmp_102_reg_4609;
assign tmp_104_fu_2733_p1 = tmp_20_2_4_2_reg_8249;
assign tmp_106_fu_2289_p1 = tmp_105_reg_4614;
assign tmp_107_fu_2736_p1 = tmp_20_2_5_2_reg_8254;
assign tmp_109_fu_2293_p1 = tmp_108_reg_4619;
assign tmp_10_fu_1672_p3 = {{tmp_s_reg_3270}, {4'd0}};
assign tmp_110_fu_2739_p1 = tmp_20_2_6_2_reg_8259;
assign tmp_112_fu_2297_p1 = tmp_111_reg_4624;
assign tmp_113_fu_2742_p1 = tmp_20_2_7_2_reg_8264;
assign tmp_115_fu_2301_p1 = tmp_114_reg_4629;
assign tmp_116_fu_2745_p1 = tmp_20_2_8_2_reg_8269;
assign tmp_118_fu_2305_p1 = tmp_117_reg_4634;
assign tmp_119_fu_2748_p1 = tmp_20_2_9_2_reg_8274;
assign tmp_11_fu_2165_p1 = tmp_350_reg_4449;
assign tmp_121_fu_2309_p1 = tmp_120_reg_4639;
assign tmp_122_fu_2751_p1 = tmp_20_2_10_2_reg_8279;
assign tmp_124_fu_2313_p1 = tmp_123_reg_4644;
assign tmp_125_fu_2754_p1 = tmp_20_2_11_2_reg_8284;
assign tmp_127_fu_2317_p1 = tmp_126_reg_4649;
assign tmp_128_fu_2757_p1 = tmp_20_2_12_2_reg_8289;
assign tmp_129_fu_2760_p14 = {{{{{{{{{{{{{tmp_128_fu_2757_p1}, {tmp_125_fu_2754_p1}}, {tmp_122_fu_2751_p1}}, {tmp_119_fu_2748_p1}}, {tmp_116_fu_2745_p1}}, {tmp_113_fu_2742_p1}}, {tmp_110_fu_2739_p1}}, {tmp_107_fu_2736_p1}}, {tmp_104_fu_2733_p1}}, {tmp_101_fu_2730_p1}}, {tmp_98_fu_2727_p1}}, {tmp_95_fu_2724_p1}}, {tmp_92_fu_2721_p1}};
assign tmp_12_1_fu_1499_p2 = (ap_phi_mux_j_phi_fu_923_p4 + 3'd1);
assign tmp_12_1_mid1_fu_1667_p2 = (3'd2 + j_mid_reg_3216);
assign tmp_12_2_fu_1505_p2 = (ap_phi_mux_j_phi_fu_923_p4 + 3'd2);
assign tmp_12_2_mid1_fu_1748_p2 = (3'd3 + j_mid_reg_3216);
assign tmp_12_3_fu_1511_p2 = (ap_phi_mux_j_phi_fu_923_p4 + 3'd3);
assign tmp_12_3_mid1_fu_1824_p2 = (j_mid_reg_3216 ^ 3'd4);
assign tmp_12_4_fu_1517_p2 = (tmp_6_cast2_fu_1495_p1 + 4'd4);
assign tmp_12_4_mid1_fu_1840_p2 = (4'd4 + tmp_6_cast2_mid1_fu_1811_p1);
assign tmp_12_5_fu_1523_p2 = (tmp_6_cast2_fu_1495_p1 + 4'd5);
assign tmp_12_5_mid1_fu_1846_p2 = (4'd5 + tmp_6_cast2_mid1_fu_1811_p1);
assign tmp_12_6_fu_1529_p2 = (tmp_6_cast2_fu_1495_p1 + 4'd6);
assign tmp_12_6_mid1_fu_1852_p2 = (4'd6 + tmp_6_cast2_mid1_fu_1811_p1);
assign tmp_12_7_fu_1535_p2 = (tmp_6_cast2_fu_1495_p1 + 4'd7);
assign tmp_12_7_mid1_fu_1858_p2 = (4'd7 + tmp_6_cast2_mid1_fu_1811_p1);
assign tmp_12_fu_2581_p1 = tmp_20_0_0_2_reg_8099;
assign tmp_130_fu_1753_p2 = (tmp_90_reg_3299 + tmp_5_mid2_cast1_fu_1718_p1);
assign tmp_131_fu_2321_p1 = tmp_354_reg_4654;
assign tmp_132_fu_2791_p1 = tmp_20_3_0_2_reg_8294;
assign tmp_134_fu_2325_p1 = tmp_133_reg_4659;
assign tmp_135_fu_2794_p1 = tmp_20_3_1_2_reg_8299;
assign tmp_137_fu_2329_p1 = tmp_136_reg_4664;
assign tmp_138_fu_2797_p1 = tmp_20_3_2_2_reg_8304;
assign tmp_13_1_mid2_cast_fu_1744_p1 = tmp_13_1_mid2_fu_1738_p3;
assign tmp_13_1_mid2_fu_1738_p3 = ((tmp_7_mid_reg_3233[0:0] === 1'b1) ? tmp_12_1_mid1_reg_3294 : tmp_13_1_mid_fu_1712_p3);
assign tmp_13_1_mid_fu_1712_p3 = ((exitcond_flatten_reg_3190[0:0] === 1'b1) ? 3'd1 : tmp_12_1_reg_3141);
assign tmp_13_2_mid2_cast_fu_1820_p1 = tmp_13_2_mid2_fu_1814_p3;
assign tmp_13_2_mid2_fu_1814_p3 = ((tmp_7_mid_reg_3233[0:0] === 1'b1) ? tmp_12_2_mid1_reg_3331 : tmp_13_2_mid_fu_1763_p3);
assign tmp_13_2_mid_fu_1763_p3 = ((exitcond_flatten_reg_3190[0:0] === 1'b1) ? 3'd2 : tmp_12_2_reg_3146);
assign tmp_13_3_mid2_cast_fu_1836_p1 = tmp_13_3_mid2_fu_1829_p3;
assign tmp_13_3_mid2_fu_1829_p3 = ((tmp_7_mid_reg_3233[0:0] === 1'b1) ? tmp_12_3_mid1_fu_1824_p2 : tmp_13_3_mid_fu_1769_p3);
assign tmp_13_3_mid_fu_1769_p3 = ((exitcond_flatten_reg_3190[0:0] === 1'b1) ? 3'd3 : tmp_12_3_reg_3151);
assign tmp_13_4_mid2_cast_fu_1932_p1 = tmp_13_4_mid2_fu_1926_p3;
assign tmp_13_4_mid2_fu_1926_p3 = ((tmp_7_mid_reg_3233[0:0] === 1'b1) ? tmp_12_4_mid1_reg_3481 : tmp_13_4_mid_fu_1886_p3);
assign tmp_13_4_mid_fu_1886_p3 = ((exitcond_flatten_reg_3190[0:0] === 1'b1) ? 4'd4 : tmp_12_4_reg_3156);
assign tmp_13_5_mid2_cast_fu_1942_p1 = tmp_13_5_mid2_fu_1936_p3;
assign tmp_13_5_mid2_fu_1936_p3 = ((tmp_7_mid_reg_3233[0:0] === 1'b1) ? tmp_12_5_mid1_reg_3486 : tmp_13_5_mid_fu_1892_p3);
assign tmp_13_5_mid_fu_1892_p3 = ((exitcond_flatten_reg_3190[0:0] === 1'b1) ? 4'd5 : tmp_12_5_reg_3161);
assign tmp_13_6_mid2_cast_fu_1952_p1 = tmp_13_6_mid2_fu_1946_p3;
assign tmp_13_6_mid2_fu_1946_p3 = ((tmp_7_mid_reg_3233[0:0] === 1'b1) ? tmp_12_6_mid1_reg_3491 : tmp_13_6_mid_fu_1898_p3);
assign tmp_13_6_mid_fu_1898_p3 = ((exitcond_flatten_reg_3190[0:0] === 1'b1) ? 4'd6 : tmp_12_6_reg_3166);
assign tmp_13_7_mid2_cast_fu_1962_p1 = tmp_13_7_mid2_fu_1956_p3;
assign tmp_13_7_mid2_fu_1956_p3 = ((tmp_7_mid_reg_3233[0:0] === 1'b1) ? tmp_12_7_mid1_reg_3496 : tmp_13_7_mid_fu_1904_p3);
assign tmp_13_7_mid_fu_1904_p3 = ((exitcond_flatten_reg_3190[0:0] === 1'b1) ? 4'd7 : tmp_12_7_reg_3171);
assign tmp_140_fu_2333_p1 = tmp_139_reg_4669;
assign tmp_141_fu_2800_p1 = tmp_20_3_3_2_reg_8309;
assign tmp_143_fu_2337_p1 = tmp_142_reg_4674;
assign tmp_144_fu_2803_p1 = tmp_20_3_4_2_reg_8314;
assign tmp_146_fu_2341_p1 = tmp_145_reg_4679;
assign tmp_147_fu_2806_p1 = tmp_20_3_5_2_reg_8319;
assign tmp_149_fu_2345_p1 = tmp_148_reg_4684;
assign tmp_14_fu_2169_p1 = tmp_13_reg_4454;
assign tmp_150_fu_2809_p1 = tmp_20_3_6_2_reg_8324;
assign tmp_152_fu_2349_p1 = tmp_151_reg_4689;
assign tmp_153_fu_2812_p1 = tmp_20_3_7_2_reg_8329;
assign tmp_155_fu_2353_p1 = tmp_154_reg_4694;
assign tmp_156_fu_2815_p1 = tmp_20_3_8_2_reg_8334;
assign tmp_158_fu_2357_p1 = tmp_157_reg_4699;
assign tmp_159_fu_2818_p1 = tmp_20_3_9_2_reg_8339;
assign tmp_15_fu_2584_p1 = tmp_20_0_1_2_reg_8104;
assign tmp_161_fu_2361_p1 = tmp_160_reg_4704;
assign tmp_162_fu_2821_p1 = tmp_20_3_10_2_reg_8344;
assign tmp_164_fu_2365_p1 = tmp_163_reg_4709;
assign tmp_165_fu_2824_p1 = tmp_20_3_11_2_reg_8349;
assign tmp_167_fu_2369_p1 = tmp_166_reg_4714;
assign tmp_168_fu_2827_p1 = tmp_20_3_12_2_reg_8354;
assign tmp_169_fu_2830_p14 = {{{{{{{{{{{{{tmp_168_fu_2827_p1}, {tmp_165_fu_2824_p1}}, {tmp_162_fu_2821_p1}}, {tmp_159_fu_2818_p1}}, {tmp_156_fu_2815_p1}}, {tmp_153_fu_2812_p1}}, {tmp_150_fu_2809_p1}}, {tmp_147_fu_2806_p1}}, {tmp_144_fu_2803_p1}}, {tmp_141_fu_2800_p1}}, {tmp_138_fu_2797_p1}}, {tmp_135_fu_2794_p1}}, {tmp_132_fu_2791_p1}};
assign tmp_170_fu_1758_p2 = (tmp_90_reg_3299 + tmp_13_1_mid2_cast_fu_1744_p1);
assign tmp_171_fu_2373_p1 = tmp_355_reg_4719;
assign tmp_172_fu_2861_p1 = tmp_20_4_0_2_reg_8359;
assign tmp_174_fu_2377_p1 = tmp_173_reg_4724;
assign tmp_175_fu_2864_p1 = tmp_20_4_1_2_reg_8364;
assign tmp_177_fu_2381_p1 = tmp_176_reg_4729;
assign tmp_178_fu_2867_p1 = tmp_20_4_2_2_reg_8369;
assign tmp_17_fu_2173_p1 = tmp_16_reg_4459;
assign tmp_180_fu_2385_p1 = tmp_179_reg_4734;
assign tmp_181_fu_2870_p1 = tmp_20_4_3_2_reg_8374;
assign tmp_183_fu_2389_p1 = tmp_182_reg_4739;
assign tmp_184_fu_2873_p1 = tmp_20_4_4_2_reg_8379;
assign tmp_186_fu_2393_p1 = tmp_185_reg_4744;
assign tmp_187_fu_2876_p1 = tmp_20_4_5_2_reg_8384;
assign tmp_189_fu_2397_p1 = tmp_188_reg_4749;
assign tmp_18_fu_2587_p1 = tmp_20_0_2_2_reg_8109;
assign tmp_190_fu_2879_p1 = tmp_20_4_6_2_reg_8389;
assign tmp_192_fu_2401_p1 = tmp_191_reg_4754;
assign tmp_193_fu_2882_p1 = tmp_20_4_7_2_reg_8394;
assign tmp_195_fu_2405_p1 = tmp_194_reg_4759;
assign tmp_196_fu_2885_p1 = tmp_20_4_8_2_reg_8399;
assign tmp_198_fu_2409_p1 = tmp_197_reg_4764;
assign tmp_199_fu_2888_p1 = tmp_20_4_9_2_reg_8404;
assign tmp_1_cast_fu_1700_p1 = tmp_1_reg_3257;
assign tmp_1_fu_1633_p2 = (tmp_1_mid2_cast_fu_1619_p1 + p_shl2_cast_fu_1629_p1);
assign tmp_1_mid2_cast_fu_1619_p1 = tmp_1_mid2_v_reg_3225;
assign tmp_1_mid2_v_fu_1584_p3 = ((exitcond_flatten_reg_3190[0:0] === 1'b1) ? i_1_reg_3185 : i_reg_896);
assign tmp_201_fu_2413_p1 = tmp_200_reg_4769;
assign tmp_202_fu_2891_p1 = tmp_20_4_10_2_reg_8409;
assign tmp_204_fu_2417_p1 = tmp_203_reg_4774;
assign tmp_205_fu_2894_p1 = tmp_20_4_11_2_reg_8414;
assign tmp_207_fu_2421_p1 = tmp_206_reg_4779;
assign tmp_208_fu_2897_p1 = tmp_20_4_12_2_reg_8419;
assign tmp_209_fu_2900_p14 = {{{{{{{{{{{{{tmp_208_fu_2897_p1}, {tmp_205_fu_2894_p1}}, {tmp_202_fu_2891_p1}}, {tmp_199_fu_2888_p1}}, {tmp_196_fu_2885_p1}}, {tmp_193_fu_2882_p1}}, {tmp_190_fu_2879_p1}}, {tmp_187_fu_2876_p1}}, {tmp_184_fu_2873_p1}}, {tmp_181_fu_2870_p1}}, {tmp_178_fu_2867_p1}}, {tmp_175_fu_2864_p1}}, {tmp_172_fu_2861_p1}};
assign tmp_20_fu_2177_p1 = tmp_19_reg_4464;
assign tmp_210_fu_1876_p2 = (tmp_90_reg_3299 + tmp_13_2_mid2_cast_fu_1820_p1);
assign tmp_211_fu_2425_p1 = tmp_356_reg_4784;
assign tmp_212_fu_2931_p1 = tmp_20_5_0_2_reg_8424;
assign tmp_214_fu_2429_p1 = tmp_213_reg_4789;
assign tmp_215_fu_2934_p1 = tmp_20_5_1_2_reg_8429;
assign tmp_217_fu_2433_p1 = tmp_216_reg_4794;
assign tmp_218_fu_2937_p1 = tmp_20_5_2_2_reg_8434;
assign tmp_21_fu_2590_p1 = tmp_20_0_3_2_reg_8114;
assign tmp_220_fu_2437_p1 = tmp_219_reg_4799;
assign tmp_221_fu_2940_p1 = tmp_20_5_3_2_reg_8439;
assign tmp_223_fu_2441_p1 = tmp_222_reg_4804;
assign tmp_224_fu_2943_p1 = tmp_20_5_4_2_reg_8444;
assign tmp_226_fu_2445_p1 = tmp_225_reg_4809;
assign tmp_227_fu_2946_p1 = tmp_20_5_5_2_reg_8449;
assign tmp_229_fu_2449_p1 = tmp_228_reg_4814;
assign tmp_230_fu_2949_p1 = tmp_20_5_6_2_reg_8454;
assign tmp_232_fu_2453_p1 = tmp_231_reg_4819;
assign tmp_233_fu_2952_p1 = tmp_20_5_7_2_reg_8459;
assign tmp_235_fu_2457_p1 = tmp_234_reg_4824;
assign tmp_236_fu_2955_p1 = tmp_20_5_8_2_reg_8464;
assign tmp_238_fu_2461_p1 = tmp_237_reg_4829;
assign tmp_239_fu_2958_p1 = tmp_20_5_9_2_reg_8469;
assign tmp_23_fu_2181_p1 = tmp_22_reg_4469;
assign tmp_241_fu_2465_p1 = tmp_240_reg_4834;
assign tmp_242_fu_2961_p1 = tmp_20_5_10_2_reg_8474;
assign tmp_244_fu_2469_p1 = tmp_243_reg_4839;
assign tmp_245_fu_2964_p1 = tmp_20_5_11_2_reg_8479;
assign tmp_247_fu_2473_p1 = tmp_246_reg_4844;
assign tmp_248_fu_2967_p1 = tmp_20_5_12_2_reg_8484;
assign tmp_249_fu_2970_p14 = {{{{{{{{{{{{{tmp_248_fu_2967_p1}, {tmp_245_fu_2964_p1}}, {tmp_242_fu_2961_p1}}, {tmp_239_fu_2958_p1}}, {tmp_236_fu_2955_p1}}, {tmp_233_fu_2952_p1}}, {tmp_230_fu_2949_p1}}, {tmp_227_fu_2946_p1}}, {tmp_224_fu_2943_p1}}, {tmp_221_fu_2940_p1}}, {tmp_218_fu_2937_p1}}, {tmp_215_fu_2934_p1}}, {tmp_212_fu_2931_p1}};
assign tmp_24_fu_2593_p1 = tmp_20_0_4_2_reg_8119;
assign tmp_250_fu_1881_p2 = (tmp_90_reg_3299 + tmp_13_3_mid2_cast_fu_1836_p1);
assign tmp_251_fu_2477_p1 = tmp_357_reg_5044;
assign tmp_252_fu_3001_p1 = tmp_20_6_0_2_reg_8489;
assign tmp_254_fu_2481_p1 = tmp_253_reg_5049;
assign tmp_255_fu_3004_p1 = tmp_20_6_1_2_reg_8494;
assign tmp_257_fu_2485_p1 = tmp_256_reg_5054;
assign tmp_258_fu_3007_p1 = tmp_20_6_2_2_reg_8499;
assign tmp_260_fu_2489_p1 = tmp_259_reg_5059;
assign tmp_261_fu_3010_p1 = tmp_20_6_3_2_reg_8504;
assign tmp_263_fu_2493_p1 = tmp_262_reg_5064;
assign tmp_264_fu_3013_p1 = tmp_20_6_4_2_reg_8509;
assign tmp_266_fu_2497_p1 = tmp_265_reg_5069;
assign tmp_267_fu_3016_p1 = tmp_20_6_5_2_reg_8514;
assign tmp_269_fu_2501_p1 = tmp_268_reg_5074;
assign tmp_26_fu_2185_p1 = tmp_25_reg_4474;
assign tmp_270_fu_3019_p1 = tmp_20_6_6_2_reg_8519;
assign tmp_272_fu_2505_p1 = tmp_271_reg_5079;
assign tmp_273_fu_3022_p1 = tmp_20_6_7_2_reg_8524;
assign tmp_275_fu_2509_p1 = tmp_274_reg_5084;
assign tmp_276_fu_3025_p1 = tmp_20_6_8_2_reg_8529;
assign tmp_278_fu_2513_p1 = tmp_277_reg_5089;
assign tmp_279_fu_3028_p1 = tmp_20_6_9_2_reg_8534;
assign tmp_27_fu_2596_p1 = tmp_20_0_5_2_reg_8124;
assign tmp_281_fu_2517_p1 = tmp_280_reg_5094;
assign tmp_282_fu_3031_p1 = tmp_20_6_10_2_reg_8539;
assign tmp_284_fu_2521_p1 = tmp_283_reg_5099;
assign tmp_285_fu_3034_p1 = tmp_20_6_11_2_reg_8544;
assign tmp_287_fu_2525_p1 = tmp_286_reg_5104;
assign tmp_288_fu_3037_p1 = tmp_20_6_12_2_reg_8549;
assign tmp_289_fu_3040_p14 = {{{{{{{{{{{{{tmp_288_fu_3037_p1}, {tmp_285_fu_3034_p1}}, {tmp_282_fu_3031_p1}}, {tmp_279_fu_3028_p1}}, {tmp_276_fu_3025_p1}}, {tmp_273_fu_3022_p1}}, {tmp_270_fu_3019_p1}}, {tmp_267_fu_3016_p1}}, {tmp_264_fu_3013_p1}}, {tmp_261_fu_3010_p1}}, {tmp_258_fu_3007_p1}}, {tmp_255_fu_3004_p1}}, {tmp_252_fu_3001_p1}};
assign tmp_290_fu_1978_p2 = (tmp_90_reg_3299 + tmp_13_4_mid2_cast_fu_1932_p1);
assign tmp_291_fu_2529_p1 = tmp_358_reg_5109;
assign tmp_292_fu_3071_p1 = tmp_20_7_0_2_reg_8554;
assign tmp_294_fu_2533_p1 = tmp_293_reg_5114;
assign tmp_295_fu_3074_p1 = tmp_20_7_1_2_reg_8559;
assign tmp_297_fu_2537_p1 = tmp_296_reg_5119;
assign tmp_298_fu_3077_p1 = tmp_20_7_2_2_reg_8564;
assign tmp_29_fu_2189_p1 = tmp_28_reg_4479;
assign tmp_2_cast_fu_1703_p1 = tmp_2_reg_3281;
assign tmp_2_cast_mid2_fu_1639_p1 = tmp_1_mid2_v_reg_3225;
assign tmp_2_fu_1657_p2 = (6'd25 + tmp_1_reg_3257);
assign tmp_300_fu_2541_p1 = tmp_299_reg_5124;
assign tmp_301_fu_3080_p1 = tmp_20_7_3_2_reg_8569;
assign tmp_303_fu_2545_p1 = tmp_302_reg_5129;
assign tmp_304_fu_3083_p1 = tmp_20_7_4_2_reg_8574;
assign tmp_306_fu_2549_p1 = tmp_305_reg_5134;
assign tmp_307_fu_3086_p1 = tmp_20_7_5_2_reg_8579;
assign tmp_309_fu_2553_p1 = tmp_308_reg_5139;
assign tmp_30_fu_2599_p1 = tmp_20_0_6_2_reg_8129;
assign tmp_310_fu_3089_p1 = tmp_20_7_6_2_reg_8584;
assign tmp_312_fu_2557_p1 = tmp_311_reg_5144;
assign tmp_313_fu_3092_p1 = tmp_20_7_7_2_reg_8589;
assign tmp_315_fu_2561_p1 = tmp_314_reg_5149;
assign tmp_316_fu_3095_p1 = tmp_20_7_8_2_reg_8594;
assign tmp_318_fu_2565_p1 = tmp_317_reg_5154;
assign tmp_319_fu_3098_p1 = tmp_20_7_9_2_reg_8599;
assign tmp_321_fu_2569_p1 = tmp_320_reg_5159;
assign tmp_322_fu_3101_p1 = tmp_20_7_10_2_reg_8604;
assign tmp_324_fu_2573_p1 = tmp_323_reg_5164;
assign tmp_325_fu_3104_p1 = tmp_20_7_11_2_reg_8609;
assign tmp_327_fu_2577_p1 = tmp_326_reg_5169;
assign tmp_328_fu_3107_p1 = tmp_20_7_12_2_reg_8614;
assign tmp_329_fu_3110_p14 = {{{{{{{{{{{{{tmp_328_fu_3107_p1}, {tmp_325_fu_3104_p1}}, {tmp_322_fu_3101_p1}}, {tmp_319_fu_3098_p1}}, {tmp_316_fu_3095_p1}}, {tmp_313_fu_3092_p1}}, {tmp_310_fu_3089_p1}}, {tmp_307_fu_3086_p1}}, {tmp_304_fu_3083_p1}}, {tmp_301_fu_3080_p1}}, {tmp_298_fu_3077_p1}}, {tmp_295_fu_3074_p1}}, {tmp_292_fu_3071_p1}};
assign tmp_32_fu_2193_p1 = tmp_31_reg_4484;
assign tmp_330_cast_fu_1910_p1 = tmp_7_reg_3356;
assign tmp_330_fu_1983_p2 = (tmp_90_reg_3299 + tmp_13_5_mid2_cast_fu_1942_p1);
assign tmp_331_fu_1988_p2 = (tmp_90_reg_3299 + tmp_13_6_mid2_cast_fu_1952_p1);
assign tmp_332_fu_1993_p2 = (tmp_90_reg_3299 + tmp_13_7_mid2_cast_fu_1962_p1);
assign tmp_333_fu_2022_p3 = {{ap_reg_pp0_iter1_row_b_mid2_reg_3245}, {3'd0}};
assign tmp_334_cast_fu_1864_p1 = $signed(tmp_130_reg_3336);
assign tmp_334_fu_2029_p1 = tmp_333_fu_2022_p3;
assign tmp_335_cast_fu_1870_p1 = $signed(tmp_170_reg_3341);
assign tmp_335_fu_2034_p2 = (tmp_333_fu_2022_p3 | 8'd1);
assign tmp_336_cast_fu_1966_p1 = tmp_210_reg_3511;
assign tmp_336_fu_2040_p3 = {{56'd0}, {tmp_335_fu_2034_p2}};
assign tmp_337_cast_fu_1972_p1 = tmp_250_reg_3516;
assign tmp_337_fu_2049_p2 = (tmp_333_reg_4307 | 8'd2);
assign tmp_338_cast_fu_1998_p1 = tmp_290_reg_3616;
assign tmp_338_fu_2054_p3 = {{56'd0}, {tmp_337_fu_2049_p2}};
assign tmp_339_cast_fu_2004_p1 = tmp_330_reg_3621;
assign tmp_339_fu_2063_p2 = (tmp_333_reg_4307 | 8'd3);
assign tmp_33_fu_2602_p1 = tmp_20_0_7_2_reg_8134;
assign tmp_340_cast_fu_2010_p1 = tmp_331_reg_3626;
assign tmp_340_fu_2068_p3 = {{56'd0}, {tmp_339_fu_2063_p2}};
assign tmp_341_cast_fu_2016_p1 = tmp_332_reg_3631;
assign tmp_341_fu_2077_p2 = (tmp_333_reg_4307 | 8'd4);
assign tmp_342_fu_2082_p3 = {{56'd0}, {tmp_341_fu_2077_p2}};
assign tmp_343_fu_2091_p2 = (tmp_333_reg_4307 | 8'd5);
assign tmp_344_fu_2096_p3 = {{56'd0}, {tmp_343_fu_2091_p2}};
assign tmp_345_fu_2113_p2 = (tmp_333_reg_4307 | 8'd6);
assign tmp_346_fu_2118_p3 = {{56'd0}, {tmp_345_fu_2113_p2}};
assign tmp_347_fu_2127_p2 = (tmp_333_reg_4307 | 8'd7);
assign tmp_348_fu_2132_p3 = {{56'd0}, {tmp_347_fu_2127_p2}};
assign tmp_350_fu_2105_p0 = bufo_Dout_A;
assign tmp_350_fu_2105_p1 = tmp_350_fu_2105_p0[31:0];
assign tmp_352_fu_2109_p0 = bufo_Dout_B;
assign tmp_352_fu_2109_p1 = tmp_352_fu_2109_p0[31:0];
assign tmp_353_fu_2141_p0 = bufo_Dout_A;
assign tmp_353_fu_2141_p1 = tmp_353_fu_2141_p0[31:0];
assign tmp_354_fu_2145_p0 = bufo_Dout_B;
assign tmp_354_fu_2145_p1 = tmp_354_fu_2145_p0[31:0];
assign tmp_355_fu_2149_p0 = bufo_Dout_A;
assign tmp_355_fu_2149_p1 = tmp_355_fu_2149_p0[31:0];
assign tmp_356_fu_2153_p0 = bufo_Dout_B;
assign tmp_356_fu_2153_p1 = tmp_356_fu_2153_p0[31:0];
assign tmp_357_fu_2157_p0 = bufo_Dout_A;
assign tmp_357_fu_2157_p1 = tmp_357_fu_2157_p0[31:0];
assign tmp_358_fu_2161_p0 = bufo_Dout_B;
assign tmp_358_fu_2161_p1 = tmp_358_fu_2161_p0[31:0];
assign tmp_35_fu_2197_p1 = tmp_34_reg_4489;
assign tmp_36_fu_2605_p1 = tmp_20_0_8_2_reg_8139;
assign tmp_38_fu_2201_p1 = tmp_37_reg_4494;
assign tmp_39_fu_2608_p1 = tmp_20_0_9_2_reg_8144;
assign tmp_3_fu_1706_p2 = (7'd50 + tmp_1_cast_fu_1700_p1);
assign tmp_41_fu_2205_p1 = tmp_40_reg_4499;
assign tmp_42_fu_2611_p1 = tmp_20_0_10_2_reg_8149;
assign tmp_44_fu_2209_p1 = tmp_43_reg_4504;
assign tmp_45_fu_2614_p1 = tmp_20_0_11_2_reg_8154;
assign tmp_47_fu_2213_p1 = tmp_46_reg_4509;
assign tmp_48_fu_2617_p1 = tmp_20_0_12_2_reg_8159;
assign tmp_49_fu_2620_p14 = {{{{{{{{{{{{{tmp_48_fu_2617_p1}, {tmp_45_fu_2614_p1}}, {tmp_42_fu_2611_p1}}, {tmp_39_fu_2608_p1}}, {tmp_36_fu_2605_p1}}, {tmp_33_fu_2602_p1}}, {tmp_30_fu_2599_p1}}, {tmp_27_fu_2596_p1}}, {tmp_24_fu_2593_p1}}, {tmp_21_fu_2590_p1}}, {tmp_18_fu_2587_p1}}, {tmp_15_fu_2584_p1}}, {tmp_12_fu_2581_p1}};
assign tmp_4_fu_1600_p2 = (tmp_7_mid_fu_1595_p2 | exitcond_flatten_reg_3190);
assign tmp_50_fu_1683_p3 = {{tmp_s_reg_3270}, {2'd0}};
assign tmp_51_fu_2217_p1 = tmp_352_reg_4514;
assign tmp_52_fu_2651_p1 = tmp_20_1_0_2_reg_8164;
assign tmp_54_fu_2221_p1 = tmp_53_reg_4519;
assign tmp_55_fu_2654_p1 = tmp_20_1_1_2_reg_8169;
assign tmp_57_fu_2225_p1 = tmp_56_reg_4524;
assign tmp_58_fu_2657_p1 = tmp_20_1_2_2_reg_8174;
assign tmp_5_fu_1565_p2 = ((ap_phi_mux_row_b_phi_fu_935_p4 == 5'd27) ? 1'b1 : 1'b0);
assign tmp_5_mid2_cast1_fu_1718_p1 = tmp_5_mid2_reg_3286;
assign tmp_5_mid2_cast2_fu_1721_p1 = tmp_5_mid2_reg_3286;
assign tmp_5_mid2_cast_fu_1724_p1 = tmp_5_mid2_reg_3286;
assign tmp_5_mid2_fu_1662_p3 = ((tmp_7_mid_reg_3233[0:0] === 1'b1) ? j_1_reg_3264 : j_mid_reg_3216);
assign tmp_60_fu_2229_p1 = tmp_59_reg_4529;
assign tmp_61_fu_2660_p1 = tmp_20_1_3_2_reg_8179;
assign tmp_63_fu_2233_p1 = tmp_62_reg_4534;
assign tmp_64_fu_2663_p1 = tmp_20_1_4_2_reg_8184;
assign tmp_66_fu_2237_p1 = tmp_65_reg_4539;
assign tmp_67_fu_2666_p1 = tmp_20_1_5_2_reg_8189;
assign tmp_69_fu_2241_p1 = tmp_68_reg_4544;
assign tmp_6_cast2_fu_1495_p1 = ap_phi_mux_j_phi_fu_923_p4;
assign tmp_6_cast2_mid1_fu_1811_p1 = j_1_reg_3264;
assign tmp_6_cast_fu_1775_p1 = tmp_6_reg_3321;
assign tmp_6_fu_1727_p2 = (tmp_1_reg_3257 + tmp_5_mid2_cast_fu_1724_p1);
assign tmp_70_fu_2669_p1 = tmp_20_1_6_2_reg_8194;
assign tmp_72_fu_2245_p1 = tmp_71_reg_4549;
assign tmp_73_fu_2672_p1 = tmp_20_1_7_2_reg_8199;
assign tmp_75_fu_2249_p1 = tmp_74_reg_4554;
assign tmp_76_fu_2675_p1 = tmp_20_1_8_2_reg_8204;
assign tmp_78_fu_2253_p1 = tmp_77_reg_4559;
assign tmp_79_fu_2678_p1 = tmp_20_1_9_2_reg_8209;
assign tmp_7_fu_1807_p2 = (tmp_3_reg_3311 + tmp_5_mid2_cast2_reg_3316);
assign tmp_7_mid_fu_1595_p2 = (tmp_5_reg_3206 & not_exitcond_flatten_fu_1590_p2);
assign tmp_81_fu_2257_p1 = tmp_80_reg_4564;
assign tmp_82_fu_2681_p1 = tmp_20_1_10_2_reg_8214;
assign tmp_84_fu_2261_p1 = tmp_83_reg_4569;
assign tmp_85_fu_2684_p1 = tmp_20_1_11_2_reg_8219;
assign tmp_87_fu_2265_p1 = tmp_86_reg_4574;
assign tmp_88_fu_2687_p1 = tmp_20_1_12_2_reg_8224;
assign tmp_89_fu_2690_p14 = {{{{{{{{{{{{{tmp_88_fu_2687_p1}, {tmp_85_fu_2684_p1}}, {tmp_82_fu_2681_p1}}, {tmp_79_fu_2678_p1}}, {tmp_76_fu_2675_p1}}, {tmp_73_fu_2672_p1}}, {tmp_70_fu_2669_p1}}, {tmp_67_fu_2666_p1}}, {tmp_64_fu_2663_p1}}, {tmp_61_fu_2660_p1}}, {tmp_58_fu_2657_p1}}, {tmp_55_fu_2654_p1}}, {tmp_52_fu_2651_p1}};
assign tmp_8_cast_fu_1791_p1 = tmp_8_reg_3326;
assign tmp_8_fu_1732_p2 = (tmp_2_cast_fu_1703_p1 + tmp_5_mid2_cast2_fu_1721_p1);
assign tmp_90_fu_1694_p2 = (p_shl_cast_fu_1679_p1 - p_shl1_cast_fu_1690_p1);
assign tmp_91_fu_2269_p1 = tmp_353_reg_4589;
assign tmp_92_fu_2721_p1 = tmp_20_2_0_2_reg_8229;
assign tmp_94_fu_2273_p1 = tmp_93_reg_4594;
assign tmp_95_fu_2724_p1 = tmp_20_2_1_2_reg_8234;
assign tmp_97_fu_2277_p1 = tmp_96_reg_4599;
assign tmp_98_fu_2727_p1 = tmp_20_2_2_2_reg_8239;
assign tmp_fu_1622_p3 = {{tmp_1_mid2_v_reg_3225}, {2'd0}};
assign tmp_s_fu_1647_p2 = (tmp_2_cast_mid2_fu_1639_p1 + row_b_mid2_reg_3245);
always @ (posedge ap_clk) begin
tmp_90_reg_3299[1:0] <= 2'b00;
tmp_5_mid2_cast2_reg_3316[6:3] <= 4'b0000;
tmp_333_reg_4307[2:0] <= 3'b000;
bufo_addr_reg_4317[2:0] <= 3'b000;
ap_reg_pp0_iter2_bufo_addr_reg_4317[2:0] <= 3'b000;
ap_reg_pp0_iter3_bufo_addr_reg_4317[2:0] <= 3'b000;
ap_reg_pp0_iter4_bufo_addr_reg_4317[2:0] <= 3'b000;
ap_reg_pp0_iter5_bufo_addr_reg_4317[2:0] <= 3'b000;
ap_reg_pp0_iter6_bufo_addr_reg_4317[2:0] <= 3'b000;
ap_reg_pp0_iter7_bufo_addr_reg_4317[2:0] <= 3'b000;
bufo_addr_1_reg_4322[2:0] <= 3'b001;
ap_reg_pp0_iter2_bufo_addr_1_reg_4322[2:0] <= 3'b001;
ap_reg_pp0_iter3_bufo_addr_1_reg_4322[2:0] <= 3'b001;
ap_reg_pp0_iter4_bufo_addr_1_reg_4322[2:0] <= 3'b001;
ap_reg_pp0_iter5_bufo_addr_1_reg_4322[2:0] <= 3'b001;
ap_reg_pp0_iter6_bufo_addr_1_reg_4322[2:0] <= 3'b001;
ap_reg_pp0_iter7_bufo_addr_1_reg_4322[2:0] <= 3'b001;
bufo_addr_2_reg_4429[2:0] <= 3'b010;
ap_reg_pp0_iter2_bufo_addr_2_reg_4429[2:0] <= 3'b010;
ap_reg_pp0_iter3_bufo_addr_2_reg_4429[2:0] <= 3'b010;
ap_reg_pp0_iter4_bufo_addr_2_reg_4429[2:0] <= 3'b010;
ap_reg_pp0_iter5_bufo_addr_2_reg_4429[2:0] <= 3'b010;
ap_reg_pp0_iter6_bufo_addr_2_reg_4429[2:0] <= 3'b010;
ap_reg_pp0_iter7_bufo_addr_2_reg_4429[2:0] <= 3'b010;
bufo_addr_3_reg_4434[2:0] <= 3'b011;
ap_reg_pp0_iter2_bufo_addr_3_reg_4434[2:0] <= 3'b011;
ap_reg_pp0_iter3_bufo_addr_3_reg_4434[2:0] <= 3'b011;
ap_reg_pp0_iter4_bufo_addr_3_reg_4434[2:0] <= 3'b011;
ap_reg_pp0_iter5_bufo_addr_3_reg_4434[2:0] <= 3'b011;
ap_reg_pp0_iter6_bufo_addr_3_reg_4434[2:0] <= 3'b011;
ap_reg_pp0_iter7_bufo_addr_3_reg_4434[2:0] <= 3'b011;
bufo_addr_4_reg_4439[2:0] <= 3'b100;
ap_reg_pp0_iter2_bufo_addr_4_reg_4439[2:0] <= 3'b100;
ap_reg_pp0_iter3_bufo_addr_4_reg_4439[2:0] <= 3'b100;
ap_reg_pp0_iter4_bufo_addr_4_reg_4439[2:0] <= 3'b100;
ap_reg_pp0_iter5_bufo_addr_4_reg_4439[2:0] <= 3'b100;
ap_reg_pp0_iter6_bufo_addr_4_reg_4439[2:0] <= 3'b100;
ap_reg_pp0_iter7_bufo_addr_4_reg_4439[2:0] <= 3'b100;
bufo_addr_5_reg_4444[2:0] <= 3'b101;
ap_reg_pp0_iter2_bufo_addr_5_reg_4444[2:0] <= 3'b101;
ap_reg_pp0_iter3_bufo_addr_5_reg_4444[2:0] <= 3'b101;
ap_reg_pp0_iter4_bufo_addr_5_reg_4444[2:0] <= 3'b101;
ap_reg_pp0_iter5_bufo_addr_5_reg_4444[2:0] <= 3'b101;
ap_reg_pp0_iter6_bufo_addr_5_reg_4444[2:0] <= 3'b101;
ap_reg_pp0_iter7_bufo_addr_5_reg_4444[2:0] <= 3'b101;
bufo_addr_6_reg_4579[2:0] <= 3'b110;
ap_reg_pp0_iter2_bufo_addr_6_reg_4579[2:0] <= 3'b110;
ap_reg_pp0_iter3_bufo_addr_6_reg_4579[2:0] <= 3'b110;
ap_reg_pp0_iter4_bufo_addr_6_reg_4579[2:0] <= 3'b110;
ap_reg_pp0_iter5_bufo_addr_6_reg_4579[2:0] <= 3'b110;
ap_reg_pp0_iter6_bufo_addr_6_reg_4579[2:0] <= 3'b110;
ap_reg_pp0_iter7_bufo_addr_6_reg_4579[2:0] <= 3'b110;
ap_reg_pp0_iter8_bufo_addr_6_reg_4579[2:0] <= 3'b110;
bufo_addr_7_reg_4584[2:0] <= 3'b111;
ap_reg_pp0_iter2_bufo_addr_7_reg_4584[2:0] <= 3'b111;
ap_reg_pp0_iter3_bufo_addr_7_reg_4584[2:0] <= 3'b111;
ap_reg_pp0_iter4_bufo_addr_7_reg_4584[2:0] <= 3'b111;
ap_reg_pp0_iter5_bufo_addr_7_reg_4584[2:0] <= 3'b111;
ap_reg_pp0_iter6_bufo_addr_7_reg_4584[2:0] <= 3'b111;
ap_reg_pp0_iter7_bufo_addr_7_reg_4584[2:0] <= 3'b111;
ap_reg_pp0_iter8_bufo_addr_7_reg_4584[2:0] <= 3'b111;
end
endmodule //convolve_kernel
|
//-----------------------------------------------------------------------------
//-- Divisor de reloj
//-- Señal de periodo igual al indicado
//-- El ancho del pulso positivo es de 1 ciclo de reloj
//--
//-- (c) BQ. September 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`include "divider.vh"
//-- ENTRADAS:
//-- -clk: Senal de reloj del sistema (12 MHZ en la iceStick)
//
//-- SALIDAS:
//-- - clk_out. Señal de salida para lograr la velocidad en baudios indicada
//-- Anchura de 1 periodo de clk. SALIDA NO REGISTRADA
module dividerp1(input wire clk,
input wire timer_ena,
output wire clk_out);
//-- Valor por defecto de la velocidad en baudios
parameter M = `T_100ms;
//-- Numero de bits para almacenar el divisor de baudios
localparam N = $clog2(M);
//-- Registro para implementar el contador modulo M
reg [N-1:0] divcounter = 0;
//-- Contador modulo M
always @(posedge clk)
if (timer_ena)
divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1;
else
divcounter <= 0;
//-- Sacar un pulso de anchura 1 ciclo de reloj si el generador
assign clk_out = (divcounter == M - 1) ? 1 : 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFBUF_8_V
`define SKY130_FD_SC_HS__BUFBUF_8_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufbuf_8 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFBUF_8_V
|
// Copyright 2021 The CFU-Playground Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
module Cfu (
input cmd_valid,
output cmd_ready,
input [9:0] cmd_payload_function_id,
input [31:0] cmd_payload_inputs_0,
input [31:0] cmd_payload_inputs_1,
output rsp_valid,
input rsp_ready,
output [31:0] rsp_payload_outputs_0,
input reset,
input clk
);
// Trivial handshaking for a combinational CFU
assign rsp_valid = cmd_valid;
assign cmd_ready = rsp_ready;
//
// select output -- note that we're not fully decoding the 3 function_id bits
//
assign rsp_payload_outputs_0 = cmd_payload_function_id[0] ?
cmd_payload_inputs_1 :
cmd_payload_inputs_0 ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4_BEHAVIORAL_V
`define SKY130_FD_SC_HD__NOR4_BEHAVIORAL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nor4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4B_BLACKBOX_V
`define SKY130_FD_SC_LP__NAND4B_BLACKBOX_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand4b (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4B_BLACKBOX_V
|
`timescale 1ps / 1ps
module main;
reg clk = 0;
always #300 clk = !clk;
reg [4:0] in = "11111";
reg [1:0] out;
reg [1:0] out_golden;
integer seed = 1234;
integer rvec_file;
integer ret;
integer soe0 = 0;
integer soe1 = 0;
initial begin
$sdf_annotate("mydesign.sdf",DUT,,,"MAXIMUM");
$dumpfile("test.vcd");
$dumpvars(0,main);
assert($urandom(seed));
`ifdef GENTEST
rvec_file = $fopen("../c17.rvec", "w");
`else
rvec_file = $fopen("../c17.rvec", "r");
`endif
if (rvec_file == 0) begin
$display("data_file handle was NULL");
$finish;
end
end
integer num_cycles = 0;
integer max_cycles = 100000;
always @ (posedge clk) begin
std::randomize(in);
if (num_cycles == max_cycles) begin
$display("SoE: %d,%d\n",soe0,soe1);
$fclose(rvec_file);
$finish;
end
num_cycles = num_cycles + 1;
end
c17 DUT (clk,in[0],in[1],in[2],in[3],in[4],out[0],out[1]);
always @ (posedge clk) begin
`ifdef GENTEST
// write output to generate golden result
$fwrite(rvec_file, "%b,%b\n", out[0],out[1]);
`else
$fscanf(rvec_file, "%b,%b\n", out_golden[0],out_golden[1]);
if (out[0] != out_golden[0]) begin
//$display("ERROR At time %t: out[0]=%b",$time,out[0]);
soe0 = soe0 + 1;
end
if (out[1] != out_golden[1]) begin
soe1 = soe1 + 1;
end
`endif
end // always @ (posedge clk)
always @(posedge clk) begin
//$display("At time %t: out[0]=%b,%b - out[1]=%b,%b",$time,out[0],out_golden[0],out[1],out_golden[1]);
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_adc_channel (
// adc interface
adc_clk,
adc_rst,
adc_enable,
adc_iqcor_enb,
adc_dcfilt_enb,
adc_dfmt_se,
adc_dfmt_type,
adc_dfmt_enable,
adc_dcfilt_offset,
adc_dcfilt_coeff,
adc_iqcor_coeff_1,
adc_iqcor_coeff_2,
adc_pnseq_sel,
adc_data_sel,
adc_pn_err,
adc_pn_oos,
adc_or,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// user controls
up_usr_datatype_be,
up_usr_datatype_signed,
up_usr_datatype_shift,
up_usr_datatype_total_bits,
up_usr_datatype_bits,
up_usr_decimation_m,
up_usr_decimation_n,
adc_usr_datatype_be,
adc_usr_datatype_signed,
adc_usr_datatype_shift,
adc_usr_datatype_total_bits,
adc_usr_datatype_bits,
adc_usr_decimation_m,
adc_usr_decimation_n,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter PCORE_ADC_CHID = 4'h0;
// adc interface
input adc_clk;
input adc_rst;
output adc_enable;
output adc_iqcor_enb;
output adc_dcfilt_enb;
output adc_dfmt_se;
output adc_dfmt_type;
output adc_dfmt_enable;
output [15:0] adc_dcfilt_offset;
output [15:0] adc_dcfilt_coeff;
output [15:0] adc_iqcor_coeff_1;
output [15:0] adc_iqcor_coeff_2;
output [ 3:0] adc_pnseq_sel;
output [ 3:0] adc_data_sel;
input adc_pn_err;
input adc_pn_oos;
input adc_or;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// user controls
output up_usr_datatype_be;
output up_usr_datatype_signed;
output [ 7:0] up_usr_datatype_shift;
output [ 7:0] up_usr_datatype_total_bits;
output [ 7:0] up_usr_datatype_bits;
output [15:0] up_usr_decimation_m;
output [15:0] up_usr_decimation_n;
input adc_usr_datatype_be;
input adc_usr_datatype_signed;
input [ 7:0] adc_usr_datatype_shift;
input [ 7:0] adc_usr_datatype_total_bits;
input [ 7:0] adc_usr_datatype_bits;
input [15:0] adc_usr_decimation_m;
input [15:0] adc_usr_decimation_n;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 'd0;
reg up_adc_lb_enb = 'd0;
reg up_adc_pn_sel = 'd0;
reg up_adc_iqcor_enb = 'd0;
reg up_adc_dcfilt_enb = 'd0;
reg up_adc_dfmt_se = 'd0;
reg up_adc_dfmt_type = 'd0;
reg up_adc_dfmt_enable = 'd0;
reg up_adc_pn_type = 'd0;
reg up_adc_enable = 'd0;
reg up_adc_pn_err = 'd0;
reg up_adc_pn_oos = 'd0;
reg up_adc_or = 'd0;
reg [15:0] up_adc_dcfilt_offset = 'd0;
reg [15:0] up_adc_dcfilt_coeff = 'd0;
reg [15:0] up_adc_iqcor_coeff_1 = 'd0;
reg [15:0] up_adc_iqcor_coeff_2 = 'd0;
reg [ 3:0] up_adc_pnseq_sel = 'd0;
reg [ 3:0] up_adc_data_sel = 'd0;
reg up_usr_datatype_be = 'd0;
reg up_usr_datatype_signed = 'd0;
reg [ 7:0] up_usr_datatype_shift = 'd0;
reg [ 7:0] up_usr_datatype_total_bits = 'd0;
reg [ 7:0] up_usr_datatype_bits = 'd0;
reg [15:0] up_usr_decimation_m = 'd0;
reg [15:0] up_usr_decimation_n = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg [15:0] up_adc_iqcor_coeff_tc_1 = 'd0;
reg [15:0] up_adc_iqcor_coeff_tc_2 = 'd0;
reg [ 3:0] up_adc_pnseq_sel_m = 'd0;
reg [ 3:0] up_adc_data_sel_m = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_adc_pn_err_s;
wire up_adc_pn_oos_s;
wire up_adc_or_s;
// 2's complement function
function [15:0] sm2tc;
input [15:0] din;
reg [15:0] dp;
reg [15:0] dn;
reg [15:0] dout;
begin
dp = {1'b0, din[14:0]};
dn = ~dp + 1'b1;
dout = (din[15] == 1'b1) ? dn : dp;
sm2tc = dout;
end
endfunction
// decode block select
assign up_wreq_s = ((up_waddr[13:8] == 6'h01) && (up_waddr[7:4] == PCORE_ADC_CHID)) ? up_wreq : 1'b0;
assign up_rreq_s = ((up_raddr[13:8] == 6'h01) && (up_raddr[7:4] == PCORE_ADC_CHID)) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_adc_lb_enb <= 'd0;
up_adc_pn_sel <= 'd0;
up_adc_iqcor_enb <= 'd0;
up_adc_dcfilt_enb <= 'd0;
up_adc_dfmt_se <= 'd0;
up_adc_dfmt_type <= 'd0;
up_adc_dfmt_enable <= 'd0;
up_adc_pn_type <= 'd0;
up_adc_enable <= 'd0;
up_adc_pn_err <= 'd0;
up_adc_pn_oos <= 'd0;
up_adc_or <= 'd0;
up_adc_dcfilt_offset <= 'd0;
up_adc_dcfilt_coeff <= 'd0;
up_adc_iqcor_coeff_1 <= 'd0;
up_adc_iqcor_coeff_2 <= 'd0;
up_adc_pnseq_sel <= 'd0;
up_adc_data_sel <= 'd0;
up_usr_datatype_be <= 'd0;
up_usr_datatype_signed <= 'd0;
up_usr_datatype_shift <= 'd0;
up_usr_datatype_total_bits <= 'd0;
up_usr_datatype_bits <= 'd0;
up_usr_decimation_m <= 'd0;
up_usr_decimation_n <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
up_adc_lb_enb <= up_wdata[11];
up_adc_pn_sel <= up_wdata[10];
up_adc_iqcor_enb <= up_wdata[9];
up_adc_dcfilt_enb <= up_wdata[8];
up_adc_dfmt_se <= up_wdata[6];
up_adc_dfmt_type <= up_wdata[5];
up_adc_dfmt_enable <= up_wdata[4];
up_adc_pn_type <= up_wdata[1];
up_adc_enable <= up_wdata[0];
end
if (up_adc_pn_err_s == 1'b1) begin
up_adc_pn_err <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
up_adc_pn_err <= up_adc_pn_err & ~up_wdata[2];
end
if (up_adc_pn_oos_s == 1'b1) begin
up_adc_pn_oos <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
up_adc_pn_oos <= up_adc_pn_oos & ~up_wdata[1];
end
if (up_adc_or_s == 1'b1) begin
up_adc_or <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
up_adc_or <= up_adc_or & ~up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin
up_adc_dcfilt_offset <= up_wdata[31:16];
up_adc_dcfilt_coeff <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin
up_adc_iqcor_coeff_1 <= up_wdata[31:16];
up_adc_iqcor_coeff_2 <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin
up_adc_pnseq_sel <= up_wdata[19:16];
up_adc_data_sel <= up_wdata[3:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin
up_usr_datatype_be <= up_wdata[25];
up_usr_datatype_signed <= up_wdata[24];
up_usr_datatype_shift <= up_wdata[23:16];
up_usr_datatype_total_bits <= up_wdata[15:8];
up_usr_datatype_bits <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin
up_usr_decimation_m <= up_wdata[31:16];
up_usr_decimation_n <= up_wdata[15:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[3:0])
4'h0: up_rdata <= {20'd0, up_adc_lb_enb, up_adc_pn_sel,
up_adc_iqcor_enb, up_adc_dcfilt_enb,
1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable,
2'd0, up_adc_pn_type, up_adc_enable};
4'h1: up_rdata <= {29'd0, up_adc_pn_err, up_adc_pn_oos, up_adc_or};
4'h4: up_rdata <= {up_adc_dcfilt_offset, up_adc_dcfilt_coeff};
4'h5: up_rdata <= {up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2};
4'h6: up_rdata <= {12'd0, up_adc_pnseq_sel, 12'd0, up_adc_data_sel};
4'h8: up_rdata <= {6'd0, adc_usr_datatype_be, adc_usr_datatype_signed,
adc_usr_datatype_shift, adc_usr_datatype_total_bits,
adc_usr_datatype_bits};
4'h9: up_rdata <= {adc_usr_decimation_m, adc_usr_decimation_n};
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// change coefficients to 2's complements
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_iqcor_coeff_tc_1 <= 16'd0;
up_adc_iqcor_coeff_tc_2 <= 16'd0;
end else begin
up_adc_iqcor_coeff_tc_1 <= sm2tc(up_adc_iqcor_coeff_1);
up_adc_iqcor_coeff_tc_2 <= sm2tc(up_adc_iqcor_coeff_2);
end
end
// data/pn sources
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_pnseq_sel_m <= 4'd0;
up_adc_data_sel_m <= 4'd0;
end else begin
case ({up_adc_pn_type, up_adc_pn_sel})
2'b10: up_adc_pnseq_sel_m <= 4'h1;
2'b01: up_adc_pnseq_sel_m <= 4'h9;
default: up_adc_pnseq_sel_m <= up_adc_pnseq_sel;
endcase
if (up_adc_lb_enb == 1'b1) begin
up_adc_data_sel_m <= 4'h1;
end else begin
up_adc_data_sel_m <= up_adc_data_sel;
end
end
end
// adc control & status
up_xfer_cntrl #(.DATA_WIDTH(78)) i_adc_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_adc_iqcor_enb,
up_adc_dcfilt_enb,
up_adc_dfmt_se,
up_adc_dfmt_type,
up_adc_dfmt_enable,
up_adc_enable,
up_adc_dcfilt_offset,
up_adc_dcfilt_coeff,
up_adc_iqcor_coeff_tc_1,
up_adc_iqcor_coeff_tc_2,
up_adc_pnseq_sel_m,
up_adc_data_sel_m}),
.up_xfer_done (),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_cntrl ({ adc_iqcor_enb,
adc_dcfilt_enb,
adc_dfmt_se,
adc_dfmt_type,
adc_dfmt_enable,
adc_enable,
adc_dcfilt_offset,
adc_dcfilt_coeff,
adc_iqcor_coeff_1,
adc_iqcor_coeff_2,
adc_pnseq_sel,
adc_data_sel}));
up_xfer_status #(.DATA_WIDTH(3)) i_adc_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_adc_pn_err_s,
up_adc_pn_oos_s,
up_adc_or_s}),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_status ({ adc_pn_err,
adc_pn_oos,
adc_or}));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//
// Copyright (c) 2014 Colin Rothwell
// Copyright (c) 2014 A. Theodore Markettos
// All rights reserved.
//
// This software was developed by SRI International and the University of
// Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
// ("CTSRD"), as part of the DARPA CRASH research programme.
//
// @BERI_LICENSE_HEADER_START@
//
// Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. BERI licenses this
// file to you under the BERI Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.beri-open-systems.org/legal/license-1-0.txt
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @BERI_LICENSE_HEADER_END@
//
// intermediary between Bluespec, which outputs an enable signal,
// and Megawizard's verilog, which doesn't have that input
module doubleAddWrapper (
clock,
dataa,
datab,
result,
dummy_enable);
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
input dummy_enable;
doubleAdd doubleAdd_component (
.clock(clock),
.dataa(dataa),
.datab(datab),
.result(result)
);
endmodule
|
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_b2s_simple_fifo
`default_nettype wire
|
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_b2s_simple_fifo
`default_nettype wire
|
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_b2s_simple_fifo
`default_nettype wire
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_1_3_bhv_ver_as
* |
* +-fifo_generator_v13_1_3_bhv_ver_ss
* |
* +-fifo_generator_v13_1_3_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_3_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_3_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_1_3
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_1_3_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy_o,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
wire rst_asreg_d1;
wire rst_asreg_d2;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire fifo_empty_fb;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire safety_ckt_wr_rst;
wire safety_ckt_rd_rst;
reg sckt_wr_rst_i_q = 1'b0;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
always @ (posedge clk_i)
sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy};
end endgenerate
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v13_1_3_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_1_3_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= 1;
ALMOSTEMPTY_P0_OUT_Q <= 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
(C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};
reg [1:0] wrst_cc = {2{1'b0}};
reg [1:0] rrst_cc = {2{1'b0}};
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
reg safety_ckt_wr_rst_i = 1'b0;
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
// end : gnrst_sync
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
reg fifo_wrst_done = 1'b0;
reg fifo_rrst_done = 1'b0;
reg sckt_wrst_i = 1'b0;
reg sckt_wrst_i_q = 1'b0;
reg rd_rst_active = 1'b0;
reg rd_rst_middle = 1'b0;
reg sckt_rd_rst_d1 = 1'b0;
reg [1:0] rst_delayed_ic_w = 2'h0;
wire rst_delayed_ic_w_i;
reg [1:0] rst_delayed_ic_r = 2'h0;
wire rst_delayed_ic_r_i;
wire arst_sync_rst;
wire fifo_rst_done;
wire fifo_rst_active;
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed_ic_w_i;
assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;
assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;
assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_w <= 2'b11;
else
rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};
end
assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_r <= 2'b11;
else
rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};
end
assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
always @(posedge WR_CLK) begin
sckt_wrst_i_q <= #`TCQ sckt_wrst_i;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
if (arst_sync_rst && ~fifo_rst_active)
sckt_wrst_i <= #`TCQ 1'b1;
else if (sckt_wrst_i && fifo_rst_done)
sckt_wrst_i <= #`TCQ 1'b0;
else
sckt_wrst_i <= #`TCQ sckt_wrst_i;
if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
fifo_rrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_rrst_done <= #`TCQ 1'b0;
else
fifo_rrst_done <= #`TCQ fifo_rrst_done;
if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
fifo_wrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_wrst_done <= #`TCQ 1'b0;
else
fifo_wrst_done <= #`TCQ fifo_wrst_done;
end
always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
if (rst_delayed_ic_w_i == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
end
assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
if (rst_delayed_ic_r_i == 1'b1) begin
rd_rst_asreg <= 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;
if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
rd_rst_active <= #`TCQ 1'b1;
rd_rst_middle <= #`TCQ 1'b1;
end else if (safety_ckt_rd_rst)
rd_rst_active <= #`TCQ 1'b0;
else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
rd_rst_middle <= #`TCQ 1'b0;
end
assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_ic_rst
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
reg [1:0] rst_delayed_cc = 2'h0;
wire rst_delayed_cc_i;
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed_cc_i;
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
rst_delayed_cc <= 2'b11;
else
rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};
end
assign rst_delayed_cc_i = rst_delayed_cc[1];
always @(posedge CLK or posedge rst_delayed_cc_i) begin
if (rst_delayed_cc_i == 1'b1) begin
rst_asreg <= 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
end
assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_cc_rst
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
// end : g8s_cc_rst
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
assign safety_ckt_wr_rst = 1'b0;
assign safety_ckt_rd_rst = 1'b0;
end
endgenerate
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d3;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule //fifo_generator_v13_1_3_conv_ver
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_1_3_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input SAFETY_CKT_WR_RST,
input SAFETY_CKT_RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg EMPTY_FB = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
EMPTY_FB <= #`TCQ 1'b1;
else if (empty_int)
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ 1'b0;
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= 0;
stage2_valid <= 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule // fifo_generator_v13_1_3_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input SAFETY_CKT_WR_RST,
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output reg EMPTY_FB = 1'b1,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_1_3_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// A quick define to help index 32-bit words inside a larger register.
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
// Perform a SHA-256 transformation on the given 512-bit data, and 256-bit
// initial state,
// Outputs one 256-bit hash every LOOP cycle(s).
//
// The LOOP parameter determines both the size and speed of this module.
// A value of 1 implies a fully unrolled SHA-256 calculation spanning 64 round
// modules and calculating a full SHA-256 hash every clock cycle. A value of
// 2 implies a half-unrolled loop, with 32 round modules and calculating
// a full hash in 2 clock cycles. And so forth.
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
// These are declared as registers in sha256_digester
wire [511:0] W; // reg tx_w
wire [255:0] state; // reg tx_state
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// A quick define to help index 32-bit words inside a larger register.
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
// Perform a SHA-256 transformation on the given 512-bit data, and 256-bit
// initial state,
// Outputs one 256-bit hash every LOOP cycle(s).
//
// The LOOP parameter determines both the size and speed of this module.
// A value of 1 implies a fully unrolled SHA-256 calculation spanning 64 round
// modules and calculating a full SHA-256 hash every clock cycle. A value of
// 2 implies a half-unrolled loop, with 32 round modules and calculating
// a full hash in 2 clock cycles. And so forth.
module sha256_transform #(
parameter LOOP = 7'd64 // For ltcminer
) (
input clk,
input feedback,
input [5:0] cnt,
input [255:0] rx_state,
input [511:0] rx_input,
output reg [255:0] tx_hash
);
// Constants defined by the SHA-2 standard.
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
genvar i;
generate
for (i = 0; i < 64/LOOP; i = i + 1) begin : HASHERS
// These are declared as registers in sha256_digester
wire [511:0] W; // reg tx_w
wire [255:0] state; // reg tx_state
if(i == 0)
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-cnt) +: 32]),
.rx_w(feedback ? W : rx_input),
.rx_state(feedback ? state : rx_state),
.tx_w(W),
.tx_state(state)
);
else
sha256_digester U (
.clk(clk),
.k(Ks[32*(63-LOOP*i-cnt) +: 32]),
.rx_w(feedback ? W : HASHERS[i-1].W),
.rx_state(feedback ? state : HASHERS[i-1].state),
.tx_w(W),
.tx_state(state)
);
end
endgenerate
always @ (posedge clk)
begin
if (!feedback)
begin
tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
end
end
endmodule
module sha256_digester (clk, k, rx_w, rx_state, tx_w, tx_state);
input clk;
input [31:0] k;
input [511:0] rx_w;
input [255:0] rx_state;
output reg [511:0] tx_w;
output reg [255:0] tx_state;
wire [31:0] e0_w, e1_w, ch_w, maj_w, s0_w, s1_w;
e0 e0_blk (rx_state[`IDX(0)], e0_w);
e1 e1_blk (rx_state[`IDX(4)], e1_w);
ch ch_blk (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0 s0_blk (rx_w[63:32], s0_w);
s1 s1_blk (rx_w[479:448], s1_w);
wire [31:0] t1 = rx_state[`IDX(7)] + e1_w + ch_w + rx_w[31:0] + k;
wire [31:0] t2 = e0_w + maj_w;
wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
always @ (posedge clk)
begin
tx_w[511:480] <= new_w;
tx_w[479:0] <= rx_w[511:32];
tx_state[`IDX(7)] <= rx_state[`IDX(6)];
tx_state[`IDX(6)] <= rx_state[`IDX(5)];
tx_state[`IDX(5)] <= rx_state[`IDX(4)];
tx_state[`IDX(4)] <= rx_state[`IDX(3)] + t1;
tx_state[`IDX(3)] <= rx_state[`IDX(2)];
tx_state[`IDX(2)] <= rx_state[`IDX(1)];
tx_state[`IDX(1)] <= rx_state[`IDX(0)];
tx_state[`IDX(0)] <= t1 + t2;
end
endmodule
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
`include "hi_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
`include "hi_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
`include "hi_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
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