text
stringlengths 938
1.05M
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`timescale 1ns / 1ps
`include "Defintions.v"
module MiniAlu
(
input wire Clock,
input wire Reset,
output wire [7:0] oLed
output wire VGA_HSYNC,
output wire VGA_VSYNC,
output wire VGA_RED,
output wire VGA_GREEN,
output wire VGA_BLUE
);
wire [15:0] wIP,wIP_temp,wIP_return;
reg rWriteEnable,rBranchTaken,rReturn,rCall;
wire [27:0] wInstruction;
wire [3:0] wOperation;
reg [15:0] rResult;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination, wDestinationPrev;
wire [15:0] wSourceData0,wSourceData1,wSourceData0_RAM,wSourceData1_RAM,wResultPrev,wIPInitialValue,wDestinationJump,wImmediateValue;
wire wHazard0, wHazard1, wWriteEnablePrev, wIsImmediate,wPushAddr;
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wInstruction[7:0] ),
.iReadAddress1( wInstruction[15:8] ),
.iWriteAddress( wDestination ),
.iDataIn( rResult ),
.oDataOut0( wSourceData0_RAM ),
.oDataOut1( wSourceData1_RAM )
);
assign wDestinationJump = (rReturn) ? wIP_return : wDestination;
assign wIPInitialValue = (Reset) ? 8'b0 : wDestinationJump;
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 16'd1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( rFFLedEN ),
.D( wSourceData1[7:0] ),
.Q( oLed )
);
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
/////////////////////////////////
// Data Hazards en el pipeline //
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD41
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wDestination),
.Q(wDestinationPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FFDRES
(
.Clock(Clock),
.Reset(Reset),
.Enable(rWriteEnable),
.D(rResult),
.Q(wResultPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFDWRITE
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D( {rWriteEnable} ),
.Q( {wWriteEnablePrev} )
);
assign wIsImmediate = wOperation[3] && wOperation[2];
assign wHazard0 = ((wDestinationPrev == wSourceAddr0) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wHazard1 = ((wDestinationPrev == wSourceAddr1) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wSourceData0 = (wHazard0) ? wResultPrev : wSourceData0_RAM;
assign wSourceData1 = (wHazard1) ? wResultPrev : wSourceData1_RAM;
// //
/////////////////////////////////
/////////////////////////////////
// CALL RET //
// assign wPushAddr = (wInstruction[27:24] == `CALL);
//assign wPushAddr = (wOperation == `CALL);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FF_RET
(
.Clock(~Clock),
.Reset(Reset),
.Enable( rCall ),
.D( wIP_temp ),
.Q( wIP_return )
);
// //
/////////////////////////////////
//////////////////////////////
// VGA Controler and Memory //
VGA_Controller vga (
.Clock(Clock),
.Enable(1'b1),
.Reset(Reset),
.iPixel(`RED),
.oHorizontalSync(VGA_HSYNC),
.oVerticalSync(VGA_VSYNC),
.oRed(VGA_RED),
.oGreen(VGA_GREEN),
.oBlue(VGA_BLUE)
);
// Instanciar memoria aqui
// //
//////////////////////////////
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 + wSourceData0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`SUB:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 - wSourceData0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
rResult <= wImmediateValue;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`CALL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b0;
rCall <= 1'b1;
end
//-------------------------------------
`RET:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b1;
rCall <= 1'b0;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
`WRITE_ROM :
begin
if (row <= 200){
}else if(row <= 400){
}else if (row <= 600) {
}else if(row <= 800) {}
end
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
endcase
end
endmodule |
(*
Copyright 2014 Cornell University
This file is part of VPrl (the Verified Nuprl project).
VPrl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VPrl is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VPrl. If not, see <http://www.gnu.org/licenses/>.
Website: http://nuprl.org/html/verification/
Authors: Abhishek Anand & Vincent Rahli
*)
Require Import rules_useful.
(** printing |- $\vdash$ *)
(** printing -> $\rightarrow$ *)
(* begin hide *)
(* end hide *)
(**
The following rule states that we can always replace an [a] for a
[b] in the conclusion of a sequent if [a] and [b] are
computationally equivalent:
<<
H |- C[a] ext t
By cequivSubstConcl
H |- C[b] ext t
H |- a ~ b
>>
*)
Definition rule_cequiv_subst_concl {o}
(H : @barehypotheses o)
(x : NVar)
(C a b t : NTerm) :=
mk_rule
(mk_baresequent H (mk_concl (subst C x a) t))
[ mk_baresequent H (mk_concl (subst C x b) t),
mk_baresequent H (mk_conclax (mk_cequiv a b))
]
[].
Lemma rule_cequiv_subst_concl_true {o} :
forall lib (H : @barehypotheses o)
(x : NVar)
(C a b t : NTerm)
(bc1 : disjoint (free_vars a) (bound_vars C))
(bc2 : disjoint (free_vars b) (bound_vars C)),
rule_true lib (rule_cequiv_subst_concl H x C a b t).
Proof.
intros.
unfold rule_cequiv_subst_concl, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
clear cargs.
destseq; allsimpl.
dLin_hyp.
destruct Hyp as [wf1 hyp1].
destruct Hyp0 as [wf2 hyp2].
unfold closed_extract; simpl.
assert (covered t (nh_vars_hyps H))
as cov by (clear hyp1 hyp2; dwfseq; intros; discover; sp).
exists cov.
(* We prove some simple facts on our sequents *)
(* xxx *)
(* done with proving these simple facts *)
vr_seq_true.
vr_seq_true in hyp1.
vr_seq_true in hyp2.
destruct wf1 as [ws1 cl1].
destruct cl1 as [ct1 ce1].
destruct ws1 as [wh1 wc1].
destruct wc1 as [wT1 we1].
destruct wf2 as [ws2 cl2].
destruct cl2 as [ct2 ce2].
destruct ws2 as [wh2 wc2].
destruct wc2 as [wT2 we2].
allunfold @closed_type; allunfold @closed_extract; allsimpl.
dup wT2 as w.
rw <- @wf_cequiv_iff in w; destruct w as [wa wb].
assert (cover_vars a s1) as cova1 by (clear hyp1 hyp2; rw @covered_cequiv in ct2; repnd; rw @cover_vars_eq; insub).
assert (cover_vars a s2) as cova2 by (clear hyp1 hyp2; rw @covered_cequiv in ct2; repnd; rw @cover_vars_eq; insub).
assert (cover_vars b s1) as covb1 by (clear hyp1 hyp2; rw @covered_cequiv in ct2; repnd; rw @cover_vars_eq; insub).
assert (cover_vars b s2) as covb2 by (clear hyp1 hyp2; rw @covered_cequiv in ct2; repnd; rw @cover_vars_eq; insub).
dup wfct as wC; unfold subst in wC; apply lsubst_wf_term in wC.
assert (cover_vars_upto C (csub_filter s1 [x]) [x])
as cuC1
by (generalize (cover_vars_upto_if_cover_vars_lsubst C s1 [(x,a)]);
rw @fold_subst; simpl; sp).
assert (cover_vars_upto C (csub_filter s2 [x]) [x])
as cuC2
by (generalize (cover_vars_upto_if_cover_vars_lsubst C s2 [(x,a)]);
rw @fold_subst; simpl; sp).
generalize (simple_lsubstc_subst a x C wfct s1 pC1 wa cova1 wC cuC1);
introv e1; autodimp e1 hyp.
rw e1; clear e1.
generalize (simple_lsubstc_subst a x C wfct s2 pC2 wa cova2 wC cuC2);
introv e2; autodimp e2 hyp.
rw e2; clear e2.
generalize (hyp2 s1 s2 eqh sim); intro h2; exrepnd; proof_irr; GC.
lsubst_tac.
rw @member_eq in h1.
rw <- @member_cequiv_iff in h1.
generalize (similarity_hyps_functionality_trans lib s1 s2 H sim eqh); intro hf2.
generalize (similarity_sym lib H s1 s2 (eqh s2 sim) sim); intro sim2.
apply similarity_refl in sim2.
generalize (hyp2 s2 s2 hf2 sim2); intro h3; exrepnd; proof_irr; GC.
lsubst_tac.
rw @member_eq in h3.
rw <- @member_cequiv_iff in h3.
clear hyp2.
spcast.
generalize (hyp1 s1 s2 eqh sim); clear hyp1; intro hyp1; exrepnd; proof_irr; GC.
generalize (simple_lsubstc_subst b x C wT1 s1 pC4 wb covb1 wC cuC1);
introv e3; autodimp e3 hyp.
rw e3 in hyp0; rw e3 in hyp1; clear e3.
generalize (simple_lsubstc_subst b x C wT1 s2 pC5 wb covb2 wC cuC2);
introv e4; autodimp e4 hyp.
rw e4 in hyp0; clear e4.
dands.
(* we prove the tequality part *)
apply tequality_respects_cequivc_left
with (T1 := substc (lsubstc b wb s1 covb1) x
(lsubstc_vars C wC (csub_filter s1 [x]) [x] cuC1));
try (complete (apply cequivc_sym; eauto with cequivc)).
apply tequality_respects_cequivc_right
with (T2 := substc (lsubstc b wb s2 covb2) x
(lsubstc_vars C wC (csub_filter s2 [x]) [x] cuC2));
auto;
try (complete (apply cequivc_sym; eauto with cequivc)).
(* we prove the equality part *)
apply cequivc_preserving_equality
with (A := substc (lsubstc b wb s1 covb1) x
(lsubstc_vars C wC (csub_filter s1 [x]) [x] cuC1));
auto;
try (complete (apply cequivc_sym; eauto with cequivc)).
Qed.
(* begin hide *)
(* end hide *)
(**
The following rule states that we can always replace an [a] for a
[b] in an hypothesis of a sequent if [a] and [b] are computationally
equivalent:
<<
H, z : T[a], J |- C ext t
By cequivSubstHyp
H, z : T[b], J |- C ext t
H, z : T[a], J |- a ~ b
>>
*)
Definition rule_cequiv_subst_hyp {o}
(H J : @barehypotheses o)
(x z : NVar)
(C T a b t : NTerm) :=
mk_rule
(mk_baresequent (snoc H (mk_hyp z (subst T x a)) ++ J) (mk_concl C t))
[ mk_baresequent (snoc H (mk_hyp z (subst T x b)) ++ J) (mk_concl C t),
mk_baresequent (snoc H (mk_hyp z (subst T x a)) ++ J) (mk_conclax (mk_cequiv a b))
]
[].
Lemma rule_cequiv_subst_hyp_true {o} :
forall lib (H J : @barehypotheses o)
(x z : NVar)
(C T a b t : NTerm)
(bc1 : disjoint (free_vars a) (bound_vars T))
(bc2 : disjoint (free_vars b) (bound_vars T)),
rule_true lib (rule_cequiv_subst_hyp H J x z C T a b t).
Proof.
intros.
unfold rule_cequiv_subst_hyp, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
clear cargs.
destseq; allsimpl.
dLin_hyp.
destruct Hyp as [wf1 hyp1].
destruct Hyp0 as [wf2 hyp2].
unfold closed_extract; simpl.
assert (covered t (nh_vars_hyps (snoc H (mk_hyp z (subst T x a)) ++ J)))
as cov by (clear hyp1 hyp2; dwfseq; intros; discover; sp).
exists cov.
(* We prove some simple facts on our sequents *)
assert (!LIn z (vars_hyps H)
# !LIn z (vars_hyps J)
# disjoint (vars_hyps H) (vars_hyps J)) as vhyps.
clear hyp1 hyp2.
dwfseq.
sp.
destruct vhyps as [ nizH vhyps].
destruct vhyps as [ nizJ disjHJ ].
(* done with proving these simple facts *)
vr_seq_true.
vr_seq_true in hyp1.
vr_seq_true in hyp2.
destruct wf1 as [ws1 cl1].
destruct cl1 as [ct1 ce1].
destruct ws1 as [wh1 wc1].
destruct wc1 as [wT1 we1].
destruct wf2 as [ws2 cl2].
destruct cl2 as [ct2 ce2].
destruct ws2 as [wh2 wc2].
destruct wc2 as [wT2 we2].
allunfold @closed_type; allunfold @closed_extract; allsimpl.
dup wT2 as w.
rw <- @wf_cequiv_iff in w; destruct w as [wa wb].
assert (wf_term T)
as wT
by (clear hyp1 hyp2;
allapply @vswf_hypotheses_nil_implies;
rw @wf_hypotheses_app in wh1; repnd;
rw @wf_hypotheses_snoc in wh0; repnd; allsimpl;
allrw @isprog_vars_eq; repnd;
allrw @nt_wf_eq;
allapply @lsubst_wf_term; auto).
(* first we check whether or not x is in the free variables of T
* because to know that a and b only depend on H, we first have to
* know that x is in T. We don't get that a and b only depend on
* H from hyp2 because hyp2 can use the other hypotheses too. *)
generalize (in_deq NVar deq_nvar x (free_vars T)); introv i.
destruct i as [i | i].
(* First, we assume that x is in the free variables of T.
* We can now prove that a and b depend on H only. *)
assert (covered a (vars_hyps H))
as cvah
by (clear hyp1 hyp2;
allapply @vswf_hypotheses_nil_implies;
rw @wf_hypotheses_app in wh2; repnd;
rw @wf_hypotheses_snoc in wh0; repnd; allsimpl;
allrw @isprog_vars_eq; repnd;
unfold covered;
generalize (eqvars_free_vars_disjoint T [(x,a)]);
introv e; rw @fold_subst in e; simpl in e;
apply subvars_eqvars with (s2 := vars_hyps H) in e; auto;
rw subvars_prop in e;
rw subvars_prop; introv j;
revert e; boolvar; try (complete sp); simpl; intro e;
apply e; rw in_app_iff; rw app_nil_r; sp).
assert (covered b (vars_hyps H))
as cvbh
by (clear hyp1 hyp2;
allapply @vswf_hypotheses_nil_implies;
rw @wf_hypotheses_app in wh1; repnd;
rw @wf_hypotheses_snoc in wh0; repnd; allsimpl;
allrw @isprog_vars_eq; repnd;
unfold covered;
generalize (eqvars_free_vars_disjoint T [(x,b)]);
introv e; rw @fold_subst in e; simpl in e;
apply subvars_eqvars with (s2 := vars_hyps H) in e; auto;
rw subvars_prop in e;
rw subvars_prop; introv j;
revert e; boolvar; try (complete sp); simpl; intro e;
apply e; rw in_app_iff; rw app_nil_r; sp).
assert (covered T (snoc (vars_hyps H) x))
as covT
by (clear hyp1 hyp2;
allapply @vswf_hypotheses_nil_implies;
rw @wf_hypotheses_app in wh1; repnd;
rw @wf_hypotheses_snoc in wh0; repnd; allsimpl;
allrw @isprog_vars_eq; repnd;
unfold covered;
generalize (eqvars_free_vars_disjoint T [(x,b)]);
introv e; rw @fold_subst in e; simpl in e;
apply subvars_eqvars with (s2 := vars_hyps H) in e; auto;
rw subvars_prop in e;
rw subvars_prop; introv j;
revert e; boolvar; try (complete sp); simpl; intro e;
rw in_snoc;
destruct (deq_nvar x0 x); subst; sp;
left; apply e; rw in_app_iff; rw app_nil_r; rw in_remove_nvars; rw in_single_iff; sp).
assert (!LIn z (free_vars a))
as niza
by (intro j; unfold covered in cvah;
rw subvars_prop in cvah; apply cvah in j; sp).
assert (!LIn z (free_vars b))
as nizb
by (intro j; unfold covered in cvbh;
rw subvars_prop in cvbh; apply cvbh in j; sp).
assert (disjoint (free_vars a) (vars_hyps J))
as daj
by (introv j k; unfold covered in cvah;
rw subvars_prop in cvah; apply cvah in j; sp;
apply disjHJ in j; sp).
assert (disjoint (free_vars b) (vars_hyps J))
as dbj
by (introv j k; unfold covered in cvbh;
rw subvars_prop in cvbh; apply cvbh in j; sp;
apply disjHJ in j; sp).
assert (subvars (free_vars (subst T x a)) (vars_hyps H))
as svaH
by (generalize (eqvars_free_vars_disjoint T [(x,a)]); intro e;
apply eqvars_sym in e;
apply subvars_eqvars with (s2 := vars_hyps H) in e; auto;
rw subvars_prop; introv; simpl;
rw in_app_iff; rw in_remove_nvars; rw in_single_iff;
boolvar; simpl; try (complete sp);
rw app_nil_r; intro j; repdors; repnd;
try (complete (unfold covered in covT; rw subvars_prop in covT;
apply covT in j1; rw in_snoc in j1; allrw; sp));
try (complete (unfold covered in cvah; rw subvars_prop in cvah;
apply cvah in j; sp))).
assert (subvars (free_vars (subst T x b)) (vars_hyps H))
as svbH
by (generalize (eqvars_free_vars_disjoint T [(x,b)]); intro e;
apply eqvars_sym in e;
apply subvars_eqvars with (s2 := vars_hyps H) in e; auto;
rw subvars_prop; introv; simpl;
rw in_app_iff; rw in_remove_nvars; rw in_single_iff;
boolvar; simpl; try (complete sp);
rw app_nil_r; intro j; repdors; repnd;
try (complete (unfold covered in covT; rw subvars_prop in covT;
apply covT in j1; rw in_snoc in j1; allrw; sp));
try (complete (unfold covered in cvbh; rw subvars_prop in cvbh;
apply cvbh in j; sp))).
assert (subvars (free_vars T) (x :: vars_hyps H))
as svTH
by (rw subvars_prop in covT; rw subvars_prop; introv j;
apply covT in j; rw in_snoc in j; simpl; sp).
generalize (hyp1 s1 s2); clear hyp1; intro hyp1.
autodimp hyp1 hyp.
(* First, we prove that the hypotheses of the first sequent are functional *)
introv sim'.
rw @similarity_app in sim'; simpl in sim'; exrepnd; subst; allrw length_snoc; cpx.
rw @similarity_snoc in sim'5; simpl in sim'5; exrepnd; subst; allrw length_snoc; cpx.
rw @eq_hyps_app.
exists (snoc s1a0 (z, t1)) s1b (snoc s2a0 (z, t2)) s2b.
allrw length_snoc; dands; try (complete sp).
assert (cover_vars (subst T x b) s2a0)
as cov2
by (apply cover_vars_change_sub with (sub1 := s1a0); sp;
allapply @similarity_dom; repnd; allrw; sp).
rw @eq_hyps_snoc; simpl.
exists s1a0 s2a0 t1 t2 w p cov2.
dands; try (complete sp).
assert (wf_term (subst T x a))
as wfsa
by (apply @lsubst_preserves_wf_term; simpl;
unfold wf_sub, sub_range_sat; simpl; sp; cpx; rw @nt_wf_eq; sp).
assert (cover_vars (subst T x a) s1a0)
as cova1 by (rw @cover_vars_eq; allapply @similarity_dom; repnd; allrw; sp).
dup eqh as hf.
apply hyps_functionality_init_seg
with (s3 := s2b) in eqh; auto.
apply @hyps_functionality_init_seg_snoc2
with (t' := t2) (w := wfsa) (c := cova1) in eqh.
apply eqh in sim'6; auto.
generalize (hyp2 (snoc s1a0 (z,t1) ++ s1b) s2 hf sim); clear hyp2; intro hyp2; exrepnd.
lsubst_tac.
rw @member_eq in hyp1.
rw <- @member_cequiv_iff in hyp1.
spcast.
assert (cover_vars_upto T (csub_filter s1a0 [x]) [x])
as covT1
by (unfold cover_vars_upto; unfold covered in covT;
rw @dom_csub_csub_filter;
rw subvars_app_remove_nvars_r; simpl;
allapply @similarity_dom; repnd; allrw; sp).
generalize (simple_lsubstc_subst b x T w s1a0 p wb c6 wT covT1);
introv e; autodimp e hyp.
rw e in sim'2; clear e.
generalize (simple_lsubstc_subst a x T wfsa s1a0 cova1 wa c4 wT covT1);
introv e; autodimp e hyp.
rw e; clear e.
apply cequivc_preserving_equality
with (A := substc (lsubstc b wb s1a0 c6) x
(lsubstc_vars T wT (csub_filter s1a0 [x]) [x] covT1));
auto;
try (complete (apply cequivc_sym; eauto with cequivc)).
(* now we prove the tequality of T[x\b] *)
assert (wf_term (subst T x a))
as wfsa
by (apply @lsubst_preserves_wf_term; sp;
unfold wf_sub, sub_range_sat; simpl; sp; cpx; rw @nt_wf_eq; sp).
assert (cover_vars (subst T x a) s1a0)
as covsa1 by (rw @cover_vars_eq; allapply @similarity_dom; repnd; allrw; sp).
generalize (eqh (snoc s2a0 (z,t1) ++ s1b)); intro eqhy.
autodimp eqhy hyp.
rw @similarity_app; simpl.
exists (snoc s1a0 (z, t1)) s1b (snoc s2a0 (z, t1)) s1b; allrw length_snoc; sp.
rw @similarity_snoc; simpl.
exists s1a0 s2a0 t1 t1 wfsa covsa1; sp.
rw @similarity_app in sim; simpl in sim; exrepnd.
apply app_split in sim0; allrw length_snoc; repnd; subst;
try (complete (allapply @similarity_dom; repnd; allrw; sp)).
rw @similarity_snoc in sim5; simpl in sim5; exrepnd; cpx; proof_irr.
apply equality_refl in sim2; sp.
apply @similarity_refl in sim'1; sp.
rw @eq_hyps_app in eqhy; simpl in eqhy; exrepnd.
apply app_split in eqhy0; allrw length_snoc; repnd; subst; cpx;
try (complete (allapply @similarity_dom; repnd; allrw; sp)).
apply app_split in eqhy2; allrw length_snoc; repnd; subst; cpx;
try (complete (allapply @similarity_dom; repnd; allrw; sp)).
rw @eq_hyps_snoc in eqhy5; simpl in eqhy5; exrepnd; cpx.
(* now we prove the tequality from eqhy0 *)
generalize (hyp2 (snoc s1a (z,t0) ++ s2b0)
(snoc s2a (z,t0) ++ s2b0)
eqh); clear hyp2; intro hyp2.
(* before using hyp2 we have to prove a few things *)
autodimp hyp2 hyp.
rw @similarity_app; simpl.
exists (snoc s1a (z,t0)) s2b0 (snoc s2a (z,t0)) s2b0; allrw length_snoc; sp.
rw @similarity_snoc; simpl.
exists s1a s2a t0 t0 w0 p1; sp.
rw @similarity_app in sim; simpl in sim; exrepnd.
apply app_split in sim0; allrw length_snoc; repnd; subst;
try (complete (allapply @similarity_dom; repnd; allrw; sp)).
rw @similarity_snoc in sim5; simpl in sim5; exrepnd; cpx; proof_irr.
apply equality_refl in sim2; sp.
apply @similarity_refl in sim'1; sp.
(* now we start using hyp2 *)
exrepnd.
lsubst_tac.
rw @tequality_mkc_cequiv in hyp0.
rw @member_eq in hyp1.
rw <- @member_cequiv_iff in hyp1.
appdup hyp0 hyp1.
spcast.
assert (cover_vars_upto T (csub_filter s1a [x]) [x])
as cvuT1
by (unfold cover_vars_upto; unfold covered in covT;
rw @dom_csub_csub_filter;
rw subvars_app_remove_nvars_r; simpl;
allapply @similarity_dom; repnd; allrw; sp).
assert (cover_vars_upto T (csub_filter s2a [x]) [x])
as cvuT2
by (unfold cover_vars_upto; unfold covered in covT;
rw @dom_csub_csub_filter;
rw subvars_app_remove_nvars_r; simpl;
allapply @similarity_dom; repnd; allrw; sp).
generalize (simple_lsubstc_subst b x T w s1a p wb c6 wT cvuT1);
intro e; autodimp e hyp.
rw e; clear e.
generalize (simple_lsubstc_subst b x T w s2a cov2 wb c10 wT cvuT2);
intro e; autodimp e hyp.
rw e; clear e.
generalize (simple_lsubstc_subst a x T w0 s1a p1 wa c4 wT cvuT1);
intro e; autodimp e hyp.
rw e in eqhy0; clear e.
generalize (simple_lsubstc_subst a x T w0 s2a p2 wa c8 wT cvuT2);
intro e; autodimp e hyp.
rw e in eqhy0; clear e.
apply tequality_respects_cequivc_left
with (T1 := substc (lsubstc a wa s1a c4) x
(lsubstc_vars T wT (csub_filter s1a [x]) [x] cvuT1));
try (complete (eauto with cequivc)).
apply tequality_respects_cequivc_right
with (T2 := substc (lsubstc a wa s2a c8) x
(lsubstc_vars T wT (csub_filter s2a [x]) [x] cvuT2));
auto;
try (complete (eauto with cequivc)).
(* Now we prove the sub_eq_hyps *)
assert (wf_term (subst T x a))
as wfsa
by (apply @lsubst_preserves_wf_term; sp;
unfold wf_sub, sub_range_sat; simpl; sp; cpx; rw @nt_wf_eq; sp).
assert (cover_vars (subst T x a) s1a0)
as covsa1 by (rw @cover_vars_eq; allapply @similarity_dom; repnd; allrw; sp).
generalize (hyp2 (snoc s1a0 (z,t1) ++ s1b)
(snoc s2a0 (z,t1) ++ s1b)
eqh); clear hyp2; intro hyp2.
(* before using hyp2 we have to prove a few things *)
autodimp hyp2 hyp.
rw @similarity_app; simpl.
exists (snoc s1a0 (z,t1)) s1b (snoc s2a0 (z,t1)) s1b; allrw length_snoc; sp.
rw @similarity_snoc; simpl.
exists s1a0 s2a0 t1 t1 wfsa covsa1; sp.
rw @similarity_app in sim; simpl in sim; exrepnd.
apply app_split in sim0; allrw length_snoc; repnd; subst;
try (complete (allapply @similarity_dom; repnd; allrw; sp)).
rw @similarity_snoc in sim5; simpl in sim5; exrepnd; cpx; proof_irr.
apply equality_refl in sim2; sp.
apply @similarity_refl in sim'1; sp.
(* now we start using hyp2 *)
exrepnd.
lsubst_tac.
rw @tequality_mkc_cequiv in hyp0.
rw @member_eq in hyp1.
rw <- @member_cequiv_iff in hyp1.
appdup hyp0 hyp1.
spcast.
generalize (eqh (snoc s2a0 (z,t2) ++ s2b)); intro eqhy.
autodimp eqhy hyp.
rw @similarity_app; simpl.
exists (snoc s1a0 (z,t1)) s1b (snoc s2a0 (z,t2)) s2b; allrw length_snoc; sp.
rw @similarity_snoc; simpl.
exists s1a0 s2a0 t1 t2 wfsa covsa1; sp.
assert (cover_vars_upto T (csub_filter s1a0 [x]) [x])
as cvuT1
by (unfold cover_vars_upto; unfold covered in covT;
rw @dom_csub_csub_filter;
rw subvars_app_remove_nvars_r; simpl;
allapply @similarity_dom; repnd; allrw; sp).
generalize (simple_lsubstc_subst b x T w s1a0 p wb c6 wT cvuT1);
intro e; autodimp e hyp.
rw e in sim'2; clear e.
generalize (simple_lsubstc_subst a x T wfsa s1a0 covsa1 wa c4 wT cvuT1);
intro e; autodimp e hyp.
rw e; clear e.
apply cequivc_preserving_equality
with (A := substc (lsubstc b wb s1a0 c6) x
(lsubstc_vars T wT (csub_filter s1a0 [x]) [x] cvuT1));
auto;
try (complete (apply cequivc_sym; eauto with cequivc)).
rw @eq_hyps_app in eqhy; exrepnd.
apply app_split in eqhy0; allrw length_snoc; repnd; subst; cpx;
try (complete (allapply @similarity_dom; repnd; allrw; sp)).
apply app_split in eqhy2; allrw length_snoc; repnd; subst; cpx;
try (complete (allapply @similarity_dom; repnd; allrw; sp)).
(* We're done proving the hyps_functionality part of hyp1.
* We now prove the similarity part of hyp1 *)
autodimp hyp1 hyp.
rw @similarity_app in sim; exrepnd; subst; cpx.
rw @similarity_snoc in sim5; simpl in sim5; exrepnd; subst; cpx.
generalize (hyp2 (snoc s1a0 (z,t1) ++ s1b)
(snoc s2a0 (z,t1) ++ s1b)
eqh); clear hyp2; intro hyp2.
(* before using hyp2 we have to prove a few things *)
autodimp hyp2 hyp.
rw @similarity_app; simpl.
exists (snoc s1a0 (z,t1)) s1b (snoc s2a0 (z,t1)) s1b; allrw length_snoc; sp.
rw @similarity_snoc; simpl.
exists s1a0 s2a0 t1 t1 w p; sp.
apply equality_refl in sim2; sp.
apply @similarity_refl in sim1; sp.
(* now we start using hyp2 *)
exrepnd.
lsubst_tac.
rw @tequality_mkc_cequiv in hyp0.
rw @member_eq in hyp1.
rw <- @member_cequiv_iff in hyp1.
appdup hyp0 hyp1.
spcast.
assert (wf_term (subst T x b))
as wfsb
by (apply @lsubst_preserves_wf_term; sp;
unfold wf_sub, sub_range_sat; simpl; sp; cpx; rw @nt_wf_eq; sp).
assert (cover_vars (subst T x b) s1a0)
as covb1 by (rw @cover_vars_eq; allapply @similarity_dom; repnd; allrw; sp).
rw @similarity_app.
exists (snoc s1a0 (z, t1)) s1b (snoc s2a0 (z, t2)) s2b; allrw length_snoc; sp.
rw @similarity_snoc; simpl.
exists s1a0 s2a0 t1 t2 wfsb covb1; sp.
assert (cover_vars_upto T (csub_filter s1a0 [x]) [x])
as cvuT1
by (unfold cover_vars_upto; unfold covered in covT;
rw @dom_csub_csub_filter;
rw subvars_app_remove_nvars_r; simpl;
allapply @similarity_dom; repnd; allrw; sp).
generalize (simple_lsubstc_subst b x T wfsb s1a0 covb1 wb c6 wT cvuT1);
intro e; autodimp e hyp.
rw e; clear e.
generalize (simple_lsubstc_subst a x T w s1a0 p wa c4 wT cvuT1);
intro e; autodimp e hyp.
rw e in sim2; clear e.
apply cequivc_preserving_equality
with (A := substc (lsubstc a wa s1a0 c4) x
(lsubstc_vars T wT (csub_filter s1a0 [x]) [x] cvuT1));
auto;
try (complete (eauto with cequivc)).
(* now we use hyp1 *)
exrepnd; proof_irr; GC; sp.
(* now we're done to the case where x is not in the free_vars of t *)
assert (subst T x a = T)
as e1 by (apply @lsubst_trivial3; introv j; rw in_single_iff in j; cpx).
allrw e1; clear e1.
assert (subst T x b = T)
as e2 by (apply @lsubst_trivial3; introv j; rw in_single_iff in j; cpx).
allrw e2; clear e2.
generalize (hyp1 s1 s2 eqh sim); clear hyp1; intro hyp1; exrepnd; proof_irr; sp.
Qed.
(* begin hide *)
(* end hide *) |
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: PLL.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module PLL (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.locked (),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "FAST",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_enable0 = "PORT_UNUSED",
altpll_component.port_enable1 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.port_extclkena0 = "PORT_UNUSED",
altpll_component.port_extclkena1 = "PORT_UNUSED",
altpll_component.port_extclkena2 = "PORT_UNUSED",
altpll_component.port_extclkena3 = "PORT_UNUSED",
altpll_component.port_sclkout0 = "PORT_UNUSED",
altpll_component.port_sclkout1 = "PORT_UNUSED";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "FAST"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_enable0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_enable1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_sclkout0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_sclkout1 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.ppf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_wave*.jpg FALSE FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DFSBP_PP_BLACKBOX_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSBP_PP_BLACKBOX_V
|
//
// Copyright (C) 2009-2012 Chris McClelland
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module
fifo_wrapper(
// Clock and depth
input wire clk_in,
output wire[7:0] depth_out,
// Data is clocked into the FIFO on each clock edge where both valid & ready are high
input wire[7:0] inputData_in,
input wire inputValid_in,
output wire inputReady_out,
// Data is clocked out of the FIFO on each clock edge where both valid & ready are high
output wire[7:0] outputData_out,
output wire outputValid_out,
input wire outputReady_in
);
wire inputFull;
wire outputEmpty;
// Invert "full/empty" signals to give "ready/valid" signals
assign inputReady_out = !inputFull;
assign outputValid_out = !outputEmpty;
// The encapsulated FIFO
altera_fifo fifo(
.clock(clk_in),
.usedw(depth_out),
// Production end
.data(inputData_in),
.wrreq(inputValid_in),
.full(inputFull),
// Consumption end
.q(outputData_out),
.empty(outputEmpty),
.rdreq(outputReady_in)
);
endmodule
|
module tb_fifo9togmii();
/* 125MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #8 sys_clk = ~sys_clk;
/* 33MHz PCI clock */
reg pci_clk;
initial pci_clk = 1'b0;
always #30 pci_clk = ~pci_clk;
/* 62.5MHz CPCI clock */
reg cpci_clk;
initial cpci_clk = 1'b0;
always #16 cpci_clk = ~cpci_clk;
/* 125MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #8 phy_rx_clk = ~phy_rx_clk;
/* 125MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #8 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
reg [8:0] dout;
reg empty;
wire rd_en;
wire rd_clk;
wire gmii_tx_en;
wire [7:0] gmii_txd;
fifo9togmii fifo9togmii_tb (
.sys_rst(sys_rst),
.dout(dout),
.empty(empty),
.rd_en(rd_en),
.rd_clk(rd_clk),
.gmii_tx_clk(phy_tx_clk),
.gmii_tx_en(gmii_tx_en),
.gmii_txd(gmii_txd)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
always @(posedge rd_clk) begin
if (gmii_tx_en == 1'b1)
$display("gmii_tx_out: %x", gmii_txd);
end
reg [11:0] counter;
reg [8:0] rom [0:4091];
always #1
{empty,dout} <= rom[ counter ];
always @(posedge phy_tx_clk) begin
if (rd_en == 1'b1)
counter <= counter + 1;
end
initial begin
$dumpfile("./test.vcd");
$dumpvars(0, tb_fifo9togmii);
$readmemh("./fifo9.hex", rom);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
counter = 0;
waitclock;
waitclock;
sys_rst = 1'b0;
waitclock;
#30000;
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_LP_V
`define SKY130_FD_SC_LP__AND4_LP_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4_lp (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4_lp (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_LP_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mc_phy_wrapper.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Oct 10 2010
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Wrapper file that encompasses the MC_PHY module
// instantiation and handles the vector remapping between
// the MC_PHY ports and the user's DDR3 ports. Vector
// remapping affects DDR3 control, address, and DQ/DQS/DM.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mc_phy_wrapper #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter tCK = 2500, // ps
parameter IODELAY_GRP = "IODELAY_MIG",
parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter BANK_WIDTH = 3, // # of bank address
parameter CKE_WIDTH = 1, // # of clock enable outputs
parameter CS_WIDTH = 1, // # of chip select
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of data mask
parameter DQ_WIDTH = 16, // # of data bits
parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of strobe pairs
parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3)
parameter RANKS = 4, // # of ranks
parameter REG_CTRL = "OFF", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // # of row/column address
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// Parameters calculated outside of this block
parameter HIGHEST_BANK = 3, // Highest I/O bank index
parameter HIGHEST_LANE = 12, // Highest byte lane index
// ** Pin mapping parameters
// Parameters for mapping between hard PHY and physical DDR3 signals
// There are 2 classes of parameters:
// - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of
// 8-bit elements. Each element indicates the bank and byte lane
// location of that particular signal. The bit lane in this case
// doesn't need to be specified, either because there's only one
// pin pair in each byte lane that the DQS or CK pair can be
// located at, or in the case of CKE_ODT_BYTE_MAP, only the byte
// lane needs to be specified in order to determine which byte
// lane generates the RCLK (Note that CKE, and ODT must be located
// in the same bank, thus only one element in CKE_ODT_BYTE_MAP)
// [7:4] = bank # (0-4)
// [3:0] = byte lane # (0-3)
// - All other MAP parameters: These consist of 12-bit elements. Each
// element indicates the bank, byte lane, and bit lane location of
// that particular signal:
// [11:8] = bank # (0-4)
// [7:4] = byte lane # (0-3)
// [3:0] = bit lane # (0-11)
// Note that not all elements in all parameters will be used - it
// depends on the actual widths of the DDR3 buses. The parameters are
// structured to support a maximum of:
// - DQS groups: 18
// - data mask bits: 18
// In addition, the default parameter size of some of the parameters will
// support a certain number of bits, however, this can be expanded at
// compile time by expanding the width of the vector passed into this
// parameter
// - chip selects: 10
// - bank bits: 3
// - address bits: 16
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
// DATAx_MAP parameter is used for byte lane X in the design
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
// MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9]
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000
)
(
input rst,
input clk,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input idelayctrl_refclk,
input phy_cmd_wr_en,
input phy_data_wr_en,
input [31:0] phy_ctl_wd,
input phy_ctl_wr,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
output if_empty,
output phy_ctl_full,
output phy_cmd_full,
output phy_data_full,
output [1:0] ddr_clk,
output phy_mc_go,
input phy_write_calib,
input phy_read_calib,
input calib_in_common,
// input [DQS_CNT_WIDTH:0] byte_sel_cnt,
input [5:0] calib_sel,
input [HIGHEST_BANK-1:0] calib_zero_inputs,
input po_fine_enable,
input po_coarse_enable,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input [5:0] pi_counter_load_val,
output pi_phase_locked,
output pi_phase_locked_all,
output pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_out_of_range,
// From/to calibration logic/soft PHY
input phy_init_data_sel,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank,
input [nCK_PER_CLK-1:0] mux_cas_n,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n,
input [nCK_PER_CLK-1:0] mux_ras_n,
input [nCK_PER_CLK-1:0] mux_we_n,
input [nCK_PER_CLK-1:0] parity_in,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Memory I/F
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [RANKS-1:0] ddr_odt,
output ddr_parity,
output ddr_ras_n,
output ddr_we_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n
);
// Enable low power mode for input buffer
localparam IBUF_LOW_PWR
= (IBUF_LPWR_MODE == "OFF") ? "FALSE" :
((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL");
// Ratio of data to strobe
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
// number of data phases per internal clock
localparam PHASE_PER_CLK = 2*nCK_PER_CLK;
// used to determine routing to OUT_FIFO for control/address for 2:1
// vs. 4:1 memory:internal clock ratio modes
localparam PHASE_DIV = 4 / nCK_PER_CLK;
// Create an aggregate parameters for data mapping to reduce # of generate
// statements required in remapping code. Need to account for the case
// when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP
// parameter will have fewer than 8 elements used
localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0],
DATA16_MAP[12*DQ_PER_DQS-1:0],
DATA15_MAP[12*DQ_PER_DQS-1:0],
DATA14_MAP[12*DQ_PER_DQS-1:0],
DATA13_MAP[12*DQ_PER_DQS-1:0],
DATA12_MAP[12*DQ_PER_DQS-1:0],
DATA11_MAP[12*DQ_PER_DQS-1:0],
DATA10_MAP[12*DQ_PER_DQS-1:0],
DATA9_MAP[12*DQ_PER_DQS-1:0],
DATA8_MAP[12*DQ_PER_DQS-1:0],
DATA7_MAP[12*DQ_PER_DQS-1:0],
DATA6_MAP[12*DQ_PER_DQS-1:0],
DATA5_MAP[12*DQ_PER_DQS-1:0],
DATA4_MAP[12*DQ_PER_DQS-1:0],
DATA3_MAP[12*DQ_PER_DQS-1:0],
DATA2_MAP[12*DQ_PER_DQS-1:0],
DATA1_MAP[12*DQ_PER_DQS-1:0],
DATA0_MAP[12*DQ_PER_DQS-1:0]};
// Same deal, but for data mask mapping
localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP};
// Temporary parameters to determine which bank is outputting the CK/CK#
// Eventually there will be support for multiple CK/CK# output
localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]);
// Temporary method to force MC_PHY to generate ODDR associated with
// CK/CK# output only for a single byte lane in the design. All banks
// that won't be generating the CK/CK# will have "UNUSED" as their
// PHY_GENERATE_DDR_CK parameter
localparam TMP_PHY_0_GENERATE_DDR_CK
= (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" :
((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
localparam TMP_PHY_1_GENERATE_DDR_CK
= (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" :
((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
localparam TMP_PHY_2_GENERATE_DDR_CK
= (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" :
((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
// Function to generate MC_PHY parameter from data mask map parameter
function [143:0] calc_phy_bitlanes_outonly;
input [215:0] data_mask_in;
integer z;
begin
calc_phy_bitlanes_outonly = 'b0;
for (z = 0; z < DM_WIDTH; z = z + 1)
calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] +
12*data_mask_in[(12*z+4)+:2] +
data_mask_in[12*z+:4]] = 1'b1;
end
endfunction
localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP);
localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0];
localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48];
localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96];
// Determine which bank and byte lane generates the RCLK used to clock
// out the auxilliary (ODT, CKE) outputs
localparam CKE_ODT_RCLK_SELECT_BANK
= (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE
= (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL")));
// OCLKDELAYED tap setting calculation:
// Parameters for calculating amount of phase shifting output clock to
// achieve 90 degree offset between DQS and DQ on writes
localparam PO_OCLKDELAY_INV = "TRUE";
localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 2500 ? "DIV2" : "NONE";
localparam real FREQ_REF_MHZ
= 1.0/((tCK/(PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1) /
1000.0) / 1000) ;
localparam real MC_OCLK_DELAY2 = FREQ_REF_MHZ/10000.0 + 0.4548;
localparam real MC_OCLK_DELAY3
= ((0.25 * (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1)) -
MC_OCLK_DELAY2 - (PO_OCLKDELAY_INV == "TRUE" ? 1 : 0) * 0.5) ;
localparam real MC_OCLK_DELAY4
= (MC_OCLK_DELAY3 + (MC_OCLK_DELAY3 < 0 )+0) * 64;
localparam real MC_OCLK_DELAY
= MC_OCLK_DELAY4 + ((tCK < 1900 ) || tCK > 3000) ;
// Value expressed as fraction of a full tCK period
localparam real SHIFT = (1 + 0.3);
// Value expressed as fraction of a full tCK period
localparam real OCLK_INTRINSIC_DELAY
= (tCK < 1000) ? 0.708 :
((tCK < 1100) ? 0.748 :
((tCK < 1300) ? 0.742 :
((tCK < 1600) ? 0.709 :
((tCK < 2500) ? 0.637 : 0.425))));
// OCLK_DELAYED due to inversion
localparam real OCLK_DELAY_INV_DELAY
= (PO_OCLKDELAY_INV == "TRUE") ? 0.5 : 0;
localparam real OCLK_DELAY_PERCENT
= (SHIFT - OCLK_INTRINSIC_DELAY - OCLK_DELAY_INV_DELAY) * 100;
localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY + 0.5;
// IDELAY value
localparam PHY_0_A_IDELAYE2_IDELAY_VALUE
= (tCK < 1000) ? 0 :
((tCK < 1330) ? 1 :
((tCK < 2300) ? 3 :
((tCK < 2500) ? 5 : 6)));
/*localparam PHY_0_A_IDELAYE2_IDELAY_VALUE
= (tCK < 1000) ? 4 :
((tCK < 1330) ? 5 :
((tCK < 2300) ? 7 :
((tCK < 2500) ? 9 : 10)));*/
// Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3?
localparam PHY_0_RD_CMD_OFFSET_0 = 10; //8
localparam PHY_0_RD_CMD_OFFSET_1 = 10; //8
localparam PHY_0_RD_CMD_OFFSET_2 = 10; //8
localparam PHY_0_RD_CMD_OFFSET_3 = 10; //8
localparam PHY_0_WR_CMD_OFFSET_0 = 10; //8
localparam PHY_0_WR_CMD_OFFSET_1 = 10; //8
localparam PHY_0_WR_CMD_OFFSET_2 = 10; //8
localparam PHY_0_WR_CMD_OFFSET_3 = 10; //8
wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out;
wire [HIGHEST_LANE-1:0] mem_dqs_in;
wire [HIGHEST_LANE-1:0] mem_dqs_out;
wire [HIGHEST_LANE-1:0] mem_dqs_ts;
wire [HIGHEST_LANE*10-1:0] mem_dq_in;
wire [HIGHEST_LANE*12-1:0] mem_dq_out;
wire [HIGHEST_LANE*12-1:0] mem_dq_ts;
wire [DQ_WIDTH-1:0] in_dq;
wire [DQS_WIDTH-1:0] in_dqs;
wire [ROW_WIDTH-1:0] out_addr;
wire [BANK_WIDTH-1:0] out_ba;
wire out_cas_n;
wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n;
wire [DM_WIDTH-1:0] out_dm;
wire [DQ_WIDTH-1:0] out_dq;
wire [DQS_WIDTH-1:0] out_dqs;
wire out_parity;
wire out_ras_n;
wire out_we_n;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire [DM_WIDTH-1:0] ts_dm;
wire [DQ_WIDTH-1:0] ts_dq;
wire [DQS_WIDTH-1:0] ts_dqs;
//***************************************************************************
// Auxiliary output steering
//***************************************************************************
// For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be
// mapped to ddr_odt and the aux_out[7:4] from one of the data banks
// will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the
// addr/ctl bank would bank would map to both ddr_odt and ddr_cke.
generate
if (RANKS == 1) begin : gen_cke_odt
assign ddr_cke = aux_out[0];
if (USE_ODT_PORT == 1) begin: gen_use_odt
assign ddr_odt = aux_out[1];
end else begin
assign ddr_odt = 1'b0;
end
end else begin: gen_2rank_cke_odt
assign ddr_cke = {aux_out[2],aux_out[0]};
if (USE_ODT_PORT == 1) begin: gen_use_odt
assign ddr_odt = {aux_out[3],aux_out[1]};
end else begin
assign ddr_odt = 2'b00;
end
end
endgenerate
//***************************************************************************
// Read data bit steering
//***************************************************************************
// Transpose elements of rd_data_map to form final read data output:
// phy_din elements are grouped according to "physical bit" - e.g.
// for nCK_PER_CLK = 4, there are 8 data phases transfered per physical
// bit per clock cycle:
// = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2,
// dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0}
// whereas rd_data is are grouped according to "phase" - e.g.
// = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0,
// dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0}
// therefore rd_data is formed by transposing phy_din - e.g.
// for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY
// bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then
// the assignments for bits of rd_data corresponding to DQ[1:0]
// would be:
// {rd_data[112], rd_data[96], rd_data[80], rd_data[64],
// rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0]
// {rd_data[113], rd_data[97], rd_data[81], rd_data[65],
// rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8]
generate
genvar i, j;
for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1
for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2
assign rd_data[DQ_WIDTH*j + i]
= phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+
80*FULL_DATA_MAP[(12*i+4)+:2] +
8*FULL_DATA_MAP[12*i+:4]) + j];
end
end
endgenerate
//***************************************************************************
// Control/address
//***************************************************************************
assign out_cas_n
= mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]];
generate
// if signal placed on bit lanes [0-9]
if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10
// Determine routing based on clock ratio mode. If running in 4:1
// mode, then all four bits from logic are used. If 2:1 mode, only
// 2-bits are provided by logic, and each bit is repeated 2x to form
// 4-bit input to IN_FIFO, e.g.
// 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]}
// 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]}
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*CAS_MAP[3:0])+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end else begin: gen_cas_ge10
// If signal is placed in bit lane [10] or [11], route to upper
// nibble of phy_dout lane [5] or [6] respectively (in this case
// phy_dout lane [5, 6] are multiplexed to take input for two
// different SDR signals - this is how bits[10,11] need to be
// provided to the OUT_FIFO
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*(CAS_MAP[3:0]-5) + 4)+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end
endgenerate
assign out_ras_n
= mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]];
generate
if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*RAS_MAP[3:0])+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end else begin: gen_ras_ge10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*(RAS_MAP[3:0]-5) + 4)+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end
endgenerate
assign out_we_n
= mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]];
generate
if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*WE_MAP[3:0])+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end else begin: gen_we_ge10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*(WE_MAP[3:0]-5) + 4)+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end
endgenerate
generate
if ((DRAM_TYPE == "DDR3") && (REG_CTRL == "ON")) begin: gen_parity_out
// Generate addr/ctrl parity output only for DDR3 registered DIMMs
assign out_parity
= mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] +
PARITY_MAP[3:0]];
if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*PARITY_MAP[3:0])+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end else begin: gen_ge10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*(PARITY_MAP[3:0]-5) + 4)+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end
end
endgenerate
//*****************************************************************
generate
genvar m, n;
//*****************************************************************
// Control/address (multi-bit) buses
//*****************************************************************
// Row/Column address
for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out
assign out_addr[m]
= mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] +
12*ADDR_MAP[(12*m+4)+:2] +
ADDR_MAP[12*m+:4]];
if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10
// For multi-bit buses, we also have to deal with transposition
// when going from the logic-side control bus to phy_dout
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*ADDR_MAP[12*m+:4] + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*(ADDR_MAP[12*m+:4]-5) + 4 + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Bank address
for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out
assign out_ba[m]
= mem_dq_out[48*BANK_MAP[(12*m+8)+:3] +
12*BANK_MAP[(12*m+4)+:2] +
BANK_MAP[12*m+:4]];
if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*BANK_MAP[12*m+:4] + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*(BANK_MAP[12*m+:4]-5) + 4 + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Chip select
for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out
assign out_cs_n[m]
= mem_dq_out[48*CS_MAP[(12*m+8)+:3] +
12*CS_MAP[(12*m+4)+:2] +
CS_MAP[12*m+:4]];
if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*CS_MAP[12*m+:4] + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*(CS_MAP[12*m+:4]-5) + 4 + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end
end
//*****************************************************************
// Data mask
//*****************************************************************
if (USE_DM_PORT == 1) begin: gen_dm_out
for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out
assign out_dm[m]
= mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
assign ts_dm[m]
= mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] +
80*FULL_MASK_MAP[(12*m+4)+:2] +
8*FULL_MASK_MAP[12*m+:4] + n]
= mux_wrdata_mask[DM_WIDTH*n + m];
end
end
end
//*****************************************************************
// Input and output DQ
//*****************************************************************
for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout
// to MC_PHY
assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] +
10*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]]
= in_dq[m];
// to I/O buffers
assign out_dq[m]
= mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
assign ts_dq[m]
= mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] +
80*FULL_DATA_MAP[(12*m+4)+:2] +
8*FULL_DATA_MAP[12*m+:4] + n]
= mux_wrdata[DQ_WIDTH*n + m];
end
end
//*****************************************************************
// Input and output DQS
//*****************************************************************
for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout
// to MC_PHY
assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]
= in_dqs[m];
// to I/O buffers
assign out_dqs[m]
= mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
assign ts_dqs[m]
= mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
end
endgenerate
//***************************************************************************
// Memory I/F output and I/O buffer instantiation
//***************************************************************************
// Note on instantiation - generally at the minimum, it's not required to
// instantiate the output buffers - they can be inferred by the synthesis
// tool, and there aren't any attributes that need to be associated with
// them. Consider as a future option to take out the OBUF instantiations
OBUF u_cas_n_obuf
(
.I (out_cas_n),
.O (ddr_cas_n)
);
OBUF u_ras_n_obuf
(
.I (out_ras_n),
.O (ddr_ras_n)
);
OBUF u_we_n_obuf
(
.I (out_we_n),
.O (ddr_we_n)
);
generate
genvar p;
for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf
OBUF u_addr_obuf
(
.I (out_addr[p]),
.O (ddr_addr[p])
);
end
for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf
OBUF u_bank_obuf
(
.I (out_ba[p]),
.O (ddr_ba[p])
);
end
for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf
OBUF u_cs_n_obuf
(
.I (out_cs_n[p]),
.O (ddr_cs_n[p])
);
end
if ((DRAM_TYPE == "DDR3") && (REG_CTRL == "ON")) begin: gen_parity_obuf
// Generate addr/ctrl parity output only for DDR3 registered DIMMs
OBUF u_parity_obuf
(
.I (out_parity),
.O (ddr_parity)
);
end else begin: gen_parity_tieoff
assign ddr_parity = 1'b0;
end
if (USE_DM_PORT == 1) begin: gen_dm_obuf
for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm
OBUFT u_dm_obuf
(
.I (out_dm[p]),
.T (ts_dm[p]),
.O (ddr_dm[p])
);
end
end else begin: gen_dm_tieoff
assign ddr_dm = 'b0;
end
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
end
end
endgenerate
//***************************************************************************
// Hard PHY instantiation
//***************************************************************************
mc_phy #
(
.PHYCTL_CMD_FIFO ("FALSE"),
.PHY_SYNC_MODE ("TRUE"),
.PHY_DISABLE_SEQ_MATCH ("FALSE"),
.PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK),
.RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE),
.DDR_CLK_SELECT_BANK (TMP_DDR_CLK_SELECT_BANK),
.PHY_0_GENERATE_DDR_CK (TMP_PHY_0_GENERATE_DDR_CK),
.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK),
.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK),
.PHY_EVENTS_DELAY (63),
.PHY_FOUR_WINDOW_CLOCKS (18),
.PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV),
.PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_RD_DURATION_0 (6),
.PHY_0_RD_DURATION_1 (6),
.PHY_0_RD_DURATION_2 (6),
.PHY_0_RD_DURATION_3 (6),
.PHY_0_WR_DURATION_0 (6),
.PHY_0_WR_DURATION_1 (6),
.PHY_0_WR_DURATION_2 (6),
.PHY_0_WR_DURATION_3 (6),
.PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PHY_0_CMD_OFFSET (10),//for CKE
.IODELAY_GRP (IODELAY_GRP)
)
u_mc_phy
(
.rst (rst),
// Don't use MC_PHY to generate DDR_RESET_N output. Instead
// generate this output outside of MC_PHY (and synchronous to CLK)
.ddr_rst_in_n (1'b1),
.phy_clk (clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
// Remove later - always same connection as phy_clk port
.mem_refclk_div4 (clk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.phy_dout (phy_dout),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_ctl_wd (phy_ctl_wd),
.phy_ctl_wr (phy_ctl_wr),
.aux_in_1 (aux_in_1),
.aux_in_2 (aux_in_2),
.cke_in (),
.if_a_empty (),
.if_empty (if_empty),
.of_ctl_a_full (phy_cmd_full),
.of_data_a_full (phy_data_full),
.of_ctl_full (),
.of_data_full (),
.idelay_ld (1'b0),
.idelay_ce (1'b0),
.input_sink (),
.phy_din (phy_din),
.phy_ctl_a_full (phy_ctl_full),
.phy_ctl_full (),
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.mem_dqs_in (mem_dqs_in),
.aux_out (aux_out),
.phy_ctl_ready (),
.rst_out (),
.ddr_clk (ddr_clk),
.rclk (),
.mcGo (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.po_fine_enable (po_fine_enable),
.po_coarse_enable (po_coarse_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (),
.po_coarse_overflow (),
.po_fine_overflow (),
.po_counter_read_val (),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (),
.pi_counter_read_val (),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (),
.pi_dqs_found_any (pi_dqs_found),
.pi_dqs_found_all (pi_dqs_found_all),
// Currently not being used. May be used in future if periodic
// reads become a requirement. This output could be used to signal
// a catastrophic failure in read capture and the need for
// re-calibration.
.pi_dqs_out_of_range (pi_dqs_out_of_range)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
`ifdef INLINE_A //verilator inline_module
`else //verilator no_inline_module
`endif
bmod bsub3 (.clk, .n(3));
bmod bsub2 (.clk, .n(2));
bmod bsub1 (.clk, .n(1));
bmod bsub0 (.clk, .n(0));
endmodule
module bmod
(input clk,
input [31:0] n);
`ifdef INLINE_B //verilator inline_module
`else //verilator no_inline_module
`endif
cmod csub (.clk, .n);
endmodule
module cmod
(input clk, input [31:0] n);
`ifdef INLINE_C //verilator inline_module
`else //verilator no_inline_module
`endif
reg [31:0] clocal;
always @ (posedge clk) clocal <= n;
dmod dsub (.clk, .n);
endmodule
module dmod (input clk, input [31:0] n);
`ifdef INLINE_D //verilator inline_module
`else //verilator no_inline_module
`endif
reg [31:0] dlocal;
always @ (posedge clk) dlocal <= n;
int cyc;
always @(posedge clk) begin
cyc <= cyc+1;
end
always @(posedge clk) begin
if (cyc>10) begin
`ifdef TEST_VERBOSE $display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal); `endif
if (csub.clocal !== n) $stop;
if (dlocal !== n) $stop;
end
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Virtual-Channel Buffers
* =======================
*
* Instantiates 'N' FIFOs in parallel, if 'push' is asserted
* data_in is sent to FIFO[pl_id].
*
* The output is determined by an external 'select' input.
*
* if 'pop' is asserted by the end of the clock cycle, the
* FIFO that was read (indicated by 'select') recieves a
* pop command.
*
* - flags[] provides access to all FIFO status flags.
* - output_port[] provides access to 'output_port' field of flits at head of FIFOs
*
* Assumptions:
* - 'pl_id' is binary encoded (select is one-hot) //and 'select' are binary encoded.
*
*/
module LAG_pl_buffers (push, pop, data_in,
data_out, flags,
clk, rst_n);
// length of PL FIFOs
parameter size = 3;
// number of physical channels
parameter n = 4;
input [n-1:0] push;
input [n-1:0] pop;
input fifo_elements_t data_in [n-1:0];
output fifo_elements_t data_out [n-1:0];
output fifov_flags_t flags [n-1:0];
input clk, rst_n;
genvar i;
generate
for (i=0; i<n; i++) begin:plbufs
// **********************************
// SINGLE FIFO holds complete flit
// **********************************
LAG_fifo_v #(.size(size)
) pl_fifo
(.push(push[i]),
.pop(pop[i]),
.data_in(data_in[i]),
.data_out(data_out[i]),
.flags(flags[i]),
.clk, .rst_n);
end
endgenerate
endmodule
|
/*
*
* Copyright (c) 2013 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
module ff_sub (
input clk,
input reset,
input [255:0] rx_a,
input [255:0] rx_b,
input [255:0] rx_p,
output reg tx_done = 1'b0,
output reg [255:0] tx_a = 256'd0
);
reg carry;
always @ (posedge clk)
begin
if (!tx_done)
begin
if (carry)
tx_a <= tx_a + rx_p;
tx_done <= 1'b1;
end
if (reset)
begin
{carry, tx_a} <= rx_a - rx_b;
tx_done <= 1'b0;
end
end
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream statistics counter
*/
module axis_stat_counter #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter TAG_ENABLE = 1,
parameter TAG_WIDTH = 16,
parameter TICK_COUNT_ENABLE = 1,
parameter TICK_COUNT_WIDTH = 32,
parameter BYTE_COUNT_ENABLE = 1,
parameter BYTE_COUNT_WIDTH = 32,
parameter FRAME_COUNT_ENABLE = 1,
parameter FRAME_COUNT_WIDTH = 32
)
(
input wire clk,
input wire rst,
/*
* AXI monitor
*/
input wire [KEEP_WIDTH-1:0] monitor_axis_tkeep,
input wire monitor_axis_tvalid,
input wire monitor_axis_tready,
input wire monitor_axis_tlast,
/*
* AXI status data output
*/
output wire [7:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [TAG_WIDTH-1:0] tag,
input wire trigger,
/*
* Status
*/
output wire busy
);
localparam TAG_BYTE_WIDTH = (TAG_WIDTH + 7) / 8;
localparam TICK_COUNT_BYTE_WIDTH = (TICK_COUNT_WIDTH + 7) / 8;
localparam BYTE_COUNT_BYTE_WIDTH = (BYTE_COUNT_WIDTH + 7) / 8;
localparam FRAME_COUNT_BYTE_WIDTH = (FRAME_COUNT_WIDTH + 7) / 8;
localparam TOTAL_LENGTH = TAG_BYTE_WIDTH + TICK_COUNT_BYTE_WIDTH + BYTE_COUNT_BYTE_WIDTH + FRAME_COUNT_BYTE_WIDTH;
// state register
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_OUTPUT_DATA = 2'd1;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [TICK_COUNT_WIDTH-1:0] tick_count_reg = 0, tick_count_next;
reg [BYTE_COUNT_WIDTH-1:0] byte_count_reg = 0, byte_count_next;
reg [FRAME_COUNT_WIDTH-1:0] frame_count_reg = 0, frame_count_next;
reg frame_reg = 0, frame_next;
reg store_output;
reg [$clog2(TOTAL_LENGTH)-1:0] frame_ptr_reg = 0, frame_ptr_next;
reg [TICK_COUNT_WIDTH-1:0] tick_count_output_reg = 0;
reg [BYTE_COUNT_WIDTH-1:0] byte_count_output_reg = 0;
reg [FRAME_COUNT_WIDTH-1:0] frame_count_output_reg = 0;
reg busy_reg = 0;
// internal datapath
reg [7:0] output_axis_tdata_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
assign busy = busy_reg;
integer offset, i, bit_cnt;
always @* begin
state_next = 2'bz;
tick_count_next = tick_count_reg;
byte_count_next = byte_count_reg;
frame_count_next = frame_count_reg;
frame_next = frame_reg;
output_axis_tdata_int = 0;
output_axis_tvalid_int = 0;
output_axis_tlast_int = 0;
output_axis_tuser_int = 0;
store_output = 0;
frame_ptr_next = frame_ptr_reg;
// data readout
case (state_reg)
STATE_IDLE: begin
if (trigger) begin
store_output = 1;
tick_count_next = 0;
byte_count_next = 0;
frame_count_next = 0;
frame_ptr_next = 0;
if (output_axis_tready_int) begin
frame_ptr_next = 1;
if (TAG_ENABLE) begin
output_axis_tdata_int = tag[(TAG_BYTE_WIDTH-1)*8 +: 8];
end else if (TICK_COUNT_ENABLE) begin
output_axis_tdata_int = tick_count_reg[(TICK_COUNT_BYTE_WIDTH-1)*8 +: 8];
end else if (BYTE_COUNT_ENABLE) begin
output_axis_tdata_int = byte_count_reg[(BYTE_COUNT_BYTE_WIDTH-1)*8 +: 8];
end else if (FRAME_COUNT_ENABLE) begin
output_axis_tdata_int = frame_count_reg[(FRAME_COUNT_BYTE_WIDTH-1)*8 +: 8];
end
output_axis_tvalid_int = 1;
end
state_next = STATE_OUTPUT_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_OUTPUT_DATA: begin
if (output_axis_tready_int) begin
state_next = STATE_OUTPUT_DATA;
frame_ptr_next = frame_ptr_reg + 1;
output_axis_tvalid_int = 1;
offset = 0;
if (TAG_ENABLE) begin
for (i = TAG_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
if (frame_ptr_reg == offset) begin
output_axis_tdata_int = tag[i*8 +: 8];
end
offset = offset + 1;
end
end
if (TICK_COUNT_ENABLE) begin
for (i = TICK_COUNT_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
if (frame_ptr_reg == offset) begin
output_axis_tdata_int = tick_count_output_reg[i*8 +: 8];
end
offset = offset + 1;
end
end
if (BYTE_COUNT_ENABLE) begin
for (i = BYTE_COUNT_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
if (frame_ptr_reg == offset) begin
output_axis_tdata_int = byte_count_output_reg[i*8 +: 8];
end
offset = offset + 1;
end
end
if (FRAME_COUNT_ENABLE) begin
for (i = FRAME_COUNT_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
if (frame_ptr_reg == offset) begin
output_axis_tdata_int = frame_count_output_reg[i*8 +: 8];
end
offset = offset + 1;
end
end
if (frame_ptr_reg == offset-1) begin
output_axis_tlast_int = 1;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_OUTPUT_DATA;
end
end
endcase
// stats collection
// increment tick count by number of words that can be transferred per cycle
tick_count_next = tick_count_next + KEEP_WIDTH;
if (monitor_axis_tready & monitor_axis_tvalid) begin
// valid transfer cycle
// increment byte count by number of words transferred
bit_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (monitor_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) bit_cnt = i;
end
byte_count_next = byte_count_next + bit_cnt;
// count frames
if (monitor_axis_tlast) begin
// end of frame
frame_next = 0;
end else if (~frame_reg) begin
// first word after end of frame
frame_count_next = frame_count_next + 1;
frame_next = 1;
end
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
tick_count_reg <= 0;
byte_count_reg <= 0;
frame_count_reg <= 0;
frame_reg <= 0;
frame_ptr_reg <= 0;
busy_reg <= 0;
tick_count_output_reg <= 0;
byte_count_output_reg <= 0;
frame_count_output_reg <= 0;
end else begin
state_reg <= state_next;
tick_count_reg <= tick_count_next;
byte_count_reg <= byte_count_next;
frame_count_reg <= frame_count_next;
frame_reg <= frame_next;
frame_ptr_reg <= frame_ptr_next;
busy_reg <= state_next != STATE_IDLE;
if (store_output) begin
tick_count_output_reg <= tick_count_reg;
byte_count_output_reg <= byte_count_reg;
frame_count_output_reg <= frame_count_reg;
end
end
end
// output datapath logic
reg [7:0] output_axis_tdata_reg = 0;
reg output_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [7:0] temp_axis_tdata_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tvalid_reg <= output_axis_tvalid_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tvalid_reg <= temp_axis_tvalid_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end
endmodule
|
`timescale 1ns / 1ps
module calc(
// clock
input wire clk,
// pushbuttons
input wire start_in, pause_in,
input wire record_in, recall_mode_in,
// switchs
input wire display_mode, // 0 is min/sec
input wire[3:0] reg_address,
// seven seg
output wire[3:0] anode,
output wire[7:0] segment,
// LEDs
output wire started_LED,
output wire paused_LED,
output wire write_LED,
output wire mode_LED);
// wire seven seg
reg[15:0] display_num;
initial begin
display_num = 16'b0;
end
display_16 seven_seg(clk, display_num, anode[3:0], segment[7:0]);
// debounce push buttons
wire start_stop, pause_resume, record_recall, recall_mode;
pbdebounce p0(clk, start_in, start_stop);
pbdebounce p1(clk, pause_in, pause_resume);
pbdebounce p2(clk, record_in, record_recall);
pbdebounce p3(clk, recall_mode_in, recall_mode);
// the stopwatch
wire[23:0] result;
wire reg_exceed;
stop_watch sw(clk,
start_stop, pause_resume,
record_recall, recall_mode,
reg_address,
reg_exceed,
started_LED, paused_LED,
write_LED, mode_LED,
result);
// choose display
always @* begin
if (reg_exceed)
display_num = 16'hEFFD; // F will display "r", D will display "."
else
case(display_mode)
1'b0: display_num = result[23:8];
1'b1: display_num = result[15:0];
endcase
end
endmodule
|
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// SVN Revision Information:
// SVN $Revision: 11864 $
// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
`timescale 1ns/100ps
module
BFM_MAIN
(
SYSCLK
,
SYSRSTN
,
PCLK
,
HCLK
,
HRESETN
,
HADDR
,
HBURST
,
HMASTLOCK
,
HPROT
,
HSIZE
,
HTRANS
,
HWRITE
,
HWDATA
,
HRDATA
,
HREADY
,
HRESP
,
HSEL
,
INTERRUPT
,
GP_OUT
,
GP_IN
,
EXT_WR
,
EXT_RD
,
EXT_ADDR
,
EXT_DATA
,
EXT_WAIT
,
CON_ADDR
,
CON_DATA
,
CON_RD
,
CON_WR
,
CON_BUSY
,
INSTR_OUT
,
INSTR_IN
,
FINISHED
,
FAILED
)
;
parameter
OPMODE
=
0
;
parameter
VECTFILE
=
"test.vec"
;
parameter
MAX_INSTRUCTIONS
=
16384
;
parameter
MAX_STACK
=
1024
;
parameter
MAX_MEMTEST
=
65536
;
parameter
TPD
=
1
;
parameter
DEBUGLEVEL
=
-
1
;
parameter
CON_SPULSE
=
0
;
parameter
ARGVALUE0
=
0
;
parameter
ARGVALUE1
=
0
;
parameter
ARGVALUE2
=
0
;
parameter
ARGVALUE3
=
0
;
parameter
ARGVALUE4
=
0
;
parameter
ARGVALUE5
=
0
;
parameter
ARGVALUE6
=
0
;
parameter
ARGVALUE7
=
0
;
parameter
ARGVALUE8
=
0
;
parameter
ARGVALUE9
=
0
;
parameter
ARGVALUE10
=
0
;
parameter
ARGVALUE11
=
0
;
parameter
ARGVALUE12
=
0
;
parameter
ARGVALUE13
=
0
;
parameter
ARGVALUE14
=
0
;
parameter
ARGVALUE15
=
0
;
parameter
ARGVALUE16
=
0
;
parameter
ARGVALUE17
=
0
;
parameter
ARGVALUE18
=
0
;
parameter
ARGVALUE19
=
0
;
parameter
ARGVALUE20
=
0
;
parameter
ARGVALUE21
=
0
;
parameter
ARGVALUE22
=
0
;
parameter
ARGVALUE23
=
0
;
parameter
ARGVALUE24
=
0
;
parameter
ARGVALUE25
=
0
;
parameter
ARGVALUE26
=
0
;
parameter
ARGVALUE27
=
0
;
parameter
ARGVALUE28
=
0
;
parameter
ARGVALUE29
=
0
;
parameter
ARGVALUE30
=
0
;
parameter
ARGVALUE31
=
0
;
parameter
ARGVALUE32
=
0
;
parameter
ARGVALUE33
=
0
;
parameter
ARGVALUE34
=
0
;
parameter
ARGVALUE35
=
0
;
parameter
ARGVALUE36
=
0
;
parameter
ARGVALUE37
=
0
;
parameter
ARGVALUE38
=
0
;
parameter
ARGVALUE39
=
0
;
parameter
ARGVALUE40
=
0
;
parameter
ARGVALUE41
=
0
;
parameter
ARGVALUE42
=
0
;
parameter
ARGVALUE43
=
0
;
parameter
ARGVALUE44
=
0
;
parameter
ARGVALUE45
=
0
;
parameter
ARGVALUE46
=
0
;
parameter
ARGVALUE47
=
0
;
parameter
ARGVALUE48
=
0
;
parameter
ARGVALUE49
=
0
;
parameter
ARGVALUE50
=
0
;
parameter
ARGVALUE51
=
0
;
parameter
ARGVALUE52
=
0
;
parameter
ARGVALUE53
=
0
;
parameter
ARGVALUE54
=
0
;
parameter
ARGVALUE55
=
0
;
parameter
ARGVALUE56
=
0
;
parameter
ARGVALUE57
=
0
;
parameter
ARGVALUE58
=
0
;
parameter
ARGVALUE59
=
0
;
parameter
ARGVALUE60
=
0
;
parameter
ARGVALUE61
=
0
;
parameter
ARGVALUE62
=
0
;
parameter
ARGVALUE63
=
0
;
parameter
ARGVALUE64
=
0
;
parameter
ARGVALUE65
=
0
;
parameter
ARGVALUE66
=
0
;
parameter
ARGVALUE67
=
0
;
parameter
ARGVALUE68
=
0
;
parameter
ARGVALUE69
=
0
;
parameter
ARGVALUE70
=
0
;
parameter
ARGVALUE71
=
0
;
parameter
ARGVALUE72
=
0
;
parameter
ARGVALUE73
=
0
;
parameter
ARGVALUE74
=
0
;
parameter
ARGVALUE75
=
0
;
parameter
ARGVALUE76
=
0
;
parameter
ARGVALUE77
=
0
;
parameter
ARGVALUE78
=
0
;
parameter
ARGVALUE79
=
0
;
parameter
ARGVALUE80
=
0
;
parameter
ARGVALUE81
=
0
;
parameter
ARGVALUE82
=
0
;
parameter
ARGVALUE83
=
0
;
parameter
ARGVALUE84
=
0
;
parameter
ARGVALUE85
=
0
;
parameter
ARGVALUE86
=
0
;
parameter
ARGVALUE87
=
0
;
parameter
ARGVALUE88
=
0
;
parameter
ARGVALUE89
=
0
;
parameter
ARGVALUE90
=
0
;
parameter
ARGVALUE91
=
0
;
parameter
ARGVALUE92
=
0
;
parameter
ARGVALUE93
=
0
;
parameter
ARGVALUE94
=
0
;
parameter
ARGVALUE95
=
0
;
parameter
ARGVALUE96
=
0
;
parameter
ARGVALUE97
=
0
;
parameter
ARGVALUE98
=
0
;
parameter
ARGVALUE99
=
0
;
localparam
[
1
:
(
3
)
*
8
]
BFMA1O
=
"2.1"
;
localparam
[
1
:
(
7
)
*
8
]
BFMA1I
=
"22Dec08"
;
input
SYSCLK
;
input
SYSRSTN
;
output
PCLK
;
wire
PCLK
;
output
HCLK
;
wire
HCLK
;
output
HRESETN
;
wire
#
TPD
HRESETN
;
output
[
31
:
0
]
HADDR
;
wire
[
31
:
0
]
#
TPD
HADDR
;
output
[
2
:
0
]
HBURST
;
wire
[
2
:
0
]
#
TPD
HBURST
;
output
HMASTLOCK
;
wire
#
TPD
HMASTLOCK
;
output
[
3
:
0
]
HPROT
;
wire
[
3
:
0
]
#
TPD
HPROT
;
output
[
2
:
0
]
HSIZE
;
wire
[
2
:
0
]
#
TPD
HSIZE
;
output
[
1
:
0
]
HTRANS
;
wire
[
1
:
0
]
#
TPD
HTRANS
;
output
HWRITE
;
wire
#
TPD
HWRITE
;
output
[
31
:
0
]
HWDATA
;
wire
[
31
:
0
]
#
TPD
HWDATA
;
input
[
31
:
0
]
HRDATA
;
input
HREADY
;
input
HRESP
;
output
[
15
:
0
]
HSEL
;
wire
[
15
:
0
]
#
TPD
HSEL
;
input
[
255
:
0
]
INTERRUPT
;
output
[
31
:
0
]
GP_OUT
;
wire
[
31
:
0
]
#
TPD
GP_OUT
;
input
[
31
:
0
]
GP_IN
;
output
EXT_WR
;
wire
#
TPD
EXT_WR
;
output
EXT_RD
;
wire
#
TPD
EXT_RD
;
output
[
31
:
0
]
EXT_ADDR
;
wire
[
31
:
0
]
#
TPD
EXT_ADDR
;
inout
[
31
:
0
]
EXT_DATA
;
wire
[
31
:
0
]
#
TPD
EXT_DATA
;
input
EXT_WAIT
;
input
[
15
:
0
]
CON_ADDR
;
inout
[
31
:
0
]
CON_DATA
;
wire
[
31
:
0
]
#
TPD
CON_DATA
;
wire
[
31
:
0
]
BFMA1l
;
input
CON_RD
;
input
CON_WR
;
output
CON_BUSY
;
reg
CON_BUSY
;
output
[
31
:
0
]
INSTR_OUT
;
reg
[
31
:
0
]
INSTR_OUT
;
input
[
31
:
0
]
INSTR_IN
;
output
FINISHED
;
wire
#
TPD
FINISHED
;
output
FAILED
;
wire
#
TPD
FAILED
;
localparam
BFMA1OI
=
0
;
wire
BFMA1II
;
integer
BFMA1lI
[
0
:
255
]
;
integer
BFMA1Ol
[
0
:
MAX_INSTRUCTIONS
-
1
]
;
reg
BFMA1Il
;
reg
[
2
:
0
]
BFMA1ll
;
reg
BFMA1O0
;
reg
[
3
:
0
]
BFMA1I0
;
reg
[
1
:
0
]
BFMA1l0
;
reg
BFMA1O1
;
wire
[
31
:
0
]
BFMA1I1
;
reg
[
31
:
0
]
BFMA1l1
;
reg
[
31
:
0
]
BFMA1OOI
;
reg
[
2
:
0
]
BFMA1IOI
;
reg
[
2
:
0
]
BFMA1lOI
;
reg
[
15
:
0
]
BFMA1OII
;
reg
BFMA1III
;
reg
BFMA1lII
;
reg
BFMA1OlI
;
reg
BFMA1IlI
;
reg
BFMA1llI
;
reg
BFMA1O0I
;
reg
BFMA1I0I
;
reg
BFMA1l0I
;
reg
[
31
:
0
]
BFMA1O1I
;
reg
[
31
:
0
]
BFMA1I1I
;
reg
[
31
:
0
]
BFMA1l1I
;
reg
[
31
:
0
]
BFMA1OOl
;
reg
[
31
:
0
]
BFMA1IOl
;
reg
[
31
:
0
]
BFMA1lOl
;
reg
[
31
:
0
]
BFMA1OIl
;
reg
[
31
:
0
]
BFMA1IIl
;
integer
BFMA1lIl
;
reg
BFMA1Oll
;
reg
BFMA1Ill
;
reg
[
31
:
0
]
BFMA1lll
;
reg
[
31
:
0
]
BFMA1O0l
;
integer
BFMA1I0l
;
reg
BFMA1l0l
;
reg
BFMA1O1l
;
reg
BFMA1I1l
;
reg
BFMA1l1l
;
reg
BFMA1OO0
;
wire
[
31
:
0
]
BFMA1IO0
;
reg
[
31
:
0
]
BFMA1lO0
;
reg
[
31
:
0
]
BFMA1OI0
;
reg
[
31
:
0
]
BFMA1II0
;
wire
[
31
:
0
]
BFMA1lI0
;
reg
[
31
:
0
]
BFMA1Ol0
;
reg
BFMA1Il0
;
reg
BFMA1ll0
;
integer
BFMA1O00
;
integer
BFMA1I00
;
reg
BFMA1l00
=
1
'b
0
;
reg
[
31
:
0
]
BFMA1O10
;
reg
[
1
:
(
80
)
*
8
]
BFMA1I10
;
reg
BFMA1l10
;
reg
BFMA1OO1
;
reg
BFMA1IO1
;
reg
BFMA1lO1
;
reg
BFMA1OI1
;
reg
BFMA1II1
;
parameter
[
31
:
0
]
BFMA1lI1
=
{
32
{
1
'b
0
}
}
;
parameter
[
255
:
0
]
BFMA1Ol1
=
{
256
{
1
'b
0
}
}
;
parameter
BFMA1Il1
=
TPD
*
1
;
assign
BFMA1II
=
SYSCLK
;
integer
BFMA1ll1
[
0
:
MAX_STACK
-
1
]
;
integer
BFMA1O01
;
integer
BFMA1I01
;
integer
BFMA1l01
;
integer
DEBUG
;
integer
BFMA1O11
;
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// SVN Revision Information:
// SVN $Revision: 11864 $
// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
localparam
BFMA1I11
=
22
;
localparam
BFMA1l11
=
0
;
localparam
BFMA1OOOI
=
4
;
localparam
BFMA1IOOI
=
8
;
localparam
BFMA1lOOI
=
12
;
localparam
BFMA1OIOI
=
16
;
localparam
BFMA1IIOI
=
20
;
localparam
BFMA1lIOI
=
24
;
localparam
BFMA1OlOI
=
28
;
localparam
BFMA1IlOI
=
32
;
localparam
BFMA1llOI
=
36
;
localparam
BFMA1O0OI
=
40
;
localparam
BFMA1I0OI
=
44
;
localparam
BFMA1l0OI
=
48
;
localparam
BFMA1O1OI
=
52
;
localparam
BFMA1I1OI
=
56
;
localparam
BFMA1l1OI
=
60
;
localparam
BFMA1OOII
=
64
;
localparam
BFMA1IOII
=
68
;
localparam
BFMA1lOII
=
72
;
localparam
BFMA1OIII
=
76
;
localparam
BFMA1IIII
=
80
;
localparam
BFMA1lIII
=
100
;
localparam
BFMA1OlII
=
101
;
localparam
BFMA1IlII
=
102
;
localparam
BFMA1llII
=
103
;
localparam
BFMA1O0II
=
104
;
localparam
BFMA1I0II
=
105
;
localparam
BFMA1l0II
=
106
;
localparam
BFMA1O1II
=
107
;
localparam
BFMA1I1II
=
108
;
localparam
BFMA1l1II
=
109
;
localparam
BFMA1OOlI
=
110
;
localparam
BFMA1IOlI
=
111
;
localparam
BFMA1lOlI
=
112
;
localparam
BFMA1OIlI
=
113
;
localparam
BFMA1IIlI
=
114
;
localparam
BFMA1lIlI
=
115
;
localparam
BFMA1OllI
=
128
;
localparam
BFMA1IllI
=
129
;
localparam
BFMA1lllI
=
130
;
localparam
BFMA1O0lI
=
131
;
localparam
BFMA1I0lI
=
132
;
localparam
BFMA1l0lI
=
133
;
localparam
BFMA1O1lI
=
134
;
localparam
BFMA1I1lI
=
135
;
localparam
BFMA1l1lI
=
136
;
localparam
BFMA1OO0I
=
137
;
localparam
BFMA1IO0I
=
138
;
localparam
BFMA1lO0I
=
139
;
localparam
BFMA1OI0I
=
140
;
localparam
BFMA1II0I
=
141
;
localparam
BFMA1lI0I
=
142
;
localparam
BFMA1Ol0I
=
150
;
localparam
BFMA1Il0I
=
151
;
localparam
BFMA1ll0I
=
152
;
localparam
BFMA1O00I
=
153
;
localparam
BFMA1I00I
=
154
;
localparam
BFMA1l00I
=
160
;
localparam
BFMA1O10I
=
161
;
localparam
BFMA1I10I
=
162
;
localparam
BFMA1l10I
=
163
;
localparam
BFMA1OO1I
=
164
;
localparam
BFMA1IO1I
=
165
;
localparam
BFMA1lO1I
=
166
;
localparam
BFMA1OI1I
=
167
;
localparam
BFMA1II1I
=
168
;
localparam
BFMA1lI1I
=
169
;
localparam
BFMA1Ol1I
=
170
;
localparam
BFMA1Il1I
=
171
;
localparam
BFMA1ll1I
=
172
;
localparam
BFMA1O01I
=
200
;
localparam
BFMA1I01I
=
201
;
localparam
BFMA1l01I
=
202
;
localparam
BFMA1O11I
=
203
;
localparam
BFMA1I11I
=
204
;
localparam
BFMA1l11I
=
205
;
localparam
BFMA1OOOl
=
206
;
localparam
BFMA1IOOl
=
207
;
localparam
BFMA1lOOl
=
208
;
localparam
BFMA1OIOl
=
209
;
localparam
BFMA1IIOl
=
210
;
localparam
BFMA1lIOl
=
211
;
localparam
BFMA1OlOl
=
212
;
localparam
BFMA1IlOl
=
213
;
localparam
BFMA1llOl
=
214
;
localparam
BFMA1O0Ol
=
215
;
localparam
BFMA1I0Ol
=
216
;
localparam
BFMA1l0Ol
=
217
;
localparam
BFMA1O1Ol
=
218
;
localparam
BFMA1I1Ol
=
219
;
localparam
BFMA1l1Ol
=
220
;
localparam
BFMA1OOIl
=
221
;
localparam
BFMA1IOIl
=
222
;
localparam
BFMA1lOIl
=
250
;
localparam
BFMA1OIIl
=
251
;
localparam
BFMA1IIIl
=
252
;
localparam
BFMA1lIIl
=
253
;
localparam
BFMA1OlIl
=
254
;
localparam
BFMA1IlIl
=
255
;
localparam
BFMA1llIl
=
1001
;
localparam
BFMA1O0Il
=
1002
;
localparam
BFMA1I0Il
=
1003
;
localparam
BFMA1l0Il
=
1004
;
localparam
BFMA1O1Il
=
1005
;
localparam
BFMA1I1Il
=
1006
;
localparam
BFMA1l1Il
=
1007
;
localparam
BFMA1OOll
=
1008
;
localparam
BFMA1IOll
=
1009
;
localparam
BFMA1lOll
=
1010
;
localparam
BFMA1OIll
=
1011
;
localparam
BFMA1IIll
=
1012
;
localparam
BFMA1lIll
=
1013
;
localparam
BFMA1Olll
=
1014
;
localparam
BFMA1Illl
=
1015
;
localparam
BFMA1llll
=
1016
;
localparam
BFMA1O0ll
=
1017
;
localparam
BFMA1I0ll
=
1018
;
localparam
BFMA1l0ll
=
1019
;
localparam
BFMA1O1ll
=
1020
;
localparam
BFMA1I1ll
=
1021
;
localparam
BFMA1l1ll
=
1022
;
localparam
BFMA1OO0l
=
1023
;
localparam
BFMA1IO0l
=
0
;
localparam
BFMA1lO0l
=
1
;
localparam
BFMA1OI0l
=
2
;
localparam
BFMA1II0l
=
3
;
localparam
BFMA1lI0l
=
4
;
localparam
BFMA1Ol0l
=
5
;
localparam
BFMA1Il0l
=
6
;
localparam
BFMA1ll0l
=
7
;
localparam
BFMA1O00l
=
8
;
localparam
BFMA1I00l
=
0
;
localparam
BFMA1l00l
=
1
;
localparam
BFMA1O10l
=
2
;
localparam
BFMA1I10l
=
3
;
localparam
BFMA1l10l
=
4
;
localparam
BFMA1OO1l
=
32
'h
00000000
;
localparam
BFMA1IO1l
=
32
'h
00002000
;
localparam
BFMA1lO1l
=
32
'h
00004000
;
localparam
BFMA1OI1l
=
32
'h
00006000
;
localparam
BFMA1II1l
=
32
'h
00008000
;
localparam
[
1
:
0
]
BFMA1lI1l
=
0
;
localparam
[
1
:
0
]
BFMA1Ol1l
=
1
;
localparam
[
1
:
0
]
BFMA1Il1l
=
2
;
localparam
[
1
:
0
]
BFMA1ll1l
=
3
;
function
integer
BFMA1O01l
;
input
[
31
:
0
]
BFMA1I01l
;
integer
BFMA1ll1l
;
begin
BFMA1ll1l
=
BFMA1I01l
;
BFMA1O01l
=
BFMA1ll1l
;
end
endfunction
function
integer
to_int_unsigned
;
input
[
31
:
0
]
BFMA1I01l
;
integer
BFMA1I01l
;
integer
BFMA1ll1l
;
begin
BFMA1ll1l
=
BFMA1I01l
;
to_int_unsigned
=
BFMA1ll1l
;
end
endfunction
function
integer
to_int_signed
;
input
[
31
:
0
]
BFMA1I01l
;
integer
BFMA1ll1l
;
begin
BFMA1ll1l
=
BFMA1I01l
;
to_int_signed
=
BFMA1ll1l
;
end
endfunction
function
[
31
:
0
]
to_slv32
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
reg
[
31
:
0
]
BFMA1I01l
;
begin
BFMA1I01l
=
BFMA1ll1l
;
to_slv32
=
BFMA1I01l
;
end
endfunction
function
[
31
:
0
]
BFMA1l01l
;
input
[
2
:
0
]
BFMA1O11l
;
input
[
1
:
0
]
BFMA1I11l
;
input
[
31
:
0
]
BFMA1l11l
;
input
BFMA1OOO0
;
integer
BFMA1OOO0
;
reg
[
31
:
0
]
BFMA1IOO0
;
reg
BFMA1lOO0
;
begin
BFMA1IOO0
=
{
32
{
1
'b
0
}
}
;
case
(
BFMA1OOO0
)
0
:
begin
case
(
BFMA1O11l
)
3
'b
000
:
begin
case
(
BFMA1I11l
)
2
'b
00
:
begin
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
01
:
begin
BFMA1IOO0
[
15
:
8
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
10
:
begin
BFMA1IOO0
[
23
:
16
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
11
:
begin
BFMA1IOO0
[
31
:
24
]
=
BFMA1l11l
[
7
:
0
]
;
end
default
:
begin
end
endcase
end
3
'b
001
:
begin
case
(
BFMA1I11l
)
2
'b
00
:
begin
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
15
:
0
]
;
end
2
'b
01
:
begin
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
15
:
0
]
;
$display
(
"BFM: Missaligned AHB Cycle(Half A10=01) ? (WARNING)"
)
;
end
2
'b
10
:
begin
BFMA1IOO0
[
31
:
16
]
=
BFMA1l11l
[
15
:
0
]
;
end
2
'b
11
:
begin
BFMA1IOO0
[
31
:
16
]
=
BFMA1l11l
[
15
:
0
]
;
$display
(
"BFM: Missaligned AHB Cycle(Half A10=11) ? (WARNING)"
)
;
end
default
:
begin
end
endcase
end
3
'b
010
:
begin
BFMA1IOO0
=
BFMA1l11l
;
case
(
BFMA1I11l
)
2
'b
00
:
begin
end
2
'b
01
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Word A10=01) ? (WARNING)"
)
;
end
2
'b
10
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Word A10=10) ? (WARNING)"
)
;
end
2
'b
11
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Word A10=11) ? (WARNING)"
)
;
end
default
:
begin
end
endcase
end
default
:
begin
$display
(
"Unexpected AHB Size setting (ERROR)"
)
;
end
endcase
end
1
:
begin
case
(
BFMA1O11l
)
3
'b
000
:
begin
case
(
BFMA1I11l
)
2
'b
00
:
begin
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
01
:
begin
BFMA1IOO0
[
15
:
8
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
10
:
begin
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
11
:
begin
BFMA1IOO0
[
15
:
8
]
=
BFMA1l11l
[
7
:
0
]
;
end
default
:
begin
end
endcase
end
3
'b
001
:
begin
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
15
:
0
]
;
case
(
BFMA1I11l
)
2
'b
00
:
begin
end
2
'b
01
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Half A10=01) ? (WARNING)"
)
;
end
2
'b
10
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Half A10=10) ? (WARNING)"
)
;
end
2
'b
11
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Half A10=11) ? (WARNING)"
)
;
end
default
:
begin
end
endcase
end
default
:
begin
$display
(
"Unexpected AHB Size setting (ERROR)"
)
;
end
endcase
end
2
:
begin
case
(
BFMA1O11l
)
3
'b
000
:
begin
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
end
default
:
begin
$display
(
"Unexpected AHB Size setting (ERROR)"
)
;
end
endcase
end
8
:
begin
BFMA1IOO0
=
BFMA1l11l
;
end
default
:
begin
$display
(
"Illegal Alignment mode (ERROR)"
)
;
end
endcase
BFMA1l01l
=
BFMA1IOO0
;
end
endfunction
function
[
31
:
0
]
BFMA1OIO0
;
input
[
2
:
0
]
BFMA1O11l
;
input
[
1
:
0
]
BFMA1I11l
;
input
[
31
:
0
]
BFMA1l11l
;
input
BFMA1OOO0
;
integer
BFMA1OOO0
;
reg
[
31
:
0
]
BFMA1IOO0
;
begin
BFMA1IOO0
=
BFMA1l01l
(
BFMA1O11l
,
BFMA1I11l
,
BFMA1l11l
,
BFMA1OOO0
)
;
BFMA1OIO0
=
BFMA1IOO0
;
end
endfunction
function
[
31
:
0
]
BFMA1IIO0
;
input
[
2
:
0
]
BFMA1O11l
;
input
[
1
:
0
]
BFMA1I11l
;
input
[
31
:
0
]
BFMA1l11l
;
input
BFMA1OOO0
;
integer
BFMA1OOO0
;
reg
[
31
:
0
]
BFMA1IOO0
;
reg
BFMA1lOO0
;
begin
if
(
BFMA1OOO0
==
8
)
begin
BFMA1IOO0
=
BFMA1l11l
;
end
else
begin
BFMA1IOO0
=
0
;
BFMA1lOO0
=
BFMA1I11l
[
1
]
;
case
(
BFMA1O11l
)
3
'b
000
:
begin
case
(
BFMA1I11l
)
2
'b
00
:
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
2
'b
01
:
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
15
:
8
]
;
2
'b
10
:
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
23
:
16
]
;
2
'b
11
:
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
31
:
24
]
;
default
:
begin
end
endcase
end
3
'b
001
:
begin
case
(
BFMA1lOO0
)
1
'b
0
:
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
15
:
0
]
;
1
'b
1
:
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
31
:
16
]
;
default
:
begin
end
endcase
end
3
'b
010
:
begin
BFMA1IOO0
=
BFMA1l11l
;
end
default
:
$display
(
"Unexpected AHB Size setting (ERROR)"
)
;
endcase
end
BFMA1IIO0
=
BFMA1IOO0
;
end
endfunction
function
integer
BFMA1lIO0
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
integer
BFMA1OlO0
;
begin
BFMA1OlO0
=
BFMA1ll1l
;
BFMA1lIO0
=
BFMA1OlO0
;
end
endfunction
function
integer
BFMA1IlO0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
integer
BFMA1OlO0
;
begin
case
(
BFMA1O11l
)
0
:
begin
BFMA1OlO0
=
'h
62
;
end
1
:
begin
BFMA1OlO0
=
'h
68
;
end
2
:
begin
BFMA1OlO0
=
'h
77
;
end
3
:
begin
BFMA1OlO0
=
'h
78
;
end
default
:
begin
BFMA1OlO0
=
'h
3f
;
end
endcase
BFMA1IlO0
=
BFMA1OlO0
;
end
endfunction
function
integer
BFMA1llO0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
input
BFMA1O0O0
;
integer
BFMA1O0O0
;
integer
BFMA1OlO0
;
begin
case
(
BFMA1O11l
)
0
:
begin
BFMA1OlO0
=
1
;
end
1
:
begin
BFMA1OlO0
=
2
;
end
2
:
begin
BFMA1OlO0
=
4
;
end
3
:
begin
BFMA1OlO0
=
BFMA1O0O0
;
end
default
:
begin
BFMA1OlO0
=
0
;
end
endcase
BFMA1llO0
=
BFMA1OlO0
;
end
endfunction
function
integer
BFMA1I0O0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
input
BFMA1l0O0
;
integer
BFMA1l0O0
;
reg
[
2
:
0
]
BFMA1OlO0
;
begin
case
(
BFMA1O11l
)
0
:
begin
BFMA1OlO0
=
3
'b
000
;
end
1
:
begin
BFMA1OlO0
=
3
'b
001
;
end
2
:
begin
BFMA1OlO0
=
3
'b
010
;
end
3
:
begin
BFMA1OlO0
=
BFMA1l0O0
;
end
default
:
begin
BFMA1OlO0
=
3
'b
XXX
;
end
endcase
BFMA1I0O0
=
BFMA1OlO0
;
end
endfunction
function
integer
BFMA1O1O0
;
input
BFMA1I1O0
;
integer
BFMA1I1O0
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
input
BFMA1l1O0
;
integer
BFMA1l1O0
;
input
BFMA1OOI0
;
integer
BFMA1OOI0
;
integer
BFMA1IOI0
;
reg
[
31
:
0
]
BFMA1lOI0
;
reg
[
31
:
0
]
BFMA1OII0
;
reg
[
31
:
0
]
BFMA1III0
;
integer
BFMA1lII0
;
reg
[
63
:
0
]
BFMA1OlI0
;
localparam
[
31
:
0
]
BFMA1IlI0
=
0
;
localparam
[
31
:
0
]
BFMA1llI0
=
1
;
begin
BFMA1lOI0
=
BFMA1ll1l
;
BFMA1OII0
=
BFMA1l1O0
;
BFMA1lII0
=
BFMA1l1O0
;
BFMA1III0
=
{
32
{
1
'b
0
}
}
;
case
(
BFMA1I1O0
)
BFMA1llIl
:
begin
BFMA1III0
=
0
;
end
BFMA1O0Il
:
begin
BFMA1III0
=
BFMA1lOI0
+
BFMA1OII0
;
end
BFMA1I0Il
:
begin
BFMA1III0
=
BFMA1lOI0
-
BFMA1OII0
;
end
BFMA1l0Il
:
begin
BFMA1OlI0
=
BFMA1lOI0
*
BFMA1OII0
;
BFMA1III0
=
BFMA1OlI0
[
31
:
0
]
;
end
BFMA1O1Il
:
begin
BFMA1III0
=
BFMA1lOI0
/
BFMA1OII0
;
end
BFMA1OOll
:
begin
BFMA1III0
=
BFMA1lOI0
&
BFMA1OII0
;
end
BFMA1IOll
:
begin
BFMA1III0
=
BFMA1lOI0
|
BFMA1OII0
;
end
BFMA1lOll
:
begin
BFMA1III0
=
BFMA1lOI0
^
BFMA1OII0
;
end
BFMA1OIll
:
begin
BFMA1III0
=
BFMA1lOI0
^
BFMA1OII0
;
end
BFMA1lIll
:
begin
if
(
BFMA1lII0
==
0
)
begin
BFMA1III0
=
BFMA1lOI0
;
end
else
begin
BFMA1III0
=
BFMA1lOI0
>>
BFMA1lII0
;
end
end
BFMA1IIll
:
begin
if
(
BFMA1lII0
==
0
)
begin
BFMA1III0
=
BFMA1lOI0
;
end
else
begin
BFMA1III0
=
BFMA1lOI0
<<
BFMA1lII0
;
end
end
BFMA1l1Il
:
begin
BFMA1OlI0
=
{
BFMA1IlI0
,
BFMA1llI0
}
;
if
(
BFMA1lII0
>
0
)
begin
begin
:
BFMA1O0I0
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
1
;
BFMA1I0I0
<=
BFMA1lII0
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OlI0
=
BFMA1OlI0
[
31
:
0
]
*
BFMA1lOI0
;
end
end
end
BFMA1III0
=
BFMA1OlI0
[
31
:
0
]
;
end
BFMA1Olll
:
begin
if
(
BFMA1lOI0
==
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1Illl
:
begin
if
(
BFMA1lOI0
!=
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1llll
:
begin
if
(
BFMA1lOI0
>
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1O0ll
:
begin
if
(
BFMA1lOI0
<
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1I0ll
:
begin
if
(
BFMA1lOI0
>=
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1l0ll
:
begin
if
(
BFMA1lOI0
<=
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1I1Il
:
begin
BFMA1III0
=
BFMA1lOI0
%
BFMA1OII0
;
end
BFMA1O1ll
:
begin
if
(
BFMA1l1O0
<=
31
)
begin
BFMA1III0
=
BFMA1lOI0
;
BFMA1III0
[
BFMA1l1O0
]
=
1
'b
1
;
end
else
begin
$display
(
"Bit operation on bit >31 (FAILURE)"
)
;
$stop
;
end
end
BFMA1I1ll
:
begin
if
(
BFMA1l1O0
<=
31
)
begin
BFMA1III0
=
BFMA1lOI0
;
BFMA1III0
[
BFMA1l1O0
]
=
1
'b
0
;
end
else
begin
$display
(
"Bit operation on bit >31 (FAILURE)"
)
;
$stop
;
end
end
BFMA1l1ll
:
begin
if
(
BFMA1l1O0
<=
31
)
begin
BFMA1III0
=
BFMA1lOI0
;
BFMA1III0
[
BFMA1l1O0
]
=
~
BFMA1III0
[
BFMA1l1O0
]
;
end
else
begin
$display
(
"Bit operation on bit >31 (FAILURE)"
)
;
$stop
;
end
end
BFMA1OO0l
:
begin
if
(
BFMA1l1O0
<=
31
)
begin
BFMA1III0
=
0
;
BFMA1III0
[
0
]
=
BFMA1lOI0
[
BFMA1l1O0
]
;
end
else
begin
$display
(
"Bit operation on bit >31 (FAILURE)"
)
;
$stop
;
end
end
default
:
begin
$display
(
"Illegal Maths Operator (FAILURE)"
)
;
$stop
;
end
endcase
BFMA1IOI0
=
BFMA1III0
;
if
(
BFMA1OOI0
>=
4
)
begin
$display
(
"Calculated %d = %d (%d) %d"
,
BFMA1IOI0
,
BFMA1ll1l
,
BFMA1I1O0
,
BFMA1l1O0
)
;
end
BFMA1O1O0
=
BFMA1IOI0
;
end
endfunction
function
[
31
:
0
]
BFMA1l0I0
;
input
[
31
:
0
]
BFMA1ll1l
;
reg
[
31
:
0
]
BFMA1O1I0
;
begin
BFMA1O1I0
=
BFMA1ll1l
;
BFMA1O1I0
=
0
;
begin
:
BFMA1I1I0
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
31
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
if
(
(
BFMA1ll1l
[
BFMA1I0I0
]
)
==
1
'b
1
)
begin
BFMA1O1I0
[
BFMA1I0I0
]
=
1
'b
1
;
end
end
end
BFMA1l0I0
=
BFMA1O1I0
;
end
endfunction
function
integer
BFMA1l1I0
;
input
BFMA1OOl0
;
integer
BFMA1OOl0
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
integer
BFMA1IOl0
;
integer
BFMA1lOl0
;
begin
BFMA1lOl0
=
BFMA1OOl0
/
BFMA1ll1l
;
BFMA1IOl0
=
BFMA1OOl0
-
BFMA1lOl0
*
BFMA1ll1l
;
BFMA1l1I0
=
BFMA1IOl0
;
end
endfunction
function
integer
BFMA1OIl0
;
input
BFMA1OOl0
;
integer
BFMA1OOl0
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
integer
BFMA1IOl0
;
integer
BFMA1lOl0
;
begin
BFMA1lOl0
=
BFMA1OOl0
/
BFMA1ll1l
;
BFMA1IOl0
=
BFMA1OOl0
-
BFMA1lOl0
*
BFMA1ll1l
;
BFMA1OIl0
=
BFMA1lOl0
;
end
endfunction
function
integer
to_boolean
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
integer
BFMA1IIl0
;
begin
BFMA1IIl0
=
0
;
if
(
BFMA1ll1l
!=
0
)
BFMA1IIl0
=
1
;
to_boolean
=
BFMA1IIl0
;
end
endfunction
function
integer
BFMA1lIl0
;
input
BFMA1Oll0
;
integer
BFMA1Oll0
;
reg
[
31
:
0
]
BFMA1Ill0
;
reg
[
31
:
0
]
BFMA1lll0
;
reg
BFMA1O0l0
;
begin
BFMA1Ill0
=
BFMA1Oll0
;
BFMA1O0l0
=
1
'b
1
;
BFMA1lll0
[
0
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
;
BFMA1lll0
[
1
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
0
]
;
BFMA1lll0
[
2
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
1
]
;
BFMA1lll0
[
3
]
=
BFMA1Ill0
[
2
]
;
BFMA1lll0
[
4
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
3
]
;
BFMA1lll0
[
5
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
4
]
;
BFMA1lll0
[
6
]
=
BFMA1Ill0
[
5
]
;
BFMA1lll0
[
7
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
6
]
;
BFMA1lll0
[
8
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
7
]
;
BFMA1lll0
[
9
]
=
BFMA1Ill0
[
8
]
;
BFMA1lll0
[
10
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
9
]
;
BFMA1lll0
[
11
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
10
]
;
BFMA1lll0
[
12
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
11
]
;
BFMA1lll0
[
13
]
=
BFMA1Ill0
[
12
]
;
BFMA1lll0
[
14
]
=
BFMA1Ill0
[
13
]
;
BFMA1lll0
[
15
]
=
BFMA1Ill0
[
14
]
;
BFMA1lll0
[
16
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
15
]
;
BFMA1lll0
[
17
]
=
BFMA1Ill0
[
16
]
;
BFMA1lll0
[
18
]
=
BFMA1Ill0
[
17
]
;
BFMA1lll0
[
19
]
=
BFMA1Ill0
[
18
]
;
BFMA1lll0
[
20
]
=
BFMA1Ill0
[
19
]
;
BFMA1lll0
[
21
]
=
BFMA1Ill0
[
20
]
;
BFMA1lll0
[
22
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
21
]
;
BFMA1lll0
[
23
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
22
]
;
BFMA1lll0
[
24
]
=
BFMA1Ill0
[
23
]
;
BFMA1lll0
[
25
]
=
BFMA1Ill0
[
24
]
;
BFMA1lll0
[
26
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
25
]
;
BFMA1lll0
[
27
]
=
BFMA1Ill0
[
26
]
;
BFMA1lll0
[
28
]
=
BFMA1Ill0
[
27
]
;
BFMA1lll0
[
29
]
=
BFMA1Ill0
[
28
]
;
BFMA1lll0
[
30
]
=
BFMA1Ill0
[
29
]
;
BFMA1lll0
[
31
]
=
BFMA1Ill0
[
30
]
;
BFMA1lIl0
=
BFMA1lll0
;
end
endfunction
function
integer
BFMA1I0l0
;
input
BFMA1Oll0
;
integer
BFMA1Oll0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
integer
BFMA1l0l0
;
integer
BFMA1I0I0
;
reg
[
31
:
0
]
BFMA1Ill0
;
begin
BFMA1Ill0
=
BFMA1Oll0
;
for
(
BFMA1I0I0
=
31
;
BFMA1I0I0
>=
BFMA1O11l
;
BFMA1I0I0
=
BFMA1I0I0
-
1
)
BFMA1Ill0
[
BFMA1I0I0
]
=
0
;
BFMA1l0l0
=
BFMA1Ill0
;
BFMA1I0l0
=
BFMA1l0l0
;
end
endfunction
function
integer
BFMA1O1l0
;
input
BFMA1Oll0
;
integer
BFMA1Oll0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
integer
BFMA1l0l0
;
reg
[
31
:
0
]
BFMA1Ill0
;
integer
BFMA1I1l0
;
integer
BFMA1I0I0
;
begin
case
(
BFMA1O11l
)
1
:
begin
BFMA1I1l0
=
0
;
end
2
:
begin
BFMA1I1l0
=
1
;
end
4
:
begin
BFMA1I1l0
=
2
;
end
8
:
begin
BFMA1I1l0
=
3
;
end
16
:
begin
BFMA1I1l0
=
4
;
end
32
:
begin
BFMA1I1l0
=
5
;
end
64
:
begin
BFMA1I1l0
=
6
;
end
128
:
begin
BFMA1I1l0
=
7
;
end
256
:
begin
BFMA1I1l0
=
8
;
end
512
:
begin
BFMA1I1l0
=
9
;
end
1024
:
begin
BFMA1I1l0
=
10
;
end
2048
:
begin
BFMA1I1l0
=
11
;
end
4096
:
begin
BFMA1I1l0
=
12
;
end
8192
:
begin
BFMA1I1l0
=
13
;
end
16384
:
begin
BFMA1I1l0
=
14
;
end
32768
:
begin
BFMA1I1l0
=
15
;
end
65536
:
begin
BFMA1I1l0
=
16
;
end
131072
:
BFMA1I1l0
=
17
;
262144
:
BFMA1I1l0
=
18
;
524288
:
BFMA1I1l0
=
19
;
1048576
:
BFMA1I1l0
=
20
;
2097152
:
BFMA1I1l0
=
21
;
4194304
:
BFMA1I1l0
=
22
;
8388608
:
BFMA1I1l0
=
23
;
16777216
:
BFMA1I1l0
=
24
;
33554432
:
BFMA1I1l0
=
25
;
67108864
:
BFMA1I1l0
=
26
;
134217728
:
BFMA1I1l0
=
27
;
268435456
:
BFMA1I1l0
=
28
;
536870912
:
BFMA1I1l0
=
29
;
1073741824
:
BFMA1I1l0
=
30
;
default
:
begin
$display
(
"Random function error (FAILURE)"
)
;
$finish
;
end
endcase
BFMA1Ill0
=
to_slv32
(
BFMA1Oll0
)
;
if
(
BFMA1I1l0
<
31
)
begin
for
(
BFMA1I0I0
=
31
;
BFMA1I0I0
>=
BFMA1I1l0
;
BFMA1I0I0
=
BFMA1I0I0
-
1
)
BFMA1Ill0
[
BFMA1I0I0
]
=
0
;
end
BFMA1l0l0
=
to_int_signed
(
BFMA1Ill0
)
;
BFMA1O1l0
=
BFMA1l0l0
;
end
endfunction
function
bound1k
;
input
BFMA1l1l0
;
integer
BFMA1l1l0
;
input
BFMA1OO00
;
integer
BFMA1OO00
;
reg
[
31
:
0
]
BFMA1IO00
;
reg
BFMA1lO00
;
begin
BFMA1IO00
=
BFMA1OO00
;
BFMA1lO00
=
0
;
case
(
BFMA1l1l0
)
0
:
begin
if
(
BFMA1IO00
[
9
:
0
]
==
10
'b
0000000000
)
begin
BFMA1lO00
=
1
;
end
end
1
:
begin
BFMA1lO00
=
1
;
end
2
:
begin
end
default
:
begin
$display
(
"Illegal Burst Boundary Set (FAILURE)"
)
;
$finish
;
end
endcase
bound1k
=
BFMA1lO00
;
end
endfunction
function
integer
BFMA1OI00
;
input
BFMA1II00
;
integer
BFMA1II00
;
integer
BFMA1lI00
;
integer
BFMA1Ol00
;
integer
BFMA1Il00
;
begin
BFMA1Ol00
=
BFMA1II00
/
65536
;
BFMA1lI00
=
BFMA1II00
%
65536
;
BFMA1Il00
=
2
+
BFMA1lI00
+
1
+
(
(
BFMA1Ol00
-
1
)
/
4
)
;
BFMA1OI00
=
BFMA1Il00
;
end
endfunction
function
[
1
:
(
256
)
*
8
]
BFMA1ll00
;
input
BFMA1O000
;
integer
BFMA1O000
;
reg
[
1
:
(
256
)
*
8
]
BFMA1I000
;
reg
[
1
:
(
256
)
*
8
]
BFMA1l000
;
integer
BFMA1I0I0
;
integer
BFMA1O100
;
integer
BFMA1I100
;
reg
[
31
:
0
]
BFMA1l100
;
integer
BFMA1lI00
;
integer
BFMA1Ol00
;
integer
BFMA1II00
;
integer
BFMA1OO10
;
begin
BFMA1Ol00
=
BFMA1Ol
[
BFMA1O000
+
1
]
/
65536
;
BFMA1lI00
=
BFMA1Ol
[
BFMA1O000
+
1
]
%
65536
;
BFMA1II00
=
2
+
BFMA1lI00
+
1
+
(
(
BFMA1Ol00
-
1
)
/
4
)
;
for
(
BFMA1O100
=
1
;
BFMA1O100
<=
256
*
8
;
BFMA1O100
=
BFMA1O100
+
1
)
BFMA1I000
[
BFMA1O100
]
=
0
;
BFMA1I0I0
=
BFMA1O000
+
2
+
BFMA1lI00
;
BFMA1I100
=
3
;
begin
:
BFMA1IO10
integer
BFMA1O100
;
for
(
BFMA1O100
=
1
;
BFMA1O100
<=
BFMA1Ol00
;
BFMA1O100
=
BFMA1O100
+
1
)
begin
BFMA1l100
=
BFMA1Ol
[
BFMA1I0I0
]
;
for
(
BFMA1OO10
=
1
;
BFMA1OO10
<=
8
;
BFMA1OO10
=
BFMA1OO10
+
1
)
BFMA1I000
[
(
BFMA1O100
-
1
)
*
8
+
BFMA1OO10
]
=
BFMA1l100
[
BFMA1I100
*
8
+
8
-
BFMA1OO10
]
;
if
(
BFMA1I100
==
0
)
begin
BFMA1I0I0
=
BFMA1I0I0
+
1
;
BFMA1I100
=
4
;
end
BFMA1I100
=
BFMA1I100
-
1
;
end
end
case
(
BFMA1lI00
)
0
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
)
;
end
1
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
,
BFMA1lI
[
2
]
)
;
end
2
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
)
;
end
3
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
,
BFMA1lI
[
4
]
)
;
end
4
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
,
BFMA1lI
[
4
]
,
BFMA1lI
[
5
]
)
;
end
5
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
,
BFMA1lI
[
4
]
,
BFMA1lI
[
5
]
,
BFMA1lI
[
6
]
)
;
end
6
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
,
BFMA1lI
[
4
]
,
BFMA1lI
[
5
]
,
BFMA1lI
[
6
]
,
BFMA1lI
[
7
]
)
;
end
7
:
begin
$sformat
(
BFMA1l000
,
BFMA1I000
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
,
BFMA1lI
[
4
]
,
BFMA1lI
[
5
]
,
BFMA1lI
[
6
]
,
BFMA1lI
[
7
]
,
BFMA1lI
[
8
]
)
;
end
default
:
begin
$display
(
"String Error (FAILURE)"
)
;
end
endcase
BFMA1ll00
=
BFMA1l000
;
end
endfunction
integer
BFMA1lO10
;
integer
BFMA1OI10
;
integer
BFMA1II10
;
integer
BFMA1lI10
;
parameter
[
2
:
0
]
BFMA1Ol10
=
0
;
parameter
[
2
:
0
]
BFMA1Il10
=
1
;
parameter
[
2
:
0
]
BFMA1ll10
=
2
;
parameter
[
2
:
0
]
BFMA1O010
=
3
;
parameter
[
2
:
0
]
BFMA1I010
=
4
;
parameter
[
2
:
0
]
BFMA1l010
=
5
;
integer
BFMA1O110
;
integer
BFMA1I110
;
integer
BFMA1l110
;
integer
BFMA1OOO1
;
integer
BFMA1IOO1
;
reg
[
2
:
0
]
BFMA1lOO1
;
integer
BFMA1OIO1
[
0
:
MAX_MEMTEST
-
1
]
;
integer
BFMA1IIO1
;
integer
BFMA1lIO1
;
integer
BFMA1OlO1
;
integer
BFMA1IlO1
;
reg
BFMA1llO1
;
integer
BFMA1O0O1
;
integer
BFMA1I0O1
;
integer
BFMA1l0O1
;
integer
BFMA1O1O1
;
integer
BFMA1I1O1
;
integer
BFMA1l1O1
;
reg
BFMA1OOI1
;
reg
BFMA1IOI1
;
reg
BFMA1lOI1
;
reg
BFMA1OII1
;
integer
BFMA1III1
;
function
automatic
integer
BFMA1lII1
;
input
BFMA1OlI1
;
input
BFMA1IlI1
;
integer
BFMA1IlI1
;
integer
BFMA1llI1
;
integer
BFMA1O0I1
;
integer
BFMA1I0I1
;
integer
BFMA1l0I1
;
integer
BFMA1O1I1
;
integer
BFMA1I1I1
;
reg
[
31
:
0
]
BFMA1I01l
;
integer
BFMA1l1I1
;
begin
if
(
BFMA1OlI1
)
begin
BFMA1I01l
=
BFMA1IlI1
;
BFMA1O0I1
=
BFMA1I01l
[
30
:
16
]
;
BFMA1I0I1
=
BFMA1I01l
[
14
:
13
]
;
BFMA1l0I1
=
BFMA1I01l
[
12
:
0
]
;
BFMA1O1I1
=
BFMA1I01l
[
12
:
8
]
;
BFMA1I1I1
=
BFMA1I01l
[
7
:
0
]
;
BFMA1l1I1
=
0
;
if
(
(
BFMA1I01l
[
15
]
)
==
1
'b
1
)
begin
BFMA1l1I1
=
BFMA1lII1
(
1
,
BFMA1O0I1
)
;
end
case
(
BFMA1I0I1
)
3
:
begin
case
(
BFMA1O1I1
)
BFMA1I00l
:
begin
case
(
BFMA1I1I1
)
BFMA1lO0l
:
begin
BFMA1llI1
=
BFMA1O01
;
end
BFMA1OI0l
:
begin
BFMA1llI1
=
(
$time
/
1
)
;
end
BFMA1II0l
:
begin
BFMA1llI1
=
DEBUG
;
end
BFMA1lI0l
:
begin
BFMA1llI1
=
BFMA1l01
;
end
BFMA1Ol0l
:
begin
BFMA1llI1
=
BFMA1II10
;
end
BFMA1Il0l
:
begin
BFMA1llI1
=
BFMA1l1O1
-
1
;
end
BFMA1ll0l
:
begin
BFMA1llI1
=
BFMA1O1O1
;
end
BFMA1O00l
:
begin
BFMA1llI1
=
BFMA1I1O1
;
end
default
:
begin
$display
(
"Illegal Parameter P0 (FAILURE)"
)
;
end
endcase
end
BFMA1l00l
:
begin
case
(
BFMA1I1I1
)
0
:
BFMA1llI1
=
ARGVALUE0
;
1
:
BFMA1llI1
=
ARGVALUE1
;
2
:
BFMA1llI1
=
ARGVALUE2
;
3
:
BFMA1llI1
=
ARGVALUE3
;
4
:
BFMA1llI1
=
ARGVALUE4
;
5
:
BFMA1llI1
=
ARGVALUE5
;
6
:
BFMA1llI1
=
ARGVALUE6
;
7
:
BFMA1llI1
=
ARGVALUE7
;
8
:
BFMA1llI1
=
ARGVALUE8
;
9
:
BFMA1llI1
=
ARGVALUE9
;
10
:
BFMA1llI1
=
ARGVALUE10
;
11
:
BFMA1llI1
=
ARGVALUE11
;
12
:
BFMA1llI1
=
ARGVALUE12
;
13
:
BFMA1llI1
=
ARGVALUE13
;
14
:
BFMA1llI1
=
ARGVALUE14
;
15
:
BFMA1llI1
=
ARGVALUE15
;
16
:
BFMA1llI1
=
ARGVALUE16
;
17
:
BFMA1llI1
=
ARGVALUE17
;
18
:
BFMA1llI1
=
ARGVALUE18
;
19
:
BFMA1llI1
=
ARGVALUE19
;
20
:
BFMA1llI1
=
ARGVALUE20
;
21
:
BFMA1llI1
=
ARGVALUE21
;
22
:
BFMA1llI1
=
ARGVALUE22
;
23
:
BFMA1llI1
=
ARGVALUE23
;
24
:
BFMA1llI1
=
ARGVALUE24
;
25
:
BFMA1llI1
=
ARGVALUE25
;
26
:
BFMA1llI1
=
ARGVALUE26
;
27
:
BFMA1llI1
=
ARGVALUE27
;
28
:
BFMA1llI1
=
ARGVALUE28
;
29
:
BFMA1llI1
=
ARGVALUE29
;
30
:
BFMA1llI1
=
ARGVALUE30
;
31
:
BFMA1llI1
=
ARGVALUE31
;
32
:
BFMA1llI1
=
ARGVALUE32
;
33
:
BFMA1llI1
=
ARGVALUE33
;
34
:
BFMA1llI1
=
ARGVALUE34
;
35
:
BFMA1llI1
=
ARGVALUE35
;
36
:
BFMA1llI1
=
ARGVALUE36
;
37
:
BFMA1llI1
=
ARGVALUE37
;
38
:
BFMA1llI1
=
ARGVALUE38
;
39
:
BFMA1llI1
=
ARGVALUE39
;
40
:
BFMA1llI1
=
ARGVALUE40
;
41
:
BFMA1llI1
=
ARGVALUE41
;
42
:
BFMA1llI1
=
ARGVALUE42
;
43
:
BFMA1llI1
=
ARGVALUE43
;
44
:
BFMA1llI1
=
ARGVALUE44
;
45
:
BFMA1llI1
=
ARGVALUE45
;
46
:
BFMA1llI1
=
ARGVALUE46
;
47
:
BFMA1llI1
=
ARGVALUE47
;
48
:
BFMA1llI1
=
ARGVALUE48
;
49
:
BFMA1llI1
=
ARGVALUE49
;
50
:
BFMA1llI1
=
ARGVALUE50
;
51
:
BFMA1llI1
=
ARGVALUE51
;
52
:
BFMA1llI1
=
ARGVALUE52
;
53
:
BFMA1llI1
=
ARGVALUE53
;
54
:
BFMA1llI1
=
ARGVALUE54
;
55
:
BFMA1llI1
=
ARGVALUE55
;
56
:
BFMA1llI1
=
ARGVALUE56
;
57
:
BFMA1llI1
=
ARGVALUE57
;
58
:
BFMA1llI1
=
ARGVALUE58
;
59
:
BFMA1llI1
=
ARGVALUE59
;
60
:
BFMA1llI1
=
ARGVALUE60
;
61
:
BFMA1llI1
=
ARGVALUE61
;
62
:
BFMA1llI1
=
ARGVALUE62
;
63
:
BFMA1llI1
=
ARGVALUE63
;
64
:
BFMA1llI1
=
ARGVALUE64
;
65
:
BFMA1llI1
=
ARGVALUE65
;
66
:
BFMA1llI1
=
ARGVALUE66
;
67
:
BFMA1llI1
=
ARGVALUE67
;
68
:
BFMA1llI1
=
ARGVALUE68
;
69
:
BFMA1llI1
=
ARGVALUE69
;
70
:
BFMA1llI1
=
ARGVALUE70
;
71
:
BFMA1llI1
=
ARGVALUE71
;
72
:
BFMA1llI1
=
ARGVALUE72
;
73
:
BFMA1llI1
=
ARGVALUE73
;
74
:
BFMA1llI1
=
ARGVALUE74
;
75
:
BFMA1llI1
=
ARGVALUE75
;
76
:
BFMA1llI1
=
ARGVALUE76
;
77
:
BFMA1llI1
=
ARGVALUE77
;
78
:
BFMA1llI1
=
ARGVALUE78
;
79
:
BFMA1llI1
=
ARGVALUE79
;
80
:
BFMA1llI1
=
ARGVALUE80
;
81
:
BFMA1llI1
=
ARGVALUE81
;
82
:
BFMA1llI1
=
ARGVALUE82
;
83
:
BFMA1llI1
=
ARGVALUE83
;
84
:
BFMA1llI1
=
ARGVALUE84
;
85
:
BFMA1llI1
=
ARGVALUE85
;
86
:
BFMA1llI1
=
ARGVALUE86
;
87
:
BFMA1llI1
=
ARGVALUE87
;
88
:
BFMA1llI1
=
ARGVALUE88
;
89
:
BFMA1llI1
=
ARGVALUE89
;
90
:
BFMA1llI1
=
ARGVALUE90
;
91
:
BFMA1llI1
=
ARGVALUE91
;
92
:
BFMA1llI1
=
ARGVALUE92
;
93
:
BFMA1llI1
=
ARGVALUE93
;
94
:
BFMA1llI1
=
ARGVALUE94
;
95
:
BFMA1llI1
=
ARGVALUE95
;
96
:
BFMA1llI1
=
ARGVALUE96
;
97
:
BFMA1llI1
=
ARGVALUE97
;
98
:
BFMA1llI1
=
ARGVALUE98
;
99
:
BFMA1llI1
=
ARGVALUE99
;
default
:
begin
$display
(
"Illegal Parameter P1 (FAILURE)"
)
;
end
endcase
end
BFMA1O10l
:
begin
BFMA1lO10
=
BFMA1lIl0
(
BFMA1lO10
)
;
BFMA1llI1
=
BFMA1I0l0
(
BFMA1lO10
,
BFMA1I1I1
)
;
end
BFMA1I10l
:
begin
BFMA1OI10
=
BFMA1lO10
;
BFMA1lO10
=
BFMA1lIl0
(
BFMA1lO10
)
;
BFMA1llI1
=
BFMA1I0l0
(
BFMA1lO10
,
BFMA1I1I1
)
;
end
BFMA1l10l
:
begin
BFMA1lO10
=
BFMA1OI10
;
BFMA1lO10
=
BFMA1lIl0
(
BFMA1lO10
)
;
BFMA1llI1
=
BFMA1I0l0
(
BFMA1lO10
,
BFMA1I1I1
)
;
end
default
:
begin
$display
(
"Illegal Parameter P2 (FAILURE)"
)
;
end
endcase
end
2
:
begin
BFMA1llI1
=
BFMA1ll1
[
BFMA1I01
-
BFMA1l0I1
+
BFMA1l1I1
]
;
end
1
:
begin
BFMA1llI1
=
BFMA1ll1
[
BFMA1l0I1
+
BFMA1l1I1
]
;
end
0
:
begin
BFMA1llI1
=
BFMA1l0I1
;
end
default
:
begin
$display
(
"Illegal Parameter P3 (FAILURE)"
)
;
end
endcase
end
else
begin
BFMA1llI1
=
BFMA1IlI1
;
end
BFMA1lII1
=
BFMA1llI1
;
end
endfunction
function
integer
BFMA1OOl1
;
input
BFMA1IlI1
;
integer
BFMA1IlI1
;
input
BFMA1I01
;
integer
BFMA1I01
;
integer
BFMA1IOl1
;
integer
BFMA1O0I1
;
integer
BFMA1I0I1
;
integer
BFMA1l0I1
;
integer
BFMA1O1I1
;
integer
BFMA1I1I1
;
reg
[
31
:
0
]
BFMA1I01l
;
integer
BFMA1l1I1
;
begin
BFMA1I01l
=
BFMA1IlI1
;
BFMA1O0I1
=
BFMA1I01l
[
30
:
16
]
;
BFMA1I0I1
=
BFMA1I01l
[
14
:
13
]
;
BFMA1l0I1
=
BFMA1I01l
[
12
:
0
]
;
BFMA1O1I1
=
BFMA1I01l
[
12
:
8
]
;
BFMA1I1I1
=
BFMA1I01l
[
7
:
0
]
;
BFMA1l1I1
=
0
;
if
(
(
BFMA1I01l
[
15
]
)
==
1
'b
1
)
begin
BFMA1l1I1
=
BFMA1lII1
(
1
,
BFMA1O0I1
)
;
end
case
(
BFMA1I0I1
)
3
:
begin
$display
(
"$Variables not allowed (FAILURE)"
)
;
end
2
:
begin
BFMA1IOl1
=
BFMA1I01
-
BFMA1l0I1
+
BFMA1l1I1
;
end
1
:
begin
BFMA1IOl1
=
BFMA1l0I1
+
BFMA1l1I1
;
end
0
:
begin
$display
(
"Immediate data not allowed (FAILURE)"
)
;
end
default
:
begin
$display
(
"Illegal Parameter P3 (FAILURE)"
)
;
end
endcase
BFMA1OOl1
=
BFMA1IOl1
;
end
endfunction
always
@
(
posedge
BFMA1II
or
negedge
SYSRSTN
)
begin
:
BFMA1lOl1
parameter
[
0
:
0
]
BFMA1OIl1
=
0
;
parameter
[
0
:
0
]
BFMA1IIl1
=
1
;
integer
BFMA1lIl1
;
reg
BFMA1Oll1
;
integer
BFMA1Ill1
[
0
:
4
]
;
reg
[
31
:
0
]
BFMA1lll1
[
0
:
255
]
;
integer
BFMA1O0l1
;
integer
BFMA1O000
;
integer
BFMA1I0l1
;
integer
BFMA1l0l1
;
integer
BFMA1O1l1
;
reg
[
31
:
0
]
BFMA1I1l1
;
reg
[
1
:
0
]
BFMA1l1l1
;
integer
BFMA1OO01
;
integer
BFMA1IO01
;
integer
BFMA1lO01
;
integer
BFMA1OI01
;
integer
BFMA1II01
;
reg
[
2
:
0
]
BFMA1lI01
;
reg
[
31
:
0
]
BFMA1Ol01
;
reg
[
31
:
0
]
BFMA1Il01
;
reg
[
31
:
0
]
BFMA1ll01
;
reg
BFMA1O001
;
reg
BFMA1I001
;
reg
BFMA1l001
;
reg
BFMA1O101
;
reg
BFMA1I101
;
reg
BFMA1l101
;
reg
BFMA1OO11
;
reg
BFMA1IO11
;
reg
BFMA1lO11
;
reg
BFMA1OI11
;
reg
BFMA1II11
;
integer
BFMA1lI11
;
integer
BFMA1Ol11
;
integer
BFMA1Il11
;
integer
BFMA1Il00
;
integer
BFMA1I0I0
;
integer
BFMA1I100
;
integer
BFMA1IlI1
;
integer
BFMA1llI1
;
integer
BFMA1ll11
;
reg
[
1
:
(
256
)
*
8
]
BFMA1l000
;
reg
[
1
:
(
256
)
*
8
]
BFMA1O011
;
reg
[
1
:
(
256
)
*
8
]
BFMA1I011
;
integer
BFMA1l011
;
integer
BFMA1O111
;
integer
BFMA1I111
;
integer
BFMA1l111
;
integer
BFMA1OOOOI
[
0
:
8191
]
;
reg
[
1
:
(
8
)
*
8
]
BFMA1IOOOI
;
reg
BFMA1lOOOI
;
reg
BFMA1OIOOI
;
reg
BFMA1IIOOI
;
integer
BFMA1lIOOI
;
integer
BFMA1OlOOI
;
integer
BFMA1IlOOI
;
integer
BFMA1llOOI
;
integer
BFMA1O0OOI
;
integer
BFMA1I0OOI
;
integer
BFMA1lI00
;
integer
BFMA1l0OOI
;
integer
BFMA1O1OOI
;
integer
BFMA1I1OOI
;
integer
BFMA1l1OOI
;
integer
BFMA1OOIOI
;
integer
BFMA1IOIOI
;
integer
BFMA1lOIOI
;
integer
BFMA1OIIOI
;
reg
[
31
:
0
]
BFMA1IIIOI
;
reg
[
31
:
0
]
BFMA1lIIOI
;
reg
BFMA1OlIOI
;
reg
BFMA1IlIOI
;
reg
BFMA1llIOI
;
reg
BFMA1O0IOI
;
reg
[
0
:
0
]
BFMA1I0IOI
;
reg
[
1
:
(
10
)
*
8
]
BFMA1l0IOI
;
reg
BFMA1O1IOI
;
reg
[
3
:
0
]
BFMA1I1IOI
;
reg
[
2
:
0
]
BFMA1l1IOI
;
integer
BFMA1OOlOI
;
reg
BFMA1IOlOI
;
reg
[
1
:
(
256
)
*
8
]
BFMA1lOlOI
[
0
:
100
]
;
integer
BFMA1OIlOI
;
integer
BFMA1IIlOI
;
reg
[
1
:
0
]
BFMA1lIlOI
;
reg
[
5
:
0
]
BFMA1OllOI
;
reg
[
16
:
0
]
BFMA1IllOI
;
reg
BFMA1lllOI
;
integer
BFMA1O0lOI
;
reg
BFMA1I0lOI
;
reg
BFMA1l0lOI
;
reg
BFMA1O1lOI
;
reg
BFMA1I1lOI
;
reg
BFMA1l1lOI
;
integer
BFMA1OO0OI
;
reg
BFMA1IO0OI
;
reg
BFMA1lO0OI
;
reg
BFMA1OI0OI
;
reg
BFMA1II0OI
;
reg
BFMA1lI0OI
;
integer
BFMA1Ol0OI
;
integer
BFMA1Il0OI
;
integer
BFMA1ll0OI
;
integer
BFMA1O00OI
;
reg
BFMA1I00OI
;
reg
[
1
:
0
]
BFMA1l00OI
;
reg
[
3
:
0
]
BFMA1O10OI
;
reg
[
2
:
0
]
BFMA1I10OI
;
reg
BFMA1l10OI
;
reg
BFMA1OO1OI
;
reg
[
256
*
8
:
0
]
BFMA1IO1OI
;
integer
BFMA1OlO0
;
integer
BFMA1OO10
;
integer
BFMA1lO1OI
;
reg
BFMA1OI1OI
;
integer
BFMA1OOI1
;
integer
BFMA1II1OI
[
0
:
15
]
;
integer
BFMA1lI1OI
;
integer
BFMA1Ol1OI
[
0
:
255
]
;
reg
[
8
:
0
]
BFMA1Il1OI
;
reg
[
8
:
0
]
BFMA1ll1OI
;
integer
BFMA1O01OI
[
0
:
255
]
;
integer
BFMA1I01OI
;
if
(
SYSRSTN
==
1
'b
0
)
begin
BFMA1OOIOI
=
0
;
BFMA1IOIOI
=
0
;
BFMA1II10
=
0
;
BFMA1OIlOI
=
0
;
BFMA1IIlOI
=
65536
;
BFMA1I0IOI
=
BFMA1OIl1
;
BFMA1lI10
=
0
;
BFMA1O1O1
=
0
;
BFMA1I1O1
=
0
;
BFMA1l00
<=
1
'b
0
;
DEBUG
<=
DEBUGLEVEL
;
BFMA1l1
<=
{
32
{
1
'b
0
}
}
;
BFMA1ll
<=
{
3
{
1
'b
0
}
}
;
BFMA1O0
<=
1
'b
0
;
BFMA1I0
<=
{
4
{
1
'b
0
}
}
;
BFMA1IOI
<=
{
3
{
1
'b
0
}
}
;
BFMA1l0
<=
{
2
{
1
'b
0
}
}
;
BFMA1O1
<=
1
'b
0
;
BFMA1O10
<=
{
32
{
1
'b
0
}
}
;
INSTR_OUT
<=
{
32
{
1
'b
0
}
}
;
BFMA1lII
<=
1
'b
0
;
BFMA1OlI
<=
1
'b
0
;
BFMA1O1I
<=
{
32
{
1
'b
0
}
}
;
BFMA1I1I
<=
{
32
{
1
'b
0
}
}
;
BFMA1l1I
<=
{
32
{
1
'b
0
}
}
;
BFMA1l1l
<=
1
'b
0
;
BFMA1l0l
<=
1
'b
0
;
BFMA1O1l
<=
1
'b
0
;
BFMA1OI0
<=
{
32
{
1
'b
0
}
}
;
BFMA1lO0
<=
{
32
{
1
'b
0
}
}
;
BFMA1l10
<=
1
'b
0
;
BFMA1I10
[
1
:
8
]
<=
{
"UNKNOWN"
,
8
'b
0
}
;
BFMA1IlI
<=
1
'b
0
;
BFMA1OOl
<=
{
32
{
1
'b
0
}
}
;
BFMA1IOl
<=
{
32
{
1
'b
0
}
}
;
BFMA1I00
<=
0
;
BFMA1OOI
<=
{
32
{
1
'b
0
}
}
;
BFMA1OO1
<=
1
'b
0
;
BFMA1Il
<=
1
'b
0
;
CON_BUSY
<=
1
'b
0
;
BFMA1I00
<=
0
;
BFMA1llI
<=
1
'b
0
;
BFMA1O0I
<=
1
'b
0
;
BFMA1IO1
<=
0
;
BFMA1lO1
<=
0
;
BFMA1OI1
<=
0
;
BFMA1II1
<=
0
;
BFMA1Oll1
=
0
;
BFMA1O000
=
0
;
BFMA1OI11
=
0
;
BFMA1l1OOI
=
0
;
BFMA1O001
=
0
;
BFMA1OO11
=
0
;
BFMA1I101
=
0
;
BFMA1I001
=
0
;
BFMA1l001
=
0
;
BFMA1O101
=
0
;
BFMA1l101
=
0
;
BFMA1IO11
=
0
;
BFMA1I01
=
0
;
BFMA1I1OOI
=
0
;
BFMA1II01
=
512
;
BFMA1IOlOI
=
0
;
BFMA1II10
=
0
;
BFMA1O0IOI
=
0
;
BFMA1O1IOI
=
1
'b
0
;
BFMA1I1IOI
=
4
'b
0011
;
BFMA1l1IOI
=
3
'b
001
;
BFMA1lOOOI
=
0
;
BFMA1lIlOI
=
2
;
BFMA1OllOI
=
4
;
BFMA1IllOI
=
0
;
BFMA1lllOI
=
0
;
BFMA1I0lOI
=
0
;
BFMA1l1lOI
=
0
;
BFMA1O01
=
0
;
BFMA1l0lOI
=
0
;
BFMA1OO0OI
=
0
;
BFMA1lO0OI
=
0
;
BFMA1OI0OI
=
0
;
BFMA1II0OI
=
0
;
BFMA1lI0OI
=
0
;
BFMA1O11
=
BFMA1OI
;
BFMA1IO0OI
=
0
;
BFMA1O00OI
=
0
;
BFMA1lO10
=
1
;
BFMA1OI10
=
1
;
BFMA1O11
=
1
;
BFMA1lI1OI
=
0
;
BFMA1Il1OI
=
0
;
BFMA1ll1OI
=
0
;
BFMA1I01OI
=
0
;
BFMA1O0lOI
=
0
;
end
else
begin
BFMA1Il0
<=
CON_RD
;
BFMA1ll0
<=
CON_WR
;
BFMA1l0l
<=
1
'b
0
;
BFMA1O1l
<=
1
'b
0
;
BFMA1l1l
<=
1
'b
0
;
BFMA1OO0
<=
1
'b
0
;
BFMA1lO11
=
0
;
if
(
~
BFMA1Oll1
)
begin
$display
(
" "
)
;
$display
(
"###########################################################################"
)
;
$display
(
"AMBA BFM Model"
)
;
$display
(
"Version %s %s"
,
BFMA1O
,
BFMA1I
)
;
$display
(
" "
)
;
$display
(
"Opening BFM Script file %0s"
,
VECTFILE
)
;
if
(
~
BFMA1Oll1
&
OPMODE
!=
2
)
begin
$readmemh
(
VECTFILE
,
BFMA1Ol
)
;
BFMA1ll11
=
3000
;
BFMA1Oll1
=
1
;
BFMA1O0l1
=
BFMA1Ol
[
4
]
;
BFMA1Ol0OI
=
BFMA1Ol
[
0
]
%
65536
;
BFMA1ll0OI
=
BFMA1Ol
[
0
]
/
65536
;
$display
(
"Read %0d Vectors - Compiler Version %0d.%0d"
,
BFMA1O0l1
,
BFMA1ll0OI
,
BFMA1Ol0OI
)
;
if
(
BFMA1ll0OI
!=
BFMA1I11
)
begin
$display
(
"Incorrect vectors file format for this BFM %0s (FAILURE) == "
,
VECTFILE
)
;
$stop
;
end
BFMA1O000
=
BFMA1Ol
[
1
]
;
BFMA1l0l1
=
BFMA1Ol
[
2
]
;
BFMA1I01
=
BFMA1Ol
[
3
]
;
BFMA1ll1
[
BFMA1I01
]
=
0
;
BFMA1I01
=
BFMA1I01
+
1
;
if
(
BFMA1O000
==
0
)
begin
$display
(
"BFM Compiler reported errors (FAILURE)"
)
;
$stop
;
end
$display
(
"BFM:Filenames referenced in Vectors"
)
;
BFMA1I1l1
=
BFMA1Ol
[
BFMA1l0l1
]
;
BFMA1OO01
=
BFMA1Ol
[
BFMA1l0l1
]
%
256
;
while
(
BFMA1OO01
==
BFMA1ll0I
)
begin
BFMA1OI01
=
BFMA1OI00
(
BFMA1Ol
[
BFMA1l0l1
+
1
]
)
;
BFMA1l000
=
BFMA1ll00
(
BFMA1l0l1
)
;
$display
(
" %0s"
,
BFMA1l000
)
;
begin
:
BFMA1l01OI
integer
BFMA1I0I0
,
BFMA1OO10
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<
256
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
for
(
BFMA1OO10
=
1
;
BFMA1OO10
<=
8
;
BFMA1OO10
=
BFMA1OO10
+
1
)
BFMA1lOlOI
[
BFMA1OIlOI
]
[
BFMA1I0I0
*
8
+
BFMA1OO10
]
=
BFMA1l000
[
BFMA1I0I0
*
8
+
BFMA1OO10
]
;
end
BFMA1OIlOI
=
BFMA1OIlOI
+
1
;
BFMA1l0l1
=
BFMA1l0l1
+
BFMA1OI01
;
BFMA1I1l1
=
to_slv32
(
BFMA1Ol
[
BFMA1l0l1
]
)
;
BFMA1OO01
=
BFMA1Ol
[
BFMA1l0l1
]
%
256
;
end
BFMA1IIlOI
=
65536
;
if
(
BFMA1OIlOI
>
1
)
BFMA1IIlOI
=
32768
;
if
(
BFMA1OIlOI
>
2
)
BFMA1IIlOI
=
16384
;
if
(
BFMA1OIlOI
>
4
)
BFMA1IIlOI
=
8912
;
if
(
BFMA1OIlOI
>
8
)
BFMA1IIlOI
=
4096
;
if
(
BFMA1OIlOI
>
16
)
BFMA1IIlOI
=
2048
;
if
(
BFMA1OIlOI
>
32
)
BFMA1IIlOI
=
1024
;
BFMA1l0lOI
=
(
OPMODE
==
0
)
;
end
end
if
(
OPMODE
==
2
&
~
BFMA1Oll1
)
begin
BFMA1IIlOI
=
65536
;
BFMA1Oll1
=
1
;
BFMA1l0lOI
=
0
;
BFMA1I01
=
BFMA1Ol
[
3
]
+
1
;
BFMA1ll1
[
BFMA1I01
]
=
0
;
BFMA1I01
=
BFMA1I01
+
1
;
end
if
(
BFMA1lI10
<=
1
)
begin
BFMA1Il
<=
1
'b
1
;
end
else
begin
BFMA1lI10
=
BFMA1lI10
-
1
;
end
case
(
BFMA1I0IOI
)
BFMA1OIl1
:
begin
if
(
HRESP
==
1
'b
1
&
HREADY
==
1
'b
1
)
begin
$display
(
"BFM: HRESP Signaling Protocol Error T2 (ERROR)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
end
if
(
HRESP
==
1
'b
1
&
HREADY
==
1
'b
0
)
begin
BFMA1I0IOI
=
BFMA1IIl1
;
end
end
BFMA1IIl1
:
begin
if
(
HRESP
==
1
'b
0
|
HREADY
==
1
'b
0
)
begin
$display
(
"BFM: HRESP Signaling Protocol Error T3 (ERROR)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
end
if
(
HRESP
==
1
'b
1
&
HREADY
==
1
'b
1
)
begin
BFMA1I0IOI
=
BFMA1OIl1
;
end
case
(
BFMA1I1OOI
)
0
:
begin
$display
(
"BFM: Unexpected HRESP Signaling Occured (ERROR)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
end
1
:
begin
BFMA1O0IOI
=
1
;
end
default
:
begin
$display
(
"BFM: HRESP mode is not correctly set (ERROR)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
end
endcase
end
endcase
if
(
OPMODE
>
0
)
begin
if
(
(
CON_WR
==
1
'b
1
)
&&
(
BFMA1ll0
==
1
'b
0
||
CON_SPULSE
==
1
)
)
begin
BFMA1Il00
=
BFMA1O01l
(
CON_ADDR
)
;
case
(
BFMA1Il00
)
0
:
begin
BFMA1l0lOI
=
(
(
BFMA1lI0
[
0
]
)
==
1
'b
1
)
;
BFMA1O1lOI
=
(
(
BFMA1lI0
[
1
]
)
==
1
'b
1
)
;
BFMA1lOOOI
=
0
;
if
(
BFMA1l0lOI
&
~
BFMA1O1lOI
)
begin
BFMA1ll1
[
BFMA1I01
]
=
0
;
BFMA1I01
=
BFMA1I01
+
1
;
end
if
(
DEBUG
>=
2
&
BFMA1l0lOI
&
~
BFMA1O1lOI
)
begin
$display
(
"BFM: Starting script at %08x (%0d parameters)"
,
BFMA1O000
,
BFMA1lI1OI
)
;
end
if
(
DEBUG
>=
2
&
BFMA1l0lOI
&
BFMA1O1lOI
)
begin
$display
(
"BFM: Starting instruction at %08x"
,
BFMA1O000
)
;
end
if
(
BFMA1l0lOI
)
begin
if
(
BFMA1lI1OI
>
0
)
begin
begin
:
BFMA1O11OI
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1lI1OI
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1ll1
[
BFMA1I01
]
=
BFMA1II1OI
[
BFMA1I0I0
]
;
BFMA1I01
=
BFMA1I01
+
1
;
end
end
BFMA1lI1OI
=
0
;
end
BFMA1Il1OI
=
0
;
BFMA1ll1OI
=
0
;
end
end
1
:
begin
BFMA1O000
=
BFMA1lI0
;
end
2
:
begin
BFMA1II1OI
[
BFMA1lI1OI
]
=
BFMA1lI0
;
BFMA1lI1OI
=
BFMA1lI1OI
+
1
;
end
default
:
begin
BFMA1Ol
[
BFMA1Il00
]
=
to_int_signed
(
BFMA1lI0
)
;
end
endcase
end
if
(
(
CON_RD
==
1
'b
1
)
&&
(
BFMA1Il0
==
1
'b
0
||
CON_SPULSE
==
1
)
)
begin
BFMA1Il00
=
BFMA1O01l
(
CON_ADDR
)
;
case
(
BFMA1Il00
)
0
:
begin
BFMA1Ol0
<=
{
32
{
1
'b
0
}
}
;
BFMA1Ol0
[
2
]
<=
BFMA1l0lOI
;
BFMA1Ol0
[
3
]
<=
(
BFMA1II10
>
0
)
;
end
1
:
begin
BFMA1Ol0
<=
BFMA1O000
;
end
2
:
begin
BFMA1Ol0
<=
BFMA1O01
;
BFMA1lI1OI
=
0
;
end
3
:
begin
if
(
BFMA1Il1OI
>
BFMA1ll1OI
)
begin
BFMA1Ol0
<=
BFMA1Ol1OI
[
BFMA1ll1OI
]
;
BFMA1ll1OI
=
BFMA1ll1OI
+
1
;
end
else
begin
$display
(
"BFM: Overread Control return stack"
)
;
BFMA1Ol0
<=
{
32
{
1
'b
0
}
}
;
end
end
default
:
begin
BFMA1Ol0
<=
{
32
{
1
'b
0
}
}
;
end
endcase
end
end
BFMA1OOIOI
=
BFMA1OOIOI
+
1
;
BFMA1l1O1
=
BFMA1l1O1
+
1
;
BFMA1OI1OI
=
1
;
while
(
BFMA1OI1OI
)
begin
BFMA1OI1OI
=
0
;
if
(
~
BFMA1OI11
&
BFMA1l0lOI
)
begin
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
7
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
BFMA1lI
[
BFMA1I0I0
]
=
0
;
BFMA1I1l1
=
BFMA1Ol
[
BFMA1O000
]
;
BFMA1l1l1
=
BFMA1I1l1
[
1
:
0
]
;
BFMA1OO01
=
BFMA1I1l1
[
7
:
0
]
;
BFMA1lO01
=
BFMA1I1l1
[
15
:
8
]
;
BFMA1l01
=
BFMA1I1l1
[
31
:
16
]
;
BFMA1Il11
=
BFMA1II01
;
BFMA1IOIOI
=
BFMA1IOIOI
+
1
;
BFMA1OI01
=
1
;
BFMA1OOlOI
=
-
1
;
BFMA1OO0OI
=
0
;
if
(
DEBUG
>=
5
)
$display
(
"BFM: Instruction %0d Line Number %0d Command %0d"
,
BFMA1O000
,
BFMA1l01
,
BFMA1OO01
)
;
if
(
BFMA1lI0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d BF %4d %4d %3d"
,
$time
,
BFMA1O000
,
BFMA1l01
,
BFMA1OO01
)
;
end
if
(
BFMA1OO01
>=
100
)
begin
BFMA1IO01
=
BFMA1OO01
;
end
else
begin
BFMA1IO01
=
4
*
(
BFMA1OO01
/
4
)
;
end
if
(
BFMA1OO01
!=
BFMA1OI1I
)
begin
BFMA1OOIOI
=
0
;
end
case
(
BFMA1IO01
)
BFMA1Ol0I
,
BFMA1Il0I
,
BFMA1ll0I
,
BFMA1OIIl
:
BFMA1Il00
=
8
;
BFMA1IlOI
,
BFMA1l0OI
:
BFMA1Il00
=
4
+
BFMA1Ol
[
BFMA1O000
+
1
]
;
BFMA1l0lI
:
BFMA1Il00
=
3
+
BFMA1Ol
[
BFMA1O000
+
2
]
;
BFMA1I0lI
:
BFMA1Il00
=
3
;
BFMA1II0I
:
BFMA1Il00
=
2
+
BFMA1Ol
[
BFMA1O000
+
1
]
;
BFMA1I11I
:
BFMA1Il00
=
3
+
BFMA1Ol
[
BFMA1O000
+
2
]
;
BFMA1OlIl
:
BFMA1Il00
=
2
+
BFMA1Ol
[
BFMA1O000
+
1
]
;
BFMA1lIlI
:
BFMA1Il00
=
3
+
BFMA1Ol
[
BFMA1O000
+
1
]
;
default
:
BFMA1Il00
=
8
;
endcase
if
(
BFMA1Il00
>
0
)
begin
begin
:
BFMA1I11OI
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1Il00
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
if
(
BFMA1I0I0
>=
1
&
BFMA1I0I0
<=
8
)
begin
BFMA1lI
[
BFMA1I0I0
]
=
BFMA1lII1
(
(
(
BFMA1I1l1
[
7
+
BFMA1I0I0
]
)
==
1
'b
1
)
,
BFMA1Ol
[
BFMA1O000
+
BFMA1I0I0
]
)
;
end
else
begin
BFMA1lI
[
BFMA1I0I0
]
=
BFMA1Ol
[
BFMA1O000
+
BFMA1I0I0
]
;
end
BFMA1lll1
[
BFMA1I0I0
]
=
to_slv32
(
BFMA1lI
[
BFMA1I0I0
]
)
;
end
end
end
case
(
BFMA1IO01
)
BFMA1IlIl
:
begin
$display
(
"BFM Compiler reported an error (FAILURE)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
$stop
;
end
BFMA1ll1I
:
begin
BFMA1OI01
=
2
;
BFMA1OI1OI
=
1
;
BFMA1Ol1OI
[
BFMA1Il1OI
]
=
BFMA1lI
[
1
]
;
BFMA1Il1OI
=
BFMA1Il1OI
+
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:conifpush %0d"
,
BFMA1l01
,
BFMA1lI
[
1
]
)
;
end
BFMA1OOOl
:
begin
BFMA1OI01
=
2
;
BFMA1Il
<=
1
'b
0
;
BFMA1lI10
=
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:RESET %0d"
,
BFMA1l01
,
BFMA1lI10
)
;
end
BFMA1IOOl
:
begin
BFMA1OI01
=
2
;
BFMA1l00
<=
BFMA1lll1
[
1
]
[
0
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:STOPCLK %0d "
,
BFMA1l01
,
BFMA1lll1
[
1
]
[
0
]
)
;
end
BFMA1l00I
:
begin
BFMA1OI01
=
2
;
BFMA1l1OOI
=
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:mode %0d (No effect in this version)"
,
BFMA1l01
,
BFMA1l1OOI
)
;
end
BFMA1O10I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
4
;
BFMA1Il00
=
BFMA1lI
[
1
]
;
BFMA1IlI1
=
BFMA1lI
[
2
]
;
BFMA1llI1
=
BFMA1lI
[
3
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:setup %0d %0d %0d "
,
BFMA1l01
,
BFMA1Il00
,
BFMA1IlI1
,
BFMA1llI1
)
;
case
(
BFMA1Il00
)
1
:
begin
BFMA1OI01
=
4
;
BFMA1lIlOI
=
BFMA1IlI1
;
BFMA1OllOI
=
BFMA1llI1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:Setup- Memory Cycle Transfer Size %0s %0d"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1lIlOI
)
,
BFMA1OllOI
)
;
end
2
:
begin
BFMA1OI01
=
3
;
BFMA1lllOI
=
to_boolean
(
BFMA1IlI1
)
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:Setup- Automatic Flush %0d"
,
BFMA1l01
,
BFMA1lllOI
)
;
end
3
:
begin
BFMA1OI01
=
3
;
BFMA1IllOI
=
BFMA1IlI1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:Setup- XRATE %0d"
,
BFMA1l01
,
BFMA1IllOI
)
;
end
4
:
begin
BFMA1OI01
=
3
;
BFMA1O0lOI
=
BFMA1IlI1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:Setup- Burst Mode %0d"
,
BFMA1l01
,
BFMA1O0lOI
)
;
end
5
:
begin
BFMA1OI01
=
3
;
BFMA1I0lOI
=
BFMA1IlI1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:Setup- Alignment %0d"
,
BFMA1l01
,
BFMA1I0lOI
)
;
if
(
BFMA1I0lOI
==
1
|
BFMA1I0lOI
==
2
)
begin
$display
(
"BFM: Untested 8 or 16 Bit alignment selected (WARNING)"
)
;
end
end
6
:
begin
BFMA1OI01
=
3
;
end
7
:
begin
BFMA1OI01
=
3
;
BFMA1l1lOI
=
BFMA1IlI1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:Setup- End Sim Action %0d"
,
BFMA1l01
,
BFMA1l1lOI
)
;
if
(
BFMA1l1lOI
>
2
)
begin
$display
(
"BFM: Unexpected End Simulation value (WARNING)"
)
;
end
end
default
:
begin
$display
(
"BFM Unknown Setup Command (FAILURE)"
)
;
end
endcase
end
BFMA1IOIl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1OI1
<=
(
(
BFMA1lll1
[
1
]
[
0
]
)
==
1
'b
1
)
;
BFMA1II1
<=
(
(
BFMA1lll1
[
1
]
[
1
]
)
==
1
'b
1
)
;
BFMA1lO1
<=
(
(
BFMA1lll1
[
1
]
[
2
]
)
==
1
'b
1
)
;
BFMA1IO1
<=
(
(
BFMA1lll1
[
1
]
[
3
]
)
==
1
'b
1
)
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:drivex %0d "
,
BFMA1l01
,
BFMA1lI
[
1
]
)
;
end
BFMA1IO1I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
3
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:error %0d %0d (No effect in this version)"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
)
;
end
BFMA1l10I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1I1IOI
=
BFMA1lll1
[
1
]
[
3
:
0
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:prot %0d "
,
BFMA1l01
,
BFMA1I1IOI
)
;
end
BFMA1OO1I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1O1IOI
=
BFMA1lll1
[
1
]
[
0
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:lock %0d "
,
BFMA1l01
,
BFMA1O1IOI
)
;
end
BFMA1lO1I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1l1IOI
=
BFMA1lll1
[
1
]
[
2
:
0
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:burst %0d "
,
BFMA1l01
,
BFMA1l1IOI
)
;
end
BFMA1OO0I
:
begin
BFMA1OI01
=
2
;
BFMA1lI11
=
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:wait %0d starting at %0d ns"
,
BFMA1l01
,
BFMA1lI11
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1OOIl
:
begin
BFMA1OI01
=
2
;
BFMA1O00OI
=
BFMA1lI
[
1
]
*
1000
+
(
$time
/
1
)
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:waitus %0d starting at %0d ns"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1l1Ol
:
begin
BFMA1OI01
=
2
;
BFMA1O00OI
=
BFMA1lI
[
1
]
*
1
+
(
$time
/
1
)
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:waitns %0d starting at %0d ns"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1OI1I
:
begin
BFMA1OI01
=
3
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:checktime %0d %0d at %0d ns"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1lI1I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
1
;
BFMA1l1O1
=
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:starttimer at %0d ns"
,
BFMA1l01
,
$time
)
;
end
BFMA1Ol1I
:
begin
BFMA1OI01
=
3
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:checktimer %0d %0d at %0d ns "
,
BFMA1l01
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1l11
:
begin
BFMA1OI01
=
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:nop"
,
BFMA1l01
)
;
end
BFMA1OOOI
:
begin
BFMA1OI01
=
4
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
BFMA1lll1
[
3
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:write %c %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1Il01
,
$time
)
;
BFMA1I101
=
1
;
end
BFMA1lOII
:
begin
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
BFMA1lll1
[
3
]
;
BFMA1I00OI
=
BFMA1lll1
[
4
]
[
0
]
;
BFMA1l00OI
=
BFMA1lll1
[
4
]
[
5
:
4
]
;
BFMA1I10OI
=
BFMA1lll1
[
4
]
[
10
:
8
]
;
BFMA1l10OI
=
BFMA1lll1
[
4
]
[
12
]
;
BFMA1O10OI
=
BFMA1lll1
[
4
]
[
19
:
16
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:idle %c %08x %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1Il01
,
BFMA1lll1
[
4
]
,
$time
)
;
BFMA1IO11
=
1
;
end
BFMA1IOOI
:
begin
BFMA1OI01
=
3
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
{
32
{
1
'b
0
}
}
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:read %c %08x at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
$time
)
;
BFMA1I001
=
1
;
end
BFMA1IOII
:
begin
BFMA1OI01
=
4
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
{
32
{
1
'b
0
}
}
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
BFMA1OOlOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
3
]
,
BFMA1I01
)
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:readstore %c %08x @%0d at %0d ns "
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1OOlOI
,
$time
)
;
BFMA1I001
=
1
;
BFMA1OO11
=
1
;
end
BFMA1lOOI
:
begin
BFMA1OI01
=
4
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
BFMA1lll1
[
3
]
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:readcheck %c %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1Il01
,
$time
)
;
BFMA1I001
=
1
;
end
BFMA1OIOI
:
begin
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
BFMA1lll1
[
3
]
;
BFMA1ll01
=
BFMA1lll1
[
4
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:readmask %c %08x %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1Il01
,
BFMA1ll01
,
$time
)
;
BFMA1I001
=
1
;
end
BFMA1IIOI
:
begin
BFMA1OI01
=
4
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
BFMA1lll1
[
3
]
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:poll %c %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1Il01
,
$time
)
;
BFMA1OI11
=
1
;
BFMA1l101
=
1
;
BFMA1l101
=
1
;
end
BFMA1lIOI
:
begin
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
BFMA1lll1
[
3
]
;
BFMA1ll01
=
BFMA1lll1
[
4
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:pollmask %c %08x %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1Il01
,
BFMA1ll01
,
$time
)
;
BFMA1l101
=
1
;
end
BFMA1OlOI
:
begin
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1Il01
=
{
32
{
1
'b
0
}
}
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
BFMA1Ol11
=
BFMA1lI
[
3
]
;
BFMA1ll01
[
BFMA1Ol11
]
=
1
'b
1
;
BFMA1Il01
[
BFMA1Ol11
]
=
BFMA1lll1
[
4
]
[
0
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:pollbit %c %08x %0d %0d at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1Ol11
,
BFMA1Il01
[
BFMA1Ol11
]
,
$time
)
;
BFMA1l101
=
1
;
end
BFMA1IlOI
:
begin
BFMA1O111
=
BFMA1lI
[
1
]
;
BFMA1OI01
=
4
+
BFMA1O111
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
2
]
+
BFMA1lI
[
3
]
)
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
begin
:
BFMA1l11OI
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1lI
[
BFMA1I0I0
+
4
]
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:writemultiple %c %08x %08x ... at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1OOOOI
[
0
]
,
$time
)
;
BFMA1l001
=
1
;
end
BFMA1llOI
:
begin
BFMA1O111
=
BFMA1lI
[
3
]
;
BFMA1OI01
=
6
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1l0OOI
=
BFMA1lI
[
4
]
;
BFMA1O1OOI
=
BFMA1lI
[
5
]
;
begin
:
BFMA1OOOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1l0OOI
;
BFMA1l0OOI
=
BFMA1l0OOI
+
BFMA1O1OOI
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:fill %c %08x %0d %0d %0d at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1O111
,
BFMA1lI
[
4
]
,
BFMA1lI
[
4
]
,
$time
)
;
BFMA1l001
=
1
;
end
BFMA1O0OI
:
begin
BFMA1O111
=
BFMA1lI
[
4
]
;
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1lIOOI
=
BFMA1lI
[
3
]
;
begin
:
BFMA1IOOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1Ol
[
2
+
BFMA1lIOOI
+
BFMA1I0I0
]
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:writetable %c %08x %0d %0d at %0d ns "
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1lIOOI
,
BFMA1O111
,
$time
)
;
BFMA1l001
=
1
;
end
BFMA1OIII
:
begin
BFMA1O111
=
BFMA1lI
[
4
]
;
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1lOIOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
3
]
,
BFMA1I01
)
;
begin
:
BFMA1lOOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1ll1
[
BFMA1lOIOI
+
BFMA1I0I0
]
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:writearray %c %08x %0d %0d at %0d ns "
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1lOIOI
,
BFMA1O111
,
$time
)
;
BFMA1l001
=
1
;
end
BFMA1I0OI
:
begin
BFMA1O111
=
BFMA1lI
[
3
]
;
BFMA1OI01
=
4
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:readmult %c %08x %0d at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1O111
,
$time
)
;
BFMA1O101
=
1
;
end
BFMA1l0OI
:
begin
BFMA1O111
=
BFMA1lI
[
1
]
;
BFMA1OI01
=
4
+
BFMA1O111
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
2
]
+
BFMA1lI
[
3
]
)
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
begin
:
BFMA1OIOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1lI
[
BFMA1I0I0
+
4
]
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:readmultchk %c %08x %08x ... at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1OOOOI
[
0
]
,
$time
)
;
BFMA1O101
=
1
;
end
BFMA1O1OI
:
begin
BFMA1O111
=
BFMA1lI
[
3
]
;
BFMA1OI01
=
6
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1l0OOI
=
BFMA1lI
[
4
]
;
BFMA1O1OOI
=
BFMA1lI
[
5
]
;
begin
:
BFMA1IIOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1l0OOI
;
BFMA1l0OOI
=
BFMA1l0OOI
+
BFMA1O1OOI
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:fillcheck %c %08x %0d %0d %0d at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1O111
,
BFMA1lI
[
4
]
,
BFMA1lI
[
5
]
,
$time
)
;
BFMA1O101
=
1
;
end
BFMA1I1OI
:
begin
BFMA1O111
=
BFMA1lI
[
4
]
;
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1lIOOI
=
BFMA1lI
[
3
]
;
begin
:
BFMA1lIOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1Ol
[
BFMA1lIOOI
+
2
+
BFMA1I0I0
]
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:readtable %c %08x %0d %0d at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1lIOOI
,
BFMA1O111
,
$time
)
;
BFMA1O101
=
1
;
end
BFMA1IIII
:
begin
BFMA1O111
=
BFMA1lI
[
4
]
;
BFMA1OI01
=
5
;
BFMA1lI01
=
BFMA1I0O0
(
BFMA1l1l1
,
BFMA1lIlOI
)
;
BFMA1Ol01
=
to_slv32
(
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
)
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
BFMA1I111
=
0
;
BFMA1l111
=
BFMA1llO0
(
BFMA1l1l1
,
BFMA1OllOI
)
;
BFMA1lOIOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
3
]
,
BFMA1I01
)
;
begin
:
BFMA1OlOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1O111
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1ll1
[
BFMA1lOIOI
+
BFMA1I0I0
]
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:readtable %c %08x %0d %0d at %0d ns"
,
BFMA1l01
,
BFMA1IlO0
(
BFMA1l1l1
)
,
BFMA1Ol01
,
BFMA1lOIOI
,
BFMA1O111
,
$time
)
;
BFMA1O101
=
1
;
end
BFMA1O00I
:
begin
BFMA1OI01
=
7
;
BFMA1O001
=
1
;
BFMA1lOO1
=
BFMA1Il10
;
end
BFMA1I00I
:
begin
BFMA1OI01
=
7
;
BFMA1O001
=
1
;
BFMA1lOO1
=
BFMA1Il10
;
end
BFMA1O1II
:
begin
BFMA1OI01
=
1
;
BFMA1IlOOI
=
0
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:waitfiq at %0d ns "
,
BFMA1l01
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1I1II
:
begin
BFMA1OI01
=
1
;
BFMA1IlOOI
=
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:waitirq at %0d ns "
,
BFMA1l01
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1l0II
:
begin
BFMA1OI01
=
2
;
BFMA1IlOOI
=
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:waitint %0d at %0d ns"
,
BFMA1l01
,
BFMA1IlOOI
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1lIII
:
begin
BFMA1OI01
=
2
;
BFMA1Il01
=
BFMA1lll1
[
1
]
;
BFMA1O10
<=
BFMA1Il01
;
BFMA1OO0
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:iowrite %08x at %0d ns "
,
BFMA1l01
,
BFMA1Il01
,
$time
)
;
end
BFMA1OlII
:
begin
BFMA1OI01
=
2
;
BFMA1Il01
=
{
32
{
1
'b
0
}
}
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
BFMA1OOlOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
1
]
,
BFMA1I01
)
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:ioread @%0d at %0d ns"
,
BFMA1l01
,
BFMA1OOlOI
,
$time
)
;
BFMA1l1l
<=
1
'b
1
;
BFMA1O001
=
1
;
BFMA1OO11
=
1
;
BFMA1lO11
=
1
;
end
BFMA1IlII
:
begin
BFMA1OI01
=
2
;
BFMA1Il01
=
BFMA1lll1
[
1
]
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
BFMA1l1l
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:iocheck %08x at %0d ns "
,
BFMA1l01
,
BFMA1Il01
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1llII
:
begin
BFMA1OI01
=
3
;
BFMA1Il01
=
BFMA1lll1
[
1
]
;
BFMA1ll01
=
BFMA1lll1
[
2
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:iomask %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1Il01
,
BFMA1ll01
,
$time
)
;
BFMA1l1l
<=
1
'b
1
;
BFMA1O001
=
1
;
end
BFMA1l1OI
:
begin
BFMA1OI01
=
2
;
BFMA1Il01
=
{
32
{
1
'b
0
}
}
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
BFMA1Ol11
=
BFMA1lI
[
1
]
;
BFMA1Il01
[
BFMA1Ol11
]
=
BFMA1I1l1
[
0
]
;
BFMA1ll01
[
BFMA1Ol11
]
=
1
'b
1
;
BFMA1l1l
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:iotest %0d %0d at %0d ns"
,
BFMA1l01
,
BFMA1Ol11
,
BFMA1I1l1
[
0
]
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1O0II
:
begin
BFMA1OI01
=
2
;
BFMA1Ol11
=
BFMA1lI
[
1
]
;
BFMA1O10
[
BFMA1Ol11
]
<=
1
'b
1
;
BFMA1OO0
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:ioset %0d at %0d ns"
,
BFMA1l01
,
BFMA1Ol11
,
$time
)
;
end
BFMA1I0II
:
begin
BFMA1OI01
=
2
;
BFMA1Ol11
=
BFMA1lI
[
1
]
;
BFMA1O10
[
BFMA1Ol11
]
<=
1
'b
0
;
BFMA1OO0
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:ioclr %0d at %0d ns"
,
BFMA1l01
,
BFMA1Ol11
,
$time
)
;
end
BFMA1OOII
:
begin
BFMA1OI01
=
2
;
BFMA1Il01
=
{
32
{
1
'b
0
}
}
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
BFMA1Ol11
=
BFMA1lI
[
1
]
;
BFMA1Il01
[
BFMA1Ol11
]
=
BFMA1I1l1
[
0
]
;
BFMA1ll01
[
BFMA1Ol11
]
=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:iowait %0d %0d at %0d ns "
,
BFMA1l01
,
BFMA1Ol11
,
BFMA1I1l1
[
0
]
,
$time
)
;
BFMA1l1l
<=
1
'b
1
;
BFMA1O001
=
1
;
end
BFMA1OOlI
:
begin
BFMA1OI01
=
3
;
BFMA1Ol01
=
BFMA1lll1
[
1
]
;
BFMA1Il01
=
BFMA1lll1
[
2
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:extwrite %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1Ol01
,
BFMA1Il01
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1IOlI
:
begin
BFMA1OI01
=
3
;
BFMA1Ol01
=
BFMA1lll1
[
1
]
;
BFMA1Il01
=
{
32
{
1
'b
0
}
}
;
BFMA1ll01
=
{
32
{
1
'b
0
}
}
;
BFMA1OOlOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
2
]
,
BFMA1I01
)
;
BFMA1O1l
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:extread @%0d %08x at %0d ns "
,
BFMA1l01
,
BFMA1OOlOI
,
BFMA1Ol01
,
$time
)
;
BFMA1O001
=
1
;
BFMA1OO11
=
1
;
BFMA1lO11
=
1
;
end
BFMA1lIlI
:
begin
BFMA1O111
=
BFMA1lI
[
1
]
;
BFMA1l011
=
BFMA1lI
[
2
]
;
BFMA1OI01
=
BFMA1O111
+
3
;
begin
:
BFMA1IlOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<
BFMA1O111
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OOOOI
[
BFMA1I0I0
]
=
BFMA1lI
[
BFMA1I0I0
+
3
]
;
end
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:extwrite %08x %0d Words at %0t ns"
,
BFMA1l01
,
BFMA1Ol01
,
BFMA1O111
,
$time
)
;
BFMA1I111
=
0
;
BFMA1O001
=
1
;
end
BFMA1lOlI
:
begin
BFMA1OI01
=
3
;
BFMA1Ol01
=
BFMA1lll1
[
1
]
;
BFMA1Il01
=
BFMA1lll1
[
2
]
;
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
BFMA1OI11
=
1
;
BFMA1O1l
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:extcheck %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1Ol01
,
BFMA1Il01
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1OIlI
:
begin
BFMA1OI01
=
4
;
BFMA1Ol01
=
BFMA1lll1
[
1
]
;
BFMA1Il01
=
BFMA1lll1
[
2
]
;
BFMA1ll01
=
BFMA1lll1
[
3
]
;
BFMA1O1l
<=
1
'b
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:extmask %08x %08x %08x at %0d ns"
,
BFMA1l01
,
BFMA1Ol01
,
BFMA1Il01
,
BFMA1ll01
,
$time
)
;
BFMA1O001
=
1
;
end
BFMA1IIlI
:
begin
BFMA1OI01
=
1
;
BFMA1lI11
=
1
;
BFMA1OI11
=
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:extwait "
,
BFMA1l01
)
;
BFMA1O001
=
1
;
end
BFMA1OllI
:
begin
$display
(
"LABEL instructions not allowed in vector files (FAILURE)"
)
;
end
BFMA1II0I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
+
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:table %08x ... (length=%0d)"
,
BFMA1l01
,
BFMA1lI
[
2
]
,
BFMA1OI01
-
2
)
;
end
BFMA1IllI
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
;
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:jump"
,
BFMA1l01
)
;
end
BFMA1lllI
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
3
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
;
if
(
BFMA1lI
[
2
]
==
0
)
begin
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:jumpz %08x"
,
BFMA1l01
,
BFMA1lI
[
2
]
)
;
end
BFMA1lOOl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
5
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
;
BFMA1OIIOI
=
BFMA1O1O0
(
BFMA1lI
[
3
]
,
BFMA1lI
[
2
]
,
BFMA1lI
[
4
]
,
DEBUG
)
;
if
(
BFMA1OIIOI
==
0
)
begin
BFMA1OI01
=
BFMA1I0OOI
+
2
-
BFMA1O000
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:if %08x func %08x"
,
BFMA1l01
,
BFMA1lI
[
2
]
,
BFMA1lI
[
4
]
)
;
end
BFMA1OIOl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
5
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
;
BFMA1OIIOI
=
BFMA1O1O0
(
BFMA1lI
[
3
]
,
BFMA1lI
[
2
]
,
BFMA1lI
[
4
]
,
DEBUG
)
;
if
(
BFMA1OIIOI
!=
0
)
begin
BFMA1OI01
=
BFMA1I0OOI
+
2
-
BFMA1O000
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:ifnot %08x func %08x"
,
BFMA1l01
,
BFMA1lI
[
2
]
,
BFMA1lI
[
4
]
)
;
end
BFMA1lIOl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
;
BFMA1OI01
=
BFMA1I0OOI
+
2
-
BFMA1O000
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:else "
,
BFMA1l01
)
;
end
BFMA1OlOl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:endif "
,
BFMA1l01
)
;
end
BFMA1IIOl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
5
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
+
2
;
BFMA1OIIOI
=
BFMA1O1O0
(
BFMA1lI
[
3
]
,
BFMA1lI
[
2
]
,
BFMA1lI
[
4
]
,
DEBUG
)
;
if
(
BFMA1OIIOI
==
0
)
begin
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:while %08x func %08x"
,
BFMA1l01
,
BFMA1lI
[
2
]
,
BFMA1lI
[
4
]
)
;
end
BFMA1IlOl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
;
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:endwhile"
,
BFMA1l01
)
;
end
BFMA1O0Ol
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
4
;
BFMA1I0OOI
=
BFMA1lI
[
3
]
;
if
(
BFMA1lI
[
1
]
!=
BFMA1lI
[
2
]
)
begin
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
end
else
begin
BFMA1O01OI
[
BFMA1I01OI
]
=
1
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:when %08x=%08x %08x"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
)
;
end
BFMA1l0Ol
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
4
;
BFMA1I0OOI
=
BFMA1lI
[
3
]
;
if
(
BFMA1O01OI
[
BFMA1I01OI
]
)
begin
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
end
else
begin
BFMA1O01OI
[
BFMA1I01OI
]
=
0
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:default %08x=%08x %08x"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
)
;
end
BFMA1llOl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
1
;
BFMA1I01OI
=
BFMA1I01OI
+
1
;
BFMA1O01OI
[
BFMA1I01OI
]
=
0
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:case"
,
BFMA1l01
)
;
end
BFMA1I0Ol
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
1
;
BFMA1I01OI
=
BFMA1I01OI
-
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:endcase"
,
BFMA1l01
)
;
end
BFMA1O0lI
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
3
;
BFMA1I0OOI
=
BFMA1lI
[
1
]
;
if
(
BFMA1lI
[
2
]
!=
0
)
begin
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:jumpnz %08x"
,
BFMA1l01
,
BFMA1lI
[
2
]
)
;
end
BFMA1l11I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
4
;
BFMA1Il01
=
BFMA1lll1
[
2
]
;
BFMA1ll01
=
BFMA1lll1
[
3
]
;
BFMA1Il0OI
=
(
BFMA1lll1
[
1
]
^
BFMA1Il01
)
&
BFMA1ll01
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:compare %08x==%08x Mask=%08x (RES=%08x) at %0d ns"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
BFMA1Il01
,
BFMA1ll01
,
BFMA1Il0OI
,
$time
)
;
if
(
BFMA1Il0OI
!=
0
)
begin
BFMA1II10
=
BFMA1II10
+
1
;
$display
(
"ERROR: compare failed %08x==%08x Mask=%08x (RES=%08x) "
,
BFMA1lI
[
1
]
,
BFMA1Il01
,
BFMA1ll01
,
BFMA1Il0OI
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1l01
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1l01
,
BFMA1IIlOI
)
)
;
$display
(
"BFM Data Compare Error (ERROR)"
)
;
$stop
;
end
end
BFMA1O1Ol
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
4
;
BFMA1Il01
=
BFMA1lll1
[
2
]
;
BFMA1ll01
=
BFMA1lll1
[
3
]
;
if
(
BFMA1lI
[
1
]
>=
BFMA1lI
[
2
]
&
BFMA1lI
[
1
]
<=
BFMA1lI
[
3
]
)
begin
BFMA1Il0OI
=
1
;
end
else
begin
BFMA1Il0OI
=
0
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:cmprange %0d in %0d to %0d at %0d ns"
,
BFMA1l01
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
,
$time
)
;
if
(
BFMA1Il0OI
==
0
)
begin
BFMA1II10
=
BFMA1II10
+
1
;
$display
(
"ERROR: cmprange failed %0d in %0d to %0d"
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1l01
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1l01
,
BFMA1IIlOI
)
)
;
$display
(
"BFM Data Compare Error (ERROR)"
)
;
$stop
;
end
end
BFMA1O11I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1lI00
=
BFMA1lI
[
1
]
;
BFMA1I01
=
BFMA1I01
+
BFMA1lI00
;
BFMA1ll1
[
BFMA1I01
]
=
0
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:int %0d"
,
BFMA1l01
,
BFMA1lI
[
1
]
)
;
end
BFMA1I0lI
,
BFMA1l0lI
:
begin
BFMA1OI1OI
=
1
;
if
(
BFMA1OO01
==
BFMA1I0lI
)
begin
BFMA1OI01
=
2
;
BFMA1lI00
=
0
;
end
else
begin
BFMA1lI00
=
BFMA1lI
[
2
]
;
BFMA1OI01
=
3
+
BFMA1lI00
;
end
BFMA1llOOI
=
BFMA1lI
[
1
]
;
BFMA1O0OOI
=
BFMA1O000
+
BFMA1OI01
;
BFMA1OI01
=
BFMA1llOOI
-
BFMA1O000
;
BFMA1ll1
[
BFMA1I01
]
=
BFMA1O0OOI
;
BFMA1I01
=
BFMA1I01
+
1
;
if
(
BFMA1lI00
>
0
)
begin
begin
:
BFMA1llOII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1lI00
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1ll1
[
BFMA1I01
]
=
BFMA1lI
[
3
+
BFMA1I0I0
]
;
BFMA1I01
=
BFMA1I01
+
1
;
end
end
end
if
(
DEBUG
>=
2
&
BFMA1OO01
==
BFMA1I0lI
)
$display
(
"BFM:%0d:call %0d"
,
BFMA1l01
,
BFMA1llOOI
)
;
if
(
DEBUG
>=
2
&
BFMA1OO01
==
BFMA1l0lI
)
$display
(
"BFM:%0d:call %0d %08x ..."
,
BFMA1l01
,
BFMA1llOOI
,
BFMA1lI
[
3
]
)
;
end
BFMA1O1lI
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1I01
=
BFMA1I01
-
BFMA1lI
[
1
]
;
BFMA1O0OOI
=
0
;
if
(
BFMA1I01
>
0
)
begin
BFMA1I01
=
BFMA1I01
-
1
;
BFMA1O0OOI
=
BFMA1ll1
[
BFMA1I01
]
;
end
if
(
BFMA1O0OOI
==
0
)
begin
BFMA1lOOOI
=
1
;
BFMA1OO11
=
1
;
BFMA1OI1OI
=
0
;
end
else
begin
BFMA1OI01
=
BFMA1O0OOI
-
BFMA1O000
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:return"
,
BFMA1l01
)
;
end
BFMA1I1Ol
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
3
;
BFMA1I01
=
BFMA1I01
-
BFMA1lI
[
1
]
;
BFMA1O0OOI
=
0
;
if
(
BFMA1I01
>
0
)
begin
BFMA1I01
=
BFMA1I01
-
1
;
BFMA1O0OOI
=
BFMA1ll1
[
BFMA1I01
]
;
end
BFMA1O01
=
BFMA1lI
[
2
]
;
if
(
BFMA1O0OOI
==
0
)
begin
BFMA1lOOOI
=
1
;
BFMA1OO11
=
1
;
BFMA1OI1OI
=
0
;
end
else
begin
BFMA1OI01
=
BFMA1O0OOI
-
BFMA1O000
;
end
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:return %08x"
,
BFMA1l01
,
BFMA1O01
)
;
end
BFMA1I1lI
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
5
;
BFMA1lOIOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
1
]
,
BFMA1I01
)
;
BFMA1OIIOI
=
BFMA1lI
[
2
]
;
BFMA1ll1
[
BFMA1lOIOI
]
=
BFMA1OIIOI
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:loop %0d %0d %0d %0d "
,
BFMA1l01
,
BFMA1lOIOI
,
BFMA1lI
[
2
]
,
BFMA1lI
[
3
]
,
BFMA1lI
[
4
]
)
;
end
BFMA1l1lI
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1I0l1
=
BFMA1lI
[
1
]
;
begin
:
BFMA1O0OII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
2
;
BFMA1I0I0
<=
4
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1Ill1
[
BFMA1I0I0
]
=
BFMA1lII1
(
(
to_slv32
(
BFMA1Ol
[
BFMA1I0l1
]
[
7
+
BFMA1I0I0
]
)
==
1
'b
1
)
,
BFMA1Ol
[
BFMA1I0l1
+
BFMA1I0I0
]
)
;
end
end
BFMA1lOIOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1I0l1
+
1
]
,
BFMA1I01
)
;
BFMA1Il00
=
BFMA1Ill1
[
4
]
;
BFMA1I100
=
BFMA1Ill1
[
3
]
;
BFMA1O1l1
=
BFMA1ll1
[
BFMA1lOIOI
]
;
BFMA1O1l1
=
BFMA1O1l1
+
BFMA1Il00
;
BFMA1ll1
[
BFMA1lOIOI
]
=
BFMA1O1l1
;
BFMA1I0OOI
=
BFMA1I0l1
+
5
;
if
(
(
BFMA1Il00
>=
0
&
BFMA1O1l1
<=
BFMA1I100
)
|
(
BFMA1Il00
<
0
&
BFMA1O1l1
>=
BFMA1I100
)
)
begin
BFMA1OI01
=
BFMA1I0OOI
-
BFMA1O000
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:endloop (Next Loop=%0d)"
,
BFMA1l01
,
BFMA1O1l1
)
;
end
else
begin
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:endloop (Finished)"
,
BFMA1l01
)
;
end
end
BFMA1OI0I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1II01
=
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:timeout %0d"
,
BFMA1l01
,
BFMA1II01
)
;
end
BFMA1Il1I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
BFMA1lO10
=
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:rand %0d"
,
BFMA1l01
,
BFMA1lO10
)
;
end
BFMA1Ol0I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
BFMA1OI00
(
BFMA1Ol
[
BFMA1O000
+
1
]
)
;
BFMA1l000
=
BFMA1ll00
(
BFMA1O000
)
;
$display
(
"BFM:%0s"
,
BFMA1l000
)
;
end
BFMA1Il0I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
BFMA1OI00
(
BFMA1Ol
[
BFMA1O000
+
1
]
)
;
BFMA1l000
=
BFMA1ll00
(
BFMA1O000
)
;
$display
(
"################################################################"
)
;
$display
(
"BFM:%0s"
,
BFMA1l000
)
;
end
BFMA1ll0I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OlOOI
=
BFMA1O01l
(
BFMA1I1l1
[
15
:
8
]
)
;
BFMA1OI01
=
(
BFMA1OlOOI
-
1
)
/
4
+
2
;
end
BFMA1I10I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
if
(
DEBUGLEVEL
>=
0
&
DEBUGLEVEL
<=
5
)
begin
$display
(
"BFM:%0d: DEBUG - ignored due to DEBUGLEVEL generic setting"
,
BFMA1l01
)
;
end
else
begin
DEBUG
<=
BFMA1lI
[
1
]
;
$display
(
"BFM:%0d: DEBUG %0d"
,
BFMA1l01
,
BFMA1lI
[
1
]
)
;
end
end
BFMA1l1II
:
begin
BFMA1OI1OI
=
0
;
BFMA1OI01
=
2
;
BFMA1I1OOI
=
BFMA1lI
[
1
]
;
BFMA1l0IOI
[
1
]
=
BFMA1OI
;
if
(
BFMA1I1OOI
==
2
)
begin
if
(
BFMA1O0IOI
)
begin
BFMA1l0IOI
[
1
:
9
]
=
{
"OCCURRED"
,
BFMA1OI
}
;
end
else
begin
$display
(
"BFM: HRESP Did Not Occur When Expected (ERROR)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
$stop
;
end
BFMA1I1OOI
=
0
;
end
BFMA1O0IOI
=
0
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:hresp %0d %0s"
,
BFMA1l01
,
BFMA1I1OOI
,
BFMA1l0IOI
)
;
end
BFMA1IO0I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:stop %0d"
,
BFMA1l01
,
BFMA1lI
[
1
]
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1l01
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1l01
,
BFMA1IIlOI
)
)
;
case
(
BFMA1lI
[
1
]
)
0
:
begin
$display
(
"BFM Script Stop Command (NOTE)"
)
;
end
1
:
begin
$display
(
"BFM Script Stop Command (WARNING)"
)
;
end
3
:
begin
$display
(
"BFM Script Stop Command (FAILURE)"
)
;
$stop
;
end
default
:
begin
$display
(
"BFM Script Stop Command (ERROR)"
)
;
$stop
;
end
endcase
end
BFMA1lO0I
:
begin
BFMA1lOOOI
=
1
;
end
BFMA1OlIl
:
begin
BFMA1OI1OI
=
1
;
if
(
DEBUG
>=
1
)
$display
(
"BFM:%0d:echo at %0d ns"
,
BFMA1l01
,
$time
)
;
BFMA1OI01
=
2
+
BFMA1lI
[
1
]
;
$display
(
"BFM Parameter values are"
)
;
begin
:
BFMA1I0OII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
BFMA1OI01
-
3
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
$display
(
" Para %0d=0x%08x (%0d)"
,
BFMA1I0I0
+
1
,
BFMA1lll1
[
2
+
BFMA1I0I0
]
,
BFMA1lll1
[
2
+
BFMA1I0I0
]
)
;
end
end
end
BFMA1lI0I
:
begin
BFMA1OI01
=
2
;
BFMA1lI11
=
BFMA1lI
[
1
]
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:flush %0d at %0d ns"
,
BFMA1l01
,
BFMA1lI11
,
$time
)
;
BFMA1OO11
=
1
;
BFMA1O001
=
1
;
end
BFMA1II1I
:
begin
BFMA1OI1OI
=
1
;
BFMA1II10
=
BFMA1II10
+
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:setfail"
,
BFMA1l01
)
;
$display
(
"BFM: User Script detected ERROR (ERROR)"
)
;
$stop
;
end
BFMA1I01I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
3
;
BFMA1lOIOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
1
]
,
BFMA1I01
)
;
BFMA1OIIOI
=
BFMA1lI
[
2
]
;
BFMA1ll1
[
BFMA1lOIOI
]
=
BFMA1OIIOI
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:set %0d= 0x%08x (%0d)"
,
BFMA1l01
,
BFMA1lOIOI
,
BFMA1OIIOI
,
BFMA1OIIOI
)
;
end
BFMA1I11I
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
BFMA1lI
[
2
]
+
3
;
BFMA1lOIOI
=
BFMA1OOl1
(
BFMA1Ol
[
BFMA1O000
+
1
]
,
BFMA1I01
)
;
BFMA1OIIOI
=
BFMA1O1O0
(
BFMA1lI
[
4
]
,
BFMA1lI
[
3
]
,
BFMA1lI
[
5
]
,
DEBUG
)
;
BFMA1I0I0
=
6
;
while
(
BFMA1I0I0
<
BFMA1OI01
)
begin
BFMA1OIIOI
=
BFMA1O1O0
(
BFMA1lI
[
BFMA1I0I0
]
,
BFMA1OIIOI
,
BFMA1lI
[
BFMA1I0I0
+
1
]
,
DEBUG
)
;
BFMA1I0I0
=
BFMA1I0I0
+
2
;
end
BFMA1ll1
[
BFMA1lOIOI
]
=
BFMA1OIIOI
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:set %0d= 0x%08x (%0d)"
,
BFMA1l01
,
BFMA1lOIOI
,
BFMA1OIIOI
,
BFMA1OIIOI
)
;
end
BFMA1OIIl
:
begin
BFMA1OI1OI
=
1
;
if
(
BFMA1O11
)
begin
$fflush
(
BFMA1lIl1
)
;
$fclose
(
BFMA1lIl1
)
;
end
BFMA1OI01
=
BFMA1OI00
(
BFMA1Ol
[
BFMA1O000
+
1
]
)
;
BFMA1I011
=
BFMA1ll00
(
BFMA1O000
)
;
$display
(
"BFM:%0d:LOGFILE %0s"
,
BFMA1l01
,
BFMA1I011
)
;
BFMA1lIl1
=
$fopen
(
BFMA1I011
,
"w"
)
;
BFMA1O11
=
1
;
end
BFMA1IIIl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
2
;
$display
(
"BFM:%0d:LOGSTART %0d"
,
BFMA1l01
,
BFMA1lI
[
1
]
)
;
if
(
BFMA1O11
==
0
)
begin
$display
(
"Logfile not defined, ignoring command (ERROR)"
)
;
end
else
begin
BFMA1lO0OI
=
(
(
BFMA1lll1
[
1
]
[
0
]
)
==
1
'b
1
)
;
BFMA1OI0OI
=
(
(
BFMA1lll1
[
1
]
[
1
]
)
==
1
'b
1
)
;
BFMA1II0OI
=
(
(
BFMA1lll1
[
1
]
[
2
]
)
==
1
'b
1
)
;
BFMA1lI0OI
=
(
(
BFMA1lll1
[
1
]
[
3
]
)
==
1
'b
1
)
;
end
end
BFMA1lIIl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
1
;
$display
(
"BFM:%0d:LOGSTOP"
,
BFMA1l01
)
;
BFMA1lO0OI
=
0
;
BFMA1OI0OI
=
0
;
BFMA1II0OI
=
0
;
BFMA1lI0OI
=
0
;
end
BFMA1lOIl
:
begin
BFMA1OI1OI
=
1
;
BFMA1OI01
=
1
;
$display
(
"BFM:%0d:VERSION"
,
BFMA1l01
)
;
$display
(
" BFM Verilog Version %0s"
,
BFMA1O
)
;
$display
(
" BFM Date %0s"
,
BFMA1I
)
;
$display
(
" SVN Revision $Revision: 11864 $"
)
;
$display
(
" SVN Date $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $"
)
;
$display
(
" Compiler Version %0d"
,
BFMA1Ol0OI
)
;
$display
(
" Vectors Version %0d"
,
BFMA1ll0OI
)
;
$display
(
" No of Vectors %0d"
,
BFMA1O0l1
)
;
if
(
BFMA1O11
!=
BFMA1OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d VR %0s %0s %0d %0d %0d"
,
$time
,
BFMA1O
,
BFMA1I
,
BFMA1Ol0OI
,
BFMA1ll0OI
,
BFMA1O0l1
)
;
end
end
default
:
begin
$display
(
"BFM: Instruction %0d Line Number %0d Command %0d"
,
BFMA1O000
,
BFMA1l01
,
BFMA1OO01
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1l01
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1l01
,
BFMA1IIlOI
)
)
;
$display
(
"Instruction not yet implemented (ERROR)"
)
;
$stop
;
end
endcase
end
if
(
BFMA1OI1OI
)
begin
BFMA1OI11
=
0
;
BFMA1O000
=
BFMA1O000
+
BFMA1OI01
;
BFMA1OI01
=
0
;
end
end
BFMA1OlIOI
=
0
;
BFMA1IlIOI
=
0
;
BFMA1llIOI
=
0
;
if
(
BFMA1IlI
==
1
'b
1
)
begin
BFMA1IIIOI
=
BFMA1OOl
&
BFMA1IOl
;
BFMA1lIIOI
=
HRDATA
&
BFMA1IOl
;
BFMA1OlIOI
=
(
BFMA1IIIOI
===
BFMA1lIIOI
)
;
end
if
(
BFMA1I1l
==
1
'b
1
)
begin
BFMA1IIIOI
=
BFMA1lll
&
BFMA1O0l
;
BFMA1lIIOI
=
BFMA1IO0
&
BFMA1O0l
;
BFMA1IlIOI
=
(
BFMA1IIIOI
===
BFMA1lIIOI
)
;
end
if
(
BFMA1l1l
==
1
'b
1
)
begin
BFMA1IIIOI
=
BFMA1OIl
&
BFMA1IIl
;
BFMA1lIIOI
=
GP_IN
&
BFMA1IIl
;
BFMA1llIOI
=
(
BFMA1IIIOI
===
BFMA1lIIOI
)
;
end
BFMA1IOlOI
=
BFMA1I001
|
BFMA1I101
|
BFMA1l001
|
BFMA1O101
|
BFMA1l101
|
BFMA1IO11
|
BFMA1lO11
|
to_boolean
(
BFMA1IlI
|
BFMA1OlI
|
BFMA1lII
|
BFMA1III
|
BFMA1O1l
|
BFMA1I1l
|
BFMA1l1l
)
;
if
(
BFMA1O001
)
begin
case
(
BFMA1IO01
)
BFMA1lI0I
:
begin
if
(
~
BFMA1IOlOI
)
begin
if
(
BFMA1lI11
<=
1
)
begin
BFMA1O001
=
0
;
end
else
begin
BFMA1lI11
=
BFMA1lI11
-
1
;
end
end
end
BFMA1OO0I
:
begin
if
(
BFMA1lI11
<=
1
)
begin
BFMA1O001
=
0
;
end
else
begin
BFMA1lI11
=
BFMA1lI11
-
1
;
end
end
BFMA1l1Ol
,
BFMA1OOIl
:
begin
if
(
$time
>=
BFMA1O00OI
)
begin
BFMA1O001
=
0
;
end
end
BFMA1I1II
,
BFMA1O1II
,
BFMA1l0II
:
begin
if
(
BFMA1IlOOI
==
256
)
begin
BFMA1I1lOI
=
(
INTERRUPT
!=
BFMA1Ol1
)
;
end
else
begin
BFMA1I1lOI
=
(
(
INTERRUPT
[
BFMA1IlOOI
]
)
===
1
'b
1
)
;
end
if
(
BFMA1I1lOI
)
begin
if
(
DEBUG
>=
2
)
$display
(
"BFM:Interrupt Wait Time %0d cycles"
,
BFMA1OOIOI
)
;
BFMA1O001
=
0
;
end
end
BFMA1OOlI
:
begin
BFMA1OI0
<=
BFMA1Ol01
;
BFMA1lO0
<=
BFMA1Il01
;
BFMA1l0l
<=
1
'b
1
;
BFMA1O001
=
0
;
end
BFMA1lIlI
:
begin
BFMA1OI0
<=
BFMA1l011
+
BFMA1I111
;
BFMA1lO0
<=
BFMA1OOOOI
[
BFMA1I111
]
;
BFMA1l0l
<=
1
'b
1
;
BFMA1I111
=
BFMA1I111
+
1
;
if
(
BFMA1I111
>=
BFMA1O111
)
begin
BFMA1O001
=
0
;
end
end
BFMA1IOlI
,
BFMA1lOlI
,
BFMA1OIlI
:
begin
BFMA1OI0
<=
BFMA1Ol01
;
BFMA1OIl
<=
BFMA1Il01
;
BFMA1IIl
<=
BFMA1ll01
;
BFMA1lIl
<=
BFMA1l01
;
BFMA1Oll
<=
1
'b
1
;
if
(
BFMA1I1l
==
1
'b
1
)
begin
BFMA1O001
=
0
;
end
end
BFMA1IIlI
:
begin
if
(
EXT_WAIT
==
1
'b
0
&
BFMA1lI11
==
0
)
begin
if
(
DEBUG
>=
2
)
$display
(
"BFM:Exteral Wait Time %0d cycles"
,
BFMA1OOIOI
)
;
BFMA1O001
=
0
;
end
if
(
BFMA1lI11
>=
1
)
begin
BFMA1lI11
=
BFMA1lI11
-
1
;
end
end
BFMA1IlII
,
BFMA1llII
,
BFMA1l1OI
,
BFMA1OlII
:
begin
BFMA1Oll
<=
1
'b
1
;
BFMA1OIl
<=
BFMA1Il01
;
BFMA1IIl
<=
BFMA1ll01
;
BFMA1lIl
<=
BFMA1l01
;
BFMA1O001
=
0
;
end
BFMA1OOII
:
begin
BFMA1OIl
<=
BFMA1Il01
;
BFMA1IIl
<=
BFMA1ll01
;
BFMA1lIl
<=
BFMA1l01
;
BFMA1l1l
<=
1
'b
1
;
BFMA1Oll
<=
1
'b
0
;
if
(
BFMA1l1l
==
1
'b
1
&
BFMA1llIOI
)
begin
BFMA1l1l
<=
1
'b
0
;
BFMA1O001
=
0
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:GP IO Wait Time %0d cycles"
,
BFMA1OOIOI
)
;
end
end
BFMA1O00I
,
BFMA1I00I
:
begin
case
(
BFMA1lOO1
)
BFMA1Ol10
:
BFMA1O001
=
0
;
BFMA1Il10
:
begin
BFMA1OlO1
=
BFMA1lI
[
1
]
+
BFMA1lI
[
2
]
;
BFMA1I110
=
BFMA1lI
[
3
]
;
BFMA1l110
=
BFMA1lI
[
4
]
%
65536
;
BFMA1IOI1
=
(
(
BFMA1lll1
[
4
]
[
16
]
)
==
1
'b
1
)
;
BFMA1lOI1
=
(
(
BFMA1lll1
[
4
]
[
17
]
)
==
1
'b
1
)
;
BFMA1OII1
=
(
(
BFMA1lll1
[
4
]
[
18
]
)
==
1
'b
1
)
;
BFMA1OOO1
=
BFMA1lI
[
5
]
;
BFMA1IOO1
=
BFMA1lI
[
6
]
;
if
(
~
BFMA1OII1
)
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<
MAX_MEMTEST
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
BFMA1OIO1
[
BFMA1I0I0
]
=
0
;
BFMA1O0O1
=
0
;
BFMA1I0O1
=
0
;
BFMA1l0O1
=
0
;
BFMA1OOI1
=
0
;
BFMA1III1
=
0
;
if
(
BFMA1IO01
==
BFMA1I00I
)
begin
BFMA1OlO1
=
BFMA1lI
[
1
]
;
BFMA1IlO1
=
BFMA1lI
[
2
]
-
BFMA1I110
;
BFMA1I110
=
2
*
BFMA1I110
;
BFMA1OOI1
=
1
;
end
if
(
BFMA1IO01
==
BFMA1O00I
)
begin
$display
(
"BFM:%0d: memtest Started at %0d ns"
,
BFMA1l01
,
$time
)
;
$display
(
"BFM: Address %08x Size %0d Cycles %5d"
,
BFMA1OlO1
,
BFMA1I110
,
BFMA1OOO1
)
;
end
else
begin
$display
(
"BFM:%0d: dual memtest Started at %0d ns"
,
BFMA1l01
,
$time
)
;
$display
(
"BFM: Address %08x %08x Size %0d Cycles %5d"
,
BFMA1OlO1
,
BFMA1IlO1
+
BFMA1I110
/
2
,
BFMA1I110
/
2
,
BFMA1OOO1
)
;
end
case
(
BFMA1l110
)
0
:
begin
end
1
:
$display
(
"BFM: Transfers are APB Byte aligned"
)
;
2
:
$display
(
"BFM: Transfers are APB Half Word aligned"
)
;
3
:
$display
(
"BFM: Transfers are APB Word aligned"
)
;
4
:
$display
(
"BFM: Byte Writes Suppressed"
)
;
default
:
$display
(
"Illegal Align on memtest (FAILURE)"
)
;
endcase
if
(
BFMA1OII1
)
begin
$display
(
"BFM: memtest restarted"
)
;
end
if
(
BFMA1IOI1
)
begin
$display
(
"BFM: Memtest Filling Memory"
)
;
BFMA1lOO1
=
BFMA1I010
;
end
else
if
(
BFMA1OOO1
>
0
)
begin
$display
(
"BFM: Memtest Random Read Writes"
)
;
BFMA1lOO1
=
BFMA1ll10
;
end
else
if
(
BFMA1lOI1
)
begin
$display
(
"BFM: Memtest Verifying Memory Content"
)
;
BFMA1lOO1
=
BFMA1l010
;
end
else
begin
BFMA1lOO1
=
BFMA1O010
;
end
end
BFMA1ll10
,
BFMA1I010
,
BFMA1l010
:
begin
if
(
~
(
BFMA1I101
|
BFMA1I001
)
)
begin
case
(
BFMA1lOO1
)
BFMA1ll10
:
begin
BFMA1IOO1
=
BFMA1lIl0
(
BFMA1IOO1
)
;
BFMA1IIO1
=
BFMA1O1l0
(
BFMA1IOO1
,
BFMA1I110
)
;
BFMA1IOO1
=
BFMA1lIl0
(
BFMA1IOO1
)
;
BFMA1lIO1
=
BFMA1O1l0
(
BFMA1IOO1
,
8
)
;
end
BFMA1I010
:
begin
BFMA1IIO1
=
BFMA1III1
;
BFMA1lIO1
=
6
;
end
BFMA1l010
:
begin
BFMA1IIO1
=
BFMA1III1
;
BFMA1lIO1
=
2
;
end
default
:
begin
end
endcase
case
(
BFMA1l110
)
0
:
begin
end
1
:
begin
BFMA1IIO1
=
4
*
(
BFMA1IIO1
/
4
)
;
case
(
BFMA1lIO1
)
0
,
4
:
begin
BFMA1lIO1
=
BFMA1lIO1
;
end
1
,
5
:
begin
BFMA1lIO1
=
BFMA1lIO1
-
1
;
end
2
,
6
:
begin
BFMA1lIO1
=
BFMA1lIO1
-
2
;
end
default
:
begin
end
endcase
end
2
:
begin
BFMA1IIO1
=
4
*
(
BFMA1IIO1
/
4
)
;
case
(
BFMA1lIO1
)
0
,
4
:
begin
BFMA1lIO1
=
BFMA1lIO1
+
1
;
end
1
,
5
:
begin
BFMA1lIO1
=
BFMA1lIO1
;
end
2
,
6
:
begin
BFMA1lIO1
=
BFMA1lIO1
-
1
;
end
default
:
begin
end
endcase
end
3
:
begin
BFMA1IIO1
=
4
*
(
BFMA1IIO1
/
4
)
;
case
(
BFMA1lIO1
)
0
,
4
:
begin
BFMA1lIO1
=
BFMA1lIO1
+
2
;
end
1
,
5
:
begin
BFMA1lIO1
=
BFMA1lIO1
+
1
;
end
2
,
6
:
begin
BFMA1lIO1
=
BFMA1lIO1
;
end
default
:
begin
end
endcase
end
4
:
begin
case
(
BFMA1lIO1
)
4
:
begin
BFMA1IIO1
=
2
*
(
BFMA1IIO1
/
2
)
;
BFMA1lIO1
=
5
;
end
default
:
begin
end
endcase
end
default
:
begin
end
endcase
if
(
BFMA1lIO1
>=
0
&
BFMA1lIO1
<=
2
)
begin
case
(
BFMA1lIO1
)
0
:
begin
BFMA1lI01
=
3
'b
000
;
BFMA1IIO1
=
BFMA1IIO1
;
BFMA1llO1
=
(
BFMA1OIO1
[
BFMA1IIO1
+
0
]
>=
256
)
;
end
1
:
begin
BFMA1lI01
=
3
'b
001
;
BFMA1IIO1
=
2
*
(
BFMA1IIO1
/
2
)
;
BFMA1llO1
=
(
(
BFMA1OIO1
[
BFMA1IIO1
+
0
]
>=
256
)
&
(
BFMA1OIO1
[
BFMA1IIO1
+
1
]
>=
256
)
)
;
end
2
:
begin
BFMA1lI01
=
3
'b
010
;
BFMA1IIO1
=
4
*
(
BFMA1IIO1
/
4
)
;
BFMA1llO1
=
(
(
BFMA1OIO1
[
BFMA1IIO1
+
0
]
>=
256
)
&
(
BFMA1OIO1
[
BFMA1IIO1
+
1
]
>=
256
)
&
(
BFMA1OIO1
[
BFMA1IIO1
+
2
]
>=
256
)
&
(
BFMA1OIO1
[
BFMA1IIO1
+
3
]
>=
256
)
)
;
end
default
:
begin
end
endcase
if
(
BFMA1llO1
)
begin
BFMA1I001
=
1
;
BFMA1O0O1
=
BFMA1O0O1
+
1
;
if
(
BFMA1OOI1
==
1
&
BFMA1IIO1
>=
BFMA1I110
/
2
)
begin
BFMA1Ol01
=
BFMA1IlO1
+
BFMA1IIO1
;
end
else
begin
BFMA1Ol01
=
BFMA1OlO1
+
BFMA1IIO1
;
end
case
(
BFMA1lIO1
)
0
:
begin
BFMA1Il01
=
{
BFMA1lI1
[
31
:
8
]
,
BFMA1OIO1
[
BFMA1IIO1
+
0
]
[
7
:
0
]
}
;
end
1
:
begin
BFMA1Il01
=
{
BFMA1lI1
[
31
:
16
]
,
BFMA1OIO1
[
BFMA1IIO1
+
1
]
[
7
:
0
]
,
BFMA1OIO1
[
BFMA1IIO1
+
0
]
[
7
:
0
]
}
;
end
2
:
begin
BFMA1Il01
=
{
BFMA1OIO1
[
BFMA1IIO1
+
3
]
[
7
:
0
]
,
BFMA1OIO1
[
BFMA1IIO1
+
2
]
[
7
:
0
]
,
BFMA1OIO1
[
BFMA1IIO1
+
1
]
[
7
:
0
]
,
BFMA1OIO1
[
BFMA1IIO1
+
0
]
[
7
:
0
]
}
;
end
default
:
begin
BFMA1Il01
=
BFMA1lI1
[
31
:
0
]
;
end
endcase
BFMA1ll01
=
{
32
{
1
'b
1
}
}
;
end
else
begin
BFMA1lIO1
=
BFMA1lIO1
+
4
;
if
(
BFMA1lIO1
==
4
&
BFMA1l110
==
4
)
begin
BFMA1lIO1
=
5
;
end
end
end
if
(
BFMA1lIO1
>=
4
&
BFMA1lIO1
<=
6
)
begin
BFMA1I101
=
1
;
BFMA1I0O1
=
BFMA1I0O1
+
1
;
BFMA1IOO1
=
BFMA1lIl0
(
BFMA1IOO1
)
;
BFMA1Il01
=
BFMA1IOO1
;
case
(
BFMA1lIO1
)
4
:
begin
BFMA1lI01
=
3
'b
000
;
BFMA1IIO1
=
BFMA1IIO1
;
BFMA1OIO1
[
BFMA1IIO1
+
0
]
=
256
+
BFMA1Il01
[
7
:
0
]
;
end
5
:
begin
BFMA1lI01
=
3
'b
001
;
BFMA1IIO1
=
2
*
(
BFMA1IIO1
/
2
)
;
BFMA1OIO1
[
BFMA1IIO1
+
0
]
=
256
+
BFMA1Il01
[
7
:
0
]
;
BFMA1OIO1
[
BFMA1IIO1
+
1
]
=
256
+
BFMA1Il01
[
15
:
8
]
;
end
6
:
begin
BFMA1lI01
=
3
'b
010
;
BFMA1IIO1
=
4
*
(
BFMA1IIO1
/
4
)
;
BFMA1OIO1
[
BFMA1IIO1
+
0
]
=
256
+
BFMA1Il01
[
7
:
0
]
;
BFMA1OIO1
[
BFMA1IIO1
+
1
]
=
256
+
BFMA1Il01
[
15
:
8
]
;
BFMA1OIO1
[
BFMA1IIO1
+
2
]
=
256
+
BFMA1Il01
[
23
:
16
]
;
BFMA1OIO1
[
BFMA1IIO1
+
3
]
=
256
+
BFMA1Il01
[
31
:
24
]
;
end
default
:
begin
end
endcase
if
(
BFMA1OOI1
==
1
&
BFMA1IIO1
>=
BFMA1I110
/
2
)
begin
BFMA1Ol01
=
BFMA1IlO1
+
BFMA1IIO1
;
end
else
begin
BFMA1Ol01
=
BFMA1OlO1
+
BFMA1IIO1
;
end
end
if
(
BFMA1lIO1
==
3
|
BFMA1lIO1
==
7
)
begin
BFMA1l0O1
=
BFMA1l0O1
+
1
;
end
BFMA1III1
=
BFMA1III1
+
4
;
case
(
BFMA1lOO1
)
BFMA1ll10
:
begin
if
(
BFMA1OOO1
>
0
)
begin
BFMA1OOO1
=
BFMA1OOO1
-
1
;
end
else
if
(
BFMA1lOI1
)
begin
BFMA1III1
=
0
;
BFMA1lOO1
=
BFMA1l010
;
$display
(
"BFM: Memtest Verifying Memory Content"
)
;
end
else
begin
BFMA1lOO1
=
BFMA1O010
;
end
end
BFMA1I010
:
begin
if
(
BFMA1III1
>=
BFMA1I110
)
begin
if
(
BFMA1OOO1
==
0
)
begin
if
(
BFMA1lOI1
)
begin
BFMA1III1
=
0
;
BFMA1lOO1
=
BFMA1l010
;
$display
(
"BFM: Memtest Verifying Memory Content"
)
;
end
else
begin
BFMA1lOO1
=
BFMA1O010
;
end
end
else
begin
BFMA1lOO1
=
BFMA1ll10
;
$display
(
"BFM: Memtest Random Read Writes"
)
;
end
end
end
BFMA1l010
:
begin
if
(
BFMA1III1
>=
BFMA1I110
)
begin
BFMA1lOO1
=
BFMA1O010
;
end
end
default
:
begin
end
endcase
BFMA1Il11
=
BFMA1II01
;
end
end
BFMA1O010
:
begin
if
(
~
BFMA1IOlOI
)
begin
BFMA1lOO1
=
BFMA1Ol10
;
$display
(
"BFM: bfmtest complete Writes %0d Reads %0d Nops %0d"
,
BFMA1I0O1
,
BFMA1O0O1
,
BFMA1l0O1
)
;
end
end
endcase
end
default
:
begin
end
endcase
end
if
(
BFMA1OO0OI
==
0
)
begin
BFMA1IO0OI
=
0
;
BFMA1OO0OI
=
BFMA1IllOI
;
end
else
begin
BFMA1OO0OI
=
BFMA1OO0OI
-
1
;
BFMA1IO0OI
=
1
;
end
if
(
HREADY
==
1
'b
1
)
begin
BFMA1l0
<=
2
'b
00
;
BFMA1O1
<=
1
'b
0
;
BFMA1lII
<=
1
'b
0
;
BFMA1OlI
<=
1
'b
0
;
BFMA1llI
<=
1
'b
0
;
if
(
BFMA1lII
==
1
'b
1
|
BFMA1OlI
==
1
'b
1
)
begin
BFMA1I0I
<=
1
'b
0
;
end
if
(
BFMA1I101
&
HREADY
==
1
'b
1
)
begin
BFMA1l1
<=
BFMA1Ol01
;
BFMA1O1
<=
1
'b
1
;
BFMA1ll
<=
BFMA1l1IOI
;
BFMA1l0
<=
2
'b
10
;
BFMA1O0
<=
BFMA1O1IOI
;
BFMA1I0
<=
BFMA1I1IOI
;
BFMA1IOI
<=
BFMA1lI01
;
BFMA1l1I
<=
BFMA1l01l
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
BFMA1Il01
,
BFMA1I0lOI
)
;
BFMA1lII
<=
1
'b
1
;
BFMA1O00
<=
BFMA1l01
;
BFMA1I101
=
0
;
end
if
(
BFMA1I001
&
HREADY
==
1
'b
1
)
begin
BFMA1l1
<=
BFMA1Ol01
;
BFMA1O1
<=
1
'b
0
;
BFMA1ll
<=
BFMA1l1IOI
;
BFMA1l0
<=
2
'b
10
;
BFMA1O0
<=
BFMA1O1IOI
;
BFMA1I0
<=
BFMA1I1IOI
;
BFMA1IOI
<=
BFMA1lI01
;
BFMA1O1I
<=
BFMA1l01l
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
BFMA1Il01
,
BFMA1I0lOI
)
;
BFMA1I1I
<=
BFMA1OIO0
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
BFMA1ll01
,
BFMA1I0lOI
)
;
BFMA1O00
<=
BFMA1l01
;
BFMA1OlI
<=
1
'b
1
;
BFMA1I0I
<=
1
'b
1
;
BFMA1I001
=
0
;
end
if
(
BFMA1IO11
&
HREADY
==
1
'b
1
)
begin
BFMA1l1
<=
BFMA1Ol01
;
BFMA1O1
<=
BFMA1I00OI
;
BFMA1ll
<=
BFMA1I10OI
;
BFMA1l0
<=
BFMA1l00OI
;
BFMA1O0
<=
BFMA1l10OI
;
BFMA1I0
<=
BFMA1O10OI
;
BFMA1IOI
<=
BFMA1lI01
;
BFMA1l1I
<=
BFMA1l01l
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
BFMA1Il01
,
BFMA1I0lOI
)
;
BFMA1lII
<=
1
'b
1
;
BFMA1O00
<=
BFMA1l01
;
BFMA1IO11
=
0
;
end
if
(
BFMA1l101
&
HREADY
==
1
'b
1
)
begin
BFMA1l1
<=
BFMA1Ol01
;
BFMA1O1
<=
1
'b
0
;
BFMA1ll
<=
BFMA1l1IOI
;
BFMA1O0
<=
BFMA1O1IOI
;
BFMA1I0
<=
BFMA1I1IOI
;
BFMA1IOI
<=
BFMA1lI01
;
BFMA1O1I
<=
BFMA1l01l
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
BFMA1Il01
,
BFMA1I0lOI
)
;
BFMA1I1I
<=
BFMA1OIO0
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
BFMA1ll01
,
BFMA1I0lOI
)
;
BFMA1O00
<=
BFMA1l01
;
if
(
BFMA1OlI
==
1
'b
1
|
BFMA1IlI
==
1
'b
1
)
begin
BFMA1l0
<=
2
'b
00
;
end
else
begin
BFMA1l0
<=
2
'b
10
;
BFMA1OlI
<=
1
'b
1
;
BFMA1llI
<=
1
'b
1
;
end
if
(
BFMA1O0I
==
1
'b
1
&
BFMA1OlIOI
)
begin
BFMA1l101
=
0
;
end
end
if
(
BFMA1l001
&
HREADY
==
1
'b
1
)
begin
BFMA1l1
<=
BFMA1Ol01
;
BFMA1O1
<=
1
'b
1
;
BFMA1ll
<=
BFMA1l1IOI
;
BFMA1O0
<=
BFMA1O1IOI
;
BFMA1I0
<=
BFMA1I1IOI
;
BFMA1IOI
<=
BFMA1lI01
;
BFMA1O00
<=
BFMA1l01
;
if
(
BFMA1IO0OI
)
begin
BFMA1l0
<=
2
'b
01
;
end
else
begin
BFMA1l1I
<=
BFMA1l01l
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
to_slv32
(
BFMA1OOOOI
[
BFMA1I111
]
)
,
BFMA1I0lOI
)
;
BFMA1lII
<=
1
'b
1
;
if
(
BFMA1I111
==
0
|
BFMA1l1l1
==
3
|
bound1k
(
BFMA1O0lOI
,
BFMA1Ol01
)
)
begin
BFMA1l0
<=
2
'b
10
;
end
else
begin
BFMA1l0
<=
2
'b
11
;
end
BFMA1Ol01
=
BFMA1Ol01
+
BFMA1l111
;
BFMA1I111
=
BFMA1I111
+
1
;
if
(
BFMA1I111
==
BFMA1O111
)
begin
BFMA1l001
=
0
;
end
end
end
if
(
BFMA1O101
&
HREADY
==
1
'b
1
)
begin
BFMA1l1
<=
BFMA1Ol01
;
BFMA1O1
<=
1
'b
0
;
BFMA1ll
<=
BFMA1l1IOI
;
BFMA1O0
<=
BFMA1O1IOI
;
BFMA1I0
<=
BFMA1I1IOI
;
BFMA1IOI
<=
BFMA1lI01
;
BFMA1O00
<=
BFMA1l01
;
if
(
BFMA1IO0OI
)
begin
BFMA1l0
<=
2
'b
01
;
end
else
begin
BFMA1O1I
<=
BFMA1l01l
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
to_slv32
(
BFMA1OOOOI
[
BFMA1I111
]
)
,
BFMA1I0lOI
)
;
BFMA1I1I
<=
BFMA1OIO0
(
BFMA1lI01
,
BFMA1Ol01
[
1
:
0
]
,
BFMA1ll01
,
BFMA1I0lOI
)
;
BFMA1OlI
<=
1
'b
1
;
BFMA1I0I
<=
1
'b
1
;
if
(
BFMA1I111
==
0
|
BFMA1l1l1
==
3
|
bound1k
(
BFMA1O0lOI
,
BFMA1Ol01
)
)
begin
BFMA1l0
<=
2
'b
10
;
end
else
begin
BFMA1l0
<=
2
'b
11
;
end
BFMA1Ol01
=
BFMA1Ol01
+
BFMA1l111
;
BFMA1I111
=
BFMA1I111
+
1
;
if
(
BFMA1I111
==
BFMA1O111
)
begin
BFMA1O101
=
0
;
end
end
end
end
if
(
HREADY
==
1
'b
1
)
begin
BFMA1III
<=
BFMA1lII
;
BFMA1IlI
<=
BFMA1OlI
;
BFMA1O0I
<=
BFMA1llI
;
BFMA1l0I
<=
BFMA1I0I
;
BFMA1OOl
<=
BFMA1O1I
;
BFMA1IOl
<=
BFMA1I1I
;
BFMA1I00
<=
BFMA1O00
;
BFMA1OOI
<=
BFMA1l1
;
BFMA1lOI
<=
BFMA1IOI
;
end
BFMA1I1l
<=
BFMA1O1l
;
BFMA1II0
<=
BFMA1OI0
;
BFMA1Ill
<=
BFMA1Oll
;
BFMA1lll
<=
BFMA1OIl
;
BFMA1O0l
<=
BFMA1IIl
;
BFMA1I0l
<=
BFMA1lIl
;
if
(
HREADY
==
1
'b
1
)
begin
if
(
BFMA1lII
==
1
'b
1
)
begin
BFMA1lOl
<=
BFMA1l1I
;
end
else
begin
BFMA1lOl
<=
{
32
{
1
'b
0
}
}
;
end
if
(
BFMA1III
==
1
'b
1
&
DEBUG
>=
3
)
begin
$display
(
"BFM: Data Write %08x %08x"
,
BFMA1OOI
,
BFMA1lOl
)
;
end
if
(
BFMA1lO0OI
&
BFMA1III
==
1
'b
1
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d AW %c %08x %08x"
,
$time
,
BFMA1IlO0
(
BFMA1lOI
)
,
BFMA1OOI
,
BFMA1lOl
)
;
end
end
if
(
BFMA1OO0
==
1
'b
1
&
BFMA1II0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d GW %08x "
,
$time
,
BFMA1O10
)
;
end
if
(
BFMA1l0l
==
1
'b
1
&
BFMA1OI0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d EW %08x %08x"
,
$time
,
BFMA1OI0
,
BFMA1lO0
)
;
end
if
(
HREADY
==
1
'b
1
)
begin
if
(
BFMA1IlI
==
1
'b
1
)
begin
if
(
DEBUG
>=
3
)
begin
if
(
BFMA1IOl
==
BFMA1lI1
)
begin
$display
(
"BFM: Data Read %08x %08x"
,
BFMA1OOI
,
HRDATA
)
;
end
else
begin
$display
(
"BFM: Data Read %08x %08x MASK:%08x"
,
BFMA1OOI
,
HRDATA
,
BFMA1IOl
)
;
end
end
if
(
BFMA1lO0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d AR %c %08x %08x"
,
$time
,
BFMA1IlO0
(
BFMA1lOI
)
,
BFMA1OOI
,
HRDATA
)
;
end
if
(
BFMA1OOlOI
>=
0
)
begin
BFMA1ll1
[
BFMA1OOlOI
]
=
BFMA1O01l
(
BFMA1IIO0
(
BFMA1lOI
,
BFMA1OOI
[
1
:
0
]
,
HRDATA
,
BFMA1I0lOI
)
)
;
end
if
(
BFMA1l0I
==
1
'b
1
&
~
BFMA1OlIOI
)
begin
BFMA1II10
=
BFMA1II10
+
1
;
$display
(
"ERROR: AHB Data Read Comparison failed Addr:%08x Got:%08x EXP:%08x (MASK:%08x)"
,
BFMA1OOI
,
HRDATA
,
BFMA1OOl
,
BFMA1IOl
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1I00
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1I00
,
BFMA1IIlOI
)
)
;
$display
(
"BFM Data Compare Error (ERROR)"
)
;
$stop
;
if
(
BFMA1lO0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d ERROR Addr:%08x Got:%08x EXP:%08x (MASK:%08x)"
,
$time
,
BFMA1OOI
,
HRDATA
,
BFMA1OOl
,
BFMA1IOl
)
;
end
end
end
end
if
(
BFMA1l1l
==
1
'b
1
)
begin
if
(
DEBUG
>=
3
)
begin
if
(
BFMA1IIl
==
BFMA1lI1
)
begin
$display
(
"BFM: GP IO Data Read %08x"
,
GP_IN
)
;
end
else
begin
$display
(
"BFM: GP IO Data Read %08x MASK:%08x"
,
GP_IN
,
BFMA1IIl
)
;
end
end
if
(
BFMA1II0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d GR %08x "
,
$time
,
BFMA1OIl
)
;
end
if
(
BFMA1OOlOI
>=
0
)
begin
BFMA1ll1
[
BFMA1OOlOI
]
=
GP_IN
;
end
if
(
BFMA1Oll
==
1
'b
1
&
~
BFMA1llIOI
)
begin
BFMA1II10
=
BFMA1II10
+
1
;
$display
(
"GPIO input not as expected Got:%08x EXP:%08x (MASK:%08x)"
,
GP_IN
,
BFMA1OIl
,
BFMA1IIl
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1lIl
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1lIl
,
BFMA1IIlOI
)
)
;
$display
(
"BFM GPIO Compare Error (ERROR)"
)
;
$stop
;
if
(
BFMA1II0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"ERROR Got:%08x EXP:%08x (MASK:%08x)"
,
GP_IN
,
BFMA1OIl
,
BFMA1IIl
)
;
end
end
end
if
(
BFMA1I1l
==
1
'b
1
)
begin
if
(
DEBUG
>=
3
)
begin
if
(
BFMA1O0l
==
BFMA1lI1
)
begin
$display
(
"BFM: Extention Data Read %08x %08x"
,
BFMA1II0
,
BFMA1IO0
)
;
end
else
begin
$display
(
"BFM: Extention Data Read %08x %08x MASK:%08x"
,
BFMA1II0
,
BFMA1IO0
,
BFMA1O0l
)
;
end
end
if
(
BFMA1OI0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"%05d ER %08x %08x"
,
$time
,
BFMA1II0
,
BFMA1lll
)
;
end
if
(
BFMA1OOlOI
>=
0
)
begin
BFMA1ll1
[
BFMA1OOlOI
]
=
BFMA1O01l
(
BFMA1IO0
)
;
end
if
(
BFMA1Ill
==
1
'b
1
&
~
BFMA1IlIOI
)
begin
BFMA1II10
=
BFMA1II10
+
1
;
$display
(
"ERROR: Extention Data Read Comparison FAILED Got:%08x EXP:%08x (MASK:%08x)"
,
BFMA1IO0
,
BFMA1lll
,
BFMA1O0l
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1I0l
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1I0l
,
BFMA1IIlOI
)
)
;
$display
(
"BFM Extention Data Compare Error (ERROR)"
)
;
$stop
;
if
(
BFMA1OI0OI
)
begin
$fdisplay
(
BFMA1lIl1
,
"ERROR Got:%08x EXP:%08x (MASK:%08x)"
,
BFMA1IO0
,
BFMA1lll
,
BFMA1O0l
)
;
end
end
end
BFMA1OO1OI
=
BFMA1I001
|
BFMA1I101
|
BFMA1l001
|
BFMA1O101
|
BFMA1l101
|
BFMA1IO11
|
to_boolean
(
BFMA1OlI
|
BFMA1lII
|
BFMA1O1l
|
BFMA1l1l
)
|
(
to_boolean
(
(
BFMA1IlI
|
BFMA1III
)
&
~
HREADY
)
)
;
if
(
BFMA1O001
)
begin
case
(
BFMA1IO01
)
BFMA1OI1I
:
begin
if
(
~
BFMA1OO1OI
)
begin
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:checktime was %0d cycles "
,
BFMA1l01
,
BFMA1OOIOI
)
;
if
(
BFMA1OOIOI
<
BFMA1lI
[
1
]
|
BFMA1OOIOI
>
BFMA1lI
[
2
]
)
begin
$display
(
"BFM: ERROR checktime %0d %0d Actual %0d"
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
BFMA1OOIOI
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1I00
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1I00
,
BFMA1IIlOI
)
)
;
$display
(
"BFM checktime failure (ERROR)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
$stop
;
end
BFMA1O001
=
0
;
BFMA1I1O1
=
BFMA1OOIOI
;
end
end
BFMA1Ol1I
:
begin
if
(
~
BFMA1OO1OI
)
begin
BFMA1l1O1
=
BFMA1l1O1
-
1
;
if
(
DEBUG
>=
2
)
$display
(
"BFM:%0d:checktimer was %0d cycles "
,
BFMA1l01
,
BFMA1l1O1
)
;
if
(
BFMA1l1O1
<
BFMA1lI
[
1
]
|
BFMA1l1O1
>
BFMA1lI
[
2
]
)
begin
$display
(
"BFM: ERROR checktimer %0d %0d Actual %0d"
,
BFMA1lI
[
1
]
,
BFMA1lI
[
2
]
,
BFMA1l1O1
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1I00
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1I00
,
BFMA1IIlOI
)
)
;
$display
(
"BFM checktimer failure (ERROR)"
)
;
BFMA1II10
=
BFMA1II10
+
1
;
$stop
;
end
BFMA1O001
=
0
;
BFMA1O1O1
=
BFMA1l1O1
;
end
end
default
:
begin
end
endcase
end
if
(
BFMA1l0lOI
)
begin
if
(
BFMA1Il11
>
0
)
begin
BFMA1Il11
=
BFMA1Il11
-
1
;
end
else
begin
BFMA1Il11
=
BFMA1II01
;
$display
(
"BFM Command Timeout Occured"
)
;
$display
(
" Stimulus file %0s Line No %0d"
,
BFMA1lOlOI
[
BFMA1OIl0
(
BFMA1I00
,
BFMA1IIlOI
)
]
,
BFMA1l1I0
(
BFMA1I00
,
BFMA1IIlOI
)
)
;
if
(
~
BFMA1lOOOI
)
$display
(
"BFM Command timeout occured (ERROR)"
)
;
if
(
BFMA1lOOOI
)
$display
(
"BFM Completed and timeout occured (ERROR)"
)
;
$stop
;
end
end
else
begin
BFMA1Il11
=
BFMA1II01
;
end
if
(
BFMA1II10
>
0
)
begin
BFMA1OO1
<=
1
'b
1
;
end
if
(
BFMA1O001
|
BFMA1I001
|
BFMA1I101
|
BFMA1l001
|
BFMA1O101
|
BFMA1l101
|
BFMA1IO11
|
(
(
BFMA1OO11
|
BFMA1lllOI
)
&
BFMA1IOlOI
)
)
begin
BFMA1OI11
=
1
;
end
else
begin
BFMA1OO11
=
0
;
if
(
~
BFMA1lOOOI
)
begin
BFMA1OI11
=
0
;
end
BFMA1O000
=
BFMA1O000
+
BFMA1OI01
;
BFMA1OI01
=
0
;
if
(
OPMODE
>
0
)
begin
if
(
BFMA1O1lOI
|
BFMA1lOOOI
)
begin
BFMA1l0lOI
=
0
;
BFMA1OI11
=
0
;
end
end
end
if
(
BFMA1l10
==
1
'b
0
&
OPMODE
==
0
&
BFMA1lOOOI
&
~
BFMA1IOlOI
)
begin
$display
(
"###########################################################"
)
;
$display
(
" "
)
;
if
(
BFMA1II10
==
0
)
begin
$display
(
"BFM Simulation Complete - %0d Instructions - NO ERRORS"
,
BFMA1IOIOI
)
;
end
else
begin
$display
(
"BFM Simulation Complete - %0d Instructions - %0d ERRORS OCCURED"
,
BFMA1IOIOI
,
BFMA1II10
)
;
end
$display
(
" "
)
;
$display
(
"###########################################################"
)
;
$display
(
" "
)
;
BFMA1l10
<=
1
'b
1
;
BFMA1OI11
=
1
;
BFMA1l0lOI
=
0
;
if
(
BFMA1O11
)
begin
$fflush
(
BFMA1lIl1
)
;
$fclose
(
BFMA1lIl1
)
;
end
if
(
BFMA1l1lOI
==
1
)
$stop
;
if
(
BFMA1l1lOI
==
2
)
$finish
;
end
CON_BUSY
<=
(
BFMA1l0lOI
|
BFMA1IOlOI
)
;
INSTR_OUT
<=
to_slv32
(
BFMA1O000
)
;
end
end
assign
#
TPD
GP_OUT
=
BFMA1O10
;
assign
#
TPD
EXT_WR
=
BFMA1l0l
;
assign
#
TPD
EXT_RD
=
BFMA1O1l
;
assign
#
TPD
EXT_ADDR
=
BFMA1OI0
;
assign
#
TPD
EXT_DATA
=
(
BFMA1l0l
==
1
'b
1
)
?
BFMA1lO0
:
{
32
{
1
'b
z
}
}
;
assign
BFMA1IO0
=
EXT_DATA
;
always
@
(
BFMA1l1
)
begin
begin
:
BFMA1l0OII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
15
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OII
[
BFMA1I0I0
]
<=
(
BFMA1l1
[
31
:
28
]
==
BFMA1I0I0
)
;
end
end
end
assign
HCLK
=
(
BFMA1IO1
)
?
1
'b
x
:
(
SYSCLK
|
BFMA1l00
)
;
assign
PCLK
=
(
BFMA1IO1
)
?
1
'b
x
:
(
SYSCLK
|
BFMA1l00
)
;
assign
#
TPD
HRESETN
=
(
BFMA1lO1
)
?
1
'b
x
:
BFMA1Il
;
assign
#
TPD
HADDR
=
(
BFMA1OI1
)
?
{
32
{
1
'b
x
}
}
:
BFMA1l1
;
assign
#
TPD
HWDATA
=
(
BFMA1II1
)
?
{
32
{
1
'b
x
}
}
:
BFMA1lOl
;
assign
#
TPD
HBURST
=
(
BFMA1OI1
)
?
{
3
{
1
'b
x
}
}
:
BFMA1ll
;
assign
#
TPD
HMASTLOCK
=
(
BFMA1OI1
)
?
1
'b
x
:
BFMA1O0
;
assign
#
TPD
HPROT
=
(
BFMA1OI1
)
?
{
4
{
1
'b
x
}
}
:
BFMA1I0
;
assign
#
TPD
HSIZE
=
(
BFMA1OI1
)
?
{
3
{
1
'b
x
}
}
:
BFMA1IOI
;
assign
#
TPD
HTRANS
=
(
BFMA1OI1
)
?
{
2
{
1
'b
x
}
}
:
BFMA1l0
;
assign
#
TPD
HWRITE
=
(
BFMA1OI1
)
?
1
'b
x
:
BFMA1O1
;
assign
#
TPD
HSEL
=
(
BFMA1OI1
)
?
{
16
{
1
'b
x
}
}
:
BFMA1OII
;
assign
#
TPD
CON_DATA
=
(
BFMA1Il0
==
1
'b
1
)
?
BFMA1Ol0
:
{
32
{
1
'b
z
}
}
;
assign
BFMA1lI0
=
CON_DATA
;
assign
#
TPD
FINISHED
=
BFMA1l10
;
assign
#
TPD
FAILED
=
BFMA1OO1
;
endmodule
|
module fcounter(clk, sig, f);
/*
This module implements a frequency counter. It has the same module signature as counter.v, which implements a period counter with inversion to give the frequency counter.
The frequency counter counts edges of the RF signal input in a register, and gates this counting with a fixed time period as measured by counting of clock edges. The +- count error of this scheme is associated with the RF signal, as opposed to the clock, so when the RF signal is slower than the clock, the period counter will have a smaller error for the same measurement time (i.e. a longer measurement time would be needed with the frequency counter, so that the error is reduced by averaging, in order to achieve the same error from the period counter).
PARAMETER SELECTION:
F_rf = #cnts/time period +-1 / (time period)
=> error= +- 1/time period = 500 Hz = acceptable error
=> time period = 1/500 Hz = 0.002 s
With 4 MHz clock => 2E-3*4E6=8E3 clock posedges count in time period.
Ted Golfinopoulos, 25 Oct 2011
*/
`define CLK_COUNTER_SIZE 14 //Number of bits in clock edge counter.
`define SIG_COUNTER_SIZE 10 //Number of bits in signal edge counter.
input clk, sig;
output reg [13:0] f; //Allows frequency count up to 819.2 kHz.
reg [13:0] n_clk; //Counter for clock positive edges.
reg [9:0] n_sig; //Counter for signal positive edges.
reg reset; //Reset flag set every NUM_CNTS_AVG clock cycles to re-compute frequency and restart counters.
parameter F_CLK=40000; //Clock frequency in HUNDREDS OF Hz.
parameter ERR=5; //Allowable frequency measurement error, HUNDREDS OF Hz.
parameter NUM_CNTS_AVG=F_CLK/ERR; //Number of clock edge counts required such that averaging reduces +-1 count error to acceptable levels.
parameter F_SCALE=ERR; //Scale rf signal counter by this amount to give a frequency measurement in HUNDREDS OF Hz.
parameter N_SIG_MAX=`SIG_COUNTER_SIZE'b1111111111; //Maximum value sig edge counter can reach.
initial begin
reset=1'b1; //Initialize reset signal counter flag low so that counting only starts when gate is actually opened.
n_clk=`CLK_COUNTER_SIZE'b0; //Initialize clock counter.
n_sig=`SIG_COUNTER_SIZE'b0; //Initialize signal counter.
end
always @(posedge clk) begin
//As for period counter, but swap gate and registered count, n_sig and n_clk, so that now, n_clk is the gate.
//n_sig is not counted when n_clk is between 0 and 1.
//The gate is open between n_clk Edges 1 and (NUM_CNTS_AVG+1) (which is also Edge 0), corresponding to
// NUM_CNTS_AVG clock intervals.
//Then f=(n_sig+-1)/(tau_clk*NUM_CNTS_AVG) = (n_sig+-1)*f_clk/NUM_CNTS_AVG => error = +-1*f_clk/NUM_CNTS_AVG.
if(n_clk>=NUM_CNTS_AVG) begin //Close frequency counter gate. Subtract one from count because actually start counting signal edges at n_clk=1.
f=F_SCALE*n_sig; //Compute frequency.
reset = 1'b1; //Set flag to re-compute the frequency and restart the frequency counter.
n_clk = 1'b0; //Restart clock positive edge counter.
end else begin
//Keep reset flag low (turn off on next clock cycle).
reset = 1'b0;
n_clk=n_clk+`CLK_COUNTER_SIZE'b1; //Increment clock cycle counter.
end
end
always @(posedge sig or posedge reset) begin
if(reset==1) begin
n_sig=`SIG_COUNTER_SIZE'b0; //Reset RF signal counter.
end else if(n_sig<=N_SIG_MAX) begin //Handle overflow gracefully - stop counting when register is saturated.
n_sig=n_sig+`SIG_COUNTER_SIZE'b1; //Increment frequency counter.
end
end
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 5
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_top,Vivado 2015.1" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_us_0,axi_dwidth_converter_v2_1_top,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_us_0,axi_dwidth_converter_v2_1_top,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=1,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=0,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_us_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
axi_dwidth_converter_v2_1_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(1),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(0),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(32'H00000000),
.s_axi_arlen(4'H0),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(2'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(3'H0),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_arvalid(1'H0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'H0),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_arvalid(),
.m_axi_arready(1'H0),
.m_axi_rdata(64'H0000000000000000),
.m_axi_rresp(2'H0),
.m_axi_rlast(1'H1),
.m_axi_rvalid(1'H0),
.m_axi_rready()
);
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module controls VGA output for Altera's DE1 and DE2 Boards. *
* *
******************************************************************************/
module amm_master_qsys_with_pcie_video_vga_controller_0 (
// Inputs
clk,
reset,
data,
startofpacket,
endofpacket,
empty,
valid,
// Bidirectionals
// Outputs
ready,
VGA_CLK,
VGA_BLANK,
VGA_SYNC,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 7;
parameter DW = 29;
parameter R_UI = 29;
parameter R_LI = 22;
parameter G_UI = 19;
parameter G_LI = 12;
parameter B_UI = 9;
parameter B_LI = 2;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter LW = 10;
parameter LINE_COUNTER_INCREMENT = 10'h001;
parameter PW = 10;
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] data;
input startofpacket;
input endofpacket;
input [ 1: 0] empty;
input valid;
// Bidirectionals
// Outputs
output ready;
output VGA_CLK;
output reg VGA_BLANK;
output reg VGA_SYNC;
output reg VGA_HS;
output reg VGA_VS;
output reg [CW: 0] VGA_R;
output reg [CW: 0] VGA_G;
output reg [CW: 0] VGA_B;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam STATE_0_SYNC_FRAME = 1'b0,
STATE_1_DISPLAY = 1'b1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_enable;
wire end_of_active_frame;
wire vga_blank_sync;
wire vga_c_sync;
wire vga_h_sync;
wire vga_v_sync;
wire vga_data_enable;
wire [CW: 0] vga_red;
wire [CW: 0] vga_green;
wire [CW: 0] vga_blue;
wire [CW: 0] vga_color_data;
// Internal Registers
reg [ 3: 0] color_select; // Use for the TRDB_LCM
// State Machine Registers
reg ns_mode;
reg s_mode;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk) // sync reset
begin
if (reset == 1'b1)
s_mode <= STATE_0_SYNC_FRAME;
else
s_mode <= ns_mode;
end
always @(*)
begin
// Defaults
ns_mode = STATE_0_SYNC_FRAME;
case (s_mode)
STATE_0_SYNC_FRAME:
begin
if (valid & startofpacket)
ns_mode = STATE_1_DISPLAY;
else
ns_mode = STATE_0_SYNC_FRAME;
end
STATE_1_DISPLAY:
begin
if (end_of_active_frame)
ns_mode = STATE_0_SYNC_FRAME;
else
ns_mode = STATE_1_DISPLAY;
end
default:
begin
ns_mode = STATE_0_SYNC_FRAME;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
VGA_BLANK <= vga_blank_sync;
VGA_SYNC <= 1'b0;
VGA_HS <= vga_h_sync;
VGA_VS <= vga_v_sync;
VGA_R <= vga_red;
VGA_G <= vga_green;
VGA_B <= vga_blue;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
color_select <= 4'h1;
else if (s_mode == STATE_0_SYNC_FRAME)
color_select <= 4'h1;
else if (~read_enable)
color_select <= {color_select[2:0], color_select[3]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ready =
(s_mode == STATE_0_SYNC_FRAME) ?
valid & ~startofpacket :
read_enable;
assign VGA_CLK = ~clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_avalon_video_vga_timing VGA_Timing (
// Inputs
.clk (clk),
.reset (reset),
.red_to_vga_display (data[R_UI:R_LI]),
.green_to_vga_display (data[G_UI:G_LI]),
.blue_to_vga_display (data[B_UI:B_LI]),
.color_select (color_select),
// .data_valid (1'b1),
// Bidirectionals
// Outputs
.read_enable (read_enable),
.end_of_active_frame (end_of_active_frame),
.end_of_frame (), // (end_of_frame),
// dac pins
.vga_blank (vga_blank_sync),
.vga_c_sync (vga_c_sync),
.vga_h_sync (vga_h_sync),
.vga_v_sync (vga_v_sync),
.vga_data_enable (vga_data_enable),
.vga_red (vga_red),
.vga_green (vga_green),
.vga_blue (vga_blue),
.vga_color_data (vga_color_data)
);
defparam
VGA_Timing.CW = CW,
VGA_Timing.H_ACTIVE = H_ACTIVE,
VGA_Timing.H_FRONT_PORCH = H_FRONT_PORCH,
VGA_Timing.H_SYNC = H_SYNC,
VGA_Timing.H_BACK_PORCH = H_BACK_PORCH,
VGA_Timing.H_TOTAL = H_TOTAL,
VGA_Timing.V_ACTIVE = V_ACTIVE,
VGA_Timing.V_FRONT_PORCH = V_FRONT_PORCH,
VGA_Timing.V_SYNC = V_SYNC,
VGA_Timing.V_BACK_PORCH = V_BACK_PORCH,
VGA_Timing.V_TOTAL = V_TOTAL,
VGA_Timing.LW = LW,
VGA_Timing.LINE_COUNTER_INCREMENT = LINE_COUNTER_INCREMENT,
VGA_Timing.PW = PW,
VGA_Timing.PIXEL_COUNTER_INCREMENT = PIXEL_COUNTER_INCREMENT;
endmodule
|
// bsg_clk_gen_osc
//
// new settings are delivered via bsg_tag_i
//
// the clock is designed to be atomically updated
// between any of its values without glitching.
//
// the order of components is:
//
// ADT, CDT, FDT --> feedback (and buffer to outside world)
//
// All three stages invert their outputs.
//
// All of the modules have delay circuits that clock their config
// flops right after the signal has passed through. All of them are
// configured to grab the new value after a negedge enters the beginning of
// of the ADT, but of course since the signal is inverted at each stage
// ADT and FDT do it on posege and CDT does it on negedge.
//
// We employ a MUXI4 that is part of the standard cell library
// that we verify to be glitch-free using spice simulation (presumably because it is based on a
// t-gate design). If the MUXI4 were made out of AND-OR circuits, care
// would have to be taken to make sure that the transitions occur when
// either all inputs are 0 or 1 to the MUXI4, depending on the implementation.
// For example, if the mux is AOI, triggered on negedge edge of input clock would
// be okay. Fortunately, we don't have to worry about this (and confirmed by spice.)
//
// We have verified this in TSMC 40 by running with sdf annotations.
//
// Gen 2 specific info (starting with 40nm) MBT 5-26-2018
//
// This Gen 2 clock generator has been slight redesigned in order to address the races
// in the gen 1 design that prevented automation.
//
// We use the bsg_tag_client_unsync implementation in order to reduce the load on
// the internally generated clock. Additionally, we separate out the we_r trigger
// signal so that it is explicitly set. This means that to set the frequency
// on average, three packets will need to be sent. First, a packet will be sent
// to set clock configuration bits. Then a packet will be sent to enable the we_r
// signal. Finally a packet will be sent to clear the we_r signal.
// This applies only for the oscillator programming.
//
// The trigger is synchronized inside the ADT; and then the synchronized signal
// is buffered and passed on to the CDT and then to the FDT, mirroring the
// flow of the clock signal through the units.
//
// The goal of this approach is to ensure that a new value is latched into the
// oscillator's configuration registers atomically, and during the first negative
// clock phase after a positive edge.
//
//
// The downsampler uses the normal interface.
//
//
// Gen 1 specific info (for reference)
//
// There is an implicit race between the bsg_tag's output fb_we_r (clocked on
// positive edge of FDT output) and these config flops that cannot be addressed
// in ICC because we cannot explicitly control timing between ICC-managed
// clocks and our internal oscillator clocks.
//
// A final check must be made on the 5 flops inside the adt / cdt / fdt
// to see that async reset drops and data inputs do not come too close
// to the appropriate clock edge. This could be verified via a script that
// processes the SDF file, but for now we pull the test trace up in DVE and
// manually check these points. Typically, the ADT is the closest
// call, where in MAX timing mode, the data changes about 481 ps before the
// positive edge of the flop's clock. With a setup time on the order of
// 261 ps, there is a slack of 220 ps. This path was originally a problem
// and it fixed by sending the clock out to the BTC at the beginning of
// the FDT as opposed to at the end. This gives more time for propagate
// through the ICC-generate clock tree for the BTC.
//
//
//
//
`timescale 1ps/1ps
`include "bsg_clk_gen.vh"
module bsg_clk_gen_osc
import bsg_tag_pkg::bsg_tag_s;
#(parameter num_adgs_p=1)
(
input bsg_tag_s bsg_tag_i
,input bsg_tag_s bsg_tag_trigger_i
,input async_reset_i
,output clk_o
);
wire fb_clk;
wire async_reset_neg = ~async_reset_i;
`declare_bsg_clk_gen_osc_tag_payload_s(num_adgs_p)
bsg_clk_gen_osc_tag_payload_s tag_r_async;
wire tag_trigger_r_async;
wire adt_to_cdt_trigger_lo, cdt_to_fdt_trigger_lo;
// this is a raw interface; and wires will toggle
// as the bits shift in. the wires are also
// unsynchronized with respect to the target domain.
bsg_tag_client_unsync
#(.width_p($bits(bsg_clk_gen_osc_tag_payload_s))
,.harden_p(1)
) btc
(.bsg_tag_i(bsg_tag_i)
,.data_async_r_o(tag_r_async)
);
bsg_tag_client_unsync
#(.width_p(1)
,.harden_p(1)
) btc_trigger
(.bsg_tag_i(bsg_tag_trigger_i)
,.data_async_r_o(tag_trigger_r_async)
);
wire adt_lo, cdt_lo;
wire fb_clk_del;
// this adds some delay in the loop for RTL simulation
// should be ignored in synthesis
assign #4000 fb_clk_del = fb_clk;
bsg_rp_clk_gen_atomic_delay_tuner adt
(.i(fb_clk_del)
,.we_async_i (tag_trigger_r_async )
,.we_inited_i(bsg_tag_trigger_i.en )
,.async_reset_neg_i(async_reset_neg )
,.sel_i(tag_r_async.adg[0] )
,.we_o(adt_to_cdt_trigger_lo )
,.o(adt_lo )
);
// instantatiate CDT (coarse delay tuner)
// this one inverts the output
// captures config state on negative edge of input clock
bsg_rp_clk_gen_coarse_delay_tuner cdt
(.i (adt_lo)
,.we_i (adt_to_cdt_trigger_lo)
,.async_reset_neg_i(async_reset_neg )
,.sel_i (tag_r_async.cdt )
,.we_o (cdt_to_fdt_trigger_lo)
,.o (cdt_lo)
);
// instantiate FDT (fine delay tuner)
// captures config state on positive edge of (inverted) input clk
// non-inverting
bsg_rp_clk_gen_fine_delay_tuner fdt
(.i (cdt_lo)
,.we_i (cdt_to_fdt_trigger_lo)
,.async_reset_neg_i(async_reset_neg)
,.sel_i (tag_r_async.fdt)
,.o (fb_clk) // in the actual critical loop
,.buf_o (clk_o) // outside this module
);
//always @(*)
// $display("%m async_reset_neg=%b fb_clk=%b adg_int=%b fb_tag_r=%b fb_we_r=%b",
// async_reset_neg,fb_clk,adg_int,fb_tag_r,fb_we_r);
endmodule // bsg_clk_gen_osc
`BSG_ABSTRACT_MODULE(bsg_clk_gen_osc)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3_SYMBOL_V
`define SKY130_FD_SC_MS__NAND3_SYMBOL_V
/**
* nand3: 3-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3_SYMBOL_V
|
/******************************************************************************/
/* FPGA Sort for VC707 ArchLab. TOKYO TECH */
/* Version 2014-11-26 */
/******************************************************************************/
`default_nettype none
`include "define.v"
`include "core.v"
/******************************************************************************/
module top_sim;
reg CLK, RST;
wire CLK100M = CLK;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
wire initdone;
wire sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] lcnt;
always @(posedge CLK) lcnt <= (RST) ? 0 : (c.last_phase && c.initdone) ? lcnt + 1 : lcnt;
reg [31:0] cnt0_0, cnt1_0, cnt2_0, cnt3_0, cnt4_0, cnt5_0, cnt6_0, cnt7_0, cnt8_0;
always @(posedge CLK) cnt0_0 <= (RST) ? 0 : (c.phase_a==0 && c.initdone) ? cnt0_0 + 1 : cnt0_0;
always @(posedge CLK) cnt1_0 <= (RST) ? 0 : (c.phase_a==1 && c.initdone) ? cnt1_0 + 1 : cnt1_0;
always @(posedge CLK) cnt2_0 <= (RST) ? 0 : (c.phase_a==2 && c.initdone) ? cnt2_0 + 1 : cnt2_0;
always @(posedge CLK) cnt3_0 <= (RST) ? 0 : (c.phase_a==3 && c.initdone) ? cnt3_0 + 1 : cnt3_0;
always @(posedge CLK) cnt4_0 <= (RST) ? 0 : (c.phase_a==4 && c.initdone) ? cnt4_0 + 1 : cnt4_0;
always @(posedge CLK) cnt5_0 <= (RST) ? 0 : (c.phase_a==5 && c.initdone) ? cnt5_0 + 1 : cnt5_0;
always @(posedge CLK) cnt6_0 <= (RST) ? 0 : (c.phase_a==6 && c.initdone) ? cnt6_0 + 1 : cnt6_0;
always @(posedge CLK) cnt7_0 <= (RST) ? 0 : (c.phase_a==7 && c.initdone) ? cnt7_0 + 1 : cnt7_0;
always @(posedge CLK) cnt8_0 <= (RST) ? 0 : (c.phase_a==8 && c.initdone) ? cnt8_0 + 1 : cnt8_0;
reg [31:0] cnt0_1, cnt1_1, cnt2_1, cnt3_1, cnt4_1, cnt5_1, cnt6_1, cnt7_1, cnt8_1;
always @(posedge CLK) cnt0_1 <= (RST) ? 0 : (c.phase_b==0 && c.initdone) ? cnt0_1 + 1 : cnt0_1;
always @(posedge CLK) cnt1_1 <= (RST) ? 0 : (c.phase_b==1 && c.initdone) ? cnt1_1 + 1 : cnt1_1;
always @(posedge CLK) cnt2_1 <= (RST) ? 0 : (c.phase_b==2 && c.initdone) ? cnt2_1 + 1 : cnt2_1;
always @(posedge CLK) cnt3_1 <= (RST) ? 0 : (c.phase_b==3 && c.initdone) ? cnt3_1 + 1 : cnt3_1;
always @(posedge CLK) cnt4_1 <= (RST) ? 0 : (c.phase_b==4 && c.initdone) ? cnt4_1 + 1 : cnt4_1;
always @(posedge CLK) cnt5_1 <= (RST) ? 0 : (c.phase_b==5 && c.initdone) ? cnt5_1 + 1 : cnt5_1;
always @(posedge CLK) cnt6_1 <= (RST) ? 0 : (c.phase_b==6 && c.initdone) ? cnt6_1 + 1 : cnt6_1;
always @(posedge CLK) cnt7_1 <= (RST) ? 0 : (c.phase_b==7 && c.initdone) ? cnt7_1 + 1 : cnt7_1;
always @(posedge CLK) cnt8_1 <= (RST) ? 0 : (c.phase_b==8 && c.initdone) ? cnt8_1 + 1 : cnt8_1;
generate
if (`INITTYPE=="reverse" || `INITTYPE=="sorted") begin
always @(posedge CLK) begin /// note
if (c.initdone) begin
$write("%d|%d|state(%d)", cnt[19:0], c.last_phase, c.state);
$write("|");
$write("P0%d(%d)|P1%d(%d)|P2%d(%d)|P3%d(%d)",
c.phase_a[2:0], c.pchange_a, c.phase_b[2:0], c.pchange_b,
c.phase_c[2:0], c.pchange_c, c.phase_d[2:0], c.pchange_d);
if (c.F01_deq0) $write("%d", c.F01_dot0); else $write(" ");
if (c.F01_deq1) $write("%d", c.F01_dot1); else $write(" ");
if (c.F01_deq2) $write("%d", c.F01_dot2); else $write(" ");
if (c.F01_deq3) $write("%d", c.F01_dot3); else $write(" ");
if (c.F01_deq4) $write("%d", c.F01_dot4); else $write(" ");
if (c.F01_deq5) $write("%d", c.F01_dot5); else $write(" ");
if (c.F01_deq6) $write("%d", c.F01_dot6); else $write(" ");
if (c.F01_deq7) $write("%d", c.F01_dot7); else $write(" ");
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if(c.sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("last(%1d): %d cycles\n", `LAST_PHASE, lcnt);
$write("phase0: %d %d cycles\n", cnt0_0, cnt0_1);
$write("phase1: %d %d cycles\n", cnt1_0, cnt1_1);
$write("phase2: %d %d cycles\n", cnt2_0, cnt2_1);
$write("phase3: %d %d cycles\n", cnt3_0, cnt3_1);
$write("phase4: %d %d cycles\n", cnt4_0, cnt4_1);
$write("phase5: %d %d cycles\n", cnt5_0, cnt5_1);
$write("phase6: %d %d cycles\n", cnt6_0, cnt6_1);
$write("phase7: %d %d cycles\n", cnt7_0, cnt7_1);
$write("phase8: %d %d cycles\n", cnt8_0, cnt8_1);
$write("Sorting finished!\n");
$finish();
end
end
end else if (`INITTYPE == "xorshift") begin
integer fp;
initial begin
fp = $fopen("test.txt", "w");
end
always @(posedge CLK) begin /// note
if (c.last_phase && c.F01_deq0) begin
$write("%08x ", c.F01_dot0);
$fwrite(fp, "%08x ", c.F01_dot0);
$fflush();
end
if (c.sortdone) begin
$fclose(fp);
$finish();
end
end
end
endgenerate
/***** DRAM Controller & DRAM Instantiation *****/
/**********************************************************************************************/
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
wire ERROR;
/***** Core Module Instantiation *****/
/**********************************************************************************************/
CORE c(CLK100M, RST, initdone, sortdone,
d_busy, d_din, d_w, d_dout, d_douten, d_req, d_initadr, d_blocks, ERROR);
endmodule
/**************************************************************************************************/
/**************************************************************************************************/
module DRAM (input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
// app_wdf_data <= D_DIN;
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:42:36 12/10/2012
// Design Name: top
// Module Name: C:/Documents and Settings/SPItoUART_Loopback/tb.v
// Project Name: SPItoUART_Loopback
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb;
// Inputs
reg rxd;
reg rst;
reg clk;
// Outputs
wire txd;
// Instantiate the Unit Under Test (UUT)
top uut (
.txd(txd),
.rxd(rxd),
.rst(rst),
.clk(clk)
);
initial begin
// Initialize Inputs
rxd = 0;
rst = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rxd = 1;
rst = 1;
#100;
rst = 0;
#10000;
rxd = 0;
#9500;
rxd = 1; // bit 0 (LSB)
#9500;
rxd = 0; // bit 1
#9500;
rxd = 1; // bit 2
#9500;
rxd = 0; // bit 3
#9500;
rxd = 1; // bit 4
#9500;
rxd = 0; // bit 5
#9500;
rxd = 1; // bit 6
#9500;
rxd = 0; // bit 7
#9500;
rxd = 1;
#9500;
// sent 0101 0101
#100000;
rxd=0;
#9500;
rxd=1;
#100000;
end
always begin
#20 clk = ~clk;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_gclk_inv_r90_256x.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// --------------------------------------------------
// File: bw_clk_gclk_inv_r90_256x.behV
// --------------------------------------------------
//
module bw_clk_gclk_inv_r90_256x (
clkout,
clkin );
output clkout;
input clkin;
assign clkout = ~( clkin );
endmodule
|
//% @file diffiodelay.v
//% @brief Convert between single-ended and differential and connect i/o through iodelay.
//% @author Yuan Mei
//%
//% @param[in] NINPUT number of inputs.
//% @param[in] NOUTPUT number of outputs.
//% @param[in] DELAY_CHANNEL address 0~(NINPUT-1) selects inputs, NINPUT~(NINPUT+NOUTPUT-1) selects outputs to control.
`timescale 1ns / 1ps
module diffiodelay
#(
parameter NINPUT = 20,
parameter NOUTPUT = 1,
parameter INPUT_DIFF_TERM = "TRUE",
parameter IODELAY_GROUP_NAME = "iodelay_grp"
)
(
input RESET,
input CLK, //% DELAY_* must be synchronous to this clock
input [7:0] DELAY_CHANNEL,
input [4:0] DELAY_VALUE,
input DELAY_UPDATE, //% a pulse to update the delay value
output [NINPUT-1:0] INPUTS_OUT,
input [NINPUT-1:0] INPUTS_P,
input [NINPUT-1:0] INPUTS_N,
input [NOUTPUT-1:0] OUTPUTS_IN,
output [NOUTPUT-1:0] OUTPUTS_P,
output [NOUTPUT-1:0] OUTPUTS_N
);
reg [(NINPUT+NOUTPUT)-1:0] delay_update_v;
wire du;
reg du_prev, du_prev1;
wire [NINPUT-1:0] inputs_out_i;
wire [NOUTPUT-1:0] outputs_in_i;
// select which channel to write the delay_value to
always @ (DELAY_CHANNEL, du) begin
delay_update_v <= 0;
delay_update_v[DELAY_CHANNEL] <= du;
end
// capture the rising edge
always @ (posedge CLK or posedge RESET) begin
if (RESET) begin
du_prev <= 0;
du_prev1 <= 0;
end
else begin
du_prev <= DELAY_UPDATE;
du_prev1 <= du_prev;
end
end
assign du = (~du_prev1)&(du_prev);
genvar i;
generate
for (i=0; i<NINPUT; i=i+1) begin
IBUFDS
#(
.DIFF_TERM(INPUT_DIFF_TERM), // Differential Termination
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
)
ibufds_inst
(
.O(inputs_out_i[i]), // Buffer output
.I(INPUTS_P[i]), // Diff_p buffer input (connect directly to top-level port)
.IB(INPUTS_N[i]) // Diff_n buffer input (connect directly to top-level port)
);
(* IODELAY_GROUP = IODELAY_GROUP_NAME *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYE2
#(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE(0), // Input delay tap setting (0-31)
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
)
idelaye2_inst
(
.CNTVALUEOUT(), // 5-bit output: Counter value output
.DATAOUT(INPUTS_OUT[i]), // 1-bit output: Delayed data output
.C(CLK), // 1-bit input: Clock input
.CE(0), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL(0), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN(DELAY_VALUE), // 5-bit input: Counter value input
.DATAIN(0), // 1-bit input: Internal delay data input
.IDATAIN(inputs_out_i[i]), // 1-bit input: Data input from the I/O
.INC(0), // 1-bit input: Increment / Decrement tap delay input
.LD(delay_update_v[i]), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN(0), // 1-bit input: Enable PIPELINE register to load data input
.REGRST(0) // 1-bit input: Active-high reset tap-delay input
);
end
for (i=0; i<NOUTPUT; i=i+1) begin
// ODELAYE2 only exists in HP banks!
(* IODELAY_GROUP = IODELAY_GROUP_NAME *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
ODELAYE2
#(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.ODELAY_VALUE(0), // Output delay tap setting (0-31)
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
)
odelaye2_inst
(
.CNTVALUEOUT(), // 5-bit output: Counter value output
.DATAOUT(outputs_in_i[i]), // 1-bit output: Delayed data/clock output
.C(CLK), // 1-bit input: Clock input
.CE(0), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL(0), // 1-bit input: Dynamic clock inversion input
.CLKIN(0), // 1-bit input: Clock delay input
.CNTVALUEIN(DELAY_VALUE), // 5-bit input: Counter value input
.INC(0), // 1-bit input: Increment / Decrement tap delay input
.LD(delay_update_v[i+NINPUT]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode,
// in VAR_LOAD or VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
.LDPIPEEN(0), // 1-bit input: Enables the pipeline register to load data
.ODATAIN(OUTPUTS_IN[i]), // 1-bit input: Output delay data input
.REGRST(0) // 1-bit input: Active-high reset tap-delay input
);
OBUFDS
#(
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
)
obufds_inst
(
.O(OUTPUTS_P[i]), // Diff_p output (connect directly to top-level port)
.OB(OUTPUTS_N[i]), // Diff_n output (connect directly to top-level port)
.I(outputs_in_i[i]) // Buffer input
);
end
endgenerate
endmodule // diffiodelay
|
(* Copyright (c) 2008-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import Arith List.
Require Import CpdtTactics.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(** %\chapter{Dependent Data Structures}% *)
(** Our red-black tree example from the last chapter illustrated how dependent types enable static enforcement of data structure invariants. To find interesting uses of dependent data structures, however, we need not look to the favorite examples of data structures and algorithms textbooks. More basic examples like length-indexed and heterogeneous lists come up again and again as the building blocks of dependent programs. There is a surprisingly large design space for this class of data structure, and we will spend this chapter exploring it. *)
(** * More Length-Indexed Lists *)
(** We begin with a deeper look at the length-indexed lists that began the last chapter.%\index{Gallina terms!ilist}% *)
Section ilist.
Variable A : Set.
Inductive ilist : nat -> Set :=
| Nil : ilist O
| Cons : forall n, A -> ilist n -> ilist (S n).
(** We might like to have a certified function for selecting an element of an [ilist] by position. We could do this using subset types and explicit manipulation of proofs, but dependent types let us do it more directly. It is helpful to define a type family %\index{Gallina terms!fin}%[fin], where [fin n] is isomorphic to [{m : nat | m < n}]. The type family name stands for "finite." *)
(* EX: Define a function [get] for extracting an [ilist] element by position. *)
(* begin thide *)
Inductive fin : nat -> Set :=
| First : forall n, fin (S n)
| Next : forall n, fin n -> fin (S n).
(** An instance of [fin] is essentially a more richly typed copy of a prefix of the natural numbers. Every element is a [First] iterated through applying [Next] a number of times that indicates which number is being selected. For instance, the three values of type [fin 3] are [First 2], [Next (First 1)], and [Next (Next (First 0))].
Now it is easy to pick a [Prop]-free type for a selection function. As usual, our first implementation attempt will not convince the type checker, and we will attack the deficiencies one at a time.
[[
Fixpoint get n (ls : ilist n) : fin n -> A :=
match ls with
| Nil => fun idx => ?
| Cons _ x ls' => fun idx =>
match idx with
| First _ => x
| Next _ idx' => get ls' idx'
end
end.
]]
%\vspace{-.15in}%We apply the usual wisdom of delaying arguments in [Fixpoint]s so that they may be included in [return] clauses. This still leaves us with a quandary in each of the [match] cases. First, we need to figure out how to take advantage of the contradiction in the [Nil] case. Every [fin] has a type of the form [S n], which cannot unify with the [O] value that we learn for [n] in the [Nil] case. The solution we adopt is another case of [match]-within-[return], with the [return] clause chosen carefully so that it returns the proper type [A] in case the [fin] index is [O], which we know is true here; and so that it returns an easy-to-inhabit type [unit] in the remaining, impossible cases, which nonetheless appear explicitly in the body of the [match].
[[
Fixpoint get n (ls : ilist n) : fin n -> A :=
match ls with
| Nil => fun idx =>
match idx in fin n' return (match n' with
| O => A
| S _ => unit
end) with
| First _ => tt
| Next _ _ => tt
end
| Cons _ x ls' => fun idx =>
match idx with
| First _ => x
| Next _ idx' => get ls' idx'
end
end.
]]
%\vspace{-.15in}%Now the first [match] case type-checks, and we see that the problem with the [Cons] case is that the pattern-bound variable [idx'] does not have an apparent type compatible with [ls']. In fact, the error message Coq gives for this exact code can be confusing, thanks to an overenthusiastic type inference heuristic. We are told that the [Nil] case body has type [match X with | O => A | S _ => unit end] for a unification variable [X], while it is expected to have type [A]. We can see that setting [X] to [O] resolves the conflict, but Coq is not yet smart enough to do this unification automatically. Repeating the function's type in a [return] annotation, used with an [in] annotation, leads us to a more informative error message, saying that [idx'] has type [fin n1] while it is expected to have type [fin n0], where [n0] is bound by the [Cons] pattern and [n1] by the [Next] pattern. As the code is written above, nothing forces these two natural numbers to be equal, though we know intuitively that they must be.
We need to use [match] annotations to make the relationship explicit. Unfortunately, the usual trick of postponing argument binding will not help us here. We need to match on both [ls] and [idx]; one or the other must be matched first. To get around this, we apply the convoy pattern that we met last chapter. This application is a little more clever than those we saw before; we use the natural number predecessor function [pred] to express the relationship between the types of these variables.
[[
Fixpoint get n (ls : ilist n) : fin n -> A :=
match ls with
| Nil => fun idx =>
match idx in fin n' return (match n' with
| O => A
| S _ => unit
end) with
| First _ => tt
| Next _ _ => tt
end
| Cons _ x ls' => fun idx =>
match idx in fin n' return ilist (pred n') -> A with
| First _ => fun _ => x
| Next _ idx' => fun ls' => get ls' idx'
end ls'
end.
]]
%\vspace{-.15in}%There is just one problem left with this implementation. Though we know that the local [ls'] in the [Next] case is equal to the original [ls'], the type-checker is not satisfied that the recursive call to [get] does not introduce non-termination. We solve the problem by convoy-binding the partial application of [get] to [ls'], rather than [ls'] by itself. *)
Fixpoint get n (ls : ilist n) : fin n -> A :=
match ls with
| Nil => fun idx =>
match idx in fin n' return (match n' with
| O => A
| S _ => unit
end) with
| First _ => tt
| Next _ _ => tt
end
| Cons _ x ls' => fun idx =>
match idx in fin n' return (fin (pred n') -> A) -> A with
| First _ => fun _ => x
| Next _ idx' => fun get_ls' => get_ls' idx'
end (get ls')
end.
(* end thide *)
End ilist.
Implicit Arguments Nil [A].
Implicit Arguments First [n].
(** A few examples show how to make use of these definitions. *)
Check Cons 0 (Cons 1 (Cons 2 Nil)).
(** %\vspace{-.15in}% [[
Cons 0 (Cons 1 (Cons 2 Nil))
: ilist nat 3
]]
*)
(* begin thide *)
Eval simpl in get (Cons 0 (Cons 1 (Cons 2 Nil))) First.
(** %\vspace{-.15in}% [[
= 0
: nat
]]
*)
Eval simpl in get (Cons 0 (Cons 1 (Cons 2 Nil))) (Next First).
(** %\vspace{-.15in}% [[
= 1
: nat
]]
*)
Eval simpl in get (Cons 0 (Cons 1 (Cons 2 Nil))) (Next (Next First)).
(** %\vspace{-.15in}% [[
= 2
: nat
]]
*)
(* end thide *)
(* begin hide *)
(* begin thide *)
Definition map' := map.
(* end thide *)
(* end hide *)
(** Our [get] function is also quite easy to reason about. We show how with a short example about an analogue to the list [map] function. *)
Section ilist_map.
Variables A B : Set.
Variable f : A -> B.
Fixpoint imap n (ls : ilist A n) : ilist B n :=
match ls with
| Nil => Nil
| Cons _ x ls' => Cons (f x) (imap ls')
end.
(** It is easy to prove that [get] "distributes over" [imap] calls. *)
(* EX: Prove that [get] distributes over [imap]. *)
(* begin thide *)
Theorem get_imap : forall n (idx : fin n) (ls : ilist A n),
get (imap ls) idx = f (get ls idx).
induction ls; dep_destruct idx; crush.
Qed.
(* end thide *)
End ilist_map.
(** The only tricky bit is remembering to use our [dep_destruct] tactic in place of plain [destruct] when faced with a baffling tactic error message. *)
(** * Heterogeneous Lists *)
(** Programmers who move to statically typed functional languages from scripting languages often complain about the requirement that every element of a list have the same type. With fancy type systems, we can partially lift this requirement. We can index a list type with a "type-level" list that explains what type each element of the list should have. This has been done in a variety of ways in Haskell using type classes, and we can do it much more cleanly and directly in Coq. *)
Section hlist.
Variable A : Type.
Variable B : A -> Type.
(* EX: Define a type [hlist] indexed by a [list A], where the type of each element is determined by running [B] on the corresponding element of the index list. *)
(** We parameterize our heterogeneous lists by a type [A] and an [A]-indexed type [B].%\index{Gallina terms!hlist}% *)
(* begin thide *)
Inductive hlist : list A -> Type :=
| HNil : hlist nil
| HCons : forall (x : A) (ls : list A), B x -> hlist ls -> hlist (x :: ls).
(** We can implement a variant of the last section's [get] function for [hlist]s. To get the dependent typing to work out, we will need to index our element selectors (in type family [member]) by the types of data that they point to.%\index{Gallina terms!member}% *)
(* end thide *)
(* EX: Define an analogue to [get] for [hlist]s. *)
(* begin thide *)
Variable elm : A.
Inductive member : list A -> Type :=
| HFirst : forall ls, member (elm :: ls)
| HNext : forall x ls, member ls -> member (x :: ls).
(** Because the element [elm] that we are "searching for" in a list does not change across the constructors of [member], we simplify our definitions by making [elm] a local variable. In the definition of [member], we say that [elm] is found in any list that begins with [elm], and, if removing the first element of a list leaves [elm] present, then [elm] is present in the original list, too. The form looks much like a predicate for list membership, but we purposely define [member] in [Type] so that we may decompose its values to guide computations.
We can use [member] to adapt our definition of [get] to [hlist]s. The same basic [match] tricks apply. In the [HCons] case, we form a two-element convoy, passing both the data element [x] and the recursor for the sublist [mls'] to the result of the inner [match]. We did not need to do that in [get]'s definition because the types of list elements were not dependent there. *)
Fixpoint hget ls (mls : hlist ls) : member ls -> B elm :=
match mls with
| HNil => fun mem =>
match mem in member ls' return (match ls' with
| nil => B elm
| _ :: _ => unit
end) with
| HFirst _ => tt
| HNext _ _ _ => tt
end
| HCons _ _ x mls' => fun mem =>
match mem in member ls' return (match ls' with
| nil => Empty_set
| x' :: ls'' =>
B x' -> (member ls'' -> B elm)
-> B elm
end) with
| HFirst _ => fun x _ => x
| HNext _ _ mem' => fun _ get_mls' => get_mls' mem'
end x (hget mls')
end.
(* end thide *)
End hlist.
(* begin thide *)
Implicit Arguments HNil [A B].
Implicit Arguments HCons [A B x ls].
Implicit Arguments HFirst [A elm ls].
Implicit Arguments HNext [A elm x ls].
(* end thide *)
(** By putting the parameters [A] and [B] in [Type], we enable fancier kinds of polymorphism than in mainstream functional languages. For instance, one use of [hlist] is for the simple heterogeneous lists that we referred to earlier. *)
Definition someTypes : list Set := nat :: bool :: nil.
(* begin thide *)
Example someValues : hlist (fun T : Set => T) someTypes :=
HCons 5 (HCons true HNil).
Eval simpl in hget someValues HFirst.
(** %\vspace{-.15in}% [[
= 5
: (fun T : Set => T) nat
]]
*)
Eval simpl in hget someValues (HNext HFirst).
(** %\vspace{-.15in}% [[
= true
: (fun T : Set => T) bool
]]
*)
(** We can also build indexed lists of pairs in this way. *)
Example somePairs : hlist (fun T : Set => T * T)%type someTypes :=
HCons (1, 2) (HCons (true, false) HNil).
(** There are many other useful applications of heterogeneous lists, based on different choices of the first argument to [hlist]. *)
(* end thide *)
(** ** A Lambda Calculus Interpreter *)
(** Heterogeneous lists are very useful in implementing %\index{interpreters}%interpreters for functional programming languages. Using the types and operations we have already defined, it is trivial to write an interpreter for simply typed lambda calculus%\index{lambda calculus}%. Our interpreter can alternatively be thought of as a denotational semantics (but worry not if you are not familiar with such terminology from semantics).
We start with an algebraic datatype for types. *)
Inductive type : Set :=
| Unit : type
| Arrow : type -> type -> type.
(** Now we can define a type family for expressions. An [exp ts t] will stand for an expression that has type [t] and whose free variables have types in the list [ts]. We effectively use the de Bruijn index variable representation%~\cite{DeBruijn}%. Variables are represented as [member] values; that is, a variable is more or less a constructive proof that a particular type is found in the type environment. *)
Inductive exp : list type -> type -> Set :=
| Const : forall ts, exp ts Unit
(* begin thide *)
| Var : forall ts t, member t ts -> exp ts t
| App : forall ts dom ran, exp ts (Arrow dom ran) -> exp ts dom -> exp ts ran
| Abs : forall ts dom ran, exp (dom :: ts) ran -> exp ts (Arrow dom ran).
(* end thide *)
Implicit Arguments Const [ts].
(** We write a simple recursive function to translate [type]s into [Set]s. *)
Fixpoint typeDenote (t : type) : Set :=
match t with
| Unit => unit
| Arrow t1 t2 => typeDenote t1 -> typeDenote t2
end.
(** Now it is straightforward to write an expression interpreter. The type of the function, [expDenote], tells us that we translate expressions into functions from properly typed environments to final values. An environment for a free variable list [ts] is simply an [hlist typeDenote ts]. That is, for each free variable, the heterogeneous list that is the environment must have a value of the variable's associated type. We use [hget] to implement the [Var] case, and we use [HCons] to extend the environment in the [Abs] case. *)
(* EX: Define an interpreter for [exp]s. *)
(* begin thide *)
Fixpoint expDenote ts t (e : exp ts t) : hlist typeDenote ts -> typeDenote t :=
match e with
| Const _ => fun _ => tt
| Var _ _ mem => fun s => hget s mem
| App _ _ _ e1 e2 => fun s => (expDenote e1 s) (expDenote e2 s)
| Abs _ _ _ e' => fun s => fun x => expDenote e' (HCons x s)
end.
(** Like for previous examples, our interpreter is easy to run with [simpl]. *)
Eval simpl in expDenote Const HNil.
(** %\vspace{-.15in}% [[
= tt
: typeDenote Unit
]]
*)
Eval simpl in expDenote (Abs (dom := Unit) (Var HFirst)) HNil.
(** %\vspace{-.15in}% [[
= fun x : unit => x
: typeDenote (Arrow Unit Unit)
]]
*)
Eval simpl in expDenote (Abs (dom := Unit)
(Abs (dom := Unit) (Var (HNext HFirst)))) HNil.
(** %\vspace{-.15in}% [[
= fun x _ : unit => x
: typeDenote (Arrow Unit (Arrow Unit Unit))
]]
*)
Eval simpl in expDenote (Abs (dom := Unit) (Abs (dom := Unit) (Var HFirst))) HNil.
(** %\vspace{-.15in}% [[
= fun _ x0 : unit => x0
: typeDenote (Arrow Unit (Arrow Unit Unit))
]]
*)
Eval simpl in expDenote (App (Abs (Var HFirst)) Const) HNil.
(** %\vspace{-.15in}% [[
= tt
: typeDenote Unit
]]
*)
(* end thide *)
(** We are starting to develop the tools behind dependent typing's amazing advantage over alternative approaches in several important areas. Here, we have implemented complete syntax, typing rules, and evaluation semantics for simply typed lambda calculus without even needing to define a syntactic substitution operation. We did it all without a single line of proof, and our implementation is manifestly executable. Other, more common approaches to language formalization often state and prove explicit theorems about type safety of languages. In the above example, we got type safety, termination, and other meta-theorems for free, by reduction to CIC, which we know has those properties. *)
(** * Recursive Type Definitions *)
(** %\index{recursive type definition}%There is another style of datatype definition that leads to much simpler definitions of the [get] and [hget] definitions above. Because Coq supports "type-level computation," we can redo our inductive definitions as _recursive_ definitions. Here we will preface type names with the letter [f] to indicate that they are based on explicit recursive _function_ definitions. *)
(* EX: Come up with an alternate [ilist] definition that makes it easier to write [get]. *)
Section filist.
Variable A : Set.
(* begin thide *)
Fixpoint filist (n : nat) : Set :=
match n with
| O => unit
| S n' => A * filist n'
end%type.
(** We say that a list of length 0 has no contents, and a list of length [S n'] is a pair of a data value and a list of length [n']. *)
Fixpoint ffin (n : nat) : Set :=
match n with
| O => Empty_set
| S n' => option (ffin n')
end.
(** We express that there are no index values when [n = O], by defining such indices as type [Empty_set]; and we express that, at [n = S n'], there is a choice between picking the first element of the list (represented as [None]) or choosing a later element (represented by [Some idx], where [idx] is an index into the list tail). For instance, the three values of type [ffin 3] are [None], [Some None], and [Some (Some None)]. *)
Fixpoint fget (n : nat) : filist n -> ffin n -> A :=
match n with
| O => fun _ idx => match idx with end
| S n' => fun ls idx =>
match idx with
| None => fst ls
| Some idx' => fget n' (snd ls) idx'
end
end.
(** Our new [get] implementation needs only one dependent [match], and its annotation is inferred for us. Our choices of data structure implementations lead to just the right typing behavior for this new definition to work out. *)
(* end thide *)
End filist.
(** Heterogeneous lists are a little trickier to define with recursion, but we then reap similar benefits in simplicity of use. *)
(* EX: Come up with an alternate [hlist] definition that makes it easier to write [hget]. *)
Section fhlist.
Variable A : Type.
Variable B : A -> Type.
(* begin thide *)
Fixpoint fhlist (ls : list A) : Type :=
match ls with
| nil => unit
| x :: ls' => B x * fhlist ls'
end%type.
(** The definition of [fhlist] follows the definition of [filist], with the added wrinkle of dependently typed data elements. *)
Variable elm : A.
Fixpoint fmember (ls : list A) : Type :=
match ls with
| nil => Empty_set
| x :: ls' => (x = elm) + fmember ls'
end%type.
(** The definition of [fmember] follows the definition of [ffin]. Empty lists have no members, and member types for nonempty lists are built by adding one new option to the type of members of the list tail. While for [ffin] we needed no new information associated with the option that we add, here we need to know that the head of the list equals the element we are searching for. We express that idea with a sum type whose left branch is the appropriate equality proposition. Since we define [fmember] to live in [Type], we can insert [Prop] types as needed, because [Prop] is a subtype of [Type].
We know all of the tricks needed to write a first attempt at a [get] function for [fhlist]s.
[[
Fixpoint fhget (ls : list A) : fhlist ls -> fmember ls -> B elm :=
match ls with
| nil => fun _ idx => match idx with end
| _ :: ls' => fun mls idx =>
match idx with
| inl _ => fst mls
| inr idx' => fhget ls' (snd mls) idx'
end
end.
]]
%\vspace{-.15in}%Only one problem remains. The expression [fst mls] is not known to have the proper type. To demonstrate that it does, we need to use the proof available in the [inl] case of the inner [match]. *)
Fixpoint fhget (ls : list A) : fhlist ls -> fmember ls -> B elm :=
match ls with
| nil => fun _ idx => match idx with end
| _ :: ls' => fun mls idx =>
match idx with
| inl pf => match pf with
| eq_refl => fst mls
end
| inr idx' => fhget ls' (snd mls) idx'
end
end.
(** By pattern-matching on the equality proof [pf], we make that equality known to the type-checker. Exactly why this works can be seen by studying the definition of equality. *)
(* begin hide *)
(* begin thide *)
Definition foo := @eq_refl.
(* end thide *)
(* end hide *)
Print eq.
(** %\vspace{-.15in}% [[
Inductive eq (A : Type) (x : A) : A -> Prop := eq_refl : x = x
]]
In a proposition [x = y], we see that [x] is a parameter and [y] is a regular argument. The type of the constructor [eq_refl] shows that [y] can only ever be instantiated to [x]. Thus, within a pattern-match with [eq_refl], occurrences of [y] can be replaced with occurrences of [x] for typing purposes. *)
(* end thide *)
End fhlist.
Implicit Arguments fhget [A B elm ls].
(** How does one choose between the two data structure encoding strategies we have presented so far? Before answering that question in this chapter's final section, we introduce one further approach. *)
(** * Data Structures as Index Functions *)
(** %\index{index function}%Indexed lists can be useful in defining other inductive types with constructors that take variable numbers of arguments. In this section, we consider parameterized trees with arbitrary branching factor. *)
(* begin hide *)
Definition red_herring := O.
(* working around a bug in Coq 8.5! *)
(* end hide *)
Section tree.
Variable A : Set.
Inductive tree : Set :=
| Leaf : A -> tree
| Node : forall n, ilist tree n -> tree.
End tree.
(** Every [Node] of a [tree] has a natural number argument, which gives the number of child trees in the second argument, typed with [ilist]. We can define two operations on trees of naturals: summing their elements and incrementing their elements. It is useful to define a generic fold function on [ilist]s first. *)
Section ifoldr.
Variables A B : Set.
Variable f : A -> B -> B.
Variable i : B.
Fixpoint ifoldr n (ls : ilist A n) : B :=
match ls with
| Nil => i
| Cons _ x ls' => f x (ifoldr ls')
end.
End ifoldr.
Fixpoint sum (t : tree nat) : nat :=
match t with
| Leaf n => n
| Node _ ls => ifoldr (fun t' n => sum t' + n) O ls
end.
Fixpoint inc (t : tree nat) : tree nat :=
match t with
| Leaf n => Leaf (S n)
| Node _ ls => Node (imap inc ls)
end.
(** Now we might like to prove that [inc] does not decrease a tree's [sum]. *)
Theorem sum_inc : forall t, sum (inc t) >= sum t.
(* begin thide *)
induction t; crush.
(** [[
n : nat
i : ilist (tree nat) n
============================
ifoldr (fun (t' : tree nat) (n0 : nat) => sum t' + n0) 0 (imap inc i) >=
ifoldr (fun (t' : tree nat) (n0 : nat) => sum t' + n0) 0 i
]]
We are left with a single subgoal which does not seem provable directly. This is the same problem that we met in Chapter 3 with other %\index{nested inductive type}%nested inductive types. *)
Check tree_ind.
(** %\vspace{-.15in}% [[
tree_ind
: forall (A : Set) (P : tree A -> Prop),
(forall a : A, P (Leaf a)) ->
(forall (n : nat) (i : ilist (tree A) n), P (Node i)) ->
forall t : tree A, P t
]]
The automatically generated induction principle is too weak. For the [Node] case, it gives us no inductive hypothesis. We could write our own induction principle, as we did in Chapter 3, but there is an easier way, if we are willing to alter the definition of [tree]. *)
Abort.
Reset tree.
(* begin hide *)
Reset red_herring.
(* working around a bug in Coq 8.5! *)
(* end hide *)
(** First, let us try using our recursive definition of [ilist]s instead of the inductive version. *)
Section tree.
Variable A : Set.
(** %\vspace{-.15in}% [[
Inductive tree : Set :=
| Leaf : A -> tree
| Node : forall n, filist tree n -> tree.
]]
<<
Error: Non strictly positive occurrence of "tree" in
"forall n : nat, filist tree n -> tree"
>>
The special-case rule for nested datatypes only works with nested uses of other inductive types, which could be replaced with uses of new mutually inductive types. We defined [filist] recursively, so it may not be used in nested inductive definitions.
Our final solution uses yet another of the inductive definition techniques introduced in Chapter 3, %\index{reflexive inductive type}%reflexive types. Instead of merely using [fin] to get elements out of [ilist], we can _define_ [ilist] in terms of [fin]. For the reasons outlined above, it turns out to be easier to work with [ffin] in place of [fin]. *)
Inductive tree : Set :=
| Leaf : A -> tree
| Node : forall n, (ffin n -> tree) -> tree.
(** A [Node] is indexed by a natural number [n], and the node's [n] children are represented as a function from [ffin n] to trees, which is isomorphic to the [ilist]-based representation that we used above. *)
End tree.
Implicit Arguments Node [A n].
(** We can redefine [sum] and [inc] for our new [tree] type. Again, it is useful to define a generic fold function first. This time, it takes in a function whose domain is some [ffin] type, and it folds another function over the results of calling the first function at every possible [ffin] value. *)
Section rifoldr.
Variables A B : Set.
Variable f : A -> B -> B.
Variable i : B.
Fixpoint rifoldr (n : nat) : (ffin n -> A) -> B :=
match n with
| O => fun _ => i
| S n' => fun get => f (get None) (rifoldr n' (fun idx => get (Some idx)))
end.
End rifoldr.
Implicit Arguments rifoldr [A B n].
Fixpoint sum (t : tree nat) : nat :=
match t with
| Leaf n => n
| Node _ f => rifoldr plus O (fun idx => sum (f idx))
end.
Fixpoint inc (t : tree nat) : tree nat :=
match t with
| Leaf n => Leaf (S n)
| Node _ f => Node (fun idx => inc (f idx))
end.
(** Now we are ready to prove the theorem where we got stuck before. We will not need to define any new induction principle, but it _will_ be helpful to prove some lemmas. *)
Lemma plus_ge : forall x1 y1 x2 y2,
x1 >= x2
-> y1 >= y2
-> x1 + y1 >= x2 + y2.
crush.
Qed.
Lemma sum_inc' : forall n (f1 f2 : ffin n -> nat),
(forall idx, f1 idx >= f2 idx)
-> rifoldr plus O f1 >= rifoldr plus O f2.
Hint Resolve plus_ge.
induction n; crush.
Qed.
Theorem sum_inc : forall t, sum (inc t) >= sum t.
Hint Resolve sum_inc'.
induction t; crush.
Qed.
(* end thide *)
(** Even if Coq would generate complete induction principles automatically for nested inductive definitions like the one we started with, there would still be advantages to using this style of reflexive encoding. We see one of those advantages in the definition of [inc], where we did not need to use any kind of auxiliary function. In general, reflexive encodings often admit direct implementations of operations that would require recursion if performed with more traditional inductive data structures. *)
(** ** Another Interpreter Example *)
(** We develop another example of variable-arity constructors, in the form of optimization of a small expression language with a construct like Scheme's <<cond>>. Each of our conditional expressions takes a list of pairs of boolean tests and bodies. The value of the conditional comes from the body of the first test in the list to evaluate to [true]. To simplify the %\index{interpreters}%interpreter we will write, we force each conditional to include a final, default case. *)
Inductive type' : Type := Nat | Bool.
Inductive exp' : type' -> Type :=
| NConst : nat -> exp' Nat
| Plus : exp' Nat -> exp' Nat -> exp' Nat
| Eq : exp' Nat -> exp' Nat -> exp' Bool
| BConst : bool -> exp' Bool
(* begin thide *)
| Cond : forall n t, (ffin n -> exp' Bool)
-> (ffin n -> exp' t) -> exp' t -> exp' t.
(* end thide *)
(** A [Cond] is parameterized by a natural [n], which tells us how many cases this conditional has. The test expressions are represented with a function of type [ffin n -> exp' Bool], and the bodies are represented with a function of type [ffin n -> exp' t], where [t] is the overall type. The final [exp' t] argument is the default case. For example, here is an expression that successively checks whether [2 + 2 = 5] (returning 0 if so) or if [1 + 1 = 2] (returning 1 if so), returning 2 otherwise. *)
Example ex1 := Cond 2
(fun f => match f with
| None => Eq (Plus (NConst 2) (NConst 2)) (NConst 5)
| Some None => Eq (Plus (NConst 1) (NConst 1)) (NConst 2)
| Some (Some v) => match v with end
end)
(fun f => match f with
| None => NConst 0
| Some None => NConst 1
| Some (Some v) => match v with end
end)
(NConst 2).
(** We start implementing our interpreter with a standard type denotation function. *)
Definition type'Denote (t : type') : Set :=
match t with
| Nat => nat
| Bool => bool
end.
(** To implement the expression interpreter, it is useful to have the following function that implements the functionality of [Cond] without involving any syntax. *)
(* begin thide *)
Section cond.
Variable A : Set.
Variable default : A.
Fixpoint cond (n : nat) : (ffin n -> bool) -> (ffin n -> A) -> A :=
match n with
| O => fun _ _ => default
| S n' => fun tests bodies =>
if tests None
then bodies None
else cond n'
(fun idx => tests (Some idx))
(fun idx => bodies (Some idx))
end.
End cond.
Implicit Arguments cond [A n].
(* end thide *)
(** Now the expression interpreter is straightforward to write. *)
(* begin thide *)
Fixpoint exp'Denote t (e : exp' t) : type'Denote t :=
match e with
| NConst n => n
| Plus e1 e2 => exp'Denote e1 + exp'Denote e2
| Eq e1 e2 =>
if eq_nat_dec (exp'Denote e1) (exp'Denote e2) then true else false
| BConst b => b
| Cond _ _ tests bodies default =>
cond
(exp'Denote default)
(fun idx => exp'Denote (tests idx))
(fun idx => exp'Denote (bodies idx))
end.
(* begin hide *)
Reset exp'Denote.
(* end hide *)
(* end thide *)
(* begin hide *)
Fixpoint exp'Denote t (e : exp' t) : type'Denote t :=
match e with
| NConst n => n
| Plus e1 e2 => exp'Denote e1 + exp'Denote e2
| Eq e1 e2 =>
if eq_nat_dec (exp'Denote e1) (exp'Denote e2) then true else false
| BConst b => b
| Cond _ _ tests bodies default =>
(* begin thide *)
cond
(exp'Denote default)
(fun idx => exp'Denote (tests idx))
(fun idx => exp'Denote (bodies idx))
(* end thide *)
end.
(* end hide *)
(** We will implement a constant-folding function that optimizes conditionals, removing cases with known-[false] tests and cases that come after known-[true] tests. A function [cfoldCond] implements the heart of this logic. The convoy pattern is used again near the end of the implementation. *)
(* begin thide *)
Section cfoldCond.
Variable t : type'.
Variable default : exp' t.
Fixpoint cfoldCond (n : nat)
: (ffin n -> exp' Bool) -> (ffin n -> exp' t) -> exp' t :=
match n with
| O => fun _ _ => default
| S n' => fun tests bodies =>
match tests None return _ with
| BConst true => bodies None
| BConst false => cfoldCond n'
(fun idx => tests (Some idx))
(fun idx => bodies (Some idx))
| _ =>
let e := cfoldCond n'
(fun idx => tests (Some idx))
(fun idx => bodies (Some idx)) in
match e in exp' t return exp' t -> exp' t with
| Cond n _ tests' bodies' default' => fun body =>
Cond
(S n)
(fun idx => match idx with
| None => tests None
| Some idx => tests' idx
end)
(fun idx => match idx with
| None => body
| Some idx => bodies' idx
end)
default'
| e => fun body =>
Cond
1
(fun _ => tests None)
(fun _ => body)
e
end (bodies None)
end
end.
End cfoldCond.
Implicit Arguments cfoldCond [t n].
(* end thide *)
(** Like for the interpreters, most of the action was in this helper function, and [cfold] itself is easy to write. *)
(* begin thide *)
Fixpoint cfold t (e : exp' t) : exp' t :=
match e with
| NConst n => NConst n
| Plus e1 e2 =>
let e1' := cfold e1 in
let e2' := cfold e2 in
match e1', e2' return exp' Nat with
| NConst n1, NConst n2 => NConst (n1 + n2)
| _, _ => Plus e1' e2'
end
| Eq e1 e2 =>
let e1' := cfold e1 in
let e2' := cfold e2 in
match e1', e2' return exp' Bool with
| NConst n1, NConst n2 => BConst (if eq_nat_dec n1 n2 then true else false)
| _, _ => Eq e1' e2'
end
| BConst b => BConst b
| Cond _ _ tests bodies default =>
cfoldCond
(cfold default)
(fun idx => cfold (tests idx))
(fun idx => cfold (bodies idx))
end.
(* end thide *)
(* begin thide *)
(** To prove our final correctness theorem, it is useful to know that [cfoldCond] preserves expression meanings. The following lemma formalizes that property. The proof is a standard mostly automated one, with the only wrinkle being a guided instantiation of the quantifiers in the induction hypothesis. *)
Lemma cfoldCond_correct : forall t (default : exp' t)
n (tests : ffin n -> exp' Bool) (bodies : ffin n -> exp' t),
exp'Denote (cfoldCond default tests bodies)
= exp'Denote (Cond n tests bodies default).
induction n; crush;
match goal with
| [ IHn : forall tests bodies, _, tests : _ -> _, bodies : _ -> _ |- _ ] =>
specialize (IHn (fun idx => tests (Some idx)) (fun idx => bodies (Some idx)))
end;
repeat (match goal with
| [ |- context[match ?E with NConst _ => _ | _ => _ end] ] =>
dep_destruct E
| [ |- context[if ?B then _ else _] ] => destruct B
end; crush).
Qed.
(** It is also useful to know that the result of a call to [cond] is not changed by substituting new tests and bodies functions, so long as the new functions have the same input-output behavior as the old. It turns out that, in Coq, it is not possible to prove in general that functions related in this way are equal. We treat this issue with our discussion of axioms in a later chapter. For now, it suffices to prove that the particular function [cond] is _extensional_; that is, it is unaffected by substitution of functions with input-output equivalents. *)
Lemma cond_ext : forall (A : Set) (default : A) n (tests tests' : ffin n -> bool)
(bodies bodies' : ffin n -> A),
(forall idx, tests idx = tests' idx)
-> (forall idx, bodies idx = bodies' idx)
-> cond default tests bodies
= cond default tests' bodies'.
induction n; crush;
match goal with
| [ |- context[if ?E then _ else _] ] => destruct E
end; crush.
Qed.
(** Now the final theorem is easy to prove. *)
(* end thide *)
Theorem cfold_correct : forall t (e : exp' t),
exp'Denote (cfold e) = exp'Denote e.
(* begin thide *)
Hint Rewrite cfoldCond_correct.
Hint Resolve cond_ext.
induction e; crush;
repeat (match goal with
| [ |- context[cfold ?E] ] => dep_destruct (cfold E)
end; crush).
Qed.
(* end thide *)
(** We add our two lemmas as hints and perform standard automation with pattern-matching of subterms to destruct. *)
(** * Choosing Between Representations *)
(** It is not always clear which of these representation techniques to apply in a particular situation, but I will try to summarize the pros and cons of each.
Inductive types are often the most pleasant to work with, after someone has spent the time implementing some basic library functions for them, using fancy [match] annotations. Many aspects of Coq's logic and tactic support are specialized to deal with inductive types, and you may miss out if you use alternate encodings.
Recursive types usually involve much less initial effort, but they can be less convenient to use with proof automation. For instance, the [simpl] tactic (which is among the ingredients in [crush]) will sometimes be overzealous in simplifying uses of functions over recursive types. Consider a call [get l f], where variable [l] has type [filist A (S n)]. The type of [l] would be simplified to an explicit pair type. In a proof involving many recursive types, this kind of unhelpful "simplification" can lead to rapid bloat in the sizes of subgoals. Even worse, it can prevent syntactic pattern-matching, like in cases where [filist] is expected but a pair type is found in the "simplified" version. The same problem applies to applications of recursive functions to values in recursive types: the recursive function call may "simplify" when the top-level structure of the type index but not the recursive value is known, because such functions are generally defined by recursion on the index, not the value.
Another disadvantage of recursive types is that they only apply to type families whose indices determine their "skeletons." This is not true for all data structures; a good counterexample comes from the richly typed programming language syntax types we have used several times so far. The fact that a piece of syntax has type [Nat] tells us nothing about the tree structure of that syntax.
Finally, Coq type inference can be more helpful in constructing values in inductive types. Application of a particular constructor of that type tells Coq what to expect from the arguments, while, for instance, forming a generic pair does not make clear an intention to interpret the value as belonging to a particular recursive type. This downside can be mitigated to an extent by writing "constructor" functions for a recursive type, mirroring the definition of the corresponding inductive type.
Reflexive encodings of data types are seen relatively rarely. As our examples demonstrated, manipulating index values manually can lead to hard-to-read code. A normal inductive type is generally easier to work with, once someone has gone through the trouble of implementing an induction principle manually with the techniques we studied in Chapter 3. For small developments, avoiding that kind of coding can justify the use of reflexive data structures. There are also some useful instances of %\index{co-inductive types}%co-inductive definitions with nested data structures (e.g., lists of values in the co-inductive type) that can only be deconstructed effectively with reflexive encoding of the nested structures. *)
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adcfifo_dma (
axi_clk,
axi_drst,
axi_dvalid,
axi_ddata,
axi_dready,
axi_xfer_status,
dma_clk,
dma_wr,
dma_wdata,
dma_wready,
dma_xfer_req,
dma_xfer_status);
// parameters
parameter AXI_DATA_WIDTH = 512;
parameter DMA_DATA_WIDTH = 64;
parameter DMA_READY_ENABLE = 1;
localparam DMA_MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH;
localparam DMA_ADDR_WIDTH = 8;
localparam AXI_ADDR_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDR_WIDTH - 1) :
((DMA_MEM_RATIO == 4) ? (DMA_ADDR_WIDTH - 2) : (DMA_ADDR_WIDTH - 3));
// adc write
input axi_clk;
input axi_drst;
input axi_dvalid;
input [AXI_DATA_WIDTH-1:0] axi_ddata;
output axi_dready;
input [ 3:0] axi_xfer_status;
// dma read
input dma_clk;
output dma_wr;
output [DMA_DATA_WIDTH-1:0] dma_wdata;
input dma_wready;
input dma_xfer_req;
output [ 3:0] dma_xfer_status;
// internal registers
reg [AXI_ADDR_WIDTH-1:0] axi_waddr = 'd0;
reg [ 2:0] axi_waddr_rel_count = 'd0;
reg axi_waddr_rel_t = 'd0;
reg [AXI_ADDR_WIDTH-1:0] axi_waddr_rel = 'd0;
reg [ 2:0] axi_raddr_rel_t_m = 'd0;
reg [DMA_ADDR_WIDTH-1:0] axi_raddr_rel = 'd0;
reg [DMA_ADDR_WIDTH-1:0] axi_addr_diff = 'd0;
reg axi_dready = 'd0;
reg dma_rst = 'd0;
reg [ 2:0] dma_waddr_rel_t_m = 'd0;
reg [AXI_ADDR_WIDTH-1:0] dma_waddr_rel = 'd0;
reg dma_rd = 'd0;
reg dma_rd_d = 'd0;
reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;
reg [DMA_ADDR_WIDTH-1:0] dma_raddr = 'd0;
reg [ 2:0] dma_raddr_rel_count = 'd0;
reg dma_raddr_rel_t = 'd0;
reg [DMA_ADDR_WIDTH-1:0] dma_raddr_rel = 'd0;
// internal signals
wire [DMA_ADDR_WIDTH:0] axi_addr_diff_s;
wire axi_raddr_rel_t_s;
wire [DMA_ADDR_WIDTH-1:0] axi_waddr_s;
wire dma_waddr_rel_t_s;
wire [DMA_ADDR_WIDTH-1:0] dma_waddr_rel_s;
wire dma_wready_s;
wire dma_rd_s;
wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;
// write interface
always @(posedge axi_clk) begin
if (axi_drst == 1'b1) begin
axi_waddr <= 'd0;
axi_waddr_rel_count <= 'd0;
axi_waddr_rel_t <= 'd0;
axi_waddr_rel <= 'd0;
end else begin
if (axi_dvalid == 1'b1) begin
axi_waddr <= axi_waddr + 1'b1;
end
axi_waddr_rel_count <= axi_waddr_rel_count + 1'b1;
if (axi_waddr_rel_count == 3'd7) begin
axi_waddr_rel_t <= ~axi_waddr_rel_t;
axi_waddr_rel <= axi_waddr;
end
end
end
assign axi_addr_diff_s = {1'b1, axi_waddr_s} - axi_raddr_rel;
assign axi_raddr_rel_t_s = axi_raddr_rel_t_m[2] ^ axi_raddr_rel_t_m[1];
assign axi_waddr_s = (DMA_MEM_RATIO == 2) ? {axi_waddr, 1'd0} :
((DMA_MEM_RATIO == 4) ? {axi_waddr, 2'd0} : {axi_waddr, 3'd0});
always @(posedge axi_clk) begin
if (axi_drst == 1'b1) begin
axi_raddr_rel_t_m <= 'd0;
axi_raddr_rel <= 'd0;
axi_addr_diff <= 'd0;
axi_dready <= 'd0;
end else begin
axi_raddr_rel_t_m <= {axi_raddr_rel_t_m[1:0], dma_raddr_rel_t};
if (axi_raddr_rel_t_s == 1'b1) begin
axi_raddr_rel <= dma_raddr_rel;
end
axi_addr_diff <= axi_addr_diff_s[DMA_ADDR_WIDTH-1:0];
if (axi_addr_diff >= 180) begin
axi_dready <= 1'b0;
end else if (axi_addr_diff <= 8) begin
axi_dready <= 1'b1;
end
end
end
// read interface
assign dma_waddr_rel_t_s = dma_waddr_rel_t_m[2] ^ dma_waddr_rel_t_m[1];
assign dma_waddr_rel_s = (DMA_MEM_RATIO == 2) ? {dma_waddr_rel, 1'd0} :
((DMA_MEM_RATIO == 4) ? {dma_waddr_rel, 2'd0} : {dma_waddr_rel, 3'd0});
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
dma_rst <= 1'b1;
dma_waddr_rel_t_m <= 'd0;
dma_waddr_rel <= 'd0;
end else begin
dma_rst <= 1'b0;
dma_waddr_rel_t_m <= {dma_waddr_rel_t_m[1:0], axi_waddr_rel_t};
if (dma_waddr_rel_t_s == 1'b1) begin
dma_waddr_rel <= axi_waddr_rel;
end
end
end
assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready;
assign dma_rd_s = (dma_raddr == dma_waddr_rel_s) ? 1'b0 : dma_wready_s;
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
dma_rd <= 'd0;
dma_rd_d <= 'd0;
dma_rdata_d <= 'd0;
dma_raddr <= 'd0;
dma_raddr_rel_count <= 'd0;
dma_raddr_rel_t <= 'd0;
dma_raddr_rel <= 'd0;
end else begin
dma_rd <= dma_rd_s;
dma_rd_d <= dma_rd;
dma_rdata_d <= dma_rdata_s;
if (dma_rd_s == 1'b1) begin
dma_raddr <= dma_raddr + 1'b1;
end
dma_raddr_rel_count <= dma_raddr_rel_count + 1'b1;
if (dma_raddr_rel_count == 3'd7) begin
dma_raddr_rel_t <= ~dma_raddr_rel_t;
dma_raddr_rel <= dma_raddr;
end
end
end
// instantiations
ad_mem_asym #(
.ADDR_WIDTH_A (AXI_ADDR_WIDTH),
.DATA_WIDTH_A (AXI_DATA_WIDTH),
.ADDR_WIDTH_B (DMA_ADDR_WIDTH),
.DATA_WIDTH_B (DMA_DATA_WIDTH))
i_mem_asym (
.clka (axi_clk),
.wea (axi_dvalid),
.addra (axi_waddr),
.dina (axi_ddata),
.clkb (dma_clk),
.addrb (dma_raddr),
.doutb (dma_rdata_s));
ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf (
.clk (dma_clk),
.rst (dma_rst),
.valid (dma_rd_d),
.last (1'd0),
.data (dma_rdata_d),
.inf_valid (dma_wr),
.inf_last (),
.inf_data (dma_wdata),
.inf_ready (dma_wready));
up_xfer_status #(.DATA_WIDTH(4)) i_xfer_status (
.up_rstn (~dma_rst),
.up_clk (dma_clk),
.up_data_status (dma_xfer_status),
.d_rst (axi_drst),
.d_clk (axi_clk),
.d_data_status (axi_xfer_status));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_dest_mm_axi (
input m_axi_aclk,
input m_axi_aresetn,
input req_valid,
output req_ready,
input [31:C_ADDR_ALIGN_BITS] req_address,
input [3:0] req_last_burst_length,
input [2:0] req_last_beat_bytes,
input enable,
output enabled,
input pause,
input sync_id,
output sync_id_ret,
output response_valid,
input response_ready,
output [1:0] response_resp,
output response_resp_eot,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
output [C_ID_WIDTH-1:0] address_id,
input data_eot,
input address_eot,
input response_eot,
input fifo_valid,
output fifo_ready,
input [C_M_AXI_DATA_WIDTH-1:0] fifo_data,
// Write address
input m_axi_awready,
output m_axi_awvalid,
output [31:0] m_axi_awaddr,
output [ 7:0] m_axi_awlen,
output [ 2:0] m_axi_awsize,
output [ 1:0] m_axi_awburst,
output [ 2:0] m_axi_awprot,
output [ 3:0] m_axi_awcache,
// Write data
output [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [(C_M_AXI_DATA_WIDTH/8)-1:0] m_axi_wstrb,
input m_axi_wready,
output m_axi_wvalid,
output m_axi_wlast,
// Write response
input m_axi_bvalid,
input [ 1:0] m_axi_bresp,
output m_axi_bready
);
parameter C_ID_WIDTH = 3;
parameter C_M_AXI_DATA_WIDTH = 64;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_DMA_LENGTH_WIDTH = 24;
wire [C_ID_WIDTH-1:0] data_id;
wire [C_ID_WIDTH-1:0] address_id;
reg [(C_M_AXI_DATA_WIDTH/8)-1:0] wstrb;
wire address_req_valid;
wire address_req_ready;
wire data_req_valid;
wire data_req_ready;
wire address_enabled;
wire data_enabled;
assign sync_id_ret = sync_id;
splitter #(
.C_NUM_M(2)
) i_req_splitter (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.s_valid(req_valid),
.s_ready(req_ready),
.m_valid({
address_req_valid,
data_req_valid
}),
.m_ready({
address_req_ready,
data_req_ready
})
);
dmac_address_generator #(
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_ID_WIDTH(C_ID_WIDTH)
) i_addr_gen (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.enable(enable),
.enabled(address_enabled),
.pause(pause),
.id(address_id),
.wait_id(request_id),
.sync_id(sync_id),
.req_valid(address_req_valid),
.req_ready(address_req_ready),
.req_address(req_address),
.req_last_burst_length(req_last_burst_length),
.eot(address_eot),
.addr_ready(m_axi_awready),
.addr_valid(m_axi_awvalid),
.addr(m_axi_awaddr),
.len(m_axi_awlen),
.size(m_axi_awsize),
.burst(m_axi_awburst),
.prot(m_axi_awprot),
.cache(m_axi_awcache)
);
wire _fifo_ready;
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_M_AXI_DATA_WIDTH)
) i_data_mover (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.enable(address_enabled),
.enabled(data_enabled),
.request_id(address_id),
.response_id(data_id),
.sync_id(sync_id),
.eot(data_eot),
.req_valid(data_req_valid),
.req_ready(data_req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_valid(fifo_valid),
.s_axi_ready(_fifo_ready),
.s_axi_data(fifo_data),
.m_axi_valid(m_axi_wvalid),
.m_axi_ready(m_axi_wready),
.m_axi_data(m_axi_wdata),
.m_axi_last(m_axi_wlast)
);
assign fifo_ready = _fifo_ready | ~enabled;
always @(*)
begin
if (data_eot & m_axi_wlast) begin
wstrb <= (1 << (req_last_beat_bytes + 1)) - 1;
end else begin
wstrb <= 8'b11111111;
end
end
assign m_axi_wstrb = wstrb;
dmac_response_handler #(
.C_ID_WIDTH(C_ID_WIDTH)
) i_response_handler (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.bvalid(m_axi_bvalid),
.bready(m_axi_bready),
.bresp(m_axi_bresp),
.enable(data_enabled),
.enabled(enabled),
.id(response_id),
.wait_id(data_id),
.sync_id(sync_id),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_resp(response_resp),
.resp_eot(response_resp_eot)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcieCore_gt_wrapper.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : gt_wrapper.v
// Description : GT Wrapper Module for 7 Series Transceiver
// Version : 19.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- GT Wrapper --------------------------------------------------------
module pcieCore_gt_wrapper #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2
parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only
parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_CHAN_BOND = 0, // PCIe channel bonding mode
parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only
parameter PCIE_LANE = 1, // PCIe number of lane
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd4, // PCIe TX electrical idle assert delay
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode
)
(
//---------- GT User Ports -----------------------------
input GT_MASTER,
input GT_GEN3,
input GT_RX_CONVERGE,
//---------- GT Clock Ports ----------------------------
input GT_GTREFCLK0,
input GT_QPLLCLK,
input GT_QPLLREFCLK,
input GT_TXUSRCLK,
input GT_RXUSRCLK,
input GT_TXUSRCLK2,
input GT_RXUSRCLK2,
input GT_OOBCLK,
input [ 1:0] GT_TXSYSCLKSEL,
input [ 1:0] GT_RXSYSCLKSEL,
output GT_TXOUTCLK,
output GT_RXOUTCLK,
output GT_CPLLLOCK,
output GT_RXCDRLOCK,
//---------- GT Reset Ports ----------------------------
input GT_CPLLPD,
input GT_CPLLRESET,
input GT_TXUSERRDY,
input GT_RXUSERRDY,
input GT_RESETOVRD,
input GT_GTTXRESET,
input GT_GTRXRESET,
input GT_TXPMARESET,
input GT_RXPMARESET,
input GT_RXCDRRESET,
input GT_RXCDRFREQRESET,
input GT_RXDFELPMRESET,
input GT_EYESCANRESET,
input GT_TXPCSRESET,
input GT_RXPCSRESET,
input GT_RXBUFRESET,
output GT_TXRESETDONE,
output GT_RXRESETDONE,
output GT_RXPMARESETDONE,
//---------- GT TX Data Ports --------------------------
input [31:0] GT_TXDATA,
input [ 3:0] GT_TXDATAK,
output GT_TXP,
output GT_TXN,
//---------- GT RX Data Ports --------------------------
input GT_RXN,
input GT_RXP,
output [31:0] GT_RXDATA,
output [ 3:0] GT_RXDATAK,
//---------- GT Command Ports --------------------------
input GT_TXDETECTRX,
input GT_TXELECIDLE,
input GT_TXCOMPLIANCE,
input GT_RXPOLARITY,
input [ 1:0] GT_TXPOWERDOWN,
input [ 1:0] GT_RXPOWERDOWN,
input [ 2:0] GT_TXRATE,
input [ 2:0] GT_RXRATE,
//---------- GT Electrical Command Ports ---------------
input [ 2:0] GT_TXMARGIN,
input GT_TXSWING,
input GT_TXDEEMPH,
input [ 4:0] GT_TXPRECURSOR,
input [ 6:0] GT_TXMAINCURSOR,
input [ 4:0] GT_TXPOSTCURSOR,
//---------- GT Status Ports ---------------------------
output GT_RXVALID,
output GT_PHYSTATUS,
output GT_RXELECIDLE,
output [ 2:0] GT_RXSTATUS,
output [ 2:0] GT_RXBUFSTATUS,
output GT_TXRATEDONE,
output GT_RXRATEDONE,
//---------- GT DRP Ports ------------------------------
input GT_DRPCLK,
input [ 8:0] GT_DRPADDR,
input GT_DRPEN,
input [15:0] GT_DRPDI,
input GT_DRPWE,
output [15:0] GT_DRPDO,
output GT_DRPRDY,
//---------- GT TX Sync Ports --------------------------
input GT_TXPHALIGN,
input GT_TXPHALIGNEN,
input GT_TXPHINIT,
input GT_TXDLYBYPASS,
input GT_TXDLYSRESET,
input GT_TXDLYEN,
output GT_TXDLYSRESETDONE,
output GT_TXPHINITDONE,
output GT_TXPHALIGNDONE,
input GT_TXPHDLYRESET,
input GT_TXSYNCMODE, // GTH
input GT_TXSYNCIN, // GTH
input GT_TXSYNCALLIN, // GTH
output GT_TXSYNCOUT, // GTH
output GT_TXSYNCDONE, // GTH
//---------- GT RX Sync Ports --------------------------
input GT_RXPHALIGN,
input GT_RXPHALIGNEN,
input GT_RXDLYBYPASS,
input GT_RXDLYSRESET,
input GT_RXDLYEN,
input GT_RXDDIEN,
output GT_RXDLYSRESETDONE,
output GT_RXPHALIGNDONE,
input GT_RXSYNCMODE, // GTH
input GT_RXSYNCIN, // GTH
input GT_RXSYNCALLIN, // GTH
output GT_RXSYNCOUT, // GTH
output GT_RXSYNCDONE, // GTH
//---------- GT Comma Alignment Ports ------------------
input GT_RXSLIDE,
output GT_RXCOMMADET,
output [ 3:0] GT_RXCHARISCOMMA,
output GT_RXBYTEISALIGNED,
output GT_RXBYTEREALIGN,
//---------- GT Channel Bonding Ports ------------------
input GT_RXCHBONDEN,
input [ 4:0] GT_RXCHBONDI,
input [ 2:0] GT_RXCHBONDLEVEL,
input GT_RXCHBONDMASTER,
input GT_RXCHBONDSLAVE,
output GT_RXCHANISALIGNED,
output [ 4:0] GT_RXCHBONDO,
//---------- GT PRBS/Loopback Ports --------------------
input [ 2:0] GT_TXPRBSSEL,
input [ 2:0] GT_RXPRBSSEL,
input GT_TXPRBSFORCEERR,
input GT_RXPRBSCNTRESET,
input [ 2:0] GT_LOOPBACK,
output GT_RXPRBSERR,
//---------- GT Debug Ports ----------------------------
output [14:0] GT_DMONITOROUT
);
//---------- Internal Signals --------------------------
wire [ 2:0] txoutclksel;
wire [ 2:0] rxoutclksel;
wire [63:0] rxdata;
wire [ 7:0] rxdatak;
wire [ 7:0] rxchariscomma;
wire rxlpmen;
wire [14:0] dmonitorout;
wire dmonitorclk;
//---------- Select CPLL and Clock Dividers ------------
localparam CPLL_REFCLK_DIV = 1;
localparam CPLL_FBDIV_45 = 5;
localparam CPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 2 :
(PCIE_REFCLK_FREQ == 1) ? 4 : 5;
localparam OUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 4 : 2;
localparam CLK25_DIV = (PCIE_REFCLK_FREQ == 2) ? 10 :
(PCIE_REFCLK_FREQ == 1) ? 5 : 4;
//---------- Select IES vs. GES ------------------------
localparam CLKMUX_PD = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? 1'd0 : 1'd1;
//---------- Select GTP CPLL configuration -------------
// PLL0/1_CFG[ 5:2] = CP1 : [ 8, 4, 2, 1] units
// PLL0/1_CFG[10:6] = CP2 : [16, 8, 4, 2, 1] units
// CP2/CP1 = 2 to 3
// (8/4=2) = 27'h01F0210 = 0000_0001_1111_0000_0010_0001_0000
// (9/3=3) = 27'h01F024C = 0000_0001_1111_0000_0010_0100_1100
// (8/3=2.67) = 27'h01F020C = 0000_0001_1111_0000_0010_0000_1100
// (7/3=2.33) = 27'h01F01CC = 0000_0001_1111_0000_0001_1100_1100
// (6/3=2) = 27'h01F018C = 0000_0001_1111_0000_0001_1000_1100
// (5/3=1.67) = 27'h01F014C = 0000_0001_1111_0000_0001_0100_1100
// (6/2=3) = 27'h01F0188 = 0000_0001_1111_0000_0001_1000_1000
//---------- Select GTX CPLL configuration -------------
// CPLL_CFG[ 5: 2] = CP1 : [ 8, 4, 2, 1] units
// CPLL_CFG[22:18] = CP2 : [16, 8, 4, 2, 1] units
// CP2/CP1 = 2 to 3
// (9/3=3) = 1010_0100_0000_0111_1100_1100
//------------------------------------------------------
localparam CPLL_CFG = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? 24'hB407CC : 24'hA407CC;
//---------- Select TX XCLK ----------------------------
// TXOUT for TX Buffer Use
// TXUSR for TX Buffer Bypass
//------------------------------------------------------
localparam TX_XCLK_SEL = (PCIE_TXBUF_EN == "TRUE") ? "TXOUT" : "TXUSR";
//---------- Select TX Receiver Detection Configuration
localparam TX_RXDETECT_CFG = (PCIE_REFCLK_FREQ == 2) ? 14'd250 :
(PCIE_REFCLK_FREQ == 1) ? 14'd125 : 14'd100;
localparam TX_RXDETECT_REF = (((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) && (PCIE_SIM_MODE == "FALSE")) ? 3'b000 : 3'b011;
//---------- Select PCS_RSVD_ATTR ----------------------
// [0]: 1 = enable latch when bypassing TX buffer, 0 = disable latch when using TX buffer
// [1]: 1 = enable manual TX sync, 0 = enable auto TX sync
// [2]: 1 = enable manual RX sync, 0 = enable auto RX sync
// [3]: 1 = select external clock for OOB 0 = select reference clock for OOB
// [6]: 1 = enable DMON 0 = disable DMON
// [7]: 1 = filter stale TX[P/N] data when exiting TX electrical idle
// [8]: 1 = power up OOB 0 = power down OOB
//------------------------------------------------------
localparam OOBCLK_SEL = (PCIE_OOBCLK_MODE == 0) ? 1'd0 : 1'd1; // GTX
localparam RXOOB_CLK_CFG = (PCIE_OOBCLK_MODE == 0) ? "PMA" : "FABRIC"; // GTH/GTP
localparam PCS_RSVD_ATTR = ((PCIE_USE_MODE == "1.0") && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd1} :
((PCIE_USE_MODE == "1.0") && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd0} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd7} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd6} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd5} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd4} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd3} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd2} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd1} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd0} : {44'h0000000001C, OOBCLK_SEL, 3'd7};
//---------- Select RXCDR_CFG --------------------------
//---------- GTX Note ----------------------------------
// For GTX PCIe Gen1/Gen2 with 8B/10B, the following CDR setting may provide more margin
// Async 72'h03_8000_23FF_1040_0020
// Sync: 72'h03_0000_23FF_1040_0020
//------------------------------------------------------
localparam RXCDR_CFG_GTX = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ?
((PCIE_ASYNC_EN == "TRUE") ? 72'b0000_0010_0000_0111_1111_1110_0010_0000_0110_0000_0010_0001_0001_0000_0000000000010000
: 72'h11_07FE_4060_0104_0000): // IES setting
((PCIE_ASYNC_EN == "TRUE") ? 72'h03_8000_23FF_1020_0020 //
: 72'h03_0000_23FF_1020_0020); // optimized for GES silicon
localparam RXCDR_CFG_GTH = (PCIE_USE_MODE == "2.0") ?
((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0011_07FE_4060_2104_1010
: 83'h0_0011_07FE_4060_0104_1010): // Optimized for IES silicon
((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0020_07FE_2000_C208_8018
: 83'h0_0020_07FE_2000_C208_0018); // Optimized for 1.2 silicon
localparam RXCDR_CFG_GTP = ((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0001_07FE_4060_2104_1010
: 83'h0_0001_07FE_4060_0104_1010); // Optimized for IES silicon
//---------- Select TX and RX Sync Mode ----------------
localparam TXSYNC_OVRD = (PCIE_TXSYNC_MODE == 1) ? 1'd0 : 1'd1;
localparam RXSYNC_OVRD = (PCIE_TXSYNC_MODE == 1) ? 1'd0 : 1'd1;
localparam TXSYNC_MULTILANE = (PCIE_LANE == 1) ? 1'd0 : 1'd1;
localparam RXSYNC_MULTILANE = (PCIE_LANE == 1) ? 1'd0 : 1'd1;
//---------- Select Clock Correction Min and Max Latency
// CLK_COR_MIN_LAT = Larger of (2 * RXCHBONDLEVEL + 13) or (CHAN_BOND_MAX_SKEW + 11)
// = 13 when PCIE_LANE = 1
// CLK_COR_MAX_LAT = CLK_COR_MIN_LAT + CLK_COR_SEQ_LEN + 1
// = CLK_COR_MIN_LAT + 2
//------------------------------------------------------
//---------- CLK_COR_MIN_LAT Look-up Table -------------
// Lane | One-Hop | Daisy-Chain | Binary-Tree
//------------------------------------------------------
// 0 | 13 | 13 | 13
// 1 | 15 to 18 | 15 to 18 | 15 to 18
// 2 | 15 to 18 | 17 to 18 | 15 to 18
// 3 | 15 to 18 | 19 | 17 to 18
// 4 | 15 to 18 | 21 | 17 to 18
// 5 | 15 to 18 | 23 | 19
// 6 | 15 to 18 | 25 | 19
// 7 | 15 to 18 | 27 | 21
//------------------------------------------------------
localparam CLK_COR_MIN_LAT = ((PCIE_LANE == 8) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 27 : 21) :
((PCIE_LANE == 7) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 25 : 19) :
((PCIE_LANE == 6) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 23 : 19) :
((PCIE_LANE == 5) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 21 : 18) :
((PCIE_LANE == 4) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 19 : 18) :
((PCIE_LANE == 3) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 18 : 18) :
((PCIE_LANE == 2) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 18 : 18) :
((PCIE_LANE == 1) || (PCIE_CHAN_BOND_EN == "FALSE")) ? 13 : 18;
localparam CLK_COR_MAX_LAT = CLK_COR_MIN_LAT + 2;
//---------- Simulation Speedup ------------------------
//localparam CFOK_CFG_GTH = (PCIE_SIM_MODE == "TRUE") ? 42'h240_0004_0F80 : 42'h248_0004_0E80; // [8] : 1 = Skip CFOK
//localparam CFOK_CFG_GTP = (PCIE_SIM_MODE == "TRUE") ? 43'h000_0000_0000 : 43'h000_0000_0100; // [2] : 1 = Skip CFOK
//---------- Select [TX/RX]OUTCLK ----------------------
assign txoutclksel = GT_MASTER ? 3'd3 : 3'd0;
assign rxoutclksel = ((PCIE_DEBUG_MODE == 1) || ((PCIE_ASYNC_EN == "TRUE") && GT_MASTER)) ? 3'd2 : 3'd0;
//---------- Select DFE vs. LPM ------------------------
// Gen1/2 = Use LPM by default. Option to use DFE.
// Gen3 = Use DFE by default. Option to use LPM.
//------------------------------------------------------
assign rxlpmen = GT_GEN3 ? ((PCIE_LPM_DFE_GEN3 == "LPM") ? 1'd1 : 1'd0) : ((PCIE_LPM_DFE == "LPM") ? 1'd1 : 1'd0);
//---------- Generate DMONITOR Clock Buffer for Debug ------
generate if (PCIE_DEBUG_MODE == 1)
begin : dmonitorclk_i
//---------- DMONITOR CLK ------------------------------
BUFG dmonitorclk_i
(
//---------- Input ---------------------------------
.I (dmonitorout[7]),
//---------- Output --------------------------------
.O (dmonitorclk)
);
end
else
begin : dmonitorclk_i_disable
assign dmonitorclk = 1'd0;
end
endgenerate
//---------- Select GTX or GTH or GTP ------------------------------------------
// Notes : Attributes that are commented out always use the GT default settings
//------------------------------------------------------------------------------
generate if (PCIE_GT_DEVICE == "GTP")
begin : gtp_channel
//---------- GTP Channel Module --------------------------------------------
GTPE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION (PCIE_USE_MODE), //
//---------- Clock Attributes ------------------------------------------
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
//.TX_CLKMUX_EN ( 1'b1), // GTP rename
//.RX_CLKMUX_EN ( 1'b1), // GTP rename
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
//.OUTREFCLK_SEL_INV ( 2'b11), //
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME ( 5'b00001), //
.RXPCSRESET_TIME ( 5'b00001), //
.TXPMARESET_TIME ( 5'b00011), //
.RXPMARESET_TIME ( 5'b00011), // Optimized for sim
//.RXISCANRESET_TIME ( 5'b00001), //
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_REF ( 3'b011), //
.RX_CM_SEL ( 2'd3), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable
.RX_CM_TRIM ( 4'b1010), // Select 800mV, Changed from 3 to 4-bits, optimized for IES
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim
.TX_EIDLE_DEASSERT_DELAY ( 3'b010), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), //
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 5'b10100), // 6.0 dB
.TX_DEEMPH1 ( 5'b01011), // 3.5 dB
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_PREDRIVER_MODE ( 1'b0), // GTP
//---------- Status Attributes -----------------------------------------
//.RX_SIG_VALID_DLY ( 4), // CHECK
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (48'h0000_0000_0100), // [8] : 1 = OOB power-up
//---------- PMA Attributes -------------------------------------------
//.CLK_COMMON_SWING ( 1'b0), // GTP new
//.PMA_RSV (32'd0), //
.PMA_RSV2 (32'h00002040), // Optimized for GES
//.PMA_RSV3 ( 2'd0), //
//.PMA_RSV4 ( 4'd0), // Changed from 15 to 4-bits
//.PMA_RSV5 ( 1'd0), // Changed from 4 to 1-bit
//.PMA_RSV6 ( 1'd0), // GTP new
//.PMA_RSV7 ( 1'd0), // GTP new
.RX_BIAS_CFG (16'h0F33), // Optimized for IES
.TERM_RCAL_CFG (15'b100001000010000), // Optimized for IES
.TERM_RCAL_OVRD ( 3'b000), // Optimized for IES
//---------- TX PI ----------------------------------------------------
//.TXPI_CFG0 ( 2'd0), //
//.TXPI_CFG1 ( 2'd0), //
//.TXPI_CFG2 ( 2'd0), //
//.TXPI_CFG3 ( 1'd0), //
//.TXPI_CFG4 ( 1'd0), //
//.TXPI_CFG5 ( 3'd000), //
//.TXPI_GREY_SEL ( 1'd0), //
//.TXPI_INVSTROBE_SEL ( 1'd0), //
//.TXPI_PPMCLK_SEL ("TXUSRCLK2"), //
//.TXPI_PPM_CFG ( 8'd0), //
//.TXPI_SYNFREQ_PPM ( 3'd0), //
//---------- RX PI -----------------------------------------------------
.RXPI_CFG0 ( 3'd0), // Changed from 3 to 2-bits, Optimized for IES
.RXPI_CFG1 ( 1'd1), // Changed from 2 to 1-bits, Optimized for IES
.RXPI_CFG2 ( 1'd1), // Changed from 2 to 1-bits, Optimized for IES
//---------- CDR Attributes ---------------------------------------------
//.RXCDR_CFG (72'b0000_001000000_11111_11111_001000000_011_0000111_000_001000_010000_100000000000000), // CHECK
.RXCDR_CFG (RXCDR_CFG_GTP), // Optimized for IES
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001) CHECK
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), //
//.RXCDRPHRESET_TIME ( 5'b00001), //
//---------- LPM Attributes --------------------------------------------
//.RXLPMRESET_TIME ( 7'b0001111), // GTP new
//.RXLPM_BIAS_STARTUP_DISABLE ( 1'b0), // GTP new
.RXLPM_CFG ( 4'b0110), // GTP new, optimized for IES
//.RXLPM_CFG1 ( 1'b0), // GTP new
//.RXLPM_CM_CFG ( 1'b0), // GTP new
.RXLPM_GC_CFG ( 9'b111100010), // GTP new, optimized for IES
.RXLPM_GC_CFG2 ( 3'b001), // GTP new, optimized for IES
//.RXLPM_HF_CFG (14'b00001111110000), //
.RXLPM_HF_CFG2 ( 5'b01010), // GTP new
//.RXLPM_HF_CFG3 ( 4'b0000), // GTP new
.RXLPM_HOLD_DURING_EIDLE ( 1'b1), // GTP new
.RXLPM_INCM_CFG ( 1'b1), // GTP new, optimized for IES
.RXLPM_IPCM_CFG ( 1'b0), // GTP new, optimized for IES
//.RXLPM_LF_CFG (18'b000000001111110000), //
.RXLPM_LF_CFG2 ( 5'b01010), // GTP new, optimized for IES
.RXLPM_OSINT_CFG ( 3'b100), // GTP new, optimized for IES
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'h0080), // CHECK
.RXOSCALRESET_TIME (5'b00011), // Optimized for IES
.RXOSCALRESET_TIMEOUT (5'b00000), // Disable timeout, Optimized for IES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CLK_PHASE_SEL ( 1'b0), //
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("TRUE"), //
//.ES_HORZ_OFFSET (12'd0), //
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
.TXPHDLY_CFG (24'h084020), // [19] : 1 = full range, 0 = half range
.TXDLY_CFG (16'h001F), //
.TXDLY_LCFG ( 9'h030), //
.TXDLY_TAP_CFG (16'd0), //
.TXSYNC_OVRD (TXSYNC_OVRD), //
.TXSYNC_MULTILANE (TXSYNC_MULTILANE), //
.TXSYNC_SKIP_DA (1'b0), //
//---------- RX Sync Attributes ----------------------------------------
.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // [19] : 1 = full range, 0 = half range
.RXDLY_CFG (16'h001F), //
.RXDLY_LCFG ( 9'h030), //
.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
.RXSYNC_OVRD (RXSYNC_OVRD), //
.RXSYNC_MULTILANE (RXSYNC_MULTILANE), //
.RXSYNC_SKIP_DA (1'b0), //
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE (4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE ( 3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes ---------------------------------
.LOOPBACK_CFG ( 1'd0), // Enable latch when bypassing TX buffer, equivalent to GTX PCS_RSVD_ATTR[0]
.RXPRBS_ERR_LOOPBACK ( 1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes --------------------------------------
.TXOOB_CFG ( 1'd1), // Filter stale TX data when exiting TX electrical idle, equivalent to GTX PCS_RSVD_ATTR[7]
//.RXOOB_CFG ( 7'b0000110), //
.RXOOB_CLK_CFG (RXOOB_CLK_CFG), //
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_PLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000B01), //
.RX_DEBUG_CFG (14'h0000), // Optimized for IES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0) //
//---------- GTP -------------------------------------------------------
//.ACJTAG_DEBUG_MODE (1'd0), //
//.ACJTAG_MODE (1'd0), //
//.ACJTAG_RESET (1'd0), //
//.ADAPT_CFG0 (20'd0), //
.CFOK_CFG (43'h490_0004_0E80), // Changed from 42 to 43-bits, Optimized for IES
.CFOK_CFG2 ( 7'b010_0000), // Changed from 6 to 7-bits, Optimized for IES
.CFOK_CFG3 ( 7'b010_0000), // Changed from 6 to 7-bits, Optimized for IES
.CFOK_CFG4 ( 1'd0), // GTP new, Optimized for IES
.CFOK_CFG5 ( 2'd0), // GTP new, Optimized for IES
.CFOK_CFG6 ( 4'd0) // GTP new, Optimized for IES
)
gtpe2_channel_i
(
//---------- Clock -----------------------------------------------------
.PLL0CLK (GT_QPLLCLK), //
.PLL1CLK (1'd0), //
.PLL0REFCLK (GT_QPLLREFCLK), //
.PLL1REFCLK (1'd0), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CLKRSVD0 (1'd0), //
.CLKRSVD1 (1'd0), //
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
//---------- Reset -----------------------------------------------------
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA (GT_TXDATA), //
.TXCHARISK (GT_TXDATAK), //
.GTPTXP (GT_TXP), // GTP
.GTPTXN (GT_TXN), // GTP
//---------- RX Data ---------------------------------------------------
.GTPRXP (GT_RXP), // GTP
.GTPRXN (GT_RXN), // GTP
.RXDATA (rxdata[31:0]), //
.RXCHARISK (rxdatak[3:0]), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( 1'd0), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({3'd0, GT_TXCOMPLIANCE}), // Changed from 8 to 4-bits
.TXCHARDISPVAL ( 4'd0), // Changed from 8 to 4-bits
.TXPOLARITY ( 1'd0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
.TXRATEMODE (1'b0), //
.RXRATEMODE (1'b0), //
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1100), // Select 850mV
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMRESET ( 1'd0), // GTP new
.RXLPMOSINTNTRLEN ( 1'd0), // GTP new
.RXLPMHFHOLD ( 1'd0), //
.RXLPMHFOVRDEN ( 1'd0), //
.RXLPMLFHOLD ( 1'd0), //
.RXLPMLFOVRDEN ( 1'd0), //
.PMARSVDIN0 ( 1'd0), // GTP new
.PMARSVDIN1 ( 1'd0), // GTP new
.PMARSVDIN2 ( 1'd0), // GTP new
.PMARSVDIN3 ( 1'd0), // GTP new
.PMARSVDIN4 ( 1'd0), // GTP new
.GTRSVD (16'd0), //
.PMARSVDOUT0 (), // GTP new
.PMARSVDOUT1 (), // GTP new
.DMONITOROUT (dmonitorout), // GTP 15-bits
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'd0), //
.RXCDROVRDEN (1'd0), //
//---------- PI --------------------------------------------------------
.TXPIPPMEN (1'd0), //
.TXPIPPMOVRDEN (1'd0), //
.TXPIPPMPD (1'd0), //
.TXPIPPMSEL (1'd0), //
.TXPIPPMSTEPSIZE (5'd0), //
.TXPISOPD (1'd0), // GTP new
//---------- DFE -------------------------------------------------------
.RXDFEXYDEN (1'd0), //
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), // Optimized for IES
.RXOSOVRDEN (1'd0), // Optimized for IES
.RXOSINTEN (1'd1), // Optimized for IES
.RXOSINTHOLD (1'd0), // Optimized for IES
.RXOSINTNTRLEN (1'd0), // Optimized for IES
.RXOSINTOVRDEN (1'd0), // Optimized for IES
.RXOSINTPD (1'd0), // GTP new, Optimized for IES
.RXOSINTSTROBE (1'd0), // Optimized for IES
.RXOSINTTESTOVRDEN (1'd0), // Optimized for IES
.RXOSINTCFG (4'b0010), // Optimized for IES
.RXOSINTID0 (4'd0), // Optimized for IES
.RXOSINTDONE (), //
.RXOSINTSTARTED (), //
.RXOSINTSTROBEDONE (), //
.RXOSINTSTROBESTARTED (), //
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'd0), //
.EYESCANDATAERROR (), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (GT_TXPHDLYRESET), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
.TXSYNCMODE (GT_TXSYNCMODE), //
.TXSYNCIN (GT_TXSYNCIN), //
.TXSYNCALLIN (GT_TXSYNCALLIN), //
.TXSYNCDONE (GT_TXSYNCDONE), //
.TXSYNCOUT (GT_TXSYNCOUT), //
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
.RXSYNCMODE (GT_RXSYNCMODE), //
.RXSYNCIN (GT_RXSYNCIN), //
.RXSYNCALLIN (GT_RXSYNCALLIN), //
.RXSYNCDONE (GT_RXSYNCDONE), //
.RXSYNCOUT (GT_RXSYNCOUT), //
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN (1'd1), //
.RXMCOMMAALIGNEN (1'd1), // No Gen3 support in GTP
.RXPCOMMAALIGNEN (1'd1), // No Gen3 support in GTP
.RXSLIDE (GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma[3:0]), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI[3:0]), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO[3:0]), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (4'd0), //
.TX8B10BEN (1'b1), // No Gen3 support in GTP
.RX8B10BEN (1'b1), // No Gen3 support in GTP
.RXDISPERR (), //
.RXNOTINTABLE (), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS/Loopback ---------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.SIGVALIDCLK (GT_OOBCLK), // Optimized for debug
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
//---------- GTP -------------------------------------------------------
.RXADAPTSELTEST (14'd0), //
.DMONFIFORESET ( 1'd0), //
.DMONITORCLK (dmonitorclk), //
.RXOSCALRESET ( 1'd0), //
.RXPMARESETDONE (GT_RXPMARESETDONE), // GTP
.TXPMARESETDONE () //
);
assign GT_CPLLLOCK = 1'b0;
end
else if (PCIE_GT_DEVICE == "GTH")
begin : gth_channel
//---------- GTH Channel Module --------------------------------------------
GTHE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_CPLLREFCLK_SEL (3'b001), //
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION ("2.0"), //
//---------- Clock Attributes ------------------------------------------
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), //
.CPLL_FBDIV_45 (CPLL_FBDIV_45), //
.CPLL_FBDIV (CPLL_FBDIV), //
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
.TX_CLKMUX_PD ( 1'b1), // GTH
.RX_CLKMUX_PD ( 1'b1), // GTH
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
.OUTREFCLK_SEL_INV ( 2'b11), //
.CPLL_CFG (29'h00A407CC), // Changed from 24 to 29-bits, Optimized for PCIe PLL BW
.CPLL_INIT_CFG (24'h00001E), // Optimized for IES
.CPLL_LOCK_CFG (16'h01E8), // Optimized for IES
//.USE_PCS_CLK_PHASE_SEL ( 1'd0) // GTH new
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME (5'b00001), //
.RXPCSRESET_TIME (5'b00001), //
.TXPMARESET_TIME (5'b00011), //
.RXPMARESET_TIME (5'b00011), // Optimized for sim and for DRP
//.RXISCANRESET_TIME (5'b00001), //
//.RESET_POWERSAVE_DISABLE ( 1'd0), // GTH new
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.TX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.RX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_PRECHARGE_TIME (17'h00001), // GTH new, Optimized for sim
.TX_RXDETECT_REF ( 3'b011), //
.RX_CM_SEL ( 2'b11), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable, optimized for silicon
.RX_CM_TRIM ( 4'b1010), // Select 800mV, Changed from 3 to 4-bits, optimized for silicon
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim (3'd4)
.TX_EIDLE_DEASSERT_DELAY ( 3'b100), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), // Optimized for sim
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 6'b010100), // 6.0 dB, optimized for compliance, changed from 5 to 6-bits
.TX_DEEMPH1 ( 6'b001011), // 3.5 dB, optimized for compliance, changed from 5 to 6-bits
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_QPI_STATUS_EN ( 1'b0), //
//---------- Status Attributes -----------------------------------------
.RX_SIG_VALID_DLY (4), // Optimized for sim
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (48'h0000_0000_0140), // [8] : 1 = OOB power-up, [6] : 1 = DMON enable, Optimized for IES
//---------- PMA Attributes --------------------------------------------
.PMA_RSV (32'h00000080), // Optimized for IES
.PMA_RSV2 (32'h1C00000A), // Changed from 16 to 32-bits, Optimized for IES
//.PMA_RSV3 ( 2'h0), //
.PMA_RSV4 (15'h0008), // GTH new, Optimized for IES
//.PMA_RSV5 ( 4'h00), // GTH new
.RX_BIAS_CFG (24'h0C0010), // Changed from 12 to 24-bits, Optimized for IES
.TERM_RCAL_CFG (15'b100001000010000), // Changed from 5 to 15-bits, Optimized for IES
.TERM_RCAL_OVRD ( 3'b000), // Changed from 1 to 3-bits, Optimized for IES
//---------- TX PI -----------------------------------------------------
//.TXPI_CFG0 ( 2'd0), // GTH new
//.TXPI_CFG1 ( 2'd0), // GTH new
//.TXPI_CFG2 ( 2'd0), // GTH new
//.TXPI_CFG3 ( 1'd0), // GTH new
//.TXPI_CFG4 ( 1'd0), // GTH new
//.TXPI_CFG5 ( 3'b100), // GTH new
//.TXPI_GREY_SEL ( 1'd0), // GTH new
//.TXPI_INVSTROBE_SEL ( 1'd0), // GTH new
//.TXPI_PPMCLK_SEL ("TXUSRCLK2"), // GTH new
//.TXPI_PPM_CFG ( 8'd0), // GTH new
//.TXPI_SYNFREQ_PPM ( 3'd0), // GTH new
//---------- RX PI -----------------------------------------------------
.RXPI_CFG0 (2'b00), // GTH new
.RXPI_CFG1 (2'b11), // GTH new
.RXPI_CFG2 (2'b11), // GTH new
.RXPI_CFG3 (2'b11), // GTH new
.RXPI_CFG4 (1'b0), // GTH new
.RXPI_CFG5 (1'b0), // GTH new
.RXPI_CFG6 (3'b100), // GTH new
//---------- CDR Attributes --------------------------------------------
.RXCDR_CFG (RXCDR_CFG_GTH), //
//.RXCDR_CFG (83'h0_0011_07FE_4060_0104_1010), // A. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-000ppm, default, converted from GTX GES VnC,(2 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_4060_2104_1010), // B. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-300ppm, default, converted from GTX GES VnC,(2 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_2060_0104_1010), // C. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-000ppm, converted from GTX GES recommended, (3 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_2060_2104_1010), // D. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-300ppm, converted from GTX GES recommended, (3 Gen1)
//.RXCDR_CFG (83'h0_0001_07FE_1060_0110_1010), // E. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-000ppm, default, (3 Gen2)
//.RXCDR_CFG (83'h0_0001_07FE_1060_2110_1010), // F. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-300ppm, default, (3 Gen2)
//.RXCDR_CFG (83'h0_0011_07FE_1060_0110_1010), // G. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-000ppm, converted from GTX GES recommended, (3 Gen2)
//.RXCDR_CFG (83'h0_0011_07FE_1060_2110_1010), // H. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-300ppm, converted from GTX GES recommended, (2 Gen1)
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001)
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), // optimized for IES
//.RXCDRPHRESET_TIME ( 5'b00001), // optimized for IES
//---------- LPM Attributes --------------------------------------------
.RXLPM_HF_CFG (14'h0200), // Optimized for IES
.RXLPM_LF_CFG (18'h09000), // Changed from 14 to 18-bits, Optimized for IES
//---------- DFE Attributes --------------------------------------------
.RXDFELPMRESET_TIME ( 7'h0F), // Optimized for IES
.RX_DFE_AGC_CFG0 ( 2'h0), // GTH new, optimized for IES
.RX_DFE_AGC_CFG1 ( 3'h4), // GTH new, optimized for IES, DFE
.RX_DFE_AGC_CFG2 ( 4'h0), // GTH new, optimized for IES
.RX_DFE_AGC_OVRDEN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_GAIN_CFG (23'h0020C0), // Optimized for IES
.RX_DFE_H2_CFG (12'h000), // Optimized for IES
.RX_DFE_H3_CFG (12'h040), // Optimized for IES
.RX_DFE_H4_CFG (11'h0E0), // Optimized for IES
.RX_DFE_H5_CFG (11'h0E0), // Optimized for IES
.RX_DFE_H6_CFG (11'h020), // GTH new, optimized for IES
.RX_DFE_H7_CFG (11'h020), // GTH new, optimized for IES
.RX_DFE_KL_CFG (33'h000000310), // Changed from 13 to 33-bits, optimized for IES
.RX_DFE_KL_LPM_KH_CFG0 ( 2'h2), // GTH new, optimized for IES, DFE
.RX_DFE_KL_LPM_KH_CFG1 ( 3'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KH_CFG2 ( 4'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KH_OVRDEN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_CFG0 ( 2'h2), // GTH new, optimized for IES, DFE
.RX_DFE_KL_LPM_KL_CFG1 ( 3'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_CFG2 ( 4'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_OVRDEN ( 1'b1), // GTH new, optimized for IES
.RX_DFE_LPM_CFG (16'h0080), // Optimized for IES
.RX_DFELPM_CFG0 ( 4'h6), // GTH new, optimized for IES
.RX_DFELPM_CFG1 ( 4'h0), // GTH new, optimized for IES
.RX_DFELPM_KLKH_AGC_STUP_EN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_LPM_HOLD_DURING_EIDLE ( 1'h1), // PCIe use mode
.RX_DFE_ST_CFG (54'h00_C100_000C_003F), // GTH new, optimized for IES
.RX_DFE_UT_CFG (17'h03800), // Optimized for IES
.RX_DFE_VP_CFG (17'h03AA3), // Optimized for IES
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'h0080), // Optimized for IES
.A_RXOSCALRESET ( 1'd0), // GTH new, optimized for IES
.RXOSCALRESET_TIME ( 5'b00011), // GTH new, optimized for IES
.RXOSCALRESET_TIMEOUT ( 5'b00000), // GTH new, disable timeout, optimized for IES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CLK_PHASE_SEL ( 1'd0), // GTH new
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("TRUE"), // Optimized for IES
.ES_HORZ_OFFSET (12'h000), // Optimized for IES
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
//.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
//.TXPHDLY_CFG (24'h084020), // [19] : 1 = full range, 0 = half range
//.TXDLY_CFG (16'h001F), //
//.TXDLY_LCFG ( 9'h030), //
//.TXDLY_TAP_CFG (16'd0), //
.TXSYNC_OVRD (TXSYNC_OVRD), // GTH new
.TXSYNC_MULTILANE (TXSYNC_MULTILANE), // GTH new
.TXSYNC_SKIP_DA (1'b0), // GTH new
//---------- RX Sync Attributes ----------------------------------------
//.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // [19] : 1 = full range, 0 = half range
//.RXDLY_CFG (16'h001F), //
//.RXDLY_LCFG ( 9'h030), //
//.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
.RXSYNC_OVRD (RXSYNC_OVRD), // GTH new
.RXSYNC_MULTILANE (RXSYNC_MULTILANE), // GTH new
.RXSYNC_SKIP_DA (1'b0), // GTH new
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE (3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes --------------------------------
.LOOPBACK_CFG ( 1'd1), // GTH new, enable latch when bypassing TX buffer, equivalent to GTX PCS_RSVD_ATTR[0]
.RXPRBS_ERR_LOOPBACK ( 1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes -------------------------------------
.TXOOB_CFG ( 1'd1), // GTH new, filter stale TX data when exiting TX electrical idle, equivalent to GTX PCS_RSVD_ATTR[7]
//.RXOOB_CFG ( 7'b0000110), //
.RXOOB_CLK_CFG (RXOOB_CLK_CFG), // GTH new
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_CPLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000AB1), // Optimized for debug; [7:4] : 1011 = AGC
//.DMONITOR_CFG (24'h000AB1), // Optimized for debug; [7:4] : 0000 = CDR FSM
.RX_DEBUG_CFG (14'b00000011000000), // Changed from 12 to 14-bits, optimized for IES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0), //
//---------- GTH -------------------------------------------------------
//.ACJTAG_DEBUG_MODE ( 1'd0), // GTH new
//.ACJTAG_MODE ( 1'd0), // GTH new
//.ACJTAG_RESET ( 1'd0), // GTH new
.ADAPT_CFG0 (20'h00C10), // GTH new, optimized for IES
.CFOK_CFG (42'h248_0004_0E80), // GTH new, optimized for IES, [8] : 1 = Skip CFOK
.CFOK_CFG2 ( 6'b100000), // GTH new, optimized for IES
.CFOK_CFG3 ( 6'b100000) // GTH new, optimized for IES
)
gthe2_channel_i
(
//---------- Clock -----------------------------------------------------
.GTGREFCLK (1'd0), //
.GTREFCLK0 (GT_GTREFCLK0), //
.GTREFCLK1 (1'd0), //
.GTNORTHREFCLK0 (1'd0), //
.GTNORTHREFCLK1 (1'd0), //
.GTSOUTHREFCLK0 (1'd0), //
.GTSOUTHREFCLK1 (1'd0), //
.QPLLCLK (GT_QPLLCLK), //
.QPLLREFCLK (GT_QPLLREFCLK), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CPLLREFCLKSEL (3'd1), //
.CPLLLOCKDETCLK (1'd0), //
.CPLLLOCKEN (1'd1), //
.CLKRSVD0 (1'd0), // GTH
.CLKRSVD1 (1'd0), // GTH
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.CPLLLOCK (GT_CPLLLOCK), //
.CPLLREFCLKLOST (), //
.CPLLFBCLKLOST (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
.GTREFCLKMONITOR (), //
//---------- Reset -----------------------------------------------------
.CPLLPD (GT_CPLLPD), //
.CPLLRESET (GT_CPLLRESET), //
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA ({32'd0, GT_TXDATA}), //
.TXCHARISK ({ 4'd0, GT_TXDATAK}), //
.GTHTXP (GT_TXP), // GTH
.GTHTXN (GT_TXN), // GTH
//---------- RX Data ---------------------------------------------------
.GTHRXP (GT_RXP), // GTH
.GTHRXN (GT_RXN), // GTH
.RXDATA (rxdata), //
.RXCHARISK (rxdatak), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( 1'd0), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({7'd0, GT_TXCOMPLIANCE}), //
.TXCHARDISPVAL ( 8'd0), //
.TXPOLARITY ( 1'd0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
.TXRATEMODE (1'd0), // GTH
.RXRATEMODE (1'd0), // GTH
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1111), // Select 850mV
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMEN (rxlpmen), // ***
.RXLPMHFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXLPMHFOVRDEN ( 1'd0), //
.RXLPMLFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXLPMLFKLOVRDEN ( 1'd0), //
.TXQPIBIASEN ( 1'd0), //
.TXQPISTRONGPDOWN ( 1'd0), //
.TXQPIWEAKPUP ( 1'd0), //
.RXQPIEN ( 1'd0), // Optimized for IES
.PMARSVDIN ( 5'd0), //
.GTRSVD (16'd0), //
.TXQPISENP (), //
.TXQPISENN (), //
.RXQPISENP (), //
.RXQPISENN (), //
.DMONITOROUT (dmonitorout), // GTH 15-bits.
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDIN2 ( 5'd0), //
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'd0), //
.RXCDROVRDEN (1'd0), //
//---------- PI --------------------------------------------------------
.TXPIPPMEN (1'd0), // GTH new
.TXPIPPMOVRDEN (1'd0), // GTH new
.TXPIPPMPD (1'd0), // GTH new
.TXPIPPMSEL (1'd0), // GTH new
.TXPIPPMSTEPSIZE (5'd0), // GTH new
//---------- DFE -------------------------------------------------------
.RXDFELPMRESET (GT_RXDFELPMRESET), //
.RXDFEAGCTRL (5'b10000), // GTH new, optimized for IES
.RXDFECM1EN (1'd0), //
.RXDFEVSEN (1'd0), //
.RXDFETAP2HOLD (1'd0), //
.RXDFETAP2OVRDEN (1'd0), //
.RXDFETAP3HOLD (1'd0), //
.RXDFETAP3OVRDEN (1'd0), //
.RXDFETAP4HOLD (1'd0), //
.RXDFETAP4OVRDEN (1'd0), //
.RXDFETAP5HOLD (1'd0), //
.RXDFETAP5OVRDEN (1'd0), //
.RXDFETAP6HOLD (1'd0), // GTH new
.RXDFETAP6OVRDEN (1'd0), // GTH new
.RXDFETAP7HOLD (1'd0), // GTH new
.RXDFETAP7OVRDEN (1'd0), // GTH new
.RXDFEAGCHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXDFEAGCOVRDEN (rxlpmen), //
.RXDFELFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXDFELFOVRDEN (1'd0), //
.RXDFEUTHOLD (1'd0), //
.RXDFEUTOVRDEN (1'd0), //
.RXDFEVPHOLD (1'd0), //
.RXDFEVPOVRDEN (1'd0), //
.RXDFEXYDEN (1'd1), // Optimized for IES
.RXMONITORSEL (2'd0), //
.RXDFESLIDETAP (5'd0), // GTH new
.RXDFESLIDETAPID (6'd0), // GTH new
.RXDFESLIDETAPHOLD (1'd0), // GTH new
.RXDFESLIDETAPOVRDEN (1'd0), // GTH new
.RXDFESLIDETAPADAPTEN (1'd0), // GTH new
.RXDFESLIDETAPINITOVRDEN (1'd0), // GTH new
.RXDFESLIDETAPONLYADAPTEN (1'd0), // GTH new
.RXDFESLIDETAPSTROBE (1'd0), // GTH new
.RXMONITOROUT (), //
.RXDFESLIDETAPSTARTED (), // GTH new
.RXDFESLIDETAPSTROBEDONE (), // GTH new
.RXDFESLIDETAPSTROBESTARTED (), // GTH new
.RXDFESTADAPTDONE (), // GTH new
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), // optimized for IES
.RXOSOVRDEN (1'd0), // optimized for IES
.RXOSINTEN (1'd1), // GTH new, optimized for IES
.RXOSINTHOLD (1'd0), // GTH new, optimized for IES
.RXOSINTNTRLEN (1'd0), // GTH new, optimized for IES
.RXOSINTOVRDEN (1'd0), // GTH new, optimized for IES
.RXOSINTSTROBE (1'd0), // GTH new, optimized for IES
.RXOSINTTESTOVRDEN (1'd0), // GTH new, optimized for IES
.RXOSINTCFG (4'b0110), // GTH new, optimized for IES
.RXOSINTID0 (4'b0000), // GTH new, optimized for IES
.RXOSCALRESET ( 1'd0), // GTH, optimized for IES
.RSOSINTDONE (), // GTH new
.RXOSINTSTARTED (), // GTH new
.RXOSINTSTROBEDONE (), // GTH new
.RXOSINTSTROBESTARTED (), // GTH new
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'd0), //
.EYESCANDATAERROR (), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (GT_TXPHDLYRESET), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
.TXSYNCMODE (GT_TXSYNCMODE), // GTH
.TXSYNCIN (GT_TXSYNCIN), // GTH
.TXSYNCALLIN (GT_TXSYNCALLIN), // GTH
.TXSYNCDONE (GT_TXSYNCDONE), // GTH
.TXSYNCOUT (GT_TXSYNCOUT), // GTH
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
.RXSYNCMODE (GT_RXSYNCMODE), // GTH
.RXSYNCIN (GT_RXSYNCIN), // GTH
.RXSYNCALLIN (GT_RXSYNCALLIN), // GTH
.RXSYNCDONE (GT_RXSYNCDONE), // GTH
.RXSYNCOUT (GT_RXSYNCOUT), // GTH
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN ( 1'd1), //
.RXMCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXPCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXSLIDE ( GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (8'd0), //
.TX8B10BEN (!GT_GEN3), // 0 = disable TX 8b10b in Gen3
.RX8B10BEN (!GT_GEN3), // 0 = disable RX 8b10b in Gen3
.RXDISPERR (), //
.RXNOTINTABLE (), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS & Loopback -------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.SIGVALIDCLK (GT_OOBCLK), // GTH, optimized for debug
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TXPISOPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
//---------- GTH -------------------------------------------------------
.RXADAPTSELTEST (14'd0), // GTH new
.DMONFIFORESET ( 1'd0), // GTH
.DMONITORCLK (dmonitorclk), // GTH, optimized for debug
//.DMONITORCLK (GT_DRPCLK), // GTH, optimized for debug
.RXPMARESETDONE (GT_RXPMARESETDONE), // GTH
.TXPMARESETDONE () // GTH
);
end
else
begin : gtx_channel
//---------- GTX Channel Module --------------------------------------------
GTXE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_CPLLREFCLK_SEL (3'b001), //
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION (PCIE_USE_MODE), //
//---------- Clock Attributes ------------------------------------------
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), //
.CPLL_FBDIV_45 (CPLL_FBDIV_45), //
.CPLL_FBDIV (CPLL_FBDIV), //
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
.TX_CLKMUX_PD (CLKMUX_PD), // GTX
.RX_CLKMUX_PD (CLKMUX_PD), // GTX
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
.OUTREFCLK_SEL_INV ( 2'b11), //
.CPLL_CFG (CPLL_CFG), // Optimized for silicon
//.CPLL_INIT_CFG (24'h00001E), //
//.CPLL_LOCK_CFG (16'h01E8), //
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME (5'b00001), //
.RXPCSRESET_TIME (5'b00001), //
.TXPMARESET_TIME (5'b00011), //
.RXPMARESET_TIME (5'b00011), // Optimized for sim and for DRP
//.RXISCANRESET_TIME (5'b00001), //
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.TX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.RX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_REF (TX_RXDETECT_REF), //
.RX_CM_SEL ( 2'd3), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable
.RX_CM_TRIM ( 3'b010), // Select 800mV
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim (3'd4)
.TX_EIDLE_DEASSERT_DELAY ( 3'b100), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), //
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 5'b10100), // 6.0 dB
.TX_DEEMPH1 ( 5'b01011), // 3.5 dB
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_PREDRIVER_MODE ( 1'b0), // GTX
.TX_QPI_STATUS_EN ( 1'b0), //
//---------- Status Attributes -----------------------------------------
.RX_SIG_VALID_DLY (4), // Optimized for sim
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (PCS_RSVD_ATTR), //
//---------- PMA Attributes --------------------------------------------
.PMA_RSV (32'h00018480), // Optimized for GES Gen1/Gen2
.PMA_RSV2 (16'h2070), // Optimized for silicon, [4] RX_CM_TRIM[4], [5] = 1 Enable Eye Scan
//.PMA_RSV3 ( 2'd0), //
//.PMA_RSV4 (32'd0), // GTX 3.0 new
.RX_BIAS_CFG (12'b000000000100), // Optimized for GES
//.TERM_RCAL_CFG ( 5'b10000), //
//.TERM_RCAL_OVRD ( 1'd0), //
//---------- CDR Attributes --------------------------------------------
.RXCDR_CFG (RXCDR_CFG_GTX), //
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001)
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), //
//.RXCDRPHRESET_TIME ( 5'b00001), //
//---------- LPM Attributes --------------------------------------------
.RXLPM_HF_CFG (14'h00F0), // Optimized for silicon
.RXLPM_LF_CFG (14'h00F0), // Optimized for silicon
//---------- DFE Attributes --------------------------------------------
//.RXDFELPMRESET_TIME ( 7'b0001111), //
.RX_DFE_GAIN_CFG (23'h020FEA), // Optimized for GES, IES = 23'h001F0A
.RX_DFE_H2_CFG (12'b000000000000), // Optimized for GES
.RX_DFE_H3_CFG (12'b000001000000), // Optimized for GES
.RX_DFE_H4_CFG (11'b00011110000), // Optimized for GES
.RX_DFE_H5_CFG (11'b00011100000), // Optimized for GES
.RX_DFE_KL_CFG (13'b0000011111110), // Optimized for GES
.RX_DFE_KL_CFG2 (32'h3290D86C), // Optimized for GES, GTX new, CTLE 3 3 5, default = 32'h3010D90C
.RX_DFE_LPM_CFG (16'h0954), // Optimized for GES
.RX_DFE_LPM_HOLD_DURING_EIDLE ( 1'd1), // Optimized for PCIe
.RX_DFE_UT_CFG (17'b10001111000000000), // Optimized for GES, IES = 17'h08F00
.RX_DFE_VP_CFG (17'b00011111100000011), // Optimized for GES
.RX_DFE_XYD_CFG (13'h0000), // Optimized for 4.0
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'b0000010000000), // Optimized for GES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("TRUE"), //
.ES_HORZ_OFFSET (12'd0), //
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
//.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
//.TXPHDLY_CFG (24'h084020), //
//.TXDLY_CFG (16'h001F), //
//.TXDLY_LCFG ( 9'h030), //
//.TXDLY_TAP_CFG (16'd0), //
//---------- RX Sync Attributes ----------------------------------------
//.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // Optimized for sim
//.RXDLY_CFG (16'h001F), //
//.RXDLY_LCFG ( 9'h030), //
//.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE (3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes --------------------------------
.RXPRBS_ERR_LOOPBACK (1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes -------------------------------------
//.RXOOB_CFG ( 7'b0000110), //
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_CPLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000B01), // Optimized for debug
.RX_DEBUG_CFG (12'd0) // Optimized for GES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0) //
)
gtxe2_channel_i
(
//---------- Clock -----------------------------------------------------
.GTGREFCLK (1'd0), //
.GTREFCLK0 (GT_GTREFCLK0), //
.GTREFCLK1 (1'd0), //
.GTNORTHREFCLK0 (1'd0), //
.GTNORTHREFCLK1 (1'd0), //
.GTSOUTHREFCLK0 (1'd0), //
.GTSOUTHREFCLK1 (1'd0), //
.QPLLCLK (GT_QPLLCLK), //
.QPLLREFCLK (GT_QPLLREFCLK), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CPLLREFCLKSEL (3'd1), //
.CPLLLOCKDETCLK (1'd0), //
.CPLLLOCKEN (1'd1), //
.CLKRSVD ({2'd0, dmonitorclk, GT_OOBCLK}), // Optimized for debug
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.CPLLLOCK (GT_CPLLLOCK), //
.CPLLREFCLKLOST (), //
.CPLLFBCLKLOST (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
.GTREFCLKMONITOR (), //
//---------- Reset -----------------------------------------------------
.CPLLPD (GT_CPLLPD), //
.CPLLRESET (GT_CPLLRESET), //
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA ({32'd0, GT_TXDATA}), //
.TXCHARISK ({ 4'd0, GT_TXDATAK}), //
.GTXTXP (GT_TXP), // GTX
.GTXTXN (GT_TXN), // GTX
//---------- RX Data ---------------------------------------------------
.GTXRXP (GT_RXP), // GTX
.GTXRXN (GT_RXN), // GTX
.RXDATA (rxdata), //
.RXCHARISK (rxdatak), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( 1'd0), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({7'd0, GT_TXCOMPLIANCE}), //
.TXCHARDISPVAL ( 8'd0), //
.TXPOLARITY ( 1'd0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1100), //
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMEN (rxlpmen), //
.RXLPMHFHOLD ( 1'd0), //
.RXLPMHFOVRDEN ( 1'd0), //
.RXLPMLFHOLD ( 1'd0), //
.RXLPMLFKLOVRDEN ( 1'd0), //
.TXQPIBIASEN ( 1'd0), //
.TXQPISTRONGPDOWN ( 1'd0), //
.TXQPIWEAKPUP ( 1'd0), //
.RXQPIEN ( 1'd0), //
.PMARSVDIN ( 5'd0), //
.PMARSVDIN2 ( 5'd0), // GTX
.GTRSVD (16'd0), //
.TXQPISENP (), //
.TXQPISENN (), //
.RXQPISENP (), //
.RXQPISENN (), //
.DMONITOROUT (dmonitorout[7:0]), // GTX 8-bits
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDIN2 ( 5'd0), //
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'd0), //
.RXCDROVRDEN (1'd0), //
//---------- DFE -------------------------------------------------------
.RXDFELPMRESET (GT_RXDFELPMRESET), //
.RXDFECM1EN (1'd0), //
.RXDFEVSEN (1'd0), //
.RXDFETAP2HOLD (1'd0), //
.RXDFETAP2OVRDEN (1'd0), //
.RXDFETAP3HOLD (1'd0), //
.RXDFETAP3OVRDEN (1'd0), //
.RXDFETAP4HOLD (1'd0), //
.RXDFETAP4OVRDEN (1'd0), //
.RXDFETAP5HOLD (1'd0), //
.RXDFETAP5OVRDEN (1'd0), //
.RXDFEAGCHOLD (GT_RX_CONVERGE), // Optimized for GES, Set to 1 after convergence
.RXDFEAGCOVRDEN (1'd0), //
.RXDFELFHOLD (1'd0), //
.RXDFELFOVRDEN (1'd1), // Optimized for GES
.RXDFEUTHOLD (1'd0), //
.RXDFEUTOVRDEN (1'd0), //
.RXDFEVPHOLD (1'd0), //
.RXDFEVPOVRDEN (1'd0), //
.RXDFEXYDEN (1'd0), //
.RXDFEXYDHOLD (1'd0), // GTX
.RXDFEXYDOVRDEN (1'd0), // GTX
.RXMONITORSEL (2'd0), //
.RXMONITOROUT (), //
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), //
.RXOSOVRDEN (1'd0), //
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'd0), //
.EYESCANDATAERROR (), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (1'd0), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN ( 1'd1), //
.RXMCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXPCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXSLIDE ( GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (8'd0), //
.TX8B10BEN (!GT_GEN3), // 0 = disable TX 8b10b in Gen3
.RX8B10BEN (!GT_GEN3), // 0 = disable RX 8b10b in Gen3
.RXDISPERR (), //
.RXNOTINTABLE (), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS/Loopback ---------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TXPISOPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
.TSTOUT () // GTX
);
//---------- Default -------------------------------------------------------
assign dmonitorout[14:8] = 7'd0; // GTH GTP
assign GT_TXSYNCOUT = 1'd0; // GTH GTP
assign GT_TXSYNCDONE = 1'd0; // GTH GTP
assign GT_RXSYNCOUT = 1'd0; // GTH GTP
assign GT_RXSYNCDONE = 1'd0; // GTH GTP
assign GT_RXPMARESETDONE = 1'd0; // GTH GTP
end
endgenerate
//---------- GT Wrapper Outputs ------------------------------------------------
assign GT_RXDATA = rxdata [31:0];
assign GT_RXDATAK = rxdatak[ 3:0];
assign GT_RXCHARISCOMMA = rxchariscomma[ 3:0];
assign GT_DMONITOROUT = dmonitorout;
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module master #(
parameter id = 0,
parameter nreads = 128,
parameter nwrites = 128,
parameter p = 4
) (
input sys_clk,
input sys_rst,
output reg [31:0] dat_w,
input [31:0] dat_r,
output reg [31:0] adr,
output [2:0] cti,
output reg we,
output reg [3:0] sel,
output cyc,
output stb,
input ack,
output reg tend
);
integer rcounter;
integer wcounter;
reg active;
assign cyc = active;
assign stb = active;
assign cti = 0;
always @(posedge sys_clk) begin
if(sys_rst) begin
dat_w = 0;
adr = 0;
we = 0;
sel = 0;
active = 0;
rcounter = 0;
wcounter = 0;
tend = 0;
end else begin
if(ack) begin
if(~active)
$display("[M%d] Spurious ack", id);
else begin
if(we)
$display("[M%d] Ack W: %x:%x [%x]", id, adr, dat_w, sel);
else
$display("[M%d] Ack R: %x:%x [%x]", id, adr, dat_r, sel);
end
active = 1'b0;
end else if(~active) begin
if(($random % p) == 0) begin
adr = $random;
adr = adr % 5;
adr = (adr << (32-3)) + id;
sel = sel + 1;
active = 1'b1;
if(($random % 2) == 0) begin
/* Read */
we = 1'b0;
rcounter = rcounter + 1;
end else begin
/* Write */
we = 1'b1;
dat_w = ($random << 16) + id;
wcounter = wcounter + 1;
end
end
end
tend = (rcounter >= nreads) && (wcounter >= nwrites);
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rotate.v
// Version: 1.00
// Verilog Standard: Verilog-2001
// Description: A simple module to perform to rotate the input data
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module rotate
#(
parameter C_DIRECTION = "LEFT",
parameter C_WIDTH = 4
)
(
input [C_WIDTH-1:0] WR_DATA,
input [clog2s(C_WIDTH)-1:0] WR_SHIFTAMT,
output [C_WIDTH-1:0] RD_DATA
);
`include "functions.vh"
wire [2*C_WIDTH-1:0] wPreShiftR;
wire [2*C_WIDTH-1:0] wPreShiftL;
wire [2*C_WIDTH-1:0] wShiftR;
wire [2*C_WIDTH-1:0] wShiftL;
assign wPreShiftL = {WR_DATA,WR_DATA};
assign wPreShiftR = {WR_DATA,WR_DATA};
assign wShiftL = wPreShiftL << WR_SHIFTAMT;
assign wShiftR = wPreShiftR >> WR_SHIFTAMT;
generate
if(C_DIRECTION == "LEFT") begin
assign RD_DATA = wShiftL[2*C_WIDTH-1:C_WIDTH];
end else if (C_DIRECTION == "RIGHT") begin
assign RD_DATA = wShiftR[C_WIDTH-1:0];
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_SYMBOL_V
`define SKY130_FD_SC_HS__NOR3B_SYMBOL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_SYMBOL_V
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/max6682.v:133" *)
(* top = 1 *)
module MAX6682(Reset_n_i, Clk_i, Enable_i, CpuIntr_o, MAX6682CS_n_o, SPI_Data_i, SPI_Write_o, SPI_ReadNext_o, SPI_Data_o, SPI_FIFOFull_i, SPI_FIFOEmpty_i, SPI_Transmission_i, PeriodCounterPresetH_i, PeriodCounterPresetL_i, SensorValue_o, Threshold_i, SPI_CPOL_o, SPI_CPHA_o, SPI_LSBFE_o);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$extract$\AddSubCmp_Greater_Direct$773.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$extract$\AddSubCmp_Greater_Direct$773.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$extract$\AddSubCmp_Greater_Direct$773.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$extract$\AddSubCmp_Greater_Direct$773.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$extract$\AddSubCmp_Greater_Direct$773.Zero_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:12" *)
wire [15:0] \$extract$\Counter32_RV1_Timer$768.DH_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:13" *)
wire [15:0] \$extract$\Counter32_RV1_Timer$768.DL_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:14" *)
wire \$extract$\Counter32_RV1_Timer$768.Overflow_s ;
(* src = "../../verilog/max6682.v:323" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/max6682.v:184" *)
wire [7:0] Byte0;
(* src = "../../verilog/max6682.v:185" *)
wire [7:0] Byte1;
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/max6682.v:137" *)
input Clk_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIRQs_s" *)
(* src = "../../verilog/max6682.v:141" *)
output CpuIntr_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIn_s" *)
(* src = "../../verilog/max6682.v:139" *)
input Enable_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "Outputs_o" *)
(* src = "../../verilog/max6682.v:143" *)
output MAX6682CS_n_o;
(* src = "../../verilog/max6682.v:9" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Done ;
(* src = "../../verilog/max6682.v:4" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Start ;
(* src = "../../verilog/max6682.v:24" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Wr0 ;
(* src = "../../verilog/max6682.v:23" *)
wire \MAX6682_SPI_FSM_1.SPI_FSM_Wr1 ;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetH_i" *)
(* src = "../../verilog/max6682.v:159" *)
input [15:0] PeriodCounterPresetH_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetL_i" *)
(* src = "../../verilog/max6682.v:161" *)
input [15:0] PeriodCounterPresetL_i;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/max6682.v:135" *)
input Reset_n_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_CPHA" *)
(* src = "../../verilog/max6682.v:169" *)
output SPI_CPHA_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_CPOL" *)
(* src = "../../verilog/max6682.v:167" *)
output SPI_CPOL_o;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "SPI_DataOut" *)
(* src = "../../verilog/max6682.v:145" *)
input [7:0] SPI_Data_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "SPI_DataIn" *)
(* src = "../../verilog/max6682.v:151" *)
output [7:0] SPI_Data_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_FIFOEmpty" *)
(* src = "../../verilog/max6682.v:155" *)
input SPI_FIFOEmpty_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_FIFOFull" *)
(* src = "../../verilog/max6682.v:153" *)
input SPI_FIFOFull_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_LSBFE" *)
(* src = "../../verilog/max6682.v:171" *)
output SPI_LSBFE_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_ReadNext" *)
(* src = "../../verilog/max6682.v:149" *)
output SPI_ReadNext_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_Transmission" *)
(* src = "../../verilog/max6682.v:157" *)
input SPI_Transmission_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_Write" *)
(* src = "../../verilog/max6682.v:147" *)
output SPI_Write_o;
(* src = "../../verilog/max6682.v:216" *)
wire SensorFSM_StoreNewValue;
(* src = "../../verilog/max6682.v:214" *)
wire SensorFSM_TimerEnable;
(* src = "../../verilog/max6682.v:212" *)
wire SensorFSM_TimerOvfl;
(* src = "../../verilog/max6682.v:213" *)
wire SensorFSM_TimerPreset;
(* src = "../../verilog/max6682.v:321" *)
wire [15:0] SensorValue;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SensorValue_o" *)
(* src = "../../verilog/max6682.v:163" *)
output [15:0] SensorValue_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "Threshold_i" *)
(* src = "../../verilog/max6682.v:165" *)
input [15:0] Threshold_i;
AbsDiff \$extract$\AbsDiff$769 (
.A_i(SensorValue),
.B_i(SensorValue_o),
.D_o(AbsDiffResult)
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$extract$\AddSubCmp_Greater_Direct$773.ThisAddSubCmp (
.A_i(AbsDiffResult),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$extract$\AddSubCmp_Greater_Direct$773.Carry_s ),
.D_o(\$extract$\AddSubCmp_Greater_Direct$773.D_s ),
.Overflow_o(\$extract$\AddSubCmp_Greater_Direct$773.Overflow_s ),
.Sign_o(\$extract$\AddSubCmp_Greater_Direct$773.Sign_s ),
.Zero_o(\$extract$\AddSubCmp_Greater_Direct$773.Zero_s )
);
(* src = "../../../../byte2wordsel/verilog/byte2wordsel_11msb.v:10" *)
Byte2WordSel \$extract$\Byte2WordSel_11MSB_Direct$781.DUT (
.H_i(Byte1),
.L_i(Byte0),
.Mask_i(4'b1011),
.Shift_i(4'b0101),
.Y_o(SensorValue)
);
(* src = "../../../../counter32/verilog/counter32_rv1.v:19" *)
Counter32 \$extract$\Counter32_RV1_Timer$768.ThisCounter (
.Clk_i(Clk_i),
.DH_o(\$extract$\Counter32_RV1_Timer$768.DH_s ),
.DL_o(\$extract$\Counter32_RV1_Timer$768.DL_s ),
.Direction_i(1'b1),
.Enable_i(SensorFSM_TimerEnable),
.Overflow_o(\$extract$\Counter32_RV1_Timer$768.Overflow_s ),
.PresetValH_i(PeriodCounterPresetH_i),
.PresetValL_i(PeriodCounterPresetL_i),
.Preset_i(SensorFSM_TimerPreset),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(SensorFSM_TimerOvfl)
);
WordRegister \$extract$\WordRegister$770 (
.Clk_i(Clk_i),
.D_i(SensorValue),
.Enable_i(SensorFSM_StoreNewValue),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/max6682.v:210" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000101),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000000101),
.NAME("\\SensorFSM_State"),
.STATE_BITS(32'b00000000000000000000000000000010),
.STATE_NUM(32'b00000000000000000000000000000100),
.STATE_NUM_LOG2(32'b00000000000000000000000000000011),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(8'b11011000),
.TRANS_NUM(32'b00000000000000000000000000001010),
.TRANS_TABLE(160'b011zzzzz01011000010zz0z101000100010zz1z100100101010zzzz00000010000101z1z011001100011zz1z0100100000100z1z01001000001zzz0z00101000000zzzz101000100000zzzz000001000)
) \$fsm$\SensorFSM_State$738 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ \$extract$\AddSubCmp_Greater_Direct$773.Zero_s , \$extract$\AddSubCmp_Greater_Direct$773.Carry_s , SensorFSM_TimerOvfl, \MAX6682_SPI_FSM_1.SPI_FSM_Done , Enable_i }),
.CTRL_OUT({ CpuIntr_o, SensorFSM_TimerPreset, SensorFSM_TimerEnable, SensorFSM_StoreNewValue, \MAX6682_SPI_FSM_1.SPI_FSM_Start })
);
ByteRegister \$techmap\MAX6682_SPI_FSM_1.$extract$\ByteRegister$771 (
.Clk_i(Clk_i),
.D_i(SPI_Data_i),
.Enable_i(\MAX6682_SPI_FSM_1.SPI_FSM_Wr0 ),
.Q_o(Byte0),
.Reset_n_i(Reset_n_i)
);
ByteRegister \$techmap\MAX6682_SPI_FSM_1.$extract$\ByteRegister$772 (
.Clk_i(Clk_i),
.D_i(SPI_Data_i),
.Enable_i(\MAX6682_SPI_FSM_1.SPI_FSM_Wr1 ),
.Q_o(Byte1),
.Reset_n_i(Reset_n_i)
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/max6682.v:21" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000010),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000000110),
.NAME("\\SPI_FSM_State"),
.STATE_BITS(32'b00000000000000000000000000000011),
.STATE_NUM(32'b00000000000000000000000000000111),
.STATE_NUM_LOG2(32'b00000000000000000000000000000011),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(21'b011101001110010100000),
.TRANS_NUM(32'b00000000000000000000000000001001),
.TRANS_TABLE(126'b1101z1100000001100z001001100101zz011010010100zz010100000011zz000010010010zz110000000001zz101001001000z1100100000000z0000010000)
) \$techmap\MAX6682_SPI_FSM_1.$fsm$\SPI_FSM_State$743 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ SPI_Transmission_i, \MAX6682_SPI_FSM_1.SPI_FSM_Start }),
.CTRL_OUT({ SPI_Write_o, MAX6682CS_n_o, SPI_ReadNext_o, \MAX6682_SPI_FSM_1.SPI_FSM_Wr1 , \MAX6682_SPI_FSM_1.SPI_FSM_Done , \MAX6682_SPI_FSM_1.SPI_FSM_Wr0 })
);
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_Data_o = 8'b00000000;
assign SPI_LSBFE_o = 1'b0;
endmodule
|
// ---------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- ------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// ---------------------------------------------------------------------------
// -- --
// -- This is the main ZAP arithmetic and logic unit. Apart from shfits --
// -- and multiplies, all other arithmetic and logic is performed here. --
// -- Also data memory access signals are generated at the end of the clock --
// -- cycle. Instructions that fail condition checks are invalidated here. --
// -- --
// ---------------------------------------------------------------------------
`default_nettype none
module zap_alu_main #(
parameter [31:0] PHY_REGS = 32'd46, // Number of physical registers.
parameter [31:0] SHIFT_OPS = 32'd5, // Number of shift operations.
parameter [31:0] ALU_OPS = 32'd32, // Number of arithmetic operations.
parameter [31:0] FLAG_WDT = 32'd32 // Width of active CPSR.
)
(
// ------------------------------------------------------------------
// Decompile Interface. Only for debug.
// ------------------------------------------------------------------
input wire [64*8-1:0] i_decompile,
output reg [64*8-1:0] o_decompile,
// ------------------------------------------------------------------
// ALU Hijack Interface. For Thumb Data Abort address calculation.
// ------------------------------------------------------------------
input wire i_hijack, // Enable hijack.
input wire [31:0] i_hijack_op1, // Hijack operand 1.
input wire [31:0] i_hijack_op2, // Hijack operand 2.
input wire i_hijack_cin, // Hijack carry in.
output wire [31:0] o_hijack_sum, // Hijack sum out.
// ------------------------------------------------------------------
// Clock and reset
// ------------------------------------------------------------------
input wire i_clk, // Clock.
input wire i_reset, // sync active high reset.
// -------------------------------------------------------------------
// Clear and Stall signals.
// -------------------------------------------------------------------
input wire i_clear_from_writeback, // Clear unit.
input wire i_data_stall, // DCACHE stall.
// -------------------------------------------------------------------
// Misc. signals
// -------------------------------------------------------------------
input wire [31:0] i_cpsr_nxt, // From passive CPSR.
input wire i_switch_ff, // Switch state.
input wire [1:0] i_taken_ff, // Branch prediction.
input wire [31:0] i_pc_ff, // Addr of instr.
input wire i_nozero_ff, // Zero flag will not be set.
// ------------------------------------------------------------------
// Source values
// ------------------------------------------------------------------
input wire [31:0] i_alu_source_value_ff, // ALU source value.
input wire [31:0] i_shifted_source_value_ff, // Shifted source value.
input wire i_shift_carry_ff, // Carry from shifter.
input wire i_shift_sat_ff, // Saturation indication from shifter.
input wire [31:0] i_pc_plus_8_ff, // PC + 8 value.
// ------------------------------------------------------------------
// Interrupt Tagging
// ------------------------------------------------------------------
input wire i_abt_ff, // ABT flagged.
input wire i_irq_ff, // IRQ flagged.
input wire i_fiq_ff, // FIQ flagged.
input wire i_swi_ff, // SWI flagged.
input wire i_und_ff, // Flagged undefined instructions.
input wire i_data_mem_fault, // Flagged Data abort.
// ------------------------------------------------------------------
// Memory Access Related
// ------------------------------------------------------------------
input wire [31:0] i_mem_srcdest_value_ff, // Value to store.
input wire [zap_clog2(PHY_REGS)-1:0] i_mem_srcdest_index_ff, // LD/ST Memory data register index.
input wire i_mem_load_ff, // LD/ST Memory load.
input wire i_mem_store_ff, // LD/ST Memory store.
input wire i_mem_pre_index_ff, // LD/ST Pre/Post index.
input wire i_mem_unsigned_byte_enable_ff, // LD/ST uint8_t data type.
input wire i_mem_signed_byte_enable_ff, // LD/ST int8_t data type.
input wire i_mem_signed_halfword_enable_ff, // LD/ST int16_t data type.
input wire i_mem_unsigned_halfword_enable_ff,// LD/ST uint16_t data type.
input wire i_mem_translate_ff, // LD/ST Force user view of memory.
input wire i_force32align_ff, // Force address alignment to 32-bit.
// -------------------------------------------------------------------
// ALU controls
// -------------------------------------------------------------------
input wire [3:0] i_condition_code_ff, // CC associated with instr.
input wire [zap_clog2(PHY_REGS)-1:0] i_destination_index_ff, // Target register index.
input wire [zap_clog2(ALU_OPS)-1:0] i_alu_operation_ff, // Operation to perform.
input wire i_flag_update_ff, // Update flags if 1.
// -----------------------------------------------------------------
// ALU result
// -----------------------------------------------------------------
output reg [31:0] o_alu_result_nxt, // For feedback. ALU result _nxt version.
output reg [31:0] o_alu_result_ff, // ALU result flopped version.
output reg o_dav_ff, // Instruction valid.
output reg o_dav_nxt, // Instruction valid _nxt version.
output reg [FLAG_WDT-1:0] o_flags_ff, // Output flags (CPSR).
output reg [FLAG_WDT-1:0] o_flags_nxt, // CPSR next.
output reg [zap_clog2(PHY_REGS)-1:0] o_destination_index_ff, // Destination register index.
// -----------------------------------------------------------------
// Interrupt Tagging
// -----------------------------------------------------------------
output reg o_abt_ff, // Instruction abort flagged.
output reg o_irq_ff, // IRQ flagged.
output reg o_fiq_ff, // FIQ flagged.
output reg o_swi_ff, // SWI flagged.
output reg o_und_ff, // Flagged undefined instructions
// -----------------------------------------------------------------
// Jump Controls, BP Confirm, PC + 8
// -----------------------------------------------------------------
output reg [31:0] o_pc_plus_8_ff, // Instr address + 8.
output reg o_clear_from_alu, // ALU commands a pipeline clear and a predictor correction.
output reg [31:0] o_pc_from_alu, // Corresponding address to go to is provided here.
output reg o_confirm_from_alu, // Tell branch predictor it was correct.
// ----------------------------------------------------------------
// Memory access related
// ----------------------------------------------------------------
output reg [zap_clog2(PHY_REGS)-1:0] o_mem_srcdest_index_ff, // LD/ST data register.
output reg o_mem_load_ff, // LD/ST load indicator.
output reg o_mem_store_ff, // LD/ST store indicator.
output reg [31:0] o_mem_address_ff, // LD/ST address to access.
output reg o_mem_unsigned_byte_enable_ff, // uint8_t
output reg o_mem_signed_byte_enable_ff, // int8_t
output reg o_mem_signed_halfword_enable_ff, // int16_t
output reg o_mem_unsigned_halfword_enable_ff, // uint16_t
output reg [31:0] o_mem_srcdest_value_ff, // LD/ST value to store.
output reg o_mem_translate_ff, // LD/ST force user view of memory.
output reg [3:0] o_ben_ff, // LD/ST byte enables (only for STore instructions).
output reg [31:0] o_address_nxt, // D pin of address register to drive TAG RAMs.
// -------------------------------------------------------------
// Wishbone signal outputs.
// -------------------------------------------------------------
output reg o_data_wb_we_nxt,
output reg o_data_wb_cyc_nxt,
output reg o_data_wb_stb_nxt,
output reg [31:0] o_data_wb_dat_nxt,
output reg [3:0] o_data_wb_sel_nxt,
output reg o_data_wb_we_ff,
output reg o_data_wb_cyc_ff,
output reg o_data_wb_stb_ff,
output reg [31:0] o_data_wb_dat_ff,
output reg [3:0] o_data_wb_sel_ff
);
// ----------------------------------------------------------------------------
// Includes
// ----------------------------------------------------------------------------
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
// -----------------------------------------------------------------------------
// Localparams
// -----------------------------------------------------------------------------
// Local N,Z,C,V structures.
localparam [1:0] _N = 2'd3;
localparam [1:0] _Z = 2'd2;
localparam [1:0] _C = 2'd1;
localparam [1:0] _V = 2'd0;
// Branch status.
localparam [1:0] SNT = 2'd0;
localparam [1:0] WNT = 2'd1;
localparam [1:0] WT = 2'd2;
localparam [1:0] ST = 2'd3;
// ------------------------------------------------------------------------------
// Variables
// ------------------------------------------------------------------------------
// Memory srcdest value (i.e., data)
wire [31:0] mem_srcdest_value_nxt;
// Byte enable generator.
wire [3:0] ben_nxt;
// Address about to be output. Used to drive tag RAMs etc.
reg [31:0] mem_address_nxt;
/*
Sleep flop. When 1 unit sleeps i.e., does not produce any output except on
the first clock cycle where LR is calculated using the ALU.
*/
reg sleep_ff, sleep_nxt;
/*
CPSR (Active CPSR). The active CPSR is from the where the CPU flags are
read out and the mode also is. Mode changes via manual writes to CPSR
are first written to the active and they then propagate to the passive CPSR
in the writeback stage. This reduces the pipeline flush penalty.
*/
reg [31:0] flags_ff, flags_nxt;
reg [31:0] rm, rn; // RM = shifted source value Rn for
// non shifted source value. These are
// values and not indices.
reg [5:0] clz_rm; // Count leading zeros in Rm.
// Destination index about to be output.
reg [zap_clog2(PHY_REGS)-1:0] o_destination_index_nxt;
// 1s complement of Rm and Rn.
wire [31:0] not_rm = ~rm;
wire [31:0] not_rn = ~rn;
// Wires which connect to an adder.
reg [31:0] op1, op2;
reg cin;
// 32-bit adder with carry input and carry output.
wire [32:0] sum = {1'd0, op1} + {1'd0, op2} + {32'd0, cin};
reg [31:0] tmp_flags, tmp_sum;
// Opcode.
wire [zap_clog2(ALU_OPS)-1:0] opcode = i_alu_operation_ff;
// -------------------------------------------------------------------------------
// Assigns
// -------------------------------------------------------------------------------
/*
For memory stores, we must generate correct byte enables. This is done
by examining access type inputs. For loads, always 1111 is generated.
If there is neither a load or a store, the old value is preserved.
*/
assign ben_nxt = generate_ben (
i_mem_unsigned_byte_enable_ff,
i_mem_signed_byte_enable_ff,
i_mem_unsigned_halfword_enable_ff,
i_mem_unsigned_halfword_enable_ff,
mem_address_nxt);
assign mem_srcdest_value_nxt = duplicate (
i_mem_unsigned_byte_enable_ff,
i_mem_signed_byte_enable_ff,
i_mem_unsigned_halfword_enable_ff,
i_mem_unsigned_halfword_enable_ff,
i_mem_srcdest_value_ff );
/*
Hijack interface. Data aborts use the hijack interface to find return
address. The writeback drives the ALU inputs to find the final output.
*/
assign o_hijack_sum = sum;
// -------------------------------------------------------------------------------
// CLZ logic.
// -------------------------------------------------------------------------------
always @* // CLZ implementation.
begin
casez(rm)
32'b1???????????????????????????????: clz_rm = 6'd00;
32'b01??????????????????????????????: clz_rm = 6'd01;
32'b001?????????????????????????????: clz_rm = 6'd02;
32'b0001????????????????????????????: clz_rm = 6'd03;
32'b00001???????????????????????????: clz_rm = 6'd04;
32'b000001??????????????????????????: clz_rm = 6'd05;
32'b0000001?????????????????????????: clz_rm = 6'd06;
32'b00000001????????????????????????: clz_rm = 6'd07;
32'b000000001???????????????????????: clz_rm = 6'd08;
32'b0000000001??????????????????????: clz_rm = 6'd09;
32'b00000000001?????????????????????: clz_rm = 6'd10;
32'b000000000001????????????????????: clz_rm = 6'd11;
32'b0000000000001???????????????????: clz_rm = 6'd12;
32'b00000000000001??????????????????: clz_rm = 6'd13;
32'b000000000000001?????????????????: clz_rm = 6'd14;
32'b0000000000000001????????????????: clz_rm = 6'd15;
32'b00000000000000001???????????????: clz_rm = 6'd16;
32'b000000000000000001??????????????: clz_rm = 6'd17;
32'b0000000000000000001?????????????: clz_rm = 6'd18;
32'b00000000000000000001????????????: clz_rm = 6'd19;
32'b000000000000000000001???????????: clz_rm = 6'd20;
32'b0000000000000000000001??????????: clz_rm = 6'd21;
32'b00000000000000000000001?????????: clz_rm = 6'd22;
32'b000000000000000000000001????????: clz_rm = 6'd23;
32'b0000000000000000000000001???????: clz_rm = 6'd24;
32'b00000000000000000000000001??????: clz_rm = 6'd25;
32'b000000000000000000000000001?????: clz_rm = 6'd26;
32'b0000000000000000000000000001????: clz_rm = 6'd27;
32'b00000000000000000000000000001???: clz_rm = 6'd28;
32'b000000000000000000000000000001??: clz_rm = 6'd29;
32'b0000000000000000000000000000001?: clz_rm = 6'd30;
32'b00000000000000000000000000000001: clz_rm = 6'd31;
default: clz_rm = 6'd32; // All zeros.
endcase
end
// ----------------------------------------------------------------------------
// Aliases
// ----------------------------------------------------------------------------
always @*
begin
rm = i_shifted_source_value_ff;
rn = i_alu_source_value_ff;
o_flags_ff = flags_ff;
o_flags_nxt = flags_nxt;
end
// -----------------------------------------------------------------------------
// Sequential logic.
// -----------------------------------------------------------------------------
always @ (posedge i_clk)
begin
if ( i_reset )
begin
// On reset, processor enters supervisory mode with interrupts
// masked.
reset;
clear ( {1'd1,1'd1,1'd0,SVC} );
end
else if ( i_clear_from_writeback )
begin
// Clear but take CPSR from writeback.
clear ( i_cpsr_nxt );
end
else if ( i_data_stall )
begin
// Preserve values.
end
else if ( i_data_mem_fault || sleep_ff )
begin
// Clear and preserve flags. Keep sleeping.
clear(flags_ff);
sleep_ff <= 1'd1;
o_dav_ff <= 1'd0; // Don't give any output.
end
else
begin
// Clock out all flops normally.
o_alu_result_ff <= o_alu_result_nxt;
o_dav_ff <= o_dav_nxt;
o_pc_plus_8_ff <= i_pc_plus_8_ff;
o_destination_index_ff <= o_destination_index_nxt;
flags_ff <= flags_nxt;
o_abt_ff <= i_abt_ff;
o_irq_ff <= i_irq_ff;
o_fiq_ff <= i_fiq_ff;
o_swi_ff <= i_swi_ff;
o_mem_srcdest_index_ff <= i_mem_srcdest_index_ff;
o_mem_srcdest_index_ff <= i_mem_srcdest_index_ff;
// Load or store must come up only if an actual LDR/STR is
// detected.
o_mem_load_ff <= o_dav_nxt ? i_mem_load_ff : 1'd0;
o_mem_store_ff <= o_dav_nxt ? i_mem_store_ff: 1'd0;
o_mem_unsigned_byte_enable_ff <= i_mem_unsigned_byte_enable_ff;
o_mem_signed_byte_enable_ff <= i_mem_signed_byte_enable_ff;
o_mem_signed_halfword_enable_ff <= i_mem_signed_halfword_enable_ff;
o_mem_unsigned_halfword_enable_ff<= i_mem_unsigned_halfword_enable_ff;
o_mem_translate_ff <= i_mem_translate_ff;
//
// The value to store will have to be duplicated for easier
// memory controller design. See the duplicate() function.
//
o_mem_srcdest_value_ff <= mem_srcdest_value_nxt;
sleep_ff <= sleep_nxt;
o_und_ff <= i_und_ff;
// Generating byte enables based on the data type and address.
o_ben_ff <= ben_nxt;
// For debug
o_decompile <= i_decompile;
end
end
// ----------------------------------------------------------------------------
always @ ( posedge i_clk ) // Wishbone flops.
begin
// Wishbone updates.
o_data_wb_cyc_ff <= o_data_wb_cyc_nxt;
o_data_wb_stb_ff <= o_data_wb_stb_nxt;
o_data_wb_we_ff <= o_data_wb_we_nxt;
o_data_wb_dat_ff <= o_data_wb_dat_nxt;
o_data_wb_sel_ff <= o_data_wb_sel_nxt;
// Hold WB address on stall. This is the flop.
if ( !i_data_stall )
begin
o_mem_address_ff <= o_address_nxt;
end
end
// -----------------------------------------------------------------------------
// WB next state logic.
// -----------------------------------------------------------------------------
always @*
begin
// Preserve values.
o_data_wb_cyc_nxt = o_data_wb_cyc_ff;
o_data_wb_stb_nxt = o_data_wb_stb_ff;
o_data_wb_we_nxt = o_data_wb_we_ff;
o_data_wb_dat_nxt = o_data_wb_dat_ff;
o_data_wb_sel_nxt = o_data_wb_sel_ff;
o_address_nxt = mem_address_nxt;
if ( i_reset ) // Synchronous reset to only those flops that need it.
begin
o_data_wb_cyc_nxt = 1'd0;
o_data_wb_stb_nxt = 1'd0;
end
else if ( i_clear_from_writeback )
begin
o_data_wb_cyc_nxt = 0;
o_data_wb_stb_nxt = 0;
end
else if ( i_data_stall )
begin
// Save state.
end
else if ( i_data_mem_fault || sleep_ff )
begin
o_data_wb_cyc_nxt = 0;
o_data_wb_stb_nxt = 0;
o_data_wb_we_nxt = 0;
end
else
begin
o_data_wb_cyc_nxt = o_dav_nxt ? i_mem_load_ff | i_mem_store_ff : 1'd0;
o_data_wb_stb_nxt = o_dav_nxt ? i_mem_load_ff | i_mem_store_ff : 1'd0;
o_data_wb_we_nxt = o_dav_nxt ? i_mem_store_ff : 1'd0;
o_data_wb_dat_nxt = mem_srcdest_value_nxt;
o_data_wb_sel_nxt = ben_nxt;
end
end
// ----------------------------------------------------------------------------
// Used to generate access address.
// ----------------------------------------------------------------------------
always @ (*)
begin:pre_post_index_address_generator
/*
* Memory address output based on pre or post index.
* For post-index, update is done after memory access.
* For pre-index, update is done before memory access.
*/
if ( i_mem_pre_index_ff == 0 )
mem_address_nxt = rn; // Postindex;
else
mem_address_nxt = sum[31:0]; // Preindex.
// If a force 32 align is set, make the lower 2 bits as zero.
if ( i_force32align_ff )
mem_address_nxt[1:0] = 2'b00;
end
// ---------------------------------------------------------------------------------
// Used to generate ALU result + Flags
// ---------------------------------------------------------------------------------
always @*
begin: alu_result
reg [3:0] flags;
reg [zap_clog2(ALU_OPS)-1:0] op;
reg n,z,c,v;
reg [31:0] exp_mask;
flags = 0;
op = 0;
{n,z,c,v} = 0;
exp_mask = 0;
// Default value.
tmp_flags = flags_ff;
// If it is a logical instruction.
if ( opcode == AND ||
opcode == EOR ||
opcode == MOV ||
opcode == SAT_MOV ||
opcode == MVN ||
opcode == BIC ||
opcode == ORR ||
opcode == TST ||
opcode == TEQ ||
opcode == CLZ
)
begin
// Call the logical processing function.
{tmp_flags[31:28], tmp_sum} = process_logical_instructions (
rn, rm, flags_ff[31:28],
opcode, opcode == SAT_MOV ? 1'd0 : i_flag_update_ff, i_nozero_ff
);
// Set only Q flag from shift stage. Don't touch other Flags.
if ( opcode == SAT_MOV )
begin
tmp_flags = flags_ff;
tmp_flags[27] = tmp_flags[27] | i_shift_sat_ff; // Sticky.
end
end
/*
* Flag MOV(FMOV) i.e., MOV to CPSR and MMOV handler.
* FMOV moves to CPSR and flushes the pipeline.
* MMOV moves to SPSR and does not flush the pipeline.
*/
else if ( opcode == FMOV || opcode == MMOV )
begin: fmov_mmov
integer i;
// Read entire CPSR or SPSR.
tmp_sum = opcode == FMOV ? flags_ff : i_mem_srcdest_value_ff;
// Generate a proper mask.
exp_mask = {{8{rn[3]}},{8{rn[2]}},{8{rn[1]}},{8{rn[0]}}};
// Change only specific bits as specified by the mask.
for ( i=0;i<32;i=i+1 )
begin
if ( exp_mask[i] )
tmp_sum[i] = rm[i];
end
/*
* FMOV moves to the CPSR in ALU and writeback.
* No register is changed. The MSR out of this will have
* a target to CPSR.
*/
if ( opcode == FMOV )
begin
tmp_flags = tmp_sum;
end
end
else
begin: blk3
op = opcode;
// Assign output of adder to flags after some minimal logic.
c = sum[32];
z = (sum[31:0] == 0);
n = sum[31];
// Overflow.
if ( ( op == ADD || op == ADC || op == CMN ) && (rn[31] == rm[31]) && (sum[31] != rn[31]) )
v = 1;
else if ( (op == RSB || op == RSC) && (rm[31] == !rn[31]) && (sum[31] != rm[31] ) )
v = 1;
else if ( (op == SUB || op == SBC || op == CMP) && (rn[31] == !rm[31]) && (sum[31] != rn[31]) )
v = 1;
else
v = 0;
//
// If you choose not to update flags, do not change the flags.
// Otherwise, they will contain their newly computed values.
//
if ( i_flag_update_ff )
begin
if ( op == OP_QADD || op == OP_QSUB || op == OP_QDADD || op == OP_QDSUB )
tmp_flags[27] = (v || i_shift_sat_ff || tmp_flags[27]) ? 1'd1 : 1'd0; // Sticky.
else
tmp_flags[31:28] = {n,z,c,v};
end
// Write out the result.
tmp_sum = op == CLZ ? clz_rm : sum;
// Saturating operations.
if ( op == OP_QADD || op == OP_QSUB || op == OP_QDADD || op == OP_QDSUB )
begin
if ( v ) // result saturated due to ALU operation.
begin
// Find the direction of saturation.
if ( rm[31] == rn[31] && rm[31] )
tmp_sum = {1'd1, {31{1'd0}}};
else
tmp_sum = {1'd0, {31{1'd1}}};
end
end
end
// Drive nxt pin of result register.
o_alu_result_nxt = tmp_sum;
end
// ----------------------------------------------------------------------------
// Flag propagation and branch prediction feedback unit
// ----------------------------------------------------------------------------
always @*
begin: flags_bp_feedback
o_clear_from_alu = 1'd0;
o_pc_from_alu = 32'd0;
sleep_nxt = sleep_ff;
flags_nxt = tmp_flags;
o_destination_index_nxt = i_destination_index_ff;
o_confirm_from_alu = 1'd0;
// Check if condition is satisfied.
o_dav_nxt = is_cc_satisfied ( i_condition_code_ff, flags_ff[31:28] );
if ( i_irq_ff || i_fiq_ff || i_abt_ff || i_swi_ff || i_und_ff )
begin
//
// Any sign of an interrupt is present, put unit to sleep.
// The current instruction will not be executed ultimately.
// However o_dav_nxt = 1 since interrupt must be carried on.
//
o_dav_nxt = 1'd1;
sleep_nxt = 1'd1;
end
else if ( (opcode == FMOV) && o_dav_nxt ) // Writes to CPSR...
begin
o_clear_from_alu = 1'd1; // Need to flush everything because we might end up fetching stuff in KERNEL instead of USER mode.
o_pc_from_alu = sum; // NOT tmp_sum, that would be loaded into CPSR.
// USR cannot change mode. Will silently fail.
flags_nxt[`CPSR_MODE] = (flags_nxt[`CPSR_MODE] == USR) ? USR : flags_nxt[`CPSR_MODE]; // Security.
end
else if ( i_destination_index_ff == ARCH_PC && (i_condition_code_ff != NV))
begin
if ( i_flag_update_ff && o_dav_nxt ) // PC update with S bit. Context restore.
begin
o_destination_index_nxt = PHY_RAZ_REGISTER;
o_clear_from_alu = 1'd1;
o_pc_from_alu = tmp_sum;
flags_nxt = i_mem_srcdest_value_ff; // Restore CPSR from SPSR.
flags_nxt[`CPSR_MODE] = (flags_nxt[`CPSR_MODE] == USR) ? USR : flags_nxt[`CPSR_MODE]; // Security.
end
else if ( o_dav_nxt ) // Branch taken and no flag update.
begin
if ( i_taken_ff == SNT || i_taken_ff == WNT ) // Incorrectly predicted.
begin
// Quick branches - Flush everything before.
// Dumping ground since PC change is done. Jump to branch target for fast switching.
o_destination_index_nxt = PHY_RAZ_REGISTER;
o_clear_from_alu = 1'd1;
o_pc_from_alu = tmp_sum;
if ( i_switch_ff )
begin
flags_nxt[T] = tmp_sum[0];
end
end
else // Correctly predicted.
begin
// If thumb bit changes, flush everything before
if ( i_switch_ff )
begin
// Quick branches! PC goes to RAZ register since
// change is done.
o_destination_index_nxt = PHY_RAZ_REGISTER;
o_clear_from_alu = 1'd1;
o_pc_from_alu = tmp_sum; // Jump to branch target.
flags_nxt[T] = tmp_sum[0];
end
else
begin
// No mode change, do not change anything.
o_destination_index_nxt = PHY_RAZ_REGISTER;
o_clear_from_alu = 1'd0;
// Send confirmation message to branch predictor.
o_pc_from_alu = 32'd0;
o_confirm_from_alu = 1'd1;
end
end
end
else // Branch not taken
begin
if ( i_taken_ff == WT || i_taken_ff == ST )
//
// Wrong prediction as taken. Go back to the same
// branch. Non branches are always predicted as not-taken.
//
// GO BACK TO THE SAME BRANCH AND INFORM PREDICTOR OF ITS
// MISTAKE - THE NEXT TIME THE PREDICTION WILL BE NOT-TAKEN.
//
begin
o_clear_from_alu = 1'd1;
o_pc_from_alu = i_pc_ff;
end
else // Correct prediction.
begin
o_clear_from_alu = 1'd0;
o_pc_from_alu = 32'd0;
end
end
end
else if ( i_mem_srcdest_index_ff == ARCH_PC && o_dav_nxt && i_mem_load_ff)
begin
// Loads to PC also puts the unit to sleep.
sleep_nxt = 1'd1;
end
// If the current instruction is invalid, do not update flags.
if ( o_dav_nxt == 1'd0 )
flags_nxt = flags_ff;
end
// ----------------------------------------------------------------------------
// MUX structure on the inputs of the adder.
// ----------------------------------------------------------------------------
// These are adder connections. Data processing and FMOV use these.
always @*
begin: adder_ip_mux
reg [zap_clog2(ALU_OPS)-1:0] op;
reg [31:0] flags;
flags = flags_ff[31:28];
op = i_alu_operation_ff;
if ( i_hijack )
begin
op1 = i_hijack_op1;
op2 = i_hijack_op2;
cin = i_hijack_cin;
end
else
case ( op )
FMOV: begin op1 = i_pc_plus_8_ff ; op2 = ~32'd4 ; cin = 1'd1; end
ADD, OP_QADD, OP_QDADD:
begin
op1 = rn ; op2 = rm ; cin = 32'd0;
end
ADC: begin op1 = rn ; op2 = rm ; cin = flags[_C]; end
SUB, OP_QSUB, OP_QDSUB:
begin
op1 = rn ; op2 = not_rm ; cin = 32'd1;
end
RSB: begin op1 = rm ; op2 = not_rn ; cin = 32'd1; end
SBC: begin op1 = rn ; op2 = not_rm ; cin = !flags[_C];end
RSC: begin op1 = rm ; op2 = not_rn ; cin = !flags[_C];end
// Target is not written.
CMP: begin op1 = rn ; op2 = not_rm ; cin = 32'd1; end
CMN: begin op1 = rn ; op2 = rm ; cin = 32'd0; end
default:
begin
op1 = 0;
op2 = 0;
cin = 0;
end
endcase
end
// ----------------------------------------------------------------------------
// Functions
// ----------------------------------------------------------------------------
// Process logical instructions.
function [35:0] process_logical_instructions
(
input [31:0] rn,
input [31:0] rm,
input [3:0] flags,
input [zap_clog2(ALU_OPS)-1:0] op,
input i_flag_upd,
input nozero
);
begin: blk2
reg [31:0] rd;
reg [3:0] flags_out;
// Avoid accidental latch inference.
rd = 0;
flags_out = 0;
case(op)
AND: rd = rn & rm;
EOR: rd = rn ^ rm;
BIC: rd = rn & ~(rm);
MOV: rd = rm;
SAT_MOV: rd = rm;
MVN: rd = ~rm;
ORR: rd = rn | rm;
TST: rd = rn & rm; // Target is not written.
TEQ: rd = rn ^ rn; // Target is not written.
default:
begin
rd = 0;
end
endcase
// Suppose flags are not going to change at ALL.
flags_out = flags;
// Assign values to the flags only if an update is requested. Note that V
// is not touched even if change is requested.
if ( i_flag_upd ) // 0x0 for SAT_MOV.
begin
// V is preserved since flags_out = flags assignment.
flags_out[_C] = i_shift_carry_ff;
if ( nozero )
// This specifically states that we must NOT set the
// ZERO flag under any circumstance.
flags_out[_Z] = 1'd0;
else
flags_out[_Z] = (rd == 0);
flags_out[_N] = rd[31];
end
process_logical_instructions = {flags_out, rd};
end
endfunction
/*
* This task clears out the flip-flops in this module.
* The flag input is used to preserve/force flags to
* a specific state.
*/
task clear ( input [31:0] flags );
begin
o_dav_ff <= 0;
flags_ff <= flags;
o_abt_ff <= 0;
o_irq_ff <= 0;
o_fiq_ff <= 0;
o_swi_ff <= 0;
o_und_ff <= 0;
sleep_ff <= 0;
o_mem_load_ff <= 0;
o_mem_store_ff <= 0;
end
endtask
/*
* The reason we use the duplicate function is to copy value over the memory
* bus for memory stores. If we have a byte write to address 1, then the
* memory controller basically takes address 0 and byte enable 0010 and writes
* to address 1. This enables implementation of a 32-bit memory controller
* with byte enables to control updates as is commonly done. Basically this
* is to faciliate byte and halfword based writes on a 32-bit aligned memory
* bus using byte enables. The rules are simple:
* For a byte access - duplicate the lower byte of the register 4 times.
* For halfword access - duplicate the lower 16-bit of the register twice.
*/
function [31:0] duplicate ( input ub, // Unsigned byte.
input sb, // Signed byte.
input uh, // Unsigned halfword.
input sh, // Signed halfword.
input [31:0] val );
reg [31:0] x;
begin
if ( ub || sb)
begin
// Byte.
x = {val[7:0], val[7:0], val[7:0], val[7:0]};
end
else if (uh || sh)
begin
// Halfword.
x = {val[15:0], val[15:0]};
end
else
begin
x = val;
end
duplicate = x;
end
endfunction
/*
* Generate byte enables based on access mode.
* This function is similar in spirit to the previous one. The
* byte enables are generated in such a way that along with
* duplicate - byte and halfword accesses are possible.
* Rules -
* For a byte access, generate a byte enable with a 1 at the
* position that the lower 2-bits read (0,1,2,3).
* For a halfword access, based on lower 2-bits, if it is 00,
* make no change to byte enable (0011) else if it is 10, then
* make byte enable as (1100) which is basically the 32-bit
* address + 2 (and 3) which will be written.
*/
function [3:0] generate_ben ( input ub, // Unsigned byte.
input sb, // Signed byte.
input uh, // Unsigned halfword.
input sh, // Signed halfword.
input [31:0] addr );
reg [3:0] x;
begin
if ( ub || sb ) // Byte oriented.
begin
case ( addr[1:0] ) // Based on address lower 2-bits.
0: x = 1;
1: x = 1 << 1;
2: x = 1 << 2;
3: x = 1 << 3;
endcase
end
else if ( uh || sh ) // Halfword. A word = 2 half words.
begin
case ( addr[1] )
0: x = 4'b0011;
1: x = 4'b1100;
endcase
end
else
begin
x = 4'b1111; // Word oriented.
end
generate_ben = x;
end
endfunction // generate_ben
task reset;
begin
o_alu_result_ff <= 0;
o_dav_ff <= 0;
o_pc_plus_8_ff <= 0;
o_destination_index_ff <= 0;
flags_ff <= 0;
o_abt_ff <= 0;
o_irq_ff <= 0;
o_fiq_ff <= 0;
o_swi_ff <= 0;
o_mem_srcdest_index_ff <= 0;
o_mem_srcdest_index_ff <= 0;
o_mem_load_ff <= 0;
o_mem_store_ff <= 0;
o_mem_unsigned_byte_enable_ff <= 0;
o_mem_signed_byte_enable_ff <= 0;
o_mem_signed_halfword_enable_ff <= 0;
o_mem_unsigned_halfword_enable_ff<= 0;
o_mem_translate_ff <= 0;
o_mem_srcdest_value_ff <= 0;
o_ben_ff <= 0;
o_decompile <= 0;
end
endtask
endmodule // zap_alu_main.v
`default_nettype wire
// ----------------------------------------------------------------------------
// END OF FILE
// ----------------------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V |
//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//
// Version and Release Control Information:
//
// File Revision : $Revision: 275084 $
// File Date : $Date: 2014-03-27 15:09:11 +0000 (Thu, 27 Mar 2014) $
//
// Release Information : Cortex-M0 DesignStart-r1p0-00rel0
//------------------------------------------------------------------------------
// Verilog-2001 (IEEE Std 1364-2001)
//------------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
// Abstract : Testbench for the Cortex-M0 example system
//-----------------------------------------------------------------------------
//
// Modified by Ronan Barzic ([email protected]) to add support :
// - Xilinx simulation and synthesis
// - Icarus iverilog simulation
`timescale 1ns/1ps
`include "cmsdk_mcu_defs.v"
module tb_cmsdk_mcu;
`include "tb_defines.v"
parameter ROM_ADDRESS_SIZE = 16;
wire XTAL1; // crystal pin 1
wire XTAL2; // crystal pin 2
wire NRST; // active low reset
wire [15:0] P0; // Port 0
wire [15:0] P1; // Port 1
//Debug tester signals
wire nTRST;
wire TDI;
wire SWDIOTMS;
wire SWCLKTCK;
wire TDO;
wire PCLK; // Clock for UART capture device
wire [5:0] debug_command; // used to drive debug tester
wire debug_running; // indicate debug test is running
wire debug_err; // indicate debug test has error
wire debug_test_en; // To enable the debug tester connection to MCU GPIO P0
// This signal is controlled by software,
// Use "UartPutc((char) 0x1B)" to send ESCAPE code to start
// the command, use "UartPutc((char) 0x11)" to send debug test
// enable command, use "UartPutc((char) 0x12)" to send debug test
// disable command. Refer to tb_uart_capture.v file for detail
parameter BE = 0; // Big or little endian
parameter BKPT = 4; // Number of breakpoint comparators
parameter DBG = 1; // Debug configuration
parameter NUMIRQ = 32; // NUM of IRQ
parameter SMUL = 0; // Multiplier configuration
parameter SYST = 1; // SysTick
parameter WIC = 1; // Wake-up interrupt controller support
parameter WICLINES = 34; // Supported WIC lines
parameter WPT = 2; // Number of DWT comparators
// --------------------------------------------------------------------------------
// Cortex-M0/Cortex-M0+ Microcontroller
// --------------------------------------------------------------------------------
cmsdk_mcu
#(.BE (BE),
.BKPT (BKPT), // Number of breakpoint comparators
.DBG (DBG), // Debug configuration
.NUMIRQ (NUMIRQ), // NUMIRQ
.SMUL (SMUL), // Multiplier configuration
.SYST (SYST), // SysTick
.WIC (WIC), // Wake-up interrupt controller support
.WICLINES (WICLINES), // Supported WIC lines
.WPT (WPT) // Number of DWT comparators
)
u_cmsdk_mcu (
.XTAL1 (XTAL1), // input
.XTAL2 (XTAL2), // output
.NRST (NRST), // active low reset
.P0 (P0),
.P1 (P1),
.nTRST (nTRST), // Not needed if serial-wire debug is used
.TDI (TDI), // Not needed if serial-wire debug is used
.TDO (TDO), // Not needed if serial-wire debug is used
.SWDIOTMS (SWDIOTMS),
.SWCLKTCK (SWCLKTCK)
);
// --------------------------------------------------------------------------------
// Source for clock and reset
// --------------------------------------------------------------------------------
cmsdk_clkreset u_cmsdk_clkreset(
.CLK (XTAL1),
.NRST (NRST)
);
// --------------------------------------------------------------------------------
// UART output capture
// --------------------------------------------------------------------------------
assign PCLK = XTAL2;
cmsdk_uart_capture u_cmsdk_uart_capture(
.RESETn (NRST),
.CLK (PCLK),
.RXD (P1[5]), // UART 2 use for StdOut
.DEBUG_TESTER_ENABLE (debug_test_en),
.SIMULATIONEND (), // This signal set to 1 at the end of simulation.
.AUXCTRL ()
);
// UART connection cross over for UART test
assign P1[0] = P1[3]; // UART 0 RXD = UART 1 TXD
assign P1[2] = P1[1]; // UART 1 RXD = UART 0 TXD
// --------------------------------------------------------------------------------
// Debug tester connection -
// --------------------------------------------------------------------------------
// No debug connection for Cortex-M0 DesignStart
assign nTRST = NRST;
assign TDI = 1'b1;
assign SWDIOTMS = 1'b1;
assign SWCLKTCK = 1'b1;
bufif1 (P0[31-16], debug_running, debug_test_en);
bufif1 (P0[30-16], debug_err, debug_test_en);
pullup (debug_running);
pullup (debug_err);
// --------------------------------------------------------------------------------
// Misc
// --------------------------------------------------------------------------------
`ifndef SDF_SIM
task load_program_memory;
reg [1024:0] filename;
reg [7:0] memory [1<<ROM_ADDRESS_SIZE:0]; // byte type memory
integer i;
reg [31:0] tmp;
integer dummy;
begin
filename = 0;
dummy = $value$plusargs("program_memory=%s", filename);
if(filename ==0) begin
$display("WARNING! No content specified for program memory");
end
else begin
$display("-I- Loading <%s>",filename);
$readmemh (filename, memory);
for(i=0; i<((1<<ROM_ADDRESS_SIZE)/4); i=i+1) begin
tmp[7:0] = memory[i*4+0];
tmp[15:8] = memory[i*4+1];
tmp[23:16] = memory[i*4+2];
tmp[31:24] = memory[i*4+3];
u_cmsdk_mcu.u_ahb_rom.U_RAM.RAM[i] = tmp;
end
end
end
endtask // load_program_memory
`endif
// Format for time reporting
initial $timeformat(-9, 0, " ns", 0);
`ifdef IVERILOG
initial begin
load_program_memory;
$dumpfile("tb_cmsdk_mcu.vcd");
$dumpvars(0,tb_cmsdk_mcu);
end
`endif
always@(posedge `hclk) begin
if(`pc === (32'h00000100 + 4)) begin
$write("%t -I- Test Ended - Return value : %d \n",$time,`r0);
$finish(`r0);
end
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 5
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_top,Vivado 2015.1" *)
(* CHECK_LICENSE_TYPE = "triangle_intersect_auto_us_0,axi_dwidth_converter_v2_1_top,{}" *)
(* CORE_GENERATION_INFO = "triangle_intersect_auto_us_0,axi_dwidth_converter_v2_1_top,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=0,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module triangle_intersect_auto_us_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(0),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(32'H00000000),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(3'H0),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awvalid(1'H0),
.s_axi_awready(),
.s_axi_wdata(32'H00000000),
.s_axi_wstrb(4'HF),
.s_axi_wlast(1'H1),
.s_axi_wvalid(1'H0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'H0),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awvalid(),
.m_axi_awready(1'H0),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wvalid(),
.m_axi_wready(1'H0),
.m_axi_bresp(2'H0),
.m_axi_bvalid(1'H0),
.m_axi_bready(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn transaction fifo.
*
*/
module rcn_fifo
(
input rst,
input clk,
input [68:0] rcn_in,
input push,
output full,
output [68:0] rcn_out,
input pop,
output empty
);
parameter DEPTH = 4; // max 32
reg [4:0] head;
reg [4:0] tail;
reg [5:0] cnt;
wire fifo_full = (cnt == DEPTH);
wire fifo_empty = (cnt == 0);
always @ (posedge clk or posedge rst)
if (rst)
begin
head <= 5'd0;
tail <= 5'd0;
cnt <= 6'd0;
end
else
begin
if (push)
head <= (head == (DEPTH - 1)) ? 5'd0 : head + 5'd1;
if (pop)
tail <= (tail == (DEPTH - 1)) ? 5'd0 : tail + 5'd1;
case ({push, pop})
2'b10: cnt <= cnt + 6'd1;
2'b01: cnt <= cnt - 6'd1;
default: ;
endcase
end
reg [67:0] fifo[(DEPTH - 1):0];
always @ (posedge clk)
if (push)
fifo[head] <= rcn_in[67:0];
assign full = fifo_full;
assign empty = fifo_empty;
assign rcn_out = {!fifo_empty, fifo[tail]};
endmodule
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______151.636_____98.575
// CLK_OUT2____25.000______0.000______50.0______175.402_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_0
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2,
// Status and control signals
output locked
);
clk_wiz_0_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
.clk_out2(clk_out2),
// Status and control signals
.locked(locked)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR2_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_BLACKBOX_V
|
`include "timescale.v"
module fb_rxstatem (MRxClk, Reset, MRxDV, MRxDEq5, MRxDEqDataSoC, MRxDEqNumbSoC, MRxDEqDistSoC, MRxDEqDelaySoC,MRxDEqDelayDistSoC,
DelayFrameEnd, DataFrameEnd, FrmCrcStateEnd, StateIdle, StateFFS, StatePreamble,
StateNumb, StateDist, StateDelay, StateData, StateFrmCrc
);
input MRxClk;
input Reset;
input MRxDV;
input MRxDEq5;
input MRxDEqDataSoC;
input MRxDEqNumbSoC;
input MRxDEqDistSoC;
input MRxDEqDelaySoC;
input MRxDEqDelayDistSoC;
input DelayFrameEnd;
input DataFrameEnd;
input FrmCrcStateEnd;
output StateIdle;
output StateFFS;
output StatePreamble;
output [1:0] StateNumb;
output [1:0] StateDist;
output [1:0] StateDelay;
output [1:0] StateData;
output StateFrmCrc;
reg StateIdle;
reg StateFFS;
reg StatePreamble;
reg [1:0] StateNumb;
reg [1:0] StateDist;
reg [1:0] StateDelay;
reg [1:0] StateData;
reg StateFrmCrc;
wire StartIdle;
wire StartFFS;
wire StartPreamble;
wire [1:0] StartNumb;
wire [1:0] StartDist;
wire [1:0] StartDelay;
wire [1:0] StartData;
wire StartFrmCrc;
// Defining the next state
assign StartIdle = ~MRxDV & ( StatePreamble | StateFFS | (|StateData) ) | StateFrmCrc & FrmCrcStateEnd;
assign StartFFS = MRxDV & ~MRxDEq5 & StateIdle;
assign StartPreamble = MRxDV & MRxDEq5 & (StateIdle | StateFFS);
assign StartNumb[0] = MRxDV & (StatePreamble & MRxDEqNumbSoC);
assign StartNumb[1] = MRxDV & StateNumb[0];
assign StartDist[0] = MRxDV & (StatePreamble & (MRxDEqDistSoC | MRxDEqDelayDistSoC ));
assign StartDist[1] = MRxDV & StateDist[0];
assign StartDelay[0] = MRxDV & (StatePreamble & MRxDEqDelaySoC | StateDelay[1] & ~DelayFrameEnd);
assign StartDelay[1] = MRxDV & StateDelay[0];
assign StartData[0] = MRxDV & (StatePreamble & MRxDEqDataSoC | (StateData[1] & ~DataFrameEnd));
assign StartData[1] = MRxDV & StateData[0] ;
assign StartFrmCrc = MRxDV & (StateNumb[1] | StateData[1] & DataFrameEnd | StateDist[1] | StateDelay[1] & DelayFrameEnd);
/*assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 &
MRxDEqD | StateData0 & ByteCntMaxFrame);*/
// Rx State Machine
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
StateIdle <= 1'b1;
StatePreamble <= 1'b0;
StateFFS <= 1'b0;
StateNumb <= 2'b0;
StateDist <= 2'b0;
StateDelay <= 2'b0;
StateData <= 2'b0;
StateFrmCrc <= 1'b0;
end
else
begin
if(StartPreamble | StartFFS)
StateIdle <= 1'b0;
else
if(StartIdle)
StateIdle <= 1'b1;
if(StartPreamble | StartIdle)
StateFFS <= 1'b0;
else
if(StartFFS)
StateFFS <= 1'b1;
if(StartDelay[0] | StartDist[0] |StartNumb[0] | StartData[0] | StartIdle )
StatePreamble <= 1'b0;
else
if(StartPreamble)
StatePreamble <= 1'b1;
if(StartNumb[1])
StateNumb[0] <= 1'b0;
else
if(StartNumb[0])
StateNumb[0] <= 1'b1;
if(StartFrmCrc)
StateNumb[1] <= 1'b0;
else
if(StartNumb[1])
StateNumb[1] <= 1'b1;
//
if(StartDist[1])
StateDist[0] <= 1'b0;
else
if(StartDist[0])
StateDist[0] <= 1'b1;
if(StartFrmCrc)
StateDist[1] <= 1'b0;
else
if(StartDist[1])
StateDist[1] <= 1'b1;
if(StartDelay[1])
StateDelay[0] <= 1'b0;
else
if(StartDelay[0])
StateDelay[0] <= 1'b1;
if(StartFrmCrc | StartDelay[0])
StateDelay[1] <= 1'b0;
else
if(StartDelay[1])
StateDelay[1] <= 1'b1;
if(StartIdle | StartData[1])
StateData[0] <= 1'b0;
else
if(StartData[0])
StateData[0] <= 1'b1;
if(StartIdle | StartData[0] | StartFrmCrc)
StateData[1] <= 1'b0;
else
if(StartData[1])
StateData[1] <= 1'b1;
if(StartIdle)
StateFrmCrc <= 1'b0;
else
if(StartFrmCrc)
StateFrmCrc <= 1'b1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221O_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A221O_FUNCTIONAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out, C1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221O_FUNCTIONAL_V |
module main
(
//////////////////// Clock Input ////////////////////
CLOCK_27, // On Board 27 MHz
CLOCK_50, // On Board 50 MHz
EXT_CLOCK, // External Clock
//////////////////// Push Button ////////////////////
KEY, // Pushbutton[3:0]
//////////////////// DPDT Switch ////////////////////
SW, // Toggle Switch[17:0]
//////////////////// 7-SEG Dispaly ////////////////////
HEX0, // Seven Segment Digit 0
HEX1, // Seven Segment Digit 1
HEX2, // Seven Segment Digit 2
HEX3, // Seven Segment Digit 3
HEX4, // Seven Segment Digit 4
HEX5, // Seven Segment Digit 5
HEX6, // Seven Segment Digit 6
HEX7, // Seven Segment Digit 7
//////////////////////// LED ////////////////////////
LEDG, // LED Green[8:0]
LEDR, // LED Red[17:0]
//////////////////////// UART ////////////////////////
UART_TXD, // UART Transmitter
UART_RXD, // UART Receiver
//////////////////////// IRDA ////////////////////////
IRDA_TXD, // IRDA Transmitter
IRDA_RXD, // IRDA Receiver
///////////////////// SDRAM Interface ////////////////
DRAM_DQ, // SDRAM Data bus 16 Bits
DRAM_ADDR, // SDRAM Address bus 12 Bits
DRAM_LDQM, // SDRAM Low-byte Data Mask
DRAM_UDQM, // SDRAM High-byte Data Mask
DRAM_WE_N, // SDRAM Write Enable
DRAM_CAS_N, // SDRAM Column Address Strobe
DRAM_RAS_N, // SDRAM Row Address Strobe
DRAM_CS_N, // SDRAM Chip Select
DRAM_BA_0, // SDRAM Bank Address 0
DRAM_BA_1, // SDRAM Bank Address 1
DRAM_CLK, // SDRAM Clock
DRAM_CKE, // SDRAM Clock Enable
//////////////////// Flash Interface ////////////////
FL_DQ, // FLASH Data bus 8 Bits
FL_ADDR, // FLASH Address bus 20 Bits
FL_WE_N, // FLASH Write Enable
FL_RST_N, // FLASH Reset
FL_OE_N, // FLASH Output Enable
FL_CE_N, // FLASH Chip Enable
//////////////////// SRAM Interface ////////////////
SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Address bus 18 Bits
SRAM_UB_N, // SRAM High-byte Data Mask
SRAM_LB_N, // SRAM Low-byte Data Mask
SRAM_WE_N, // SRAM Write Enable
SRAM_CE_N, // SRAM Chip Enable
SRAM_OE_N, // SRAM Output Enable
//////////////////// ISP1362 Interface ////////////////
OTG_DATA, // ISP1362 Data bus 16 Bits
OTG_ADDR, // ISP1362 Address 2 Bits
OTG_CS_N, // ISP1362 Chip Select
OTG_RD_N, // ISP1362 Write
OTG_WR_N, // ISP1362 Read
OTG_RST_N, // ISP1362 Reset
OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
OTG_INT0, // ISP1362 Interrupt 0
OTG_INT1, // ISP1362 Interrupt 1
OTG_DREQ0, // ISP1362 DMA Request 0
OTG_DREQ1, // ISP1362 DMA Request 1
OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2 ////////////////
LCD_ON, // LCD Power ON/OFF
LCD_BLON, // LCD Back Light ON/OFF
LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
LCD_EN, // LCD Enable
LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
LCD_DATA, // LCD Data bus 8 bits
//////////////////// SD_Card Interface ////////////////
SD_DAT, // SD Card Data
SD_WP_N, // SD Write protect
SD_CMD, // SD Card Command Signal
SD_CLK, // SD Card Clock
//////////////////// USB JTAG link ////////////////////
TDI, // CPLD -> FPGA (Data in)
TCK, // CPLD -> FPGA (Clock)
TCS, // CPLD -> FPGA (CS)
TDO, // FPGA -> CPLD (Data out)
//////////////////// I2C ////////////////////////////
I2C_SDAT, // I2C Data
I2C_SCLK, // I2C Clock
//////////////////// PS2 ////////////////////////////
PS2_DAT, // PS2 Data
PS2_CLK, // PS2 Clock
//////////////////// VGA ////////////////////////////
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK, // VGA BLANK
VGA_SYNC, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // VGA Blue[9:0]
//////////// Ethernet Interface ////////////////////////
ENET_DATA, // DM9000A DATA bus 16Bits
ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
ENET_CS_N, // DM9000A Chip Select
ENET_WR_N, // DM9000A Write
ENET_RD_N, // DM9000A Read
ENET_RST_N, // DM9000A Reset
ENET_INT, // DM9000A Interrupt
ENET_CLK, // DM9000A Clock 25 MHz
//////////////// Audio CODEC ////////////////////////
AUD_ADCLRCK, // Audio CODEC ADC LR Clock
AUD_ADCDAT, // Audio CODEC ADC Data
AUD_DACLRCK, // Audio CODEC DAC LR Clock
AUD_DACDAT, // Audio CODEC DAC Data
AUD_BCLK, // Audio CODEC Bit-Stream Clock
AUD_XCK, // Audio CODEC Chip Clock
//////////////// TV Decoder ////////////////////////
TD_DATA, // TV Decoder Data bus 8 bits
TD_HS, // TV Decoder H_SYNC
TD_VS, // TV Decoder V_SYNC
TD_RESET, // TV Decoder Reset
TD_CLK, // TV Decoder Line Locked Clock
//iTD_CLK, // TV Decoder Line Locked Clock
//////////////////// GPIO ////////////////////////////
GPIO_0, // GPIO Connection 0
GPIO_1 // GPIO Connection 1
);
//////////////////////// Clock Input ////////////////////////
input CLOCK_27; // On Board 27 MHz
input CLOCK_50; // On Board 50 MHz
input EXT_CLOCK; // External Clock
//////////////////////// Push Button ////////////////////////
input [3:0] KEY; // Pushbutton[3:0]
//////////////////////// DPDT Switch ////////////////////////
input [17:0] SW; // Toggle Switch[17:0]
//////////////////////// 7-SEG Display ////////////////////////
output [6:0] HEX0; // Seven Segment Digit 0
output [6:0] HEX1; // Seven Segment Digit 1
output [6:0] HEX2; // Seven Segment Digit 2
output [6:0] HEX3; // Seven Segment Digit 3
output [6:0] HEX4; // Seven Segment Digit 4
output [6:0] HEX5; // Seven Segment Digit 5
output [6:0] HEX6; // Seven Segment Digit 6
output [6:0] HEX7; // Seven Segment Digit 7
//////////////////////////// LED ////////////////////////////
output [8:0] LEDG; // LED Green[8:0]
output [17:0] LEDR; // LED Red[17:0]
//////////////////////////// UART ////////////////////////////
output UART_TXD; // UART Transmitter
input UART_RXD; // UART Receiver
//////////////////////////// IRDA ////////////////////////////
output IRDA_TXD; // IRDA Transmitter
input IRDA_RXD; // IRDA Receiver
/////////////////////// SDRAM Interface ////////////////////////
inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
output DRAM_LDQM; // SDRAM Low-byte Data Mask
output DRAM_UDQM; // SDRAM High-byte Data Mask
output DRAM_WE_N; // SDRAM Write Enable
output DRAM_CAS_N; // SDRAM Column Address Strobe
output DRAM_RAS_N; // SDRAM Row Address Strobe
output DRAM_CS_N; // SDRAM Chip Select
output DRAM_BA_0; // SDRAM Bank Address 0
output DRAM_BA_1; // SDRAM Bank Address 0
output DRAM_CLK; // SDRAM Clock
output DRAM_CKE; // SDRAM Clock Enable
//////////////////////// Flash Interface ////////////////////////
inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
output FL_WE_N; // FLASH Write Enable
output FL_RST_N; // FLASH Reset
output FL_OE_N; // FLASH Output Enable
output FL_CE_N; // FLASH Chip Enable
//////////////////////// SRAM Interface ////////////////////////
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output SRAM_UB_N; // SRAM Low-byte Data Mask
output SRAM_LB_N; // SRAM High-byte Data Mask
output SRAM_WE_N; // SRAM Write Enable
output SRAM_CE_N; // SRAM Chip Enable
output SRAM_OE_N; // SRAM Output Enable
//////////////////// ISP1362 Interface ////////////////////////
inout [15:0] OTG_DATA; // ISP1362 Data bus 16 Bits
output [1:0] OTG_ADDR; // ISP1362 Address 2 Bits
output OTG_CS_N; // ISP1362 Chip Select
output OTG_RD_N; // ISP1362 Write
output OTG_WR_N; // ISP1362 Read
output OTG_RST_N; // ISP1362 Reset
output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
input OTG_INT0; // ISP1362 Interrupt 0
input OTG_INT1; // ISP1362 Interrupt 1
input OTG_DREQ0; // ISP1362 DMA Request 0
input OTG_DREQ1; // ISP1362 DMA Request 1
output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2 ////////////////////////////
inout [7:0] LCD_DATA; // LCD Data bus 8 bits
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN; // LCD Enable
output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
//////////////////// SD Card Interface ////////////////////////
inout [3:0] SD_DAT; // SD Card Data
input SD_WP_N; // SD write protect
inout SD_CMD; // SD Card Command Signal
output SD_CLK; // SD Card Clock
//////////////////////// I2C ////////////////////////////////
inout I2C_SDAT; // I2C Data
output I2C_SCLK; // I2C Clock
//////////////////////// PS2 ////////////////////////////////
input PS2_DAT; // PS2 Data
input PS2_CLK; // PS2 Clock
//////////////////// USB JTAG link ////////////////////////////
input TDI; // CPLD -> FPGA (data in)
input TCK; // CPLD -> FPGA (clk)
input TCS; // CPLD -> FPGA (CS)
output TDO; // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK; // VGA BLANK
output VGA_SYNC; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
//////////////// Ethernet Interface ////////////////////////////
inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits
output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
output ENET_CS_N; // DM9000A Chip Select
output ENET_WR_N; // DM9000A Write
output ENET_RD_N; // DM9000A Read
output ENET_RST_N; // DM9000A Reset
input ENET_INT; // DM9000A Interrupt
output ENET_CLK; // DM9000A Clock 25 MHz
//////////////////// Audio CODEC ////////////////////////////
inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock
//////////////////// TV Devoder ////////////////////////////
input [7:0] TD_DATA; // TV Decoder Data bus 8 bits
input TD_HS; // TV Decoder H_SYNC
input TD_VS; // TV Decoder V_SYNC
output TD_RESET; // TV Decoder Reset
input TD_CLK; // TV Decoder Line Locked Clock
//input iTD_CLK; // TV Decoder Line Locked Clock
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
// Flash
assign FL_RST_N = 1'b1;
wire FL_16BIT_IP_A0;
// 16*2 LCD Module
assign LCD_ON = 1'b1; // LCD ON
assign LCD_BLON = 1'b1; // LCD Back Light
// All inout port turn to tri-state
assign SD_DAT[0] = 1'bz;
assign AUD_ADCLRCK = AUD_DACLRCK;
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
// Disable USB speed select
assign OTG_FSPEED = 1'bz;
assign OTG_LSPEED = 1'bz;
// Turn On TV Decoder
assign TD_RESET = KEY[0];
// Set SD Card to SD Mode
wire [3:1] SD_DAT_dummy;
assign SD_DAT_dummy = 3'bzzz;
assign SD_DAT[3] = 1'b1;
//========== SSRAM
wire [1:0] SRAM_DUMMY_ADDR; // used to ignore the A0/A1 pin from Cypress SSRAM IP core
wire [15:0] SRAM_DUMMY_DQ;
//========== SDRAM
assign DRAM_CLK = pll_c1_memory;
wire CPU_RESET_N;
wire pll_c0_system, pll_c1_memory, pll_c2_audio;
// Reset
Reset_Delay delay1 (.iRST(KEY[0]),.iCLK(CLOCK_50),.oRESET(CPU_RESET_N));
///////////////////////// adding your SoPC here ////////////////////////////////
DE2_SoPC DE2_SoPC_inst
(
// globe signals
.clk_50 (CLOCK_50),
.reset_n (CPU_RESET_N),
//.pll_c0_system (pll_c0_system),
//.pll_c1_memory (pll_c1_memory),
//.pll_c2_audio (pll_c2_audio),
//sdram
/*
.zs_addr_from_the_sdram (DRAM_ADDR),
.zs_ba_from_the_sdram ({DRAM_BA_1,DRAM_BA_0}),
.zs_cas_n_from_the_sdram (DRAM_CAS_N),
.zs_cke_from_the_sdram (DRAM_CKE),
.zs_cs_n_from_the_sdram (DRAM_CS_N),
.zs_dq_to_and_from_the_sdram (DRAM_DQ),
.zs_dqm_from_the_sdram ({DRAM_UDQM,DRAM_LDQM}),
.zs_ras_n_from_the_sdram (DRAM_RAS_N),
.zs_we_n_from_the_sdram (DRAM_WE_N),
*/
//ssram
.SRAM_ADDR_from_the_sram (SRAM_ADDR),
.SRAM_CE_N_from_the_sram (SRAM_CE_N),
.SRAM_DQ_to_and_from_the_sram (SRAM_DQ),
.SRAM_LB_N_from_the_sram (SRAM_LB_N),
.SRAM_OE_N_from_the_sram (SRAM_OE_N),
.SRAM_UB_N_from_the_sram (SRAM_UB_N),
.SRAM_WE_N_from_the_sram (SRAM_WE_N),
//flash
.tri_state_bridge_flash_address (FL_ADDR),
.tri_state_bridge_flash_readn (FL_OE_N),
.write_n_to_the_cfi_flash_0 (FL_WE_N),
.select_n_to_the_cfi_flash_0 (FL_CE_N),
.tri_state_bridge_flash_data (FL_DQ),
//lcd
.LCD_E_from_the_lcd (LCD_EN),
.LCD_RS_from_the_lcd (LCD_RS),
.LCD_RW_from_the_lcd (LCD_RW),
.LCD_data_to_and_from_the_lcd (LCD_DATA),
//i2c
.scl_pad_io_to_and_from_the_i2c (I2C_SCLK),//(I2C_SCLK),
.sda_pad_io_to_and_from_the_i2c (I2C_SDAT),//(I2C_SDAT),
/*
//sd card
.out_port_from_the_SD_CLK (SD_CLK),
.bidir_port_to_and_from_the_SD_CMD (SD_CMD),
.bidir_port_to_and_from_the_SD_DAT ({SD_DAT_dummy,SD_DAT[0]}),
//.bidir_port_to_and_from_the_sd_dat3 (SD_DAT[3]),
//swtich
.in_port_to_the_pio_button (KEY[3:1]),
.in_port_to_the_pio_switch (SW[17:0]),
//hex
.oSEG0_from_the_seg7 (HEX0),
.oSEG1_from_the_seg7 (HEX1),
.oSEG2_from_the_seg7 (HEX2),
.oSEG3_from_the_seg7 (HEX3),
.oSEG4_from_the_seg7 (HEX4),
.oSEG5_from_the_seg7 (HEX5),
.oSEG6_from_the_seg7 (HEX6),
.oSEG7_from_the_seg7 (HEX7),
//led
.out_port_from_the_pio_green_led (LEDG),
.out_port_from_the_pio_red_led (LEDR),
*/
//the_uart
.rxd_to_the_uart (UART_RXD),
.txd_from_the_uart (UART_TXD),
//vga
.VGA_BLANK_from_the_vga_0 (VGA_BLANK),
.VGA_B_from_the_vga_0 (VGA_B),
.VGA_CLK_from_the_vga_0 (VGA_CLK),
.VGA_G_from_the_vga_0 (VGA_G),
.VGA_HS_from_the_vga_0 (VGA_HS),
.VGA_R_from_the_vga_0 (VGA_R),
.VGA_SYNC_from_the_vga_0 (VGA_SYNC),
.VGA_VS_from_the_vga_0 (VGA_VS),
.iCLK_25_to_the_vga_0 (CLOCK_27)
);
///////////////////////////////////////////////////////////////////////////////////
endmodule
module Reset_Delay(iRST,iCLK,oRESET);
input iCLK;
input iRST;
output reg oRESET;
reg [27:0] Cont;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
oRESET <= 1'b0;
Cont <= 28'h0000000;
end
else
begin
if(Cont!=28'h4FFFFFF) // about 300ms at 50MHz
begin
Cont <= Cont+1;
oRESET <= 1'b0;
end
else
oRESET <= 1'b1;
end
end
endmodule
/////////////////// sopc binding referance ////////////////////////
/*
DE2_SoPC DE2_SoPC_inst
(
// globe signals
.clk_50 (CLOCK_50),
.reset_n (CPU_RESET_N),
.pll_c0_system (pll_c0_system),
.pll_c1_memory (pll_c1_memory),
.pll_c2_audio (pll_c2_audio),
//sdram
.zs_addr_from_the_sdram (DRAM_ADDR),
.zs_ba_from_the_sdram ({DRAM_BA_1,DRAM_BA_0}),
.zs_cas_n_from_the_sdram (DRAM_CAS_N),
.zs_cke_from_the_sdram (DRAM_CKE),
.zs_cs_n_from_the_sdram (DRAM_CS_N),
.zs_dq_to_and_from_the_sdram (DRAM_DQ),
.zs_dqm_from_the_sdram ({DRAM_UDQM,DRAM_LDQM}),
.zs_ras_n_from_the_sdram (DRAM_RAS_N),
.zs_we_n_from_the_sdram (DRAM_WE_N),
//ssram
.SRAM_ADDR_from_the_sram (SRAM_ADDR),
.SRAM_CE_N_from_the_sram (SRAM_CE_N),
.SRAM_DQ_to_and_from_the_sram (SRAM_DQ),
.SRAM_LB_N_from_the_sram (SRAM_LB_N),
.SRAM_OE_N_from_the_sram (SRAM_OE_N),
.SRAM_UB_N_from_the_sram (SRAM_UB_N),
.SRAM_WE_N_from_the_sram (SRAM_WE_N),
//flash
.tri_state_bridge_flash_address (FL_ADDR),
.tri_state_bridge_flash_readn (FL_OE_N),
.write_n_to_the_cfi_flash (FL_WE_N),
.select_n_to_the_cfi_flash (FL_CE_N),
.tri_state_bridge_flash_data (FL_DQ),
//lcd
.LCD_E_from_the_lcd (LCD_EN),
.LCD_RS_from_the_lcd (LCD_RS),
.LCD_RW_from_the_lcd (LCD_RW),
.LCD_data_to_and_from_the_lcd (LCD_DATA),
//i2c
.out_port_from_the_i2c_sclk (),//(I2C_SCLK),
.bidir_port_to_and_from_the_i2c_sdat (),//(I2C_SDAT),
//sd card
.out_port_from_the_SD_CLK (SD_CLK),
.bidir_port_to_and_from_the_SD_CMD (SD_CMD),
.bidir_port_to_and_from_the_SD_DAT ({SD_DAT_dummy,SD_DAT[0]}),
//.bidir_port_to_and_from_the_sd_dat3 (SD_DAT[3]),
//swtich
.in_port_to_the_pio_button (KEY[3:1]),
.in_port_to_the_pio_switch (SW[17:0]),
//hex
.oSEG0_from_the_seg7 (HEX0),
.oSEG1_from_the_seg7 (HEX1),
.oSEG2_from_the_seg7 (HEX2),
.oSEG3_from_the_seg7 (HEX3),
.oSEG4_from_the_seg7 (HEX4),
.oSEG5_from_the_seg7 (HEX5),
.oSEG6_from_the_seg7 (HEX6),
.oSEG7_from_the_seg7 (HEX7),
//led
.out_port_from_the_pio_green_led (LEDG),
.out_port_from_the_pio_red_led (LEDR),
//the_uart
.rxd_to_the_uart (UART_RXD),
.txd_from_the_uart (UART_TXD),
//vga
.VGA_BLANK_from_the_vga (VGA_BLANK),
.VGA_B_from_the_vga (VGA_B),
.VGA_CLK_from_the_vga (VGA_CLK),
.VGA_G_from_the_vga (VGA_G),
.VGA_HS_from_the_vga (VGA_HS),
.VGA_R_from_the_vga (VGA_R),
.VGA_SYNC_from_the_vga (VGA_SYNC),
.VGA_VS_from_the_vga (VGA_VS),
.iCLK_25_to_the_vga (CLOCK_27)
);
*/ |
// simple ram
// 2014, [email protected]
module tg68_ram #(
parameter MS = 512
)(
input wire clk,
input wire tg68_as,
input wire [ 32-1:0] tg68_adr,
input wire tg68_rw,
input wire tg68_lds,
input wire tg68_uds,
input wire [ 16-1:0] tg68_dat_out,
output wire [ 16-1:0] tg68_dat_in,
output wire tg68_dtack
);
// memory
reg [8-1:0] mem0 [0:MS-1];
reg [8-1:0] mem1 [0:MS-1];
// internal signals
reg [16-1:0] mem_do = 0;
reg trn = 1;
reg ack = 1;
// clear on start
integer i;
initial begin
for (i=0; i<MS; i=i+1) begin
mem1[i] = 0;
mem0[i] = 0;
end
end
// read
always @ (posedge clk) begin
if (!tg68_as && tg68_rw) mem_do <= #1 {mem1[tg68_adr[31:1]], mem0[tg68_adr[31:1]]};
end
//write
always @ (posedge clk) begin
if (!tg68_as && !tg68_rw) begin
if (!tg68_uds) mem1[tg68_adr[31:1]] <= #1 tg68_dat_out[15:8];
if (!tg68_lds) mem0[tg68_adr[31:1]] <= #1 tg68_dat_out[7:0];
end
end
// acknowledge
always @ (posedge clk) begin
trn <= #1 tg68_as;
ack <= #1 trn;
end
// outputs
assign tg68_dat_in = mem_do;
assign tg68_dtack = ack || tg68_as; // TODO
// load task
task load;
input [1024*8-1:0] file;
reg [16-1:0] memory[0:MS-1];
reg [16-1:0] dat;
integer i;
begin
$readmemh(file, memory);
for (i=0; i<MS; i=i+1) begin
dat = memory[i];
mem1[i] = dat[15:8];
mem0[i] = dat[7:0];
end
end
endtask
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_interrupt.v
// Title : Interrupt logic
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_interrupt (
// ----- Inputs -------
clk_i,
rst_i,
// From external devices
interrupt,
// From pipeline
stall_x,
`ifdef CFG_DEBUG_ENABLED
non_debug_exception,
debug_exception,
`else
exception,
`endif
eret_q_x,
`ifdef CFG_DEBUG_ENABLED
bret_q_x,
`endif
csr,
csr_write_data,
csr_write_enable,
// ----- Outputs -------
interrupt_exception,
// To pipeline
csr_read_data
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input [interrupts-1:0] interrupt; // Interrupt pins, active-low
input stall_x; // Stall X pipeline stage
`ifdef CFG_DEBUG_ENABLED
input non_debug_exception; // Non-debug related exception has been raised
input debug_exception; // Debug-related exception has been raised
`else
input exception; // Exception has been raised
`endif
input eret_q_x; // Return from exception
`ifdef CFG_DEBUG_ENABLED
input bret_q_x; // Return from breakpoint
`endif
input [`LM32_CSR_RNG] csr; // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input csr_write_enable; // CSR write enable
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output interrupt_exception; // Request to raide an interrupt exception
wire interrupt_exception;
output [`LM32_WORD_RNG] csr_read_data; // Data read from CSR
reg [`LM32_WORD_RNG] csr_read_data;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted
//pragma attribute asserted preserve_signal true
wire [interrupts-1:0] interrupt_n_exception;
// Interrupt CSRs
reg ie; // Interrupt enable
reg eie; // Exception interrupt enable
`ifdef CFG_DEBUG_ENABLED
reg bie; // Breakpoint interrupt enable
`endif
reg [interrupts-1:0] ip; // Interrupt pending
reg [interrupts-1:0] im; // Interrupt mask
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Determine which interrupts have occured and are unmasked
assign interrupt_n_exception = ip & im;
// Determine if any unmasked interrupts have occured
assign interrupt_exception = (|interrupt_n_exception) & ie;
// Determine which interrupts are currently being asserted (active-low) or are already pending
assign asserted = ip | interrupt;
assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
assign ip_csr_read_data = ip;
assign im_csr_read_data = im;
generate
if (interrupts > 1)
begin
// CSR read
always @(*)
begin
case (csr)
`LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
`LM32_CSR_IP: csr_read_data = ip;
`LM32_CSR_IM: csr_read_data = im;
default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
end
else
begin
// CSR read
always @(*)
begin
case (csr)
`LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
`LM32_CSR_IP: csr_read_data = ip;
default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
end
endgenerate
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
generate
if (interrupts > 1)
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
ie <= `FALSE;
eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
bie <= `FALSE;
`endif
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
end
else
begin
// Set IP bit when interrupt line is asserted
ip <= asserted;
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
else if (debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
bie <= ie;
ie <= `FALSE;
end
`else
if (exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
// Restore interrupt enable
ie <= eie;
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
ie <= bie;
`endif
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
if (csr == `LM32_CSR_IE)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
bie <= csr_write_data[2];
`endif
end
if (csr == `LM32_CSR_IM)
im <= csr_write_data[interrupts-1:0];
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
end
end
end
else
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
ie <= `FALSE;
eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
bie <= `FALSE;
`endif
ip <= {interrupts{1'b0}};
end
else
begin
// Set IP bit when interrupt line is asserted
ip <= asserted;
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
else if (debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
bie <= ie;
ie <= `FALSE;
end
`else
if (exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
// Restore interrupt enable
ie <= eie;
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
ie <= bie;
`endif
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
if (csr == `LM32_CSR_IE)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
bie <= csr_write_data[2];
`endif
end
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
end
end
end
endgenerate
endmodule
|
(** * Lists: Working with Structured Data *)
From LF Require Export Induction.
Module NatList.
(* ################################################################# *)
(** * Pairs of Numbers *)
(** In an [Inductive] type definition, each constructor can take
any number of arguments -- none (as with [true] and [O]), one (as
with [S]), or more than one (as with [nybble], and here): *)
Inductive natprod : Type :=
| pair (n1 n2 : nat).
(** This declaration can be read: "The one and only way to
construct a pair of numbers is by applying the constructor [pair]
to two arguments of type [nat]." *)
Check (pair 3 5) : natprod.
(** Here are simple functions for extracting the first and
second components of a pair. *)
Definition fst (p : natprod) : nat :=
match p with
| pair x y => x
end.
Definition snd (p : natprod) : nat :=
match p with
| pair x y => y
end.
Compute (fst (pair 3 5)).
(* ===> 3 *)
(** Since pairs will be used heavily in what follows, it is nice
to be able to write them with the standard mathematical notation
[(x,y)] instead of [pair x y]. We can tell Coq to allow this with
a [Notation] declaration. *)
Notation "( x , y )" := (pair x y).
(** The new notation can be used both in expressions and in pattern
matches. *)
Compute (fst (3,5)).
Definition fst' (p : natprod) : nat :=
match p with
| (x,y) => x
end.
Definition snd' (p : natprod) : nat :=
match p with
| (x,y) => y
end.
Definition swap_pair (p : natprod) : natprod :=
match p with
| (x,y) => (y,x)
end.
(** Note that pattern-matching on a pair (with parentheses: [(x, y)])
is not to be confused with the "multiple pattern" syntax (with no
parentheses: [x, y]) that we have seen previously. The above
examples illustrate pattern matching on a pair with elements [x]
and [y], whereas, for example, the definition of [minus] in
[Basics] performs pattern matching on the values [n] and [m]:
Fixpoint minus (n m : nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
The distinction is minor, but it is worth knowing that they
are not the same. For instance, the following definitions are
ill-formed:
(* Can't match on a pair with multiple patterns: *)
Definition bad_fst (p : natprod) : nat :=
match p with
| x, y => x
end.
(* Can't match on multiple values with pair patterns: *)
Definition bad_minus (n m : nat) : nat :=
match n, m with
| (O , _ ) => O
| (S _ , O ) => n
| (S n', S m') => bad_minus n' m'
end.
*)
(** Now let's try to prove a few simple facts about pairs.
If we state properties of pairs in a slightly peculiar way, we can
sometimes complete their proofs with just reflexivity (and its
built-in simplification): *)
Theorem surjective_pairing' : forall (n m : nat),
(n,m) = (fst (n,m), snd (n,m)).
Proof.
reflexivity. Qed.
(** But [reflexivity] is not enough if we state the lemma in a more
natural way: *)
Theorem surjective_pairing_stuck : forall (p : natprod),
p = (fst p, snd p).
Proof.
simpl. (* Doesn't reduce anything! *)
Abort.
(** Instead, we need to expose the structure of [p] so that
[simpl] can perform the pattern match in [fst] and [snd]. We can
do this with [destruct]. *)
Theorem surjective_pairing : forall (p : natprod),
p = (fst p, snd p).
Proof.
intros p. destruct p as [n m]. simpl. reflexivity. Qed.
(** Notice that, unlike its behavior with [nat]s, where it
generates two subgoals, [destruct] generates just one subgoal
here. That's because [natprod]s can only be constructed in one
way. *)
(** **** Exercise: 1 star, standard (snd_fst_is_swap) *)
Theorem snd_fst_is_swap : forall (p : natprod),
(snd p, fst p) = swap_pair p.
Proof.
destruct p. simpl. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star, standard, optional (fst_swap_is_snd) *)
Theorem fst_swap_is_snd : forall (p : natprod),
fst (swap_pair p) = snd p.
Proof.
destruct p. simpl. reflexivity. Qed.
(** [] *)
(* ################################################################# *)
(** * Lists of Numbers *)
(** Generalizing the definition of pairs, we can describe the
type of _lists_ of numbers like this: "A list is either the empty
list or else a pair of a number and another list." *)
Inductive natlist : Type :=
| nil
| cons (n : nat) (l : natlist).
(** For example, here is a three-element list: *)
Definition mylist := cons 1 (cons 2 (cons 3 nil)).
(** As with pairs, it is more convenient to write lists in
familiar programming notation. The following declarations
allow us to use [::] as an infix [cons] operator and square
brackets as an "outfix" notation for constructing lists. *)
Notation "x :: l" := (cons x l)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y nil) ..).
(** It is not necessary to understand the details of these
declarations, but here is roughly what's going on in case you are
interested. The "[right associativity]" annotation tells Coq how to
parenthesize expressions involving multiple uses of [::] so that,
for example, the next three declarations mean exactly the same
thing: *)
Definition mylist1 := 1 :: (2 :: (3 :: nil)).
Definition mylist2 := 1 :: 2 :: 3 :: nil.
Definition mylist3 := [1;2;3].
(** The "[at level 60]" part tells Coq how to parenthesize
expressions that involve both [::] and some other infix operator.
For example, since we defined [+] as infix notation for the [plus]
function at level 50,
Notation "x + y" := (plus x y)
(at level 50, left associativity).
the [+] operator will bind tighter than [::], so [1 + 2 :: [3]]
will be parsed, as we'd expect, as [(1 + 2) :: [3]] rather than
[1 + (2 :: [3])].
(Expressions like "[1 + 2 :: [3]]" can be a little confusing when
you read them in a [.v] file. The inner brackets, around 3, indicate
a list, but the outer brackets, which are invisible in the HTML
rendering, are there to instruct the "coqdoc" tool that the bracketed
part should be displayed as Coq code rather than running text.)
The second and third [Notation] declarations above introduce the
standard square-bracket notation for lists; the right-hand side of
the third one illustrates Coq's syntax for declaring n-ary
notations and translating them to nested sequences of binary
constructors. *)
(* ----------------------------------------------------------------- *)
(** *** Repeat *)
(** Next let's look at several functions for constructing and
manipulating lists. First, the [repeat] function takes a number
[n] and a [count] and returns a list of length [count] in which
every element is [n]. *)
Fixpoint repeat (n count : nat) : natlist :=
match count with
| O => nil
| S count' => n :: (repeat n count')
end.
(* ----------------------------------------------------------------- *)
(** *** Length *)
(** The [length] function calculates the length of a list. *)
Fixpoint length (l:natlist) : nat :=
match l with
| nil => O
| h :: t => S (length t)
end.
(* ----------------------------------------------------------------- *)
(** *** Append *)
(** The [app] function concatenates (appends) two lists. *)
Fixpoint app (l1 l2 : natlist) : natlist :=
match l1 with
| nil => l2
| h :: t => h :: (app t l2)
end.
(** Since [app] will be used extensively, it is again convenient
to have an infix operator for it. *)
Notation "x ++ y" := (app x y)
(right associativity, at level 60).
Example test_app1: [1;2;3] ++ [4;5] = [1;2;3;4;5].
Proof. reflexivity. Qed.
Example test_app2: nil ++ [4;5] = [4;5].
Proof. reflexivity. Qed.
Example test_app3: [1;2;3] ++ nil = [1;2;3].
Proof. reflexivity. Qed.
(* ----------------------------------------------------------------- *)
(** *** Head and Tail *)
(** Here are two smaller examples of programming with lists.
The [hd] function returns the first element (the "head") of the
list, while [tl] returns everything but the first element (the
"tail"). Since the empty list has no first element, we pass
a default value to be returned in that case. *)
Definition hd (default : nat) (l : natlist) : nat :=
match l with
| nil => default
| h :: t => h
end.
Definition tl (l : natlist) : natlist :=
match l with
| nil => nil
| h :: t => t
end.
Example test_hd1: hd 0 [1;2;3] = 1.
Proof. reflexivity. Qed.
Example test_hd2: hd 0 [] = 0.
Proof. reflexivity. Qed.
Example test_tl: tl [1;2;3] = [2;3].
Proof. reflexivity. Qed.
(* ----------------------------------------------------------------- *)
(** *** Exercises *)
(** **** Exercise: 2 stars, standard, especially useful (list_funs)
Complete the definitions of [nonzeros], [oddmembers], and
[countoddmembers] below. Have a look at the tests to understand
what these functions should do. *)
Fixpoint nonzeros (l:natlist) : natlist :=
match l with
| [] => []
| (0 :: xs) => nonzeros xs
| (n :: xs) => n :: nonzeros xs
end.
Example test_nonzeros:
nonzeros [0;1;0;2;3;0;0] = [1;2;3].
Proof. reflexivity. Qed.
Fixpoint oddmembers (l:natlist) : natlist :=
match l with
| [] => []
| (n :: xs) => match oddb n with
| true => n :: (oddmembers xs)
| false => oddmembers xs
end
end.
Example test_oddmembers:
oddmembers [0;1;0;2;3;0;0] = [1;3].
Proof. reflexivity. Qed.
Definition countoddmembers (l:natlist) : nat :=
length (oddmembers l).
Example test_countoddmembers1:
countoddmembers [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers2:
countoddmembers [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers3:
countoddmembers nil = 0.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (alternate)
Complete the following definition of [alternate], which
interleaves two lists into one, alternating between elements taken
from the first list and elements from the second. See the tests
below for more specific examples.
(Note: one natural and elegant way of writing [alternate] will
fail to satisfy Coq's requirement that all [Fixpoint] definitions
be "obviously terminating." If you find yourself in this rut,
look for a slightly more verbose solution that considers elements
of both lists at the same time. One possible solution involves
defining a new kind of pairs, but this is not the only way.) *)
Fixpoint alternate (l1 l2 : natlist) : natlist :=
match l1 with
| [] => l2
| (x::xs) => match l2 with
| [] => x::xs
| (y::ys) => x :: y :: (alternate xs ys)
end
end.
Example test_alternate1:
alternate [1;2;3] [4;5;6] = [1;4;2;5;3;6].
Proof. reflexivity. Qed.
Example test_alternate2:
alternate [1] [4;5;6] = [1;4;5;6].
Proof. reflexivity. Qed.
Example test_alternate3:
alternate [1;2;3] [4] = [1;4;2;3].
Proof. simpl. reflexivity. Qed.
Example test_alternate4:
alternate [] [20;30] = [20;30].
Proof. reflexivity. Qed.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Bags via Lists *)
(** A [bag] (or [multiset]) is like a set, except that each element
can appear multiple times rather than just once. One possible
representation for a bag of numbers is as a list. *)
Definition bag := natlist.
(** **** Exercise: 3 stars, standard, especially useful (bag_functions)
Complete the following definitions for the functions
[count], [sum], [add], and [member] for bags. *)
Fixpoint count (v : nat) (s : bag) : nat :=
match s with
| [] => 0
| n::xs => match eqb n v with
| true => S (count v xs)
| false => count v xs
end
end.
(** All these proofs can be done just by [reflexivity]. *)
Example test_count1: count 1 [1;2;3;1;4;1] = 3.
Proof. reflexivity. Qed.
Example test_count2: count 6 [1;2;3;1;4;1] = 0.
Proof. reflexivity. Qed.
(** Multiset [sum] is similar to set [union]: [sum a b] contains all
the elements of [a] and of [b]. (Mathematicians usually define
[union] on multisets a little bit differently -- using max instead
of sum -- which is why we don't call this operation [union].) For
[sum], we're giving you a header that does not give explicit names
to the arguments. Moreover, it uses the keyword [Definition]
instead of [Fixpoint], so even if you had names for the arguments,
you wouldn't be able to process them recursively. The point of
stating the question this way is to encourage you to think about
whether [sum] can be implemented in another way -- perhaps by
using one or more functions that have already been defined. *)
Definition sum : bag -> bag -> bag := app.
Example test_sum1: count 1 (sum [1;2;3] [1;4;1]) = 3.
Proof. reflexivity. Qed.
Definition add (v : nat) (s : bag) : bag := cons v s.
Example test_add1: count 1 (add 1 [1;4;1]) = 3.
Proof. reflexivity. Qed.
Example test_add2: count 5 (add 1 [1;4;1]) = 0.
Proof. reflexivity. Qed.
Definition member (v : nat) (s : bag) : bool := ltb 0 (count v s).
Example test_member1: member 1 [1;4;1] = true.
Proof. reflexivity. Qed.
Example test_member2: member 2 [1;4;1] = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (bag_more_functions)
Here are some more [bag] functions for you to practice with. *)
(** When [remove_one] is applied to a bag without the number to
remove, it should return the same bag unchanged. (This exercise
is optional, but students following the advanced track will need
to fill in the definition of [remove_one] for a later
exercise.) *)
Fixpoint remove_one (v : nat) (s : bag) : bag :=
match s with
| [] => []
| x::xs => match eqb v x with
| true => xs
| false => x :: (remove_one v xs)
end
end.
Example test_remove_one1:
count 5 (remove_one 5 [2;1;5;4;1]) = 0.
Proof. reflexivity. Qed.
Example test_remove_one2:
count 5 (remove_one 5 [2;1;4;1]) = 0.
Proof. reflexivity. Qed.
Example test_remove_one3:
count 4 (remove_one 5 [2;1;4;5;1;4]) = 2.
Proof. reflexivity. Qed.
Example test_remove_one4:
count 5 (remove_one 5 [2;1;5;4;5;1;4]) = 1.
Proof. reflexivity. Qed.
Fixpoint remove_all (v:nat) (s:bag) : bag :=
match s with
| [] => []
| x::xs => match eqb v x with
| true => remove_all v xs
| false => x :: (remove_all v xs)
end
end.
Example test_remove_all1: count 5 (remove_all 5 [2;1;5;4;1]) = 0.
Proof. reflexivity. Qed.
Example test_remove_all2: count 5 (remove_all 5 [2;1;4;1]) = 0.
Proof. reflexivity. Qed.
Example test_remove_all3: count 4 (remove_all 5 [2;1;4;5;1;4]) = 2.
Proof. reflexivity. Qed.
Example test_remove_all4: count 5 (remove_all 5 [2;1;5;4;5;1;4;5;1;4]) = 0.
Proof. reflexivity. Qed.
Fixpoint subset (s1 : bag) (s2 : bag) : bool :=
match s1 with
| [] => true
| (x::xs) => match member x s2 with
| true => subset xs (remove_one x s2)
| false => false
end
end.
Example test_subset1: subset [1;2] [2;1;4;1] = true.
Proof. reflexivity. Qed.
Example test_subset2: subset [1;2;2] [2;1;4;1] = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars, standard, especially useful (add_inc_count)
Adding a value to a bag should increase the value's count by one.
State that as a theorem and prove it. *)
Theorem eqb_n : forall n, n =? n = true.
Proof.
intros.
induction n.
- reflexivity.
- simpl. rewrite IHn. reflexivity.
Qed.
Theorem add_inc_count : forall b v n,
n = count v b -> S n = count v (add v b).
Proof.
intros.
simpl. rewrite eqb_n.
rewrite H. reflexivity.
Qed.
(* Do not modify the following line: *)
Definition manual_grade_for_add_inc_count : option (nat*string) := None.
(** [] *)
(* ################################################################# *)
(** * Reasoning About Lists *)
(** As with numbers, simple facts about list-processing
functions can sometimes be proved entirely by simplification. For
example, just the simplification performed by [reflexivity] is
enough for this theorem... *)
Theorem nil_app : forall l : natlist,
[] ++ l = l.
Proof. reflexivity. Qed.
(** ...because the [[]] is substituted into the
"scrutinee" (the expression whose value is being "scrutinized" by
the match) in the definition of [app], allowing the match itself
to be simplified. *)
(** Also, as with numbers, it is sometimes helpful to perform case
analysis on the possible shapes (empty or non-empty) of an unknown
list. *)
Theorem tl_length_pred : forall l:natlist,
pred (length l) = length (tl l).
Proof.
intros l. destruct l as [| n l'].
- (* l = nil *)
reflexivity.
- (* l = cons n l' *)
reflexivity. Qed.
(** Here, the [nil] case works because we've chosen to define
[tl nil = nil]. Notice that the [as] annotation on the [destruct]
tactic here introduces two names, [n] and [l'], corresponding to
the fact that the [cons] constructor for lists takes two
arguments (the head and tail of the list it is constructing). *)
(** Usually, though, interesting theorems about lists require
induction for their proofs. We'll see how to do this next. *)
(** (Micro-Sermon: As we get deeper into this material, simply
_reading_ proof scripts will not get you very far! It is
important to step through the details of each one using Coq and
think about what each step achieves. Otherwise it is more or less
guaranteed that the exercises will make no sense when you get to
them. 'Nuff said.) *)
(* ================================================================= *)
(** ** Induction on Lists *)
(** Proofs by induction over datatypes like [natlist] are a
little less familiar than standard natural number induction, but
the idea is equally simple. Each [Inductive] declaration defines
a set of data values that can be built up using the declared
constructors. For example, a boolean can be either [true] or
[false]; a number can be either [O] or [S] applied to another
number; and a list can be either [nil] or [cons] applied to a
number and a list. Moreover, applications of the declared
constructors to one another are the _only_ possible shapes
that elements of an inductively defined set can have.
This last fact directly gives rise to a way of reasoning about
inductively defined sets: a number is either [O] or else it is [S]
applied to some _smaller_ number; a list is either [nil] or else
it is [cons] applied to some number and some _smaller_ list;
etc. So, if we have in mind some proposition [P] that mentions a
list [l] and we want to argue that [P] holds for _all_ lists, we
can reason as follows:
- First, show that [P] is true of [l] when [l] is [nil].
- Then show that [P] is true of [l] when [l] is [cons n l'] for
some number [n] and some smaller list [l'], assuming that [P]
is true for [l'].
Since larger lists can always be broken down into smaller ones,
eventually reaching [nil], these two arguments together establish
the truth of [P] for all lists [l]. Here's a concrete example: *)
Theorem app_assoc : forall l1 l2 l3 : natlist,
(l1 ++ l2) ++ l3 = l1 ++ (l2 ++ l3).
Proof.
intros l1 l2 l3. induction l1 as [| n l1' IHl1'].
- (* l1 = nil *)
reflexivity.
- (* l1 = cons n l1' *)
simpl. rewrite -> IHl1'. reflexivity. Qed.
(** Notice that, as when doing induction on natural numbers, the
[as...] clause provided to the [induction] tactic gives a name to
the induction hypothesis corresponding to the smaller list [l1']
in the [cons] case.
Once again, this Coq proof is not especially illuminating as a
static document -- it is easy to see what's going on if you are
reading the proof in an interactive Coq session and you can see
the current goal and context at each point, but this state is not
visible in the written-down parts of the Coq proof. So a
natural-language proof -- one written for human readers -- will
need to include more explicit signposts; in particular, it will
help the reader stay oriented if we remind them exactly what the
induction hypothesis is in the second case. *)
(** For comparison, here is an informal proof of the same theorem. *)
(** _Theorem_: For all lists [l1], [l2], and [l3],
[(l1 ++ l2) ++ l3 = l1 ++ (l2 ++ l3)].
_Proof_: By induction on [l1].
- First, suppose [l1 = []]. We must show
([] ++ l2) ++ l3 = [] ++ (l2 ++ l3),
which follows directly from the definition of [++].
- Next, suppose [l1 = n::l1'], with
(l1' ++ l2) ++ l3 = l1' ++ (l2 ++ l3)
(the induction hypothesis). We must show
((n :: l1') ++ l2) ++ l3 = (n :: l1') ++ (l2 ++ l3).
By the definition of [++], this follows from
n :: ((l1' ++ l2) ++ l3) = n :: (l1' ++ (l2 ++ l3)),
which is immediate from the induction hypothesis. [] *)
(* ----------------------------------------------------------------- *)
(** *** Reversing a List *)
(** For a slightly more involved example of inductive proof over
lists, suppose we use [app] to define a list-reversing
function [rev]: *)
Fixpoint rev (l:natlist) : natlist :=
match l with
| nil => nil
| h :: t => rev t ++ [h]
end.
Example test_rev1: rev [1;2;3] = [3;2;1].
Proof. reflexivity. Qed.
Example test_rev2: rev nil = nil.
Proof. reflexivity. Qed.
(** For something a bit more challenging than the proofs
we've seen so far, let's prove that reversing a list does not
change its length. Our first attempt gets stuck in the successor
case... *)
Theorem rev_length_firsttry : forall l : natlist,
length (rev l) = length l.
Proof.
intros l. induction l as [| n l' IHl'].
- (* l = nil *)
reflexivity.
- (* l = n :: l' *)
(* This is the tricky case. Let's begin as usual
by simplifying. *)
simpl.
(* Now we seem to be stuck: the goal is an equality
involving [++], but we don't have any useful equations
in either the immediate context or in the global
environment! We can make a little progress by using
the IH to rewrite the goal... *)
rewrite <- IHl'.
(* ... but now we can't go any further. *)
Abort.
(** So let's take the equation relating [++] and [length] that
would have enabled us to make progress at the point where we got
stuck and state it as a separate lemma. *)
Theorem app_length : forall l1 l2 : natlist,
length (l1 ++ l2) = (length l1) + (length l2).
Proof.
(* WORKED IN CLASS *)
intros l1 l2. induction l1 as [| n l1' IHl1'].
- (* l1 = nil *)
reflexivity.
- (* l1 = cons *)
simpl. rewrite -> IHl1'. reflexivity. Qed.
(** Note that, to make the lemma as general as possible, we
quantify over _all_ [natlist]s, not just those that result from an
application of [rev]. This should seem natural, because the truth
of the goal clearly doesn't depend on the list having been
reversed. Moreover, it is easier to prove the more general
property. *)
(** Now we can complete the original proof. *)
Theorem rev_length : forall l : natlist,
length (rev l) = length l.
Proof.
intros l. induction l as [| n l' IHl'].
- (* l = nil *)
reflexivity.
- (* l = cons *)
simpl. rewrite -> app_length.
simpl. rewrite -> IHl'. rewrite plus_comm.
reflexivity.
Qed.
(** For comparison, here are informal proofs of these two theorems:
_Theorem_: For all lists [l1] and [l2],
[length (l1 ++ l2) = length l1 + length l2].
_Proof_: By induction on [l1].
- First, suppose [l1 = []]. We must show
length ([] ++ l2) = length [] + length l2,
which follows directly from the definitions of
[length], [++], and [plus].
- Next, suppose [l1 = n::l1'], with
length (l1' ++ l2) = length l1' + length l2.
We must show
length ((n::l1') ++ l2) = length (n::l1') + length l2.
This follows directly from the definitions of [length] and [++]
together with the induction hypothesis. [] *)
(** _Theorem_: For all lists [l], [length (rev l) = length l].
_Proof_: By induction on [l].
- First, suppose [l = []]. We must show
length (rev []) = length [],
which follows directly from the definitions of [length]
and [rev].
- Next, suppose [l = n::l'], with
length (rev l') = length l'.
We must show
length (rev (n :: l')) = length (n :: l').
By the definition of [rev], this follows from
length ((rev l') ++ [n]) = S (length l')
which, by the previous lemma, is the same as
length (rev l') + length [n] = S (length l').
This follows directly from the induction hypothesis and the
definition of [length]. [] *)
(** The style of these proofs is rather longwinded and pedantic.
After reading a couple like this, we might find it easier to
follow proofs that give fewer details (which we can easily work
out in our own minds or on scratch paper if necessary) and just
highlight the non-obvious steps. In this more compressed style,
the above proof might look like this: *)
(** _Theorem_: For all lists [l], [length (rev l) = length l].
_Proof_: First, observe that [length (l ++ [n]) = S (length l)]
for any [l], by a straightforward induction on [l]. The main
property again follows by induction on [l], using the observation
together with the induction hypothesis in the case where [l =
n'::l']. [] *)
(** Which style is preferable in a given situation depends on
the sophistication of the expected audience and how similar the
proof at hand is to ones that they will already be familiar with.
The more pedantic style is a good default for our present
purposes. *)
(* ================================================================= *)
(** ** [Search] *)
(** We've seen that proofs can make use of other theorems we've
already proved, e.g., using [rewrite]. But in order to refer to a
theorem, we need to know its name! Indeed, it is often hard even
to remember what theorems have been proven, much less what they
are called.
Coq's [Search] command is quite helpful with this. Let's say
you've forgotten the name of a theorem about [rev]. The command
[Search rev] will cause Coq to display a list of all theorems
involving [rev]. *)
Search rev.
(** Or say you've forgotten the name of the theorem showing that plus
is commutative. You can use a pattern to search for all theorems
involving the equality of two additions. *)
Search (_ + _ = _ + _).
(** You'll see a lot of results there, nearly all of them from the
standard library. To restrict the results, you can search inside
a particular module: *)
Search (_ + _ = _ + _) inside Induction.
(** You can also make the search more precise by using variables in
the search pattern instead of wildcards: *)
Search (?x + ?y = ?y + ?x).
(** The question mark in front of the variable is needed to indicate
that it is a variable in the search pattern, rather than a
variable that is expected to be in scope currently. *)
(** Keep [Search] in mind as you do the following exercises and
throughout the rest of the book; it can save you a lot of time!
Your IDE likely has its own functionality to help with searching.
For example, in ProofGeneral, you can run [Search] with [C-c C-a
C-a], and paste its response into your buffer with [C-c C-;]. *)
(* ================================================================= *)
(** ** List Exercises, Part 1 *)
(** **** Exercise: 3 stars, standard (list_exercises)
More practice with lists: *)
Theorem app_nil_r : forall l : natlist,
l ++ [] = l.
Proof.
intros.
induction l.
- reflexivity.
- simpl. rewrite IHl. reflexivity.
Qed.
Theorem rev_app_distr: forall l1 l2 : natlist,
rev (l1 ++ l2) = rev l2 ++ rev l1.
Proof.
intros.
induction l1.
- simpl. rewrite app_nil_r. reflexivity.
- simpl. rewrite IHl1. rewrite app_assoc. reflexivity.
Qed.
Theorem rev_involutive : forall l : natlist,
rev (rev l) = l.
Proof.
intros.
induction l.
- reflexivity.
- simpl. rewrite rev_app_distr. simpl. rewrite IHl. reflexivity.
Qed.
(** There is a short solution to the next one. If you find yourself
getting tangled up, step back and try to look for a simpler
way. *)
Theorem app_assoc4 : forall l1 l2 l3 l4 : natlist,
l1 ++ (l2 ++ (l3 ++ l4)) = ((l1 ++ l2) ++ l3) ++ l4.
Proof.
intros.
induction l1.
- simpl. rewrite app_assoc. reflexivity.
- simpl. rewrite IHl1. reflexivity.
Qed.
(** An exercise about your implementation of [nonzeros]: *)
Lemma nonzeros_app : forall l1 l2 : natlist,
nonzeros (l1 ++ l2) = (nonzeros l1) ++ (nonzeros l2).
Proof.
intros.
induction l1.
- simpl. reflexivity.
- simpl. induction n.
+ rewrite IHl1. reflexivity.
+ simpl. rewrite IHl1. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard (eqblist)
Fill in the definition of [eqblist], which compares
lists of numbers for equality. Prove that [eqblist l l]
yields [true] for every list [l]. *)
Fixpoint eqblist (l1 l2 : natlist) : bool :=
match l1, l2 with
| [], [] => true
| (x::xs), (y::ys) => match eqb x y with
| true => eqblist xs ys
| false => false
end
| _, _ => false
end.
Example test_eqblist1 :
(eqblist nil nil = true).
Proof. reflexivity. Qed.
Example test_eqblist2 :
eqblist [1;2;3] [1;2;3] = true.
Proof. reflexivity. Qed.
Example test_eqblist3 :
eqblist [1;2;3] [1;2;4] = false.
Proof. reflexivity. Qed.
Theorem eqblist_refl : forall l:natlist,
true = eqblist l l.
Proof.
intros.
induction l.
- reflexivity.
- simpl. rewrite eqb_n. rewrite <- IHl. reflexivity.
Qed.
(** [] *)
(* ================================================================= *)
(** ** List Exercises, Part 2 *)
(** Here are a couple of little theorems to prove about your
definitions about bags above. *)
(** **** Exercise: 1 star, standard (count_member_nonzero) *)
Theorem count_member_nonzero : forall (s : bag),
1 <=? (count 1 (1 :: s)) = true.
Proof. intros. simpl. reflexivity. Qed.
(** [] *)
(** The following lemma about [leb] might help you in the next exercise. *)
Theorem leb_n_Sn : forall n,
n <=? (S n) = true.
Proof.
intros n. induction n as [| n' IHn'].
- (* 0 *)
simpl. reflexivity.
- (* S n' *)
simpl. rewrite IHn'. reflexivity. Qed.
(** Before doing the next exercise, make sure you've filled in the
definition of [remove_one] above. *)
(** **** Exercise: 3 stars, advanced (remove_does_not_increase_count) *)
Theorem remove_does_not_increase_count: forall (s : bag),
(count 0 (remove_one 0 s)) <=? (count 0 s) = true.
Proof.
intros.
induction s.
- reflexivity.
- induction n.
+ simpl. rewrite leb_n_Sn. reflexivity.
+ simpl. rewrite IHs. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (bag_count_sum)
Write down an interesting theorem [bag_count_sum] about bags
involving the functions [count] and [sum], and prove it using
Coq. (You may find that the difficulty of the proof depends on
how you defined [count]!) *)
Theorem bag_count_sum: forall n b1 b2,
count n b1 + count n b2 = count n (sum b1 b2).
Proof.
intros.
induction b1.
- simpl. reflexivity.
- simpl. destruct (n0 =? n).
+ simpl. rewrite IHb1. reflexivity.
+ rewrite IHb1. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (rev_injective)
Prove that the [rev] function is injective. There is a hard way
and an easy way to do this. *)
Theorem rev_injective : forall (l1 l2 : natlist),
rev l1 = rev l2 -> l1 = l2.
Proof.
intros.
assert (Hx: rev (rev l1) = rev (rev l2)).
rewrite H. reflexivity.
rewrite rev_involutive in Hx; rewrite rev_involutive in Hx.
rewrite Hx.
reflexivity.
Qed.
(** [] *)
(* ################################################################# *)
(** * Options *)
(** Suppose we want to write a function that returns the [n]th
element of some list. If we give it type [nat -> natlist -> nat],
then we'll have to choose some number to return when the list is
too short... *)
Fixpoint nth_bad (l:natlist) (n:nat) : nat :=
match l with
| nil => 42
| a :: l' => match n with
| 0 => a
| S n' => nth_bad l' n'
end
end.
(** This solution is not so good: If [nth_bad] returns [42], we
can't tell whether that value actually appears on the input
without further processing. A better alternative is to change the
return type of [nth_bad] to include an error value as a possible
outcome. We call this type [natoption]. *)
Inductive natoption : Type :=
| Some (n : nat)
| None.
(** We can then change the above definition of [nth_bad] to
return [None] when the list is too short and [Some a] when the
list has enough members and [a] appears at position [n]. We call
this new function [nth_error] to indicate that it may result in an
error. As we see here, constructors of inductive definitions can
be capitalized. *)
Fixpoint nth_error (l:natlist) (n:nat) : natoption :=
match l with
| nil => None
| a :: l' => match n with
| O => Some a
| S n' => nth_error l' n'
end
end.
Example test_nth_error1 : nth_error [4;5;6;7] 0 = Some 4.
Proof. reflexivity. Qed.
Example test_nth_error2 : nth_error [4;5;6;7] 3 = Some 7.
Proof. reflexivity. Qed.
Example test_nth_error3 : nth_error [4;5;6;7] 9 = None.
Proof. reflexivity. Qed.
(** (In the HTML version, the boilerplate proofs of these
examples are elided. Click on a box if you want to see one.)
This example is also an opportunity to introduce one more small
feature of Coq's programming language: conditional
expressions... *)
Fixpoint nth_error' (l:natlist) (n:nat) : natoption :=
match l with
| nil => None
| a :: l' => if n =? O then Some a
else nth_error' l' (pred n)
end.
(** Coq's conditionals are exactly like those found in any other
language, with one small generalization. Since the [bool] type
is not built in, Coq actually supports conditional expressions over
_any_ inductively defined type with exactly two constructors. The
guard is considered true if it evaluates to the first constructor
in the [Inductive] definition and false if it evaluates to the
second. *)
(** The function below pulls the [nat] out of a [natoption], returning
a supplied default in the [None] case. *)
Definition option_elim (d : nat) (o : natoption) : nat :=
match o with
| Some n' => n'
| None => d
end.
(** **** Exercise: 2 stars, standard (hd_error)
Using the same idea, fix the [hd] function from earlier so we don't
have to pass a default element for the [nil] case. *)
Definition hd_error (l : natlist) : natoption :=
match l with
| [] => None
| x::_ => Some x
end.
Example test_hd_error1 : hd_error [] = None.
Proof. reflexivity. Qed.
Example test_hd_error2 : hd_error [1] = Some 1.
Proof. reflexivity. Qed.
Example test_hd_error3 : hd_error [5;6] = Some 5.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star, standard, optional (option_elim_hd)
This exercise relates your new [hd_error] to the old [hd]. *)
Theorem option_elim_hd : forall (l:natlist) (default:nat),
hd default l = option_elim default (hd_error l).
Proof.
intros.
destruct l; reflexivity.
Qed.
(** [] *)
End NatList.
(* ################################################################# *)
(** * Partial Maps *)
(** As a final illustration of how data structures can be defined in
Coq, here is a simple _partial map_ data type, analogous to the
map or dictionary data structures found in most programming
languages. *)
(** First, we define a new inductive datatype [id] to serve as the
"keys" of our partial maps. *)
Inductive id : Type :=
| Id (n : nat).
(** Internally, an [id] is just a number. Introducing a separate type
by wrapping each nat with the tag [Id] makes definitions more
readable and gives us more flexibility. *)
(** We'll also need an equality test for [id]s: *)
Definition eqb_id (x1 x2 : id) :=
match x1, x2 with
| Id n1, Id n2 => n1 =? n2
end.
(** **** Exercise: 1 star, standard (eqb_id_refl) *)
Theorem eqb_id_refl : forall x, true = eqb_id x x.
Proof.
intros. destruct x. induction n.
- reflexivity.
- simpl. rewrite <- eqb_refl. reflexivity.
Qed.
(** [] *)
(** Now we define the type of partial maps: *)
Module PartialMap.
Export NatList.
Inductive partial_map : Type :=
| empty
| record (i : id) (v : nat) (m : partial_map).
(** This declaration can be read: "There are two ways to construct a
[partial_map]: either using the constructor [empty] to represent an
empty partial map, or applying the constructor [record] to
a key, a value, and an existing [partial_map] to construct a
[partial_map] with an additional key-to-value mapping." *)
(** The [update] function overrides the entry for a given key in a
partial map by shadowing it with a new one (or simply adds a new
entry if the given key is not already present). *)
Definition update (d : partial_map)
(x : id) (value : nat)
: partial_map :=
record x value d.
(** Last, the [find] function searches a [partial_map] for a given
key. It returns [None] if the key was not found and [Some val] if
the key was associated with [val]. If the same key is mapped to
multiple values, [find] will return the first one it
encounters. *)
Fixpoint find (x : id) (d : partial_map) : natoption :=
match d with
| empty => None
| record y v d' => if eqb_id x y
then Some v
else find x d'
end.
(** **** Exercise: 1 star, standard (update_eq) *)
Theorem update_eq :
forall (d : partial_map) (x : id) (v: nat),
find x (update d x v) = Some v.
Proof.
intros. simpl. rewrite <- eqb_id_refl. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star, standard (update_neq) *)
Theorem update_neq :
forall (d : partial_map) (x y : id) (o: nat),
eqb_id x y = false -> find x (update d y o) = find x d.
Proof.
intros.
simpl.
rewrite H. reflexivity.
Qed.
(** [] *)
End PartialMap.
(** **** Exercise: 2 stars, standard, optional (baz_num_elts)
Consider the following inductive definition: *)
Inductive baz : Type :=
| Baz1 (x : baz)
| Baz2 (y : baz) (b : bool).
(** How _many_ elements does the type [baz] have? (Explain in words,
in a comment.) *)
(* There is no base constructor, so there is no
possible, "finite" element. However, there can be elements that are infinite.
The "baz" type can be thought of a infinite list of either:
- a bottom value
- either true or false
Overall, there are 3*infinity = infinity of possible elements.
*)
(* Do not modify the following line: *)
Definition manual_grade_for_baz_num_elts : option (nat*string) := None.
(** [] *)
(* 2020-09-09 20:51 *)
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: Dave McCoy ([email protected])
* Description:
* Translates data from an AXI stream interface to a Ping Pong FIFO
*
*
* Changes Who? What?
* 12/26/2015: DFM Initial Checkin
* 04/06/2017: DFM Modified documentation, there is no need for the
* data of either the PPFIFO or AXI Stream to be the same
* size
*/
module adapter_axi_stream_2_block_fifo #(
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = DATA_WIDTH / 8,
parameter USE_KEEP = 0
)(
input rst,
//AXI Stream Input
input i_axi_clk,
output o_axi_ready,
input [DATA_WIDTH - 1:0] i_axi_data,
input [STROBE_WIDTH - 1:0] i_axi_keep,
input i_axi_last,
input i_axi_valid,
//Ping Pong FIFO Write Controller
output o_block_fifo_clk,
input i_block_fifo_rdy,
output reg o_block_fifo_act,
input [23:0] i_block_fifo_size,
output reg o_block_fifo_stb,
output reg [DATA_WIDTH - 1:0] o_block_fifo_data
);
//local parameters
localparam IDLE = 0;
localparam READY = 1;
localparam RELEASE = 2;
//registes/wires
wire clk; //Convenience Signal
reg [3:0] state;
reg [23:0] r_count;
//submodules
//asynchronous logic
//This is a little strange to just connect the output clock with the input clock but if this is done
//Users do not need to figure out how to hook up the clocks
assign o_block_fifo_clk = i_axi_clk;
assign clk = i_axi_clk;
assign o_axi_ready = o_block_fifo_act && (r_count < i_block_fifo_size);
//synchronous logic
always @ (posedge clk) begin
o_block_fifo_stb <= 0;
if (rst) begin
r_count <= 0;
o_block_fifo_act <= 0;
o_block_fifo_data <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
o_block_fifo_act <= 0;
if (i_block_fifo_rdy && !o_block_fifo_act) begin
r_count <= 0;
o_block_fifo_act <= 1;
state <= READY;
end
end
READY: begin
if (r_count < i_block_fifo_size) begin
if (i_axi_valid) begin
o_block_fifo_stb <= 1;
o_block_fifo_data <= i_axi_data;
r_count <= r_count + 1;
end
end
//Conditions to release the FIFO or stop a transaction
else begin
state <= RELEASE;
end
if (i_axi_last) begin
state <= RELEASE;
end
end
RELEASE: begin
o_block_fifo_act <= 0;
state <= IDLE;
end
default: begin
end
endcase
end
end
endmodule
|
/* Module from the schematic_gui program written by Andreas Ehliar <[email protected]>
This Verilog file is licensed under the CC0 license. */
module mux4 #(parameter WIREWIDTH = 1) (input wire [1:0] s,
input wire [WIREWIDTH:0] d0, d1, d2,d3,
output reg [WIREWIDTH:0] o);
initial begin
$schematic_boundingbox(40,200);
$schematic_polygonstart;
$schematic_coord(10,10);
$schematic_coord(30,30);
$schematic_coord(30,170);
$schematic_coord(10,190);
$schematic_polygonend;
$schematic_linestart;
$schematic_coord(20,19);
$schematic_coord(20,10);
$schematic_lineend;
$schematic_connector(d0,0,40);
$schematic_connector(d1,0,80);
$schematic_connector(d2,0,120);
$schematic_connector(d3,0,160);
$schematic_connector(o,40,100);
$schematic_connector(s,20,0);
$schematic_symboltext("0", 20,40);
$schematic_symboltext("1", 20,80);
$schematic_symboltext("2", 20,120);
$schematic_symboltext("3", 20,160);
end
always @* begin
case(s)
0: o = d0;
1: o = d1;
2: o = d2;
3: o = d3;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O211AI_BEHAVIORAL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o211ai (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1N_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__INPUTISO1N_PP_BLACKBOX_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso1n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1N_PP_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_dds (
// interface
clk,
dds_format,
dds_phase_0,
dds_scale_0,
dds_phase_1,
dds_scale_1,
dds_data);
// interface
input clk;
input dds_format;
input [15:0] dds_phase_0;
input [15:0] dds_scale_0;
input [15:0] dds_phase_1;
input [15:0] dds_scale_1;
output [15:0] dds_data;
// internal registers
reg [15:0] dds_data_int = 'd0;
reg [15:0] dds_data = 'd0;
reg [15:0] dds_scale_0_r = 'd0;
reg [15:0] dds_scale_1_r = 'd0;
// internal signals
wire [15:0] dds_data_0_s;
wire [15:0] dds_data_1_s;
// dds channel output
always @(posedge clk) begin
dds_data_int <= dds_data_0_s + dds_data_1_s;
dds_data[15:15] <= dds_data_int[15] ^ dds_format;
dds_data[14: 0] <= dds_data_int[14:0];
end
always @(posedge clk) begin
dds_scale_0_r <= dds_scale_0;
dds_scale_1_r <= dds_scale_1;
end
// dds-1
ad_dds_1 i_dds_1_0 (
.clk (clk),
.angle (dds_phase_0),
.scale (dds_scale_0_r),
.dds_data (dds_data_0_s));
// dds-2
ad_dds_1 i_dds_1_1 (
.clk (clk),
.angle (dds_phase_1),
.scale (dds_scale_1_r),
.dds_data (dds_data_1_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file Data_Mem.v when simulating
// the core, Data_Mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module Data_Mem(
a,
d,
clk,
we,
spo);
input [5 : 0] a;
input [31 : 0] d;
input clk;
input we;
output [31 : 0] spo;
// synthesis translate_off
DIST_MEM_GEN_V5_1 #(
.C_ADDR_WIDTH(6),
.C_DEFAULT_DATA("0"),
.C_DEPTH(64),
.C_FAMILY("spartan3"),
.C_HAS_CLK(1),
.C_HAS_D(1),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_SPRA(0),
.C_HAS_WE(1),
.C_MEM_INIT_FILE("Data_Mem.mif"),
.C_MEM_TYPE(1),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(32))
inst (
.A(a),
.D(d),
.CLK(clk),
.WE(we),
.SPO(spo),
.DPRA(),
.SPRA(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.DPO(),
.QSPO(),
.QDPO());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of Data_Mem is "black_box"
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A221O_BEHAVIORAL_PP_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221O_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSBP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SDFSBP_BLACKBOX_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSBP_BLACKBOX_V
|
`timescale 1ns / 1ps
module tx_sm_tb ();
`include "dut.v"
integer i;
initial
begin
//$dumpfile("test.vcd");
//$dumpvars(0,tx_sm_tb,U_tx_sm);
end
initial
begin
#15 reset = 0;
// Will initially wait IFG before making any transmissions
// Set fifo_count to 1 and check IFG delay before tx_enable is asserted
// Clock flips every 5ns -> 10ns period
// tx_enable_monitor will take care of these checks
fifo_count = 1;
#110
expected_tx_enable = 1;
// MAC should then start transmitting the preamble
// 7 bytes
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
// Followed by the SFD
// 1 byte
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
// Followed by the frame data we supply
// 10 Bytes
fork
// Data Start
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
// Data End
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
// Followed by padding
// 50 bytes
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
// Followed by CRC
// 4 bytes
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
// Wait IFG and send the same packet again
#120
// Assert Carrier Sense - Should have no effect in Full Duplex
carrier_sense = 1;
expected_tx_enable = 1;
// MAC should start transmitting the preamble
// 7 bytes
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
// Followed by the SFD
// 1 byte
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
// Followed by the frame data we supply
// 10 Bytes
fork
// Data Start
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
// Data End
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
// Followed by padding
// 50 bytes
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
// Followed by CRC
// 4 bytes
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
// Wait IFG and send the same packet again
#120
expected_tx_enable = 1;
// MAC should start transmitting the preamble
// 7 bytes
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
// Followed by the SFD
// 1 byte
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
// Assert a collision - Should have no effect in Full Duplex
collision = 1;
// Followed by the frame data we supply
// 10 Bytes
fork
// Data Start
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
// Data End
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
// Followed by padding
// 50 bytes
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
// Followed by CRC
// 4 bytes
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
$finish;
end
endmodule
|
`timescale 1ns / 1ps
module LowPassFilter(clk, new_sample, input_sample, output_sample);
input clk;
input new_sample;
reg enable_systolic;
wire clk_systolic;
input [15:0] input_sample;
output [15:0] output_sample;
reg [2:0] state;
localparam IDLE = 3'd0,
CLK_A = 3'd1,
CLK_B = 3'd2,
CLK_C = 3'd3,
CLK_D = 3'd4;
initial begin
state <= IDLE;
enable_systolic <= 1'b0;
end
always @ (posedge clk) begin
case(state)
IDLE: begin
if(new_sample)
state <= CLK_A;
else
state <= IDLE;
end
CLK_A: begin
enable_systolic <= 1'b1;
state <= CLK_B;
end
CLK_B: begin
enable_systolic <= 1'b1;
state <= CLK_C;
end
CLK_C: begin
enable_systolic <= 1'b0;
state <= IDLE;
end
endcase
end
localparam NUM_COEFFS = 99; // 57
localparam BITS_COEFF = 8;
localparam NUM_COEFFS_BITS = NUM_COEFFS * BITS_COEFF;
/*
// Simulator coefficients
localparam [NUM_COEFFS_BITS-1:0] COEFFS = {
8'sd1,
8'sd1,
8'sd1,
-8'sd1
};
*/
/*
// Low pass coefficients
localparam [NUM_COEFFS_BITS-1:0] COEFFS = {
6'd0,
6'd0,
6'd0,
6'd1,
6'd1,
6'd2,
6'd3,
6'd5,
6'd7,
6'd10,
6'd12,
6'd15,
6'd19,
6'd22,
6'd25,
6'd28,
6'd31,
6'd33,
6'd34,
6'd34,
6'd34,
6'd33,
6'd31,
6'd28,
6'd25,
6'd22,
6'd19,
6'd15,
6'd12,
6'd10,
6'd7,
6'd5,
6'd3,
6'd2,
6'd1,
6'd1,
6'd0,
6'd0,
6'd0
};
*/
// low pass 99 coeff, 100 Hz stop freq, 60 dB attenuate, 48 khz sampling freq, multiplier: 4926
localparam [NUM_COEFFS_BITS-1:0] COEFFS = {
8'sd0,
8'sd1,
8'sd1,
8'sd1,
8'sd1,
8'sd1,
8'sd2,
8'sd2,
8'sd2,
8'sd2,
8'sd3,
8'sd3,
8'sd4,
8'sd4,
8'sd4,
8'sd5,
8'sd5,
8'sd6,
8'sd6,
8'sd7,
8'sd8,
8'sd8,
8'sd9,
8'sd9,
8'sd10,
8'sd11,
8'sd11,
8'sd12,
8'sd12,
8'sd13,
8'sd14,
8'sd14,
8'sd15,
8'sd15,
8'sd16,
8'sd16,
8'sd17,
8'sd17,
8'sd18,
8'sd18,
8'sd19,
8'sd19,
8'sd19,
8'sd20,
8'sd20,
8'sd20,
8'sd20,
8'sd20,
8'sd21,
8'sd21,
8'sd21,
8'sd20,
8'sd20,
8'sd20,
8'sd20,
8'sd20,
8'sd19,
8'sd19,
8'sd19,
8'sd18,
8'sd18,
8'sd17,
8'sd17,
8'sd16,
8'sd16,
8'sd15,
8'sd15,
8'sd14,
8'sd14,
8'sd13,
8'sd12,
8'sd12,
8'sd11,
8'sd11,
8'sd10,
8'sd9,
8'sd9,
8'sd8,
8'sd8,
8'sd7,
8'sd6,
8'sd6,
8'sd5,
8'sd5,
8'sd4,
8'sd4,
8'sd4,
8'sd3,
8'sd3,
8'sd2,
8'sd2,
8'sd2,
8'sd2,
8'sd1,
8'sd1,
8'sd1,
8'sd1,
8'sd1,
8'sd0
};
wire [31:0] a_out [0:NUM_COEFFS];
wire [31:0] b_out [0:NUM_COEFFS];
genvar j;
generate
for(j = 0; j < NUM_COEFFS; j = j+1) begin: GEN
processingUnit #(COEFFS[NUM_COEFFS_BITS-1-(j*BITS_COEFF):NUM_COEFFS_BITS-(j*BITS_COEFF)-BITS_COEFF]) gen_proc(
.clk(clk),
.a_in(a_out[j]),
.a_out(a_out[j+1]),
.b_out(b_out[j]),
.b_in(b_out[j+1]),
.enable(enable_systolic)
);
end
endgenerate
assign a_out[0] = {{16{input_sample[15]}}, input_sample}; // sign extend to 32 bits
assign b_out[NUM_COEFFS] = 32'h0;
assign output_sample = b_out[0][26:10]; // divide by 1024
endmodule
/*
processingUnit #(1) p00 (clk, systolic_input, a_out[0], systolic_output, b_out[17], enable_systolic);
processingUnit #(3) p01 (clk, a_out[0], a_out[1], b_out[17], b_out[16], enable_systolic);
processingUnit #(5) p02 (clk, a_out[1], a_out[2], b_out[16], b_out[15], enable_systolic);
processingUnit #(7) p03 (clk, a_out[2], a_out[3], b_out[15], b_out[14], enable_systolic);
processingUnit #(11)p04 (clk, a_out[3], a_out[4], b_out[14], b_out[13], enable_systolic);
processingUnit #(13)p05 (clk, a_out[4], a_out[5], b_out[13], b_out[12], enable_systolic);
processingUnit #(16)p06 (clk, a_out[5], a_out[6], b_out[12], b_out[11], enable_systolic);
processingUnit #(19)p07 (clk, a_out[6], a_out[7], b_out[11], b_out[10], enable_systolic);
processingUnit #(20)p08 (clk, a_out[7], a_out[8], b_out[10], b_out[9], enable_systolic);
processingUnit #(21)p09 (clk, a_out[8], a_out[9], b_out[9], b_out[8], enable_systolic);
processingUnit #(20)p10 (clk, a_out[9], a_out[10], b_out[8], b_out[7], enable_systolic);
processingUnit #(19)p11 (clk, a_out[10], a_out[11], b_out[7], b_out[6], enable_systolic);
processingUnit #(16)p12 (clk, a_out[11], a_out[12], b_out[6], b_out[5], enable_systolic);
processingUnit #(13)p13 (clk, a_out[12], a_out[13], b_out[5], b_out[4], enable_systolic);
processingUnit #(11)p14 (clk, a_out[13], a_out[14], b_out[4], b_out[3], enable_systolic);
processingUnit #(7) p15 (clk, a_out[14], a_out[15], b_out[3], b_out[2], enable_systolic);
processingUnit #(5) p16 (clk, a_out[15], a_out[16], b_out[2], b_out[1], enable_systolic);
processingUnit #(3) p17 (clk, a_out[16], a_out[17], b_out[1], b_out[0], enable_systolic);
processingUnit #(1) p18 (clk, a_out[17], , b_out[0], 32'h0, enable_systolic);*/
|
//--------------------------------------------------------------------------------
// Auto-generated by Migen (41922fd) & LiteX (b6d35c92) on 2019-11-22 10:43:17
//--------------------------------------------------------------------------------
module top(
output reg serial_tx,
input serial_rx,
input cpu_reset,
input clk100
);
wire ctrl_reset_reset_re;
wire ctrl_reset_reset_r;
wire ctrl_reset_reset_we;
reg ctrl_reset_reset_w = 1'd0;
reg [31:0] ctrl_storage = 32'd305419896;
reg ctrl_re = 1'd0;
wire [31:0] ctrl_bus_errors_status;
wire ctrl_bus_errors_we;
wire ctrl_reset;
wire ctrl_bus_error;
reg [31:0] ctrl_bus_errors = 32'd0;
wire vexriscv_reset;
wire [29:0] vexriscv_ibus_adr;
wire [31:0] vexriscv_ibus_dat_w;
wire [31:0] vexriscv_ibus_dat_r;
wire [3:0] vexriscv_ibus_sel;
wire vexriscv_ibus_cyc;
wire vexriscv_ibus_stb;
wire vexriscv_ibus_ack;
wire vexriscv_ibus_we;
wire [2:0] vexriscv_ibus_cti;
wire [1:0] vexriscv_ibus_bte;
wire vexriscv_ibus_err;
wire [29:0] vexriscv_dbus_adr;
wire [31:0] vexriscv_dbus_dat_w;
wire [31:0] vexriscv_dbus_dat_r;
wire [3:0] vexriscv_dbus_sel;
wire vexriscv_dbus_cyc;
wire vexriscv_dbus_stb;
wire vexriscv_dbus_ack;
wire vexriscv_dbus_we;
wire [2:0] vexriscv_dbus_cti;
wire [1:0] vexriscv_dbus_bte;
wire vexriscv_dbus_err;
reg [31:0] vexriscv_interrupt = 32'd0;
wire [29:0] interface0_soc_bus_adr;
wire [31:0] interface0_soc_bus_dat_w;
wire [31:0] interface0_soc_bus_dat_r;
wire [3:0] interface0_soc_bus_sel;
wire interface0_soc_bus_cyc;
wire interface0_soc_bus_stb;
wire interface0_soc_bus_ack;
wire interface0_soc_bus_we;
wire [2:0] interface0_soc_bus_cti;
wire [1:0] interface0_soc_bus_bte;
wire interface0_soc_bus_err;
wire [29:0] interface1_soc_bus_adr;
wire [31:0] interface1_soc_bus_dat_w;
wire [31:0] interface1_soc_bus_dat_r;
wire [3:0] interface1_soc_bus_sel;
wire interface1_soc_bus_cyc;
wire interface1_soc_bus_stb;
wire interface1_soc_bus_ack;
wire interface1_soc_bus_we;
wire [2:0] interface1_soc_bus_cti;
wire [1:0] interface1_soc_bus_bte;
wire interface1_soc_bus_err;
wire [29:0] rom_bus_adr;
wire [31:0] rom_bus_dat_w;
wire [31:0] rom_bus_dat_r;
wire [3:0] rom_bus_sel;
wire rom_bus_cyc;
wire rom_bus_stb;
reg rom_bus_ack = 1'd0;
wire rom_bus_we;
wire [2:0] rom_bus_cti;
wire [1:0] rom_bus_bte;
reg rom_bus_err = 1'd0;
wire [12:0] rom_adr;
wire [31:0] rom_dat_r;
wire [29:0] sram_bus_adr;
wire [31:0] sram_bus_dat_w;
wire [31:0] sram_bus_dat_r;
wire [3:0] sram_bus_sel;
wire sram_bus_cyc;
wire sram_bus_stb;
reg sram_bus_ack = 1'd0;
wire sram_bus_we;
wire [2:0] sram_bus_cti;
wire [1:0] sram_bus_bte;
reg sram_bus_err = 1'd0;
wire [12:0] sram_adr;
wire [31:0] sram_dat_r;
reg [3:0] sram_we = 4'd0;
wire [31:0] sram_dat_w;
reg [31:0] uart_phy_storage = 32'd4947802;
reg uart_phy_re = 1'd0;
wire uart_phy_sink_valid;
reg uart_phy_sink_ready = 1'd0;
wire uart_phy_sink_first;
wire uart_phy_sink_last;
wire [7:0] uart_phy_sink_payload_data;
reg uart_phy_uart_clk_txen = 1'd0;
reg [31:0] uart_phy_phase_accumulator_tx = 32'd0;
reg [7:0] uart_phy_tx_reg = 8'd0;
reg [3:0] uart_phy_tx_bitcount = 4'd0;
reg uart_phy_tx_busy = 1'd0;
reg uart_phy_source_valid = 1'd0;
wire uart_phy_source_ready;
reg uart_phy_source_first = 1'd0;
reg uart_phy_source_last = 1'd0;
reg [7:0] uart_phy_source_payload_data = 8'd0;
reg uart_phy_uart_clk_rxen = 1'd0;
reg [31:0] uart_phy_phase_accumulator_rx = 32'd0;
wire uart_phy_rx;
reg uart_phy_rx_r = 1'd0;
reg [7:0] uart_phy_rx_reg = 8'd0;
reg [3:0] uart_phy_rx_bitcount = 4'd0;
reg uart_phy_rx_busy = 1'd0;
wire uart_rxtx_re;
wire [7:0] uart_rxtx_r;
wire uart_rxtx_we;
wire [7:0] uart_rxtx_w;
wire uart_txfull_status;
wire uart_txfull_we;
wire uart_rxempty_status;
wire uart_rxempty_we;
wire uart_irq;
wire uart_tx_status;
reg uart_tx_pending = 1'd0;
wire uart_tx_trigger;
reg uart_tx_clear = 1'd0;
reg uart_tx_old_trigger = 1'd0;
wire uart_rx_status;
reg uart_rx_pending = 1'd0;
wire uart_rx_trigger;
reg uart_rx_clear = 1'd0;
reg uart_rx_old_trigger = 1'd0;
wire uart_eventmanager_status_re;
wire [1:0] uart_eventmanager_status_r;
wire uart_eventmanager_status_we;
reg [1:0] uart_eventmanager_status_w = 2'd0;
wire uart_eventmanager_pending_re;
wire [1:0] uart_eventmanager_pending_r;
wire uart_eventmanager_pending_we;
reg [1:0] uart_eventmanager_pending_w = 2'd0;
reg [1:0] uart_eventmanager_storage = 2'd0;
reg uart_eventmanager_re = 1'd0;
wire uart_tx_fifo_sink_valid;
wire uart_tx_fifo_sink_ready;
reg uart_tx_fifo_sink_first = 1'd0;
reg uart_tx_fifo_sink_last = 1'd0;
wire [7:0] uart_tx_fifo_sink_payload_data;
wire uart_tx_fifo_source_valid;
wire uart_tx_fifo_source_ready;
wire uart_tx_fifo_source_first;
wire uart_tx_fifo_source_last;
wire [7:0] uart_tx_fifo_source_payload_data;
wire uart_tx_fifo_re;
reg uart_tx_fifo_readable = 1'd0;
wire uart_tx_fifo_syncfifo_we;
wire uart_tx_fifo_syncfifo_writable;
wire uart_tx_fifo_syncfifo_re;
wire uart_tx_fifo_syncfifo_readable;
wire [9:0] uart_tx_fifo_syncfifo_din;
wire [9:0] uart_tx_fifo_syncfifo_dout;
reg [4:0] uart_tx_fifo_level0 = 5'd0;
reg uart_tx_fifo_replace = 1'd0;
reg [3:0] uart_tx_fifo_produce = 4'd0;
reg [3:0] uart_tx_fifo_consume = 4'd0;
reg [3:0] uart_tx_fifo_wrport_adr = 4'd0;
wire [9:0] uart_tx_fifo_wrport_dat_r;
wire uart_tx_fifo_wrport_we;
wire [9:0] uart_tx_fifo_wrport_dat_w;
wire uart_tx_fifo_do_read;
wire [3:0] uart_tx_fifo_rdport_adr;
wire [9:0] uart_tx_fifo_rdport_dat_r;
wire uart_tx_fifo_rdport_re;
wire [4:0] uart_tx_fifo_level1;
wire [7:0] uart_tx_fifo_fifo_in_payload_data;
wire uart_tx_fifo_fifo_in_first;
wire uart_tx_fifo_fifo_in_last;
wire [7:0] uart_tx_fifo_fifo_out_payload_data;
wire uart_tx_fifo_fifo_out_first;
wire uart_tx_fifo_fifo_out_last;
wire uart_rx_fifo_sink_valid;
wire uart_rx_fifo_sink_ready;
wire uart_rx_fifo_sink_first;
wire uart_rx_fifo_sink_last;
wire [7:0] uart_rx_fifo_sink_payload_data;
wire uart_rx_fifo_source_valid;
wire uart_rx_fifo_source_ready;
wire uart_rx_fifo_source_first;
wire uart_rx_fifo_source_last;
wire [7:0] uart_rx_fifo_source_payload_data;
wire uart_rx_fifo_re;
reg uart_rx_fifo_readable = 1'd0;
wire uart_rx_fifo_syncfifo_we;
wire uart_rx_fifo_syncfifo_writable;
wire uart_rx_fifo_syncfifo_re;
wire uart_rx_fifo_syncfifo_readable;
wire [9:0] uart_rx_fifo_syncfifo_din;
wire [9:0] uart_rx_fifo_syncfifo_dout;
reg [4:0] uart_rx_fifo_level0 = 5'd0;
reg uart_rx_fifo_replace = 1'd0;
reg [3:0] uart_rx_fifo_produce = 4'd0;
reg [3:0] uart_rx_fifo_consume = 4'd0;
reg [3:0] uart_rx_fifo_wrport_adr = 4'd0;
wire [9:0] uart_rx_fifo_wrport_dat_r;
wire uart_rx_fifo_wrport_we;
wire [9:0] uart_rx_fifo_wrport_dat_w;
wire uart_rx_fifo_do_read;
wire [3:0] uart_rx_fifo_rdport_adr;
wire [9:0] uart_rx_fifo_rdport_dat_r;
wire uart_rx_fifo_rdport_re;
wire [4:0] uart_rx_fifo_level1;
wire [7:0] uart_rx_fifo_fifo_in_payload_data;
wire uart_rx_fifo_fifo_in_first;
wire uart_rx_fifo_fifo_in_last;
wire [7:0] uart_rx_fifo_fifo_out_payload_data;
wire uart_rx_fifo_fifo_out_first;
wire uart_rx_fifo_fifo_out_last;
reg uart_reset = 1'd0;
reg [31:0] timer0_load_storage = 32'd0;
reg timer0_load_re = 1'd0;
reg [31:0] timer0_reload_storage = 32'd0;
reg timer0_reload_re = 1'd0;
reg timer0_en_storage = 1'd0;
reg timer0_en_re = 1'd0;
reg timer0_update_value_storage = 1'd0;
reg timer0_update_value_re = 1'd0;
reg [31:0] timer0_value_status = 32'd0;
wire timer0_value_we;
wire timer0_irq;
wire timer0_zero_status;
reg timer0_zero_pending = 1'd0;
wire timer0_zero_trigger;
reg timer0_zero_clear = 1'd0;
reg timer0_zero_old_trigger = 1'd0;
wire timer0_eventmanager_status_re;
wire timer0_eventmanager_status_r;
wire timer0_eventmanager_status_we;
wire timer0_eventmanager_status_w;
wire timer0_eventmanager_pending_re;
wire timer0_eventmanager_pending_r;
wire timer0_eventmanager_pending_we;
wire timer0_eventmanager_pending_w;
reg timer0_eventmanager_storage = 1'd0;
reg timer0_eventmanager_re = 1'd0;
reg [31:0] timer0_value = 32'd0;
reg [13:0] interface_adr = 14'd0;
reg interface_we = 1'd0;
wire [7:0] interface_dat_w;
wire [7:0] interface_dat_r;
wire [29:0] bus_wishbone_adr;
wire [31:0] bus_wishbone_dat_w;
wire [31:0] bus_wishbone_dat_r;
wire [3:0] bus_wishbone_sel;
wire bus_wishbone_cyc;
wire bus_wishbone_stb;
reg bus_wishbone_ack = 1'd0;
wire bus_wishbone_we;
wire [2:0] bus_wishbone_cti;
wire [1:0] bus_wishbone_bte;
reg bus_wishbone_err = 1'd0;
(* dont_touch = "true" *) wire sys_clk;
wire sys_rst;
wire reset;
wire locked;
wire clkin;
wire clkout;
wire clkout_buf;
reg state = 1'd0;
reg next_state = 1'd0;
wire pll_fb;
wire [29:0] shared_adr;
wire [31:0] shared_dat_w;
reg [31:0] shared_dat_r = 32'd0;
wire [3:0] shared_sel;
wire shared_cyc;
wire shared_stb;
reg shared_ack = 1'd0;
wire shared_we;
wire [2:0] shared_cti;
wire [1:0] shared_bte;
wire shared_err;
wire [1:0] request;
reg grant = 1'd0;
reg [2:0] slave_sel = 3'd0;
reg [2:0] slave_sel_r = 3'd0;
reg error = 1'd0;
wire wait_1;
wire done;
reg [19:0] count = 20'd1000000;
wire [13:0] csrbankarray_interface0_bank_bus_adr;
wire csrbankarray_interface0_bank_bus_we;
wire [7:0] csrbankarray_interface0_bank_bus_dat_w;
reg [7:0] csrbankarray_interface0_bank_bus_dat_r = 8'd0;
wire csrbankarray_csrbank0_scratch3_re;
wire [7:0] csrbankarray_csrbank0_scratch3_r;
wire csrbankarray_csrbank0_scratch3_we;
wire [7:0] csrbankarray_csrbank0_scratch3_w;
wire csrbankarray_csrbank0_scratch2_re;
wire [7:0] csrbankarray_csrbank0_scratch2_r;
wire csrbankarray_csrbank0_scratch2_we;
wire [7:0] csrbankarray_csrbank0_scratch2_w;
wire csrbankarray_csrbank0_scratch1_re;
wire [7:0] csrbankarray_csrbank0_scratch1_r;
wire csrbankarray_csrbank0_scratch1_we;
wire [7:0] csrbankarray_csrbank0_scratch1_w;
wire csrbankarray_csrbank0_scratch0_re;
wire [7:0] csrbankarray_csrbank0_scratch0_r;
wire csrbankarray_csrbank0_scratch0_we;
wire [7:0] csrbankarray_csrbank0_scratch0_w;
wire csrbankarray_csrbank0_bus_errors3_re;
wire [7:0] csrbankarray_csrbank0_bus_errors3_r;
wire csrbankarray_csrbank0_bus_errors3_we;
wire [7:0] csrbankarray_csrbank0_bus_errors3_w;
wire csrbankarray_csrbank0_bus_errors2_re;
wire [7:0] csrbankarray_csrbank0_bus_errors2_r;
wire csrbankarray_csrbank0_bus_errors2_we;
wire [7:0] csrbankarray_csrbank0_bus_errors2_w;
wire csrbankarray_csrbank0_bus_errors1_re;
wire [7:0] csrbankarray_csrbank0_bus_errors1_r;
wire csrbankarray_csrbank0_bus_errors1_we;
wire [7:0] csrbankarray_csrbank0_bus_errors1_w;
wire csrbankarray_csrbank0_bus_errors0_re;
wire [7:0] csrbankarray_csrbank0_bus_errors0_r;
wire csrbankarray_csrbank0_bus_errors0_we;
wire [7:0] csrbankarray_csrbank0_bus_errors0_w;
wire csrbankarray_csrbank0_sel;
wire [13:0] csrbankarray_sram_bus_adr;
wire csrbankarray_sram_bus_we;
wire [7:0] csrbankarray_sram_bus_dat_w;
reg [7:0] csrbankarray_sram_bus_dat_r = 8'd0;
wire [3:0] csrbankarray_adr;
wire [7:0] csrbankarray_dat_r;
wire csrbankarray_sel;
reg csrbankarray_sel_r = 1'd0;
wire [13:0] csrbankarray_interface1_bank_bus_adr;
wire csrbankarray_interface1_bank_bus_we;
wire [7:0] csrbankarray_interface1_bank_bus_dat_w;
reg [7:0] csrbankarray_interface1_bank_bus_dat_r = 8'd0;
wire csrbankarray_csrbank1_load3_re;
wire [7:0] csrbankarray_csrbank1_load3_r;
wire csrbankarray_csrbank1_load3_we;
wire [7:0] csrbankarray_csrbank1_load3_w;
wire csrbankarray_csrbank1_load2_re;
wire [7:0] csrbankarray_csrbank1_load2_r;
wire csrbankarray_csrbank1_load2_we;
wire [7:0] csrbankarray_csrbank1_load2_w;
wire csrbankarray_csrbank1_load1_re;
wire [7:0] csrbankarray_csrbank1_load1_r;
wire csrbankarray_csrbank1_load1_we;
wire [7:0] csrbankarray_csrbank1_load1_w;
wire csrbankarray_csrbank1_load0_re;
wire [7:0] csrbankarray_csrbank1_load0_r;
wire csrbankarray_csrbank1_load0_we;
wire [7:0] csrbankarray_csrbank1_load0_w;
wire csrbankarray_csrbank1_reload3_re;
wire [7:0] csrbankarray_csrbank1_reload3_r;
wire csrbankarray_csrbank1_reload3_we;
wire [7:0] csrbankarray_csrbank1_reload3_w;
wire csrbankarray_csrbank1_reload2_re;
wire [7:0] csrbankarray_csrbank1_reload2_r;
wire csrbankarray_csrbank1_reload2_we;
wire [7:0] csrbankarray_csrbank1_reload2_w;
wire csrbankarray_csrbank1_reload1_re;
wire [7:0] csrbankarray_csrbank1_reload1_r;
wire csrbankarray_csrbank1_reload1_we;
wire [7:0] csrbankarray_csrbank1_reload1_w;
wire csrbankarray_csrbank1_reload0_re;
wire [7:0] csrbankarray_csrbank1_reload0_r;
wire csrbankarray_csrbank1_reload0_we;
wire [7:0] csrbankarray_csrbank1_reload0_w;
wire csrbankarray_csrbank1_en0_re;
wire csrbankarray_csrbank1_en0_r;
wire csrbankarray_csrbank1_en0_we;
wire csrbankarray_csrbank1_en0_w;
wire csrbankarray_csrbank1_update_value0_re;
wire csrbankarray_csrbank1_update_value0_r;
wire csrbankarray_csrbank1_update_value0_we;
wire csrbankarray_csrbank1_update_value0_w;
wire csrbankarray_csrbank1_value3_re;
wire [7:0] csrbankarray_csrbank1_value3_r;
wire csrbankarray_csrbank1_value3_we;
wire [7:0] csrbankarray_csrbank1_value3_w;
wire csrbankarray_csrbank1_value2_re;
wire [7:0] csrbankarray_csrbank1_value2_r;
wire csrbankarray_csrbank1_value2_we;
wire [7:0] csrbankarray_csrbank1_value2_w;
wire csrbankarray_csrbank1_value1_re;
wire [7:0] csrbankarray_csrbank1_value1_r;
wire csrbankarray_csrbank1_value1_we;
wire [7:0] csrbankarray_csrbank1_value1_w;
wire csrbankarray_csrbank1_value0_re;
wire [7:0] csrbankarray_csrbank1_value0_r;
wire csrbankarray_csrbank1_value0_we;
wire [7:0] csrbankarray_csrbank1_value0_w;
wire csrbankarray_csrbank1_ev_enable0_re;
wire csrbankarray_csrbank1_ev_enable0_r;
wire csrbankarray_csrbank1_ev_enable0_we;
wire csrbankarray_csrbank1_ev_enable0_w;
wire csrbankarray_csrbank1_sel;
wire [13:0] csrbankarray_interface2_bank_bus_adr;
wire csrbankarray_interface2_bank_bus_we;
wire [7:0] csrbankarray_interface2_bank_bus_dat_w;
reg [7:0] csrbankarray_interface2_bank_bus_dat_r = 8'd0;
wire csrbankarray_csrbank2_txfull_re;
wire csrbankarray_csrbank2_txfull_r;
wire csrbankarray_csrbank2_txfull_we;
wire csrbankarray_csrbank2_txfull_w;
wire csrbankarray_csrbank2_rxempty_re;
wire csrbankarray_csrbank2_rxempty_r;
wire csrbankarray_csrbank2_rxempty_we;
wire csrbankarray_csrbank2_rxempty_w;
wire csrbankarray_csrbank2_ev_enable0_re;
wire [1:0] csrbankarray_csrbank2_ev_enable0_r;
wire csrbankarray_csrbank2_ev_enable0_we;
wire [1:0] csrbankarray_csrbank2_ev_enable0_w;
wire csrbankarray_csrbank2_sel;
wire [13:0] csrbankarray_interface3_bank_bus_adr;
wire csrbankarray_interface3_bank_bus_we;
wire [7:0] csrbankarray_interface3_bank_bus_dat_w;
reg [7:0] csrbankarray_interface3_bank_bus_dat_r = 8'd0;
wire csrbankarray_csrbank3_tuning_word3_re;
wire [7:0] csrbankarray_csrbank3_tuning_word3_r;
wire csrbankarray_csrbank3_tuning_word3_we;
wire [7:0] csrbankarray_csrbank3_tuning_word3_w;
wire csrbankarray_csrbank3_tuning_word2_re;
wire [7:0] csrbankarray_csrbank3_tuning_word2_r;
wire csrbankarray_csrbank3_tuning_word2_we;
wire [7:0] csrbankarray_csrbank3_tuning_word2_w;
wire csrbankarray_csrbank3_tuning_word1_re;
wire [7:0] csrbankarray_csrbank3_tuning_word1_r;
wire csrbankarray_csrbank3_tuning_word1_we;
wire [7:0] csrbankarray_csrbank3_tuning_word1_w;
wire csrbankarray_csrbank3_tuning_word0_re;
wire [7:0] csrbankarray_csrbank3_tuning_word0_r;
wire csrbankarray_csrbank3_tuning_word0_we;
wire [7:0] csrbankarray_csrbank3_tuning_word0_w;
wire csrbankarray_csrbank3_sel;
wire [13:0] csrcon_adr;
wire csrcon_we;
wire [7:0] csrcon_dat_w;
wire [7:0] csrcon_dat_r;
reg [29:0] array_muxed0 = 30'd0;
reg [31:0] array_muxed1 = 32'd0;
reg [3:0] array_muxed2 = 4'd0;
reg array_muxed3 = 1'd0;
reg array_muxed4 = 1'd0;
reg array_muxed5 = 1'd0;
reg [2:0] array_muxed6 = 3'd0;
reg [1:0] array_muxed7 = 2'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg regs0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *) reg regs1 = 1'd0;
wire xilinxasyncresetsynchronizerimpl;
wire xilinxasyncresetsynchronizerimpl_rst_meta;
assign vexriscv_reset = ctrl_reset;
assign ctrl_bus_error = error;
always @(*) begin
vexriscv_interrupt <= 32'd0;
vexriscv_interrupt[1] <= timer0_irq;
vexriscv_interrupt[0] <= uart_irq;
end
assign ctrl_reset = ctrl_reset_reset_re;
assign ctrl_bus_errors_status = ctrl_bus_errors;
assign interface0_soc_bus_adr = vexriscv_ibus_adr;
assign interface0_soc_bus_dat_w = vexriscv_ibus_dat_w;
assign vexriscv_ibus_dat_r = interface0_soc_bus_dat_r;
assign interface0_soc_bus_sel = vexriscv_ibus_sel;
assign interface0_soc_bus_cyc = vexriscv_ibus_cyc;
assign interface0_soc_bus_stb = vexriscv_ibus_stb;
assign vexriscv_ibus_ack = interface0_soc_bus_ack;
assign interface0_soc_bus_we = vexriscv_ibus_we;
assign interface0_soc_bus_cti = vexriscv_ibus_cti;
assign interface0_soc_bus_bte = vexriscv_ibus_bte;
assign vexriscv_ibus_err = interface0_soc_bus_err;
assign interface1_soc_bus_adr = vexriscv_dbus_adr;
assign interface1_soc_bus_dat_w = vexriscv_dbus_dat_w;
assign vexriscv_dbus_dat_r = interface1_soc_bus_dat_r;
assign interface1_soc_bus_sel = vexriscv_dbus_sel;
assign interface1_soc_bus_cyc = vexriscv_dbus_cyc;
assign interface1_soc_bus_stb = vexriscv_dbus_stb;
assign vexriscv_dbus_ack = interface1_soc_bus_ack;
assign interface1_soc_bus_we = vexriscv_dbus_we;
assign interface1_soc_bus_cti = vexriscv_dbus_cti;
assign interface1_soc_bus_bte = vexriscv_dbus_bte;
assign vexriscv_dbus_err = interface1_soc_bus_err;
assign rom_adr = rom_bus_adr[12:0];
assign rom_bus_dat_r = rom_dat_r;
always @(*) begin
sram_we <= 4'd0;
sram_we[0] <= (((sram_bus_cyc & sram_bus_stb) & sram_bus_we) & sram_bus_sel[0]);
sram_we[1] <= (((sram_bus_cyc & sram_bus_stb) & sram_bus_we) & sram_bus_sel[1]);
sram_we[2] <= (((sram_bus_cyc & sram_bus_stb) & sram_bus_we) & sram_bus_sel[2]);
sram_we[3] <= (((sram_bus_cyc & sram_bus_stb) & sram_bus_we) & sram_bus_sel[3]);
end
assign sram_adr = sram_bus_adr[12:0];
assign sram_bus_dat_r = sram_dat_r;
assign sram_dat_w = sram_bus_dat_w;
assign uart_tx_fifo_sink_valid = uart_rxtx_re;
assign uart_tx_fifo_sink_payload_data = uart_rxtx_r;
assign uart_txfull_status = (~uart_tx_fifo_sink_ready);
assign uart_phy_sink_valid = uart_tx_fifo_source_valid;
assign uart_tx_fifo_source_ready = uart_phy_sink_ready;
assign uart_phy_sink_first = uart_tx_fifo_source_first;
assign uart_phy_sink_last = uart_tx_fifo_source_last;
assign uart_phy_sink_payload_data = uart_tx_fifo_source_payload_data;
assign uart_tx_trigger = (~uart_tx_fifo_sink_ready);
assign uart_rx_fifo_sink_valid = uart_phy_source_valid;
assign uart_phy_source_ready = uart_rx_fifo_sink_ready;
assign uart_rx_fifo_sink_first = uart_phy_source_first;
assign uart_rx_fifo_sink_last = uart_phy_source_last;
assign uart_rx_fifo_sink_payload_data = uart_phy_source_payload_data;
assign uart_rxempty_status = (~uart_rx_fifo_source_valid);
assign uart_rxtx_w = uart_rx_fifo_source_payload_data;
assign uart_rx_fifo_source_ready = uart_rx_clear;
assign uart_rx_trigger = (~uart_rx_fifo_source_valid);
always @(*) begin
uart_tx_clear <= 1'd0;
if ((uart_eventmanager_pending_re & uart_eventmanager_pending_r[0])) begin
uart_tx_clear <= 1'd1;
end
end
always @(*) begin
uart_eventmanager_status_w <= 2'd0;
uart_eventmanager_status_w[0] <= uart_tx_status;
uart_eventmanager_status_w[1] <= uart_rx_status;
end
always @(*) begin
uart_rx_clear <= 1'd0;
if ((uart_eventmanager_pending_re & uart_eventmanager_pending_r[1])) begin
uart_rx_clear <= 1'd1;
end
end
always @(*) begin
uart_eventmanager_pending_w <= 2'd0;
uart_eventmanager_pending_w[0] <= uart_tx_pending;
uart_eventmanager_pending_w[1] <= uart_rx_pending;
end
assign uart_irq = ((uart_eventmanager_pending_w[0] & uart_eventmanager_storage[0]) | (uart_eventmanager_pending_w[1] & uart_eventmanager_storage[1]));
assign uart_tx_status = uart_tx_trigger;
assign uart_rx_status = uart_rx_trigger;
assign uart_tx_fifo_syncfifo_din = {uart_tx_fifo_fifo_in_last, uart_tx_fifo_fifo_in_first, uart_tx_fifo_fifo_in_payload_data};
assign {uart_tx_fifo_fifo_out_last, uart_tx_fifo_fifo_out_first, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout;
assign uart_tx_fifo_sink_ready = uart_tx_fifo_syncfifo_writable;
assign uart_tx_fifo_syncfifo_we = uart_tx_fifo_sink_valid;
assign uart_tx_fifo_fifo_in_first = uart_tx_fifo_sink_first;
assign uart_tx_fifo_fifo_in_last = uart_tx_fifo_sink_last;
assign uart_tx_fifo_fifo_in_payload_data = uart_tx_fifo_sink_payload_data;
assign uart_tx_fifo_source_valid = uart_tx_fifo_readable;
assign uart_tx_fifo_source_first = uart_tx_fifo_fifo_out_first;
assign uart_tx_fifo_source_last = uart_tx_fifo_fifo_out_last;
assign uart_tx_fifo_source_payload_data = uart_tx_fifo_fifo_out_payload_data;
assign uart_tx_fifo_re = uart_tx_fifo_source_ready;
assign uart_tx_fifo_syncfifo_re = (uart_tx_fifo_syncfifo_readable & ((~uart_tx_fifo_readable) | uart_tx_fifo_re));
assign uart_tx_fifo_level1 = (uart_tx_fifo_level0 + uart_tx_fifo_readable);
always @(*) begin
uart_tx_fifo_wrport_adr <= 4'd0;
if (uart_tx_fifo_replace) begin
uart_tx_fifo_wrport_adr <= (uart_tx_fifo_produce - 1'd1);
end else begin
uart_tx_fifo_wrport_adr <= uart_tx_fifo_produce;
end
end
assign uart_tx_fifo_wrport_dat_w = uart_tx_fifo_syncfifo_din;
assign uart_tx_fifo_wrport_we = (uart_tx_fifo_syncfifo_we & (uart_tx_fifo_syncfifo_writable | uart_tx_fifo_replace));
assign uart_tx_fifo_do_read = (uart_tx_fifo_syncfifo_readable & uart_tx_fifo_syncfifo_re);
assign uart_tx_fifo_rdport_adr = uart_tx_fifo_consume;
assign uart_tx_fifo_syncfifo_dout = uart_tx_fifo_rdport_dat_r;
assign uart_tx_fifo_rdport_re = uart_tx_fifo_do_read;
assign uart_tx_fifo_syncfifo_writable = (uart_tx_fifo_level0 != 5'd16);
assign uart_tx_fifo_syncfifo_readable = (uart_tx_fifo_level0 != 1'd0);
assign uart_rx_fifo_syncfifo_din = {uart_rx_fifo_fifo_in_last, uart_rx_fifo_fifo_in_first, uart_rx_fifo_fifo_in_payload_data};
assign {uart_rx_fifo_fifo_out_last, uart_rx_fifo_fifo_out_first, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout;
assign uart_rx_fifo_sink_ready = uart_rx_fifo_syncfifo_writable;
assign uart_rx_fifo_syncfifo_we = uart_rx_fifo_sink_valid;
assign uart_rx_fifo_fifo_in_first = uart_rx_fifo_sink_first;
assign uart_rx_fifo_fifo_in_last = uart_rx_fifo_sink_last;
assign uart_rx_fifo_fifo_in_payload_data = uart_rx_fifo_sink_payload_data;
assign uart_rx_fifo_source_valid = uart_rx_fifo_readable;
assign uart_rx_fifo_source_first = uart_rx_fifo_fifo_out_first;
assign uart_rx_fifo_source_last = uart_rx_fifo_fifo_out_last;
assign uart_rx_fifo_source_payload_data = uart_rx_fifo_fifo_out_payload_data;
assign uart_rx_fifo_re = uart_rx_fifo_source_ready;
assign uart_rx_fifo_syncfifo_re = (uart_rx_fifo_syncfifo_readable & ((~uart_rx_fifo_readable) | uart_rx_fifo_re));
assign uart_rx_fifo_level1 = (uart_rx_fifo_level0 + uart_rx_fifo_readable);
always @(*) begin
uart_rx_fifo_wrport_adr <= 4'd0;
if (uart_rx_fifo_replace) begin
uart_rx_fifo_wrport_adr <= (uart_rx_fifo_produce - 1'd1);
end else begin
uart_rx_fifo_wrport_adr <= uart_rx_fifo_produce;
end
end
assign uart_rx_fifo_wrport_dat_w = uart_rx_fifo_syncfifo_din;
assign uart_rx_fifo_wrport_we = (uart_rx_fifo_syncfifo_we & (uart_rx_fifo_syncfifo_writable | uart_rx_fifo_replace));
assign uart_rx_fifo_do_read = (uart_rx_fifo_syncfifo_readable & uart_rx_fifo_syncfifo_re);
assign uart_rx_fifo_rdport_adr = uart_rx_fifo_consume;
assign uart_rx_fifo_syncfifo_dout = uart_rx_fifo_rdport_dat_r;
assign uart_rx_fifo_rdport_re = uart_rx_fifo_do_read;
assign uart_rx_fifo_syncfifo_writable = (uart_rx_fifo_level0 != 5'd16);
assign uart_rx_fifo_syncfifo_readable = (uart_rx_fifo_level0 != 1'd0);
assign timer0_zero_trigger = (timer0_value != 1'd0);
assign timer0_eventmanager_status_w = timer0_zero_status;
always @(*) begin
timer0_zero_clear <= 1'd0;
if ((timer0_eventmanager_pending_re & timer0_eventmanager_pending_r)) begin
timer0_zero_clear <= 1'd1;
end
end
assign timer0_eventmanager_pending_w = timer0_zero_pending;
assign timer0_irq = (timer0_eventmanager_pending_w & timer0_eventmanager_storage);
assign timer0_zero_status = timer0_zero_trigger;
assign interface_dat_w = bus_wishbone_dat_w;
assign bus_wishbone_dat_r = interface_dat_r;
always @(*) begin
next_state <= 1'd0;
interface_adr <= 14'd0;
interface_we <= 1'd0;
bus_wishbone_ack <= 1'd0;
next_state <= state;
case (state)
1'd1: begin
bus_wishbone_ack <= 1'd1;
next_state <= 1'd0;
end
default: begin
if ((bus_wishbone_cyc & bus_wishbone_stb)) begin
interface_adr <= bus_wishbone_adr;
interface_we <= bus_wishbone_we;
next_state <= 1'd1;
end
end
endcase
end
assign reset = (~cpu_reset);
assign sys_clk = clkout_buf;
assign shared_adr = array_muxed0;
assign shared_dat_w = array_muxed1;
assign shared_sel = array_muxed2;
assign shared_cyc = array_muxed3;
assign shared_stb = array_muxed4;
assign shared_we = array_muxed5;
assign shared_cti = array_muxed6;
assign shared_bte = array_muxed7;
assign interface0_soc_bus_dat_r = shared_dat_r;
assign interface1_soc_bus_dat_r = shared_dat_r;
assign interface0_soc_bus_ack = (shared_ack & (grant == 1'd0));
assign interface1_soc_bus_ack = (shared_ack & (grant == 1'd1));
assign interface0_soc_bus_err = (shared_err & (grant == 1'd0));
assign interface1_soc_bus_err = (shared_err & (grant == 1'd1));
assign request = {interface1_soc_bus_cyc, interface0_soc_bus_cyc};
always @(*) begin
slave_sel <= 3'd0;
slave_sel[0] <= (shared_adr[28:13] == 1'd0);
slave_sel[1] <= (shared_adr[28:13] == 10'd512);
slave_sel[2] <= (shared_adr[28:22] == 2'd2);
end
assign rom_bus_adr = shared_adr;
assign rom_bus_dat_w = shared_dat_w;
assign rom_bus_sel = shared_sel;
assign rom_bus_stb = shared_stb;
assign rom_bus_we = shared_we;
assign rom_bus_cti = shared_cti;
assign rom_bus_bte = shared_bte;
assign sram_bus_adr = shared_adr;
assign sram_bus_dat_w = shared_dat_w;
assign sram_bus_sel = shared_sel;
assign sram_bus_stb = shared_stb;
assign sram_bus_we = shared_we;
assign sram_bus_cti = shared_cti;
assign sram_bus_bte = shared_bte;
assign bus_wishbone_adr = shared_adr;
assign bus_wishbone_dat_w = shared_dat_w;
assign bus_wishbone_sel = shared_sel;
assign bus_wishbone_stb = shared_stb;
assign bus_wishbone_we = shared_we;
assign bus_wishbone_cti = shared_cti;
assign bus_wishbone_bte = shared_bte;
assign rom_bus_cyc = (shared_cyc & slave_sel[0]);
assign sram_bus_cyc = (shared_cyc & slave_sel[1]);
assign bus_wishbone_cyc = (shared_cyc & slave_sel[2]);
assign shared_err = ((rom_bus_err | sram_bus_err) | bus_wishbone_err);
assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack));
always @(*) begin
shared_ack <= 1'd0;
error <= 1'd0;
shared_dat_r <= 32'd0;
shared_ack <= ((rom_bus_ack | sram_bus_ack) | bus_wishbone_ack);
shared_dat_r <= ((({32{slave_sel_r[0]}} & rom_bus_dat_r) | ({32{slave_sel_r[1]}} & sram_bus_dat_r)) | ({32{slave_sel_r[2]}} & bus_wishbone_dat_r));
if (done) begin
shared_dat_r <= 32'd4294967295;
shared_ack <= 1'd1;
error <= 1'd1;
end
end
assign done = (count == 1'd0);
assign csrbankarray_csrbank0_sel = (csrbankarray_interface0_bank_bus_adr[13:9] == 1'd0);
assign ctrl_reset_reset_r = csrbankarray_interface0_bank_bus_dat_w[0];
assign ctrl_reset_reset_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 1'd0));
assign ctrl_reset_reset_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 1'd0));
assign csrbankarray_csrbank0_scratch3_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_scratch3_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 1'd1));
assign csrbankarray_csrbank0_scratch3_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 1'd1));
assign csrbankarray_csrbank0_scratch2_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_scratch2_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 2'd2));
assign csrbankarray_csrbank0_scratch2_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 2'd2));
assign csrbankarray_csrbank0_scratch1_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_scratch1_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 2'd3));
assign csrbankarray_csrbank0_scratch1_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 2'd3));
assign csrbankarray_csrbank0_scratch0_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_scratch0_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd4));
assign csrbankarray_csrbank0_scratch0_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd4));
assign csrbankarray_csrbank0_bus_errors3_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_bus_errors3_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd5));
assign csrbankarray_csrbank0_bus_errors3_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd5));
assign csrbankarray_csrbank0_bus_errors2_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_bus_errors2_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd6));
assign csrbankarray_csrbank0_bus_errors2_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd6));
assign csrbankarray_csrbank0_bus_errors1_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_bus_errors1_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd7));
assign csrbankarray_csrbank0_bus_errors1_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 3'd7));
assign csrbankarray_csrbank0_bus_errors0_r = csrbankarray_interface0_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank0_bus_errors0_re = ((csrbankarray_csrbank0_sel & csrbankarray_interface0_bank_bus_we) & (csrbankarray_interface0_bank_bus_adr[3:0] == 4'd8));
assign csrbankarray_csrbank0_bus_errors0_we = ((csrbankarray_csrbank0_sel & (~csrbankarray_interface0_bank_bus_we)) & (csrbankarray_interface0_bank_bus_adr[3:0] == 4'd8));
assign csrbankarray_csrbank0_scratch3_w = ctrl_storage[31:24];
assign csrbankarray_csrbank0_scratch2_w = ctrl_storage[23:16];
assign csrbankarray_csrbank0_scratch1_w = ctrl_storage[15:8];
assign csrbankarray_csrbank0_scratch0_w = ctrl_storage[7:0];
assign csrbankarray_csrbank0_bus_errors3_w = ctrl_bus_errors_status[31:24];
assign csrbankarray_csrbank0_bus_errors2_w = ctrl_bus_errors_status[23:16];
assign csrbankarray_csrbank0_bus_errors1_w = ctrl_bus_errors_status[15:8];
assign csrbankarray_csrbank0_bus_errors0_w = ctrl_bus_errors_status[7:0];
assign ctrl_bus_errors_we = csrbankarray_csrbank0_bus_errors0_we;
assign csrbankarray_sel = (csrbankarray_sram_bus_adr[13:9] == 3'd4);
always @(*) begin
csrbankarray_sram_bus_dat_r <= 8'd0;
if (csrbankarray_sel_r) begin
csrbankarray_sram_bus_dat_r <= csrbankarray_dat_r;
end
end
assign csrbankarray_adr = csrbankarray_sram_bus_adr[3:0];
assign csrbankarray_csrbank1_sel = (csrbankarray_interface1_bank_bus_adr[13:9] == 3'd5);
assign csrbankarray_csrbank1_load3_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_load3_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 1'd0));
assign csrbankarray_csrbank1_load3_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 1'd0));
assign csrbankarray_csrbank1_load2_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_load2_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 1'd1));
assign csrbankarray_csrbank1_load2_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 1'd1));
assign csrbankarray_csrbank1_load1_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_load1_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 2'd2));
assign csrbankarray_csrbank1_load1_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 2'd2));
assign csrbankarray_csrbank1_load0_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_load0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 2'd3));
assign csrbankarray_csrbank1_load0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 2'd3));
assign csrbankarray_csrbank1_reload3_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_reload3_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd4));
assign csrbankarray_csrbank1_reload3_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd4));
assign csrbankarray_csrbank1_reload2_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_reload2_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd5));
assign csrbankarray_csrbank1_reload2_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd5));
assign csrbankarray_csrbank1_reload1_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_reload1_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd6));
assign csrbankarray_csrbank1_reload1_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd6));
assign csrbankarray_csrbank1_reload0_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_reload0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd7));
assign csrbankarray_csrbank1_reload0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 3'd7));
assign csrbankarray_csrbank1_en0_r = csrbankarray_interface1_bank_bus_dat_w[0];
assign csrbankarray_csrbank1_en0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd8));
assign csrbankarray_csrbank1_en0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd8));
assign csrbankarray_csrbank1_update_value0_r = csrbankarray_interface1_bank_bus_dat_w[0];
assign csrbankarray_csrbank1_update_value0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd9));
assign csrbankarray_csrbank1_update_value0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd9));
assign csrbankarray_csrbank1_value3_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_value3_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd10));
assign csrbankarray_csrbank1_value3_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd10));
assign csrbankarray_csrbank1_value2_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_value2_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd11));
assign csrbankarray_csrbank1_value2_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd11));
assign csrbankarray_csrbank1_value1_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_value1_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd12));
assign csrbankarray_csrbank1_value1_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd12));
assign csrbankarray_csrbank1_value0_r = csrbankarray_interface1_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank1_value0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd13));
assign csrbankarray_csrbank1_value0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd13));
assign timer0_eventmanager_status_r = csrbankarray_interface1_bank_bus_dat_w[0];
assign timer0_eventmanager_status_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd14));
assign timer0_eventmanager_status_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd14));
assign timer0_eventmanager_pending_r = csrbankarray_interface1_bank_bus_dat_w[0];
assign timer0_eventmanager_pending_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd15));
assign timer0_eventmanager_pending_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 4'd15));
assign csrbankarray_csrbank1_ev_enable0_r = csrbankarray_interface1_bank_bus_dat_w[0];
assign csrbankarray_csrbank1_ev_enable0_re = ((csrbankarray_csrbank1_sel & csrbankarray_interface1_bank_bus_we) & (csrbankarray_interface1_bank_bus_adr[4:0] == 5'd16));
assign csrbankarray_csrbank1_ev_enable0_we = ((csrbankarray_csrbank1_sel & (~csrbankarray_interface1_bank_bus_we)) & (csrbankarray_interface1_bank_bus_adr[4:0] == 5'd16));
assign csrbankarray_csrbank1_load3_w = timer0_load_storage[31:24];
assign csrbankarray_csrbank1_load2_w = timer0_load_storage[23:16];
assign csrbankarray_csrbank1_load1_w = timer0_load_storage[15:8];
assign csrbankarray_csrbank1_load0_w = timer0_load_storage[7:0];
assign csrbankarray_csrbank1_reload3_w = timer0_reload_storage[31:24];
assign csrbankarray_csrbank1_reload2_w = timer0_reload_storage[23:16];
assign csrbankarray_csrbank1_reload1_w = timer0_reload_storage[15:8];
assign csrbankarray_csrbank1_reload0_w = timer0_reload_storage[7:0];
assign csrbankarray_csrbank1_en0_w = timer0_en_storage;
assign csrbankarray_csrbank1_update_value0_w = timer0_update_value_storage;
assign csrbankarray_csrbank1_value3_w = timer0_value_status[31:24];
assign csrbankarray_csrbank1_value2_w = timer0_value_status[23:16];
assign csrbankarray_csrbank1_value1_w = timer0_value_status[15:8];
assign csrbankarray_csrbank1_value0_w = timer0_value_status[7:0];
assign timer0_value_we = csrbankarray_csrbank1_value0_we;
assign csrbankarray_csrbank1_ev_enable0_w = timer0_eventmanager_storage;
assign csrbankarray_csrbank2_sel = (csrbankarray_interface2_bank_bus_adr[13:9] == 2'd3);
assign uart_rxtx_r = csrbankarray_interface2_bank_bus_dat_w[7:0];
assign uart_rxtx_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 1'd0));
assign uart_rxtx_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 1'd0));
assign csrbankarray_csrbank2_txfull_r = csrbankarray_interface2_bank_bus_dat_w[0];
assign csrbankarray_csrbank2_txfull_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 1'd1));
assign csrbankarray_csrbank2_txfull_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 1'd1));
assign csrbankarray_csrbank2_rxempty_r = csrbankarray_interface2_bank_bus_dat_w[0];
assign csrbankarray_csrbank2_rxempty_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 2'd2));
assign csrbankarray_csrbank2_rxempty_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 2'd2));
assign uart_eventmanager_status_r = csrbankarray_interface2_bank_bus_dat_w[1:0];
assign uart_eventmanager_status_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 2'd3));
assign uart_eventmanager_status_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 2'd3));
assign uart_eventmanager_pending_r = csrbankarray_interface2_bank_bus_dat_w[1:0];
assign uart_eventmanager_pending_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 3'd4));
assign uart_eventmanager_pending_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 3'd4));
assign csrbankarray_csrbank2_ev_enable0_r = csrbankarray_interface2_bank_bus_dat_w[1:0];
assign csrbankarray_csrbank2_ev_enable0_re = ((csrbankarray_csrbank2_sel & csrbankarray_interface2_bank_bus_we) & (csrbankarray_interface2_bank_bus_adr[2:0] == 3'd5));
assign csrbankarray_csrbank2_ev_enable0_we = ((csrbankarray_csrbank2_sel & (~csrbankarray_interface2_bank_bus_we)) & (csrbankarray_interface2_bank_bus_adr[2:0] == 3'd5));
assign csrbankarray_csrbank2_txfull_w = uart_txfull_status;
assign uart_txfull_we = csrbankarray_csrbank2_txfull_we;
assign csrbankarray_csrbank2_rxempty_w = uart_rxempty_status;
assign uart_rxempty_we = csrbankarray_csrbank2_rxempty_we;
assign csrbankarray_csrbank2_ev_enable0_w = uart_eventmanager_storage[1:0];
assign csrbankarray_csrbank3_sel = (csrbankarray_interface3_bank_bus_adr[13:9] == 2'd2);
assign csrbankarray_csrbank3_tuning_word3_r = csrbankarray_interface3_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank3_tuning_word3_re = ((csrbankarray_csrbank3_sel & csrbankarray_interface3_bank_bus_we) & (csrbankarray_interface3_bank_bus_adr[1:0] == 1'd0));
assign csrbankarray_csrbank3_tuning_word3_we = ((csrbankarray_csrbank3_sel & (~csrbankarray_interface3_bank_bus_we)) & (csrbankarray_interface3_bank_bus_adr[1:0] == 1'd0));
assign csrbankarray_csrbank3_tuning_word2_r = csrbankarray_interface3_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank3_tuning_word2_re = ((csrbankarray_csrbank3_sel & csrbankarray_interface3_bank_bus_we) & (csrbankarray_interface3_bank_bus_adr[1:0] == 1'd1));
assign csrbankarray_csrbank3_tuning_word2_we = ((csrbankarray_csrbank3_sel & (~csrbankarray_interface3_bank_bus_we)) & (csrbankarray_interface3_bank_bus_adr[1:0] == 1'd1));
assign csrbankarray_csrbank3_tuning_word1_r = csrbankarray_interface3_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank3_tuning_word1_re = ((csrbankarray_csrbank3_sel & csrbankarray_interface3_bank_bus_we) & (csrbankarray_interface3_bank_bus_adr[1:0] == 2'd2));
assign csrbankarray_csrbank3_tuning_word1_we = ((csrbankarray_csrbank3_sel & (~csrbankarray_interface3_bank_bus_we)) & (csrbankarray_interface3_bank_bus_adr[1:0] == 2'd2));
assign csrbankarray_csrbank3_tuning_word0_r = csrbankarray_interface3_bank_bus_dat_w[7:0];
assign csrbankarray_csrbank3_tuning_word0_re = ((csrbankarray_csrbank3_sel & csrbankarray_interface3_bank_bus_we) & (csrbankarray_interface3_bank_bus_adr[1:0] == 2'd3));
assign csrbankarray_csrbank3_tuning_word0_we = ((csrbankarray_csrbank3_sel & (~csrbankarray_interface3_bank_bus_we)) & (csrbankarray_interface3_bank_bus_adr[1:0] == 2'd3));
assign csrbankarray_csrbank3_tuning_word3_w = uart_phy_storage[31:24];
assign csrbankarray_csrbank3_tuning_word2_w = uart_phy_storage[23:16];
assign csrbankarray_csrbank3_tuning_word1_w = uart_phy_storage[15:8];
assign csrbankarray_csrbank3_tuning_word0_w = uart_phy_storage[7:0];
assign csrcon_adr = interface_adr;
assign csrcon_we = interface_we;
assign csrcon_dat_w = interface_dat_w;
assign interface_dat_r = csrcon_dat_r;
assign csrbankarray_interface0_bank_bus_adr = csrcon_adr;
assign csrbankarray_interface1_bank_bus_adr = csrcon_adr;
assign csrbankarray_interface2_bank_bus_adr = csrcon_adr;
assign csrbankarray_interface3_bank_bus_adr = csrcon_adr;
assign csrbankarray_sram_bus_adr = csrcon_adr;
assign csrbankarray_interface0_bank_bus_we = csrcon_we;
assign csrbankarray_interface1_bank_bus_we = csrcon_we;
assign csrbankarray_interface2_bank_bus_we = csrcon_we;
assign csrbankarray_interface3_bank_bus_we = csrcon_we;
assign csrbankarray_sram_bus_we = csrcon_we;
assign csrbankarray_interface0_bank_bus_dat_w = csrcon_dat_w;
assign csrbankarray_interface1_bank_bus_dat_w = csrcon_dat_w;
assign csrbankarray_interface2_bank_bus_dat_w = csrcon_dat_w;
assign csrbankarray_interface3_bank_bus_dat_w = csrcon_dat_w;
assign csrbankarray_sram_bus_dat_w = csrcon_dat_w;
assign csrcon_dat_r = ((((csrbankarray_interface0_bank_bus_dat_r | csrbankarray_interface1_bank_bus_dat_r) | csrbankarray_interface2_bank_bus_dat_r) | csrbankarray_interface3_bank_bus_dat_r) | csrbankarray_sram_bus_dat_r);
always @(*) begin
array_muxed0 <= 30'd0;
case (grant)
1'd0: begin
array_muxed0 <= interface0_soc_bus_adr;
end
default: begin
array_muxed0 <= interface1_soc_bus_adr;
end
endcase
end
always @(*) begin
array_muxed1 <= 32'd0;
case (grant)
1'd0: begin
array_muxed1 <= interface0_soc_bus_dat_w;
end
default: begin
array_muxed1 <= interface1_soc_bus_dat_w;
end
endcase
end
always @(*) begin
array_muxed2 <= 4'd0;
case (grant)
1'd0: begin
array_muxed2 <= interface0_soc_bus_sel;
end
default: begin
array_muxed2 <= interface1_soc_bus_sel;
end
endcase
end
always @(*) begin
array_muxed3 <= 1'd0;
case (grant)
1'd0: begin
array_muxed3 <= interface0_soc_bus_cyc;
end
default: begin
array_muxed3 <= interface1_soc_bus_cyc;
end
endcase
end
always @(*) begin
array_muxed4 <= 1'd0;
case (grant)
1'd0: begin
array_muxed4 <= interface0_soc_bus_stb;
end
default: begin
array_muxed4 <= interface1_soc_bus_stb;
end
endcase
end
always @(*) begin
array_muxed5 <= 1'd0;
case (grant)
1'd0: begin
array_muxed5 <= interface0_soc_bus_we;
end
default: begin
array_muxed5 <= interface1_soc_bus_we;
end
endcase
end
always @(*) begin
array_muxed6 <= 3'd0;
case (grant)
1'd0: begin
array_muxed6 <= interface0_soc_bus_cti;
end
default: begin
array_muxed6 <= interface1_soc_bus_cti;
end
endcase
end
always @(*) begin
array_muxed7 <= 2'd0;
case (grant)
1'd0: begin
array_muxed7 <= interface0_soc_bus_bte;
end
default: begin
array_muxed7 <= interface1_soc_bus_bte;
end
endcase
end
assign uart_phy_rx = regs1;
assign xilinxasyncresetsynchronizerimpl = ((~locked) | reset);
always @(posedge sys_clk) begin
if ((ctrl_bus_errors != 32'd4294967295)) begin
if (ctrl_bus_error) begin
ctrl_bus_errors <= (ctrl_bus_errors + 1'd1);
end
end
rom_bus_ack <= 1'd0;
if (((rom_bus_cyc & rom_bus_stb) & (~rom_bus_ack))) begin
rom_bus_ack <= 1'd1;
end
sram_bus_ack <= 1'd0;
if (((sram_bus_cyc & sram_bus_stb) & (~sram_bus_ack))) begin
sram_bus_ack <= 1'd1;
end
uart_phy_sink_ready <= 1'd0;
if (((uart_phy_sink_valid & (~uart_phy_tx_busy)) & (~uart_phy_sink_ready))) begin
uart_phy_tx_reg <= uart_phy_sink_payload_data;
uart_phy_tx_bitcount <= 1'd0;
uart_phy_tx_busy <= 1'd1;
serial_tx <= 1'd0;
end else begin
if ((uart_phy_uart_clk_txen & uart_phy_tx_busy)) begin
uart_phy_tx_bitcount <= (uart_phy_tx_bitcount + 1'd1);
if ((uart_phy_tx_bitcount == 4'd8)) begin
serial_tx <= 1'd1;
end else begin
if ((uart_phy_tx_bitcount == 4'd9)) begin
serial_tx <= 1'd1;
uart_phy_tx_busy <= 1'd0;
uart_phy_sink_ready <= 1'd1;
end else begin
serial_tx <= uart_phy_tx_reg[0];
uart_phy_tx_reg <= {1'd0, uart_phy_tx_reg[7:1]};
end
end
end
end
if (uart_phy_tx_busy) begin
{uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= (uart_phy_phase_accumulator_tx + uart_phy_storage);
end else begin
{uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= 1'd0;
end
uart_phy_source_valid <= 1'd0;
uart_phy_rx_r <= uart_phy_rx;
if ((~uart_phy_rx_busy)) begin
if (((~uart_phy_rx) & uart_phy_rx_r)) begin
uart_phy_rx_busy <= 1'd1;
uart_phy_rx_bitcount <= 1'd0;
end
end else begin
if (uart_phy_uart_clk_rxen) begin
uart_phy_rx_bitcount <= (uart_phy_rx_bitcount + 1'd1);
if ((uart_phy_rx_bitcount == 1'd0)) begin
if (uart_phy_rx) begin
uart_phy_rx_busy <= 1'd0;
end
end else begin
if ((uart_phy_rx_bitcount == 4'd9)) begin
uart_phy_rx_busy <= 1'd0;
if (uart_phy_rx) begin
uart_phy_source_payload_data <= uart_phy_rx_reg;
uart_phy_source_valid <= 1'd1;
end
end else begin
uart_phy_rx_reg <= {uart_phy_rx, uart_phy_rx_reg[7:1]};
end
end
end
end
if (uart_phy_rx_busy) begin
{uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= (uart_phy_phase_accumulator_rx + uart_phy_storage);
end else begin
{uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= 32'd2147483648;
end
if (uart_tx_clear) begin
uart_tx_pending <= 1'd0;
end
uart_tx_old_trigger <= uart_tx_trigger;
if (((~uart_tx_trigger) & uart_tx_old_trigger)) begin
uart_tx_pending <= 1'd1;
end
if (uart_rx_clear) begin
uart_rx_pending <= 1'd0;
end
uart_rx_old_trigger <= uart_rx_trigger;
if (((~uart_rx_trigger) & uart_rx_old_trigger)) begin
uart_rx_pending <= 1'd1;
end
if (uart_tx_fifo_syncfifo_re) begin
uart_tx_fifo_readable <= 1'd1;
end else begin
if (uart_tx_fifo_re) begin
uart_tx_fifo_readable <= 1'd0;
end
end
if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
uart_tx_fifo_produce <= (uart_tx_fifo_produce + 1'd1);
end
if (uart_tx_fifo_do_read) begin
uart_tx_fifo_consume <= (uart_tx_fifo_consume + 1'd1);
end
if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
if ((~uart_tx_fifo_do_read)) begin
uart_tx_fifo_level0 <= (uart_tx_fifo_level0 + 1'd1);
end
end else begin
if (uart_tx_fifo_do_read) begin
uart_tx_fifo_level0 <= (uart_tx_fifo_level0 - 1'd1);
end
end
if (uart_rx_fifo_syncfifo_re) begin
uart_rx_fifo_readable <= 1'd1;
end else begin
if (uart_rx_fifo_re) begin
uart_rx_fifo_readable <= 1'd0;
end
end
if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
uart_rx_fifo_produce <= (uart_rx_fifo_produce + 1'd1);
end
if (uart_rx_fifo_do_read) begin
uart_rx_fifo_consume <= (uart_rx_fifo_consume + 1'd1);
end
if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
if ((~uart_rx_fifo_do_read)) begin
uart_rx_fifo_level0 <= (uart_rx_fifo_level0 + 1'd1);
end
end else begin
if (uart_rx_fifo_do_read) begin
uart_rx_fifo_level0 <= (uart_rx_fifo_level0 - 1'd1);
end
end
if (uart_reset) begin
uart_tx_pending <= 1'd0;
uart_tx_old_trigger <= 1'd0;
uart_rx_pending <= 1'd0;
uart_rx_old_trigger <= 1'd0;
uart_tx_fifo_readable <= 1'd0;
uart_tx_fifo_level0 <= 5'd0;
uart_tx_fifo_produce <= 4'd0;
uart_tx_fifo_consume <= 4'd0;
uart_rx_fifo_readable <= 1'd0;
uart_rx_fifo_level0 <= 5'd0;
uart_rx_fifo_produce <= 4'd0;
uart_rx_fifo_consume <= 4'd0;
end
if (timer0_en_storage) begin
if ((timer0_value == 1'd0)) begin
timer0_value <= timer0_reload_storage;
end else begin
timer0_value <= (timer0_value - 1'd1);
end
end else begin
timer0_value <= timer0_load_storage;
end
if (timer0_update_value_re) begin
timer0_value_status <= timer0_value;
end
if (timer0_zero_clear) begin
timer0_zero_pending <= 1'd0;
end
timer0_zero_old_trigger <= timer0_zero_trigger;
if (((~timer0_zero_trigger) & timer0_zero_old_trigger)) begin
timer0_zero_pending <= 1'd1;
end
state <= next_state;
case (grant)
1'd0: begin
if ((~request[0])) begin
if (request[1]) begin
grant <= 1'd1;
end
end
end
1'd1: begin
if ((~request[1])) begin
if (request[0]) begin
grant <= 1'd0;
end
end
end
endcase
slave_sel_r <= slave_sel;
if (wait_1) begin
if ((~done)) begin
count <= (count - 1'd1);
end
end else begin
count <= 20'd1000000;
end
csrbankarray_interface0_bank_bus_dat_r <= 1'd0;
if (csrbankarray_csrbank0_sel) begin
case (csrbankarray_interface0_bank_bus_adr[3:0])
1'd0: begin
csrbankarray_interface0_bank_bus_dat_r <= ctrl_reset_reset_w;
end
1'd1: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_scratch3_w;
end
2'd2: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_scratch2_w;
end
2'd3: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_scratch1_w;
end
3'd4: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_scratch0_w;
end
3'd5: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_bus_errors3_w;
end
3'd6: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_bus_errors2_w;
end
3'd7: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_bus_errors1_w;
end
4'd8: begin
csrbankarray_interface0_bank_bus_dat_r <= csrbankarray_csrbank0_bus_errors0_w;
end
endcase
end
if (csrbankarray_csrbank0_scratch3_re) begin
ctrl_storage[31:24] <= csrbankarray_csrbank0_scratch3_r;
end
if (csrbankarray_csrbank0_scratch2_re) begin
ctrl_storage[23:16] <= csrbankarray_csrbank0_scratch2_r;
end
if (csrbankarray_csrbank0_scratch1_re) begin
ctrl_storage[15:8] <= csrbankarray_csrbank0_scratch1_r;
end
if (csrbankarray_csrbank0_scratch0_re) begin
ctrl_storage[7:0] <= csrbankarray_csrbank0_scratch0_r;
end
ctrl_re <= csrbankarray_csrbank0_scratch0_re;
csrbankarray_sel_r <= csrbankarray_sel;
csrbankarray_interface1_bank_bus_dat_r <= 1'd0;
if (csrbankarray_csrbank1_sel) begin
case (csrbankarray_interface1_bank_bus_adr[4:0])
1'd0: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_load3_w;
end
1'd1: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_load2_w;
end
2'd2: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_load1_w;
end
2'd3: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_load0_w;
end
3'd4: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_reload3_w;
end
3'd5: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_reload2_w;
end
3'd6: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_reload1_w;
end
3'd7: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_reload0_w;
end
4'd8: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_en0_w;
end
4'd9: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_update_value0_w;
end
4'd10: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_value3_w;
end
4'd11: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_value2_w;
end
4'd12: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_value1_w;
end
4'd13: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_value0_w;
end
4'd14: begin
csrbankarray_interface1_bank_bus_dat_r <= timer0_eventmanager_status_w;
end
4'd15: begin
csrbankarray_interface1_bank_bus_dat_r <= timer0_eventmanager_pending_w;
end
5'd16: begin
csrbankarray_interface1_bank_bus_dat_r <= csrbankarray_csrbank1_ev_enable0_w;
end
endcase
end
if (csrbankarray_csrbank1_load3_re) begin
timer0_load_storage[31:24] <= csrbankarray_csrbank1_load3_r;
end
if (csrbankarray_csrbank1_load2_re) begin
timer0_load_storage[23:16] <= csrbankarray_csrbank1_load2_r;
end
if (csrbankarray_csrbank1_load1_re) begin
timer0_load_storage[15:8] <= csrbankarray_csrbank1_load1_r;
end
if (csrbankarray_csrbank1_load0_re) begin
timer0_load_storage[7:0] <= csrbankarray_csrbank1_load0_r;
end
timer0_load_re <= csrbankarray_csrbank1_load0_re;
if (csrbankarray_csrbank1_reload3_re) begin
timer0_reload_storage[31:24] <= csrbankarray_csrbank1_reload3_r;
end
if (csrbankarray_csrbank1_reload2_re) begin
timer0_reload_storage[23:16] <= csrbankarray_csrbank1_reload2_r;
end
if (csrbankarray_csrbank1_reload1_re) begin
timer0_reload_storage[15:8] <= csrbankarray_csrbank1_reload1_r;
end
if (csrbankarray_csrbank1_reload0_re) begin
timer0_reload_storage[7:0] <= csrbankarray_csrbank1_reload0_r;
end
timer0_reload_re <= csrbankarray_csrbank1_reload0_re;
if (csrbankarray_csrbank1_en0_re) begin
timer0_en_storage <= csrbankarray_csrbank1_en0_r;
end
timer0_en_re <= csrbankarray_csrbank1_en0_re;
if (csrbankarray_csrbank1_update_value0_re) begin
timer0_update_value_storage <= csrbankarray_csrbank1_update_value0_r;
end
timer0_update_value_re <= csrbankarray_csrbank1_update_value0_re;
if (csrbankarray_csrbank1_ev_enable0_re) begin
timer0_eventmanager_storage <= csrbankarray_csrbank1_ev_enable0_r;
end
timer0_eventmanager_re <= csrbankarray_csrbank1_ev_enable0_re;
csrbankarray_interface2_bank_bus_dat_r <= 1'd0;
if (csrbankarray_csrbank2_sel) begin
case (csrbankarray_interface2_bank_bus_adr[2:0])
1'd0: begin
csrbankarray_interface2_bank_bus_dat_r <= uart_rxtx_w;
end
1'd1: begin
csrbankarray_interface2_bank_bus_dat_r <= csrbankarray_csrbank2_txfull_w;
end
2'd2: begin
csrbankarray_interface2_bank_bus_dat_r <= csrbankarray_csrbank2_rxempty_w;
end
2'd3: begin
csrbankarray_interface2_bank_bus_dat_r <= uart_eventmanager_status_w;
end
3'd4: begin
csrbankarray_interface2_bank_bus_dat_r <= uart_eventmanager_pending_w;
end
3'd5: begin
csrbankarray_interface2_bank_bus_dat_r <= csrbankarray_csrbank2_ev_enable0_w;
end
endcase
end
if (csrbankarray_csrbank2_ev_enable0_re) begin
uart_eventmanager_storage[1:0] <= csrbankarray_csrbank2_ev_enable0_r;
end
uart_eventmanager_re <= csrbankarray_csrbank2_ev_enable0_re;
csrbankarray_interface3_bank_bus_dat_r <= 1'd0;
if (csrbankarray_csrbank3_sel) begin
case (csrbankarray_interface3_bank_bus_adr[1:0])
1'd0: begin
csrbankarray_interface3_bank_bus_dat_r <= csrbankarray_csrbank3_tuning_word3_w;
end
1'd1: begin
csrbankarray_interface3_bank_bus_dat_r <= csrbankarray_csrbank3_tuning_word2_w;
end
2'd2: begin
csrbankarray_interface3_bank_bus_dat_r <= csrbankarray_csrbank3_tuning_word1_w;
end
2'd3: begin
csrbankarray_interface3_bank_bus_dat_r <= csrbankarray_csrbank3_tuning_word0_w;
end
endcase
end
if (csrbankarray_csrbank3_tuning_word3_re) begin
uart_phy_storage[31:24] <= csrbankarray_csrbank3_tuning_word3_r;
end
if (csrbankarray_csrbank3_tuning_word2_re) begin
uart_phy_storage[23:16] <= csrbankarray_csrbank3_tuning_word2_r;
end
if (csrbankarray_csrbank3_tuning_word1_re) begin
uart_phy_storage[15:8] <= csrbankarray_csrbank3_tuning_word1_r;
end
if (csrbankarray_csrbank3_tuning_word0_re) begin
uart_phy_storage[7:0] <= csrbankarray_csrbank3_tuning_word0_r;
end
uart_phy_re <= csrbankarray_csrbank3_tuning_word0_re;
if (sys_rst) begin
ctrl_storage <= 32'd305419896;
ctrl_re <= 1'd0;
ctrl_bus_errors <= 32'd0;
rom_bus_ack <= 1'd0;
sram_bus_ack <= 1'd0;
serial_tx <= 1'd1;
uart_phy_storage <= 32'd4947802;
uart_phy_re <= 1'd0;
uart_phy_sink_ready <= 1'd0;
uart_phy_uart_clk_txen <= 1'd0;
uart_phy_phase_accumulator_tx <= 32'd0;
uart_phy_tx_reg <= 8'd0;
uart_phy_tx_bitcount <= 4'd0;
uart_phy_tx_busy <= 1'd0;
uart_phy_source_valid <= 1'd0;
uart_phy_source_payload_data <= 8'd0;
uart_phy_uart_clk_rxen <= 1'd0;
uart_phy_phase_accumulator_rx <= 32'd0;
uart_phy_rx_r <= 1'd0;
uart_phy_rx_reg <= 8'd0;
uart_phy_rx_bitcount <= 4'd0;
uart_phy_rx_busy <= 1'd0;
uart_tx_pending <= 1'd0;
uart_tx_old_trigger <= 1'd0;
uart_rx_pending <= 1'd0;
uart_rx_old_trigger <= 1'd0;
uart_eventmanager_storage <= 2'd0;
uart_eventmanager_re <= 1'd0;
uart_tx_fifo_readable <= 1'd0;
uart_tx_fifo_level0 <= 5'd0;
uart_tx_fifo_produce <= 4'd0;
uart_tx_fifo_consume <= 4'd0;
uart_rx_fifo_readable <= 1'd0;
uart_rx_fifo_level0 <= 5'd0;
uart_rx_fifo_produce <= 4'd0;
uart_rx_fifo_consume <= 4'd0;
timer0_load_storage <= 32'd0;
timer0_load_re <= 1'd0;
timer0_reload_storage <= 32'd0;
timer0_reload_re <= 1'd0;
timer0_en_storage <= 1'd0;
timer0_en_re <= 1'd0;
timer0_update_value_storage <= 1'd0;
timer0_update_value_re <= 1'd0;
timer0_value_status <= 32'd0;
timer0_zero_pending <= 1'd0;
timer0_zero_old_trigger <= 1'd0;
timer0_eventmanager_storage <= 1'd0;
timer0_eventmanager_re <= 1'd0;
timer0_value <= 32'd0;
state <= 1'd0;
grant <= 1'd0;
slave_sel_r <= 3'd0;
count <= 20'd1000000;
csrbankarray_interface0_bank_bus_dat_r <= 8'd0;
csrbankarray_sel_r <= 1'd0;
csrbankarray_interface1_bank_bus_dat_r <= 8'd0;
csrbankarray_interface2_bank_bus_dat_r <= 8'd0;
csrbankarray_interface3_bank_bus_dat_r <= 8'd0;
end
regs0 <= serial_rx;
regs1 <= regs0;
end
reg [31:0] mem[0:8191];
reg [31:0] memdat;
always @(posedge sys_clk) begin
memdat <= mem[rom_adr];
end
assign rom_dat_r = memdat;
initial begin
$readmemh("mem.init", mem);
end
reg [31:0] mem_1[0:8191];
reg [12:0] memadr;
always @(posedge sys_clk) begin
if (sram_we[0])
mem_1[sram_adr][7:0] <= sram_dat_w[7:0];
if (sram_we[1])
mem_1[sram_adr][15:8] <= sram_dat_w[15:8];
if (sram_we[2])
mem_1[sram_adr][23:16] <= sram_dat_w[23:16];
if (sram_we[3])
mem_1[sram_adr][31:24] <= sram_dat_w[31:24];
memadr <= sram_adr;
end
assign sram_dat_r = mem_1[memadr];
initial begin
$readmemh("mem_1.init", mem_1);
end
reg [9:0] storage[0:15];
reg [9:0] memdat_1;
reg [9:0] memdat_2;
always @(posedge sys_clk) begin
if (uart_tx_fifo_wrport_we)
storage[uart_tx_fifo_wrport_adr] <= uart_tx_fifo_wrport_dat_w;
memdat_1 <= storage[uart_tx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (uart_tx_fifo_rdport_re)
memdat_2 <= storage[uart_tx_fifo_rdport_adr];
end
assign uart_tx_fifo_wrport_dat_r = memdat_1;
assign uart_tx_fifo_rdport_dat_r = memdat_2;
reg [9:0] storage_1[0:15];
reg [9:0] memdat_3;
reg [9:0] memdat_4;
always @(posedge sys_clk) begin
if (uart_rx_fifo_wrport_we)
storage_1[uart_rx_fifo_wrport_adr] <= uart_rx_fifo_wrport_dat_w;
memdat_3 <= storage_1[uart_rx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (uart_rx_fifo_rdport_re)
memdat_4 <= storage_1[uart_rx_fifo_rdport_adr];
end
assign uart_rx_fifo_wrport_dat_r = memdat_3;
assign uart_rx_fifo_rdport_dat_r = memdat_4;
reg [7:0] mem_2[0:9];
reg [3:0] memadr_1;
always @(posedge sys_clk) begin
memadr_1 <= csrbankarray_adr;
end
assign csrbankarray_dat_r = mem_2[memadr_1];
initial begin
$readmemh("mem_2.init", mem_2);
end
BUFG BUFG_OUT(
.I(clkout),
.O(clkout_buf)
);
VexRiscv VexRiscv(
.clk(sys_clk),
.dBusWishbone_ACK(vexriscv_dbus_ack),
.dBusWishbone_DAT_MISO(vexriscv_dbus_dat_r),
.dBusWishbone_ERR(vexriscv_dbus_err),
.externalInterruptArray(vexriscv_interrupt),
.externalResetVector(1'd0),
.iBusWishbone_ACK(vexriscv_ibus_ack),
.iBusWishbone_DAT_MISO(vexriscv_ibus_dat_r),
.iBusWishbone_ERR(vexriscv_ibus_err),
.reset((sys_rst | vexriscv_reset)),
.softwareInterrupt(1'd0),
.timerInterrupt(1'd0),
.dBusWishbone_ADR(vexriscv_dbus_adr),
.dBusWishbone_BTE(vexriscv_dbus_bte),
.dBusWishbone_CTI(vexriscv_dbus_cti),
.dBusWishbone_CYC(vexriscv_dbus_cyc),
.dBusWishbone_DAT_MOSI(vexriscv_dbus_dat_w),
.dBusWishbone_SEL(vexriscv_dbus_sel),
.dBusWishbone_STB(vexriscv_dbus_stb),
.dBusWishbone_WE(vexriscv_dbus_we),
.iBusWishbone_ADR(vexriscv_ibus_adr),
.iBusWishbone_BTE(vexriscv_ibus_bte),
.iBusWishbone_CTI(vexriscv_ibus_cti),
.iBusWishbone_CYC(vexriscv_ibus_cyc),
.iBusWishbone_DAT_MOSI(vexriscv_ibus_dat_w),
.iBusWishbone_SEL(vexriscv_ibus_sel),
.iBusWishbone_STB(vexriscv_ibus_stb),
.iBusWishbone_WE(vexriscv_ibus_we)
);
BUFG BUFG_IN(
.I(clk100),
.O(clkin)
);
PLLE2_ADV #(
.CLKFBOUT_MULT(5'd16),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(5'd16),
.CLKOUT0_PHASE(1'd0),
.DIVCLK_DIVIDE(1'd1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(pll_fb),
.CLKIN1(clkin),
.CLKFBOUT(pll_fb),
.CLKOUT0(clkout),
.LOCKED(locked)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE (
.C(sys_clk),
.CE(1'd1),
.D(1'd0),
.PRE(xilinxasyncresetsynchronizerimpl),
.Q(xilinxasyncresetsynchronizerimpl_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_1 (
.C(sys_clk),
.CE(1'd1),
.D(xilinxasyncresetsynchronizerimpl_rst_meta),
.PRE(xilinxasyncresetsynchronizerimpl),
.Q(sys_rst)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level bank machine block. A structural block instantiating the configured
// individual bank machines, and a common block that computes various items shared
// by all bank machines.
`timescale 1ps/1ps
module mig_7series_v2_0_bank_mach #
(
parameter TCQ = 100,
parameter EVEN_CWL_2T_MODE = "OFF",
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter CL = 5,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter LOW_IDLE_CNT = 1,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCS_PER_RANK = 1,
parameter nOP_WAIT = 0,
parameter nRAS = 20,
parameter nRCD = 5,
parameter nRFC = 44,
parameter nRTP = 4,
parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal
parameter nRP = 10,
parameter nSLOTS = 2,
parameter nWR = 6,
parameter nXSDLL = 512,
parameter ORDERING = "NORM",
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010,
parameter tZQCS = 64
)
(/*AUTOARG*/
// Outputs
output accept, // From bank_common0 of bank_common.v
output accept_ns, // From bank_common0 of bank_common.v
output [BM_CNT_WIDTH-1:0] bank_mach_next, // From bank_common0 of bank_common.v
output [ROW_WIDTH-1:0] col_a, // From arb_mux0 of arb_mux.v
output [BANK_WIDTH-1:0] col_ba, // From arb_mux0 of arb_mux.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_mux0 of arb_mux.v
output col_periodic_rd, // From arb_mux0 of arb_mux.v
output [RANK_WIDTH-1:0] col_ra, // From arb_mux0 of arb_mux.v
output col_rmw, // From arb_mux0 of arb_mux.v
output col_rd_wr,
output [ROW_WIDTH-1:0] col_row, // From arb_mux0 of arb_mux.v
output col_size, // From arb_mux0 of arb_mux.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_mux0 of arb_mux.v
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [1:0] mc_odt,
output wire [nCK_PER_CLK-1:0] mc_cke,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output [5:0] mc_data_offset,
output [5:0] mc_data_offset_1,
output [5:0] mc_data_offset_2,
output [1:0] mc_cas_slot,
output insert_maint_r1, // From arb_mux0 of arb_mux.v
output maint_wip_r, // From bank_common0 of bank_common.v
output wire [nBANK_MACHS-1:0] sending_row,
output wire [nBANK_MACHS-1:0] sending_col,
output wire sent_col,
output wire sent_col_r,
output periodic_rd_ack_r,
output wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,
output wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r,
output wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,
output wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,
output idle,
// Inputs
input [BANK_WIDTH-1:0] bank, // To bank0 of bank_cntrl.v
input [6*RANKS-1:0] calib_rddata_offset,
input [6*RANKS-1:0] calib_rddata_offset_1,
input [6*RANKS-1:0] calib_rddata_offset_2,
input clk, // To bank0 of bank_cntrl.v, ...
input [2:0] cmd, // To bank0 of bank_cntrl.v, ...
input [COL_WIDTH-1:0] col, // To bank0 of bank_cntrl.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,// To bank0 of bank_cntrl.v
input init_calib_complete, // To bank_common0 of bank_common.v
input phy_rddata_valid, // To bank0 of bank_cntrl.v
input dq_busy_data, // To bank0 of bank_cntrl.v
input hi_priority, // To bank0 of bank_cntrl.v, ...
input [RANKS-1:0] inhbt_act_faw_r, // To bank0 of bank_cntrl.v
input [RANKS-1:0] inhbt_rd, // To bank0 of bank_cntrl.v
input [RANKS-1:0] inhbt_wr, // To bank0 of bank_cntrl.v
input [RANK_WIDTH-1:0] maint_rank_r, // To bank0 of bank_cntrl.v, ...
input maint_req_r, // To bank0 of bank_cntrl.v, ...
input maint_zq_r, // To bank0 of bank_cntrl.v, ...
input maint_sre_r, // To bank0 of bank_cntrl.v, ...
input maint_srx_r, // To bank0 of bank_cntrl.v, ...
input periodic_rd_r, // To bank_common0 of bank_common.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r, // To bank0 of bank_cntrl.v
input phy_mc_ctl_full,
input phy_mc_cmd_full,
input phy_mc_data_full,
input [RANK_WIDTH-1:0] rank, // To bank0 of bank_cntrl.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, // To bank0 of bank_cntrl.v
input rd_rmw, // To bank0 of bank_cntrl.v
input [ROW_WIDTH-1:0] row, // To bank0 of bank_cntrl.v
input rst, // To bank0 of bank_cntrl.v, ...
input size, // To bank0 of bank_cntrl.v
input [7:0] slot_0_present, // To bank_common0 of bank_common.v, ...
input [7:0] slot_1_present, // To bank_common0 of bank_common.v, ...
input use_addr
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam RANK_VECT_INDX = (nBANK_MACHS *RANK_WIDTH) - 1;
localparam BANK_VECT_INDX = (nBANK_MACHS * BANK_WIDTH) - 1;
localparam ROW_VECT_INDX = (nBANK_MACHS * ROW_WIDTH) - 1;
localparam DATA_BUF_ADDR_VECT_INDX = (nBANK_MACHS * DATA_BUF_ADDR_WIDTH) - 1;
localparam nRAS_CLKS = (nCK_PER_CLK == 1) ? nRAS : (nCK_PER_CLK == 2) ? ((nRAS/2) + (nRAS % 2)) : ((nRAS/4) + ((nRAS%4) ? 1 : 0));
localparam nWTP = CWL + ((BURST_MODE == "4") ? 2 : 4) + nWR;
// Unless 2T mode, add one to nWTP_CLKS for 2:1 mode. This accounts for loss of
// one DRAM CK due to column command to row command fixed offset. In 2T mode,
// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T
// mode, in which case we add 1 if the remainder exceeds the fixed offset.
localparam nWTP_CLKS = (nCK_PER_CLK == 1)
? nWTP :
(nCK_PER_CLK == 2)
? (nWTP/2) + ((ADDR_CMD_MODE == "2T") ? nWTP%2 : 1) :
(nWTP/4) + ((ADDR_CMD_MODE == "2T") ? (nWTP%4 > 2 ? 2 : 1) : 2);
localparam RAS_TIMER_WIDTH = clogb2(((nRAS_CLKS > nWTP_CLKS)
? nRAS_CLKS
: nWTP_CLKS) - 1);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire accept_internal_r; // From bank_common0 of bank_common.v
wire accept_req; // From bank_common0 of bank_common.v
wire adv_order_q; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v
wire insert_maint_r; // From bank_common0 of bank_common.v
wire low_idle_cnt_r; // From bank_common0 of bank_common.v
wire maint_idle; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v
wire periodic_rd_insert; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v
wire sent_row; // From arb_mux0 of arb_mux.v
wire was_priority; // From bank_common0 of bank_common.v
wire was_wr; // From bank_common0 of bank_common.v
// End of automatics
wire [RANK_WIDTH-1:0] rnk_config;
wire rnk_config_strobe;
wire rnk_config_kill_rts_col;
wire rnk_config_valid_r;
wire [nBANK_MACHS-1:0] rts_row;
wire [nBANK_MACHS-1:0] rts_col;
wire [nBANK_MACHS-1:0] rts_pre;
wire [nBANK_MACHS-1:0] col_rdy_wr;
wire [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] sending_pre;
wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r;
wire [nBANK_MACHS-1:0] req_size_r;
wire [RANK_VECT_INDX:0] req_rank_r;
wire [BANK_VECT_INDX:0] req_bank_r;
wire [ROW_VECT_INDX:0] req_row_r;
wire [ROW_VECT_INDX:0] col_addr;
wire [nBANK_MACHS-1:0] req_periodic_rd_r;
wire [nBANK_MACHS-1:0] req_wr_r;
wire [nBANK_MACHS-1:0] rd_wr_r;
wire [nBANK_MACHS-1:0] req_ras;
wire [nBANK_MACHS-1:0] req_cas;
wire [ROW_VECT_INDX:0] row_addr;
wire [nBANK_MACHS-1:0] row_cmd_wr;
wire [nBANK_MACHS-1:0] demand_priority;
wire [nBANK_MACHS-1:0] demand_act_priority;
wire [nBANK_MACHS-1:0] idle_ns;
wire [nBANK_MACHS-1:0] rb_hit_busy_r;
wire [nBANK_MACHS-1:0] bm_end;
wire [nBANK_MACHS-1:0] passing_open_bank;
wire [nBANK_MACHS-1:0] ordered_r;
wire [nBANK_MACHS-1:0] ordered_issued;
wire [nBANK_MACHS-1:0] rb_hit_busy_ns;
wire [nBANK_MACHS-1:0] maint_hit;
wire [nBANK_MACHS-1:0] idle_r;
wire [nBANK_MACHS-1:0] head_r;
wire [nBANK_MACHS-1:0] start_rcd;
wire [nBANK_MACHS-1:0] end_rtp;
wire [nBANK_MACHS-1:0] op_exit_req;
wire [nBANK_MACHS-1:0] op_exit_grant;
wire [nBANK_MACHS-1:0] start_pre_wait;
wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns;
genvar ID;
generate for (ID=0; ID<nBANK_MACHS; ID=ID+1) begin:bank_cntrl
mig_7series_v2_0_bank_cntrl #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRCD (nRCD),
.nRTP (nRTP),
.nRP (nRP),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank0
(.demand_priority (demand_priority[ID]),
.demand_priority_in ({2{demand_priority}}),
.demand_act_priority (demand_act_priority[ID]),
.demand_act_priority_in ({2{demand_act_priority}}),
.rts_row (rts_row[ID]),
.rts_col (rts_col[ID]),
.rts_pre (rts_pre[ID]),
.col_rdy_wr (col_rdy_wr[ID]),
.rtc (rtc[ID]),
.sending_row (sending_row[ID]),
.sending_pre (sending_pre[ID]),
.sending_col (sending_col[ID]),
.req_data_buf_addr_r (req_data_buf_addr_r[(ID*DATA_BUF_ADDR_WIDTH)+:DATA_BUF_ADDR_WIDTH]),
.req_size_r (req_size_r[ID]),
.req_rank_r (req_rank_r[(ID*RANK_WIDTH)+:RANK_WIDTH]),
.req_bank_r (req_bank_r[(ID*BANK_WIDTH)+:BANK_WIDTH]),
.req_row_r (req_row_r[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.col_addr (col_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.req_wr_r (req_wr_r[ID]),
.rd_wr_r (rd_wr_r[ID]),
.req_periodic_rd_r (req_periodic_rd_r[ID]),
.req_ras (req_ras[ID]),
.req_cas (req_cas[ID]),
.row_addr (row_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.row_cmd_wr (row_cmd_wr[ID]),
.act_this_rank_r (act_this_rank_r[(ID*RANKS)+:RANKS]),
.wr_this_rank_r (wr_this_rank_r[(ID*RANKS)+:RANKS]),
.rd_this_rank_r (rd_this_rank_r[(ID*RANKS)+:RANKS]),
.idle_ns (idle_ns[ID]),
.rb_hit_busy_r (rb_hit_busy_r[ID]),
.bm_end (bm_end[ID]),
.bm_end_in ({2{bm_end}}),
.passing_open_bank (passing_open_bank[ID]),
.passing_open_bank_in ({2{passing_open_bank}}),
.ordered_r (ordered_r[ID]),
.ordered_issued (ordered_issued[ID]),
.rb_hit_busy_ns (rb_hit_busy_ns[ID]),
.rb_hit_busy_ns_in ({2{rb_hit_busy_ns}}),
.maint_hit (maint_hit[ID]),
.req_rank_r_in ({2{req_rank_r}}),
.idle_r (idle_r[ID]),
.head_r (head_r[ID]),
.start_rcd (start_rcd[ID]),
.start_rcd_in ({2{start_rcd}}),
.end_rtp (end_rtp[ID]),
.op_exit_req (op_exit_req[ID]),
.op_exit_grant (op_exit_grant[ID]),
.start_pre_wait (start_pre_wait[ID]),
.ras_timer_ns (ras_timer_ns[(ID*RAS_TIMER_WIDTH)+:RAS_TIMER_WIDTH]),
.ras_timer_ns_in ({2{ras_timer_ns}}),
.rank_busy_r (rank_busy_r[ID*RANKS+:RANKS]),
/*AUTOINST*/
// Inputs
.accept_internal_r (accept_internal_r),
.accept_req (accept_req),
.adv_order_q (adv_order_q),
.bank (bank[BANK_WIDTH-1:0]),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.dq_busy_data (dq_busy_data),
.hi_priority (hi_priority),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.low_idle_cnt_r (low_idle_cnt_r),
.maint_idle (maint_idle),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r),
.periodic_rd_insert (periodic_rd_insert),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rank (rank[RANK_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_rmw (rd_rmw),
.row (row[ROW_WIDTH-1:0]),
.rst (rst),
.sent_col (sent_col),
.sent_row (sent_row),
.size (size),
.use_addr (use_addr),
.was_priority (was_priority),
.was_wr (was_wr));
end
endgenerate
mig_7series_v2_0_bank_common #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.LOW_IDLE_CNT (LOW_IDLE_CNT),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRFC (nRFC),
.nXSDLL (nXSDLL),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.CWL (CWL),
.tZQCS (tZQCS))
bank_common0
(.op_exit_grant (op_exit_grant[nBANK_MACHS-1:0]),
/*AUTOINST*/
// Outputs
.accept_internal_r (accept_internal_r),
.accept_ns (accept_ns),
.accept (accept),
.periodic_rd_insert (periodic_rd_insert),
.periodic_rd_ack_r (periodic_rd_ack_r),
.accept_req (accept_req),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.idle (idle),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.adv_order_q (adv_order_q),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.low_idle_cnt_r (low_idle_cnt_r),
.was_wr (was_wr),
.was_priority (was_priority),
.maint_wip_r (maint_wip_r),
.maint_idle (maint_idle),
.insert_maint_r (insert_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.idle_ns (idle_ns[nBANK_MACHS-1:0]),
.init_calib_complete (init_calib_complete),
.periodic_rd_r (periodic_rd_r),
.use_addr (use_addr),
.rb_hit_busy_r (rb_hit_busy_r[nBANK_MACHS-1:0]),
.idle_r (idle_r[nBANK_MACHS-1:0]),
.ordered_r (ordered_r[nBANK_MACHS-1:0]),
.ordered_issued (ordered_issued[nBANK_MACHS-1:0]),
.head_r (head_r[nBANK_MACHS-1:0]),
.end_rtp (end_rtp[nBANK_MACHS-1:0]),
.passing_open_bank (passing_open_bank[nBANK_MACHS-1:0]),
.op_exit_req (op_exit_req[nBANK_MACHS-1:0]),
.start_pre_wait (start_pre_wait[nBANK_MACHS-1:0]),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_hit (maint_hit[nBANK_MACHS-1:0]),
.bm_end (bm_end[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]));
mig_7series_v2_0_arb_mux #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_VECT_INDX (BANK_VECT_INDX),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.CS_WIDTH (CS_WIDTH),
.CL (CL),
.CWL (CWL),
.DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.nRAS (nRAS),
.nRCD (nRCD),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nSLOTS (nSLOTS),
.nWR (nWR),
.RANKS (RANKS),
.RANK_VECT_INDX (RANK_VECT_INDX),
.RANK_WIDTH (RANK_WIDTH),
.ROW_VECT_INDX (ROW_VECT_INDX),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG))
arb_mux0
(.rts_col (rts_col[nBANK_MACHS-1:0]), // AUTOs wants to make this an input.
/*AUTOINST*/
// Outputs
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank),
.mc_address (mc_address),
.mc_ras_n (mc_ras_n),
.mc_cas_n (mc_cas_n),
.mc_we_n (mc_we_n),
.mc_cs_n (mc_cs_n),
.mc_odt (mc_odt),
.mc_cke (mc_cke),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_cmd (mc_cmd),
.mc_data_offset (mc_data_offset),
.mc_data_offset_1 (mc_data_offset_1),
.mc_data_offset_2 (mc_data_offset_2),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_valid_r (rnk_config_valid_r),
.mc_cas_slot (mc_cas_slot),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_pre (sending_pre[nBANK_MACHS-1:0]),
.sent_col (sent_col),
.sent_col_r (sent_col_r),
.sent_row (sent_row),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.insert_maint_r1 (insert_maint_r1),
// Inputs
.init_calib_complete (init_calib_complete),
.calib_rddata_offset (calib_rddata_offset),
.calib_rddata_offset_1 (calib_rddata_offset_1),
.calib_rddata_offset_2 (calib_rddata_offset_2),
.col_addr (col_addr[ROW_VECT_INDX:0]),
.col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]),
.insert_maint_r (insert_maint_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
.req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
.req_cas (req_cas[nBANK_MACHS-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
.req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
.req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
.req_ras (req_ras[nBANK_MACHS-1:0]),
.req_row_r (req_row_r[ROW_VECT_INDX:0]),
.req_size_r (req_size_r[nBANK_MACHS-1:0]),
.req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
.row_addr (row_addr[ROW_VECT_INDX:0]),
.row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
.rts_row (rts_row[nBANK_MACHS-1:0]),
.rtc (rtc[nBANK_MACHS-1:0]),
.rts_pre (rts_pre[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.clk (clk),
.rst (rst));
endmodule // bank_mach
|
/*
* plle2_base_tb.v: Testbench for plle2_base.v
* author: Till Mahlburg
* year: 2019-2020
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
`ifndef WAIT_INTERVAL
`define WAIT_INTERVAL 1000
`endif
/* define all attributes as macros, so different combinations can be tested
* more easily.
* By default these are the given default values of the part.
*/
/* not implemented */
`ifndef BANDWIDTH
`define BANDWIDTH "OPTIMIZED"
`endif
`ifndef CLKFBOUT_MULT
`define CLKFBOUT_MULT 5
`endif
`ifndef CLKFBOUT_PHASE
`define CLKFBOUT_PHASE 0.000
`endif
/* This deviates from the default values, because it is required to be set */
`ifndef CLKIN1_PERIOD
`define CLKIN1_PERIOD 5.000
`endif
`ifndef CLKOUT0_DIVIDE
`define CLKOUT0_DIVIDE 1
`endif
`ifndef CLKOUT1_DIVIDE
`define CLKOUT1_DIVIDE 1
`endif
`ifndef CLKOUT2_DIVIDE
`define CLKOUT2_DIVIDE 1
`endif
`ifndef CLKOUT2_DIVIDE
`define CLKOUT2_DIVIDE 1
`endif
`ifndef CLKOUT3_DIVIDE
`define CLKOUT3_DIVIDE 1
`endif
`ifndef CLKOUT4_DIVIDE
`define CLKOUT4_DIVIDE 1
`endif
`ifndef CLKOUT5_DIVIDE
`define CLKOUT5_DIVIDE 1
`endif
`ifndef CLKOUT0_DUTY_CYCLE
`define CLKOUT0_DUTY_CYCLE 0.500
`endif
`ifndef CLKOUT1_DUTY_CYCLE
`define CLKOUT1_DUTY_CYCLE 0.500
`endif
`ifndef CLKOUT2_DUTY_CYCLE
`define CLKOUT2_DUTY_CYCLE 0.500
`endif
`ifndef CLKOUT3_DUTY_CYCLE
`define CLKOUT3_DUTY_CYCLE 0.500
`endif
`ifndef CLKOUT4_DUTY_CYCLE
`define CLKOUT4_DUTY_CYCLE 0.500
`endif
`ifndef CLKOUT5_DUTY_CYCLE
`define CLKOUT5_DUTY_CYCLE 0.500
`endif
`ifndef CLKOUT0_PHASE
`define CLKOUT0_PHASE 0.000
`endif
`ifndef CLKOUT1_PHASE
`define CLKOUT1_PHASE 0.000
`endif
`ifndef CLKOUT2_PHASE
`define CLKOUT2_PHASE 0.000
`endif
`ifndef CLKOUT3_PHASE
`define CLKOUT3_PHASE 0.000
`endif
`ifndef CLKOUT4_PHASE
`define CLKOUT4_PHASE 0.000
`endif
`ifndef CLKOUT5_PHASE
`define CLKOUT5_PHASE 0.000
`endif
`ifndef DIVCLK_DIVIDE
`define DIVCLK_DIVIDE 1
`endif
/* not implemented */
`ifndef REF_JITTER1
`define REF_JITTER1 0.010
`endif
/* not implemented */
`ifndef STARTUP_WAIT
`define STARTUP_WAIT "FALSE"
`endif
module PLLE2_BASE_tb();
wire CLKOUT[0:5];
wire CLKFBOUT;
wire LOCKED;
reg CLKIN1;
reg PWRDWN;
reg RST;
wire CLKFBIN;
integer pass_count;
integer fail_count;
/* change according to the number of test cases */
localparam total = 23;
reg reset;
wire [31:0] period_1000[0:5];
wire [31:0] period_1000_fb;
wire dcc_fail[0:5];
wire dcc_fail_fb;
wire psc_fail[0:5];
wire psc_fail_fb;
wire [31:0] CLKOUT_DIVIDE[0:5];
assign CLKOUT_DIVIDE[0] = `CLKOUT0_DIVIDE;
assign CLKOUT_DIVIDE[1] = `CLKOUT1_DIVIDE;
assign CLKOUT_DIVIDE[2] = `CLKOUT2_DIVIDE;
assign CLKOUT_DIVIDE[3] = `CLKOUT3_DIVIDE;
assign CLKOUT_DIVIDE[4] = `CLKOUT4_DIVIDE;
assign CLKOUT_DIVIDE[5] = `CLKOUT5_DIVIDE;
wire [31:0] CLKOUT_DUTY_CYCLE_1000[0:5];
assign CLKOUT_DUTY_CYCLE_1000[0] = (`CLKOUT0_DUTY_CYCLE * 1000);
assign CLKOUT_DUTY_CYCLE_1000[1] = (`CLKOUT1_DUTY_CYCLE * 1000);
assign CLKOUT_DUTY_CYCLE_1000[2] = (`CLKOUT2_DUTY_CYCLE * 1000);
assign CLKOUT_DUTY_CYCLE_1000[3] = (`CLKOUT3_DUTY_CYCLE * 1000);
assign CLKOUT_DUTY_CYCLE_1000[4] = (`CLKOUT4_DUTY_CYCLE * 1000);
assign CLKOUT_DUTY_CYCLE_1000[5] = (`CLKOUT5_DUTY_CYCLE * 1000);
wire [31:0] CLKOUT_PHASE_1000[0:5];
assign CLKOUT_PHASE_1000[0] = (`CLKOUT0_PHASE * 1000);
assign CLKOUT_PHASE_1000[1] = (`CLKOUT1_PHASE * 1000);
assign CLKOUT_PHASE_1000[2] = (`CLKOUT2_PHASE * 1000);
assign CLKOUT_PHASE_1000[3] = (`CLKOUT3_PHASE * 1000);
assign CLKOUT_PHASE_1000[4] = (`CLKOUT4_PHASE * 1000);
assign CLKOUT_PHASE_1000[5] = (`CLKOUT5_PHASE * 1000);
/* instantiate PLLE2_BASE with default values for all the attributes */
PLLE2_BASE #(
.BANDWIDTH(`BANDWIDTH),
.CLKFBOUT_MULT(`CLKFBOUT_MULT),
.CLKFBOUT_PHASE(`CLKFBOUT_PHASE),
.CLKIN1_PERIOD(`CLKIN1_PERIOD),
.CLKOUT0_DIVIDE(`CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE(`CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE(`CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE(`CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE(`CLKOUT4_DIVIDE),
.CLKOUT5_DIVIDE(`CLKOUT5_DIVIDE),
.CLKOUT0_DUTY_CYCLE(`CLKOUT0_DUTY_CYCLE),
.CLKOUT1_DUTY_CYCLE(`CLKOUT1_DUTY_CYCLE),
.CLKOUT2_DUTY_CYCLE(`CLKOUT2_DUTY_CYCLE),
.CLKOUT3_DUTY_CYCLE(`CLKOUT3_DUTY_CYCLE),
.CLKOUT4_DUTY_CYCLE(`CLKOUT4_DUTY_CYCLE),
.CLKOUT5_DUTY_CYCLE(`CLKOUT5_DUTY_CYCLE),
.CLKOUT0_PHASE(`CLKOUT0_PHASE),
.CLKOUT1_PHASE(`CLKOUT1_PHASE),
.CLKOUT2_PHASE(`CLKOUT2_PHASE),
.CLKOUT3_PHASE(`CLKOUT3_PHASE),
.CLKOUT4_PHASE(`CLKOUT4_PHASE),
.CLKOUT5_PHASE(`CLKOUT5_PHASE),
.DIVCLK_DIVIDE(`DIVCLK_DIVIDE),
.REF_JITTER1(`REF_JITTER1),
.STARTUP_WAIT(`STARTUP_WAIT))
dut (
.CLKOUT0(CLKOUT[0]),
.CLKOUT1(CLKOUT[1]),
.CLKOUT2(CLKOUT[2]),
.CLKOUT3(CLKOUT[3]),
.CLKOUT4(CLKOUT[4]),
.CLKOUT5(CLKOUT[5]),
.CLKFBOUT(CLKFBOUT),
.LOCKED(LOCKED),
.CLKIN1(CLKIN1),
.PWRDWN(PWRDWN),
.RST(RST),
.CLKFBIN(CLKFBIN)
);
genvar i;
generate
for (i = 0; i <= 5; i = i + 1) begin : period_count
period_count period_count (
.RST(reset),
.clk(CLKOUT[i]),
.period_length_1000(period_1000[i]));
end
for (i = 0; i <= 5; i = i + 1) begin : dcc
duty_cycle_check dcc (
.desired_duty_cycle_1000(CLKOUT_DUTY_CYCLE_1000[i]),
.clk_period_1000((`CLKIN1_PERIOD * ((`DIVCLK_DIVIDE * CLKOUT_DIVIDE[i]) / `CLKFBOUT_MULT)) * 1000),
.clk(CLKOUT[i]),
.reset(reset),
.LOCKED(LOCKED),
.fail(dcc_fail[i]));
end
for (i = 0; i <= 5; i = i + 1) begin : psc
phase_shift_check psc (
.desired_shift_1000(CLKOUT_PHASE_1000[i]),
.clk_period_1000(1000 * `CLKIN1_PERIOD * ((`DIVCLK_DIVIDE * CLKOUT_DIVIDE[i]) / `CLKFBOUT_MULT)),
.clk_shifted(CLKOUT[i]),
.clk(CLKFBOUT),
.rst(RST),
.LOCKED(LOCKED),
.fail(psc_fail[i]));
end
endgenerate
period_count period_count_fb (
.RST(reset),
.clk(CLKFBOUT),
.period_length_1000(period_1000_fb));
phase_shift_check pscfb (
.desired_shift_1000(`CLKFBOUT_PHASE * 1000),
.clk_period_1000(`CLKIN1_PERIOD * (`DIVCLK_DIVIDE / `CLKFBOUT_MULT) * 1000),
.clk_shifted(CLKFBOUT),
.clk(CLKIN1),
.rst(RST),
.LOCKED(LOCKED),
.fail(psc_fail_fb));
/* ------------ BEGIN TEST CASES ------------- */
/* default loop variable */
integer k;
initial begin
$dumpfile("plle2_base_tb.vcd");
$dumpvars(0, PLLE2_BASE_tb);
pass_count = 0;
fail_count = 0;
reset = 0;
CLKIN1 = 0;
RST = 0;
PWRDWN = 0;
#10;
reset = 1;
RST = 1;
#10;
if ((CLKOUT[0] & CLKOUT[1] & CLKOUT[2] & CLKOUT[3] & CLKOUT[4] & CLKOUT[5] & CLKFBOUT & LOCKED) == 0) begin
$display("PASSED: RST signal");
pass_count = pass_count + 1;
end else begin
$display("FAILED: RST signal");
fail_count = fail_count + 1;
end
reset = 0;
RST = 0;
/* Test for correct number of highs for the given parameters.
* This is down for all six outputs and the feedback output.
*/
#`WAIT_INTERVAL;
if (LOCKED === 1'b1) begin
$display("PASSED: LOCKED");
pass_count = pass_count + 1;
end else begin
$display("FAILED: LOCKED");
fail_count = fail_count + 1;
end
/*------- FREQUENCY ---------*/
for (k = 0; k <= 5; k = k + 1) begin
if ((period_1000[k] / 1000.0 == `CLKIN1_PERIOD * ((`DIVCLK_DIVIDE * CLKOUT_DIVIDE[k] * 1.0) / `CLKFBOUT_MULT))) begin
$display("PASSED: CLKOUT%0d frequency", k);
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT%0d frequency", k);
fail_count = fail_count + 1;
end
end
if ((period_1000_fb / 1000.0) == (`CLKIN1_PERIOD * ((`DIVCLK_DIVIDE * 1.0) / `CLKFBOUT_MULT))) begin
$display("PASSED: CLKFBOUT frequency");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKFBOUT frequency");
fail_count = fail_count + 1;
end
/*------- DUTY CYCLE ---------*/
for (k = 0; k <= 5; k = k + 1) begin
if (dcc_fail[k] !== 1'b1) begin
$display("PASSED: CLKOUT%0d duty cycle", k);
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT%0d duty cycle", k);
fail_count = fail_count + 1;
end
end
/*------- PHASE SHIFT ---------*/
for (k = 0; k <= 5; k = k + 1) begin
if (psc_fail[k] !== 1'b1) begin
$display("PASSED: CLKOUT%0d phase shift", k);
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT%0d phase shift", k);
fail_count = fail_count + 1;
end
end
if (psc_fail_fb !== 1'b1) begin
$display("PASSED: CLKOUTFB phase shift");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUTFB phase shift");
fail_count = fail_count + 1;
end
PWRDWN = 1;
#100;
if ((CLKOUT[0] & CLKOUT[1] & CLKOUT[2] & CLKOUT[3] & CLKOUT[4] & CLKOUT[5] & CLKFBOUT) === 1'bx) begin
$display("PASSED: PWRDWN");
pass_count = pass_count + 1;
end else begin
$display("FAILED: PWRDWN");
fail_count = fail_count + 1;
end
if ((pass_count + fail_count) == total) begin
$display("PASSED: number of test cases");
pass_count = pass_count + 1;
end else begin
$display("FAILED: number of test cases");
fail_count = fail_count + 1;
end
$display("%0d/%0d PASSED", pass_count, (total + 1));
$finish;
end
/* connect CLKFBIN with CLKFBOUT to use internal feedback */
assign CLKFBIN = CLKFBOUT;
always #(`CLKIN1_PERIOD / 2) CLKIN1 = ~CLKIN1;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD1_FUNCTIONAL_PP_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD1_FUNCTIONAL_PP_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Sep 19 14:35:07 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
endmodule
|
// nios_solo_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_solo_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [31:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [29:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
nios_solo_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
// megafunction wizard: %ALT2GXB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt2gxb
// ============================================================
// File Name: altera_tse_alt2gxb_gige_wo_rmfifo.v
// Megafunction Name(s):
// alt2gxb
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Internal Build 138 03/15/2011 PN Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_alt2gxb_gige_wo_rmfifo (
cal_blk_clk,
gxb_powerdown,
pll_inclk,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_seriallpbken,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
pll_locked,
reconfig_fromgxb,
rx_clkout,
rx_ctrldetect,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_freqlocked,
rx_patterndetect,
rx_recovclkout,
rx_rlv,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_syncstatus,
tx_clkout,
tx_dataout);
input cal_blk_clk;
input [0:0] gxb_powerdown;
input pll_inclk;
input reconfig_clk;
input [2:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [0:0] rx_cruclk;
input [0:0] rx_datain;
input [0:0] rx_digitalreset;
input [0:0] rx_seriallpbken;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
input [0:0] tx_digitalreset;
output [0:0] pll_locked;
output [0:0] reconfig_fromgxb;
output rx_clkout;
output [0:0] rx_ctrldetect;
output [7:0] rx_dataout;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_freqlocked;
output [0:0] rx_patterndetect;
output [0:0] rx_recovclkout;
output [0:0] rx_rlv;
output [0:0] rx_rmfifodatadeleted;
output [0:0] rx_rmfifodatainserted;
output [0:0] rx_runningdisp;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
output [0:0] tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
// Please this parameter and the section that use it when this module is regenerated
parameter ENABLE_ALT_RECONFIG = 1;
wire [0:0] sub_wire0;
wire [0:0] sub_wire1;
wire [0:0] sub_wire2;
wire [0:0] sub_wire3;
wire [0:0] sub_wire4;
wire [0:0] sub_wire5;
wire [0:0] sub_wire6;
wire [0:0] sub_wire7;
wire sub_wire8;
wire [7:0] sub_wire9;
wire [0:0] sub_wire10;
wire [0:0] sub_wire11;
wire [0:0] sub_wire12;
wire [0:0] sub_wire13;
wire [0:0] sub_wire14;
wire [0:0] sub_wire15;
wire [0:0] sub_wire16;
wire [0:0] rx_patterndetect = sub_wire0[0:0];
wire [0:0] pll_locked = sub_wire1[0:0];
wire [0:0] reconfig_fromgxb = sub_wire2[0:0];
wire [0:0] rx_freqlocked = sub_wire3[0:0];
wire [0:0] rx_disperr = sub_wire4[0:0];
wire [0:0] rx_recovclkout = sub_wire5[0:0];
wire [0:0] rx_runningdisp = sub_wire6[0:0];
wire [0:0] rx_syncstatus = sub_wire7[0:0];
wire rx_clkout = sub_wire8;
wire [7:0] rx_dataout = sub_wire9[7:0];
wire [0:0] rx_errdetect = sub_wire10[0:0];
wire [0:0] rx_rmfifodatainserted = sub_wire11[0:0];
wire [0:0] rx_rlv = sub_wire12[0:0];
wire [0:0] rx_rmfifodatadeleted = sub_wire13[0:0];
wire [0:0] tx_clkout = sub_wire14[0:0];
wire [0:0] tx_dataout = sub_wire15[0:0];
wire [0:0] rx_ctrldetect = sub_wire16[0:0];
alt2gxb alt2gxb_component (
.pll_inclk (pll_inclk),
.reconfig_togxb (reconfig_togxb),
.cal_blk_clk (cal_blk_clk),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.tx_datain (tx_datain),
.tx_digitalreset (tx_digitalreset),
.gxb_powerdown (gxb_powerdown),
.rx_cruclk (rx_cruclk),
.rx_seriallpbken (rx_seriallpbken),
.reconfig_clk (reconfig_clk),
.rx_analogreset (rx_analogreset),
.tx_ctrlenable (tx_ctrlenable),
.rx_patterndetect (sub_wire0),
.pll_locked (sub_wire1),
.reconfig_fromgxb (sub_wire2),
.rx_freqlocked (sub_wire3),
.rx_disperr (sub_wire4),
.rx_recovclkout (sub_wire5),
.rx_runningdisp (sub_wire6),
.rx_syncstatus (sub_wire7),
.rx_clkout (sub_wire8),
.rx_dataout (sub_wire9),
.rx_errdetect (sub_wire10),
.rx_rmfifodatainserted (sub_wire11),
.rx_rlv (sub_wire12),
.rx_rmfifodatadeleted (sub_wire13),
.tx_clkout (sub_wire14),
.tx_dataout (sub_wire15),
.rx_ctrldetect (sub_wire16)
// synopsys translate_off
,
.aeq_fromgxb (),
.aeq_togxb (),
.cal_blk_calibrationstatus (),
.cal_blk_powerdown (),
.coreclkout (),
.debug_rx_phase_comp_fifo_error (),
.debug_tx_phase_comp_fifo_error (),
.fixedclk (),
.gxb_enable (),
.pipe8b10binvpolarity (),
.pipedatavalid (),
.pipeelecidle (),
.pipephydonestatus (),
.pipestatus (),
.pll_inclk_alt (),
.pll_inclk_rx_cruclk (),
.pll_locked_alt (),
.powerdn (),
.reconfig_fromgxb_oe (),
.rx_a1a2size (),
.rx_a1a2sizeout (),
.rx_a1detect (),
.rx_a2detect (),
.rx_bistdone (),
.rx_bisterr (),
.rx_bitslip (),
.rx_byteorderalignstatus (),
.rx_channelaligned (),
.rx_coreclk (),
.rx_cruclk_alt (),
.rx_dataoutfull (),
.rx_enabyteord (),
.rx_enapatternalign (),
.rx_invpolarity (),
.rx_k1detect (),
.rx_k2detect (),
.rx_locktodata (),
.rx_locktorefclk (),
.rx_phfifooverflow (),
.rx_phfifordenable (),
.rx_phfiforeset (),
.rx_phfifounderflow (),
.rx_phfifowrdisable (),
.rx_pll_locked (),
.rx_powerdown (),
.rx_revbitorderwa (),
.rx_revbyteorderwa (),
.rx_rmfifoalmostempty (),
.rx_rmfifoalmostfull (),
.rx_rmfifoempty (),
.rx_rmfifofull (),
.rx_rmfifordena (),
.rx_rmfiforeset (),
.rx_rmfifowrena (),
.rx_signaldetect (),
.tx_coreclk (),
.tx_datainfull (),
.tx_detectrxloop (),
.tx_dispval (),
.tx_forcedisp (),
.tx_forcedispcompliance (),
.tx_forceelecidle (),
.tx_invpolarity (),
.tx_phfifooverflow (),
.tx_phfiforeset (),
.tx_phfifounderflow (),
.tx_revparallellpbken ()
// synopsys translate_on
);
defparam
alt2gxb_component.starting_channel_number = starting_channel_number,
alt2gxb_component.cmu_pll_inclock_period = 8000,
alt2gxb_component.cmu_pll_loop_filter_resistor_control = 3,
alt2gxb_component.digitalreset_port_width = 1,
alt2gxb_component.en_local_clk_div_ctrl = "true",
alt2gxb_component.equalizer_ctrl_a_setting = 0,
alt2gxb_component.equalizer_ctrl_b_setting = 0,
alt2gxb_component.equalizer_ctrl_c_setting = 0,
alt2gxb_component.equalizer_ctrl_d_setting = 0,
alt2gxb_component.equalizer_ctrl_v_setting = 0,
alt2gxb_component.equalizer_dcgain_setting = 0,
alt2gxb_component.gen_reconfig_pll = "false",
alt2gxb_component.intended_device_family = "Stratix II GX",
alt2gxb_component.loopback_mode = "slb",
alt2gxb_component.lpm_type = "alt2gxb",
alt2gxb_component.number_of_channels = 1,
alt2gxb_component.operation_mode = "duplex",
alt2gxb_component.pll_legal_multiplier_list = "disable_4_5_mult_above_3125",
alt2gxb_component.preemphasis_ctrl_1stposttap_setting = 0,
alt2gxb_component.preemphasis_ctrl_2ndposttap_inv_setting = "false",
alt2gxb_component.preemphasis_ctrl_2ndposttap_setting = 0,
alt2gxb_component.preemphasis_ctrl_pretap_inv_setting = "false",
alt2gxb_component.preemphasis_ctrl_pretap_setting = 0,
alt2gxb_component.protocol = "gige",
alt2gxb_component.receiver_termination = "oct_100_ohms",
alt2gxb_component.reconfig_dprio_mode = ENABLE_ALT_RECONFIG,
alt2gxb_component.reverse_loopback_mode = "none",
alt2gxb_component.rx_8b_10b_compatibility_mode = "true",
alt2gxb_component.rx_8b_10b_mode = "normal",
alt2gxb_component.rx_align_pattern = "0101111100",
alt2gxb_component.rx_align_pattern_length = 10,
alt2gxb_component.rx_allow_align_polarity_inversion = "false",
alt2gxb_component.rx_allow_pipe_polarity_inversion = "false",
alt2gxb_component.rx_bandwidth_mode = 1,
alt2gxb_component.rx_bitslip_enable = "false",
alt2gxb_component.rx_byte_ordering_mode = "none",
alt2gxb_component.rx_channel_width = 8,
alt2gxb_component.rx_common_mode = "0.9v",
alt2gxb_component.rx_cru_inclock_period = 8000,
alt2gxb_component.rx_cru_pre_divide_by = 1,
alt2gxb_component.rx_datapath_protocol = "basic",
alt2gxb_component.rx_data_rate = 1250,
alt2gxb_component.rx_data_rate_remainder = 0,
alt2gxb_component.rx_disable_auto_idle_insertion = "true",
alt2gxb_component.rx_enable_bit_reversal = "false",
alt2gxb_component.rx_enable_lock_to_data_sig = "false",
alt2gxb_component.rx_enable_lock_to_refclk_sig = "false",
alt2gxb_component.rx_enable_self_test_mode = "false",
alt2gxb_component.rx_enable_true_complement_match_in_word_align = "false",
alt2gxb_component.rx_force_signal_detect = "true",
alt2gxb_component.rx_ppmselect = 32,
alt2gxb_component.rx_rate_match_back_to_back = "true",
alt2gxb_component.rx_rate_match_fifo_mode = "normal",
alt2gxb_component.rx_rate_match_fifo_mode_manual_control = "none",
alt2gxb_component.rx_rate_match_ordered_set_based = "true",
alt2gxb_component.rx_rate_match_pattern1 = "10100010010101111100",
alt2gxb_component.rx_rate_match_pattern2 = "10101011011010000011",
alt2gxb_component.rx_rate_match_pattern_size = 20,
alt2gxb_component.rx_rate_match_skip_set_based = "true",
alt2gxb_component.rx_run_length = 5,
alt2gxb_component.rx_run_length_enable = "true",
alt2gxb_component.rx_signal_detect_threshold = 2,
alt2gxb_component.rx_use_align_state_machine = "true",
alt2gxb_component.rx_use_clkout = "true",
alt2gxb_component.rx_use_coreclk = "false",
alt2gxb_component.rx_use_cruclk = "true",
alt2gxb_component.rx_use_deserializer_double_data_mode = "false",
alt2gxb_component.rx_use_deskew_fifo = "false",
alt2gxb_component.rx_use_double_data_mode = "false",
alt2gxb_component.rx_use_rate_match_pattern1_only = "false",
alt2gxb_component.transmitter_termination = "oct_100_ohms",
alt2gxb_component.tx_8b_10b_compatibility_mode = "true",
alt2gxb_component.tx_8b_10b_mode = "normal",
alt2gxb_component.tx_allow_polarity_inversion = "false",
alt2gxb_component.tx_analog_power = "1.5v",
alt2gxb_component.tx_channel_width = 8,
alt2gxb_component.tx_common_mode = "0.6v",
alt2gxb_component.tx_data_rate = 1250,
alt2gxb_component.tx_data_rate_remainder = 0,
alt2gxb_component.tx_enable_bit_reversal = "false",
alt2gxb_component.tx_enable_idle_selection = "true",
alt2gxb_component.tx_enable_self_test_mode = "false",
alt2gxb_component.tx_refclk_divide_by = 1,
alt2gxb_component.tx_transmit_protocol = "basic",
alt2gxb_component.tx_use_coreclk = "false",
alt2gxb_component.tx_use_double_data_mode = "false",
alt2gxb_component.tx_use_serializer_double_data_mode = "false",
alt2gxb_component.use_calibration_block = "true",
alt2gxb_component.vod_ctrl_setting = 3;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ALT_SIMLIB_GEN STRING "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "74"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "50.0 62.5 78.125 100.0 125.0 156.25 250.0 312.5 500.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2500"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "50.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "125"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "GIGE-Enhanced"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: CMU_PLL_INCLOCK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: CMU_PLL_LOOP_FILTER_RESISTOR_CONTROL NUMERIC "3"
// Retrieval info: CONSTANT: DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: EN_LOCAL_CLK_DIV_CTRL STRING "true"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II GX"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt2gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_LEGAL_MULTIPLIER_LIST STRING "disable_4_5_mult_above_3125"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "gige"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
// Retrieval info: CONSTANT: REVERSE_LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: RX_8B_10B_COMPATIBILITY_MODE STRING "true"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_BANDWIDTH_MODE NUMERIC "1"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "none"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.9v"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: RX_CRU_PRE_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DISABLE_AUTO_IDLE_INSERTION STRING "true"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_TRUE_COMPLEMENT_MATCH_IN_WORD_ALIGN STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
// Retrieval info: CONSTANT: RX_RATE_MATCH_BACK_TO_BACK STRING "true"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE_MANUAL_CONTROL STRING "none"
// Retrieval info: CONSTANT: RX_RATE_MATCH_ORDERED_SET_BASED STRING "true"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RATE_MATCH_SKIP_SET_BASED STRING "true"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "5"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "true"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_COMPATIBILITY_MODE STRING "true"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.5v"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.6v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_IDLE_SELECTION STRING "true"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_REFCLK_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "3"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 1 0 OUTPUT NODEFVAL "reconfig_fromgxb[0..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 3 0 INPUT NODEFVAL "reconfig_togxb[2..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_clkout 0 0 0 0 OUTPUT NODEFVAL "rx_clkout"
// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]"
// Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
// Retrieval info: USED_PORT: rx_recovclkout 0 0 1 0 OUTPUT NODEFVAL "rx_recovclkout[0..0]"
// Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]"
// Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[0..0]"
// Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[0..0]"
// Retrieval info: USED_PORT: rx_runningdisp 0 0 1 0 OUTPUT NODEFVAL "rx_runningdisp[0..0]"
// Retrieval info: USED_PORT: rx_seriallpbken 0 0 1 0 INPUT NODEFVAL "rx_seriallpbken[0..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 3 0 reconfig_togxb 0 0 3 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @rx_seriallpbken 0 0 1 0 rx_seriallpbken 0 0 1 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 1 0 @reconfig_fromgxb 0 0 1 0
// Retrieval info: CONNECT: rx_clkout 0 0 0 0 @rx_clkout 0 0 0 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
// Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0
// Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
// Retrieval info: CONNECT: rx_recovclkout 0 0 1 0 @rx_recovclkout 0 0 1 0
// Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0
// Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 1 0 @rx_rmfifodatadeleted 0 0 1 0
// Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 1 0 @rx_rmfifodatainserted 0 0 1 0
// Retrieval info: CONNECT: rx_runningdisp 0 0 1 0 @rx_runningdisp 0 0 1 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_wo_rmfifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_wo_rmfifo.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_wo_rmfifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_wo_rmfifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_wo_rmfifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_wo_rmfifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt2gxb_gige_wo_rmfifo_bb.v FALSE
|
module srl_init_tester #
(
parameter [255:0] PATTERN = 256'hFE1AB3FE7610D3D205D9A526C103C40F6477E986F53C53FA663A9CE45E851D30,
parameter SRL_LENGTH = 32
)
(
input wire clk,
input wire rst,
input wire ce,
output reg srl_sh,
output wire [SRL_BITS-1:0] srl_a,
output wire srl_d,
input wire srl_q,
output reg error
);
// ============================================================================
// ROM
wire [7:0] rom_adr;
wire rom_dat;
ROM #(.CONTENT(PATTERN)) rom
(
.clk (clk),
.adr (rom_adr),
.dat (rom_dat)
);
// ============================================================================
// Control
localparam SRL_BITS = $clog2(SRL_LENGTH);
// Bit counter
reg[SRL_BITS-1:0] bit_cnt;
always @(posedge clk)
if (rst)
bit_cnt <= SRL_LENGTH - 1;
else if (ce)
bit_cnt <= bit_cnt - 1;
// Data readout
assign rom_adr = bit_cnt;
// SRL32 control
assign srl_a = SRL_LENGTH - 1;
assign srl_d = srl_q;
initial srl_sh <= 1'b0;
always @(posedge clk)
srl_sh <= ce & !rst;
// Error check
initial error <= 1'b0;
always @(posedge clk)
if (rst)
error <= 1'b0;
else if(ce)
error <= rom_dat ^ srl_q;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
/*
* Helper module for synchronizing a counter from one clock domain to another
* using gray code. To work correctly the counter must not change its value by
* more than one in one clock cycle in the source domain. I.e. the value may
* change by either -1, 0 or +1.
*/
`timescale 1ns/100ps
module sync_gray #(
// Bit-width of the counter
parameter DATA_WIDTH = 1,
// Whether the input and output clock are asynchronous, if set to 0 the
// synchronizer will be bypassed and out_count will be in_count.
parameter ASYNC_CLK = 1)(
input in_clk,
input in_resetn,
input [DATA_WIDTH-1:0] in_count,
input out_resetn,
input out_clk,
output [DATA_WIDTH-1:0] out_count);
generate if (ASYNC_CLK == 1) begin
reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
reg [DATA_WIDTH-1:0] out_count_m = 'h0;
function [DATA_WIDTH-1:0] g2b;
input [DATA_WIDTH-1:0] g;
reg [DATA_WIDTH-1:0] b;
integer i;
begin
b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i - 1)
b[i] = b[i + 1] ^ g[i];
g2b = b;
end
endfunction
function [DATA_WIDTH-1:0] b2g;
input [DATA_WIDTH-1:0] b;
reg [DATA_WIDTH-1:0] g;
integer i;
begin
g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
g[i] = b[i + 1] ^ b[i];
b2g = g;
end
endfunction
always @(posedge in_clk) begin
if (in_resetn == 1'b0) begin
cdc_sync_stage0 <= 'h00;
end else begin
cdc_sync_stage0 <= b2g(in_count);
end
end
always @(posedge out_clk) begin
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'h00;
cdc_sync_stage2 <= 'h00;
out_count_m <= 'h00;
end else begin
cdc_sync_stage1 <= cdc_sync_stage0;
cdc_sync_stage2 <= cdc_sync_stage1;
out_count_m <= g2b(cdc_sync_stage2);
end
end
assign out_count = out_count_m;
end else begin
assign out_count = in_count;
end endgenerate
endmodule
|
// system_acl_iface_acl_kernel_interface_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.28.12:23:20
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface_mm_interconnect_0 (
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cra_reset_reset_bridge_in_reset_reset, // kernel_cra_reset_reset_bridge_in_reset.reset
input wire [29:0] address_span_extender_0_expanded_master_address, // address_span_extender_0_expanded_master.address
output wire address_span_extender_0_expanded_master_waitrequest, // .waitrequest
input wire [0:0] address_span_extender_0_expanded_master_burstcount, // .burstcount
input wire [3:0] address_span_extender_0_expanded_master_byteenable, // .byteenable
input wire address_span_extender_0_expanded_master_read, // .read
output wire [31:0] address_span_extender_0_expanded_master_readdata, // .readdata
output wire address_span_extender_0_expanded_master_readdatavalid, // .readdatavalid
input wire address_span_extender_0_expanded_master_write, // .write
input wire [31:0] address_span_extender_0_expanded_master_writedata, // .writedata
output wire [29:0] kernel_cra_s0_address, // kernel_cra_s0.address
output wire kernel_cra_s0_write, // .write
output wire kernel_cra_s0_read, // .read
input wire [63:0] kernel_cra_s0_readdata, // .readdata
output wire [63:0] kernel_cra_s0_writedata, // .writedata
output wire [0:0] kernel_cra_s0_burstcount, // .burstcount
output wire [7:0] kernel_cra_s0_byteenable, // .byteenable
input wire kernel_cra_s0_readdatavalid, // .readdatavalid
input wire kernel_cra_s0_waitrequest, // .waitrequest
output wire kernel_cra_s0_debugaccess // .debugaccess
);
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest; // address_span_extender_0_expanded_master_agent:av_waitrequest -> address_span_extender_0_expanded_master_translator:uav_waitrequest
wire [2:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount; // address_span_extender_0_expanded_master_translator:uav_burstcount -> address_span_extender_0_expanded_master_agent:av_burstcount
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata; // address_span_extender_0_expanded_master_translator:uav_writedata -> address_span_extender_0_expanded_master_agent:av_writedata
wire [29:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address; // address_span_extender_0_expanded_master_translator:uav_address -> address_span_extender_0_expanded_master_agent:av_address
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock; // address_span_extender_0_expanded_master_translator:uav_lock -> address_span_extender_0_expanded_master_agent:av_lock
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write; // address_span_extender_0_expanded_master_translator:uav_write -> address_span_extender_0_expanded_master_agent:av_write
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read; // address_span_extender_0_expanded_master_translator:uav_read -> address_span_extender_0_expanded_master_agent:av_read
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata; // address_span_extender_0_expanded_master_agent:av_readdata -> address_span_extender_0_expanded_master_translator:uav_readdata
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess; // address_span_extender_0_expanded_master_translator:uav_debugaccess -> address_span_extender_0_expanded_master_agent:av_debugaccess
wire [3:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable; // address_span_extender_0_expanded_master_translator:uav_byteenable -> address_span_extender_0_expanded_master_agent:av_byteenable
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_0_expanded_master_agent:av_readdatavalid -> address_span_extender_0_expanded_master_translator:uav_readdatavalid
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> address_span_extender_0_expanded_master_agent:rp_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> address_span_extender_0_expanded_master_agent:rp_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> address_span_extender_0_expanded_master_agent:rp_startofpacket
wire [100:0] rsp_mux_src_data; // rsp_mux:src_data -> address_span_extender_0_expanded_master_agent:rp_data
wire [0:0] rsp_mux_src_channel; // rsp_mux:src_channel -> address_span_extender_0_expanded_master_agent:rp_channel
wire rsp_mux_src_ready; // address_span_extender_0_expanded_master_agent:rp_ready -> rsp_mux:src_ready
wire kernel_cra_s0_agent_m0_waitrequest; // kernel_cra_s0_translator:uav_waitrequest -> kernel_cra_s0_agent:m0_waitrequest
wire [3:0] kernel_cra_s0_agent_m0_burstcount; // kernel_cra_s0_agent:m0_burstcount -> kernel_cra_s0_translator:uav_burstcount
wire [63:0] kernel_cra_s0_agent_m0_writedata; // kernel_cra_s0_agent:m0_writedata -> kernel_cra_s0_translator:uav_writedata
wire [29:0] kernel_cra_s0_agent_m0_address; // kernel_cra_s0_agent:m0_address -> kernel_cra_s0_translator:uav_address
wire kernel_cra_s0_agent_m0_write; // kernel_cra_s0_agent:m0_write -> kernel_cra_s0_translator:uav_write
wire kernel_cra_s0_agent_m0_lock; // kernel_cra_s0_agent:m0_lock -> kernel_cra_s0_translator:uav_lock
wire kernel_cra_s0_agent_m0_read; // kernel_cra_s0_agent:m0_read -> kernel_cra_s0_translator:uav_read
wire [63:0] kernel_cra_s0_agent_m0_readdata; // kernel_cra_s0_translator:uav_readdata -> kernel_cra_s0_agent:m0_readdata
wire kernel_cra_s0_agent_m0_readdatavalid; // kernel_cra_s0_translator:uav_readdatavalid -> kernel_cra_s0_agent:m0_readdatavalid
wire kernel_cra_s0_agent_m0_debugaccess; // kernel_cra_s0_agent:m0_debugaccess -> kernel_cra_s0_translator:uav_debugaccess
wire [7:0] kernel_cra_s0_agent_m0_byteenable; // kernel_cra_s0_agent:m0_byteenable -> kernel_cra_s0_translator:uav_byteenable
wire kernel_cra_s0_agent_rf_source_endofpacket; // kernel_cra_s0_agent:rf_source_endofpacket -> kernel_cra_s0_agent_rsp_fifo:in_endofpacket
wire kernel_cra_s0_agent_rf_source_valid; // kernel_cra_s0_agent:rf_source_valid -> kernel_cra_s0_agent_rsp_fifo:in_valid
wire kernel_cra_s0_agent_rf_source_startofpacket; // kernel_cra_s0_agent:rf_source_startofpacket -> kernel_cra_s0_agent_rsp_fifo:in_startofpacket
wire [137:0] kernel_cra_s0_agent_rf_source_data; // kernel_cra_s0_agent:rf_source_data -> kernel_cra_s0_agent_rsp_fifo:in_data
wire kernel_cra_s0_agent_rf_source_ready; // kernel_cra_s0_agent_rsp_fifo:in_ready -> kernel_cra_s0_agent:rf_source_ready
wire kernel_cra_s0_agent_rsp_fifo_out_endofpacket; // kernel_cra_s0_agent_rsp_fifo:out_endofpacket -> kernel_cra_s0_agent:rf_sink_endofpacket
wire kernel_cra_s0_agent_rsp_fifo_out_valid; // kernel_cra_s0_agent_rsp_fifo:out_valid -> kernel_cra_s0_agent:rf_sink_valid
wire kernel_cra_s0_agent_rsp_fifo_out_startofpacket; // kernel_cra_s0_agent_rsp_fifo:out_startofpacket -> kernel_cra_s0_agent:rf_sink_startofpacket
wire [137:0] kernel_cra_s0_agent_rsp_fifo_out_data; // kernel_cra_s0_agent_rsp_fifo:out_data -> kernel_cra_s0_agent:rf_sink_data
wire kernel_cra_s0_agent_rsp_fifo_out_ready; // kernel_cra_s0_agent:rf_sink_ready -> kernel_cra_s0_agent_rsp_fifo:out_ready
wire kernel_cra_s0_agent_rdata_fifo_src_valid; // kernel_cra_s0_agent:rdata_fifo_src_valid -> kernel_cra_s0_agent:rdata_fifo_sink_valid
wire [65:0] kernel_cra_s0_agent_rdata_fifo_src_data; // kernel_cra_s0_agent:rdata_fifo_src_data -> kernel_cra_s0_agent:rdata_fifo_sink_data
wire kernel_cra_s0_agent_rdata_fifo_src_ready; // kernel_cra_s0_agent:rdata_fifo_sink_ready -> kernel_cra_s0_agent:rdata_fifo_src_ready
wire address_span_extender_0_expanded_master_agent_cp_endofpacket; // address_span_extender_0_expanded_master_agent:cp_endofpacket -> router:sink_endofpacket
wire address_span_extender_0_expanded_master_agent_cp_valid; // address_span_extender_0_expanded_master_agent:cp_valid -> router:sink_valid
wire address_span_extender_0_expanded_master_agent_cp_startofpacket; // address_span_extender_0_expanded_master_agent:cp_startofpacket -> router:sink_startofpacket
wire [100:0] address_span_extender_0_expanded_master_agent_cp_data; // address_span_extender_0_expanded_master_agent:cp_data -> router:sink_data
wire address_span_extender_0_expanded_master_agent_cp_ready; // router:sink_ready -> address_span_extender_0_expanded_master_agent:cp_ready
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire [100:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire [0:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire kernel_cra_s0_agent_rp_endofpacket; // kernel_cra_s0_agent:rp_endofpacket -> router_001:sink_endofpacket
wire kernel_cra_s0_agent_rp_valid; // kernel_cra_s0_agent:rp_valid -> router_001:sink_valid
wire kernel_cra_s0_agent_rp_startofpacket; // kernel_cra_s0_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [136:0] kernel_cra_s0_agent_rp_data; // kernel_cra_s0_agent:rp_data -> router_001:sink_data
wire kernel_cra_s0_agent_rp_ready; // router_001:sink_ready -> kernel_cra_s0_agent:rp_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [100:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [0:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [100:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [0:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> kernel_cra_s0_cmd_width_adapter:in_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> kernel_cra_s0_cmd_width_adapter:in_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> kernel_cra_s0_cmd_width_adapter:in_startofpacket
wire [100:0] cmd_mux_src_data; // cmd_mux:src_data -> kernel_cra_s0_cmd_width_adapter:in_data
wire [0:0] cmd_mux_src_channel; // cmd_mux:src_channel -> kernel_cra_s0_cmd_width_adapter:in_channel
wire cmd_mux_src_ready; // kernel_cra_s0_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire kernel_cra_s0_cmd_width_adapter_src_endofpacket; // kernel_cra_s0_cmd_width_adapter:out_endofpacket -> kernel_cra_s0_agent:cp_endofpacket
wire kernel_cra_s0_cmd_width_adapter_src_valid; // kernel_cra_s0_cmd_width_adapter:out_valid -> kernel_cra_s0_agent:cp_valid
wire kernel_cra_s0_cmd_width_adapter_src_startofpacket; // kernel_cra_s0_cmd_width_adapter:out_startofpacket -> kernel_cra_s0_agent:cp_startofpacket
wire [136:0] kernel_cra_s0_cmd_width_adapter_src_data; // kernel_cra_s0_cmd_width_adapter:out_data -> kernel_cra_s0_agent:cp_data
wire kernel_cra_s0_cmd_width_adapter_src_ready; // kernel_cra_s0_agent:cp_ready -> kernel_cra_s0_cmd_width_adapter:out_ready
wire [0:0] kernel_cra_s0_cmd_width_adapter_src_channel; // kernel_cra_s0_cmd_width_adapter:out_channel -> kernel_cra_s0_agent:cp_channel
wire router_001_src_endofpacket; // router_001:src_endofpacket -> kernel_cra_s0_rsp_width_adapter:in_endofpacket
wire router_001_src_valid; // router_001:src_valid -> kernel_cra_s0_rsp_width_adapter:in_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> kernel_cra_s0_rsp_width_adapter:in_startofpacket
wire [136:0] router_001_src_data; // router_001:src_data -> kernel_cra_s0_rsp_width_adapter:in_data
wire [0:0] router_001_src_channel; // router_001:src_channel -> kernel_cra_s0_rsp_width_adapter:in_channel
wire router_001_src_ready; // kernel_cra_s0_rsp_width_adapter:in_ready -> router_001:src_ready
wire kernel_cra_s0_rsp_width_adapter_src_endofpacket; // kernel_cra_s0_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire kernel_cra_s0_rsp_width_adapter_src_valid; // kernel_cra_s0_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire kernel_cra_s0_rsp_width_adapter_src_startofpacket; // kernel_cra_s0_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire [100:0] kernel_cra_s0_rsp_width_adapter_src_data; // kernel_cra_s0_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire kernel_cra_s0_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> kernel_cra_s0_rsp_width_adapter:out_ready
wire [0:0] kernel_cra_s0_rsp_width_adapter_src_channel; // kernel_cra_s0_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) address_span_extender_0_expanded_master_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.uav_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_expanded_master_address), // avalon_anti_master_0.address
.av_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.av_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.av_read (address_span_extender_0_expanded_master_read), // .read
.av_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.av_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.av_write (address_span_extender_0_expanded_master_write), // .write
.av_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) kernel_cra_s0_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cra_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.uav_read (kernel_cra_s0_agent_m0_read), // .read
.uav_write (kernel_cra_s0_agent_m0_write), // .write
.uav_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.uav_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.uav_lock (kernel_cra_s0_agent_m0_lock), // .lock
.uav_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.av_address (kernel_cra_s0_address), // avalon_anti_slave_0.address
.av_write (kernel_cra_s0_write), // .write
.av_read (kernel_cra_s0_read), // .read
.av_readdata (kernel_cra_s0_readdata), // .readdata
.av_writedata (kernel_cra_s0_writedata), // .writedata
.av_burstcount (kernel_cra_s0_burstcount), // .burstcount
.av_byteenable (kernel_cra_s0_byteenable), // .byteenable
.av_readdatavalid (kernel_cra_s0_readdatavalid), // .readdatavalid
.av_waitrequest (kernel_cra_s0_waitrequest), // .waitrequest
.av_debugaccess (kernel_cra_s0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BEGIN_BURST (84),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (76),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (72),
.PKT_ADDR_H (65),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (66),
.PKT_TRANS_POSTED (67),
.PKT_TRANS_WRITE (68),
.PKT_TRANS_READ (69),
.PKT_TRANS_LOCK (70),
.PKT_TRANS_EXCLUSIVE (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_THREAD_ID_H (88),
.PKT_THREAD_ID_L (88),
.PKT_CACHE_H (95),
.PKT_CACHE_L (92),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_ORI_BURST_SIZE_H (100),
.ST_DATA_W (101),
.ST_CHANNEL_W (1),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_expanded_master_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // av.address
.av_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.av_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (address_span_extender_0_expanded_master_agent_cp_valid), // cp.valid
.cp_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.cp_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (address_span_extender_0_expanded_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (120),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (101),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (102),
.PKT_TRANS_POSTED (103),
.PKT_TRANS_WRITE (104),
.PKT_TRANS_READ (105),
.PKT_TRANS_LOCK (106),
.PKT_SRC_ID_H (122),
.PKT_SRC_ID_L (122),
.PKT_DEST_ID_H (123),
.PKT_DEST_ID_L (123),
.PKT_BURSTWRAP_H (112),
.PKT_BURSTWRAP_L (112),
.PKT_BYTE_CNT_H (111),
.PKT_BYTE_CNT_L (108),
.PKT_PROTECTION_H (127),
.PKT_PROTECTION_L (125),
.PKT_RESPONSE_STATUS_H (133),
.PKT_RESPONSE_STATUS_L (132),
.PKT_BURST_SIZE_H (115),
.PKT_BURST_SIZE_L (113),
.PKT_ORI_BURST_SIZE_L (134),
.PKT_ORI_BURST_SIZE_H (136),
.ST_CHANNEL_W (1),
.ST_DATA_W (137),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) kernel_cra_s0_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (kernel_cra_s0_agent_m0_address), // m0.address
.m0_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (kernel_cra_s0_agent_m0_lock), // .lock
.m0_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (kernel_cra_s0_agent_m0_read), // .read
.m0_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.m0_write (kernel_cra_s0_agent_m0_write), // .write
.rp_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (kernel_cra_s0_agent_rp_ready), // .ready
.rp_valid (kernel_cra_s0_agent_rp_valid), // .valid
.rp_data (kernel_cra_s0_agent_rp_data), // .data
.rp_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.cp_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.cp_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (kernel_cra_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (kernel_cra_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (kernel_cra_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (kernel_cra_s0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (kernel_cra_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (138),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) kernel_cra_s0_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (kernel_cra_s0_agent_rf_source_data), // in.data
.in_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.in_ready (kernel_cra_s0_agent_rf_source_ready), // .ready
.in_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (kernel_cra_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router router (
.sink_ready (address_span_extender_0_expanded_master_agent_cp_ready), // sink.ready
.sink_valid (address_span_extender_0_expanded_master_agent_cp_valid), // .valid
.sink_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.sink_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router_001 router_001 (
.sink_ready (kernel_cra_s0_agent_rp_ready), // sink.ready
.sink_valid (kernel_cra_s0_agent_rp_valid), // .valid
.sink_data (kernel_cra_s0_agent_rp_data), // .data
.sink_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux cmd_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.sink_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.sink_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_rsp_mux rsp_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (65),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (72),
.IN_PKT_TRANS_COMPRESSED_READ (66),
.IN_PKT_BURSTWRAP_H (76),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (79),
.IN_PKT_BURST_SIZE_L (77),
.IN_PKT_RESPONSE_STATUS_H (97),
.IN_PKT_RESPONSE_STATUS_L (96),
.IN_PKT_TRANS_EXCLUSIVE (71),
.IN_PKT_BURST_TYPE_H (81),
.IN_PKT_BURST_TYPE_L (80),
.IN_PKT_ORI_BURST_SIZE_L (98),
.IN_PKT_ORI_BURST_SIZE_H (100),
.IN_ST_DATA_W (101),
.OUT_PKT_ADDR_H (101),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (111),
.OUT_PKT_BYTE_CNT_L (108),
.OUT_PKT_TRANS_COMPRESSED_READ (102),
.OUT_PKT_BURST_SIZE_H (115),
.OUT_PKT_BURST_SIZE_L (113),
.OUT_PKT_RESPONSE_STATUS_H (133),
.OUT_PKT_RESPONSE_STATUS_L (132),
.OUT_PKT_TRANS_EXCLUSIVE (107),
.OUT_PKT_BURST_TYPE_H (117),
.OUT_PKT_BURST_TYPE_L (116),
.OUT_PKT_ORI_BURST_SIZE_L (134),
.OUT_PKT_ORI_BURST_SIZE_H (136),
.OUT_ST_DATA_W (137),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (101),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (111),
.IN_PKT_BYTE_CNT_L (108),
.IN_PKT_TRANS_COMPRESSED_READ (102),
.IN_PKT_BURSTWRAP_H (112),
.IN_PKT_BURSTWRAP_L (112),
.IN_PKT_BURST_SIZE_H (115),
.IN_PKT_BURST_SIZE_L (113),
.IN_PKT_RESPONSE_STATUS_H (133),
.IN_PKT_RESPONSE_STATUS_L (132),
.IN_PKT_TRANS_EXCLUSIVE (107),
.IN_PKT_BURST_TYPE_H (117),
.IN_PKT_BURST_TYPE_L (116),
.IN_PKT_ORI_BURST_SIZE_L (134),
.IN_PKT_ORI_BURST_SIZE_H (136),
.IN_ST_DATA_W (137),
.OUT_PKT_ADDR_H (65),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (72),
.OUT_PKT_TRANS_COMPRESSED_READ (66),
.OUT_PKT_BURST_SIZE_H (79),
.OUT_PKT_BURST_SIZE_L (77),
.OUT_PKT_RESPONSE_STATUS_H (97),
.OUT_PKT_RESPONSE_STATUS_L (96),
.OUT_PKT_TRANS_EXCLUSIVE (71),
.OUT_PKT_BURST_TYPE_H (81),
.OUT_PKT_BURST_TYPE_L (80),
.OUT_PKT_ORI_BURST_SIZE_L (98),
.OUT_PKT_ORI_BURST_SIZE_H (100),
.OUT_ST_DATA_W (101),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_001_src_valid), // sink.valid
.in_channel (router_001_src_channel), // .channel
.in_startofpacket (router_001_src_startofpacket), // .startofpacket
.in_endofpacket (router_001_src_endofpacket), // .endofpacket
.in_ready (router_001_src_ready), // .ready
.in_data (router_001_src_data), // .data
.out_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211OI_2_V
`define SKY130_FD_SC_HS__A211OI_2_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a211oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a211oi_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211OI_2_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_src_fifo_inf (
input clk,
input resetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
input eot,
input en,
input [C_DATA_WIDTH-1:0] din,
output reg overflow,
input sync,
input fifo_ready,
output fifo_valid,
output [C_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [3:0] req_last_burst_length,
input req_sync_transfer_start
);
parameter C_ID_WIDTH = 3;
parameter C_DATA_WIDTH = 64;
parameter C_LENGTH_WIDTH = 24;
reg valid = 1'b0;
wire ready;
reg [C_DATA_WIDTH-1:0] buffer = 'h00;
reg buffer_sync = 1'b0;
reg needs_sync = 1'b0;
wire has_sync = ~needs_sync | buffer_sync;
wire sync_valid = valid & has_sync;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
needs_sync <= 1'b0;
end else begin
if (ready && valid && buffer_sync) begin
needs_sync <= 1'b0;
end else if (req_valid && req_ready) begin
needs_sync <= req_sync_transfer_start;
end
end
end
always @(posedge clk)
begin
if (resetn == 1'b0) begin
valid <= 1'b0;
overflow <= 1'b0;
end else begin
if (enable) begin
if (en) begin
buffer <= din;
buffer_sync <= sync;
valid <= 1'b1;
end else if (ready) begin
valid <= 1'b0;
end
overflow <= en & valid & ~ready;
end else begin
if (ready)
valid <= 1'b0;
overflow <= en;
end
end
end
assign sync_id_ret = sync_id;
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
.clk(clk),
.resetn(resetn),
.enable(enable),
.enabled(enabled),
.sync_id(sync_id),
.request_id(request_id),
.response_id(response_id),
.eot(eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_ready(ready),
.s_axi_valid(sync_valid),
.s_axi_data(buffer),
.m_axi_ready(fifo_ready),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data)
);
endmodule
|
module jserialaddertb;
wire [3:0]y;
wire carryout,isValid;
wire currentsum, currentcarryout;
wire [1:0]currentbitcount;
reg clk, rst;
reg a,b,carryin;
reg [3:0]A,B;// temporary variables to ease the testing
integer timeLapsed;
integer i;
jserialadder jsa(y,carryout,isValid,currentsum,currentcarryout,currentbitcount,clk,rst,a,b,carryin);
//always #5 clk = ~clk;// THIS can NOT be done as we have to control the inputs with the clock
initial
begin
// The general concept of testing is to put the block of statement within the clock change
$display("INITIALIZING");
timeLapsed = 0;
i = 0;
a = 0; b = 0; carryin = 0; A = 0; B = 0; // donot have "x" values, it is most confusing :-)
// First time initialization
// Always reset the adder before starting addition
#10; clk = 0; rst = 1; #10; clk =1 ; #10; clk = 0 ; rst =0; #10; // Reset the adder
timeLapsed = timeLapsed + 40;
$display("\nTESTING");
$display("RSLT\tTIME(ns)\ta A\tb B\tCYIN\t\tCYOUT\tSUM\tISVALID\t\tBITT\tCCRY\tCSUM");
//$display("NEXT Reset");
a = 0; b = 0; carryin = 0; A = 0; B = 0; // donot have "x" values, it is most confusing :-)
// Always reset the adder before starting addition
#10; clk = 0; rst = 1; #10; clk =1 ; #10; clk = 0 ; rst =0; #10; // Reset the adder
timeLapsed = timeLapsed + 40;
$display("Reset\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
A = 5; B =5; carryin = 0; // Set the inputs
i = 0;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 1;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 2;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 3;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
clk = 0; #10; clk = 1; #10; // Extra clock since it is a serial adder
timeLapsed = timeLapsed + 20;
if ( (carryout == 0 ) && (y === 10))
$display("PASS==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
else
$display("FAIL==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
a = 0; b = 0; carryin = 0; A = 0; B = 0; // donot have "x" values, it is most confusing :-)
// Always reset the adder before starting addition
#10; clk = 0; rst = 1; #10; clk =1 ; #10; clk = 0 ; rst =0; #10; // Reset the adder
timeLapsed = timeLapsed + 40;
$display("Reset\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
A = 10; B = 5; carryin = 0; // Set the inputs
i = 0;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 1;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 2;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 3;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
clk = 0; #10; clk = 1; #10; // Extra clock since it is a serial adder
timeLapsed = timeLapsed + 20;
if ( (carryout == 0 ) && (y === 15))
$display("PASS==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
else
$display("FAIL==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
a = 0; b = 0; carryin = 0; A = 0; B = 0; // donot have "x" values, it is most confusing :-)
// Always reset the adder before starting addition
#10; clk = 0; rst = 1; #10; clk =1 ; #10; clk = 0 ; rst =0; #10; // Reset the adder
timeLapsed = timeLapsed + 40;
$display("Reset\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
A = 6; B = 10; carryin = 0; // Set the inputs
i = 0;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 1;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 2;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 3;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
clk = 0; #10; clk = 1; #10; // Extra clock since it is a serial adder
timeLapsed = timeLapsed + 20;
if ( (carryout == 1 ) && (y === 0))
$display("PASS==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
else
$display("FAIL==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
a = 0; b = 0; carryin = 0; A = 0; B = 0; // donot have "x" values, it is most confusing :-)
// Always reset the adder before starting addition
#10; clk = 0; rst = 1; #10; clk =1 ; #10; clk = 0 ; rst =0; #10; // Reset the adder
timeLapsed = timeLapsed + 40;
$display("Reset\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
A = 15; B = 15; carryin = 0; // Set the inputs
i = 0;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 1;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 2;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
i = 3;
clk = 0; #10; a = A[i]; b = B[i]; #10; clk = 1; #10; // Set inputs enable clock
timeLapsed = timeLapsed + 30;
$display("BitN\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d\t%d\t%d",timeLapsed,a,b,carryin,carryout,y,isValid,currentbitcount,currentcarryout,currentsum);
clk = 0; #10; clk = 1; #10; // Extra clock since it is a serial adder
timeLapsed = timeLapsed + 20;
if ( (carryout == 1 ) && (y === 14))
$display("PASS==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
else
$display("FAIL==>\t%d\t%d\t%d\t%d\t=\t%d\t%d\t%d\t\t%d==>",timeLapsed,A,B,carryin,carryout,y,isValid,currentbitcount);
end
endmodule
// Below is the test module for the lab provided code
module jserialaddlabtb;
reg clk, reset, a, b;
wire sum, carry, cout;
wire [2:0] count;
wire [3:0] so;
jserialaddlab jslab(a,b,clk,reset,sum,carry,cout,count,so);
initial
begin
clk=1;reset=1;
a=0; b=0;
#10;
reset=0;
// Now send a = 0101 and b = 1010
a=1;b=0;
#10;
a=0;b=1;
#10;
a=1;b=0;
#10;
a=0;b=1;
#10;
// After four cycles the reset should be out
// check for 5 + 10 = 15 i.e. y = 1111 and carry = 0
// Now send a = 0100 and b = 0110
a=0;b=0;
#10
a=0;b=1;
#10;
a=1;b=1;
#10
a=0;b=0;
#10;
// After four cycles the reset should be out
// check for 4 + 6 = 10 i.e. y = 1010 and carry = 0
#100;
#10;
// why would the above line not break
#10;
end
always #5 clk=~clk;
always @(posedge clk)
begin
if(count == 3'b100)
$display("The carry and sum are = %d %d", carry, so);
end
endmodule |
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 05:33:33 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_2_stub.v
// Design : design_1_processing_system7_0_2
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID,
M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O22A_FUNCTIONAL_PP_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22A_FUNCTIONAL_PP_V |
//-----------------------------------------------------
// Proyecto 1 : DISEÑO DE UN CONTROLADOR DE SD HOST
// Archivo : DATA_PHYSICAL.v
// Descripcion : Control de capa física de datos del SD Host.
// La función de este bloque es servir de interfaz entre la tajeta SD, la capa física y el buffer FIFO.
// Se comunica con el bloque de Registros y los convertidores Serial a Paralelo, Paralelo a Serial y el bloque
// PAD.
//
// Grupo 02
// Estudiante : Mario Castresana Avendaño | A41267
//-----------------------------------------------------
/*
=================================================
CAPA FÍSICA DEL MODULO DE CONTROL DE DATOS
=================================================
Este módulo por aparte se especializa en manejar tramas de datos directamente
con la tarjeta SD y sus pines físicos. Su arquitectura es muy similar a la de
la capa física del bloque CMD, con la diferencia de que a DATA_PHYSICAL le toca
interactuar directamente con el buffer FIFO.
PINOUT del módulo:
Para nombrar señales se usa la convención señal_procedencia_destino
---
notas:
1- entiéndase PS como el módulo Parallel to Serial y SP como el módulo Serial to Parallel.
2- SD_CLK opera a 25MHz
_____________________________________________________________________________________
Nombre de Señal : Entradas : Salidas : procedencia : destino
SD_CLK x - SD_CARD DATA_PHYSICAL
RESET_L x - Host DATA_PHYSICAL
strobe_IN_DATA_Phy x - DATA DATA_PHYSICAL
ack_IN_DATA_Phy x - DATA DATA_PHYSICAL
timeout_Reg_DATA_Phy [15:0] x - DATA DATA_PHYSICAL
blocks_DATA_Phy [3:0] x - DATA DATA_PHYSICAL
writeRead_DATA_Phy x - DATA DATA_PHYSICAL
multiple_DATA_Phy x - DATA DATA_PHYSICAL
idle_in_DATA_Phy x - DATA DATA_PHYSICAL
transmission_complete_PS_Phy x - PS DATA_PHYSICAL
reception_complete_SP_Phy x - SP DATA_PHYSICAL
data_read_SP_Phy [31:0] x - SP DATA_PHYSICAL
dataFromFIFO_FIFO_Phy [31:0] x - FIFO DATA_PHYSICAL
serial_Ready_Phy_DATA - x DATA_PHYSICAL DATA
complete_Phy_DATA - x DATA_PHYSICAL DATA
ack_OUT_Phy_DATA - x DATA_PHYSICAL DATA
data_timeout_Phy_DATA - x DATA_PHYSICAL DATA y Regs
reset_Wrapper_Phy_PS - x DATA_PHYSICAL PS y SP
enable_pts_Wrapper_Phy_PS - x DATA_PHYSICAL PS
enable_stp_Wrapper_Phy_SP - x DATA_PHYSICAL SP
dataParallel_Phy_PS [31:0] - x DATA_PHYSICAL PS
pad_state_Phy_PAD - x DATA_PHYSICAL PAD
pad_enable_Phy_PAD - x DATA_PHYSICAL PAD
writeFIFO_enable_Phy_FIFO - x DATA_PHYSICAL FIFO
readFIFO_enable_Phy_FIFO - x DATA_PHYSICAL FIFO
dataReadToFIFO_Phy_FIFO [31:0] - x DATA_PHYSICAL FIFO
DAT_pin_IN_SDCard_Phy x - SD_CARD DATA_PHYSICAL <<< es un pin de entrada/salida que no se usa
DAT_pin_OUT_Phy_SDCard - x DATA_PHYSICAL SD_CARD en la implementacion final
DAT_pin_OUT_Enable_Phy_SDCard - x DATA_PHYSICAL SD_CARD
_____________________________________________________________________________________
*/
module DATA_PHYSICAL(
input wire SD_CLK,
input wire RESET_L,
input wire strobe_IN_DATA_Phy,
input wire ack_IN_DATA_Phy,
input wire [15:0] timeout_Reg_DATA_Phy,
input wire [3:0] blocks_DATA_Phy,
input wire writeRead_DATA_Phy,
input wire multiple_DATA_Phy,
input wire idle_in_DATA_Phy,
input wire transmission_complete_PS_Phy,
input wire reception_complete_SP_Phy,
input wire [31:0] data_read_SP_Phy,
input wire [31:0] dataFromFIFO_FIFO_Phy,
output reg serial_Ready_Phy_DATA,
output reg complete_Phy_DATA,
output reg ack_OUT_Phy_DATA,
output reg data_timeout_Phy_DATA,
output reg reset_Wrapper_Phy_PS,
output reg enable_pts_Wrapper_Phy_PS,
output reg enable_stp_Wrapper_Phy_SP,
output reg [31:0] dataParallel_Phy_PS,
output reg pad_state_Phy_PAD,
output reg pad_enable_Phy_PAD,
output reg writeFIFO_enable_Phy_FIFO,
output reg readFIFO_enable_Phy_FIFO,
output reg [31:0] dataReadToFIFO_Phy_FIFO,
output reg IO_enable_Phy_SD_CARD
);
//Definición y condificación de estados one-hot
parameter RESET = 11'b00000000001;
parameter IDLE = 11'b00000000010;
parameter FIFO_READ = 11'b00000000100;
parameter LOAD_WRITE = 11'b00000001000;
parameter SEND = 11'b00000010000;
parameter WAIT_RESPONSE = 11'b00000100000;
parameter READ = 11'b00001000000;
parameter READ_FIFO_WRITE = 11'b00010000000;
parameter READ_WRAPPER_RESET = 11'b00100000000;
parameter WAIT_ACK = 11'b01000000000;
parameter SEND_ACK = 11'b10000000000;
//registros internos de interés
reg [15:0] timeout_input;
reg [3:0] blocks;
reg [10:0] STATE;
reg [10:0] NEXT_STATE;
//Inicializar, en el estado IDLE, los contadores para timeout_Reg_DATA_Phy y bloques
//timeout_input es el contador para el timeout_Reg_DATA_Phy;
//blocks es el contador para blocks_DATA_Phy;
//NEXT_STATE logic (always_ff)
always @ (posedge SD_CLK)
begin
if (!RESET_L)
begin
STATE <= RESET;
end
else
begin
STATE <= NEXT_STATE;
end
end
//--------------------------------
//CURRENT_STATE logic (always comb)
always @ (*)
begin
case (STATE)
RESET:
begin
//se ponen todas las salidas a 0 excepto reset_Wrapper_Phy_PS
serial_Ready_Phy_DATA = 0;
complete_Phy_DATA = 0;
ack_OUT_Phy_DATA = 0;
data_timeout_Phy_DATA = 0;
reset_Wrapper_Phy_PS = 1; //solo esta en 1 porque el wrapper se resetea en 0
enable_pts_Wrapper_Phy_PS = 0;
enable_stp_Wrapper_Phy_SP = 0;
dataParallel_Phy_PS = 32'b0;
pad_state_Phy_PAD = 0;
pad_enable_Phy_PAD = 0;
writeFIFO_enable_Phy_FIFO = 0;
readFIFO_enable_Phy_FIFO = 0;
dataReadToFIFO_Phy_FIFO = 32'b0;
IO_enable_Phy_SD_CARD = 0; //por default el host recibe datos desde la tarjeta SD
//avanza automaticamente a IDLE
NEXT_STATE = IDLE;
end
//------------------------------
IDLE:
begin
// estado por defecto en caso de interrupcion
// afirma la salida serial_Ready_Phy_DATA
serial_Ready_Phy_DATA = 1;
//reiniciar blocks_DATA_Phy y timeout_Reg_DATA_Phy
blocks = 4'b0;
timeout_input = 16'b0;
if (strobe_IN_DATA_Phy && writeRead_DATA_Phy)
begin
NEXT_STATE = FIFO_READ;
end
else
begin
NEXT_STATE = READ;
end
end
//-------------------------------
FIFO_READ:
begin
//se afirma writeFIFO_enable_Phy_FIFO
writeFIFO_enable_Phy_FIFO = 1;
dataParallel_Phy_PS = dataFromFIFO_FIFO_Phy;
//se avanza al estado LOAD_WRITE
NEXT_STATE = LOAD_WRITE;
end
//--------------------------------
LOAD_WRITE:
begin
//se carga al convertidor PS los datos que venían del FIFO mediante la
//combinación de señales:
enable_pts_Wrapper_Phy_PS = 1;
IO_enable_Phy_SD_CARD = 0;
pad_state_Phy_PAD = 1;
pad_enable_Phy_PAD = 1;
//se avanza al estado SEND
NEXT_STATE = SEND;
end
//---------------------------------
SEND:
begin
//avisar al hardware que se entregarán datos
IO_enable_Phy_SD_CARD = 1;
//se avanza al estado WAIT_RESPONSE
NEXT_STATE = WAIT_RESPONSE;
end
//---------------------------------
WAIT_RESPONSE:
begin
//desabilitar convertidor PS
enable_pts_Wrapper_Phy_PS = 0;
//habilitar el convertidor SP
enable_stp_Wrapper_Phy_SP = 1;
//preparar el PAD para su uso
pad_state_Phy_PAD = 0;
//comienza la cuenta de timeout_input y genera interrupcion si se pasa
timeout_input = timeout_input + 1;
if (timeout_input == timeout_Reg_DATA_Phy)
begin
data_timeout_Phy_DATA = 1;
end
else
begin
data_timeout_Phy_DATA = 0;
end
if (reception_complete_SP_Phy)
begin
//se incrementa en 1 los bloques transmitidos
blocks = blocks + 1;
//y se decide el estado
if (!multiple_DATA_Phy || (blocks==blocks_DATA_Phy))
begin
NEXT_STATE = WAIT_ACK;
end
else
begin
//continúa la transmisión del siguiente bloque
NEXT_STATE = FIFO_READ;
end
end
else
begin
NEXT_STATE = WAIT_RESPONSE;
end
end
//-----------------------------------
READ:
begin
//se afirma la señal pad_enable_Phy_PAD
pad_enable_Phy_PAD = 1;
//pad_state_Phy_PAD se pone en bajo para usarlo como entrada
pad_state_Phy_PAD = 0;
//habilitar convertidad SP
enable_stp_Wrapper_Phy_SP = 1;
//se realiza una cuenta de timeout
timeout_input = timeout_input + 1;
//genera interrupcion si se pasa
if (timeout_input == timeout_Reg_DATA_Phy)
begin
data_timeout_Phy_DATA = 1;
end
else
begin
data_timeout_Phy_DATA = 0;
end
//revisar si la transmisión está completa
if (reception_complete_SP_Phy)
begin
//se incrementa en 1 los bloques transmitidos
blocks = blocks + 1;
NEXT_STATE = READ_FIFO_WRITE;
end
else
begin
NEXT_STATE = READ;
end
end
//------------------------------------
READ_FIFO_WRITE:
begin
//afirma la señal readFIFO_enable_Phy_FIFO
readFIFO_enable_Phy_FIFO = 1;
//se coloca la salida dataReadToFIFO_Phy_FIFO en data_read_SP_Phy
dataReadToFIFO_Phy_FIFO = data_read_SP_Phy;
//se desabilita el convertidor SP
enable_stp_Wrapper_Phy_SP = 0;
if ((blocks == blocks_DATA_Phy) || !multiple_DATA_Phy)
begin
NEXT_STATE = WAIT_ACK;
end
else
begin
NEXT_STATE = READ_WRAPPER_RESET;
end
end
//------------------------------------
READ_WRAPPER_RESET:
begin
//reiniciar los wrappers
reset_Wrapper_Phy_PS = 1;
NEXT_STATE = READ;
end
//------------------------------------
WAIT_ACK:
begin
//afirma la señal complete_Phy_DATA para indicar que se terminó la transacción de DATA
complete_Phy_DATA = 1;
if (ack_IN_DATA_Phy)
begin
NEXT_STATE = SEND_ACK;
end
else
begin
NEXT_STATE = WAIT_ACK;
end
end
//-------------------------------------
SEND_ACK:
begin
//afirma la señal ack_OUT_Phy_DATA para reconocer que se recibió ack_IN_DATA_Phy por parte del CONTROLADOR DATA
ack_OUT_Phy_DATA = 1;
NEXT_STATE = IDLE;
end
//-------------------------------------
default:
begin
NEXT_STATE = IDLE; //estado por defecto
end
endcase
end //always
endmodule // DATA_PHYSICAL
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 29.10.2015 13:14:46
// Design Name:
// Module Name: pfd
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
module red_pitaya_pfd_block
#(
parameter ISR = 0
)
( input rstn_i,
input clk_i,
input s1, //signal 1
input s2, //signal 2
output [14-1:0] integral_o
);
reg l1; //s1 from last cycle
reg l2; //s2 from last cycle
wire e1;
wire e2;
reg [14+ISR-1:0] integral;
assign e1 = ( {s1,l1} == 2'b10 ) ? 1'b1 : 1'b0;
assign e2 = ( {s2,l2} == 2'b10 ) ? 1'b1 : 1'b0;
assign integral_o = integral[14+ISR-1:ISR];
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
l1 <= 1'b0;
l2 <= 1'b0;
integral <= {(14+ISR){1'b0}};
end
else begin
l1 <= s1;
l2 <= s2;
if (integral == {1'b0,{14+ISR-1{1'b1}}}) //auto-reset or positive saturation
//integral <= {INTBITS{1'b0}};
integral <= integral + {14+ISR{1'b1}}; //decrement by one
else if (integral == {1'b1,{14+ISR-1{1'b0}}}) //auto-reset or negative saturation
//integral <= {INTBITS{1'b0}};
integral <= integral + {{14+ISR-1{1'b0}},1'b1};
//output signal is proportional to frequency difference of s1-s2
else if ({e1,e2}==2'b10)
integral <= integral + {{14+ISR-1{1'b0}},1'b1};
else if ({e1,e2}==2'b01)
integral <= integral + {14+ISR{1'b1}};
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR2_4_V
`define SKY130_FD_SC_HDLL__XOR2_4_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR2_4_V
|
module top (
input wire clk,
input wire [7:0] sw,
output wire [7:0] led,
output wire [3:0] io_out,
input wire [3:0] io_inp
);
// PLL (to get clock division and still keep 50% duty cycle)
wire fb;
wire clk_ddr;
wire clk_ddr_nobuf;
PLLE2_ADV # (
.CLKFBOUT_MULT (16),
.CLKOUT0_DIVIDE (64) // 25MHz
) pll (
.CLKIN1 (clk),
.CLKFBIN (fb),
.CLKFBOUT (fb),
.CLKOUT0 (clk_ddr_nobuf)
);
BUFG bufg (.I(clk_ddr_nobuf), .O(clk_ddr));
// Heartbeat
reg [23:0] cnt;
always @(posedge clk_ddr)
cnt <= cnt + 1;
assign led[7] = cnt[23];
// IDELAYCTRL
IDELAYCTRL idelayctrl (
.REFCLK (clk_ddr),
.RDY (led[6])
);
// Testers
ioddr_tester #(.DDR_CLK_EDGE("SAME_EDGE"))
tester0 (.CLK(clk_ddr), .CLKB(clk_ddr), .ERR(led[0]), .Q(io_out[0]), .D(io_inp[0]));
ioddr_tester #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), .USE_IDELAY(1))
tester1 (.CLK(clk_ddr), .CLKB(clk_ddr), .ERR(led[1]), .Q(io_out[1]), .D(io_inp[1]));
ioddr_tester #(.DDR_CLK_EDGE("OPPOSITE_EDGE"))
tester2 (.CLK(clk_ddr), .CLKB(clk_ddr), .ERR(led[2]), .Q(io_out[2]), .D(io_inp[2]));
ioddr_tester #(.USE_PHY_ODDR(0))
tester3 (.CLK(clk_ddr), .CLKB(clk_ddr), .ERR(led[3]), .Q(io_out[3]), .D(io_inp[3]));
// Unused LEDs
assign led[5:4] = |sw;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_ctl_pad.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_ctl_pad(/*AUTOARG*/
// Outputs
ctl_pad_clk_so, bso,
// Inouts
pad,
// Inputs
vrefcode, vdd_h, update_dr, testmode_l, shift_dr, rst_l,
mode_ctrl, hiz_n, data, ctl_pad_clk_si, ctl_pad_clk_se, clock_dr,
clk, cbu, cbd, bsi
);
//////////////////////////////////////////////////////////////////////////
// INPUTS
//////////////////////////////////////////////////////////////////////////
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input bsi; // To sstl_pad of dram_sstl_pad.v
input [8:1] cbd; // To sstl_pad of dram_sstl_pad.v
input [8:1] cbu; // To sstl_pad of dram_sstl_pad.v
input clk; // To ctl_edgelogic of dram_ctl_edgelogic.v
input clock_dr; // To sstl_pad of dram_sstl_pad.v
input ctl_pad_clk_se; // To ctl_edgelogic of dram_ctl_edgelogic.v
input ctl_pad_clk_si; // To ctl_edgelogic of dram_ctl_edgelogic.v
input data; // To ctl_edgelogic of dram_ctl_edgelogic.v
input hiz_n; // To sstl_pad of dram_sstl_pad.v
input mode_ctrl; // To sstl_pad of dram_sstl_pad.v
input rst_l; // To ctl_edgelogic of dram_ctl_edgelogic.v
input shift_dr; // To sstl_pad of dram_sstl_pad.v
input testmode_l; // To ctl_edgelogic of dram_ctl_edgelogic.v
input update_dr; // To sstl_pad of dram_sstl_pad.v
input vdd_h; // To sstl_pad of dram_sstl_pad.v
input [7:0] vrefcode; // To sstl_pad of dram_sstl_pad.v
// End of automatics
//////////////////////////////////////////////////////////////////////////
// INOUTPUTS
//////////////////////////////////////////////////////////////////////////
inout pad;
//////////////////////////////////////////////////////////////////////////
// OUTPUTS
//////////////////////////////////////////////////////////////////////////
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output bso; // From sstl_pad of dram_sstl_pad.v
output ctl_pad_clk_so; // From ctl_edgelogic of dram_ctl_edgelogic.v
// End of automatics
//////////////////////////////////////////////////////////////////////////
// CODE
//////////////////////////////////////////////////////////////////////////
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire to_pad; // From ctl_edgelogic of dram_ctl_edgelogic.v
// End of automatics
// INSTANTIATING PAD LOGIC
dram_ctl_edgelogic ctl_edgelogic(/*AUTOINST*/
// Outputs
.ctl_pad_clk_so(ctl_pad_clk_so),
.to_pad(to_pad),
// Inputs
.clk (clk),
.rst_l (rst_l),
.testmode_l(testmode_l),
.ctl_pad_clk_se(ctl_pad_clk_se),
.ctl_pad_clk_si(ctl_pad_clk_si),
.data (data));
// SSTL LOGIC
/*dram_sstl_pad AUTO_TEMPLATE(
.pad (pad),
.oe (1'b1),
.to_core (),
.odt_enable_mask (1'b1),
.data_in (to_pad));
*/
dram_sstl_pad sstl_pad(/*AUTOINST*/
// Outputs
.bso (bso),
.to_core (), // Templated
// Inouts
.pad (pad), // Templated
// Inputs
.bsi (bsi),
.cbd (cbd[8:1]),
.cbu (cbu[8:1]),
.clock_dr (clock_dr),
.data_in (to_pad), // Templated
.hiz_n (hiz_n),
.mode_ctrl (mode_ctrl),
.odt_enable_mask (1'b1), // Templated
.oe (1'b1), // Templated
.shift_dr (shift_dr),
.update_dr (update_dr),
.vdd_h (vdd_h),
.vrefcode (vrefcode[7:0]));
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
// Date : Fri Sep 22 17:40:41 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_bram_ctrl,Vivado 2017.2.1" *)
(* NotValidForBitStream *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [12:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input s_axi_awlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [12:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input s_axi_arlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *) output bram_rst_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) output bram_clk_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) output bram_en_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) output [3:0]bram_we_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) output [12:0]bram_addr_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) output [31:0]bram_wrdata_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) input [31:0]bram_rddata_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *) output bram_rst_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) output bram_clk_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) output bram_en_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) output [3:0]bram_we_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) output [12:0]bram_addr_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) output [31:0]bram_wrdata_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) input [31:0]bram_rddata_b;
wire [12:0]bram_addr_a;
wire [12:0]bram_addr_b;
wire bram_clk_a;
wire bram_clk_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_a;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire bram_rst_b;
wire [3:0]bram_we_a;
wire [3:0]bram_we_b;
wire [31:0]bram_wrdata_a;
wire [31:0]bram_wrdata_b;
wire s_axi_aclk;
wire [12:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arlock;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [12:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awlock;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ecc_interrupt_UNCONNECTED;
wire NLW_U0_ecc_ue_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_arready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_awready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_wready_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_bresp_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_ctrl_rdata_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_rresp_UNCONNECTED;
(* C_BRAM_ADDR_WIDTH = "11" *)
(* C_BRAM_INST_MODE = "EXTERNAL" *)
(* C_ECC = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "0" *)
(* C_ECC_TYPE = "0" *)
(* C_FAMILY = "zynq" *)
(* C_FAULT_INJECT = "0" *)
(* C_MEMORY_DEPTH = "2048" *)
(* C_SELECT_XPM = "0" *)
(* C_SINGLE_PORT_BRAM = "0" *)
(* C_S_AXI_ADDR_WIDTH = "13" *)
(* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_S_AXI_ID_WIDTH = "12" *)
(* C_S_AXI_PROTOCOL = "AXI4" *)
(* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl U0
(.bram_addr_a(bram_addr_a),
.bram_addr_b(bram_addr_b),
.bram_clk_a(bram_clk_a),
.bram_clk_b(bram_clk_b),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_a(bram_rddata_a),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_rst_b(bram_rst_b),
.bram_we_a(bram_we_a),
.bram_we_b(bram_we_b),
.bram_wrdata_a(bram_wrdata_a),
.bram_wrdata_b(bram_wrdata_b),
.ecc_interrupt(NLW_U0_ecc_interrupt_UNCONNECTED),
.ecc_ue(NLW_U0_ecc_ue_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_ctrl_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_arready(NLW_U0_s_axi_ctrl_arready_UNCONNECTED),
.s_axi_ctrl_arvalid(1'b0),
.s_axi_ctrl_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_awready(NLW_U0_s_axi_ctrl_awready_UNCONNECTED),
.s_axi_ctrl_awvalid(1'b0),
.s_axi_ctrl_bready(1'b0),
.s_axi_ctrl_bresp(NLW_U0_s_axi_ctrl_bresp_UNCONNECTED[1:0]),
.s_axi_ctrl_bvalid(NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED),
.s_axi_ctrl_rdata(NLW_U0_s_axi_ctrl_rdata_UNCONNECTED[31:0]),
.s_axi_ctrl_rready(1'b0),
.s_axi_ctrl_rresp(NLW_U0_s_axi_ctrl_rresp_UNCONNECTED[1:0]),
.s_axi_ctrl_rvalid(NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED),
.s_axi_ctrl_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_wready(NLW_U0_s_axi_ctrl_wready_UNCONNECTED),
.s_axi_ctrl_wvalid(1'b0),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "SRL_FIFO" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO
(E,
bid_gets_fifo_load,
bvalid_cnt_inc,
bid_gets_fifo_load_d1_reg,
D,
axi_wdata_full_cmb114_out,
SR,
s_axi_aclk,
\bvalid_cnt_reg[2] ,
wr_addr_sm_cs,
\bvalid_cnt_reg[2]_0 ,
\GEN_AWREADY.axi_aresetn_d2_reg ,
axi_awaddr_full,
bram_addr_ld_en,
bid_gets_fifo_load_d1,
s_axi_bready,
axi_bvalid_int_reg,
bvalid_cnt,
Q,
s_axi_awid,
\bvalid_cnt_reg[1] ,
aw_active,
s_axi_awready,
s_axi_awvalid,
curr_awlen_reg_1_or_2,
axi_awlen_pipe_1_or_2,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ,
last_data_ack_mod,
out,
axi_wr_burst,
s_axi_wvalid,
s_axi_wlast);
output [0:0]E;
output bid_gets_fifo_load;
output bvalid_cnt_inc;
output bid_gets_fifo_load_d1_reg;
output [11:0]D;
output axi_wdata_full_cmb114_out;
input [0:0]SR;
input s_axi_aclk;
input \bvalid_cnt_reg[2] ;
input wr_addr_sm_cs;
input \bvalid_cnt_reg[2]_0 ;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input axi_awaddr_full;
input bram_addr_ld_en;
input bid_gets_fifo_load_d1;
input s_axi_bready;
input axi_bvalid_int_reg;
input [2:0]bvalid_cnt;
input [11:0]Q;
input [11:0]s_axi_awid;
input \bvalid_cnt_reg[1] ;
input aw_active;
input s_axi_awready;
input s_axi_awvalid;
input curr_awlen_reg_1_or_2;
input axi_awlen_pipe_1_or_2;
input \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
input last_data_ack_mod;
input [2:0]out;
input axi_wr_burst;
input s_axi_wvalid;
input s_axi_wlast;
wire \Addr_Counters[0].FDRE_I_n_0 ;
wire \Addr_Counters[1].FDRE_I_n_0 ;
wire \Addr_Counters[2].FDRE_I_n_0 ;
wire \Addr_Counters[3].FDRE_I_n_0 ;
wire \Addr_Counters[3].XORCY_I_i_1_n_0 ;
wire CI;
wire [11:0]D;
wire D_0;
wire Data_Exists_DFF_i_2_n_0;
wire Data_Exists_DFF_i_3_n_0;
wire [0:0]E;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
wire [11:0]Q;
wire S;
wire S0_out;
wire S1_out;
wire [0:0]SR;
wire addr_cy_1;
wire addr_cy_2;
wire addr_cy_3;
wire aw_active;
wire axi_awaddr_full;
wire axi_awlen_pipe_1_or_2;
wire \axi_bid_int[11]_i_3_n_0 ;
wire axi_bvalid_int_i_4_n_0;
wire axi_bvalid_int_i_5_n_0;
wire axi_bvalid_int_i_6_n_0;
wire axi_bvalid_int_reg;
wire axi_wdata_full_cmb114_out;
wire axi_wr_burst;
wire [11:0]bid_fifo_ld;
wire bid_fifo_not_empty;
wire [11:0]bid_fifo_rd;
wire bid_gets_fifo_load;
wire bid_gets_fifo_load_d1;
wire bid_gets_fifo_load_d1_i_3_n_0;
wire bid_gets_fifo_load_d1_reg;
wire bram_addr_ld_en;
wire [2:0]bvalid_cnt;
wire bvalid_cnt_inc;
wire \bvalid_cnt_reg[1] ;
wire \bvalid_cnt_reg[2] ;
wire \bvalid_cnt_reg[2]_0 ;
wire curr_awlen_reg_1_or_2;
wire last_data_ack_mod;
wire [2:0]out;
wire s_axi_aclk;
wire [11:0]s_axi_awid;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_wlast;
wire s_axi_wvalid;
wire sum_A_0;
wire sum_A_1;
wire sum_A_2;
wire sum_A_3;
wire wr_addr_sm_cs;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[0].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_3),
.Q(\Addr_Counters[0].FDRE_I_n_0 ),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \Addr_Counters[0].MUXCY_L_I_CARRY4
(.CI(1'b0),
.CO({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED [3],addr_cy_1,addr_cy_2,addr_cy_3}),
.CYINIT(CI),
.DI({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED [3],\Addr_Counters[2].FDRE_I_n_0 ,\Addr_Counters[1].FDRE_I_n_0 ,\Addr_Counters[0].FDRE_I_n_0 }),
.O({sum_A_0,sum_A_1,sum_A_2,sum_A_3}),
.S({\Addr_Counters[3].XORCY_I_i_1_n_0 ,S0_out,S1_out,S}));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[0].MUXCY_L_I_i_1
(.I0(\Addr_Counters[1].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[0].FDRE_I_n_0 ),
.O(S));
LUT6 #(
.INIT(64'h8AAAAAAAAAAAAAAA))
\Addr_Counters[0].MUXCY_L_I_i_2
(.I0(bram_addr_ld_en),
.I1(\axi_bid_int[11]_i_3_n_0 ),
.I2(\Addr_Counters[0].FDRE_I_n_0 ),
.I3(\Addr_Counters[1].FDRE_I_n_0 ),
.I4(\Addr_Counters[3].FDRE_I_n_0 ),
.I5(\Addr_Counters[2].FDRE_I_n_0 ),
.O(CI));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[1].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_2),
.Q(\Addr_Counters[1].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[1].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[1].FDRE_I_n_0 ),
.O(S1_out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[2].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_1),
.Q(\Addr_Counters[2].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[2].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[2].FDRE_I_n_0 ),
.O(S0_out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[3].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_0),
.Q(\Addr_Counters[3].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[3].XORCY_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[3].FDRE_I_n_0 ),
.O(\Addr_Counters[3].XORCY_I_i_1_n_0 ));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
Data_Exists_DFF
(.C(s_axi_aclk),
.CE(1'b1),
.D(D_0),
.Q(bid_fifo_not_empty),
.R(SR));
LUT4 #(
.INIT(16'hFE0A))
Data_Exists_DFF_i_1
(.I0(bram_addr_ld_en),
.I1(Data_Exists_DFF_i_2_n_0),
.I2(Data_Exists_DFF_i_3_n_0),
.I3(bid_fifo_not_empty),
.O(D_0));
LUT6 #(
.INIT(64'h000000000000FFFD))
Data_Exists_DFF_i_2
(.I0(bvalid_cnt_inc),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.I3(bvalid_cnt[1]),
.I4(bid_gets_fifo_load_d1_reg),
.I5(bid_gets_fifo_load_d1),
.O(Data_Exists_DFF_i_2_n_0));
LUT4 #(
.INIT(16'hFFFE))
Data_Exists_DFF_i_3
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(\Addr_Counters[2].FDRE_I_n_0 ),
.O(Data_Exists_DFF_i_3_n_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[0].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[11]),
.Q(bid_fifo_rd[11]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[0].SRL16E_I_i_1
(.I0(Q[11]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[11]),
.O(bid_fifo_ld[11]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[10].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[10].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[1]),
.Q(bid_fifo_rd[1]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[10].SRL16E_I_i_1
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[1]),
.O(bid_fifo_ld[1]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[11].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[11].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[0]),
.Q(bid_fifo_rd[0]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[11].SRL16E_I_i_1
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[0]),
.O(bid_fifo_ld[0]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[1].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[1].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[10]),
.Q(bid_fifo_rd[10]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[1].SRL16E_I_i_1
(.I0(Q[10]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[10]),
.O(bid_fifo_ld[10]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[2].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[2].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[9]),
.Q(bid_fifo_rd[9]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[2].SRL16E_I_i_1
(.I0(Q[9]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[9]),
.O(bid_fifo_ld[9]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[3].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[3].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[8]),
.Q(bid_fifo_rd[8]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[3].SRL16E_I_i_1
(.I0(Q[8]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[8]),
.O(bid_fifo_ld[8]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[4].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[4].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[7]),
.Q(bid_fifo_rd[7]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[4].SRL16E_I_i_1
(.I0(Q[7]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[7]),
.O(bid_fifo_ld[7]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[5].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[5].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[6]),
.Q(bid_fifo_rd[6]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[5].SRL16E_I_i_1
(.I0(Q[6]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[6]),
.O(bid_fifo_ld[6]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[6].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[6].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[5]),
.Q(bid_fifo_rd[5]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[6].SRL16E_I_i_1
(.I0(Q[5]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[5]),
.O(bid_fifo_ld[5]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[7].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[7].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[4]),
.Q(bid_fifo_rd[4]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[7].SRL16E_I_i_1
(.I0(Q[4]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[4]),
.O(bid_fifo_ld[4]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[8].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[8].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[3]),
.Q(bid_fifo_rd[3]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[8].SRL16E_I_i_1
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[3]),
.O(bid_fifo_ld[3]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[9].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[9].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[2]),
.Q(bid_fifo_rd[2]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[9].SRL16E_I_i_1
(.I0(Q[2]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[2]),
.O(bid_fifo_ld[2]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[0]_i_1
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[0]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[0]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[10]_i_1
(.I0(Q[10]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[10]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[10]),
.O(D[10]));
LUT2 #(
.INIT(4'hE))
\axi_bid_int[11]_i_1
(.I0(bid_gets_fifo_load),
.I1(\axi_bid_int[11]_i_3_n_0 ),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[11]_i_2
(.I0(Q[11]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[11]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[11]),
.O(D[11]));
LUT6 #(
.INIT(64'hA888AAAAA8888888))
\axi_bid_int[11]_i_3
(.I0(bid_fifo_not_empty),
.I1(bid_gets_fifo_load_d1),
.I2(s_axi_bready),
.I3(axi_bvalid_int_reg),
.I4(bid_gets_fifo_load_d1_i_3_n_0),
.I5(bvalid_cnt_inc),
.O(\axi_bid_int[11]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[1]_i_1
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[1]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[2]_i_1
(.I0(Q[2]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[2]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[2]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[3]_i_1
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[3]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[3]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[4]_i_1
(.I0(Q[4]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[4]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[4]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[5]_i_1
(.I0(Q[5]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[5]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[5]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[6]_i_1
(.I0(Q[6]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[6]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[6]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[7]_i_1
(.I0(Q[7]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[7]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[8]_i_1
(.I0(Q[8]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[8]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[8]),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[9]_i_1
(.I0(Q[9]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[9]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[9]),
.O(D[9]));
LUT6 #(
.INIT(64'h000055FD00000000))
axi_bvalid_int_i_2
(.I0(out[2]),
.I1(axi_wdata_full_cmb114_out),
.I2(axi_bvalid_int_i_4_n_0),
.I3(axi_wr_burst),
.I4(out[1]),
.I5(axi_bvalid_int_i_5_n_0),
.O(bvalid_cnt_inc));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT5 #(
.INIT(32'hFE000000))
axi_bvalid_int_i_3
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.I3(axi_bvalid_int_reg),
.I4(s_axi_bready),
.O(bid_gets_fifo_load_d1_reg));
LUT6 #(
.INIT(64'h1F11000000000000))
axi_bvalid_int_i_4
(.I0(axi_bvalid_int_i_6_n_0),
.I1(\bvalid_cnt_reg[2] ),
.I2(wr_addr_sm_cs),
.I3(\bvalid_cnt_reg[2]_0 ),
.I4(\GEN_AWREADY.axi_aresetn_d2_reg ),
.I5(axi_awaddr_full),
.O(axi_bvalid_int_i_4_n_0));
LUT5 #(
.INIT(32'h74446444))
axi_bvalid_int_i_5
(.I0(out[0]),
.I1(out[2]),
.I2(s_axi_wvalid),
.I3(s_axi_wlast),
.I4(axi_wdata_full_cmb114_out),
.O(axi_bvalid_int_i_5_n_0));
LUT5 #(
.INIT(32'hFEFFFFFF))
axi_bvalid_int_i_6
(.I0(curr_awlen_reg_1_or_2),
.I1(axi_awlen_pipe_1_or_2),
.I2(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ),
.I3(axi_awaddr_full),
.I4(last_data_ack_mod),
.O(axi_bvalid_int_i_6_n_0));
LUT6 #(
.INIT(64'h7F7F7F007F007F00))
axi_wready_int_mod_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.I3(aw_active),
.I4(s_axi_awready),
.I5(s_axi_awvalid),
.O(axi_wdata_full_cmb114_out));
LUT6 #(
.INIT(64'h00000800AA00AA00))
bid_gets_fifo_load_d1_i_1
(.I0(bram_addr_ld_en),
.I1(bid_gets_fifo_load_d1_reg),
.I2(bid_fifo_not_empty),
.I3(bvalid_cnt_inc),
.I4(\bvalid_cnt_reg[1] ),
.I5(bid_gets_fifo_load_d1_i_3_n_0),
.O(bid_gets_fifo_load));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hFE))
bid_gets_fifo_load_d1_i_3
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.O(bid_gets_fifo_load_d1_i_3_n_0));
endmodule
(* C_BRAM_ADDR_WIDTH = "11" *) (* C_BRAM_INST_MODE = "EXTERNAL" *) (* C_ECC = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "0" *) (* C_ECC_TYPE = "0" *) (* C_FAMILY = "zynq" *)
(* C_FAULT_INJECT = "0" *) (* C_MEMORY_DEPTH = "2048" *) (* C_SELECT_XPM = "0" *)
(* C_SINGLE_PORT_BRAM = "0" *) (* C_S_AXI_ADDR_WIDTH = "13" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_S_AXI_DATA_WIDTH = "32" *) (* C_S_AXI_ID_WIDTH = "12" *)
(* C_S_AXI_PROTOCOL = "AXI4" *) (* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *) (* ORIG_REF_NAME = "axi_bram_ctrl" *)
(* downgradeipidentifiedwarnings = "yes" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl
(s_axi_aclk,
s_axi_aresetn,
ecc_interrupt,
ecc_ue,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_ctrl_awvalid,
s_axi_ctrl_awready,
s_axi_ctrl_awaddr,
s_axi_ctrl_wdata,
s_axi_ctrl_wvalid,
s_axi_ctrl_wready,
s_axi_ctrl_bresp,
s_axi_ctrl_bvalid,
s_axi_ctrl_bready,
s_axi_ctrl_araddr,
s_axi_ctrl_arvalid,
s_axi_ctrl_arready,
s_axi_ctrl_rdata,
s_axi_ctrl_rresp,
s_axi_ctrl_rvalid,
s_axi_ctrl_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
input s_axi_aclk;
input s_axi_aresetn;
output ecc_interrupt;
output ecc_ue;
input [11:0]s_axi_awid;
input [12:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [12:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_ctrl_awvalid;
output s_axi_ctrl_awready;
input [31:0]s_axi_ctrl_awaddr;
input [31:0]s_axi_ctrl_wdata;
input s_axi_ctrl_wvalid;
output s_axi_ctrl_wready;
output [1:0]s_axi_ctrl_bresp;
output s_axi_ctrl_bvalid;
input s_axi_ctrl_bready;
input [31:0]s_axi_ctrl_araddr;
input s_axi_ctrl_arvalid;
output s_axi_ctrl_arready;
output [31:0]s_axi_ctrl_rdata;
output [1:0]s_axi_ctrl_rresp;
output s_axi_ctrl_rvalid;
input s_axi_ctrl_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [12:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [12:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
wire \<const0> ;
wire [12:2]\^bram_addr_a ;
wire [12:2]\^bram_addr_b ;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [12:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [12:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign bram_addr_a[12:2] = \^bram_addr_a [12:2];
assign bram_addr_a[1] = \<const0> ;
assign bram_addr_a[0] = \<const0> ;
assign bram_addr_b[12:2] = \^bram_addr_b [12:2];
assign bram_addr_b[1] = \<const0> ;
assign bram_addr_b[0] = \<const0> ;
assign bram_clk_a = s_axi_aclk;
assign bram_clk_b = s_axi_aclk;
assign bram_rst_b = bram_rst_a;
assign bram_we_b[3] = \<const0> ;
assign bram_we_b[2] = \<const0> ;
assign bram_we_b[1] = \<const0> ;
assign bram_we_b[0] = \<const0> ;
assign bram_wrdata_b[31] = \<const0> ;
assign bram_wrdata_b[30] = \<const0> ;
assign bram_wrdata_b[29] = \<const0> ;
assign bram_wrdata_b[28] = \<const0> ;
assign bram_wrdata_b[27] = \<const0> ;
assign bram_wrdata_b[26] = \<const0> ;
assign bram_wrdata_b[25] = \<const0> ;
assign bram_wrdata_b[24] = \<const0> ;
assign bram_wrdata_b[23] = \<const0> ;
assign bram_wrdata_b[22] = \<const0> ;
assign bram_wrdata_b[21] = \<const0> ;
assign bram_wrdata_b[20] = \<const0> ;
assign bram_wrdata_b[19] = \<const0> ;
assign bram_wrdata_b[18] = \<const0> ;
assign bram_wrdata_b[17] = \<const0> ;
assign bram_wrdata_b[16] = \<const0> ;
assign bram_wrdata_b[15] = \<const0> ;
assign bram_wrdata_b[14] = \<const0> ;
assign bram_wrdata_b[13] = \<const0> ;
assign bram_wrdata_b[12] = \<const0> ;
assign bram_wrdata_b[11] = \<const0> ;
assign bram_wrdata_b[10] = \<const0> ;
assign bram_wrdata_b[9] = \<const0> ;
assign bram_wrdata_b[8] = \<const0> ;
assign bram_wrdata_b[7] = \<const0> ;
assign bram_wrdata_b[6] = \<const0> ;
assign bram_wrdata_b[5] = \<const0> ;
assign bram_wrdata_b[4] = \<const0> ;
assign bram_wrdata_b[3] = \<const0> ;
assign bram_wrdata_b[2] = \<const0> ;
assign bram_wrdata_b[1] = \<const0> ;
assign bram_wrdata_b[0] = \<const0> ;
assign ecc_interrupt = \<const0> ;
assign ecc_ue = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_ctrl_arready = \<const0> ;
assign s_axi_ctrl_awready = \<const0> ;
assign s_axi_ctrl_bresp[1] = \<const0> ;
assign s_axi_ctrl_bresp[0] = \<const0> ;
assign s_axi_ctrl_bvalid = \<const0> ;
assign s_axi_ctrl_rdata[31] = \<const0> ;
assign s_axi_ctrl_rdata[30] = \<const0> ;
assign s_axi_ctrl_rdata[29] = \<const0> ;
assign s_axi_ctrl_rdata[28] = \<const0> ;
assign s_axi_ctrl_rdata[27] = \<const0> ;
assign s_axi_ctrl_rdata[26] = \<const0> ;
assign s_axi_ctrl_rdata[25] = \<const0> ;
assign s_axi_ctrl_rdata[24] = \<const0> ;
assign s_axi_ctrl_rdata[23] = \<const0> ;
assign s_axi_ctrl_rdata[22] = \<const0> ;
assign s_axi_ctrl_rdata[21] = \<const0> ;
assign s_axi_ctrl_rdata[20] = \<const0> ;
assign s_axi_ctrl_rdata[19] = \<const0> ;
assign s_axi_ctrl_rdata[18] = \<const0> ;
assign s_axi_ctrl_rdata[17] = \<const0> ;
assign s_axi_ctrl_rdata[16] = \<const0> ;
assign s_axi_ctrl_rdata[15] = \<const0> ;
assign s_axi_ctrl_rdata[14] = \<const0> ;
assign s_axi_ctrl_rdata[13] = \<const0> ;
assign s_axi_ctrl_rdata[12] = \<const0> ;
assign s_axi_ctrl_rdata[11] = \<const0> ;
assign s_axi_ctrl_rdata[10] = \<const0> ;
assign s_axi_ctrl_rdata[9] = \<const0> ;
assign s_axi_ctrl_rdata[8] = \<const0> ;
assign s_axi_ctrl_rdata[7] = \<const0> ;
assign s_axi_ctrl_rdata[6] = \<const0> ;
assign s_axi_ctrl_rdata[5] = \<const0> ;
assign s_axi_ctrl_rdata[4] = \<const0> ;
assign s_axi_ctrl_rdata[3] = \<const0> ;
assign s_axi_ctrl_rdata[2] = \<const0> ;
assign s_axi_ctrl_rdata[1] = \<const0> ;
assign s_axi_ctrl_rdata[0] = \<const0> ;
assign s_axi_ctrl_rresp[1] = \<const0> ;
assign s_axi_ctrl_rresp[0] = \<const0> ;
assign s_axi_ctrl_rvalid = \<const0> ;
assign s_axi_ctrl_wready = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
GND GND
(.G(\<const0> ));
zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top \gext_inst.abcv4_0_ext_inst
(.bram_addr_a(\^bram_addr_a ),
.bram_addr_b(\^bram_addr_b ),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[12:2]),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[12:2]),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi_bram_ctrl_top" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top
(s_axi_rvalid,
s_axi_rlast,
s_axi_bvalid,
s_axi_awready,
bram_rst_a,
bram_addr_a,
s_axi_bid,
bram_en_a,
bram_we_a,
bram_wrdata_a,
bram_addr_b,
s_axi_rid,
s_axi_rdata,
s_axi_wready,
s_axi_arready,
bram_en_b,
s_axi_aresetn,
s_axi_wvalid,
s_axi_wlast,
s_axi_rready,
s_axi_bready,
s_axi_awburst,
s_axi_aclk,
s_axi_awlen,
s_axi_awaddr,
s_axi_awid,
s_axi_wstrb,
s_axi_wdata,
s_axi_arlen,
s_axi_araddr,
s_axi_arid,
bram_rddata_b,
s_axi_arburst,
s_axi_awvalid,
s_axi_arvalid);
output s_axi_rvalid;
output s_axi_rlast;
output s_axi_bvalid;
output s_axi_awready;
output bram_rst_a;
output [10:0]bram_addr_a;
output [11:0]s_axi_bid;
output bram_en_a;
output [3:0]bram_we_a;
output [31:0]bram_wrdata_a;
output [10:0]bram_addr_b;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output s_axi_wready;
output s_axi_arready;
output bram_en_b;
input s_axi_aresetn;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_aclk;
input [7:0]s_axi_awlen;
input [10:0]s_axi_awaddr;
input [11:0]s_axi_awid;
input [3:0]s_axi_wstrb;
input [31:0]s_axi_wdata;
input [7:0]s_axi_arlen;
input [10:0]s_axi_araddr;
input [11:0]s_axi_arid;
input [31:0]bram_rddata_b;
input [1:0]s_axi_arburst;
input s_axi_awvalid;
input s_axi_arvalid;
wire [10:0]bram_addr_a;
wire [10:0]bram_addr_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [10:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [10:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi \GEN_AXI4.I_FULL_AXI
(.bram_addr_a(bram_addr_a),
.bram_addr_b(bram_addr_b),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "full_axi" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi
(s_axi_rvalid,
s_axi_rlast,
s_axi_bvalid,
s_axi_awready,
bram_rst_a,
bram_addr_a,
s_axi_bid,
bram_en_a,
bram_we_a,
bram_wrdata_a,
bram_addr_b,
s_axi_rid,
s_axi_rdata,
s_axi_wready,
s_axi_arready,
bram_en_b,
s_axi_aresetn,
s_axi_wvalid,
s_axi_wlast,
s_axi_rready,
s_axi_bready,
s_axi_awburst,
s_axi_aclk,
s_axi_awlen,
s_axi_awaddr,
s_axi_awid,
s_axi_wstrb,
s_axi_wdata,
s_axi_arlen,
s_axi_araddr,
s_axi_arid,
bram_rddata_b,
s_axi_arburst,
s_axi_awvalid,
s_axi_arvalid);
output s_axi_rvalid;
output s_axi_rlast;
output s_axi_bvalid;
output s_axi_awready;
output bram_rst_a;
output [10:0]bram_addr_a;
output [11:0]s_axi_bid;
output bram_en_a;
output [3:0]bram_we_a;
output [31:0]bram_wrdata_a;
output [10:0]bram_addr_b;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output s_axi_wready;
output s_axi_arready;
output bram_en_b;
input s_axi_aresetn;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_aclk;
input [7:0]s_axi_awlen;
input [10:0]s_axi_awaddr;
input [11:0]s_axi_awid;
input [3:0]s_axi_wstrb;
input [31:0]s_axi_wdata;
input [7:0]s_axi_arlen;
input [10:0]s_axi_araddr;
input [11:0]s_axi_arid;
input [31:0]bram_rddata_b;
input [1:0]s_axi_arburst;
input s_axi_awvalid;
input s_axi_arvalid;
wire I_WR_CHNL_n_36;
wire axi_aresetn_d2;
wire axi_aresetn_re_reg;
wire [10:0]bram_addr_a;
wire [10:0]bram_addr_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [10:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [10:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl I_RD_CHNL
(.\GEN_AWREADY.axi_aresetn_d2_reg (I_WR_CHNL_n_36),
.Q(bram_addr_b[9:0]),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_aresetn_re_reg(axi_aresetn_re_reg),
.bram_addr_b(bram_addr_b[10]),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl I_WR_CHNL
(.\GEN_AW_DUAL.aw_active_reg_0 (I_WR_CHNL_n_36),
.SR(bram_rst_a),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_aresetn_re_reg(axi_aresetn_re_reg),
.bram_addr_a(bram_addr_a),
.bram_en_a(bram_en_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "rd_chnl" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl
(bram_rst_a,
s_axi_rdata,
s_axi_rlast,
s_axi_rvalid,
bram_en_b,
Q,
s_axi_arready,
bram_addr_b,
s_axi_rid,
s_axi_araddr,
s_axi_aclk,
\GEN_AWREADY.axi_aresetn_d2_reg ,
s_axi_rready,
s_axi_aresetn,
s_axi_arlen,
axi_aresetn_d2,
s_axi_arvalid,
axi_aresetn_re_reg,
s_axi_arid,
s_axi_arburst,
bram_rddata_b);
output bram_rst_a;
output [31:0]s_axi_rdata;
output s_axi_rlast;
output s_axi_rvalid;
output bram_en_b;
output [9:0]Q;
output s_axi_arready;
output [0:0]bram_addr_b;
output [11:0]s_axi_rid;
input [10:0]s_axi_araddr;
input s_axi_aclk;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input s_axi_rready;
input s_axi_aresetn;
input [7:0]s_axi_arlen;
input axi_aresetn_d2;
input s_axi_arvalid;
input axi_aresetn_re_reg;
input [11:0]s_axi_arid;
input [1:0]s_axi_arburst;
input [31:0]bram_rddata_b;
wire \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ;
wire \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ;
wire \/i__n_0 ;
wire \FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ;
wire \FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ;
wire \FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ;
wire \GEN_ARREADY.axi_arready_int_i_1_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_2_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_3_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_1_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_2_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_3_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_4_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_5_n_0 ;
wire \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ;
wire \GEN_RID.axi_rid_int[11]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp2_full_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[0]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[10]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[11]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[11]_i_2_n_0 ;
wire \GEN_RID.axi_rid_temp[1]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[2]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[3]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[4]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[5]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[6]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[7]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[8]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[9]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp_full_i_1_n_0 ;
wire I_WRAP_BRST_n_0;
wire I_WRAP_BRST_n_10;
wire I_WRAP_BRST_n_11;
wire I_WRAP_BRST_n_12;
wire I_WRAP_BRST_n_13;
wire I_WRAP_BRST_n_14;
wire I_WRAP_BRST_n_15;
wire I_WRAP_BRST_n_16;
wire I_WRAP_BRST_n_17;
wire I_WRAP_BRST_n_18;
wire I_WRAP_BRST_n_2;
wire I_WRAP_BRST_n_20;
wire I_WRAP_BRST_n_21;
wire I_WRAP_BRST_n_22;
wire I_WRAP_BRST_n_23;
wire I_WRAP_BRST_n_24;
wire I_WRAP_BRST_n_25;
wire I_WRAP_BRST_n_3;
wire I_WRAP_BRST_n_4;
wire I_WRAP_BRST_n_5;
wire I_WRAP_BRST_n_6;
wire I_WRAP_BRST_n_7;
wire I_WRAP_BRST_n_8;
wire I_WRAP_BRST_n_9;
wire [9:0]Q;
wire act_rd_burst;
wire act_rd_burst_i_1_n_0;
wire act_rd_burst_i_3_n_0;
wire act_rd_burst_i_4_n_0;
wire act_rd_burst_set;
wire act_rd_burst_two;
wire act_rd_burst_two_i_1_n_0;
wire ar_active;
wire araddr_pipe_ld43_out;
wire axi_araddr_full;
wire [1:0]axi_arburst_pipe;
wire axi_aresetn_d2;
wire axi_aresetn_re_reg;
wire [11:0]axi_arid_pipe;
wire [7:0]axi_arlen_pipe;
wire axi_arlen_pipe_1_or_2;
wire axi_arready_int;
wire [1:1]axi_arsize_pipe;
wire axi_arsize_pipe_max;
wire axi_arsize_pipe_max_i_1_n_0;
wire axi_b2b_brst;
wire axi_b2b_brst_i_1_n_0;
wire axi_b2b_brst_i_3_n_0;
wire axi_early_arready_int;
wire axi_rd_burst;
wire axi_rd_burst_i_1_n_0;
wire axi_rd_burst_i_2_n_0;
wire axi_rd_burst_i_3_n_0;
wire axi_rd_burst_two;
wire axi_rd_burst_two_i_1_n_0;
wire axi_rd_burst_two_reg_n_0;
wire [11:0]axi_rid_temp;
wire [11:0]axi_rid_temp2;
wire [11:0]axi_rid_temp20_in;
wire axi_rid_temp2_full;
wire axi_rid_temp_full;
wire axi_rid_temp_full_d1;
wire axi_rlast_int_i_1_n_0;
wire axi_rlast_set;
wire axi_rvalid_clr_ok;
wire axi_rvalid_clr_ok_i_1_n_0;
wire axi_rvalid_clr_ok_i_2_n_0;
wire axi_rvalid_clr_ok_i_3_n_0;
wire axi_rvalid_int_i_1_n_0;
wire axi_rvalid_set;
wire axi_rvalid_set_cmb;
wire [0:0]bram_addr_b;
wire bram_addr_ld_en;
wire bram_en_b;
wire bram_en_int_i_10_n_0;
wire bram_en_int_i_11_n_0;
wire bram_en_int_i_1_n_0;
wire bram_en_int_i_2_n_0;
wire bram_en_int_i_3_n_0;
wire bram_en_int_i_4_n_0;
wire bram_en_int_i_6_n_0;
wire bram_en_int_i_7_n_0;
wire bram_en_int_i_9_n_0;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [7:0]brst_cnt;
wire \brst_cnt[0]_i_1_n_0 ;
wire \brst_cnt[1]_i_1_n_0 ;
wire \brst_cnt[2]_i_1_n_0 ;
wire \brst_cnt[3]_i_1_n_0 ;
wire \brst_cnt[4]_i_1_n_0 ;
wire \brst_cnt[4]_i_2_n_0 ;
wire \brst_cnt[5]_i_1_n_0 ;
wire \brst_cnt[6]_i_1_n_0 ;
wire \brst_cnt[6]_i_2_n_0 ;
wire \brst_cnt[7]_i_1_n_0 ;
wire \brst_cnt[7]_i_2_n_0 ;
wire \brst_cnt[7]_i_3_n_0 ;
wire \brst_cnt[7]_i_4_n_0 ;
wire brst_cnt_max;
wire brst_cnt_max_d1;
wire brst_one;
wire brst_one0;
wire brst_one_i_1_n_0;
wire brst_zero;
wire brst_zero_i_1_n_0;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire disable_b2b_brst;
wire disable_b2b_brst_cmb;
wire disable_b2b_brst_i_2_n_0;
wire disable_b2b_brst_i_3_n_0;
wire disable_b2b_brst_i_4_n_0;
wire end_brst_rd;
wire end_brst_rd_clr;
wire end_brst_rd_clr_i_1_n_0;
wire end_brst_rd_i_1_n_0;
wire last_bram_addr;
wire last_bram_addr0;
wire last_bram_addr_i_10_n_0;
wire last_bram_addr_i_2_n_0;
wire last_bram_addr_i_3_n_0;
wire last_bram_addr_i_4_n_0;
wire last_bram_addr_i_5_n_0;
wire last_bram_addr_i_6_n_0;
wire last_bram_addr_i_7_n_0;
wire last_bram_addr_i_8_n_0;
wire last_bram_addr_i_9_n_0;
wire no_ar_ack;
wire no_ar_ack_i_1_n_0;
wire p_0_in13_in;
wire p_13_out;
wire p_26_out;
wire p_48_out;
wire p_4_out;
wire p_9_out;
wire pend_rd_op;
wire pend_rd_op_i_1_n_0;
wire pend_rd_op_i_2_n_0;
wire pend_rd_op_i_3_n_0;
wire pend_rd_op_i_4_n_0;
wire pend_rd_op_i_5_n_0;
wire pend_rd_op_i_6_n_0;
wire pend_rd_op_i_7_n_0;
wire rd_addr_sm_cs;
wire rd_adv_buf67_out;
wire [3:0]rd_data_sm_cs;
wire \rd_data_sm_cs[0]_i_1_n_0 ;
wire \rd_data_sm_cs[0]_i_2_n_0 ;
wire \rd_data_sm_cs[0]_i_3_n_0 ;
wire \rd_data_sm_cs[0]_i_4_n_0 ;
wire \rd_data_sm_cs[1]_i_1_n_0 ;
wire \rd_data_sm_cs[1]_i_3_n_0 ;
wire \rd_data_sm_cs[2]_i_1_n_0 ;
wire \rd_data_sm_cs[2]_i_2_n_0 ;
wire \rd_data_sm_cs[2]_i_3_n_0 ;
wire \rd_data_sm_cs[2]_i_4_n_0 ;
wire \rd_data_sm_cs[2]_i_5_n_0 ;
wire \rd_data_sm_cs[3]_i_2_n_0 ;
wire \rd_data_sm_cs[3]_i_3_n_0 ;
wire \rd_data_sm_cs[3]_i_4_n_0 ;
wire \rd_data_sm_cs[3]_i_5_n_0 ;
wire \rd_data_sm_cs[3]_i_6_n_0 ;
wire \rd_data_sm_cs[3]_i_7_n_0 ;
wire rd_data_sm_ns;
wire [31:0]rd_skid_buf;
wire rd_skid_buf_ld;
wire rd_skid_buf_ld_cmb;
wire rd_skid_buf_ld_reg;
wire rddata_mux_sel;
wire rddata_mux_sel_cmb;
wire rddata_mux_sel_i_1_n_0;
wire rddata_mux_sel_i_3_n_0;
(* RTL_KEEP = "yes" *) wire [2:0]rlast_sm_cs;
wire s_axi_aclk;
wire [10:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
LUT6 #(
.INIT(64'h0011001300130013))
\/FSM_sequential_rlast_sm_cs[0]_i_2
(.I0(axi_rd_burst),
.I1(rlast_sm_cs[1]),
.I2(act_rd_burst_two),
.I3(axi_rd_burst_two_reg_n_0),
.I4(s_axi_rvalid),
.I5(s_axi_rready),
.O(\/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h003F007F003F0055))
\/FSM_sequential_rlast_sm_cs[1]_i_2
(.I0(axi_rd_burst),
.I1(s_axi_rready),
.I2(s_axi_rvalid),
.I3(rlast_sm_cs[1]),
.I4(axi_rd_burst_two_reg_n_0),
.I5(act_rd_burst_two),
.O(\/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF000F111F000E000))
\/i_
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[1]),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(rlast_sm_cs[0]),
.I5(last_bram_addr),
.O(\/i__n_0 ));
LUT6 #(
.INIT(64'h00008080000F8080))
\/i___0
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(rlast_sm_cs[0]),
.I3(rlast_sm_cs[1]),
.I4(rlast_sm_cs[2]),
.I5(s_axi_rlast),
.O(axi_rlast_set));
LUT5 #(
.INIT(32'h01FF0100))
\FSM_sequential_rlast_sm_cs[0]_i_1
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[0]),
.I2(\/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ),
.I3(\/i__n_0 ),
.I4(rlast_sm_cs[0]),
.O(\FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h01FF0100))
\FSM_sequential_rlast_sm_cs[1]_i_1
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[0]),
.I2(\/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ),
.I3(\/i__n_0 ),
.I4(rlast_sm_cs[1]),
.O(\FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00A4FFFF00A40000))
\FSM_sequential_rlast_sm_cs[2]_i_1
(.I0(rlast_sm_cs[1]),
.I1(p_0_in13_in),
.I2(rlast_sm_cs[0]),
.I3(rlast_sm_cs[2]),
.I4(\/i__n_0 ),
.I5(rlast_sm_cs[2]),
.O(\FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ));
LUT2 #(
.INIT(4'h1))
\FSM_sequential_rlast_sm_cs[2]_i_2
(.I0(axi_rd_burst_two_reg_n_0),
.I1(axi_rd_burst),
.O(p_0_in13_in));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ),
.Q(rlast_sm_cs[0]),
.R(bram_rst_a));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ),
.Q(rlast_sm_cs[1]),
.R(bram_rst_a));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ),
.Q(rlast_sm_cs[2]),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hAAAAAEEE))
\GEN_ARREADY.axi_arready_int_i_1
(.I0(p_9_out),
.I1(axi_arready_int),
.I2(s_axi_arvalid),
.I3(axi_araddr_full),
.I4(araddr_pipe_ld43_out),
.O(\GEN_ARREADY.axi_arready_int_i_1_n_0 ));
LUT4 #(
.INIT(16'hBAAA))
\GEN_ARREADY.axi_arready_int_i_2
(.I0(axi_aresetn_re_reg),
.I1(axi_early_arready_int),
.I2(axi_araddr_full),
.I3(bram_addr_ld_en),
.O(p_9_out));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_ARREADY.axi_arready_int_i_1_n_0 ),
.Q(axi_arready_int),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h0000000000000200))
\GEN_ARREADY.axi_early_arready_int_i_1
(.I0(\GEN_ARREADY.axi_early_arready_int_i_2_n_0 ),
.I1(\GEN_ARREADY.axi_early_arready_int_i_3_n_0 ),
.I2(rd_data_sm_cs[3]),
.I3(brst_one),
.I4(axi_arready_int),
.I5(I_WRAP_BRST_n_23),
.O(p_48_out));
LUT6 #(
.INIT(64'h00CC304400000044))
\GEN_ARREADY.axi_early_arready_int_i_2
(.I0(axi_rd_burst_two_reg_n_0),
.I1(rd_data_sm_cs[1]),
.I2(\rd_data_sm_cs[2]_i_5_n_0 ),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[0]),
.I5(rd_adv_buf67_out),
.O(\GEN_ARREADY.axi_early_arready_int_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h7))
\GEN_ARREADY.axi_early_arready_int_i_3
(.I0(axi_araddr_full),
.I1(s_axi_arvalid),
.O(\GEN_ARREADY.axi_early_arready_int_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_early_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_48_out),
.Q(axi_early_arready_int),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hCDCDCDDDCCCCCCCC))
\GEN_AR_DUAL.ar_active_i_1
(.I0(\GEN_AR_DUAL.ar_active_i_2_n_0 ),
.I1(bram_addr_ld_en),
.I2(\GEN_AR_DUAL.ar_active_i_3_n_0 ),
.I3(end_brst_rd),
.I4(brst_zero),
.I5(ar_active),
.O(\GEN_AR_DUAL.ar_active_i_1_n_0 ));
LUT6 #(
.INIT(64'h808880808088A280))
\GEN_AR_DUAL.ar_active_i_2
(.I0(\GEN_AR_DUAL.ar_active_i_4_n_0 ),
.I1(rd_data_sm_cs[1]),
.I2(\GEN_AR_DUAL.ar_active_i_5_n_0 ),
.I3(rd_data_sm_cs[0]),
.I4(axi_rd_burst_two_reg_n_0),
.I5(axi_rd_burst),
.O(\GEN_AR_DUAL.ar_active_i_2_n_0 ));
LUT6 #(
.INIT(64'h0010000000000000))
\GEN_AR_DUAL.ar_active_i_3
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(s_axi_rvalid),
.I5(s_axi_rready),
.O(\GEN_AR_DUAL.ar_active_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h1))
\GEN_AR_DUAL.ar_active_i_4
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.O(\GEN_AR_DUAL.ar_active_i_4_n_0 ));
LUT6 #(
.INIT(64'h8A88000000000000))
\GEN_AR_DUAL.ar_active_i_5
(.I0(I_WRAP_BRST_n_24),
.I1(brst_zero),
.I2(axi_b2b_brst),
.I3(end_brst_rd),
.I4(rd_adv_buf67_out),
.I5(rd_data_sm_cs[0]),
.O(\GEN_AR_DUAL.ar_active_i_5_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_DUAL.ar_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_DUAL.ar_active_i_1_n_0 ),
.Q(ar_active),
.R(\GEN_AWREADY.axi_aresetn_d2_reg ));
LUT6 #(
.INIT(64'h10001000F0F01000))
\GEN_AR_DUAL.rd_addr_sm_cs_i_1
(.I0(rd_addr_sm_cs),
.I1(axi_araddr_full),
.I2(s_axi_arvalid),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ),
.I4(last_bram_addr),
.I5(I_WRAP_BRST_n_23),
.O(\GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ));
FDRE \GEN_AR_DUAL.rd_addr_sm_cs_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ),
.Q(rd_addr_sm_cs),
.R(\GEN_AWREADY.axi_aresetn_d2_reg ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[8]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[9]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[10]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[0]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[1]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[2]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[3]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[4]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[5]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[6]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[7]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.R(1'b0));
LUT6 #(
.INIT(64'h00C08888CCCC8888))
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1
(.I0(araddr_pipe_ld43_out),
.I1(s_axi_aresetn),
.I2(s_axi_arvalid),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ),
.I4(axi_araddr_full),
.I5(bram_addr_ld_en),
.O(\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ),
.Q(axi_araddr_full),
.R(1'b0));
LUT4 #(
.INIT(16'h03AA))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1
(.I0(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.I1(s_axi_arburst[0]),
.I2(s_axi_arburst[1]),
.I3(araddr_pipe_ld43_out),
.O(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ),
.Q(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arburst[0]),
.Q(axi_arburst_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arburst[1]),
.Q(axi_arburst_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[0]),
.Q(axi_arid_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[10]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[10]),
.Q(axi_arid_pipe[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[11]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[11]),
.Q(axi_arid_pipe[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[1]),
.Q(axi_arid_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[2]),
.Q(axi_arid_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[3]),
.Q(axi_arid_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[4]),
.Q(axi_arid_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[5]),
.Q(axi_arid_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[6]),
.Q(axi_arid_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[7]),
.Q(axi_arid_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[8]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[8]),
.Q(axi_arid_pipe[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[9]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[9]),
.Q(axi_arid_pipe[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h220022002A002200))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1
(.I0(axi_aresetn_d2),
.I1(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ),
.I2(rd_addr_sm_cs),
.I3(s_axi_arvalid),
.I4(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ),
.I5(axi_araddr_full),
.O(araddr_pipe_ld43_out));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'hB))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2
(.I0(I_WRAP_BRST_n_23),
.I1(last_bram_addr),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hFE))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3
(.I0(no_ar_ack),
.I1(pend_rd_op),
.I2(ar_active),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ));
LUT4 #(
.INIT(16'h0001))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1
(.I0(s_axi_arlen[7]),
.I1(s_axi_arlen[1]),
.I2(s_axi_arlen[3]),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ),
.O(p_13_out));
LUT4 #(
.INIT(16'hFFFE))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2
(.I0(s_axi_arlen[5]),
.I1(s_axi_arlen[4]),
.I2(s_axi_arlen[2]),
.I3(s_axi_arlen[6]),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(p_13_out),
.Q(axi_arlen_pipe_1_or_2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[0]),
.Q(axi_arlen_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[1]),
.Q(axi_arlen_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[2]),
.Q(axi_arlen_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[3]),
.Q(axi_arlen_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[4]),
.Q(axi_arlen_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[5]),
.Q(axi_arlen_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[6]),
.Q(axi_arlen_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[7]),
.Q(axi_arlen_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(1'b1),
.Q(axi_arsize_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000BAAA0000))
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1
(.I0(brst_cnt_max),
.I1(pend_rd_op),
.I2(ar_active),
.I3(brst_zero),
.I4(s_axi_aresetn),
.I5(bram_addr_ld_en),
.O(\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ),
.Q(brst_cnt_max),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2
(.I0(Q[4]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[3]),
.I5(Q[5]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'hF7FFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0
(.I0(Q[6]),
.I1(Q[4]),
.I2(I_WRAP_BRST_n_20),
.I3(Q[5]),
.I4(Q[7]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hE2))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1
(.I0(I_WRAP_BRST_n_21),
.I1(I_WRAP_BRST_n_7),
.I2(bram_addr_b),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_10),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_9),
.Q(Q[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ),
.Q(bram_addr_b),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_18),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_17),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_16),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_15),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_14),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_13),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_12),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_11),
.Q(Q[7]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1
(.I0(rd_skid_buf[0]),
.I1(bram_rddata_b[0]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ),
.Q(s_axi_rdata[0]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1
(.I0(rd_skid_buf[10]),
.I1(bram_rddata_b[10]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ),
.Q(s_axi_rdata[10]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1
(.I0(rd_skid_buf[11]),
.I1(bram_rddata_b[11]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ),
.Q(s_axi_rdata[11]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1
(.I0(rd_skid_buf[12]),
.I1(bram_rddata_b[12]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ),
.Q(s_axi_rdata[12]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1
(.I0(rd_skid_buf[13]),
.I1(bram_rddata_b[13]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ),
.Q(s_axi_rdata[13]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1
(.I0(rd_skid_buf[14]),
.I1(bram_rddata_b[14]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ),
.Q(s_axi_rdata[14]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1
(.I0(rd_skid_buf[15]),
.I1(bram_rddata_b[15]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ),
.Q(s_axi_rdata[15]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1
(.I0(rd_skid_buf[16]),
.I1(bram_rddata_b[16]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ),
.Q(s_axi_rdata[16]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1
(.I0(rd_skid_buf[17]),
.I1(bram_rddata_b[17]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ),
.Q(s_axi_rdata[17]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1
(.I0(rd_skid_buf[18]),
.I1(bram_rddata_b[18]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ),
.Q(s_axi_rdata[18]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1
(.I0(rd_skid_buf[19]),
.I1(bram_rddata_b[19]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ),
.Q(s_axi_rdata[19]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1
(.I0(rd_skid_buf[1]),
.I1(bram_rddata_b[1]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ),
.Q(s_axi_rdata[1]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1
(.I0(rd_skid_buf[20]),
.I1(bram_rddata_b[20]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ),
.Q(s_axi_rdata[20]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1
(.I0(rd_skid_buf[21]),
.I1(bram_rddata_b[21]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ),
.Q(s_axi_rdata[21]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1
(.I0(rd_skid_buf[22]),
.I1(bram_rddata_b[22]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ),
.Q(s_axi_rdata[22]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1
(.I0(rd_skid_buf[23]),
.I1(bram_rddata_b[23]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ),
.Q(s_axi_rdata[23]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1
(.I0(rd_skid_buf[24]),
.I1(bram_rddata_b[24]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ),
.Q(s_axi_rdata[24]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1
(.I0(rd_skid_buf[25]),
.I1(bram_rddata_b[25]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ),
.Q(s_axi_rdata[25]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1
(.I0(rd_skid_buf[26]),
.I1(bram_rddata_b[26]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ),
.Q(s_axi_rdata[26]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1
(.I0(rd_skid_buf[27]),
.I1(bram_rddata_b[27]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ),
.Q(s_axi_rdata[27]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1
(.I0(rd_skid_buf[28]),
.I1(bram_rddata_b[28]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ),
.Q(s_axi_rdata[28]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1
(.I0(rd_skid_buf[29]),
.I1(bram_rddata_b[29]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ),
.Q(s_axi_rdata[29]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1
(.I0(rd_skid_buf[2]),
.I1(bram_rddata_b[2]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ),
.Q(s_axi_rdata[2]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1
(.I0(rd_skid_buf[30]),
.I1(bram_rddata_b[30]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ),
.Q(s_axi_rdata[30]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'h1414545410000404))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ),
.I4(rd_data_sm_cs[0]),
.I5(rd_adv_buf67_out),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2
(.I0(rd_skid_buf[31]),
.I1(bram_rddata_b[31]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h1))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3
(.I0(act_rd_burst),
.I1(act_rd_burst_two),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.Q(s_axi_rdata[31]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1
(.I0(rd_skid_buf[3]),
.I1(bram_rddata_b[3]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ),
.Q(s_axi_rdata[3]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1
(.I0(rd_skid_buf[4]),
.I1(bram_rddata_b[4]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ),
.Q(s_axi_rdata[4]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1
(.I0(rd_skid_buf[5]),
.I1(bram_rddata_b[5]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ),
.Q(s_axi_rdata[5]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1
(.I0(rd_skid_buf[6]),
.I1(bram_rddata_b[6]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ),
.Q(s_axi_rdata[6]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1
(.I0(rd_skid_buf[7]),
.I1(bram_rddata_b[7]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ),
.Q(s_axi_rdata[7]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1
(.I0(rd_skid_buf[8]),
.I1(bram_rddata_b[8]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ),
.Q(s_axi_rdata[8]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1
(.I0(rd_skid_buf[9]),
.I1(bram_rddata_b[9]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ),
.Q(s_axi_rdata[9]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAEAA))
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1
(.I0(rd_skid_buf_ld_reg),
.I1(rd_adv_buf67_out),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[3]),
.O(rd_skid_buf_ld));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[0]),
.Q(rd_skid_buf[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[10]),
.Q(rd_skid_buf[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[11]),
.Q(rd_skid_buf[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[12]),
.Q(rd_skid_buf[12]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[13]),
.Q(rd_skid_buf[13]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[14]),
.Q(rd_skid_buf[14]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[15]),
.Q(rd_skid_buf[15]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[16]),
.Q(rd_skid_buf[16]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[17]),
.Q(rd_skid_buf[17]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[18]),
.Q(rd_skid_buf[18]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[19]),
.Q(rd_skid_buf[19]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[1]),
.Q(rd_skid_buf[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[20]),
.Q(rd_skid_buf[20]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[21]),
.Q(rd_skid_buf[21]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[22]),
.Q(rd_skid_buf[22]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[23]),
.Q(rd_skid_buf[23]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[24]),
.Q(rd_skid_buf[24]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[25]),
.Q(rd_skid_buf[25]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[26]),
.Q(rd_skid_buf[26]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[27]),
.Q(rd_skid_buf[27]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[28]),
.Q(rd_skid_buf[28]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[29]),
.Q(rd_skid_buf[29]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[2]),
.Q(rd_skid_buf[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[30]),
.Q(rd_skid_buf[30]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[31]),
.Q(rd_skid_buf[31]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[3]),
.Q(rd_skid_buf[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[4]),
.Q(rd_skid_buf[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[5]),
.Q(rd_skid_buf[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[6]),
.Q(rd_skid_buf[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[7]),
.Q(rd_skid_buf[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[8]),
.Q(rd_skid_buf[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[9]),
.Q(rd_skid_buf[9]),
.R(bram_rst_a));
LUT4 #(
.INIT(16'h08FF))
\GEN_RID.axi_rid_int[11]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rlast),
.I2(axi_b2b_brst),
.I3(s_axi_aresetn),
.O(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEAAA))
\GEN_RID.axi_rid_int[11]_i_2
(.I0(axi_rvalid_set),
.I1(s_axi_rready),
.I2(s_axi_rlast),
.I3(axi_b2b_brst),
.O(p_4_out));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[0]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[0]),
.Q(s_axi_rid[0]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[10]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[10]),
.Q(s_axi_rid[10]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[11]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[11]),
.Q(s_axi_rid[11]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[1]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[1]),
.Q(s_axi_rid[1]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[2]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[2]),
.Q(s_axi_rid[2]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[3]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[3]),
.Q(s_axi_rid[3]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[4]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[4]),
.Q(s_axi_rid[4]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[5]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[5]),
.Q(s_axi_rid[5]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[6]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[6]),
.Q(s_axi_rid[6]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[7]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[7]),
.Q(s_axi_rid[7]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[8]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[8]),
.Q(s_axi_rid[8]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[9]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[9]),
.Q(s_axi_rid[9]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[0]_i_1
(.I0(axi_arid_pipe[0]),
.I1(axi_araddr_full),
.I2(s_axi_arid[0]),
.O(axi_rid_temp20_in[0]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[10]_i_1
(.I0(axi_arid_pipe[10]),
.I1(axi_araddr_full),
.I2(s_axi_arid[10]),
.O(axi_rid_temp20_in[10]));
LUT2 #(
.INIT(4'h8))
\GEN_RID.axi_rid_temp2[11]_i_1
(.I0(axi_rid_temp_full),
.I1(bram_addr_ld_en),
.O(p_26_out));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[11]_i_2
(.I0(axi_arid_pipe[11]),
.I1(axi_araddr_full),
.I2(s_axi_arid[11]),
.O(axi_rid_temp20_in[11]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[1]_i_1
(.I0(axi_arid_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arid[1]),
.O(axi_rid_temp20_in[1]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[2]_i_1
(.I0(axi_arid_pipe[2]),
.I1(axi_araddr_full),
.I2(s_axi_arid[2]),
.O(axi_rid_temp20_in[2]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[3]_i_1
(.I0(axi_arid_pipe[3]),
.I1(axi_araddr_full),
.I2(s_axi_arid[3]),
.O(axi_rid_temp20_in[3]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[4]_i_1
(.I0(axi_arid_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arid[4]),
.O(axi_rid_temp20_in[4]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[5]_i_1
(.I0(axi_arid_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arid[5]),
.O(axi_rid_temp20_in[5]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[6]_i_1
(.I0(axi_arid_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arid[6]),
.O(axi_rid_temp20_in[6]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[7]_i_1
(.I0(axi_arid_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arid[7]),
.O(axi_rid_temp20_in[7]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[8]_i_1
(.I0(axi_arid_pipe[8]),
.I1(axi_araddr_full),
.I2(s_axi_arid[8]),
.O(axi_rid_temp20_in[8]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[9]_i_1
(.I0(axi_arid_pipe[9]),
.I1(axi_araddr_full),
.I2(s_axi_arid[9]),
.O(axi_rid_temp20_in[9]));
LUT6 #(
.INIT(64'h08080000C8C800C0))
\GEN_RID.axi_rid_temp2_full_i_1
(.I0(bram_addr_ld_en),
.I1(s_axi_aresetn),
.I2(axi_rid_temp2_full),
.I3(axi_rid_temp_full_d1),
.I4(axi_rid_temp_full),
.I5(p_4_out),
.O(\GEN_RID.axi_rid_temp2_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp2_full_i_1_n_0 ),
.Q(axi_rid_temp2_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[0]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[0]),
.Q(axi_rid_temp2[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[10]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[10]),
.Q(axi_rid_temp2[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[11]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[11]),
.Q(axi_rid_temp2[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[1]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[1]),
.Q(axi_rid_temp2[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[2]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[2]),
.Q(axi_rid_temp2[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[3]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[3]),
.Q(axi_rid_temp2[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[4]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[4]),
.Q(axi_rid_temp2[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[5]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[5]),
.Q(axi_rid_temp2[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[6]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[6]),
.Q(axi_rid_temp2[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[7]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[7]),
.Q(axi_rid_temp2[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[8]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[8]),
.Q(axi_rid_temp2[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[9]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[9]),
.Q(axi_rid_temp2[9]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[0]_i_1
(.I0(axi_arid_pipe[0]),
.I1(axi_araddr_full),
.I2(s_axi_arid[0]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[0]),
.O(\GEN_RID.axi_rid_temp[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[10]_i_1
(.I0(axi_arid_pipe[10]),
.I1(axi_araddr_full),
.I2(s_axi_arid[10]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[10]),
.O(\GEN_RID.axi_rid_temp[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hA0FFA0E0))
\GEN_RID.axi_rid_temp[11]_i_1
(.I0(p_4_out),
.I1(axi_rid_temp_full_d1),
.I2(axi_rid_temp2_full),
.I3(axi_rid_temp_full),
.I4(bram_addr_ld_en),
.O(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[11]_i_2
(.I0(axi_arid_pipe[11]),
.I1(axi_araddr_full),
.I2(s_axi_arid[11]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[11]),
.O(\GEN_RID.axi_rid_temp[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[1]_i_1
(.I0(axi_arid_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arid[1]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[1]),
.O(\GEN_RID.axi_rid_temp[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[2]_i_1
(.I0(axi_arid_pipe[2]),
.I1(axi_araddr_full),
.I2(s_axi_arid[2]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[2]),
.O(\GEN_RID.axi_rid_temp[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[3]_i_1
(.I0(axi_arid_pipe[3]),
.I1(axi_araddr_full),
.I2(s_axi_arid[3]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[3]),
.O(\GEN_RID.axi_rid_temp[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[4]_i_1
(.I0(axi_arid_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arid[4]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[4]),
.O(\GEN_RID.axi_rid_temp[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[5]_i_1
(.I0(axi_arid_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arid[5]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[5]),
.O(\GEN_RID.axi_rid_temp[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[6]_i_1
(.I0(axi_arid_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arid[6]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[6]),
.O(\GEN_RID.axi_rid_temp[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[7]_i_1
(.I0(axi_arid_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arid[7]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[7]),
.O(\GEN_RID.axi_rid_temp[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[8]_i_1
(.I0(axi_arid_pipe[8]),
.I1(axi_araddr_full),
.I2(s_axi_arid[8]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[8]),
.O(\GEN_RID.axi_rid_temp[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[9]_i_1
(.I0(axi_arid_pipe[9]),
.I1(axi_araddr_full),
.I2(s_axi_arid[9]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[9]),
.O(\GEN_RID.axi_rid_temp[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_full_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rid_temp_full),
.Q(axi_rid_temp_full_d1),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hF0F0F0E000F0A0A0))
\GEN_RID.axi_rid_temp_full_i_1
(.I0(bram_addr_ld_en),
.I1(axi_rid_temp_full_d1),
.I2(s_axi_aresetn),
.I3(p_4_out),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2_full),
.O(\GEN_RID.axi_rid_temp_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp_full_i_1_n_0 ),
.Q(axi_rid_temp_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[0]_i_1_n_0 ),
.Q(axi_rid_temp[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[10]_i_1_n_0 ),
.Q(axi_rid_temp[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[11]_i_2_n_0 ),
.Q(axi_rid_temp[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[1]_i_1_n_0 ),
.Q(axi_rid_temp[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[2]_i_1_n_0 ),
.Q(axi_rid_temp[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[3]_i_1_n_0 ),
.Q(axi_rid_temp[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[4]_i_1_n_0 ),
.Q(axi_rid_temp[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[5]_i_1_n_0 ),
.Q(axi_rid_temp[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[6]_i_1_n_0 ),
.Q(axi_rid_temp[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[7]_i_1_n_0 ),
.Q(axi_rid_temp[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[8]_i_1_n_0 ),
.Q(axi_rid_temp[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[9]_i_1_n_0 ),
.Q(axi_rid_temp[9]),
.R(bram_rst_a));
zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 I_WRAP_BRST
(.D({I_WRAP_BRST_n_9,I_WRAP_BRST_n_10,I_WRAP_BRST_n_11,I_WRAP_BRST_n_12,I_WRAP_BRST_n_13,I_WRAP_BRST_n_14,I_WRAP_BRST_n_15,I_WRAP_BRST_n_16,I_WRAP_BRST_n_17,I_WRAP_BRST_n_18}),
.E(I_WRAP_BRST_n_6),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg (\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] (axi_arlen_pipe[3:0]),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] (I_WRAP_BRST_n_0),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 (I_WRAP_BRST_n_7),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 (I_WRAP_BRST_n_8),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 (Q),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] (I_WRAP_BRST_n_20),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 (\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] (\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4__0_n_0 ),
.Q(rd_data_sm_cs),
.SR(bram_rst_a),
.ar_active(ar_active),
.axi_araddr_full(axi_araddr_full),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_arlen_pipe_1_or_2(axi_arlen_pipe_1_or_2),
.axi_arsize_pipe(axi_arsize_pipe),
.axi_arsize_pipe_max(axi_arsize_pipe_max),
.axi_b2b_brst(axi_b2b_brst),
.axi_b2b_brst_reg(I_WRAP_BRST_n_24),
.axi_rd_burst(axi_rd_burst),
.axi_rd_burst_two_reg(axi_rd_burst_two_reg_n_0),
.axi_rvalid_int_reg(s_axi_rvalid),
.bram_addr_ld_en(bram_addr_ld_en),
.brst_zero(brst_zero),
.curr_fixed_burst_reg(curr_fixed_burst_reg),
.curr_wrap_burst_reg(curr_wrap_burst_reg),
.disable_b2b_brst(disable_b2b_brst),
.end_brst_rd(end_brst_rd),
.last_bram_addr(last_bram_addr),
.no_ar_ack(no_ar_ack),
.pend_rd_op(pend_rd_op),
.rd_addr_sm_cs(rd_addr_sm_cs),
.rd_adv_buf67_out(rd_adv_buf67_out),
.\rd_data_sm_cs_reg[1] (I_WRAP_BRST_n_22),
.\rd_data_sm_cs_reg[3] (I_WRAP_BRST_n_25),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arlen(s_axi_arlen[3:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rready(s_axi_rready),
.\save_init_bram_addr_ld_reg[12]_0 (I_WRAP_BRST_n_21),
.\save_init_bram_addr_ld_reg[12]_1 (I_WRAP_BRST_n_23),
.\wrap_burst_total_reg[0]_0 (I_WRAP_BRST_n_2),
.\wrap_burst_total_reg[0]_1 (I_WRAP_BRST_n_3),
.\wrap_burst_total_reg[0]_2 (I_WRAP_BRST_n_4),
.\wrap_burst_total_reg[0]_3 (I_WRAP_BRST_n_5));
LUT6 #(
.INIT(64'h000000002EEE22E2))
act_rd_burst_i_1
(.I0(act_rd_burst),
.I1(act_rd_burst_set),
.I2(bram_addr_ld_en),
.I3(axi_rd_burst_two),
.I4(axi_rd_burst),
.I5(act_rd_burst_i_3_n_0),
.O(act_rd_burst_i_1_n_0));
LUT6 #(
.INIT(64'hA8A8AAA8A8A8A8A8))
act_rd_burst_i_2
(.I0(\GEN_AR_DUAL.ar_active_i_4_n_0 ),
.I1(act_rd_burst_i_4_n_0),
.I2(axi_b2b_brst_i_3_n_0),
.I3(\rd_data_sm_cs[2]_i_4_n_0 ),
.I4(last_bram_addr_i_8_n_0),
.I5(bram_addr_ld_en),
.O(act_rd_burst_set));
LUT6 #(
.INIT(64'h02000004FFFFFFFF))
act_rd_burst_i_3
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(\rd_data_sm_cs[3]_i_6_n_0 ),
.I3(rd_data_sm_cs[1]),
.I4(rd_data_sm_cs[0]),
.I5(s_axi_aresetn),
.O(act_rd_burst_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h4440))
act_rd_burst_i_4
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.I2(axi_rd_burst),
.I3(axi_rd_burst_two_reg_n_0),
.O(act_rd_burst_i_4_n_0));
FDRE #(
.INIT(1'b0))
act_rd_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(act_rd_burst_i_1_n_0),
.Q(act_rd_burst),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000E2EEE222))
act_rd_burst_two_i_1
(.I0(act_rd_burst_two),
.I1(act_rd_burst_set),
.I2(axi_rd_burst_two),
.I3(bram_addr_ld_en),
.I4(axi_rd_burst_two_reg_n_0),
.I5(act_rd_burst_i_3_n_0),
.O(act_rd_burst_two_i_1_n_0));
FDRE #(
.INIT(1'b0))
act_rd_burst_two_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(act_rd_burst_two_i_1_n_0),
.Q(act_rd_burst_two),
.R(1'b0));
LUT2 #(
.INIT(4'hE))
axi_arsize_pipe_max_i_1
(.I0(araddr_pipe_ld43_out),
.I1(axi_arsize_pipe_max),
.O(axi_arsize_pipe_max_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_arsize_pipe_max_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_arsize_pipe_max_i_1_n_0),
.Q(axi_arsize_pipe_max),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hCC0CCC55CC0CCCCC))
axi_b2b_brst_i_1
(.I0(I_WRAP_BRST_n_24),
.I1(axi_b2b_brst),
.I2(disable_b2b_brst_i_2_n_0),
.I3(rd_data_sm_cs[3]),
.I4(rd_data_sm_cs[2]),
.I5(axi_b2b_brst_i_3_n_0),
.O(axi_b2b_brst_i_1_n_0));
LUT6 #(
.INIT(64'h0000000088880080))
axi_b2b_brst_i_3
(.I0(\rd_data_sm_cs[0]_i_3_n_0 ),
.I1(rd_adv_buf67_out),
.I2(end_brst_rd),
.I3(axi_b2b_brst),
.I4(brst_zero),
.I5(I_WRAP_BRST_n_24),
.O(axi_b2b_brst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_b2b_brst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_b2b_brst_i_1_n_0),
.Q(axi_b2b_brst),
.R(bram_rst_a));
LUT5 #(
.INIT(32'h303000A0))
axi_rd_burst_i_1
(.I0(axi_rd_burst),
.I1(axi_rd_burst_i_2_n_0),
.I2(s_axi_aresetn),
.I3(brst_zero),
.I4(bram_addr_ld_en),
.O(axi_rd_burst_i_1_n_0));
LUT6 #(
.INIT(64'h0000000000000004))
axi_rd_burst_i_2
(.I0(\brst_cnt[6]_i_2_n_0 ),
.I1(axi_rd_burst_i_3_n_0),
.I2(I_WRAP_BRST_n_4),
.I3(\brst_cnt[7]_i_3_n_0 ),
.I4(I_WRAP_BRST_n_3),
.I5(I_WRAP_BRST_n_2),
.O(axi_rd_burst_i_2_n_0));
LUT5 #(
.INIT(32'h00053305))
axi_rd_burst_i_3
(.I0(s_axi_arlen[5]),
.I1(axi_arlen_pipe[5]),
.I2(s_axi_arlen[4]),
.I3(axi_araddr_full),
.I4(axi_arlen_pipe[4]),
.O(axi_rd_burst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_rd_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rd_burst_i_1_n_0),
.Q(axi_rd_burst),
.R(1'b0));
LUT5 #(
.INIT(32'hC0C000A0))
axi_rd_burst_two_i_1
(.I0(axi_rd_burst_two_reg_n_0),
.I1(axi_rd_burst_two),
.I2(s_axi_aresetn),
.I3(brst_zero),
.I4(bram_addr_ld_en),
.O(axi_rd_burst_two_i_1_n_0));
LUT4 #(
.INIT(16'hA808))
axi_rd_burst_two_i_2
(.I0(axi_rd_burst_i_2_n_0),
.I1(s_axi_arlen[0]),
.I2(axi_araddr_full),
.I3(axi_arlen_pipe[0]),
.O(axi_rd_burst_two));
FDRE #(
.INIT(1'b0))
axi_rd_burst_two_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rd_burst_two_i_1_n_0),
.Q(axi_rd_burst_two_reg_n_0),
.R(1'b0));
LUT4 #(
.INIT(16'h88A8))
axi_rlast_int_i_1
(.I0(s_axi_aresetn),
.I1(axi_rlast_set),
.I2(s_axi_rlast),
.I3(s_axi_rready),
.O(axi_rlast_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_rlast_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rlast_int_i_1_n_0),
.Q(s_axi_rlast),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000FFFFEEEA))
axi_rvalid_clr_ok_i_1
(.I0(axi_rvalid_clr_ok),
.I1(last_bram_addr),
.I2(disable_b2b_brst),
.I3(disable_b2b_brst_cmb),
.I4(axi_rvalid_clr_ok_i_2_n_0),
.I5(axi_rvalid_clr_ok_i_3_n_0),
.O(axi_rvalid_clr_ok_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hAAAABAAA))
axi_rvalid_clr_ok_i_2
(.I0(bram_addr_ld_en),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.O(axi_rvalid_clr_ok_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'h4F))
axi_rvalid_clr_ok_i_3
(.I0(I_WRAP_BRST_n_23),
.I1(bram_addr_ld_en),
.I2(s_axi_aresetn),
.O(axi_rvalid_clr_ok_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_rvalid_clr_ok_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_clr_ok_i_1_n_0),
.Q(axi_rvalid_clr_ok),
.R(1'b0));
LUT6 #(
.INIT(64'h00E0E0E0E0E0E0E0))
axi_rvalid_int_i_1
(.I0(s_axi_rvalid),
.I1(axi_rvalid_set),
.I2(s_axi_aresetn),
.I3(axi_rvalid_clr_ok),
.I4(s_axi_rlast),
.I5(s_axi_rready),
.O(axi_rvalid_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_rvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_int_i_1_n_0),
.Q(s_axi_rvalid),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0100))
axi_rvalid_set_i_1
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.O(axi_rvalid_set_cmb));
FDRE #(
.INIT(1'b0))
axi_rvalid_set_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_set_cmb),
.Q(axi_rvalid_set),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hEEEEFFFEEEEE000E))
bram_en_int_i_1
(.I0(bram_en_int_i_2_n_0),
.I1(bram_en_int_i_3_n_0),
.I2(bram_en_int_i_4_n_0),
.I3(I_WRAP_BRST_n_25),
.I4(bram_en_int_i_6_n_0),
.I5(bram_en_b),
.O(bram_en_int_i_1_n_0));
LUT6 #(
.INIT(64'hFFFF777FFFFFFFFF))
bram_en_int_i_10
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(act_rd_burst),
.I3(act_rd_burst_two),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_10_n_0));
LUT6 #(
.INIT(64'hD0D000F0D0D0F0F0))
bram_en_int_i_11
(.I0(\rd_data_sm_cs[3]_i_7_n_0 ),
.I1(I_WRAP_BRST_n_24),
.I2(rd_data_sm_cs[1]),
.I3(brst_one),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[2]_i_5_n_0 ),
.O(bram_en_int_i_11_n_0));
LUT6 #(
.INIT(64'h00000000FDF50000))
bram_en_int_i_2
(.I0(rd_data_sm_cs[2]),
.I1(pend_rd_op),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(rd_data_sm_cs[1]),
.I5(bram_en_int_i_7_n_0),
.O(bram_en_int_i_2_n_0));
LUT6 #(
.INIT(64'hAAAAEEAFAAAAAAEE))
bram_en_int_i_3
(.I0(I_WRAP_BRST_n_0),
.I1(bram_addr_ld_en),
.I2(p_0_in13_in),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_3_n_0));
LUT6 #(
.INIT(64'h000F007F0000007F))
bram_en_int_i_4
(.I0(pend_rd_op),
.I1(rd_adv_buf67_out),
.I2(\rd_data_sm_cs[0]_i_3_n_0 ),
.I3(bram_en_int_i_9_n_0),
.I4(bram_addr_ld_en),
.I5(bram_en_int_i_10_n_0),
.O(bram_en_int_i_4_n_0));
LUT6 #(
.INIT(64'h1010111111111110))
bram_en_int_i_6
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(bram_en_int_i_11_n_0),
.I3(bram_addr_ld_en),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_6_n_0));
LUT6 #(
.INIT(64'h3330131003001310))
bram_en_int_i_7
(.I0(\rd_data_sm_cs[2]_i_5_n_0 ),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[0]),
.I3(axi_rd_burst_two_reg_n_0),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[3]_i_7_n_0 ),
.O(bram_en_int_i_7_n_0));
LUT6 #(
.INIT(64'h1111111111111000))
bram_en_int_i_9
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(brst_zero),
.I5(end_brst_rd),
.O(bram_en_int_i_9_n_0));
FDRE #(
.INIT(1'b0))
bram_en_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bram_en_int_i_1_n_0),
.Q(bram_en_b),
.R(bram_rst_a));
LUT5 #(
.INIT(32'hD1DDD111))
\brst_cnt[0]_i_1
(.I0(brst_cnt[0]),
.I1(bram_addr_ld_en),
.I2(axi_arlen_pipe[0]),
.I3(axi_araddr_full),
.I4(s_axi_arlen[0]),
.O(\brst_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8FFB800B800B8FF))
\brst_cnt[1]_i_1
(.I0(axi_arlen_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[1]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[0]),
.I5(brst_cnt[1]),
.O(\brst_cnt[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8B8B88B))
\brst_cnt[2]_i_1
(.I0(I_WRAP_BRST_n_2),
.I1(bram_addr_ld_en),
.I2(brst_cnt[2]),
.I3(brst_cnt[1]),
.I4(brst_cnt[0]),
.O(\brst_cnt[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8B8B8B8B88B))
\brst_cnt[3]_i_1
(.I0(I_WRAP_BRST_n_3),
.I1(bram_addr_ld_en),
.I2(brst_cnt[3]),
.I3(brst_cnt[2]),
.I4(brst_cnt[0]),
.I5(brst_cnt[1]),
.O(\brst_cnt[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\brst_cnt[4]_i_1
(.I0(axi_arlen_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[4]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[4]),
.I5(\brst_cnt[4]_i_2_n_0 ),
.O(\brst_cnt[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0001))
\brst_cnt[4]_i_2
(.I0(brst_cnt[2]),
.I1(brst_cnt[0]),
.I2(brst_cnt[1]),
.I3(brst_cnt[3]),
.O(\brst_cnt[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\brst_cnt[5]_i_1
(.I0(axi_arlen_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[5]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[5]),
.I5(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'hB88BB8B8))
\brst_cnt[6]_i_1
(.I0(\brst_cnt[6]_i_2_n_0 ),
.I1(bram_addr_ld_en),
.I2(brst_cnt[6]),
.I3(brst_cnt[5]),
.I4(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\brst_cnt[6]_i_2
(.I0(axi_arlen_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[6]),
.O(\brst_cnt[6]_i_2_n_0 ));
LUT2 #(
.INIT(4'hE))
\brst_cnt[7]_i_1
(.I0(bram_addr_ld_en),
.I1(I_WRAP_BRST_n_8),
.O(\brst_cnt[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B88BB8B8B8B8))
\brst_cnt[7]_i_2
(.I0(\brst_cnt[7]_i_3_n_0 ),
.I1(bram_addr_ld_en),
.I2(brst_cnt[7]),
.I3(brst_cnt[6]),
.I4(brst_cnt[5]),
.I5(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\brst_cnt[7]_i_3
(.I0(axi_arlen_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[7]),
.O(\brst_cnt[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00000001))
\brst_cnt[7]_i_4
(.I0(brst_cnt[3]),
.I1(brst_cnt[1]),
.I2(brst_cnt[0]),
.I3(brst_cnt[2]),
.I4(brst_cnt[4]),
.O(\brst_cnt[7]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
brst_cnt_max_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_cnt_max),
.Q(brst_cnt_max_d1),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[0]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[0]_i_1_n_0 ),
.Q(brst_cnt[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[1]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[1]_i_1_n_0 ),
.Q(brst_cnt[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[2]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[2]_i_1_n_0 ),
.Q(brst_cnt[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[3]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[3]_i_1_n_0 ),
.Q(brst_cnt[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[4]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[4]_i_1_n_0 ),
.Q(brst_cnt[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[5]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[5]_i_1_n_0 ),
.Q(brst_cnt[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[6]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[6]_i_1_n_0 ),
.Q(brst_cnt[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[7]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[7]_i_2_n_0 ),
.Q(brst_cnt[7]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h00000000E0EE0000))
brst_one_i_1
(.I0(brst_one),
.I1(brst_one0),
.I2(axi_rd_burst_two),
.I3(bram_addr_ld_en),
.I4(s_axi_aresetn),
.I5(last_bram_addr_i_7_n_0),
.O(brst_one_i_1_n_0));
LUT6 #(
.INIT(64'h80FF808080808080))
brst_one_i_2
(.I0(bram_addr_ld_en),
.I1(I_WRAP_BRST_n_5),
.I2(axi_rd_burst_i_2_n_0),
.I3(brst_cnt[0]),
.I4(brst_cnt[1]),
.I5(last_bram_addr_i_9_n_0),
.O(brst_one0));
FDRE #(
.INIT(1'b0))
brst_one_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_one_i_1_n_0),
.Q(brst_one),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h00E0))
brst_zero_i_1
(.I0(brst_zero),
.I1(last_bram_addr_i_7_n_0),
.I2(s_axi_aresetn),
.I3(last_bram_addr_i_3_n_0),
.O(brst_zero_i_1_n_0));
FDRE #(
.INIT(1'b0))
brst_zero_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_zero_i_1_n_0),
.Q(brst_zero),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h00053305))
curr_fixed_burst_reg_i_1
(.I0(s_axi_arburst[0]),
.I1(axi_arburst_pipe[0]),
.I2(s_axi_arburst[1]),
.I3(axi_araddr_full),
.I4(axi_arburst_pipe[1]),
.O(curr_fixed_burst));
FDRE #(
.INIT(1'b0))
curr_fixed_burst_reg_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_fixed_burst),
.Q(curr_fixed_burst_reg),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h000ACC0A))
curr_wrap_burst_reg_i_1
(.I0(s_axi_arburst[1]),
.I1(axi_arburst_pipe[1]),
.I2(s_axi_arburst[0]),
.I3(axi_araddr_full),
.I4(axi_arburst_pipe[0]),
.O(curr_wrap_burst));
FDRE #(
.INIT(1'b0))
curr_wrap_burst_reg_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_wrap_burst),
.Q(curr_wrap_burst_reg),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFFF000D0000))
disable_b2b_brst_i_1
(.I0(axi_rd_burst),
.I1(axi_rd_burst_two_reg_n_0),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[3]),
.I4(disable_b2b_brst_i_2_n_0),
.I5(disable_b2b_brst_i_3_n_0),
.O(disable_b2b_brst_cmb));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h2))
disable_b2b_brst_i_2
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.O(disable_b2b_brst_i_2_n_0));
LUT6 #(
.INIT(64'hFE7D0000FE7DFE7D))
disable_b2b_brst_i_3
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[3]),
.I4(disable_b2b_brst),
.I5(disable_b2b_brst_i_4_n_0),
.O(disable_b2b_brst_i_3_n_0));
LUT6 #(
.INIT(64'hDFDFDFDFDFDFDFFF))
disable_b2b_brst_i_4
(.I0(\GEN_AR_DUAL.ar_active_i_4_n_0 ),
.I1(rd_adv_buf67_out),
.I2(rd_data_sm_cs[0]),
.I3(brst_zero),
.I4(end_brst_rd),
.I5(brst_one),
.O(disable_b2b_brst_i_4_n_0));
FDRE #(
.INIT(1'b0))
disable_b2b_brst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(disable_b2b_brst_cmb),
.Q(disable_b2b_brst),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFEFEFEFF10100000))
end_brst_rd_clr_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(bram_addr_ld_en),
.I4(rd_data_sm_cs[0]),
.I5(end_brst_rd_clr),
.O(end_brst_rd_clr_i_1_n_0));
FDRE #(
.INIT(1'b0))
end_brst_rd_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(end_brst_rd_clr_i_1_n_0),
.Q(end_brst_rd_clr),
.R(bram_rst_a));
LUT5 #(
.INIT(32'h0020F020))
end_brst_rd_i_1
(.I0(brst_cnt_max),
.I1(brst_cnt_max_d1),
.I2(s_axi_aresetn),
.I3(end_brst_rd),
.I4(end_brst_rd_clr),
.O(end_brst_rd_i_1_n_0));
FDRE #(
.INIT(1'b0))
end_brst_rd_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(end_brst_rd_i_1_n_0),
.Q(end_brst_rd),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFF57550000))
last_bram_addr_i_1
(.I0(last_bram_addr_i_2_n_0),
.I1(last_bram_addr_i_3_n_0),
.I2(last_bram_addr_i_4_n_0),
.I3(last_bram_addr_i_5_n_0),
.I4(last_bram_addr_i_6_n_0),
.I5(last_bram_addr_i_7_n_0),
.O(last_bram_addr0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'hE))
last_bram_addr_i_10
(.I0(brst_cnt[6]),
.I1(brst_cnt[5]),
.O(last_bram_addr_i_10_n_0));
LUT6 #(
.INIT(64'hAABFFFBFFFBFFFBF))
last_bram_addr_i_2
(.I0(rd_data_sm_cs[2]),
.I1(last_bram_addr_i_8_n_0),
.I2(bram_addr_ld_en),
.I3(rd_data_sm_cs[3]),
.I4(rd_adv_buf67_out),
.I5(p_0_in13_in),
.O(last_bram_addr_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h8A80AAAA))
last_bram_addr_i_3
(.I0(bram_addr_ld_en),
.I1(axi_arlen_pipe[0]),
.I2(axi_araddr_full),
.I3(s_axi_arlen[0]),
.I4(axi_rd_burst_i_2_n_0),
.O(last_bram_addr_i_3_n_0));
LUT6 #(
.INIT(64'hDDDDDDDDFFFDFFFF))
last_bram_addr_i_4
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(axi_rd_burst),
.I3(axi_rd_burst_two_reg_n_0),
.I4(pend_rd_op),
.I5(bram_addr_ld_en),
.O(last_bram_addr_i_4_n_0));
LUT4 #(
.INIT(16'h8880))
last_bram_addr_i_5
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(bram_addr_ld_en),
.I3(pend_rd_op),
.O(last_bram_addr_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h81))
last_bram_addr_i_6
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[0]),
.O(last_bram_addr_i_6_n_0));
LUT3 #(
.INIT(8'h08))
last_bram_addr_i_7
(.I0(last_bram_addr_i_9_n_0),
.I1(brst_cnt[0]),
.I2(brst_cnt[1]),
.O(last_bram_addr_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h02A2))
last_bram_addr_i_8
(.I0(axi_rd_burst_i_2_n_0),
.I1(s_axi_arlen[0]),
.I2(axi_araddr_full),
.I3(axi_arlen_pipe[0]),
.O(last_bram_addr_i_8_n_0));
LUT6 #(
.INIT(64'h0000000000000002))
last_bram_addr_i_9
(.I0(I_WRAP_BRST_n_8),
.I1(last_bram_addr_i_10_n_0),
.I2(brst_cnt[3]),
.I3(brst_cnt[2]),
.I4(brst_cnt[4]),
.I5(brst_cnt[7]),
.O(last_bram_addr_i_9_n_0));
FDRE #(
.INIT(1'b0))
last_bram_addr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(last_bram_addr0),
.Q(last_bram_addr),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hAAAAAAAA88C8AAAA))
no_ar_ack_i_1
(.I0(no_ar_ack),
.I1(rd_data_sm_cs[1]),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(rd_data_sm_cs[0]),
.I5(I_WRAP_BRST_n_25),
.O(no_ar_ack_i_1_n_0));
FDRE #(
.INIT(1'b0))
no_ar_ack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(no_ar_ack_i_1_n_0),
.Q(no_ar_ack),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hAAAAFFFEAAAA0002))
pend_rd_op_i_1
(.I0(pend_rd_op_i_2_n_0),
.I1(pend_rd_op_i_3_n_0),
.I2(rd_data_sm_cs[3]),
.I3(rd_data_sm_cs[2]),
.I4(pend_rd_op_i_4_n_0),
.I5(pend_rd_op),
.O(pend_rd_op_i_1_n_0));
LUT6 #(
.INIT(64'h0FFCC8C80CCCC8C8))
pend_rd_op_i_2
(.I0(p_0_in13_in),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[2]),
.I5(pend_rd_op_i_5_n_0),
.O(pend_rd_op_i_2_n_0));
LUT6 #(
.INIT(64'h0303070733F3FFFF))
pend_rd_op_i_3
(.I0(p_0_in13_in),
.I1(rd_data_sm_cs[0]),
.I2(rd_data_sm_cs[1]),
.I3(s_axi_rlast),
.I4(pend_rd_op),
.I5(bram_addr_ld_en),
.O(pend_rd_op_i_3_n_0));
LUT6 #(
.INIT(64'h00000000BBBABB00))
pend_rd_op_i_4
(.I0(pend_rd_op_i_6_n_0),
.I1(rd_data_sm_cs[0]),
.I2(pend_rd_op_i_5_n_0),
.I3(bram_addr_ld_en),
.I4(pend_rd_op_i_7_n_0),
.I5(I_WRAP_BRST_n_25),
.O(pend_rd_op_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
pend_rd_op_i_5
(.I0(ar_active),
.I1(end_brst_rd),
.O(pend_rd_op_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h8000FFFF))
pend_rd_op_i_6
(.I0(pend_rd_op),
.I1(s_axi_rready),
.I2(s_axi_rvalid),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.O(pend_rd_op_i_6_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFF0008888))
pend_rd_op_i_7
(.I0(pend_rd_op),
.I1(s_axi_rlast),
.I2(ar_active),
.I3(end_brst_rd),
.I4(rd_data_sm_cs[0]),
.I5(rd_data_sm_cs[1]),
.O(pend_rd_op_i_7_n_0));
FDRE #(
.INIT(1'b0))
pend_rd_op_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(pend_rd_op_i_1_n_0),
.Q(pend_rd_op),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFFF54005555))
\rd_data_sm_cs[0]_i_1
(.I0(\rd_data_sm_cs[0]_i_2_n_0 ),
.I1(pend_rd_op),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(\rd_data_sm_cs[0]_i_3_n_0 ),
.I5(\rd_data_sm_cs[0]_i_4_n_0 ),
.O(\rd_data_sm_cs[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFEAAAAAAFEAAFEAA))
\rd_data_sm_cs[0]_i_2
(.I0(I_WRAP_BRST_n_25),
.I1(act_rd_burst_two),
.I2(act_rd_burst),
.I3(disable_b2b_brst_i_2_n_0),
.I4(bram_addr_ld_en),
.I5(rd_adv_buf67_out),
.O(\rd_data_sm_cs[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h8))
\rd_data_sm_cs[0]_i_3
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000300BF0003008F))
\rd_data_sm_cs[0]_i_4
(.I0(rd_adv_buf67_out),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[3]),
.I5(p_0_in13_in),
.O(\rd_data_sm_cs[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAABAAABAFFFFAABA))
\rd_data_sm_cs[1]_i_1
(.I0(\rd_data_sm_cs[2]_i_2_n_0 ),
.I1(I_WRAP_BRST_n_25),
.I2(\rd_data_sm_cs[2]_i_5_n_0 ),
.I3(rd_data_sm_cs[0]),
.I4(I_WRAP_BRST_n_22),
.I5(\rd_data_sm_cs[1]_i_3_n_0 ),
.O(\rd_data_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hC0CCCCCC88888888))
\rd_data_sm_cs[1]_i_3
(.I0(axi_rd_burst_two_reg_n_0),
.I1(rd_data_sm_cs[1]),
.I2(I_WRAP_BRST_n_24),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.I5(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAAABAAABAEAFAAAB))
\rd_data_sm_cs[2]_i_1
(.I0(\rd_data_sm_cs[2]_i_2_n_0 ),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[3]),
.I3(\rd_data_sm_cs[2]_i_3_n_0 ),
.I4(\rd_data_sm_cs[2]_i_4_n_0 ),
.I5(\rd_data_sm_cs[2]_i_5_n_0 ),
.O(\rd_data_sm_cs[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000000DF00000))
\rd_data_sm_cs[2]_i_2
(.I0(bram_addr_ld_en),
.I1(\rd_data_sm_cs[3]_i_6_n_0 ),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[2]),
.I5(rd_data_sm_cs[3]),
.O(\rd_data_sm_cs[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00C0FFFF33F3BBBB))
\rd_data_sm_cs[2]_i_3
(.I0(axi_rd_burst),
.I1(rd_data_sm_cs[0]),
.I2(rd_adv_buf67_out),
.I3(I_WRAP_BRST_n_24),
.I4(rd_data_sm_cs[1]),
.I5(axi_rd_burst_two_reg_n_0),
.O(\rd_data_sm_cs[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h1))
\rd_data_sm_cs[2]_i_4
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[2]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h1))
\rd_data_sm_cs[2]_i_5
(.I0(brst_zero),
.I1(end_brst_rd),
.O(\rd_data_sm_cs[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFCCCBBBB3000B888))
\rd_data_sm_cs[3]_i_1
(.I0(\rd_data_sm_cs[3]_i_3_n_0 ),
.I1(\rd_data_sm_cs[3]_i_4_n_0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.I4(\rd_data_sm_cs[3]_i_5_n_0 ),
.I5(bram_addr_ld_en),
.O(rd_data_sm_ns));
LUT6 #(
.INIT(64'h0000004050005040))
\rd_data_sm_cs[3]_i_2
(.I0(I_WRAP_BRST_n_25),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[1]),
.I4(\rd_data_sm_cs[3]_i_6_n_0 ),
.I5(rd_adv_buf67_out),
.O(\rd_data_sm_cs[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFF5EFFFF))
\rd_data_sm_cs[3]_i_3
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[3]),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[3]_i_7_n_0 ),
.O(\rd_data_sm_cs[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hBFAD))
\rd_data_sm_cs[3]_i_4
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[3]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0035))
\rd_data_sm_cs[3]_i_5
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h1FFF))
\rd_data_sm_cs[3]_i_6
(.I0(act_rd_burst_two),
.I1(act_rd_burst),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(\rd_data_sm_cs[3]_i_6_n_0 ));
LUT3 #(
.INIT(8'hBA))
\rd_data_sm_cs[3]_i_7
(.I0(brst_zero),
.I1(axi_b2b_brst),
.I2(end_brst_rd),
.O(\rd_data_sm_cs[3]_i_7_n_0 ));
FDRE \rd_data_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[0]_i_1_n_0 ),
.Q(rd_data_sm_cs[0]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[1]_i_1_n_0 ),
.Q(rd_data_sm_cs[1]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[2]_i_1_n_0 ),
.Q(rd_data_sm_cs[2]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[3]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[3]_i_2_n_0 ),
.Q(rd_data_sm_cs[3]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h1110011001100110))
rd_skid_buf_ld_reg_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[1]),
.I4(s_axi_rready),
.I5(s_axi_rvalid),
.O(rd_skid_buf_ld_cmb));
FDRE #(
.INIT(1'b0))
rd_skid_buf_ld_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rd_skid_buf_ld_cmb),
.Q(rd_skid_buf_ld_reg),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hFE02))
rddata_mux_sel_i_1
(.I0(rddata_mux_sel_cmb),
.I1(rd_data_sm_cs[3]),
.I2(rddata_mux_sel_i_3_n_0),
.I3(rddata_mux_sel),
.O(rddata_mux_sel_i_1_n_0));
LUT6 #(
.INIT(64'hF0F010F00F00F000))
rddata_mux_sel_i_2
(.I0(act_rd_burst),
.I1(act_rd_burst_two),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.I5(rd_adv_buf67_out),
.O(rddata_mux_sel_cmb));
LUT6 #(
.INIT(64'hF700070FF70F070F))
rddata_mux_sel_i_3
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(axi_rd_burst_two_reg_n_0),
.O(rddata_mux_sel_i_3_n_0));
FDRE #(
.INIT(1'b0))
rddata_mux_sel_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rddata_mux_sel_i_1_n_0),
.Q(rddata_mux_sel),
.R(bram_rst_a));
LUT4 #(
.INIT(16'hEAAA))
s_axi_arready_INST_0
(.I0(axi_arready_int),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(axi_early_arready_int),
.O(s_axi_arready));
endmodule
(* ORIG_REF_NAME = "wr_chnl" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl
(axi_aresetn_d2,
axi_aresetn_re_reg,
bram_en_a,
bram_wrdata_a,
s_axi_bvalid,
\GEN_AW_DUAL.aw_active_reg_0 ,
s_axi_wready,
s_axi_awready,
bram_addr_a,
s_axi_bid,
bram_we_a,
SR,
s_axi_aclk,
s_axi_awaddr,
s_axi_aresetn,
s_axi_wdata,
s_axi_wvalid,
s_axi_wlast,
s_axi_bready,
s_axi_awburst,
s_axi_awid,
s_axi_awvalid,
s_axi_awlen,
s_axi_wstrb);
output axi_aresetn_d2;
output axi_aresetn_re_reg;
output bram_en_a;
output [31:0]bram_wrdata_a;
output s_axi_bvalid;
output \GEN_AW_DUAL.aw_active_reg_0 ;
output s_axi_wready;
output s_axi_awready;
output [10:0]bram_addr_a;
output [11:0]s_axi_bid;
output [3:0]bram_we_a;
input [0:0]SR;
input s_axi_aclk;
input [10:0]s_axi_awaddr;
input s_axi_aresetn;
input [31:0]s_axi_wdata;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_bready;
input [1:0]s_axi_awburst;
input [11:0]s_axi_awid;
input s_axi_awvalid;
input [7:0]s_axi_awlen;
input [3:0]s_axi_wstrb;
wire BID_FIFO_n_0;
wire BID_FIFO_n_10;
wire BID_FIFO_n_11;
wire BID_FIFO_n_12;
wire BID_FIFO_n_13;
wire BID_FIFO_n_14;
wire BID_FIFO_n_15;
wire BID_FIFO_n_3;
wire BID_FIFO_n_4;
wire BID_FIFO_n_5;
wire BID_FIFO_n_6;
wire BID_FIFO_n_7;
wire BID_FIFO_n_8;
wire BID_FIFO_n_9;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_1_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_2_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_3_n_0 ;
wire \GEN_AW_DUAL.aw_active_i_2_n_0 ;
wire \GEN_AW_DUAL.aw_active_reg_0 ;
wire \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ;
wire \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ;
wire \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ;
wire \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ;
wire \I_RD_CHNL/axi_aresetn_d1 ;
wire I_WRAP_BRST_n_0;
wire I_WRAP_BRST_n_10;
wire I_WRAP_BRST_n_11;
wire I_WRAP_BRST_n_12;
wire I_WRAP_BRST_n_14;
wire I_WRAP_BRST_n_16;
wire I_WRAP_BRST_n_17;
wire I_WRAP_BRST_n_18;
wire I_WRAP_BRST_n_19;
wire I_WRAP_BRST_n_2;
wire I_WRAP_BRST_n_20;
wire I_WRAP_BRST_n_3;
wire I_WRAP_BRST_n_4;
wire I_WRAP_BRST_n_5;
wire I_WRAP_BRST_n_6;
wire I_WRAP_BRST_n_7;
wire I_WRAP_BRST_n_8;
wire I_WRAP_BRST_n_9;
wire [0:0]SR;
wire aw_active;
wire axi_aresetn_d2;
wire axi_aresetn_re;
wire axi_aresetn_re_reg;
wire axi_awaddr_full;
wire [1:0]axi_awburst_pipe;
wire [11:0]axi_awid_pipe;
wire [7:0]axi_awlen_pipe;
wire axi_awlen_pipe_1_or_2;
wire [1:1]axi_awsize_pipe;
wire axi_bvalid_int_i_1_n_0;
wire axi_wdata_full_cmb;
wire axi_wdata_full_cmb114_out;
wire axi_wdata_full_reg;
wire axi_wr_burst;
wire axi_wr_burst_cmb;
wire axi_wr_burst_cmb0;
wire axi_wr_burst_i_1_n_0;
wire axi_wr_burst_i_3_n_0;
wire axi_wready_int_mod_i_1_n_0;
wire axi_wready_int_mod_i_3_n_0;
wire bid_gets_fifo_load;
wire bid_gets_fifo_load_d1;
wire bid_gets_fifo_load_d1_i_2_n_0;
wire [10:0]bram_addr_a;
wire bram_addr_inc;
wire [10:10]bram_addr_ld;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_addr_rst_cmb;
wire bram_en_a;
wire bram_en_cmb;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire [2:0]bvalid_cnt;
wire \bvalid_cnt[0]_i_1_n_0 ;
wire \bvalid_cnt[1]_i_1_n_0 ;
wire \bvalid_cnt[2]_i_1_n_0 ;
wire bvalid_cnt_inc;
wire bvalid_cnt_inc11_out;
wire clr_bram_we;
wire clr_bram_we_cmb;
wire curr_awlen_reg_1_or_2;
wire curr_awlen_reg_1_or_20;
wire curr_awlen_reg_1_or_2_i_2_n_0;
wire curr_awlen_reg_1_or_2_i_3_n_0;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire delay_aw_active_clr;
wire last_data_ack_mod;
wire p_18_out;
wire p_9_out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [10:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire wr_addr_sm_cs;
(* RTL_KEEP = "yes" *) wire [2:0]wr_data_sm_cs;
zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO BID_FIFO
(.D({BID_FIFO_n_4,BID_FIFO_n_5,BID_FIFO_n_6,BID_FIFO_n_7,BID_FIFO_n_8,BID_FIFO_n_9,BID_FIFO_n_10,BID_FIFO_n_11,BID_FIFO_n_12,BID_FIFO_n_13,BID_FIFO_n_14,BID_FIFO_n_15}),
.E(BID_FIFO_n_0),
.\GEN_AWREADY.axi_aresetn_d2_reg (axi_aresetn_d2),
.\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg (\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.Q(axi_awid_pipe),
.SR(SR),
.aw_active(aw_active),
.axi_awaddr_full(axi_awaddr_full),
.axi_awlen_pipe_1_or_2(axi_awlen_pipe_1_or_2),
.axi_bvalid_int_reg(s_axi_bvalid),
.axi_wdata_full_cmb114_out(axi_wdata_full_cmb114_out),
.axi_wr_burst(axi_wr_burst),
.bid_gets_fifo_load(bid_gets_fifo_load),
.bid_gets_fifo_load_d1(bid_gets_fifo_load_d1),
.bid_gets_fifo_load_d1_reg(BID_FIFO_n_3),
.bram_addr_ld_en(bram_addr_ld_en),
.bvalid_cnt(bvalid_cnt),
.bvalid_cnt_inc(bvalid_cnt_inc),
.\bvalid_cnt_reg[1] (bid_gets_fifo_load_d1_i_2_n_0),
.\bvalid_cnt_reg[2] (I_WRAP_BRST_n_17),
.\bvalid_cnt_reg[2]_0 (I_WRAP_BRST_n_16),
.curr_awlen_reg_1_or_2(curr_awlen_reg_1_or_2),
.last_data_ack_mod(last_data_ack_mod),
.out(wr_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_awid(s_axi_awid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.wr_addr_sm_cs(wr_addr_sm_cs));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[0]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h05051F1A))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2
(.I0(wr_data_sm_cs[1]),
.I1(axi_wr_burst_cmb0),
.I2(wr_data_sm_cs[0]),
.I3(axi_wdata_full_cmb114_out),
.I4(wr_data_sm_cs[2]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT4 #(
.INIT(16'h5515))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3
(.I0(I_WRAP_BRST_n_18),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.O(axi_wr_burst_cmb0));
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[1]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000554000555540))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2
(.I0(wr_data_sm_cs[1]),
.I1(s_axi_wlast),
.I2(axi_wdata_full_cmb114_out),
.I3(wr_data_sm_cs[0]),
.I4(wr_data_sm_cs[2]),
.I5(axi_wr_burst),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[2]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h44010001))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2
(.I0(wr_data_sm_cs[2]),
.I1(wr_data_sm_cs[1]),
.I2(axi_wdata_full_cmb114_out),
.I3(wr_data_sm_cs[0]),
.I4(s_axi_wvalid),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h7774777774744444))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[1]),
.I3(s_axi_wlast),
.I4(wr_data_sm_cs[0]),
.I5(s_axi_wvalid),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ),
.Q(wr_data_sm_cs[0]),
.R(SR));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ),
.Q(wr_data_sm_cs[1]),
.R(SR));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ),
.Q(wr_data_sm_cs[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_aresetn),
.Q(\I_RD_CHNL/axi_aresetn_d1 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\I_RD_CHNL/axi_aresetn_d1 ),
.Q(axi_aresetn_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\GEN_AWREADY.axi_aresetn_re_reg_i_1
(.I0(s_axi_aresetn),
.I1(\I_RD_CHNL/axi_aresetn_d1 ),
.O(axi_aresetn_re));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_re_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_aresetn_re),
.Q(axi_aresetn_re_reg),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFBFBFFFFFAA00))
\GEN_AWREADY.axi_awready_int_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(bram_addr_ld_en),
.I4(axi_aresetn_re_reg),
.I5(s_axi_awready),
.O(\GEN_AWREADY.axi_awready_int_i_1_n_0 ));
LUT6 #(
.INIT(64'h5444444400000000))
\GEN_AWREADY.axi_awready_int_i_2
(.I0(\GEN_AWREADY.axi_awready_int_i_3_n_0 ),
.I1(aw_active),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[2]),
.I5(s_axi_awvalid),
.O(\GEN_AWREADY.axi_awready_int_i_2_n_0 ));
LUT6 #(
.INIT(64'hAABABABABABABABA))
\GEN_AWREADY.axi_awready_int_i_3
(.I0(wr_addr_sm_cs),
.I1(I_WRAP_BRST_n_18),
.I2(last_data_ack_mod),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\GEN_AWREADY.axi_awready_int_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_awready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AWREADY.axi_awready_int_i_1_n_0 ),
.Q(s_axi_awready),
.R(SR));
LUT1 #(
.INIT(2'h1))
\GEN_AW_DUAL.aw_active_i_1
(.I0(axi_aresetn_d2),
.O(\GEN_AW_DUAL.aw_active_reg_0 ));
LUT6 #(
.INIT(64'hFFFFF7FFFFFF0000))
\GEN_AW_DUAL.aw_active_i_2
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[0]),
.I2(wr_data_sm_cs[2]),
.I3(delay_aw_active_clr),
.I4(bram_addr_ld_en),
.I5(aw_active),
.O(\GEN_AW_DUAL.aw_active_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_DUAL.aw_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_DUAL.aw_active_i_2_n_0 ),
.Q(aw_active),
.R(\GEN_AW_DUAL.aw_active_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'h80))
\GEN_AW_DUAL.last_data_ack_mod_i_1
(.I0(s_axi_wready),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.O(p_18_out));
FDRE #(
.INIT(1'b0))
\GEN_AW_DUAL.last_data_ack_mod_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_18_out),
.Q(last_data_ack_mod),
.R(SR));
LUT6 #(
.INIT(64'h0010001000100000))
\GEN_AW_DUAL.wr_addr_sm_cs_i_1
(.I0(\GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ),
.I1(wr_addr_sm_cs),
.I2(s_axi_awvalid),
.I3(axi_awaddr_full),
.I4(I_WRAP_BRST_n_17),
.I5(aw_active),
.O(\GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000040))
\GEN_AW_DUAL.wr_addr_sm_cs_i_2
(.I0(I_WRAP_BRST_n_17),
.I1(last_data_ack_mod),
.I2(axi_awaddr_full),
.I3(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.I4(axi_awlen_pipe_1_or_2),
.I5(curr_awlen_reg_1_or_2),
.O(\GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ));
FDRE \GEN_AW_DUAL.wr_addr_sm_cs_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ),
.Q(wr_addr_sm_cs),
.R(\GEN_AW_DUAL.aw_active_reg_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[8]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[9]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[10]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[0]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[1]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[2]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[3]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[4]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[5]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[6]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[7]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.R(1'b0));
LUT5 #(
.INIT(32'h4000EA00))
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(s_axi_aresetn),
.I4(bram_addr_ld_en),
.O(\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ),
.Q(axi_awaddr_full),
.R(1'b0));
LUT6 #(
.INIT(64'hBF00BF00BF00FF40))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.I4(s_axi_awburst[0]),
.I5(s_axi_awburst[1]),
.O(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ),
.Q(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awburst[0]),
.Q(axi_awburst_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awburst[1]),
.Q(axi_awburst_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[0]),
.Q(axi_awid_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[10]),
.Q(axi_awid_pipe[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[11]),
.Q(axi_awid_pipe[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[1]),
.Q(axi_awid_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[2]),
.Q(axi_awid_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[3]),
.Q(axi_awid_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[4]),
.Q(axi_awid_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[5]),
.Q(axi_awid_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[6]),
.Q(axi_awid_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[7]),
.Q(axi_awid_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[8]),
.Q(axi_awid_pipe[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[9]),
.Q(axi_awid_pipe[9]),
.R(1'b0));
LUT3 #(
.INIT(8'h40))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.O(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0002))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1
(.I0(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ),
.I1(s_axi_awlen[3]),
.I2(s_axi_awlen[2]),
.I3(s_axi_awlen[1]),
.O(p_9_out));
LUT4 #(
.INIT(16'h0001))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2
(.I0(s_axi_awlen[4]),
.I1(s_axi_awlen[6]),
.I2(s_axi_awlen[7]),
.I3(s_axi_awlen[5]),
.O(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(p_9_out),
.Q(axi_awlen_pipe_1_or_2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[0]),
.Q(axi_awlen_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[1]),
.Q(axi_awlen_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[2]),
.Q(axi_awlen_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[3]),
.Q(axi_awlen_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[4]),
.Q(axi_awlen_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[5]),
.Q(axi_awlen_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[6]),
.Q(axi_awlen_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[7]),
.Q(axi_awlen_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(1'b1),
.Q(axi_awsize_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0
(.I0(bram_addr_a[4]),
.I1(bram_addr_a[1]),
.I2(bram_addr_a[0]),
.I3(bram_addr_a[2]),
.I4(bram_addr_a[3]),
.I5(bram_addr_a[5]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ));
LUT4 #(
.INIT(16'h1000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[0]),
.I3(s_axi_wvalid),
.O(bram_addr_inc));
LUT4 #(
.INIT(16'h1000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[0]),
.I3(wr_data_sm_cs[1]),
.O(bram_addr_rst_cmb));
LUT5 #(
.INIT(32'hF7FFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0
(.I0(bram_addr_a[6]),
.I1(bram_addr_a[4]),
.I2(I_WRAP_BRST_n_14),
.I3(bram_addr_a[5]),
.I4(bram_addr_a[7]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0 ));
LUT4 #(
.INIT(16'h00E2))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1
(.I0(bram_addr_a[10]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_ld),
.I3(I_WRAP_BRST_n_0),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_4),
.Q(bram_addr_a[8]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_3),
.Q(bram_addr_a[9]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1_n_0 ),
.Q(bram_addr_a[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_12),
.Q(bram_addr_a[0]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_11),
.Q(bram_addr_a[1]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_10),
.Q(bram_addr_a[2]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_9),
.Q(bram_addr_a[3]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_8),
.Q(bram_addr_a[4]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_7),
.Q(bram_addr_a[5]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_6),
.Q(bram_addr_a[6]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_5),
.Q(bram_addr_a[7]),
.R(I_WRAP_BRST_n_0));
LUT5 #(
.INIT(32'h15FF1500))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.I3(wr_data_sm_cs[2]),
.I4(axi_wready_int_mod_i_3_n_0),
.O(axi_wdata_full_cmb));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wdata_full_cmb),
.Q(axi_wdata_full_reg),
.R(SR));
LUT6 #(
.INIT(64'h4777477444444444))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[1]),
.I3(wr_data_sm_cs[0]),
.I4(axi_wdata_full_cmb114_out),
.I5(s_axi_wvalid),
.O(bram_en_cmb));
LUT3 #(
.INIT(8'h15))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bram_en_cmb),
.Q(bram_en_a),
.R(SR));
LUT6 #(
.INIT(64'h0010001000101110))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1
(.I0(wr_data_sm_cs[0]),
.I1(wr_data_sm_cs[1]),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ),
.I3(wr_data_sm_cs[2]),
.I4(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I5(axi_wr_burst),
.O(clr_bram_we_cmb));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'h80))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2
(.I0(axi_wdata_full_cmb114_out),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(clr_bram_we_cmb),
.Q(clr_bram_we),
.R(SR));
LUT6 #(
.INIT(64'hFEAAFEFF02AA0200))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ),
.I1(axi_wr_burst),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I3(wr_data_sm_cs[2]),
.I4(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ),
.I5(delay_aw_active_clr),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ));
LUT5 #(
.INIT(32'h0000222E))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2
(.I0(s_axi_wlast),
.I1(wr_data_sm_cs[2]),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I3(wr_data_sm_cs[0]),
.I4(wr_data_sm_cs[1]),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ));
LUT6 #(
.INIT(64'h8B338B0088008800))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3
(.I0(delay_aw_active_clr),
.I1(wr_data_sm_cs[1]),
.I2(axi_wr_burst_cmb0),
.I3(wr_data_sm_cs[0]),
.I4(axi_wdata_full_cmb114_out),
.I5(bvalid_cnt_inc11_out),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4
(.I0(s_axi_wvalid),
.I1(s_axi_wlast),
.O(bvalid_cnt_inc11_out));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ),
.Q(delay_aw_active_clr),
.R(SR));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[0].bram_wrdata_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[0]),
.Q(bram_wrdata_a[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[10].bram_wrdata_int_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[10]),
.Q(bram_wrdata_a[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[11].bram_wrdata_int_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[11]),
.Q(bram_wrdata_a[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[12].bram_wrdata_int_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[12]),
.Q(bram_wrdata_a[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[13].bram_wrdata_int_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[13]),
.Q(bram_wrdata_a[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[14].bram_wrdata_int_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[14]),
.Q(bram_wrdata_a[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[15].bram_wrdata_int_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[15]),
.Q(bram_wrdata_a[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[16].bram_wrdata_int_reg[16]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[16]),
.Q(bram_wrdata_a[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[17].bram_wrdata_int_reg[17]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[17]),
.Q(bram_wrdata_a[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[18].bram_wrdata_int_reg[18]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[18]),
.Q(bram_wrdata_a[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[19].bram_wrdata_int_reg[19]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[19]),
.Q(bram_wrdata_a[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[1].bram_wrdata_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[1]),
.Q(bram_wrdata_a[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[20].bram_wrdata_int_reg[20]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[20]),
.Q(bram_wrdata_a[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[21].bram_wrdata_int_reg[21]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[21]),
.Q(bram_wrdata_a[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[22].bram_wrdata_int_reg[22]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[22]),
.Q(bram_wrdata_a[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[23].bram_wrdata_int_reg[23]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[23]),
.Q(bram_wrdata_a[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[24].bram_wrdata_int_reg[24]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[24]),
.Q(bram_wrdata_a[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[25].bram_wrdata_int_reg[25]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[25]),
.Q(bram_wrdata_a[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[26].bram_wrdata_int_reg[26]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[26]),
.Q(bram_wrdata_a[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[27].bram_wrdata_int_reg[27]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[27]),
.Q(bram_wrdata_a[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[28].bram_wrdata_int_reg[28]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[28]),
.Q(bram_wrdata_a[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[29].bram_wrdata_int_reg[29]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[29]),
.Q(bram_wrdata_a[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[2].bram_wrdata_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[2]),
.Q(bram_wrdata_a[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[30].bram_wrdata_int_reg[30]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[30]),
.Q(bram_wrdata_a[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[31].bram_wrdata_int_reg[31]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[31]),
.Q(bram_wrdata_a[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[3].bram_wrdata_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[3]),
.Q(bram_wrdata_a[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[4].bram_wrdata_int_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[4]),
.Q(bram_wrdata_a[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[5].bram_wrdata_int_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[5]),
.Q(bram_wrdata_a[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[6].bram_wrdata_int_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[6]),
.Q(bram_wrdata_a[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[7].bram_wrdata_int_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[7]),
.Q(bram_wrdata_a[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[8].bram_wrdata_int_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[8]),
.Q(bram_wrdata_a[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[9].bram_wrdata_int_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[9]),
.Q(bram_wrdata_a[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hD0FF))
\GEN_WR_NO_ECC.bram_we_int[3]_i_1
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.I2(clr_bram_we),
.I3(s_axi_aresetn),
.O(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\GEN_WR_NO_ECC.bram_we_int[3]_i_2
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.O(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[0]),
.Q(bram_we_a[0]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[1]),
.Q(bram_we_a[1]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[2]),
.Q(bram_we_a[2]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[3]),
.Q(bram_we_a[3]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst I_WRAP_BRST
(.D({I_WRAP_BRST_n_3,I_WRAP_BRST_n_4,I_WRAP_BRST_n_5,I_WRAP_BRST_n_6,I_WRAP_BRST_n_7,I_WRAP_BRST_n_8,I_WRAP_BRST_n_9,I_WRAP_BRST_n_10,I_WRAP_BRST_n_11,I_WRAP_BRST_n_12}),
.E(I_WRAP_BRST_n_2),
.\GEN_AWREADY.axi_aresetn_d2_reg (axi_aresetn_d2),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg (\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] (I_WRAP_BRST_n_0),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] (\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] (I_WRAP_BRST_n_14),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 (\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6__0_n_0 ),
.Q(axi_awlen_pipe[3:0]),
.SR(SR),
.aw_active(aw_active),
.axi_awaddr_full(axi_awaddr_full),
.axi_awlen_pipe_1_or_2(axi_awlen_pipe_1_or_2),
.axi_awsize_pipe(axi_awsize_pipe),
.bram_addr_a(bram_addr_a[9:0]),
.bram_addr_inc(bram_addr_inc),
.bram_addr_ld_en(bram_addr_ld_en),
.bram_addr_ld_en_mod(bram_addr_ld_en_mod),
.bram_addr_rst_cmb(bram_addr_rst_cmb),
.bvalid_cnt(bvalid_cnt),
.curr_awlen_reg_1_or_2(curr_awlen_reg_1_or_2),
.curr_fixed_burst(curr_fixed_burst),
.curr_fixed_burst_reg(curr_fixed_burst_reg),
.curr_fixed_burst_reg_reg(I_WRAP_BRST_n_19),
.curr_wrap_burst(curr_wrap_burst),
.curr_wrap_burst_reg(curr_wrap_burst_reg),
.curr_wrap_burst_reg_reg(I_WRAP_BRST_n_20),
.last_data_ack_mod(last_data_ack_mod),
.out(wr_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen[3:0]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wvalid(s_axi_wvalid),
.\save_init_bram_addr_ld_reg[12]_0 (bram_addr_ld),
.\save_init_bram_addr_ld_reg[12]_1 (I_WRAP_BRST_n_16),
.\save_init_bram_addr_ld_reg[12]_2 (I_WRAP_BRST_n_17),
.\save_init_bram_addr_ld_reg[12]_3 (I_WRAP_BRST_n_18),
.wr_addr_sm_cs(wr_addr_sm_cs));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[0]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_15),
.Q(s_axi_bid[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[10]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_5),
.Q(s_axi_bid[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[11]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_4),
.Q(s_axi_bid[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[1]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_14),
.Q(s_axi_bid[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[2]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_13),
.Q(s_axi_bid[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[3]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_12),
.Q(s_axi_bid[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[4]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_11),
.Q(s_axi_bid[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[5]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_10),
.Q(s_axi_bid[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[6]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_9),
.Q(s_axi_bid[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[7]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_8),
.Q(s_axi_bid[7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[8]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_7),
.Q(s_axi_bid[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[9]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_6),
.Q(s_axi_bid[9]),
.R(SR));
LUT6 #(
.INIT(64'hAAAAAAAAAAAA8A88))
axi_bvalid_int_i_1
(.I0(s_axi_aresetn),
.I1(bvalid_cnt_inc),
.I2(BID_FIFO_n_3),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[2]),
.I5(bvalid_cnt[1]),
.O(axi_bvalid_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_bvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_bvalid_int_i_1_n_0),
.Q(s_axi_bvalid),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
axi_wr_burst_i_1
(.I0(axi_wr_burst_cmb),
.I1(axi_wr_burst_i_3_n_0),
.I2(axi_wr_burst),
.O(axi_wr_burst_i_1_n_0));
LUT5 #(
.INIT(32'h3088FCBB))
axi_wr_burst_i_2
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[1]),
.I2(axi_wr_burst_cmb0),
.I3(wr_data_sm_cs[0]),
.I4(s_axi_wlast),
.O(axi_wr_burst_cmb));
LUT6 #(
.INIT(64'h00000000AAAAA222))
axi_wr_burst_i_3
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[0]),
.I2(axi_wr_burst_cmb0),
.I3(s_axi_wlast),
.I4(wr_data_sm_cs[1]),
.I5(wr_data_sm_cs[2]),
.O(axi_wr_burst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_wr_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wr_burst_i_1_n_0),
.Q(axi_wr_burst),
.R(SR));
LUT6 #(
.INIT(64'hEA00EAFF00000000))
axi_wready_int_mod_i_1
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.I3(wr_data_sm_cs[2]),
.I4(axi_wready_int_mod_i_3_n_0),
.I5(s_axi_aresetn),
.O(axi_wready_int_mod_i_1_n_0));
LUT5 #(
.INIT(32'hF8F9F0F0))
axi_wready_int_mod_i_3
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[0]),
.I2(axi_wdata_full_reg),
.I3(axi_wdata_full_cmb114_out),
.I4(s_axi_wvalid),
.O(axi_wready_int_mod_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_wready_int_mod_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wready_int_mod_i_1_n_0),
.Q(s_axi_wready),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hEF))
bid_gets_fifo_load_d1_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.O(bid_gets_fifo_load_d1_i_2_n_0));
FDRE #(
.INIT(1'b0))
bid_gets_fifo_load_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bid_gets_fifo_load),
.Q(bid_gets_fifo_load_d1),
.R(SR));
LUT6 #(
.INIT(64'h95956A6A95956AAA))
\bvalid_cnt[0]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hD5D5BFBF2A2A4000))
\bvalid_cnt[1]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hD52AFF00FF00BF00))
\bvalid_cnt[2]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[0]_i_1_n_0 ),
.Q(bvalid_cnt[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[1]_i_1_n_0 ),
.Q(bvalid_cnt[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[2]_i_1_n_0 ),
.Q(bvalid_cnt[2]),
.R(SR));
LUT6 #(
.INIT(64'h5000303050003000))
curr_awlen_reg_1_or_2_i_1
(.I0(axi_awlen_pipe[3]),
.I1(s_axi_awlen[3]),
.I2(curr_awlen_reg_1_or_2_i_2_n_0),
.I3(curr_awlen_reg_1_or_2_i_3_n_0),
.I4(axi_awaddr_full),
.I5(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ),
.O(curr_awlen_reg_1_or_20));
LUT5 #(
.INIT(32'h00053305))
curr_awlen_reg_1_or_2_i_2
(.I0(s_axi_awlen[2]),
.I1(axi_awlen_pipe[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(axi_awlen_pipe[1]),
.O(curr_awlen_reg_1_or_2_i_2_n_0));
LUT5 #(
.INIT(32'h00000100))
curr_awlen_reg_1_or_2_i_3
(.I0(axi_awlen_pipe[4]),
.I1(axi_awlen_pipe[7]),
.I2(axi_awlen_pipe[6]),
.I3(axi_awaddr_full),
.I4(axi_awlen_pipe[5]),
.O(curr_awlen_reg_1_or_2_i_3_n_0));
FDRE #(
.INIT(1'b0))
curr_awlen_reg_1_or_2_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_awlen_reg_1_or_20),
.Q(curr_awlen_reg_1_or_2),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT5 #(
.INIT(32'h00053305))
curr_fixed_burst_reg_i_2
(.I0(s_axi_awburst[1]),
.I1(axi_awburst_pipe[1]),
.I2(s_axi_awburst[0]),
.I3(axi_awaddr_full),
.I4(axi_awburst_pipe[0]),
.O(curr_fixed_burst));
FDRE #(
.INIT(1'b0))
curr_fixed_burst_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_WRAP_BRST_n_19),
.Q(curr_fixed_burst_reg),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT5 #(
.INIT(32'h000ACC0A))
curr_wrap_burst_reg_i_2
(.I0(s_axi_awburst[1]),
.I1(axi_awburst_pipe[1]),
.I2(s_axi_awburst[0]),
.I3(axi_awaddr_full),
.I4(axi_awburst_pipe[0]),
.O(curr_wrap_burst));
FDRE #(
.INIT(1'b0))
curr_wrap_burst_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_WRAP_BRST_n_20),
.Q(curr_wrap_burst_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "wrap_brst" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst
(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ,
bram_addr_ld_en_mod,
E,
D,
\save_init_bram_addr_ld_reg[12]_0 ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ,
bram_addr_ld_en,
\save_init_bram_addr_ld_reg[12]_1 ,
\save_init_bram_addr_ld_reg[12]_2 ,
\save_init_bram_addr_ld_reg[12]_3 ,
curr_fixed_burst_reg_reg,
curr_wrap_burst_reg_reg,
curr_fixed_burst_reg,
bram_addr_inc,
bram_addr_rst_cmb,
s_axi_aresetn,
out,
s_axi_wvalid,
bram_addr_a,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ,
axi_awaddr_full,
s_axi_awaddr,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ,
\GEN_AWREADY.axi_aresetn_d2_reg ,
wr_addr_sm_cs,
last_data_ack_mod,
bvalid_cnt,
aw_active,
s_axi_awvalid,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ,
axi_awlen_pipe_1_or_2,
curr_awlen_reg_1_or_2,
curr_wrap_burst_reg,
Q,
s_axi_awlen,
axi_awsize_pipe,
curr_fixed_burst,
curr_wrap_burst,
SR,
s_axi_aclk);
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
output bram_addr_ld_en_mod;
output [0:0]E;
output [9:0]D;
output [0:0]\save_init_bram_addr_ld_reg[12]_0 ;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
output bram_addr_ld_en;
output \save_init_bram_addr_ld_reg[12]_1 ;
output \save_init_bram_addr_ld_reg[12]_2 ;
output \save_init_bram_addr_ld_reg[12]_3 ;
output curr_fixed_burst_reg_reg;
output curr_wrap_burst_reg_reg;
input curr_fixed_burst_reg;
input bram_addr_inc;
input bram_addr_rst_cmb;
input s_axi_aresetn;
input [2:0]out;
input s_axi_wvalid;
input [9:0]bram_addr_a;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
input axi_awaddr_full;
input [10:0]s_axi_awaddr;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input wr_addr_sm_cs;
input last_data_ack_mod;
input [2:0]bvalid_cnt;
input aw_active;
input s_axi_awvalid;
input \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
input axi_awlen_pipe_1_or_2;
input curr_awlen_reg_1_or_2;
input curr_wrap_burst_reg;
input [3:0]Q;
input [3:0]s_axi_awlen;
input [0:0]axi_awsize_pipe;
input curr_fixed_burst;
input curr_wrap_burst;
input [0:0]SR;
input s_axi_aclk;
wire [9:0]D;
wire [0:0]E;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ;
wire [3:0]Q;
wire [0:0]SR;
wire aw_active;
wire axi_awaddr_full;
wire axi_awlen_pipe_1_or_2;
wire [0:0]axi_awsize_pipe;
wire [9:0]bram_addr_a;
wire bram_addr_inc;
wire [9:1]bram_addr_ld;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_addr_rst_cmb;
wire [2:0]bvalid_cnt;
wire curr_awlen_reg_1_or_2;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_fixed_burst_reg_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire curr_wrap_burst_reg_reg;
wire last_data_ack_mod;
wire [2:0]out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [10:0]s_axi_awaddr;
wire [3:0]s_axi_awlen;
wire s_axi_awvalid;
wire s_axi_wvalid;
wire [12:3]save_init_bram_addr_ld;
wire \save_init_bram_addr_ld[12]_i_6_n_0 ;
wire \save_init_bram_addr_ld[3]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[4]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[5]_i_2__0_n_0 ;
wire [0:0]\save_init_bram_addr_ld_reg[12]_0 ;
wire \save_init_bram_addr_ld_reg[12]_1 ;
wire \save_init_bram_addr_ld_reg[12]_2 ;
wire \save_init_bram_addr_ld_reg[12]_3 ;
wire wr_addr_sm_cs;
wire [2:0]wrap_burst_total;
wire \wrap_burst_total[0]_i_1__0_n_0 ;
wire \wrap_burst_total[0]_i_2__0_n_0 ;
wire \wrap_burst_total[0]_i_3_n_0 ;
wire \wrap_burst_total[1]_i_1__0_n_0 ;
wire \wrap_burst_total[1]_i_2__0_n_0 ;
wire \wrap_burst_total[1]_i_3__0_n_0 ;
wire \wrap_burst_total[2]_i_1__0_n_0 ;
wire \wrap_burst_total[2]_i_2__0_n_0 ;
wire \wrap_burst_total[2]_i_3_n_0 ;
LUT6 #(
.INIT(64'hBB8BBBBB88B88888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1
(.I0(bram_addr_ld[8]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[6]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(bram_addr_a[7]),
.I5(bram_addr_a[8]),
.O(D[8]));
LUT5 #(
.INIT(32'h4500FFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0
(.I0(bram_addr_ld_en_mod),
.I1(curr_fixed_burst_reg),
.I2(bram_addr_inc),
.I3(bram_addr_rst_cmb),
.I4(s_axi_aresetn),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ));
LUT6 #(
.INIT(64'hAAABAAAAAAAAAAAA))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2
(.I0(bram_addr_ld_en_mod),
.I1(curr_fixed_burst_reg),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(s_axi_wvalid),
.O(E));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3
(.I0(bram_addr_ld[9]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[9]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ),
.I4(bram_addr_a[8]),
.O(D[9]));
LUT6 #(
.INIT(64'hAAABAAAAAAAAAAAA))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_2
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0 ),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(s_axi_wvalid),
.O(bram_addr_ld_en_mod));
LUT6 #(
.INIT(64'h55555555FFFFFFDF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3
(.I0(curr_wrap_burst_reg),
.I1(wrap_burst_total[1]),
.I2(wrap_burst_total[2]),
.I3(wrap_burst_total[0]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000000008F00C000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4
(.I0(bram_addr_a[2]),
.I1(bram_addr_a[1]),
.I2(wrap_burst_total[1]),
.I3(bram_addr_a[0]),
.I4(wrap_burst_total[0]),
.I5(wrap_burst_total[2]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_4_n_0 ));
LUT6 #(
.INIT(64'hB800B800B800FFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1
(.I0(\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.I1(axi_awaddr_full),
.I2(s_axi_awaddr[0]),
.I3(bram_addr_ld_en),
.I4(bram_addr_ld_en_mod),
.I5(bram_addr_a[0]),
.O(D[0]));
LUT4 #(
.INIT(16'h8BB8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1
(.I0(bram_addr_ld[1]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[1]),
.I3(bram_addr_a[0]),
.O(D[1]));
LUT5 #(
.INIT(32'h8BB8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1
(.I0(bram_addr_ld[2]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[2]),
.I3(bram_addr_a[0]),
.I4(bram_addr_a[1]),
.O(D[2]));
LUT6 #(
.INIT(64'h8BB8B8B8B8B8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1
(.I0(bram_addr_ld[3]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[3]),
.I3(bram_addr_a[2]),
.I4(bram_addr_a[0]),
.I5(bram_addr_a[1]),
.O(D[3]));
LUT4 #(
.INIT(16'hB88B))
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1
(.I0(bram_addr_ld[4]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[4]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.O(D[4]));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1
(.I0(bram_addr_ld[5]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[5]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I4(bram_addr_a[4]),
.O(D[5]));
LUT6 #(
.INIT(64'hB8B88BB8B8B8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1
(.I0(bram_addr_ld[6]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[6]),
.I3(bram_addr_a[4]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I5(bram_addr_a[5]),
.O(D[6]));
LUT4 #(
.INIT(16'h7FFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0
(.I0(bram_addr_a[1]),
.I1(bram_addr_a[0]),
.I2(bram_addr_a[2]),
.I3(bram_addr_a[3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1
(.I0(bram_addr_ld[7]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[7]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(bram_addr_a[6]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT4 #(
.INIT(16'h00E2))
curr_fixed_burst_reg_i_1__0
(.I0(curr_fixed_burst_reg),
.I1(bram_addr_ld_en),
.I2(curr_fixed_burst),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.O(curr_fixed_burst_reg_reg));
LUT4 #(
.INIT(16'h00E2))
curr_wrap_burst_reg_i_1__0
(.I0(curr_wrap_burst_reg),
.I1(bram_addr_ld_en),
.I2(curr_wrap_burst),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.O(curr_wrap_burst_reg_reg));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[10]_i_1
(.I0(save_init_bram_addr_ld[10]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[8]),
.O(bram_addr_ld[8]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[11]_i_1
(.I0(save_init_bram_addr_ld[11]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[9]),
.O(bram_addr_ld[9]));
LUT6 #(
.INIT(64'h0808080808AA0808))
\save_init_bram_addr_ld[12]_i_1
(.I0(\GEN_AWREADY.axi_aresetn_d2_reg ),
.I1(\save_init_bram_addr_ld_reg[12]_1 ),
.I2(wr_addr_sm_cs),
.I3(\save_init_bram_addr_ld_reg[12]_2 ),
.I4(last_data_ack_mod),
.I5(\save_init_bram_addr_ld_reg[12]_3 ),
.O(bram_addr_ld_en));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[12]_i_2
(.I0(save_init_bram_addr_ld[12]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[10]),
.O(\save_init_bram_addr_ld_reg[12]_0 ));
LUT6 #(
.INIT(64'h007F007F007F0000))
\save_init_bram_addr_ld[12]_i_3
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.I3(aw_active),
.I4(axi_awaddr_full),
.I5(s_axi_awvalid),
.O(\save_init_bram_addr_ld_reg[12]_1 ));
LUT3 #(
.INIT(8'h80))
\save_init_bram_addr_ld[12]_i_4
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.O(\save_init_bram_addr_ld_reg[12]_2 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT4 #(
.INIT(16'hFFFD))
\save_init_bram_addr_ld[12]_i_5
(.I0(axi_awaddr_full),
.I1(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ),
.I2(axi_awlen_pipe_1_or_2),
.I3(curr_awlen_reg_1_or_2),
.O(\save_init_bram_addr_ld_reg[12]_3 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT2 #(
.INIT(4'h1))
\save_init_bram_addr_ld[12]_i_6
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_3_n_0 ),
.O(\save_init_bram_addr_ld[12]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[3]_i_1
(.I0(\save_init_bram_addr_ld[3]_i_2__0_n_0 ),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[1]),
.O(bram_addr_ld[1]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT4 #(
.INIT(16'hC80C))
\save_init_bram_addr_ld[3]_i_2__0
(.I0(wrap_burst_total[0]),
.I1(save_init_bram_addr_ld[3]),
.I2(wrap_burst_total[1]),
.I3(wrap_burst_total[2]),
.O(\save_init_bram_addr_ld[3]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[4]_i_1
(.I0(\save_init_bram_addr_ld[4]_i_2__0_n_0 ),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[2]),
.O(bram_addr_ld[2]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT4 #(
.INIT(16'hA28A))
\save_init_bram_addr_ld[4]_i_2__0
(.I0(save_init_bram_addr_ld[4]),
.I1(wrap_burst_total[0]),
.I2(wrap_burst_total[2]),
.I3(wrap_burst_total[1]),
.O(\save_init_bram_addr_ld[4]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h8F808F8F8F808080))
\save_init_bram_addr_ld[5]_i_1
(.I0(save_init_bram_addr_ld[5]),
.I1(\save_init_bram_addr_ld[5]_i_2__0_n_0 ),
.I2(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I3(\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.I4(axi_awaddr_full),
.I5(s_axi_awaddr[3]),
.O(bram_addr_ld[3]));
LUT3 #(
.INIT(8'hFB))
\save_init_bram_addr_ld[5]_i_2__0
(.I0(wrap_burst_total[0]),
.I1(wrap_burst_total[2]),
.I2(wrap_burst_total[1]),
.O(\save_init_bram_addr_ld[5]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[6]_i_1
(.I0(save_init_bram_addr_ld[6]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[4]),
.O(bram_addr_ld[4]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[7]_i_1
(.I0(save_init_bram_addr_ld[7]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[5]),
.O(bram_addr_ld[5]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[8]_i_1
(.I0(save_init_bram_addr_ld[8]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[6]),
.O(bram_addr_ld[6]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[9]_i_1
(.I0(save_init_bram_addr_ld[9]),
.I1(\save_init_bram_addr_ld[12]_i_6_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[7]),
.O(bram_addr_ld[7]));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[10]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[8]),
.Q(save_init_bram_addr_ld[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[11]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[9]),
.Q(save_init_bram_addr_ld[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld_reg[12]_0 ),
.Q(save_init_bram_addr_ld[12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[3]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[1]),
.Q(save_init_bram_addr_ld[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[4]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[2]),
.Q(save_init_bram_addr_ld[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[5]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[3]),
.Q(save_init_bram_addr_ld[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[6]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[4]),
.Q(save_init_bram_addr_ld[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[7]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[5]),
.Q(save_init_bram_addr_ld[7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[8]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[6]),
.Q(save_init_bram_addr_ld[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[9]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[7]),
.Q(save_init_bram_addr_ld[9]),
.R(SR));
LUT6 #(
.INIT(64'h0000A22200000000))
\wrap_burst_total[0]_i_1__0
(.I0(\wrap_burst_total[0]_i_2__0_n_0 ),
.I1(\wrap_burst_total[0]_i_3_n_0 ),
.I2(Q[1]),
.I3(Q[2]),
.I4(\wrap_burst_total[2]_i_2__0_n_0 ),
.I5(\wrap_burst_total[1]_i_2__0_n_0 ),
.O(\wrap_burst_total[0]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hCCA533A5FFA5FFA5))
\wrap_burst_total[0]_i_2__0
(.I0(s_axi_awlen[2]),
.I1(Q[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(Q[1]),
.I5(axi_awsize_pipe),
.O(\wrap_burst_total[0]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT2 #(
.INIT(4'h2))
\wrap_burst_total[0]_i_3
(.I0(axi_awaddr_full),
.I1(axi_awsize_pipe),
.O(\wrap_burst_total[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h08000800F3000000))
\wrap_burst_total[1]_i_1__0
(.I0(\wrap_burst_total[2]_i_3_n_0 ),
.I1(axi_awaddr_full),
.I2(axi_awsize_pipe),
.I3(\wrap_burst_total[1]_i_2__0_n_0 ),
.I4(\wrap_burst_total[1]_i_3__0_n_0 ),
.I5(\wrap_burst_total[2]_i_2__0_n_0 ),
.O(\wrap_burst_total[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_2__0
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[0]),
.O(\wrap_burst_total[1]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_3__0
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[1]),
.O(\wrap_burst_total[1]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hA000000088008800))
\wrap_burst_total[2]_i_1__0
(.I0(\wrap_burst_total[2]_i_2__0_n_0 ),
.I1(s_axi_awlen[0]),
.I2(Q[0]),
.I3(\wrap_burst_total[2]_i_3_n_0 ),
.I4(axi_awsize_pipe),
.I5(axi_awaddr_full),
.O(\wrap_burst_total[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[2]_i_2__0
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[3]),
.O(\wrap_burst_total[2]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT5 #(
.INIT(32'hCCA000A0))
\wrap_burst_total[2]_i_3
(.I0(s_axi_awlen[2]),
.I1(Q[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(Q[1]),
.O(\wrap_burst_total[2]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[0]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[0]_i_1__0_n_0 ),
.Q(wrap_burst_total[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[1]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[1]_i_1__0_n_0 ),
.Q(wrap_burst_total[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[2]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[2]_i_1__0_n_0 ),
.Q(wrap_burst_total[2]),
.R(SR));
endmodule
(* ORIG_REF_NAME = "wrap_brst" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0
(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ,
SR,
\wrap_burst_total_reg[0]_0 ,
\wrap_burst_total_reg[0]_1 ,
\wrap_burst_total_reg[0]_2 ,
\wrap_burst_total_reg[0]_3 ,
E,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ,
D,
bram_addr_ld_en,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ,
\save_init_bram_addr_ld_reg[12]_0 ,
\rd_data_sm_cs_reg[1] ,
\save_init_bram_addr_ld_reg[12]_1 ,
axi_b2b_brst_reg,
\rd_data_sm_cs_reg[3] ,
rd_adv_buf67_out,
end_brst_rd,
brst_zero,
Q,
axi_rvalid_int_reg,
s_axi_rready,
s_axi_aresetn,
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ,
axi_arsize_pipe,
axi_araddr_full,
s_axi_arlen,
curr_fixed_burst_reg,
s_axi_araddr,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ,
curr_wrap_burst_reg,
axi_rd_burst_two_reg,
axi_rd_burst,
axi_aresetn_d2,
rd_addr_sm_cs,
last_bram_addr,
ar_active,
pend_rd_op,
no_ar_ack,
s_axi_arvalid,
axi_b2b_brst,
axi_arsize_pipe_max,
disable_b2b_brst,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ,
axi_arlen_pipe_1_or_2,
s_axi_aclk);
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
output [0:0]SR;
output \wrap_burst_total_reg[0]_0 ;
output \wrap_burst_total_reg[0]_1 ;
output \wrap_burst_total_reg[0]_2 ;
output \wrap_burst_total_reg[0]_3 ;
output [0:0]E;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ;
output [9:0]D;
output bram_addr_ld_en;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
output [0:0]\save_init_bram_addr_ld_reg[12]_0 ;
output \rd_data_sm_cs_reg[1] ;
output \save_init_bram_addr_ld_reg[12]_1 ;
output axi_b2b_brst_reg;
output \rd_data_sm_cs_reg[3] ;
output rd_adv_buf67_out;
input end_brst_rd;
input brst_zero;
input [3:0]Q;
input axi_rvalid_int_reg;
input s_axi_rready;
input s_axi_aresetn;
input [3:0]\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ;
input [0:0]axi_arsize_pipe;
input axi_araddr_full;
input [3:0]s_axi_arlen;
input curr_fixed_burst_reg;
input [10:0]s_axi_araddr;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
input [9:0]\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
input curr_wrap_burst_reg;
input axi_rd_burst_two_reg;
input axi_rd_burst;
input axi_aresetn_d2;
input rd_addr_sm_cs;
input last_bram_addr;
input ar_active;
input pend_rd_op;
input no_ar_ack;
input s_axi_arvalid;
input axi_b2b_brst;
input axi_arsize_pipe_max;
input disable_b2b_brst;
input \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ;
input axi_arlen_pipe_1_or_2;
input s_axi_aclk;
wire [9:0]D;
wire [0:0]E;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ;
wire [3:0]\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ;
wire [9:0]\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
wire [3:0]Q;
wire [0:0]SR;
wire ar_active;
wire axi_araddr_full;
wire axi_aresetn_d2;
wire axi_arlen_pipe_1_or_2;
wire [0:0]axi_arsize_pipe;
wire axi_arsize_pipe_max;
wire axi_b2b_brst;
wire axi_b2b_brst_reg;
wire axi_rd_burst;
wire axi_rd_burst_two_reg;
wire axi_rvalid_int_reg;
wire bram_addr_ld_en;
wire brst_zero;
wire curr_fixed_burst_reg;
wire curr_wrap_burst_reg;
wire disable_b2b_brst;
wire end_brst_rd;
wire last_bram_addr;
wire no_ar_ack;
wire pend_rd_op;
wire rd_addr_sm_cs;
wire rd_adv_buf67_out;
wire \rd_data_sm_cs_reg[1] ;
wire \rd_data_sm_cs_reg[3] ;
wire s_axi_aclk;
wire [10:0]s_axi_araddr;
wire s_axi_aresetn;
wire [3:0]s_axi_arlen;
wire s_axi_arvalid;
wire s_axi_rready;
wire \save_init_bram_addr_ld[10]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[11]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[12]_i_3__0_n_0 ;
wire \save_init_bram_addr_ld[3]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[3]_i_2_n_0 ;
wire \save_init_bram_addr_ld[4]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[4]_i_2_n_0 ;
wire \save_init_bram_addr_ld[5]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[5]_i_2_n_0 ;
wire \save_init_bram_addr_ld[6]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[7]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[8]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[9]_i_1__0_n_0 ;
wire [0:0]\save_init_bram_addr_ld_reg[12]_0 ;
wire \save_init_bram_addr_ld_reg[12]_1 ;
wire \save_init_bram_addr_ld_reg_n_0_[10] ;
wire \save_init_bram_addr_ld_reg_n_0_[11] ;
wire \save_init_bram_addr_ld_reg_n_0_[12] ;
wire \save_init_bram_addr_ld_reg_n_0_[3] ;
wire \save_init_bram_addr_ld_reg_n_0_[4] ;
wire \save_init_bram_addr_ld_reg_n_0_[5] ;
wire \save_init_bram_addr_ld_reg_n_0_[6] ;
wire \save_init_bram_addr_ld_reg_n_0_[7] ;
wire \save_init_bram_addr_ld_reg_n_0_[8] ;
wire \save_init_bram_addr_ld_reg_n_0_[9] ;
wire \wrap_burst_total[0]_i_1_n_0 ;
wire \wrap_burst_total[0]_i_3__0_n_0 ;
wire \wrap_burst_total[1]_i_1_n_0 ;
wire \wrap_burst_total[2]_i_1_n_0 ;
wire \wrap_burst_total[2]_i_2_n_0 ;
wire \wrap_burst_total_reg[0]_0 ;
wire \wrap_burst_total_reg[0]_1 ;
wire \wrap_burst_total_reg[0]_2 ;
wire \wrap_burst_total_reg[0]_3 ;
wire \wrap_burst_total_reg_n_0_[0] ;
wire \wrap_burst_total_reg_n_0_[1] ;
wire \wrap_burst_total_reg_n_0_[2] ;
LUT6 #(
.INIT(64'hDF20FFFFDF200000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [7]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [8]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I5(\save_init_bram_addr_ld[10]_i_1__0_n_0 ),
.O(D[8]));
LUT3 #(
.INIT(8'h5D))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ),
.I2(curr_fixed_burst_reg),
.O(E));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [9]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [8]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I4(\save_init_bram_addr_ld[11]_i_1__0_n_0 ),
.O(D[9]));
LUT6 #(
.INIT(64'hE0E0F0F0E0E0FFF0))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ),
.I2(\rd_data_sm_cs_reg[1] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.I4(Q[1]),
.I5(Q[3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ));
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0
(.I0(axi_rd_burst_two_reg),
.I1(Q[0]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h0000000080800080))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6
(.I0(Q[0]),
.I1(axi_rvalid_int_reg),
.I2(s_axi_rready),
.I3(end_brst_rd),
.I4(axi_b2b_brst),
.I5(brst_zero),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ));
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_2__0
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ));
LUT6 #(
.INIT(64'h00000000A808FD5D))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0
(.I0(bram_addr_ld_en),
.I1(s_axi_araddr[0]),
.I2(axi_araddr_full),
.I3(\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.O(D[0]));
LUT5 #(
.INIT(32'h88A80000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0 ),
.I2(\save_init_bram_addr_ld[5]_i_2_n_0 ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(curr_wrap_burst_reg),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000000008F00A000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [2]),
.I2(\wrap_burst_total_reg_n_0_[1] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I4(\wrap_burst_total_reg_n_0_[0] ),
.I5(\wrap_burst_total_reg_n_0_[2] ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_3_n_0 ));
LUT4 #(
.INIT(16'h6F60))
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I3(\save_init_bram_addr_ld[3]_i_1__0_n_0 ),
.O(D[1]));
LUT5 #(
.INIT(32'h6AFF6A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [2]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I4(\save_init_bram_addr_ld[4]_i_1__0_n_0 ),
.O(D[2]));
LUT6 #(
.INIT(64'h6AAAFFFF6AAA0000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [3]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [2]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I5(\save_init_bram_addr_ld[5]_i_1__0_n_0 ),
.O(D[3]));
LUT4 #(
.INIT(16'h9F90))
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [4]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I3(\save_init_bram_addr_ld[6]_i_1__0_n_0 ),
.O(D[4]));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [5]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [4]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I4(\save_init_bram_addr_ld[7]_i_1__0_n_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hA6AAFFFFA6AA0000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [4]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [5]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I5(\save_init_bram_addr_ld[8]_i_1__0_n_0 ),
.O(D[6]));
LUT4 #(
.INIT(16'h7FFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [2]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [7]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_2 [6]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I4(\save_init_bram_addr_ld[9]_i_1__0_n_0 ),
.O(D[7]));
LUT2 #(
.INIT(4'h8))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4
(.I0(axi_rvalid_int_reg),
.I1(s_axi_rready),
.O(rd_adv_buf67_out));
LUT5 #(
.INIT(32'hFFFDFFFF))
axi_b2b_brst_i_2
(.I0(axi_arsize_pipe_max),
.I1(disable_b2b_brst),
.I2(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ),
.I3(axi_arlen_pipe_1_or_2),
.I4(axi_araddr_full),
.O(axi_b2b_brst_reg));
LUT2 #(
.INIT(4'hB))
bram_en_int_i_5
(.I0(Q[3]),
.I1(Q[2]),
.O(\rd_data_sm_cs_reg[3] ));
LUT6 #(
.INIT(64'h0010000000000000))
bram_en_int_i_8
(.I0(end_brst_rd),
.I1(brst_zero),
.I2(Q[2]),
.I3(Q[0]),
.I4(axi_rvalid_int_reg),
.I5(s_axi_rready),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ));
LUT1 #(
.INIT(2'h1))
bram_rst_b_INST_0
(.I0(s_axi_aresetn),
.O(SR));
LUT6 #(
.INIT(64'h000F000E000F0000))
\rd_data_sm_cs[1]_i_2
(.I0(axi_rd_burst_two_reg),
.I1(axi_rd_burst),
.I2(Q[3]),
.I3(Q[2]),
.I4(Q[1]),
.I5(Q[0]),
.O(\rd_data_sm_cs_reg[1] ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[10]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[10] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[8]),
.O(\save_init_bram_addr_ld[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[11]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[11] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[9]),
.O(\save_init_bram_addr_ld[11]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'h02AA0202))
\save_init_bram_addr_ld[12]_i_1__0
(.I0(axi_aresetn_d2),
.I1(rd_addr_sm_cs),
.I2(\save_init_bram_addr_ld[12]_i_3__0_n_0 ),
.I3(\save_init_bram_addr_ld_reg[12]_1 ),
.I4(last_bram_addr),
.O(bram_addr_ld_en));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[12]_i_2__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[12] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[10]),
.O(\save_init_bram_addr_ld_reg[12]_0 ));
LUT5 #(
.INIT(32'hFEFEFEFF))
\save_init_bram_addr_ld[12]_i_3__0
(.I0(ar_active),
.I1(pend_rd_op),
.I2(no_ar_ack),
.I3(s_axi_arvalid),
.I4(axi_araddr_full),
.O(\save_init_bram_addr_ld[12]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAABAAABAFFFFAABA))
\save_init_bram_addr_ld[12]_i_4__0
(.I0(axi_b2b_brst_reg),
.I1(Q[0]),
.I2(Q[1]),
.I3(\rd_data_sm_cs_reg[3] ),
.I4(brst_zero),
.I5(rd_adv_buf67_out),
.O(\save_init_bram_addr_ld_reg[12]_1 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[3]_i_1__0
(.I0(\save_init_bram_addr_ld[3]_i_2_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[1]),
.O(\save_init_bram_addr_ld[3]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'hA282))
\save_init_bram_addr_ld[3]_i_2
(.I0(\save_init_bram_addr_ld_reg_n_0_[3] ),
.I1(\wrap_burst_total_reg_n_0_[1] ),
.I2(\wrap_burst_total_reg_n_0_[2] ),
.I3(\wrap_burst_total_reg_n_0_[0] ),
.O(\save_init_bram_addr_ld[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[4]_i_1__0
(.I0(\save_init_bram_addr_ld[4]_i_2_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[2]),
.O(\save_init_bram_addr_ld[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hA28A))
\save_init_bram_addr_ld[4]_i_2
(.I0(\save_init_bram_addr_ld_reg_n_0_[4] ),
.I1(\wrap_burst_total_reg_n_0_[0] ),
.I2(\wrap_burst_total_reg_n_0_[2] ),
.I3(\wrap_burst_total_reg_n_0_[1] ),
.O(\save_init_bram_addr_ld[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h2F202F2F2F202020))
\save_init_bram_addr_ld[5]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[5] ),
.I1(\save_init_bram_addr_ld[5]_i_2_n_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I3(\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.I4(axi_araddr_full),
.I5(s_axi_araddr[3]),
.O(\save_init_bram_addr_ld[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h04))
\save_init_bram_addr_ld[5]_i_2
(.I0(\wrap_burst_total_reg_n_0_[0] ),
.I1(\wrap_burst_total_reg_n_0_[2] ),
.I2(\wrap_burst_total_reg_n_0_[1] ),
.O(\save_init_bram_addr_ld[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[6]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[6] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[4]),
.O(\save_init_bram_addr_ld[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[7]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[7] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[5]),
.O(\save_init_bram_addr_ld[7]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[8]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[8] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[6]),
.O(\save_init_bram_addr_ld[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[9]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[9] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_2_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[7]),
.O(\save_init_bram_addr_ld[9]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[10]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[10]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[10] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[11]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[11]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[11] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld_reg[12]_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[12] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[3]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[3]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[3] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[4]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[4]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[4] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[5]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[5]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[5] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[6]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[6]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[6] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[7]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[7]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[7] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[8]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[8]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[8] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[9]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[9]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[9] ),
.R(SR));
LUT6 #(
.INIT(64'h3202010100000000))
\wrap_burst_total[0]_i_1
(.I0(\wrap_burst_total_reg[0]_0 ),
.I1(\wrap_burst_total_reg[0]_1 ),
.I2(\wrap_burst_total[0]_i_3__0_n_0 ),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I4(\wrap_burst_total_reg[0]_2 ),
.I5(\wrap_burst_total_reg[0]_3 ),
.O(\wrap_burst_total[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_2
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[2]),
.O(\wrap_burst_total_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
\wrap_burst_total[0]_i_3__0
(.I0(axi_araddr_full),
.I1(axi_arsize_pipe),
.O(\wrap_burst_total[0]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h20CF000000000000))
\wrap_burst_total[1]_i_1
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I1(axi_arsize_pipe),
.I2(axi_araddr_full),
.I3(\wrap_burst_total_reg[0]_1 ),
.I4(\wrap_burst_total_reg[0]_3 ),
.I5(\wrap_burst_total_reg[0]_2 ),
.O(\wrap_burst_total[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_2
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [3]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[3]),
.O(\wrap_burst_total_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_3
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [0]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[0]),
.O(\wrap_burst_total_reg[0]_3 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_4
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [1]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[1]),
.O(\wrap_burst_total_reg[0]_2 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0000D580))
\wrap_burst_total[2]_i_1
(.I0(axi_araddr_full),
.I1(axi_arsize_pipe),
.I2(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I3(s_axi_arlen[2]),
.I4(\wrap_burst_total[2]_i_2_n_0 ),
.O(\wrap_burst_total[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3FFF5F5F3FFFFFFF))
\wrap_burst_total[2]_i_2
(.I0(s_axi_arlen[3]),
.I1(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [3]),
.I2(\wrap_burst_total_reg[0]_3 ),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [1]),
.I4(axi_araddr_full),
.I5(s_axi_arlen[1]),
.O(\wrap_burst_total[2]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[0]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[0]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[1]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[1]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[1] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[2]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[2]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[2] ),
.R(SR));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// div_pipelined.v
// Created: 4.3.2012
// Modified: 4.5.2012
//
// Testbench for div_pipelined.v
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_div_pipelined();
reg clk, start, reset_n;
reg [7:0] dividend, divisor;
wire data_valid, div_by_zero;
wire [7:0] quotient, quotient_correct;
parameter
BITS = 8;
div_pipelined
#(
.BITS(BITS)
)
div_pipelined
(
.clk(clk),
.reset_n(reset_n),
.dividend(dividend),
.divisor(divisor),
.quotient(quotient),
.div_by_zero(div_by_zero),
// .quotient_correct(quotient_correct),
.start(start),
.data_valid(data_valid)
);
initial begin
#10 reset_n = 0;
#50 reset_n = 1;
#1
clk = 0;
dividend = -1;
divisor = 127;
#1000 $finish;
end
// always
// #20 dividend = dividend + 1;
always begin
#10 divisor = divisor - 1; start = 1;
#10 start = 0;
end
always
#5 clk = ~clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4B_4_V
`define SKY130_FD_SC_LP__AND4B_4_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4b_4 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4b_4 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4B_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A21OI_FUNCTIONAL_PP_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21OI_FUNCTIONAL_PP_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:29:47 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_processing_system7_0_2_stub.v
// Design : zynq_design_1_processing_system7_0_2
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
`timescale 1ns / 1ps
// UART wants the LSB first
// RX modified to accept 40 MHz clock and receive at 115200 bps
// Note 40e6 / 115200 = 347.2222 and 347.2 / 2 = 173.6 ~= 174 cycles
// For 460800
// 40e6 / 460800 = 86.8 and 86.8 / 2 =~= 43
// For 230400
// 40e6 / 230400 = 173.6 and 173.6/2 = 86.8
// Modified for 460800 baud rate
module uart2_tx #(parameter WIDTH = 8, parameter real BAUD = 9600) (
input reset,
input clk,
//input [1:0] baud_rate,
input ld_tx_data,
input [WIDTH-1:0] tx_data,
input tx_enable,
(* IOB = "TRUE" *) output reg tx_out = 1'b1,
output reg tx_empty = 1'b1
);
//parameter ML505 = 0; //default to 0 if not specified
`ifdef ML505 localparam real CLK_FREQ = 100e6;
`else localparam real CLK_FREQ = 40e6;
`endif
localparam BAUD_CNT_SIZE = bits_to_fit(CLK_FREQ/BAUD);
localparam BIT_CNT_SIZE = bits_to_fit(WIDTH+2);
localparam [BAUD_CNT_SIZE-1:0] FRAME_WIDTH = CLK_FREQ/BAUD;
// Internal registers
reg [WIDTH-1:0] tx_reg = {WIDTH{1'b0}};
reg [BIT_CNT_SIZE-1:0] tx_cnt = {BIT_CNT_SIZE{1'b0}};
reg [BAUD_CNT_SIZE-1:0] baud_cnt = {BAUD_CNT_SIZE{1'b0}};
reg baud_clk = 1'b0;
// UART TX Logic
always @ (posedge clk) begin
if (reset) begin
baud_clk <= 1'b0;
baud_cnt <= {BAUD_CNT_SIZE{1'b0}};
tx_reg <= {WIDTH{1'b0}};
tx_empty <= 1'b1;
tx_out <= 1'b1;
tx_cnt <= {BIT_CNT_SIZE{1'b0}};
end else begin // if (reset)
if (baud_cnt == FRAME_WIDTH) begin
baud_clk <= 1'b1;
baud_cnt <= {BAUD_CNT_SIZE{1'b0}};
end else begin
baud_clk <= 1'b0;
baud_cnt <= baud_cnt + 1'b1;
end
if (tx_enable && baud_clk) begin
if (ld_tx_data && tx_empty) begin
tx_reg <= tx_data;
tx_empty <= 1'b0;
tx_out <= 1'b0; //Send start bit immediately
tx_cnt <= tx_cnt;
end else if (!tx_empty) begin
tx_reg <= tx_reg;
if (tx_cnt == 4'd8) begin
tx_cnt <= 4'd0;
tx_out <= 1'b1;
tx_empty <= 1'b1;
end else begin
tx_cnt <= tx_cnt + 1;
tx_out <= tx_reg[tx_cnt];
tx_empty <= tx_empty;
end
end else begin
tx_reg <= tx_reg;
tx_cnt <= tx_cnt;
tx_out <= tx_out;
tx_empty <= tx_empty;
end
end else begin
tx_reg <= tx_reg;
tx_cnt <= tx_cnt;
tx_out <= tx_out;
tx_empty <= tx_empty;
end //if (~(tx_enable && baud_clk))
end //if (~reset)
end //always
function integer bits_to_fit;
input [31:0] value;
for (bits_to_fit=0; value>0; bits_to_fit=bits_to_fit+1)
value = value >> 1;
endfunction
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC FSM ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Insn cache state machine ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_ic_fsm.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.10 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.9 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.8.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.8 2003/06/06 02:54:47 lampret
// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
//
// Revision 1.7 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.6 2002/03/28 19:10:40 lampret
// Optimized cache controller FSM.
//
// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
`define OR1200_ICFSM_IDLE 2'd0
`define OR1200_ICFSM_CFETCH 2'd1
`define OR1200_ICFSM_LREFILL3 2'd2
`define OR1200_ICFSM_IFETCH 2'd3
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
module or1200_ic_fsm(
// Clock and reset
clk, rst,
// Internal i/f to top level IC
ic_en, icqmem_cycstb_i, icqmem_ci_i,
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
burst, tag_we
);
//
// I/O
//
input clk;
input rst;
input ic_en;
input icqmem_cycstb_i;
input icqmem_ci_i;
input tagcomp_miss;
input biudata_valid;
input biudata_error;
input [31:0] start_addr;
output [31:0] saved_addr;
output [3:0] icram_we;
output biu_read;
output first_hit_ack;
output first_miss_ack;
output first_miss_err;
output burst;
output tag_we;
//
// Internal wires and regs
//
reg [31:0] saved_addr_r;
reg [1:0] state;
reg [2:0] cnt;
reg hitmiss_eval;
reg load;
reg cache_inhibit;
//
// Generate of ICRAM write enables
//
assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
assign saved_addr = saved_addr_r;
//
// Assert for cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icqmem_ci_i;
assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & !cache_inhibit
| (state == `OR1200_ICFSM_LREFILL3);
//
// Main IC FSM
//
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= #1 `OR1200_ICFSM_IDLE;
saved_addr_r <= #1 32'b0;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cnt <= #1 3'b000;
cache_inhibit <= #1 1'b0;
end
else
case (state) // synopsys parallel_case
`OR1200_ICFSM_IDLE :
if (ic_en & icqmem_cycstb_i) begin // fetch
state <= #1 `OR1200_ICFSM_CFETCH;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b1;
load <= #1 1'b1;
cache_inhibit <= #1 1'b0;
end
else begin // idle
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
`OR1200_ICFSM_CFETCH: begin // fetch
if (icqmem_cycstb_i & icqmem_ci_i)
cache_inhibit <= #1 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= #1 start_addr[31:13];
if ((!ic_en) ||
(hitmiss_eval & !icqmem_cycstb_i) || // fetch aborted (usually caused by IMMU)
(biudata_error) || // fetch terminated with an error
(cache_inhibit & biudata_valid)) begin // fetch from cache-inhibited page
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill
state <= #1 `OR1200_ICFSM_LREFILL3;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
hitmiss_eval <= #1 1'b0;
cnt <= #1 `OR1200_ICLS-2;
cache_inhibit <= #1 1'b0;
end
else if (!tagcomp_miss & !icqmem_ci_i) begin // fetch hit, finish immediately
saved_addr_r <= #1 start_addr;
cache_inhibit <= #1 1'b0;
end
else if (!icqmem_cycstb_i) begin // fetch aborted (usually caused by exception)
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else // fetch in-progress
hitmiss_eval <= #1 1'b0;
end
`OR1200_ICFSM_LREFILL3 : begin
if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
cnt <= #1 cnt - 3'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
end
else if (biudata_valid) begin // last fetch of line refill
state <= #1 `OR1200_ICFSM_IDLE;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
end
end
default:
state <= #1 `OR1200_ICFSM_IDLE;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP2_TB_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP2_TB_V
/**
* busdrivernovlp2: Bus driver, enable gates pulldown only (pmos
* devices).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busdrivernovlp2.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__busdrivernovlp2 dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP2_TB_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: spu_mamul.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: state machine to do MA mul/acc/shf.
*/
////////////////////////////////////////////////////////////////////////
module spu_mamul (
/*outputs*/
spu_mamul_memren,
spu_mamul_memwen,
spu_mamul_rst_iptr,
spu_mamul_rst_jptr,
spu_mamul_incr_iptr,
spu_mamul_incr_jptr,
spu_mamul_a_rd_oprnd_sel,
spu_mamul_ax_rd_oprnd_sel,
spu_mamul_b_rd_oprnd_sel,
spu_mamul_ba_rd_oprnd_sel,
spu_mamul_m_rd_oprnd_sel,
spu_mamul_me_rd_oprnd_sel,
spu_mamul_n_rd_oprnd_sel,
spu_mamul_m_wr_oprnd_sel,
spu_mamul_me_wr_oprnd_sel,
spu_mamul_i_ptr_sel,
spu_mamul_iminus1_ptr_sel,
spu_mamul_j_ptr_sel,
spu_mamul_iminusj_ptr_sel,
spu_mamul_iminuslenminus1_sel,
spu_mamul_jjptr_wen,
spu_mamul_oprnd2_wen,
spu_mamul_oprnd2_bypass,
spu_mamul_oprnd1_mxsel_l,
spu_mamul_oprnd1_wen,
spu_mul_req_vld,
spu_mul_areg_shf,
spu_mul_acc,
spu_mul_areg_rst,
spu_mamul_mul_done,
spu_mamul_jjptr_sel,
spu_mamul_rst,
/*inputs*/
spu_maaeqb_jjptr_sel,
spu_mactl_mulop,
spu_maaddr_iequtwolenplus2,
spu_maaddr_iequtwolenplus1,
spu_maaddr_jequiminus1,
spu_maaddr_jequlen,
spu_maaddr_halfpnt_set,
spu_mactl_iss_pulse_dly,
spu_mared_oprnd2_wen,
mul_spu_ack,
mul_spu_shf_ack,
spu_maexp_start_mulred_anoteqb,
spu_mactl_expop,
spu_maaddr_aequb,
spu_maaeqb_rst_iptr,
spu_maaeqb_rst_jptr,
spu_maaeqb_incr_iptr,
spu_maaeqb_incr_jptr,
spu_maaeqb_a_rd_oprnd_sel,
spu_maaeqb_ax_rd_oprnd_sel,
spu_maaeqb_m_rd_oprnd_sel,
spu_maaeqb_me_rd_oprnd_sel,
spu_maaeqb_n_rd_oprnd_sel,
spu_maaeqb_m_wr_oprnd_sel,
spu_maaeqb_me_wr_oprnd_sel,
spu_maaeqb_iminus1_ptr_sel,
spu_maaeqb_j_ptr_sel,
spu_maaeqb_iminusj_ptr_sel,
spu_maaeqb_iminuslenminus1_sel,
spu_maaeqb_jjptr_wen,
spu_maaeqb_oprnd2_wen,
spu_maaeqb_oprnd2_bypass,
spu_maaeqb_mul_req_vld,
spu_maaeqb_mul_areg_shf,
spu_maaeqb_mul_acc,
spu_maaeqb_mul_areg_rst,
spu_maaeqb_mul_done,
spu_maaeqb_oprnd1_mxsel,
spu_maaeqb_oprnd1_wen,
spu_mactl_kill_op,
spu_mactl_stxa_force_abort,
se,
reset,
rclk);
// ---------------------------------------------------------------
input reset;
input rclk;
input se;
input spu_maaddr_iequtwolenplus2;
input spu_maaddr_iequtwolenplus1;
input spu_maaddr_jequiminus1;
input spu_maaddr_jequlen;
input spu_maaddr_halfpnt_set;
input mul_spu_ack;
input mul_spu_shf_ack;
input spu_mactl_mulop;
input spu_mactl_iss_pulse_dly;
input spu_mared_oprnd2_wen;
input spu_maexp_start_mulred_anoteqb;
input spu_mactl_expop;
input spu_maaddr_aequb;
input spu_maaeqb_rst_iptr;
input spu_maaeqb_rst_jptr;
input spu_maaeqb_incr_iptr;
input spu_maaeqb_incr_jptr;
input spu_maaeqb_a_rd_oprnd_sel;
input spu_maaeqb_ax_rd_oprnd_sel;
input spu_maaeqb_m_rd_oprnd_sel;
input spu_maaeqb_me_rd_oprnd_sel;
input spu_maaeqb_n_rd_oprnd_sel;
input spu_maaeqb_m_wr_oprnd_sel;
input spu_maaeqb_me_wr_oprnd_sel;
input spu_maaeqb_iminus1_ptr_sel;
input spu_maaeqb_j_ptr_sel;
input spu_maaeqb_iminusj_ptr_sel;
input spu_maaeqb_iminuslenminus1_sel;
input spu_maaeqb_jjptr_wen;
input spu_maaeqb_oprnd2_wen;
input spu_maaeqb_oprnd2_bypass;
input spu_maaeqb_mul_req_vld;
input spu_maaeqb_mul_areg_shf;
input spu_maaeqb_mul_acc;
input spu_maaeqb_mul_areg_rst;
input spu_maaeqb_mul_done;
input [1:0] spu_maaeqb_oprnd1_mxsel;
input spu_maaeqb_oprnd1_wen;
input spu_maaeqb_jjptr_sel;
input spu_mactl_kill_op;
input spu_mactl_stxa_force_abort;
// ---------------------------------------------------------------
output spu_mamul_memwen;
output spu_mamul_memren;
output spu_mamul_rst_iptr;
output spu_mamul_rst_jptr;
output spu_mamul_incr_iptr;
output spu_mamul_incr_jptr;
output spu_mamul_a_rd_oprnd_sel;
output spu_mamul_ax_rd_oprnd_sel;
output spu_mamul_b_rd_oprnd_sel;
output spu_mamul_ba_rd_oprnd_sel;
output spu_mamul_m_rd_oprnd_sel;
output spu_mamul_me_rd_oprnd_sel;
output spu_mamul_n_rd_oprnd_sel;
output spu_mamul_m_wr_oprnd_sel;
output spu_mamul_me_wr_oprnd_sel;
output spu_mamul_i_ptr_sel;
output spu_mamul_iminus1_ptr_sel;
output spu_mamul_j_ptr_sel;
output spu_mamul_iminusj_ptr_sel;
output spu_mamul_iminuslenminus1_sel;
output spu_mamul_jjptr_wen;
output spu_mamul_oprnd2_wen;
output spu_mamul_oprnd2_bypass;
output [2:0] spu_mamul_oprnd1_mxsel_l;
output spu_mamul_oprnd1_wen;
output spu_mul_req_vld;
output spu_mul_areg_shf;
output spu_mul_acc;
output spu_mul_areg_rst;
output spu_mamul_mul_done;
output spu_mamul_jjptr_sel;
output spu_mamul_rst;
// ---------------------------------------------------------------
wire tr2mwrite_frm_accumshft_pre;
wire tr2mwrite_frm_accumshft,tr2iloopa_frm_jloopn;
wire spu_mamul_rd_aj,spu_mamul_rd_biminusj,spu_mamul_rd_mj,
spu_mamul_rd_niminusj,spu_mamul_rd_ai,spu_mamul_rd_b0,
spu_mamul_wr_mi,spu_mamul_wr_miminuslenminus1,
spu_mamul_rd_n0;
wire tr2accumshft_frm_mwrite;
wire tr2accumshft_frm_iloopn;
wire nxt_mwrite_state;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
//wire local_stxa_abort = cur_mwrite_state & spu_mactl_stxa_force_abort;// this causes x to in perr_set
wire local_stxa_abort = nxt_mwrite_state & spu_mactl_stxa_force_abort;
wire state_reset = reset | spu_mactl_kill_op | local_stxa_abort;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
dff_s #(1) idle_state_ff (
.din(nxt_idle_state) ,
.q(cur_idle_state),
.clk (rclk), .se(se), .si(), .so());
dffr_s #(1) jloopa_state_ff (
.din(nxt_jloopa_state) ,
.q(cur_jloopa_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) jloopb_state_ff (
.din(nxt_jloopb_state) ,
.q(cur_jloopb_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) jloopn_state_ff (
.din(nxt_jloopn_state) ,
.q(cur_jloopn_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) jloopm_state_ff (
.din(nxt_jloopm_state) ,
.q(cur_jloopm_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) iloopa_state_ff (
.din(nxt_iloopa_state) ,
.q(cur_iloopa_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) iloopb_state_ff (
.din(nxt_iloopb_state) ,
.q(cur_iloopb_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) nprime_state_ff (
.din(nxt_nprime_state) ,
.q(cur_nprime_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) mwrite_state_ff (
.din(nxt_mwrite_state) ,
.q(cur_mwrite_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) iloopn_state_ff (
.din(nxt_iloopn_state) ,
.q(cur_iloopn_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) accumshft_state_ff (
.din(nxt_accumshft_state) ,
.q(cur_accumshft_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
// ---------------------------------------------------------------
wire spu_maaddr_aequb_q;
dff_s #(1) spu_maaddr_aequb_ff (
.din(spu_maaddr_aequb) ,
.q(spu_maaddr_aequb_q),
.clk (rclk), .se(se), .si(), .so());
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// 4 cycle delay for mul result coming back.
// ---------------------------------------------------------------
wire tr2mwrite_frm_jloopn = cur_jloopn_state & mul_spu_ack & spu_maaddr_halfpnt_set &
spu_maaddr_jequlen;
wire mul_result_c0,mul_result_c1,mul_result_c2,mul_result_c3,mul_result_c4,mul_result_c5;
//assign mul_result_c0 = (cur_nprime_state & mul_spu_ack & ~spu_maaddr_halfpnt_set) |
assign mul_result_c0 = (cur_nprime_state & mul_spu_ack) |
( tr2mwrite_frm_jloopn );
dffr_s #(5) mul_res_ff (
.din({mul_result_c0,mul_result_c1,mul_result_c2,mul_result_c3,mul_result_c4}) ,
.q({mul_result_c1,mul_result_c2,mul_result_c3,mul_result_c4,mul_result_c5}),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
wire tr2idle_frm_accumshft = cur_accumshft_state & spu_maaddr_iequtwolenplus2 &
mul_spu_shf_ack;
wire spu_mamul_mul_done_pre = tr2idle_frm_accumshft;
wire spu_mamul_mul_done_q;
dff_s #(1) muldone_dly_ff (
.din(spu_mamul_mul_done_pre) ,
.q(spu_mamul_mul_done_q),
.clk (rclk), .se(se), .si(), .so());
assign spu_mamul_mul_done = spu_mamul_mul_done_q | spu_maaeqb_mul_done | local_stxa_abort;
assign spu_mamul_rst_iptr = tr2idle_frm_accumshft | spu_maaeqb_rst_iptr;
// the following is to reset jptr on the 1st half.
wire tr2iloopa_frm_jloopn_dly;
dff_s #(1) tr2iloopa_frm_jloopn_dly_ff (
.din(tr2iloopa_frm_jloopn) ,
.q(tr2iloopa_frm_jloopn_dly),
.clk (rclk), .se(se), .si(), .so());
// ---------------------------------------------------------------
wire mulop_start = (spu_mactl_iss_pulse_dly & spu_mactl_mulop & ~spu_maaddr_aequb_q) |
spu_maexp_start_mulred_anoteqb;
assign spu_mul_areg_rst = mulop_start | spu_maaeqb_mul_areg_rst;
assign spu_mamul_rst = spu_mul_areg_rst;
assign nxt_idle_state = (
state_reset |
tr2idle_frm_accumshft |
(cur_idle_state & ~mulop_start));
// ---------------------------------------------------------------
wire tr2jloopa_frm_accumshft = cur_accumshft_state & ~spu_maaddr_iequtwolenplus2 &
~spu_maaddr_iequtwolenplus1 & mul_spu_shf_ack;
wire tr2jloopa_frm_accumshft_dly;
dffr_s #(1) tr2jloopa_frm_accumshft_dly_ff (
.din(tr2jloopa_frm_accumshft) ,
.q(tr2jloopa_frm_accumshft_dly),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
wire tr2jloopa_frm_jloopn = cur_jloopn_state & mul_spu_ack &
((~spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set) |
(~spu_maaddr_jequlen & spu_maaddr_halfpnt_set)) ;
assign nxt_jloopa_state = (
tr2jloopa_frm_jloopn |
tr2jloopa_frm_accumshft_dly );
assign spu_mamul_jjptr_wen = cur_jloopm_state | spu_maaeqb_jjptr_wen;
assign spu_mamul_incr_jptr = tr2jloopa_frm_jloopn | spu_maaeqb_incr_jptr;
assign spu_mamul_jjptr_sel = cur_jloopn_state | spu_maaeqb_jjptr_sel;
//assign spu_mamul_rd_aj = nxt_jloopa_state;
assign spu_mamul_rd_aj =
(cur_jloopn_state & ((~spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set) |
(~spu_maaddr_jequlen & spu_maaddr_halfpnt_set))) |
tr2jloopa_frm_accumshft_dly;
// ---------------------------------------------------------------
assign nxt_jloopb_state = (
cur_jloopa_state |
(cur_jloopb_state & ~mul_spu_ack));
//assign spu_mamul_rd_biminusj = nxt_jloopb_state | cur_jloopb_state;
assign spu_mamul_rd_biminusj = cur_jloopa_state;
// ---------------------------------------------------------------
assign nxt_jloopm_state = (
(cur_jloopb_state & mul_spu_ack));
//assign spu_mamul_rd_mj = nxt_jloopm_state;
assign spu_mamul_rd_mj = cur_jloopb_state;
// ---------------------------------------------------------------
assign nxt_jloopn_state = (
cur_jloopm_state |
(cur_jloopn_state & ~mul_spu_ack));
//assign spu_mamul_rd_niminusj = nxt_jloopn_state;
assign spu_mamul_rd_niminusj = cur_jloopm_state;
// ---------------------------------------------------------------
assign tr2iloopa_frm_jloopn = cur_jloopn_state & mul_spu_ack &
spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set;
wire tr2iloopa_frm_idle = cur_idle_state & mulop_start;
wire tr2iloopa_frm_idle_dly;
dff_s #(1) tr2iloopa_frm_idle_ff (
.din(tr2iloopa_frm_idle) ,
.q(tr2iloopa_frm_idle_dly),
.clk (rclk), .se(se), .si(), .so());
assign nxt_iloopa_state = (
(tr2iloopa_frm_idle_dly) |
(tr2iloopa_frm_jloopn));
// iloop reads are done in cur_* state where as the jloop reads
// are done in nxt_* and cur_* state(this to hold the rd indx during
// requests. Due to read of the iloop in cur_* state the spu_mul_req_vld
// is delayed by a cycle.
//assign spu_mamul_rd_ai = nxt_iloopa_state;
assign spu_mamul_rd_ai =
(cur_jloopn_state & (spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set)) | tr2iloopa_frm_idle_dly;
// ---------------------------------------------------------------
assign nxt_iloopb_state = (
(cur_iloopa_state) |
(cur_iloopb_state & ~mul_spu_ack));
//assign spu_mamul_rd_b0 = nxt_iloopb_state;
assign spu_mamul_rd_b0 = cur_iloopa_state;
// ---------------------------------------------------------------
assign nxt_nprime_state = (
(cur_iloopb_state & mul_spu_ack) |
(cur_nprime_state & ~mul_spu_ack));
// ---------------------------------------------------------------
// assign tr2mwrite_frm_accumshft = cur_accumshft_state & mul_spu_shf_ack &
// spu_maaddr_iequtwolenplus1;
assign tr2mwrite_frm_accumshft_pre = cur_accumshft_state & mul_spu_shf_ack &
spu_maaddr_iequtwolenplus1;
// delaying for one cycle to allow time to do i ptr increment
// and calculate i-len-1(M[i-len-1]).This is due to skipping jloop on last
// i iteration, not enough time to do both.
dffr_s #(1) tr2mwrite_frm_accumshft_ff (
.din(tr2mwrite_frm_accumshft_pre) ,
.q(tr2mwrite_frm_accumshft),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
assign nxt_mwrite_state = (
tr2mwrite_frm_accumshft |
(mul_result_c5));
// assign spu_mamul_memwen = nxt_mwrite_state;
//need the following to capture mul data into flop.
wire spu_mamul_wr_mi_oprnd2_wenbyp = nxt_mwrite_state & ~spu_maaddr_halfpnt_set;
wire spu_mamul_wr_miminuslenminus1_oprnd2_wenbyp = nxt_mwrite_state & spu_maaddr_halfpnt_set;
// ---------------------------------------------------------------
assign nxt_iloopn_state = (
(cur_mwrite_state & ~spu_maaddr_halfpnt_set) |
(cur_iloopn_state & ~mul_spu_ack));
//assign spu_mamul_rd_n0 = nxt_iloopn_state | cur_iloopn_state;
assign spu_mamul_rd_n0 = cur_mwrite_state;
// ---------------------------------------------------------------
assign tr2accumshft_frm_mwrite = cur_mwrite_state & spu_maaddr_halfpnt_set;
assign tr2accumshft_frm_iloopn = cur_iloopn_state & mul_spu_ack;
assign nxt_accumshft_state = (
tr2accumshft_frm_mwrite |
tr2accumshft_frm_iloopn |
(cur_accumshft_state & ~mul_spu_shf_ack));
wire mamul_incr_iptr = tr2accumshft_frm_mwrite | tr2accumshft_frm_iloopn;
assign spu_mamul_incr_iptr = mamul_incr_iptr | spu_maaeqb_incr_iptr;
dff_s #(1) memwen_dly_ff (
.din(mamul_incr_iptr) ,
.q(spu_mamul_memwen),
.clk (rclk), .se(se), .si(), .so());
assign spu_mamul_wr_mi = spu_mamul_memwen & ~spu_maaddr_halfpnt_set;
assign spu_mamul_wr_miminuslenminus1 = spu_mamul_memwen & spu_maaddr_halfpnt_set;
// ---------------------------------------------------------------
wire cur_accumshft_pulse,cur_accumshft_q;
dff_s #(1) cur_accumshft_pulse_ff (
.din(cur_accumshft_state) ,
.q(cur_accumshft_q),
.clk (rclk), .se(se), .si(), .so());
assign cur_accumshft_pulse = ~cur_accumshft_q & cur_accumshft_state;
wire mamul_rst_jptr = mulop_start | tr2iloopa_frm_jloopn_dly | (cur_accumshft_pulse &
spu_maaddr_halfpnt_set & ~spu_maaddr_iequtwolenplus2 &
~spu_maaddr_iequtwolenplus1);
assign spu_mamul_rst_jptr = mamul_rst_jptr | spu_maaeqb_rst_jptr;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// send selects to spu_maaddr.v
// ---------------------------------------------------------------
// ---------------------------------------------------------------
assign spu_mamul_memren = spu_mamul_rd_aj |
spu_mamul_rd_biminusj |
spu_mamul_rd_mj |
spu_mamul_rd_niminusj |
spu_mamul_rd_ai | spu_mamul_rd_b0 | spu_mamul_rd_n0;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
wire mamul_a_rd_oprnd_sel = (spu_mamul_rd_aj | spu_mamul_rd_ai) & ~spu_mactl_expop;
assign spu_mamul_a_rd_oprnd_sel = mamul_a_rd_oprnd_sel | spu_maaeqb_a_rd_oprnd_sel;
wire mamul_ax_rd_oprnd_sel = (spu_mamul_rd_aj | spu_mamul_rd_ai) & spu_mactl_expop;
assign spu_mamul_ax_rd_oprnd_sel = mamul_ax_rd_oprnd_sel | spu_maaeqb_ax_rd_oprnd_sel;
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//assign spu_mamul_b_rd_oprnd_sel = ((spu_mamul_rd_biminusj & ~spu_mamul_rd_aj & ~spu_mamul_rd_mj) |
assign spu_mamul_b_rd_oprnd_sel = (spu_mamul_rd_biminusj |
spu_mamul_rd_b0) & ~spu_mactl_expop;
// bx should be removed, since xxnm does not start mamul, instead it starts maaeqb.
// assign spu_mamul_bx_rd_oprnd_sel = ((spu_mamul_rd_biminusj & ~spu_mamul_rd_aj & ~spu_mamul_rd_mj) |
// spu_mamul_rd_b0) & spu_maexp_b_to_x_sel & spu_mactl_expop;
//assign spu_mamul_ba_rd_oprnd_sel = ((spu_mamul_rd_biminusj & ~spu_mamul_rd_aj & ~spu_mamul_rd_mj) |
assign spu_mamul_ba_rd_oprnd_sel = (spu_mamul_rd_biminusj |
spu_mamul_rd_b0) & spu_mactl_expop;
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
wire mamul_m_rd_oprnd_sel = spu_mamul_rd_mj & ~spu_mactl_expop ;
assign spu_mamul_m_rd_oprnd_sel = mamul_m_rd_oprnd_sel | spu_maaeqb_m_rd_oprnd_sel ;
wire mamul_me_rd_oprnd_sel = spu_mamul_rd_mj & spu_mactl_expop ;
assign spu_mamul_me_rd_oprnd_sel = mamul_me_rd_oprnd_sel | spu_maaeqb_me_rd_oprnd_sel ;
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//wire mamul_n_rd_oprnd_sel = (spu_mamul_rd_niminusj & ~spu_mamul_rd_aj & ~spu_mamul_rd_mj) | spu_mamul_rd_n0;
wire mamul_n_rd_oprnd_sel = spu_mamul_rd_niminusj | spu_mamul_rd_n0;
assign spu_mamul_n_rd_oprnd_sel = mamul_n_rd_oprnd_sel | spu_maaeqb_n_rd_oprnd_sel;
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
wire mamul_m_wr_oprnd_sel = (spu_mamul_wr_mi | spu_mamul_wr_miminuslenminus1) &
~spu_mactl_expop;
assign spu_mamul_m_wr_oprnd_sel = mamul_m_wr_oprnd_sel | spu_maaeqb_m_wr_oprnd_sel;
wire mamul_me_wr_oprnd_sel = (spu_mamul_wr_mi | spu_mamul_wr_miminuslenminus1) &
spu_mactl_expop;
assign spu_mamul_me_wr_oprnd_sel = mamul_me_wr_oprnd_sel | spu_maaeqb_me_wr_oprnd_sel;
wire mamul_m_wr_oprnd2_wen = (spu_mamul_wr_mi_oprnd2_wenbyp |
spu_mamul_wr_miminuslenminus1_oprnd2_wenbyp) &
~spu_mactl_expop;
wire mamul_me_wr_oprnd2_wen = (spu_mamul_wr_mi_oprnd2_wenbyp |
spu_mamul_wr_miminuslenminus1_oprnd2_wenbyp) &
spu_mactl_expop;
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//assign spu_mamul_i_ptr_sel = (spu_mamul_rd_ai | spu_mamul_wr_mi) | spu_maaeqb_i_ptr_sel;
assign spu_mamul_i_ptr_sel = spu_mamul_rd_ai ;
assign spu_mamul_iminus1_ptr_sel = spu_mamul_wr_mi | spu_maaeqb_iminus1_ptr_sel ;
assign spu_mamul_j_ptr_sel = (spu_mamul_rd_aj | spu_mamul_rd_mj) | spu_maaeqb_j_ptr_sel;
wire mamul_iminusj_ptr_sel =
//(spu_mamul_rd_biminusj | spu_mamul_rd_niminusj) & ~(spu_mamul_rd_aj | spu_mamul_rd_mj);
(spu_mamul_rd_biminusj | spu_mamul_rd_niminusj) ;
assign spu_mamul_iminusj_ptr_sel = mamul_iminusj_ptr_sel | spu_maaeqb_iminusj_ptr_sel;
assign spu_mamul_iminuslenminus1_sel = spu_mamul_wr_miminuslenminus1 | spu_maaeqb_iminuslenminus1_sel;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// request to mul unit when asserted
/*
wire iloop_or_req_d;
wire iloop_or_req = (cur_iloopb_state | cur_nprime_state | cur_iloopn_state)&
~mul_spu_ack;
dff_s #(1) iloop_dly_req_ff (
.din(iloop_or_req) ,
.q(iloop_or_req_d),
.clk (rclk), .se(se), .si(), .so());
assign spu_mul_req_vld = (cur_jloopb_state | cur_jloopn_state | iloop_or_req_d) ;
*/
wire mamul_mul_req_vld_pre = nxt_jloopb_state | nxt_jloopn_state | nxt_iloopb_state |
nxt_nprime_state | nxt_iloopn_state ;
dffr_s #(1) mamul_mul_req_vld_ff (
.din(mamul_mul_req_vld_pre) ,
.q(mamul_mul_req_vld),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
/*
wire mamul_mul_req_vld = cur_jloopb_state | cur_jloopn_state | cur_iloopb_state |
cur_nprime_state | cur_iloopn_state ;
*/
assign spu_mul_req_vld = mamul_mul_req_vld | spu_maaeqb_mul_req_vld;
// ---------------------------------------------------------------
assign spu_mul_areg_shf = cur_accumshft_state | spu_maaeqb_mul_areg_shf;
// ---------------------------------------------------------------
/*
wire oprnd2_sel = mamul_a_rd_oprnd_sel | mamul_ax_rd_oprnd_sel |
mamul_m_rd_oprnd_sel | mamul_me_rd_oprnd_sel) &
*/
wire oprnd2_sel = nxt_jloopa_state | nxt_iloopa_state | nxt_jloopm_state ;
wire oprnd2_sel_q;
dff_s #(1) oprnd2_wen_ff (
.din(oprnd2_sel) ,
.q(oprnd2_sel_q),
.clk (rclk), .se(se), .si(), .so());
assign spu_mamul_oprnd2_wen = oprnd2_sel_q | mamul_m_wr_oprnd2_wen | mamul_me_wr_oprnd2_wen |
spu_mared_oprnd2_wen |
spu_maaeqb_oprnd2_wen;
assign spu_mamul_oprnd2_bypass = mamul_m_wr_oprnd2_wen | mamul_me_wr_oprnd2_wen |
spu_maaeqb_oprnd2_bypass;
//assign spu_mamul_oprnd1_sel = cur_nprime_state | spu_maaeqb_oprnd1_sel; // only select nprime if set
// ---------------------------------------------------------------
assign spu_mul_acc = (mamul_mul_req_vld & ~cur_nprime_state) | spu_maaeqb_mul_acc;
// ---------------------------------------------------------------
// ---------------------------------------------------------------
// ---------------------------------------------------------------
wire select_mamul = ~cur_idle_state;
wire spu_mamul_memrd4op1 = spu_mamul_rd_biminusj | spu_mamul_rd_b0 | spu_mamul_rd_n0 |
spu_mamul_rd_niminusj;
wire spu_mamul_memrd4op1_q;
dff_s #(1) spu_mamul_memrd4op1_ff (
.din(spu_mamul_memrd4op1) ,
.q(spu_mamul_memrd4op1_q),
.clk (rclk), .se(se), .si(), .so());
wire [1:0] spu_mamul_oprnd1_mxsel;
assign spu_mamul_oprnd1_mxsel[0] = (select_mamul & (~cur_nprime_state & ~spu_mamul_memrd4op1_q)) |
(~select_mamul & spu_maaeqb_oprnd1_mxsel[0]) ;
assign spu_mamul_oprnd1_mxsel[1] = (select_mamul & (~cur_nprime_state & spu_mamul_memrd4op1_q)) |
(~select_mamul & spu_maaeqb_oprnd1_mxsel[1]);
//assign spu_mamul_oprnd1_mxsel[2] = (select_mamul & cur_nprime_state) | (~select_mamul & spu_maaeqb_oprnd1_mxsel[2]);
wire [2:0] spu_mamul_oprnd1_mxsel_ps;
assign spu_mamul_oprnd1_mxsel_ps[0] = spu_mamul_oprnd1_mxsel[0];
assign spu_mamul_oprnd1_mxsel_ps[1] = ~spu_mamul_oprnd1_mxsel[0] & spu_mamul_oprnd1_mxsel[1];
assign spu_mamul_oprnd1_mxsel_ps[2] = ~spu_mamul_oprnd1_mxsel[0] & ~spu_mamul_oprnd1_mxsel[1];
assign spu_mamul_oprnd1_mxsel_l = ~spu_mamul_oprnd1_mxsel_ps;
assign spu_mamul_oprnd1_wen = spu_mamul_memrd4op1_q | spu_maaeqb_oprnd1_wen;
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/cpu.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* 6502 core implementation.
***************************************************************************************************/
`timescale 1ps / 1ps
module cpu (
input wire clk_in, // 100MHz system clock
input wire rst_in, // reset signal
input wire ready_in, // ready signal
// Interrupt lines.
input wire nnmi_in, // /nmi interrupt signal (active low)
input wire nres_in, // /res interrupt signal (console reset, active low)
input wire nirq_in, // /irq intterupt signal (active low)
// Memory bus.
input wire [ 7:0] d_in, // data input bus
output wire [ 7:0] d_out, // data output bus
output wire [15:0] a_out, // address bus
output reg r_nw_out, // R/!W signal
// Debug support.
input wire [ 3:0] dbgreg_sel_in, // dbg reg select
input wire [ 7:0] dbgreg_in, // dbg reg write input
input wire dbgreg_wr_in, // dbg reg rd/wr select
output reg [ 7:0] dbgreg_out, // dbg reg read output
output reg brk_out // debug break signal
);
// dbgreg_sel defines. Selects register for read/write through the debugger block.
`define REGSEL_PCL 0
`define REGSEL_PCH 1
`define REGSEL_AC 2
`define REGSEL_X 3
`define REGSEL_Y 4
`define REGSEL_P 5
`define REGSEL_S 6
// Opcodes.
localparam [7:0] ADC_ABS = 8'h6D, ADC_ABSX = 8'h7D, ADC_ABSY = 8'h79, ADC_IMM = 8'h69,
ADC_INDX = 8'h61, ADC_INDY = 8'h71, ADC_ZP = 8'h65,
ADC_ZPX = 8'h75,
AND_ABS = 8'h2D, AND_ABSX = 8'h3D, AND_ABSY = 8'h39, AND_IMM = 8'h29,
AND_INDX = 8'h21, AND_INDY = 8'h31, AND_ZP = 8'h25,
AND_ZPX = 8'h35,
ASL_ABS = 8'h0E, ASL_ABSX = 8'h1E, ASL_ACC = 8'h0A, ASL_ZP = 8'h06,
ASL_ZPX = 8'h16,
BCC = 8'h90,
BCS = 8'hB0,
BEQ = 8'hF0,
BIT_ABS = 8'h2C, BIT_ZP = 8'h24,
BMI = 8'h30,
BNE = 8'hD0,
BPL = 8'h10,
BRK = 8'h00,
BVC = 8'h50,
BVS = 8'h70,
CLC = 8'h18,
CLD = 8'hD8,
CLI = 8'h58,
CLV = 8'hB8,
CMP_ABS = 8'hCD, CMP_ABSX = 8'hDD, CMP_ABSY = 8'hD9, CMP_IMM = 8'hC9,
CMP_INDX = 8'hC1, CMP_INDY = 8'hD1, CMP_ZP = 8'hC5,
CMP_ZPX = 8'hD5,
CPX_ABS = 8'hEC, CPX_IMM = 8'hE0, CPX_ZP = 8'hE4,
CPY_ABS = 8'hCC, CPY_IMM = 8'hC0, CPY_ZP = 8'hC4,
DEC_ABS = 8'hCE, DEC_ABSX = 8'hDE, DEC_ZP = 8'hC6, DEC_ZPX = 8'hD6,
DEX = 8'hCA,
DEY = 8'h88,
EOR_ABS = 8'h4D, EOR_ABSX = 8'h5D, EOR_ABSY = 8'h59, EOR_IMM = 8'h49,
EOR_INDX = 8'h41, EOR_INDY = 8'h51, EOR_ZP = 8'h45,
EOR_ZPX = 8'h55,
HLT = 8'h02,
INC_ABS = 8'hEE, INC_ABSX = 8'hFE, INC_ZP = 8'hE6, INC_ZPX = 8'hF6,
INX = 8'hE8,
INY = 8'hC8,
JMP_ABS = 8'h4C, JMP_IND = 8'h6C,
JSR = 8'h20,
LDA_ABS = 8'hAD, LDA_ABSX = 8'hBD, LDA_ABSY = 8'hB9, LDA_IMM = 8'hA9,
LDA_INDX = 8'hA1, LDA_INDY = 8'hB1, LDA_ZP = 8'hA5,
LDA_ZPX = 8'hB5,
LDX_ABS = 8'hAE, LDX_ABSY = 8'hBE, LDX_IMM = 8'hA2, LDX_ZP = 8'hA6,
LDX_ZPY = 8'hB6,
LDY_ABS = 8'hAC, LDY_ABSX = 8'hBC, LDY_IMM = 8'hA0, LDY_ZP = 8'hA4,
LDY_ZPX = 8'hB4,
LSR_ABS = 8'h4E, LSR_ABSX = 8'h5E, LSR_ACC = 8'h4A, LSR_ZP = 8'h46,
LSR_ZPX = 8'h56,
NOP = 8'hEA,
ORA_ABS = 8'h0D, ORA_ABSX = 8'h1D, ORA_ABSY = 8'h19, ORA_IMM = 8'h09,
ORA_INDX = 8'h01, ORA_INDY = 8'h11, ORA_ZP = 8'h05,
ORA_ZPX = 8'h15,
PHA = 8'h48,
PHP = 8'h08,
PLA = 8'h68,
PLP = 8'h28,
ROL_ABS = 8'h2E, ROL_ABSX = 8'h3E, ROL_ACC = 8'h2A, ROL_ZP = 8'h26,
ROL_ZPX = 8'h36,
ROR_ABS = 8'h6E, ROR_ABSX = 8'h7E, ROR_ACC = 8'h6A, ROR_ZP = 8'h66,
ROR_ZPX = 8'h76,
RTI = 8'h40,
RTS = 8'h60,
SAX_ABS = 8'h8F, SAX_INDX = 8'h83, SAX_ZP = 8'h87, SAX_ZPY = 8'h97,
SBC_ABS = 8'hED, SBC_ABSX = 8'hFD, SBC_ABSY = 8'hF9, SBC_IMM = 8'hE9,
SBC_INDX = 8'hE1, SBC_INDY = 8'hF1, SBC_ZP = 8'hE5,
SBC_ZPX = 8'hF5,
SEC = 8'h38,
SED = 8'hF8,
SEI = 8'h78,
STA_ABS = 8'h8D, STA_ABSX = 8'h9D, STA_ABSY = 8'h99, STA_INDX = 8'h81,
STA_INDY = 8'h91, STA_ZP = 8'h85, STA_ZPX = 8'h95,
STX_ABS = 8'h8E, STX_ZP = 8'h86, STX_ZPY = 8'h96,
STY_ABS = 8'h8C, STY_ZP = 8'h84, STY_ZPX = 8'h94,
TAX = 8'hAA,
TAY = 8'hA8,
TSX = 8'hBA,
TXA = 8'h8A,
TXS = 8'h9A,
TYA = 8'h98;
// Macro to check if a value is a valid opcode.
`define IS_VALID_OPCODE(op) \
(((op) == ADC_ABS ) || ((op) == ADC_ABSX) || ((op) == ADC_ABSY) || ((op) == ADC_IMM ) || \
((op) == ADC_INDX) || ((op) == ADC_INDY) || ((op) == ADC_ZP ) || ((op) == ADC_ZPX ) || \
((op) == AND_ABS ) || ((op) == AND_ABSX) || ((op) == AND_ABSY) || ((op) == AND_IMM ) || \
((op) == AND_INDX) || ((op) == AND_INDY) || ((op) == AND_ZP ) || ((op) == AND_ZPX ) || \
((op) == ASL_ABS ) || ((op) == ASL_ABSX) || ((op) == ASL_ACC ) || ((op) == ASL_ZP ) || \
((op) == ASL_ZPX ) || ((op) == BCC ) || ((op) == BCS ) || ((op) == BEQ ) || \
((op) == BIT_ABS ) || ((op) == BIT_ZP ) || ((op) == BMI ) || ((op) == BNE ) || \
((op) == BPL ) || ((op) == BRK ) || ((op) == BVC ) || ((op) == BVS ) || \
((op) == CLC ) || ((op) == CLD ) || ((op) == CLI ) || ((op) == CLV ) || \
((op) == CMP_ABS ) || ((op) == CMP_ABSX) || ((op) == CMP_ABSY) || ((op) == CMP_IMM ) || \
((op) == CMP_INDX) || ((op) == CMP_INDY) || ((op) == CMP_ZP ) || ((op) == CMP_ZPX ) || \
((op) == CPX_ABS ) || ((op) == CPX_IMM ) || ((op) == CPX_ZP ) || ((op) == CPY_ABS ) || \
((op) == CPY_IMM ) || ((op) == CPY_ZP ) || ((op) == DEC_ABS ) || ((op) == DEC_ABSX) || \
((op) == DEC_ZP ) || ((op) == DEC_ZPX ) || ((op) == DEX ) || ((op) == DEY ) || \
((op) == EOR_ABS ) || ((op) == EOR_ABSX) || ((op) == EOR_ABSY) || ((op) == EOR_IMM ) || \
((op) == EOR_INDX) || ((op) == EOR_INDY) || ((op) == EOR_ZP ) || ((op) == EOR_ZPX ) || \
((op) == HLT ) || ((op) == INC_ABS ) || ((op) == INC_ABSX) || ((op) == INC_ZP ) || \
((op) == INC_ZPX ) || ((op) == INX ) || ((op) == INY ) || ((op) == JMP_ABS ) || \
((op) == JMP_IND ) || ((op) == JSR ) || ((op) == LDA_ABS ) || ((op) == LDA_ABSX) || \
((op) == LDA_ABSY) || ((op) == LDA_IMM ) || ((op) == LDA_INDX) || ((op) == LDA_INDY) || \
((op) == LDA_ZP ) || ((op) == LDA_ZPX ) || ((op) == LDX_ABS ) || ((op) == LDX_ABSY) || \
((op) == LDX_IMM ) || ((op) == LDX_ZP ) || ((op) == LDX_ZPY ) || ((op) == LDY_ABS ) || \
((op) == LDY_ABSX) || ((op) == LDY_IMM ) || ((op) == LDY_ZP ) || ((op) == LDY_ZPX ) || \
((op) == LSR_ABS ) || ((op) == LSR_ABSX) || ((op) == LSR_ACC ) || ((op) == LSR_ZP ) || \
((op) == LSR_ZPX ) || ((op) == NOP ) || ((op) == ORA_ABS ) || ((op) == ORA_ABSX) || \
((op) == ORA_ABSY) || ((op) == ORA_IMM ) || ((op) == ORA_INDX) || ((op) == ORA_INDY) || \
((op) == ORA_ZP ) || ((op) == ORA_ZPX ) || ((op) == PHA ) || ((op) == PHP ) || \
((op) == PLA ) || ((op) == PLP ) || ((op) == ROL_ABS ) || ((op) == ROL_ABSX) || \
((op) == ROL_ACC ) || ((op) == ROL_ZP ) || ((op) == ROL_ZPX ) || ((op) == ROR_ABS ) || \
((op) == ROR_ABSX) || ((op) == ROR_ACC ) || ((op) == ROR_ZP ) || ((op) == ROR_ZPX ) || \
((op) == RTI ) || ((op) == RTS ) || ((op) == SAX_ABS ) || ((op) == SAX_INDX) || \
((op) == SAX_ZP ) || ((op) == SAX_ZPY ) || ((op) == SBC_ABS ) || ((op) == SBC_ABSX) || \
((op) == SBC_ABSY) || ((op) == SBC_IMM ) || ((op) == SBC_INDX) || ((op) == SBC_INDY) || \
((op) == SBC_ZP ) || ((op) == SBC_ZPX ) || ((op) == SEC ) || ((op) == SED ) || \
((op) == SEI ) || ((op) == STA_ABS ) || ((op) == STA_ABSX) || ((op) == STA_ABSY) || \
((op) == STA_INDX) || ((op) == STA_INDY) || ((op) == STA_ZP ) || ((op) == STA_ZPX ) || \
((op) == STX_ABS ) || ((op) == STX_ZP ) || ((op) == STX_ZPY ) || ((op) == STY_ABS ) || \
((op) == STY_ZP ) || ((op) == STY_ZPX ) || ((op) == TAX ) || ((op) == TAY ) || \
((op) == TSX ) || ((op) == TXA ) || ((op) == TXS ) || ((op) == TYA ))
// Timing generation cycle states.
localparam [2:0] T0 = 3'h0,
T1 = 3'h1,
T2 = 3'h2,
T3 = 3'h3,
T4 = 3'h4,
T5 = 3'h5,
T6 = 3'h6;
// Interrupt types.
localparam [1:0] INTERRUPT_RST = 2'h0,
INTERRUPT_NMI = 2'h1,
INTERRUPT_IRQ = 2'h2,
INTERRUPT_BRK = 2'h3;
// User registers.
reg [7:0] q_ac; // accumulator register
wire [7:0] d_ac;
reg [7:0] q_x; // x index register
wire [7:0] d_x;
reg [7:0] q_y; // y index register
wire [7:0] d_y;
// Processor status register.
wire [7:0] p; // full processor status reg, grouped from the following FFs
reg q_c; // carry flag
wire d_c;
reg q_d; // decimal mode flag
wire d_d;
reg q_i; // interrupt disable flag
wire d_i;
reg q_n; // negative flag
wire d_n;
reg q_v; // overflow flag
wire d_v;
reg q_z; // zero flag
wire d_z;
// Internal registers.
reg [7:0] q_abh; // address bus high register
wire [7:0] d_abh;
reg [7:0] q_abl; // address bus low register
wire [7:0] d_abl;
reg q_acr; // internal carry latch
reg [7:0] q_add; // adder hold register
reg [7:0] d_add;
reg [7:0] q_ai; // alu input register a
wire [7:0] d_ai;
reg [7:0] q_bi; // alu input register b
wire [7:0] d_bi;
reg [7:0] q_dl; // input data latch
wire [7:0] d_dl;
reg [7:0] q_dor; // data output register
wire [7:0] d_dor;
reg [7:0] q_ir; // instruction register
reg [7:0] d_ir;
reg [7:0] q_pch; // program counter high register
wire [7:0] d_pch;
reg [7:0] q_pcl; // program counter low register
wire [7:0] d_pcl;
reg [7:0] q_pchs; // program counter high select register
wire [7:0] d_pchs;
reg [7:0] q_pcls; // program counter low select register
wire [7:0] d_pcls;
reg [7:0] q_pd; // pre-decode register
wire [7:0] d_pd;
reg [7:0] q_s; // stack pointer register
wire [7:0] d_s;
reg [2:0] q_t; // timing cycle register
reg [2:0] d_t;
// Internal buses.
wire [7:0] adl; // ADL bus
wire [7:0] adh_in, // ADH bus
adh_out;
wire [7:0] db_in, // DB bus
db_out;
wire [7:0] sb_in, // SB bus
sb_out;
//
// Internal control signals. These names are all taken directly from the original 6502 block
// diagram.
//
wire zero_adl0;
wire zero_adl1;
wire zero_adl2;
// ADL bus drive enables.
wire add_adl; // output adder hold register to adl bus
wire dl_adl; // output dl reg to adl bus
wire pcl_adl; // output pcl reg to adl bus
wire s_adl; // output s reg to adl bus
// ADH bus drive enables.
wire dl_adh; // output dl reg to adh bus
wire pch_adh; // output pch reg to adh bus
wire zero_adh0; // output 0 to bit 0 of adh bus
wire zero_adh17; // output 0 to bits 1-7 of adh bus
// DB bus drive enables.
wire ac_db; // output ac reg to db bus
wire dl_db; // output dl reg to db bus
wire p_db; // output p reg to db bus
wire pch_db; // output pch reg to db bus
wire pcl_db; // output pcl reg to db bus
// SB bus drive enables.
wire ac_sb; // output ac reg to sb bus
wire add_sb; // output add reg to sb bus
wire x_sb; // output x reg to sb bus
wire y_sb; // output y reg to sb bus
wire s_sb; // output s reg to sb bus
// Pass MOSFET controls.
wire sb_adh; // controls sb/adh pass mosfet
wire sb_db; // controls sb/db pass mosfet
// Register LOAD controls.
wire adh_abh; // latch adh bus value in abh reg
wire adl_abl; // latch adl bus value in abl reg
wire sb_ac; // latch sb bus value in ac reg
wire adl_add; // latch adl bus value in bi reg
wire db_add; // latch db bus value in bi reg
wire invdb_add; // latch ~db value in bi reg
wire sb_add; // latch sb bus value in ai reg
wire zero_add; // latch 0 into ai reg
wire adh_pch; // latch adh bus value in pch reg
wire adl_pcl; // latch adl bus value in pcl reg
wire sb_s; // latch sb bus value in s reg
wire sb_x; // latch sb bus value in x reg
wire sb_y; // latch sb bus value in y reg
// Processor status controls.
wire acr_c; // latch acr into c status reg
wire db0_c; // latch db[0] into c status reg
wire ir5_c; // latch ir[5] into c status reg
wire db3_d; // latch db[3] into d status reg
wire ir5_d; // latch ir[5] into d status reg
wire db2_i; // latch db[2] into i status reg
wire ir5_i; // latch ir[5] into i status reg
wire db7_n; // latch db[7] into n status reg
wire avr_v; // latch avr into v status reg
wire db6_v; // latch db[6] into v status reg
wire zero_v; // latch 0 into v status reg
wire db1_z; // latch db[1] into z status reg
wire dbz_z; // latch ~|db into z status reg
// Misc. controls.
wire i_pc; // increment pc
// ALU controls, signals.
wire ands; // perform bitwise and on alu
wire eors; // perform bitwise xor on alu
wire ors; // perform bitwise or on alu
wire sums; // perform addition on alu
wire srs; // perform right bitshift
wire addc; // carry in
reg acr; // carry out
reg avr; // overflow out
//
// Ready Control.
//
wire rdy; // internal, modified ready signal.
reg q_ready; // latch external ready signal to delay 1 clk so top-level addr muxing can complete
always @(posedge clk_in)
begin
if (rst_in)
q_ready <= 1'b0;
else
q_ready <= ready_in;
end
assign rdy = ready_in && q_ready;
//
// Clock phase generation logic.
//
reg [5:0] q_clk_phase;
wire [5:0] d_clk_phase;
always @(posedge clk_in)
begin
if (rst_in)
q_clk_phase <= 6'h01;
else if (rdy)
q_clk_phase <= d_clk_phase;
// If the debugger writes a PC register, this is a partial reset: the cycle is set to
// T0, and the clock phase should be set to the beginning of the 4 clock cycle.
else if (dbgreg_wr_in && ((dbgreg_sel_in == `REGSEL_PCH) || (dbgreg_sel_in == `REGSEL_PCL)))
q_clk_phase <= 6'h01;
end
assign d_clk_phase = (q_clk_phase == 6'h37) ? 6'h00 : q_clk_phase + 6'h01;
//
// Interrupt and Reset Control.
//
reg [1:0] q_irq_sel, d_irq_sel; // interrupt selected for service
reg q_rst; // rst interrupt needs to be serviced
wire d_rst;
reg q_nres; // latch last nres input signal for falling edge detection
reg q_nmi; // nmi interrupt needs to be serviced
wire d_nmi;
reg q_nnmi; // latch last nnmi input signal for falling edge detection
reg clear_rst; // clear rst interrupt
reg clear_nmi; // clear nmi interrupt
reg force_noinc_pc; // override stage-0 PC increment
always @(posedge clk_in)
begin
if (rst_in)
begin
q_irq_sel <= INTERRUPT_RST;
q_rst <= 1'b0;
q_nres <= 1'b1;
q_nmi <= 1'b0;
q_nnmi <= 1'b1;
end
else if (q_clk_phase == 6'h00)
begin
q_irq_sel <= d_irq_sel;
q_rst <= d_rst;
q_nres <= nres_in;
q_nmi <= d_nmi;
q_nnmi <= nnmi_in;
end
end
assign d_rst = (clear_rst) ? 1'b0 :
(!nres_in && q_nres) ? 1'b1 :
q_rst;
assign d_nmi = (clear_nmi) ? 1'b0 :
(!nnmi_in && q_nnmi) ? 1'b1 :
q_nmi;
//
// Update phase-1 clocked registers.
//
always @(posedge clk_in)
begin
if (rst_in)
begin
q_ac <= 8'h00;
q_x <= 8'h00;
q_y <= 8'h00;
q_c <= 1'b0;
q_d <= 1'b0;
q_i <= 1'b0;
q_n <= 1'b0;
q_v <= 1'b0;
q_z <= 1'b0;
q_abh <= 8'h80;
q_abl <= 8'h00;
q_acr <= 1'b0;
q_ai <= 8'h00;
q_bi <= 8'h00;
q_dor <= 8'h00;
q_ir <= NOP;
q_pchs <= 8'h80;
q_pcls <= 8'h00;
q_s <= 8'hFF;
q_t <= T1;
end
else if (rdy && (q_clk_phase == 6'h00))
begin
q_ac <= d_ac;
q_x <= d_x;
q_y <= d_y;
q_c <= d_c;
q_d <= d_d;
q_i <= d_i;
q_n <= d_n;
q_v <= d_v;
q_z <= d_z;
q_abh <= d_abh;
q_abl <= d_abl;
q_acr <= acr;
q_ai <= d_ai;
q_bi <= d_bi;
q_dor <= d_dor;
q_ir <= d_ir;
q_pchs <= d_pchs;
q_pcls <= d_pcls;
q_s <= d_s;
q_t <= d_t;
end
else if (!rdy)
begin
// Update registers based on debug register write packets.
if (dbgreg_wr_in)
begin
q_ac <= (dbgreg_sel_in == `REGSEL_AC) ? dbgreg_in : q_ac;
q_x <= (dbgreg_sel_in == `REGSEL_X) ? dbgreg_in : q_x;
q_y <= (dbgreg_sel_in == `REGSEL_Y) ? dbgreg_in : q_y;
q_c <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[0] : q_c;
q_d <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[3] : q_d;
q_i <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[2] : q_i;
q_n <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[7] : q_n;
q_v <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[6] : q_v;
q_z <= (dbgreg_sel_in == `REGSEL_P) ? dbgreg_in[1] : q_z;
// Treat the debugger writing PC registers as a partial reset. Set the cycle to T0,
// and setup the address bus so the first opcode fill be fetched as soon as rdy is
// asserted again.
q_pchs <= (dbgreg_sel_in == `REGSEL_PCH) ? dbgreg_in : q_pchs;
q_pcls <= (dbgreg_sel_in == `REGSEL_PCL) ? dbgreg_in : q_pcls;
q_abh <= (dbgreg_sel_in == `REGSEL_PCH) ? dbgreg_in : q_abh;
q_abl <= (dbgreg_sel_in == `REGSEL_PCL) ? dbgreg_in : q_abl;
q_t <= ((dbgreg_sel_in == `REGSEL_PCH) || (dbgreg_sel_in == `REGSEL_PCL)) ? T0 : q_t;
end
end
end
//
// Update phase-2 clocked registers.
//
always @(posedge clk_in)
begin
if (rst_in)
begin
q_pcl <= 8'h00;
q_pch <= 8'h80;
q_dl <= 8'h00;
q_pd <= 8'h00;
q_add <= 8'h00;
end
else if (rdy && (q_clk_phase == 6'h1C))
begin
q_pcl <= d_pcl;
q_pch <= d_pch;
q_dl <= d_dl;
q_pd <= d_pd;
q_add <= d_add;
end
else if (!rdy && dbgreg_wr_in)
begin
// Update registers based on debug register write packets.
q_pcl <= (dbgreg_sel_in == `REGSEL_PCL) ? dbgreg_in : q_pcl;
q_pch <= (dbgreg_sel_in == `REGSEL_PCH) ? dbgreg_in : q_pch;
end
end
//
// Timing Generation Logic
//
always @*
begin
d_t = T0;
d_irq_sel = q_irq_sel;
force_noinc_pc = 1'b0;
case (q_t)
T0:
d_t = T1;
T1:
begin
// These instructions are in their last cycle but do not prefetch.
if ((q_ir == CLC) || (q_ir == CLD) || (q_ir == CLI) || (q_ir == CLV) ||
(q_ir == HLT) || (q_ir == LDA_IMM) || (q_ir == LDX_IMM) || (q_ir == LDY_IMM) ||
(q_ir == NOP) || (q_ir == SEC) || (q_ir == SED) || (q_ir == SEI) ||
(q_ir == TAX) || (q_ir == TAY) || (q_ir == TSX) || (q_ir == TXA) ||
(q_ir == TXS) || (q_ir == TYA))
begin
d_t = T0;
end
// Check for not-taken branches. These instructions must setup the not-taken PC during
// T1, and we can move to T0 of the next instruction.
else if (((q_ir == BCC) && q_c) || ((q_ir == BCS) && !q_c) ||
((q_ir == BPL) && q_n) || ((q_ir == BMI) && !q_n) ||
((q_ir == BVC) && q_v) || ((q_ir == BVS) && !q_v) ||
((q_ir == BNE) && q_z) || ((q_ir == BEQ) && !q_z))
begin
d_t = T0;
end
else
begin
d_t = T2;
end
end
T2:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_IMM) || (q_ir == AND_IMM) || (q_ir == ASL_ACC) || (q_ir == CMP_IMM) ||
(q_ir == CPX_IMM) || (q_ir == CPY_IMM) || (q_ir == DEX) || (q_ir == DEY) ||
(q_ir == EOR_IMM) || (q_ir == INX) || (q_ir == INY) || (q_ir == LSR_ACC) ||
(q_ir == ORA_IMM) || (q_ir == ROL_ACC) || (q_ir == ROR_ACC) || (q_ir == SBC_IMM))
begin
d_t = T1;
end
// These instructions are in their last cycle but do not prefetch.
else if ((q_ir == JMP_ABS) || (q_ir == LDA_ZP) || (q_ir == LDX_ZP) || (q_ir == LDY_ZP) ||
(q_ir == SAX_ZP) || (q_ir == STA_ZP) || (q_ir == STX_ZP) || (q_ir == STY_ZP))
begin
d_t = T0;
end
// For ops using relative absolute addressing modes, we can skip stage 3 if the result
// doesn't cross a page boundary (i.e., don't need to add 1 to the high byte).
else if (!acr && ((q_ir == ADC_ABSX) || (q_ir == ADC_ABSY) || (q_ir == AND_ABSX) ||
(q_ir == AND_ABSY) || (q_ir == CMP_ABSX) || (q_ir == CMP_ABSY) ||
(q_ir == EOR_ABSX) || (q_ir == EOR_ABSY) || (q_ir == LDA_ABSX) ||
(q_ir == LDA_ABSY) || (q_ir == ORA_ABSX) || (q_ir == ORA_ABSY) ||
(q_ir == SBC_ABSX) || (q_ir == SBC_ABSY)))
begin
d_t = T4;
end
// For relative addressing ops (branches), we can skip stage 3 if the new PC doesn't
// cross a page boundary (forward or backward).
else if ((acr == q_ai[7]) && ((q_ir == BCC) || (q_ir == BCS) || (q_ir == BEQ) ||
(q_ir == BMI) || (q_ir == BNE) || (q_ir == BPL) ||
(q_ir == BVC) || (q_ir == BVS)))
begin
d_t = T0;
end
else
begin
d_t = T3;
end
end
T3:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_ZP) || (q_ir == AND_ZP) || (q_ir == BIT_ZP) || (q_ir == CMP_ZP) ||
(q_ir == CPX_ZP) || (q_ir == CPY_ZP) || (q_ir == EOR_ZP) || (q_ir == ORA_ZP) ||
(q_ir == PHA) || (q_ir == PHP) || (q_ir == SBC_ZP))
begin
d_t = T1;
end
// These instructions are in their last cycle but do not prefetch.
else if ((q_ir == BCC) || (q_ir == BCS) || (q_ir == BEQ) ||
(q_ir == BMI) || (q_ir == BNE) || (q_ir == BPL) ||
(q_ir == BVC) || (q_ir == BVS) || (q_ir == LDA_ABS) ||
(q_ir == LDA_ZPX) || (q_ir == LDX_ABS) || (q_ir == LDX_ZPY) ||
(q_ir == LDY_ABS) || (q_ir == LDY_ZPX) || (q_ir == PLA) ||
(q_ir == PLP) || (q_ir == SAX_ABS) || (q_ir == SAX_ZPY) ||
(q_ir == STA_ABS) || (q_ir == STA_ZPX) || (q_ir == STX_ABS) ||
(q_ir == STX_ZPY) || (q_ir == STY_ABS) || (q_ir == STY_ZPX))
begin
d_t = T0;
end
// For loads using (indirect),Y addressing modes, we can skip stage 4 if the result
// doesn't cross a page boundary (i.e., don't need to add 1 to the high byte).
else if (!acr && ((q_ir == ADC_INDY) || (q_ir == AND_INDY) || (q_ir == CMP_INDY) ||
(q_ir == EOR_INDY) || (q_ir == LDA_INDY) ||
(q_ir == ORA_INDY) || (q_ir == SBC_INDY)))
begin
d_t = T5;
end
else
begin
d_t = T4;
end
end
T4:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_ABS) || (q_ir == ADC_ZPX) || (q_ir == AND_ABS) || (q_ir == AND_ZPX) ||
(q_ir == BIT_ABS) || (q_ir == CMP_ABS) || (q_ir == CMP_ZPX) || (q_ir == CPX_ABS) ||
(q_ir == CPY_ABS) || (q_ir == EOR_ABS) || (q_ir == EOR_ZPX) || (q_ir == ORA_ABS) ||
(q_ir == ORA_ZPX) || (q_ir == SBC_ABS) || (q_ir == SBC_ZPX))
begin
d_t = T1;
end
// These instructions are in their last cycle but do not prefetch.
else if ((q_ir == ASL_ZP) || (q_ir == DEC_ZP) || (q_ir == INC_ZP) ||
(q_ir == JMP_IND) || (q_ir == LDA_ABSX) || (q_ir == LDA_ABSY) ||
(q_ir == LDX_ABSY) || (q_ir == LDY_ABSX) || (q_ir == LSR_ZP) ||
(q_ir == ROL_ZP) || (q_ir == ROR_ZP) || (q_ir == STA_ABSX) ||
(q_ir == STA_ABSY))
begin
d_t = T0;
end
else
begin
d_t = T5;
end
end
T5:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_ABSX) || (q_ir == ADC_ABSY) || (q_ir == AND_ABSX) ||
(q_ir == AND_ABSY) || (q_ir == CMP_ABSX) || (q_ir == CMP_ABSY) ||
(q_ir == EOR_ABSX) || (q_ir == EOR_ABSY) || (q_ir == ORA_ABSX) ||
(q_ir == ORA_ABSY) || (q_ir == SBC_ABSX) || (q_ir == SBC_ABSY))
begin
d_t = T1;
end
// These instructions are in their last cycle but do not prefetch.
else if ((q_ir == ASL_ABS) || (q_ir == ASL_ZPX) || (q_ir == DEC_ABS) ||
(q_ir == DEC_ZPX) || (q_ir == INC_ABS) || (q_ir == INC_ZPX) ||
(q_ir == JSR) || (q_ir == LDA_INDX) || (q_ir == LDA_INDY) ||
(q_ir == LSR_ABS) || (q_ir == LSR_ZPX) || (q_ir == ROL_ABS) ||
(q_ir == ROL_ZPX) || (q_ir == ROR_ABS) || (q_ir == ROR_ZPX) ||
(q_ir == RTI) || (q_ir == RTS) || (q_ir == SAX_INDX) ||
(q_ir == STA_INDX) || (q_ir == STA_INDY))
begin
d_t = T0;
end
else
begin
d_t = T6;
end
end
T6:
begin
// These instructions prefetch the next opcode during their final cycle.
if ((q_ir == ADC_INDX) || (q_ir == ADC_INDY) || (q_ir == AND_INDX) ||
(q_ir == AND_INDY) || (q_ir == CMP_INDX) || (q_ir == CMP_INDY) ||
(q_ir == EOR_INDX) || (q_ir == EOR_INDY) || (q_ir == ORA_INDX) ||
(q_ir == ORA_INDY) || (q_ir == SBC_INDX) || (q_ir == SBC_INDY))
begin
d_t = T1;
end
else
begin
d_t = T0;
end
end
endcase
// Update IR register on cycle 1, otherwise retain current IR.
if (d_t == T1)
begin
if (q_rst || q_nmi || !nirq_in)
begin
d_ir = BRK;
force_noinc_pc = 1'b1;
if (q_rst)
d_irq_sel = INTERRUPT_RST;
else if (q_nmi)
d_irq_sel = INTERRUPT_NMI;
else
d_irq_sel = INTERRUPT_IRQ;
end
else
begin
d_ir = q_pd;
d_irq_sel = INTERRUPT_BRK;
end
end
else
begin
d_ir = q_ir;
end
end
//
// Decode ROM output signals. Corresponds to 130 bit bus coming out of the Decode ROM in the
// block diagram, although the details of implementation will differ.
//
// PC and program stream controls.
reg load_prg_byte; // put PC on addr bus and increment PC (adh, adl)
reg load_prg_byte_noinc; // put PC on addr bus only (adh, adl)
reg incpc_noload; // increment PC only (-)
reg alusum_to_pch; // load pch with ai+bi (adh, sb)
reg dl_to_pch; // load pch with current data latch register (adh)
reg alusum_to_pcl; // load pcl with ai+bi (adl)
reg s_to_pcl; // load pcl with s (adl)
// Instruction-specific controls. Typically triggers the meat of a particular operation that
// occurs regardless of addressing mode.
reg adc_op; // final cycle of an adc inst (db, sb)
reg and_op; // final cycle of an and inst (db, sb)
reg asl_acc_op; // perform asl_acc inst (db, sb)
reg asl_mem_op; // perform meat of asl inst for memory addressing modes (db, sb)
reg bit_op; // final cycle of a bit inst (db, sb)
reg cmp_op; // final cycle of a cmp inst (db, sb)
reg clc_op; // clear carry bit (-)
reg cld_op; // clear decimal mode bit (-)
reg cli_op; // clear interrupt disable bit (-)
reg clv_op; // clear overflow bit (-)
reg dec_op; // perform meat of dec inst (db, sb)
reg dex_op; // final cycle of a dex inst (db, sb)
reg dey_op; // final cycle of a dey inst (db, sb)
reg eor_op; // final cycle of an eor inst (db, sb)
reg inc_op; // perform meat of inc inst (db, sb)
reg inx_op; // final cycle of an inx inst (db, sb)
reg iny_op; // final cycle of an iny inst (db, sb)
reg lda_op; // final cycle of an lda inst (db, sb)
reg ldx_op; // final cycle of an ldx inst (db, sb)
reg ldy_op; // final cycle of an ldy inst (db, sb)
reg lsr_acc_op; // perform lsr_acc inst (db, sb)
reg lsr_mem_op; // perform meat of lsr inst for memory addressing modes (db, sb)
reg ora_op; // final cycle of an ora inst (db, sb)
reg rol_acc_op; // perform rol_acc inst (db, sb)
reg rol_mem_op; // perform meat of rol inst for memory addressing modes (db, sb)
reg ror_acc_op; // perform ror_acc inst (db, sb)
reg ror_mem_op; // perform meat of ror inst for memory addressing modes (db, sb)
reg sec_op; // set carry bit (-)
reg sed_op; // set decimal mode bit (-)
reg sei_op; // set interrupt disable bit (-)
reg tax_op; // transfer ac to x (db, sb)
reg tay_op; // transfer ac to y (db, sb)
reg tsx_op; // transfer s to x (db, sb)
reg txa_op; // transfer x to z (db, sb)
reg txs_op; // transfer x to s (db, sb)
reg tya_op; // transfer y to a (db, sb)
// DOR (data output register) load controls.
reg ac_to_dor; // load current ac value into dor (db)
reg p_to_dor; // load current p value into dor (db)
reg pch_to_dor; // load current pch value into dor (db)
reg pcl_to_dor; // load current pcl value into dor (db)
reg x_to_dor; // load current x value into dor (db, sb)
reg y_to_dor; // load current y value into dor (db, sb)
// AB (address bus hold registers) load controls.
reg aluinc_to_abh; // load abh with ai+bi+1 (adh, sb)
reg alusum_to_abh; // load abh with ai+bi (adh, sb)
reg dl_to_abh; // load abh with dl (adh)
reg ff_to_abh; // load abh with 8'hff (adh)
reg one_to_abh; // load abh with 8'h01 (adh)
reg zero_to_abh; // load abh with 8'h00 (adh)
reg aluinc_to_abl; // load abl with ai+bi+1 (adl)
reg alusum_to_abl; // load abl with ai+bi (adl)
reg dl_to_abl; // load abl with dl (adl)
reg fa_to_abl; // load abl with 8'hfa (adl)
reg fb_to_abl; // load abl with 8'hfb (adl)
reg fc_to_abl; // load abl with 8'hfc (adl)
reg fd_to_abl; // load abl with 8'hfd (adl)
reg fe_to_abl; // load abl with 8'hfe (adl)
reg ff_to_abl; // load abl with 8'hff (adl)
reg s_to_abl; // load abl with s (adl)
// AI/BI (ALU input registers) load controls.
reg ac_to_ai; // load ai with ac (sb)
reg dl_to_ai; // load ai with dl (db, sb)
reg one_to_ai; // load ai with 1 (adh, sb)
reg neg1_to_ai; // load ai with -1 (sb)
reg s_to_ai; // load ai with s (sb)
reg x_to_ai; // load ai with x (sb)
reg y_to_ai; // load ai with y (sb)
reg zero_to_ai; // load ai with 0 (sb)
reg ac_to_bi; // load bi with ac (db)
reg aluinc_to_bi; // load bi with ai+bi+1 (adl)
reg alusum_to_bi; // load bi with ai+bi (adl)
reg dl_to_bi; // load bi with dl (db)
reg invdl_to_bi; // load bi with ~dl (db)
reg neg1_to_bi; // load bi with -1 (db)
reg pch_to_bi; // load bi with pch (db)
reg pcl_to_bi; // load bi with pcl (adl)
reg s_to_bi; // load bi with s (adl)
reg x_to_bi; // load bi with x (db, sb)
reg y_to_bi; // load bi with y (db, sb)
// Stack related controls.
reg aluinc_to_s; // load ai+bi+1 into s (sb)
reg alusum_to_s; // load ai+bi into s (sb)
reg dl_to_s; // load s with current data latch register (db, sb)
// Process status register controls.
reg dl_bits67_to_p; // latch bits 6 and 7 into P V and N bits (db)
reg dl_to_p; // load dl into p (db)
reg one_to_i; // used to supress irqs while processing an interrupt
// Sets all decode ROM output signals to the specified value (0 for init, X for con't care states.
`define SET_ALL_CONTROL_SIGNALS(val) \
load_prg_byte = (val); \
load_prg_byte_noinc = (val); \
incpc_noload = (val); \
alusum_to_pch = (val); \
dl_to_pch = (val); \
alusum_to_pcl = (val); \
s_to_pcl = (val); \
\
adc_op = (val); \
and_op = (val); \
asl_acc_op = (val); \
asl_mem_op = (val); \
bit_op = (val); \
cmp_op = (val); \
clc_op = (val); \
cld_op = (val); \
cli_op = (val); \
clv_op = (val); \
dec_op = (val); \
dex_op = (val); \
dey_op = (val); \
eor_op = (val); \
inc_op = (val); \
inx_op = (val); \
iny_op = (val); \
lda_op = (val); \
ldx_op = (val); \
ldy_op = (val); \
lsr_acc_op = (val); \
lsr_mem_op = (val); \
ora_op = (val); \
rol_acc_op = (val); \
rol_mem_op = (val); \
ror_acc_op = (val); \
ror_mem_op = (val); \
sec_op = (val); \
sed_op = (val); \
sei_op = (val); \
tax_op = (val); \
tay_op = (val); \
tsx_op = (val); \
txa_op = (val); \
txs_op = (val); \
tya_op = (val); \
\
ac_to_dor = (val); \
p_to_dor = (val); \
pch_to_dor = (val); \
pcl_to_dor = (val); \
x_to_dor = (val); \
y_to_dor = (val); \
\
aluinc_to_abh = (val); \
alusum_to_abh = (val); \
dl_to_abh = (val); \
ff_to_abh = (val); \
one_to_abh = (val); \
zero_to_abh = (val); \
aluinc_to_abl = (val); \
alusum_to_abl = (val); \
dl_to_abl = (val); \
fa_to_abl = (val); \
fb_to_abl = (val); \
fc_to_abl = (val); \
fd_to_abl = (val); \
fe_to_abl = (val); \
ff_to_abl = (val); \
s_to_abl = (val); \
\
ac_to_ai = (val); \
dl_to_ai = (val); \
one_to_ai = (val); \
neg1_to_ai = (val); \
s_to_ai = (val); \
x_to_ai = (val); \
y_to_ai = (val); \
zero_to_ai = (val); \
ac_to_bi = (val); \
aluinc_to_bi = (val); \
alusum_to_bi = (val); \
dl_to_bi = (val); \
invdl_to_bi = (val); \
neg1_to_bi = (val); \
pch_to_bi = (val); \
pcl_to_bi = (val); \
s_to_bi = (val); \
x_to_bi = (val); \
y_to_bi = (val); \
\
aluinc_to_s = (val); \
alusum_to_s = (val); \
dl_to_s = (val); \
\
dl_to_p = (val); \
dl_bits67_to_p = (val); \
one_to_i = (val);
//
// Decode ROM logic.
//
always @*
begin
// Default all control signals to 0.
`SET_ALL_CONTROL_SIGNALS(1'b0)
// Defaults for output signals.
r_nw_out = 1'b1;
brk_out = 1'b0;
clear_rst = 1'b0;
clear_nmi = 1'b0;
if (q_t == T0)
begin
load_prg_byte = 1'b1;
end
else if (q_t == T1)
begin
case (q_ir)
ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS,
INC_ABS, JMP_ABS, JMP_IND, LDA_ABS, LDX_ABS, LDY_ABS, LSR_ABS,
ORA_ABS, ROL_ABS, ROR_ABS, SAX_ABS, SBC_ABS,
STA_ABS, STX_ABS, STY_ABS:
begin
load_prg_byte = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ABSX, AND_ABSX, ASL_ABSX, CMP_ABSX, DEC_ABSX, EOR_ABSX, INC_ABSX,
LDA_ABSX, LDY_ABSX, LSR_ABSX, ORA_ABSX, ROL_ABSX,
ROR_ABSX, SBC_ABSX, STA_ABSX:
begin
load_prg_byte = 1'b1;
x_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ABSY, AND_ABSY, CMP_ABSY, EOR_ABSY, LDA_ABSY, LDX_ABSY,
ORA_ABSY, SBC_ABSY, STA_ABSY:
begin
load_prg_byte = 1'b1;
y_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_IMM, AND_IMM, EOR_IMM, ORA_IMM:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_INDX, AND_INDX, CMP_INDX, EOR_INDX, LDA_INDX, ORA_INDX,
SAX_INDX, SBC_INDX, STA_INDX,
ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX,
EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX,
LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX, SBC_ZPX,
STA_ZPX, STY_ZPX:
begin
x_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_INDY, AND_INDY, CMP_INDY, EOR_INDY, LDA_INDY, ORA_INDY,
SBC_INDY, STA_INDY:
begin
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ZP, AND_ZP, ASL_ZP, BIT_ZP, CMP_ZP, CPX_ZP, CPY_ZP, DEC_ZP,
EOR_ZP, INC_ZP, LDA_ZP, LDX_ZP, LDY_ZP, LSR_ZP, ORA_ZP,
ROL_ZP, ROR_ZP, SBC_ZP:
begin
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC:
begin
ac_to_ai = 1'b1;
ac_to_bi = 1'b1;
end
BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS:
begin
load_prg_byte = 1'b1;
dl_to_ai = 1'b1;
pcl_to_bi = 1'b1;
end
BRK:
begin
if (q_irq_sel == INTERRUPT_BRK)
incpc_noload = 1'b1;
pch_to_dor = 1'b1;
one_to_abh = 1'b1;
s_to_abl = 1'b1;
neg1_to_ai = 1'b1;
s_to_bi = 1'b1;
end
CLC:
clc_op = 1'b1;
CLD:
cld_op = 1'b1;
CLI:
cli_op = 1'b1;
CLV:
clv_op = 1'b1;
CMP_IMM, SBC_IMM:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPX_IMM:
begin
load_prg_byte = 1'b1;
x_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPY_IMM:
begin
load_prg_byte = 1'b1;
y_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEX:
begin
x_to_ai = 1'b1;
neg1_to_bi = 1'b1;
end
DEY:
begin
y_to_ai = 1'b1;
neg1_to_bi = 1'b1;
end
HLT:
begin
// The HLT instruction asks hci to deassert the rdy signal, effectively pausing the
// cpu and allowing the debug block to inspect the internal state.
brk_out = (q_clk_phase == 6'h01) && rdy;
end
INX:
begin
zero_to_ai = 1'b1;
x_to_bi = 1'b1;
end
INY:
begin
zero_to_ai = 1'b1;
y_to_bi = 1'b1;
end
JSR:
begin
incpc_noload = 1'b1;
one_to_abh = 1'b1;
s_to_abl = 1'b1;
s_to_bi = 1'b1;
dl_to_s = 1'b1;
end
LDX_ZPY, SAX_ZPY, STX_ZPY:
begin
y_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
LDA_IMM:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LDX_IMM:
begin
load_prg_byte = 1'b1;
ldx_op = 1'b1;
end
LDY_IMM:
begin
load_prg_byte = 1'b1;
ldy_op = 1'b1;
end
PHA:
begin
ac_to_dor = 1'b1;
one_to_abh = 1'b1;
s_to_abl = 1'b1;
end
PHP:
begin
p_to_dor = 1'b1;
one_to_abh = 1'b1;
s_to_abl = 1'b1;
end
PLA, PLP, RTI, RTS:
begin
zero_to_ai = 1'b1;
s_to_bi = 1'b1;
end
SEC:
sec_op = 1'b1;
SED:
sed_op = 1'b1;
SEI:
sei_op = 1'b1;
SAX_ZP:
begin
ac_to_dor = 1'b1;
x_to_dor = 1'b1;
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
STA_ZP:
begin
ac_to_dor = 1'b1;
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
STX_ZP:
begin
x_to_dor = 1'b1;
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
STY_ZP:
begin
y_to_dor = 1'b1;
zero_to_abh = 1'b1;
dl_to_abl = 1'b1;
end
TAX:
tax_op = 1'b1;
TAY:
tay_op = 1'b1;
TSX:
tsx_op = 1'b1;
TXA:
txa_op = 1'b1;
TXS:
txs_op = 1'b1;
TYA:
tya_op = 1'b1;
endcase
end
else if (q_t == T2)
begin
case (q_ir)
ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS,
INC_ABS, LDA_ABS, LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS,
ROL_ABS, ROR_ABS, SBC_ABS,
JMP_IND:
begin
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
ADC_ABSX, AND_ABSX, ASL_ABSX, CMP_ABSX, DEC_ABSX, EOR_ABSX, INC_ABSX,
LDA_ABSX, LDY_ABSX, LSR_ABSX, ORA_ABSX, ROL_ABSX,
ROR_ABSX, SBC_ABSX, STA_ABSX,
ADC_ABSY, AND_ABSY, CMP_ABSY, EOR_ABSY, LDA_ABSY,
LDX_ABSY, ORA_ABSY, SBC_ABSY,
STA_ABSY:
begin
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_IMM, SBC_IMM:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
ADC_INDX, AND_INDX, CMP_INDX, EOR_INDX, LDA_INDX, ORA_INDX,
SAX_INDX, SBC_INDX, STA_INDX,
ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX,
EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX,
LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX, SBC_ZPX,
LDX_ZPY:
begin
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
ADC_INDY, AND_INDY, CMP_INDY, EOR_INDY, LDA_INDY, ORA_INDY,
SBC_INDY, STA_INDY:
begin
zero_to_abh = 1'b1;
aluinc_to_abl = 1'b1;
y_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ZP, AND_ZP, EOR_ZP, ORA_ZP:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
AND_IMM:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ACC:
begin
load_prg_byte = 1'b1;
asl_acc_op = 1'b1;
end
ASL_ZP, LSR_ZP, ROL_ZP, ROR_ZP:
begin
dl_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
LSR_ACC:
begin
load_prg_byte = 1'b1;
lsr_acc_op = 1'b1;
end
BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS:
begin
alusum_to_pcl = 1'b1;
alusum_to_abl = 1'b1;
if (q_ai[7])
neg1_to_ai = 1'b1;
else
one_to_ai = 1'b1;
pch_to_bi = 1'b1;
end
BIT_ZP:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
dl_bits67_to_p = 1'b1;
end
BRK:
begin
pcl_to_dor = 1'b1;
alusum_to_abl = 1'b1;
alusum_to_bi = 1'b1;
r_nw_out = 1'b0;
end
CMP_IMM, CPX_IMM, CPY_IMM:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
CMP_ZP, SBC_ZP:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPX_ZP:
begin
load_prg_byte = 1'b1;
x_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPY_ZP:
begin
load_prg_byte = 1'b1;
y_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEC_ZP:
begin
neg1_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
DEX:
begin
load_prg_byte = 1'b1;
dex_op = 1'b1;
end
DEY:
begin
load_prg_byte = 1'b1;
dey_op = 1'b1;
end
EOR_IMM:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
INC_ZP:
begin
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
INX:
begin
load_prg_byte = 1'b1;
inx_op = 1'b1;
end
INY:
begin
load_prg_byte = 1'b1;
iny_op = 1'b1;
end
JMP_ABS:
begin
dl_to_pch = 1'b1;
alusum_to_pcl = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
JSR:
begin
pch_to_dor = 1'b1;
neg1_to_ai = 1'b1;
end
LDA_ZP:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LDX_ZP:
begin
load_prg_byte = 1'b1;
ldx_op = 1'b1;
end
LDY_ZP:
begin
load_prg_byte = 1'b1;
ldy_op = 1'b1;
end
ORA_IMM:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
PHA, PHP:
begin
load_prg_byte_noinc = 1'b1;
s_to_ai = 1'b1;
neg1_to_bi = 1'b1;
r_nw_out = 1'b0;
end
PLA, PLP:
begin
one_to_abh = 1'b1;
aluinc_to_abl = 1'b1;
aluinc_to_s = 1'b1;
end
ROL_ACC:
begin
load_prg_byte = 1'b1;
rol_acc_op = 1'b1;
end
ROR_ACC:
begin
load_prg_byte = 1'b1;
ror_acc_op = 1'b1;
end
RTI, RTS:
begin
one_to_abh = 1'b1;
aluinc_to_abl = 1'b1;
aluinc_to_bi = 1'b1;
end
SAX_ABS:
begin
ac_to_dor = 1'b1;
x_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
SAX_ZP, STA_ZP, STX_ZP, STY_ZP:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
SAX_ZPY:
begin
ac_to_dor = 1'b1;
x_to_dor = 1'b1;
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STA_ABS:
begin
ac_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STA_ZPX:
begin
ac_to_dor = 1'b1;
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STX_ABS:
begin
x_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STX_ZPY:
begin
x_to_dor = 1'b1;
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STY_ABS:
begin
y_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STY_ZPX:
begin
y_to_dor = 1'b1;
zero_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
endcase
end
else if (q_t == T3)
begin
case (q_ir)
ADC_ABS, AND_ABS, EOR_ABS, ORA_ABS,
ADC_ZPX, AND_ZPX, EOR_ZPX, ORA_ZPX:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ABSX, AND_ABSX, ASL_ABSX, CMP_ABSX, DEC_ABSX, EOR_ABSX, INC_ABSX,
LDA_ABSX, LDY_ABSX, LSR_ABSX, ORA_ABSX, ROL_ABSX,
ROR_ABSX, SBC_ABSX,
ADC_ABSY, AND_ABSY, CMP_ABSY, EOR_ABSY, LDA_ABSY,
LDX_ABSY, ORA_ABSY, SBC_ABSY:
begin
aluinc_to_abh = q_acr;
end
ADC_INDX, AND_INDX, CMP_INDX, EOR_INDX, LDA_INDX, ORA_INDX,
SAX_INDX, STA_INDX, SBC_INDX:
begin
zero_to_abh = 1'b1;
aluinc_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_INDY, AND_INDY, CMP_INDY, EOR_INDY, LDA_INDY, ORA_INDY,
SBC_INDY, STA_INDY:
begin
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_ZP, SBC_ZP:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
AND_ZP:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ABS, LSR_ABS, ROL_ABS, ROR_ABS,
ASL_ZPX, LSR_ZPX, ROL_ZPX, ROR_ZPX:
begin
dl_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ASL_ZP:
asl_mem_op = 1'b1;
BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS:
begin
alusum_to_pch = 1'b1;
alusum_to_abh = 1'b1;
end
BIT_ABS:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
dl_bits67_to_p = 1'b1;
end
BIT_ZP:
begin
load_prg_byte = 1'b1;
bit_op = 1'b1;
end
BRK:
begin
p_to_dor = 1'b1;
alusum_to_abl = 1'b1;
alusum_to_bi = 1'b1;
r_nw_out = 1'b0;
end
CMP_ABS, SBC_ABS,
CMP_ZPX, SBC_ZPX:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CMP_ZP, CPX_ZP, CPY_ZP:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
CPX_ABS:
begin
load_prg_byte = 1'b1;
x_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
CPY_ABS:
begin
load_prg_byte = 1'b1;
y_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEC_ABS,
DEC_ZPX:
begin
neg1_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
DEC_ZP:
dec_op = 1'b1;
EOR_ZP:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
INC_ABS,
INC_ZPX:
begin
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
INC_ZP:
inc_op = 1'b1;
JMP_IND:
begin
aluinc_to_abl = 1'b1;
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
JSR:
begin
pcl_to_dor = 1'b1;
alusum_to_abl = 1'b1;
alusum_to_bi = 1'b1;
r_nw_out = 1'b0;
end
LDA_ABS, LDA_ZPX:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LDX_ABS, LDX_ZPY:
begin
load_prg_byte = 1'b1;
ldx_op = 1'b1;
end
LDY_ABS, LDY_ZPX:
begin
load_prg_byte = 1'b1;
ldy_op = 1'b1;
end
LSR_ZP:
lsr_mem_op = 1'b1;
ORA_ZP:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
PHA, PHP:
begin
load_prg_byte = 1'b1;
alusum_to_s = 1'b1;
end
PLA:
begin
load_prg_byte_noinc = 1'b1;
lda_op = 1'b1;
end
PLP:
begin
load_prg_byte_noinc = 1'b1;
dl_to_p = 1'b1;
end
ROL_ZP:
rol_mem_op = 1'b1;
ROR_ZP:
ror_mem_op = 1'b1;
RTI:
begin
aluinc_to_abl = 1'b1;
aluinc_to_bi = 1'b1;
dl_to_p = 1'b1;
end
RTS:
begin
aluinc_to_abl = 1'b1;
dl_to_s = 1'b1;
end
SAX_ABS, STA_ABS, STX_ABS, STY_ABS,
STA_ZPX, STY_ZPX,
SAX_ZPY, STX_ZPY:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
STA_ABSX,
STA_ABSY:
begin
ac_to_dor = 1'b1;
aluinc_to_abh = q_acr;
end
endcase
end
else if (q_t == T4)
begin
case (q_ir)
ADC_ABS, SBC_ABS,
ADC_ZPX, SBC_ZPX:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
ADC_ABSX, AND_ABSX, EOR_ABSX, ORA_ABSX,
ADC_ABSY, AND_ABSY, EOR_ABSY, ORA_ABSY:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
ADC_INDX, AND_INDX, CMP_INDX, EOR_INDX, LDA_INDX, ORA_INDX,
SBC_INDX:
begin
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
ADC_INDY, AND_INDY, CMP_INDY, EOR_INDY, LDA_INDY, ORA_INDY,
SBC_INDY:
begin
aluinc_to_abh = q_acr;
end
AND_ABS,
AND_ZPX:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ABS,
ASL_ZPX:
asl_mem_op = 1'b1;
ASL_ZP, DEC_ZP, INC_ZP, LSR_ZP, ROL_ZP, ROR_ZP,
STA_ABSX,
STA_ABSY:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
ASL_ABSX, LSR_ABSX, ROL_ABSX, ROR_ABSX:
begin
dl_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
BIT_ABS:
begin
load_prg_byte = 1'b1;
bit_op = 1'b1;
end
BRK:
begin
ff_to_abh = 1'b1;
r_nw_out = 1'b0;
one_to_i = 1'b1;
case (q_irq_sel)
INTERRUPT_RST: fc_to_abl = 1'b1;
INTERRUPT_NMI: fa_to_abl = 1'b1;
INTERRUPT_IRQ, INTERRUPT_BRK: fe_to_abl = 1'b1;
endcase
end
CMP_ABS, CPX_ABS, CPY_ABS,
CMP_ZPX:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
CMP_ABSX, SBC_ABSX,
CMP_ABSY, SBC_ABSY:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEC_ABS,
DEC_ZPX:
dec_op = 1'b1;
DEC_ABSX:
begin
neg1_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
EOR_ABS,
EOR_ZPX:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
INC_ABS,
INC_ZPX:
inc_op = 1'b1;
INC_ABSX:
begin
zero_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
JMP_IND:
begin
dl_to_pch = 1'b1;
alusum_to_pcl = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
JSR:
begin
load_prg_byte_noinc = 1'b1;
r_nw_out = 1'b0;
end
LDA_ABSX,
LDA_ABSY:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LDX_ABSY:
begin
load_prg_byte = 1'b1;
ldx_op = 1'b1;
end
LDY_ABSX:
begin
load_prg_byte = 1'b1;
ldy_op = 1'b1;
end
LSR_ABS,
LSR_ZPX:
lsr_mem_op = 1'b1;
ORA_ABS,
ORA_ZPX:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
ROL_ABS,
ROL_ZPX:
rol_mem_op = 1'b1;
ROR_ABS,
ROR_ZPX:
ror_mem_op = 1'b1;
RTI:
begin
aluinc_to_abl = 1'b1;
dl_to_s = 1'b1;
end
RTS:
begin
dl_to_pch = 1'b1;
s_to_pcl = 1'b1;
aluinc_to_s = 1'b1;
end
SAX_INDX:
begin
ac_to_dor = 1'b1;
x_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STA_INDX:
begin
ac_to_dor = 1'b1;
dl_to_abh = 1'b1;
alusum_to_abl = 1'b1;
end
STA_INDY:
begin
ac_to_dor = 1'b1;
aluinc_to_abh = q_acr;
end
endcase
end
else if (q_t == T5)
begin
case (q_ir)
ADC_ABSX, SBC_ABSX,
ADC_ABSY, SBC_ABSY:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
ADC_INDX, AND_INDX, EOR_INDX, ORA_INDX,
ADC_INDY, AND_INDY, EOR_INDY, ORA_INDY:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
dl_to_bi = 1'b1;
end
AND_ABSX,
AND_ABSY:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ABS, DEC_ABS, INC_ABS, LSR_ABS, ROL_ABS, ROR_ABS,
ASL_ZPX, DEC_ZPX, INC_ZPX, LSR_ZPX, ROL_ZPX, ROR_ZPX,
SAX_INDX, STA_INDX,
STA_INDY:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
ASL_ABSX:
asl_mem_op = 1'b1;
BRK:
begin
ff_to_abh = 1'b1;
dl_to_s = 1'b1;
case (q_irq_sel)
INTERRUPT_RST: fd_to_abl = 1'b1;
INTERRUPT_NMI: fb_to_abl = 1'b1;
INTERRUPT_IRQ, INTERRUPT_BRK: ff_to_abl = 1'b1;
endcase
end
CMP_ABSX,
CMP_ABSY:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
CMP_INDX, SBC_INDX,
CMP_INDY, SBC_INDY:
begin
load_prg_byte = 1'b1;
ac_to_ai = 1'b1;
invdl_to_bi = 1'b1;
end
DEC_ABSX:
dec_op = 1'b1;
EOR_ABSX,
EOR_ABSY:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
INC_ABSX:
inc_op = 1'b1;
JSR:
begin
dl_to_pch = 1'b1;
s_to_pcl = 1'b1;
dl_to_abh = 1'b1;
s_to_abl = 1'b1;
alusum_to_s = 1'b1;
end
LDA_INDX,
LDA_INDY:
begin
load_prg_byte = 1'b1;
lda_op = 1'b1;
end
LSR_ABSX:
lsr_mem_op = 1'b1;
ORA_ABSX,
ORA_ABSY:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
ROL_ABSX:
rol_mem_op = 1'b1;
ROR_ABSX:
ror_mem_op = 1'b1;
RTI:
begin
dl_to_pch = 1'b1;
s_to_pcl = 1'b1;
dl_to_abh = 1'b1;
s_to_abl = 1'b1;
aluinc_to_s = 1'b1;
end
RTS:
load_prg_byte = 1'b1;
endcase
end
else if (q_t == T6)
begin
case (q_ir)
ADC_INDX, SBC_INDX,
ADC_INDY, SBC_INDY:
begin
load_prg_byte = 1'b1;
adc_op = 1'b1;
end
AND_INDX,
AND_INDY:
begin
load_prg_byte = 1'b1;
and_op = 1'b1;
end
ASL_ABSX, DEC_ABSX, INC_ABSX, LSR_ABSX, ROL_ABSX, ROR_ABSX:
begin
load_prg_byte = 1'b1;
r_nw_out = 1'b0;
end
BRK:
begin
dl_to_pch = 1'b1;
s_to_pcl = 1'b1;
dl_to_abh = 1'b1;
s_to_abl = 1'b1;
alusum_to_s = 1'b1;
case (q_irq_sel)
INTERRUPT_RST: clear_rst = 1'b1;
INTERRUPT_NMI: clear_nmi = 1'b1;
endcase
end
CMP_INDX,
CMP_INDY:
begin
load_prg_byte = 1'b1;
cmp_op = 1'b1;
end
EOR_INDX,
EOR_INDY:
begin
load_prg_byte = 1'b1;
eor_op = 1'b1;
end
ORA_INDX,
ORA_INDY:
begin
load_prg_byte = 1'b1;
ora_op = 1'b1;
end
endcase
end
end
//
// ALU
//
always @*
begin
acr = 1'b0;
avr = 1'b0;
if (ands)
d_add = q_ai & q_bi;
else if (eors)
d_add = q_ai ^ q_bi;
else if (ors)
d_add = q_ai | q_bi;
else if (sums)
begin
{ acr, d_add } = q_ai + q_bi + addc;
avr = ((q_ai[7] ^ q_bi[7]) ^ d_add[7]) ^ acr;
end
else if (srs)
{ d_add, acr } = { addc, q_bi };
else
d_add = q_add;
end
//
// Random Control Logic
//
assign add_adl = aluinc_to_abl | aluinc_to_bi | alusum_to_abl |
alusum_to_bi | alusum_to_pcl;
assign dl_adl = dl_to_abl;
assign pcl_adl = load_prg_byte | load_prg_byte_noinc |
pcl_to_bi;
assign s_adl = s_to_abl | s_to_bi | s_to_pcl;
assign zero_adl0 = fa_to_abl | fc_to_abl | fe_to_abl;
assign zero_adl1 = fc_to_abl | fd_to_abl;
assign zero_adl2 = fa_to_abl | fb_to_abl;
assign dl_adh = dl_to_abh | dl_to_pch;
assign pch_adh = load_prg_byte | load_prg_byte_noinc;
assign zero_adh0 = zero_to_abh;
assign zero_adh17 = one_to_abh | one_to_ai | zero_to_abh;
assign ac_db = ac_to_bi | ac_to_dor;
assign dl_db = dl_to_ai | dl_to_bi |
dl_to_p | dl_to_s | invdl_to_bi |
lda_op | ldx_op | ldy_op;
assign p_db = p_to_dor;
assign pch_db = pch_to_bi | pch_to_dor;
assign pcl_db = pcl_to_dor;
assign ac_sb = ac_to_ai | tax_op | tay_op;
assign add_sb = adc_op | aluinc_to_abh |
aluinc_to_s | alusum_to_abh | alusum_to_pch |
alusum_to_s | and_op |
asl_acc_op | asl_mem_op | bit_op |
cmp_op | dec_op | dex_op |
dey_op | eor_op | inc_op |
inx_op | iny_op | lsr_acc_op |
lsr_mem_op | ora_op | rol_acc_op |
rol_mem_op | ror_acc_op | ror_mem_op;
assign x_sb = txa_op | txs_op | x_to_ai |
x_to_bi | x_to_dor;
assign y_sb = tya_op | y_to_ai | y_to_bi |
y_to_dor;
assign s_sb = s_to_ai | tsx_op;
assign sb_adh = aluinc_to_abh | alusum_to_abh | alusum_to_pch |
one_to_ai | one_to_i;
assign sb_db = adc_op |
and_op | asl_acc_op |
asl_mem_op | bit_op | cmp_op |
dl_to_s | dec_op | dex_op |
dey_op | dl_to_ai | eor_op |
inc_op | inx_op | iny_op |
lda_op | ldx_op | ldy_op |
lsr_acc_op | lsr_mem_op | one_to_i |
ora_op | rol_acc_op | rol_mem_op |
ror_acc_op | ror_mem_op | tax_op |
tay_op | tsx_op | txa_op |
tya_op | x_to_bi | x_to_dor |
y_to_bi | y_to_dor;
assign adh_abh = aluinc_to_abh | alusum_to_abh | dl_to_abh |
ff_to_abh | load_prg_byte | load_prg_byte_noinc |
one_to_abh | zero_to_abh;
assign adl_abl = aluinc_to_abl | alusum_to_abl | dl_to_abl |
fa_to_abl | fb_to_abl | fc_to_abl |
fd_to_abl | fe_to_abl | ff_to_abl |
load_prg_byte | load_prg_byte_noinc |
s_to_abl;
assign adl_add = aluinc_to_bi | alusum_to_bi | pcl_to_bi |
s_to_bi;
assign db_add = ac_to_bi | dl_to_bi |
neg1_to_bi | pch_to_bi | x_to_bi |
y_to_bi;
assign invdb_add = invdl_to_bi;
assign sb_s = aluinc_to_s | alusum_to_s | dl_to_s |
txs_op;
assign zero_add = zero_to_ai;
assign sb_ac = adc_op | and_op |
asl_acc_op | eor_op |
lda_op | lsr_acc_op | ora_op |
rol_acc_op | ror_acc_op | txa_op |
tya_op;
assign sb_add = ac_to_ai | dl_to_ai | neg1_to_ai |
one_to_ai | s_to_ai | x_to_ai |
y_to_ai;
assign adh_pch = alusum_to_pch | dl_to_pch;
assign adl_pcl = alusum_to_pcl | s_to_pcl;
assign sb_x = dex_op | inx_op | ldx_op |
tax_op | tsx_op;
assign sb_y = dey_op | iny_op | ldy_op |
tay_op;
assign acr_c = adc_op | asl_acc_op | asl_mem_op |
cmp_op | lsr_acc_op | lsr_mem_op |
rol_acc_op | rol_mem_op | ror_acc_op |
ror_mem_op;
assign db0_c = dl_to_p;
assign ir5_c = clc_op | sec_op;
assign db3_d = dl_to_p;
assign ir5_d = cld_op | sed_op;
assign db2_i = dl_to_p | one_to_i;
assign ir5_i = cli_op | sei_op;
assign db7_n = adc_op | and_op |
asl_acc_op | asl_mem_op |
cmp_op | dec_op | dex_op |
dey_op | dl_bits67_to_p | dl_to_p |
eor_op | inc_op | inx_op |
iny_op | lda_op | ldx_op |
ldy_op | lsr_acc_op | lsr_mem_op |
ora_op | rol_acc_op | rol_mem_op |
ror_acc_op | ror_mem_op | tax_op |
tay_op | tsx_op | txa_op |
tya_op;
assign avr_v = adc_op;
assign db6_v = dl_bits67_to_p | dl_to_p;
assign zero_v = clv_op;
assign db1_z = dl_to_p;
assign dbz_z = adc_op | and_op |
asl_acc_op | asl_mem_op |
bit_op | cmp_op | dec_op |
dex_op | dey_op | eor_op |
inc_op | inx_op | iny_op |
lda_op | ldx_op | ldy_op |
lsr_acc_op | lsr_mem_op | ora_op |
rol_acc_op | rol_mem_op | ror_acc_op |
ror_mem_op | tax_op | tay_op |
tsx_op | txa_op | tya_op;
assign ands = and_op | bit_op;
assign eors = eor_op;
assign ors = ora_op;
assign sums = adc_op | aluinc_to_abh | aluinc_to_abl |
aluinc_to_bi | aluinc_to_s |
alusum_to_abh | alusum_to_abl | alusum_to_bi |
alusum_to_pch | alusum_to_pcl | alusum_to_s |
asl_acc_op | asl_mem_op | cmp_op |
dec_op | dex_op | dey_op |
inc_op | inx_op | iny_op |
rol_acc_op | rol_mem_op;
assign srs = lsr_acc_op | lsr_mem_op |
ror_acc_op | ror_mem_op;
assign addc = (adc_op | rol_acc_op | rol_mem_op | ror_acc_op | ror_mem_op) ? q_c :
aluinc_to_abh | aluinc_to_abl | aluinc_to_bi |
aluinc_to_s | cmp_op |
inc_op | inx_op | iny_op;
assign i_pc = (incpc_noload | load_prg_byte) & !force_noinc_pc;
//
// Update internal buses. Use in/out to replicate pass mosfets and avoid using internal
// tristate buffers.
//
assign adh_in[7:1] = (dl_adh) ? q_dl[7:1] :
(pch_adh) ? q_pch[7:1] :
(zero_adh17) ? 7'h00 : 7'h7F;
assign adh_in[0] = (dl_adh) ? q_dl[0] :
(pch_adh) ? q_pch[0] :
(zero_adh0) ? 1'b0 : 1'b1;
assign adl[7:3] = (add_adl) ? q_add[7:3] :
(dl_adl) ? q_dl[7:3] :
(pcl_adl) ? q_pcl[7:3] :
(s_adl) ? q_s[7:3] : 5'h1F;
assign adl[2] = (add_adl) ? q_add[2] :
(dl_adl) ? q_dl[2] :
(pcl_adl) ? q_pcl[2] :
(s_adl) ? q_s[2] :
(zero_adl2) ? 1'b0 : 1'b1;
assign adl[1] = (add_adl) ? q_add[1] :
(dl_adl) ? q_dl[1] :
(pcl_adl) ? q_pcl[1] :
(s_adl) ? q_s[1] :
(zero_adl1) ? 1'b0 : 1'b1;
assign adl[0] = (add_adl) ? q_add[0] :
(dl_adl) ? q_dl[0] :
(pcl_adl) ? q_pcl[0] :
(s_adl) ? q_s[0] :
(zero_adl0) ? 1'b0 : 1'b1;
assign db_in = 8'hFF & ({8{~ac_db}} | q_ac) &
({8{~dl_db}} | q_dl) &
({8{~p_db}} | p) &
({8{~pch_db}} | q_pch) &
({8{~pcl_db}} | q_pcl);
assign sb_in = 8'hFF & ({8{~ac_sb}} | q_ac) &
({8{~add_sb}} | q_add) &
({8{~s_sb}} | q_s) &
({8{~x_sb}} | q_x) &
({8{~y_sb}} | q_y);
assign adh_out = (sb_adh & sb_db) ? (adh_in & sb_in & db_in) :
(sb_adh) ? (adh_in & sb_in) :
(adh_in);
assign db_out = (sb_db & sb_adh) ? (db_in & sb_in & adh_in) :
(sb_db) ? (db_in & sb_in) :
(db_in);
assign sb_out = (sb_adh & sb_db) ? (sb_in & db_in & adh_in) :
(sb_db) ? (sb_in & db_in) :
(sb_adh) ? (sb_in & adh_in) :
(sb_in);
//
// Assign next FF states.
//
assign d_ac = (sb_ac) ? sb_out : q_ac;
assign d_x = (sb_x) ? sb_out : q_x;
assign d_y = (sb_y) ? sb_out : q_y;
assign d_c = (acr_c) ? acr :
(db0_c) ? db_out[0] :
(ir5_c) ? q_ir[5] : q_c;
assign d_d = (db3_d) ? db_out[3] :
(ir5_d) ? q_ir[5] : q_d;
assign d_i = (db2_i) ? db_out[2] :
(ir5_i) ? q_ir[5] : q_i;
assign d_n = (db7_n) ? db_out[7] : q_n;
assign d_v = (avr_v) ? avr :
(db6_v) ? db_out[6] :
(zero_v) ? 1'b0 : q_v;
assign d_z = (db1_z) ? db_out[1] :
(dbz_z) ? ~|db_out : q_z;
assign d_abh = (adh_abh) ? adh_out : q_abh;
assign d_abl = (adl_abl) ? adl : q_abl;
assign d_ai = (sb_add) ? sb_out :
(zero_add) ? 8'h0 : q_ai;
assign d_bi = (adl_add) ? adl :
(db_add) ? db_out :
(invdb_add) ? ~db_out : q_bi;
assign d_dl = (r_nw_out) ? d_in : q_dl;
assign d_dor = db_out;
assign d_pd = (r_nw_out) ? d_in : q_pd;
assign d_s = (sb_s) ? sb_out : q_s;
assign d_pchs = (adh_pch) ? adh_out : q_pch;
assign d_pcls = (adl_pcl) ? adl : q_pcl;
assign { d_pch, d_pcl } = (i_pc) ? { q_pchs, q_pcls } + 16'h0001 : { q_pchs, q_pcls };
// Combine full processor status register.
assign p = { q_n, q_v, 1'b1, (q_irq_sel == INTERRUPT_BRK), q_d, q_i, q_z, q_c };
//
// Assign output signals.
//
assign d_out = q_dor;
assign a_out = { q_abh, q_abl };
always @*
begin
case (dbgreg_sel_in)
`REGSEL_AC: dbgreg_out = q_ac;
`REGSEL_X: dbgreg_out = q_x;
`REGSEL_Y: dbgreg_out = q_y;
`REGSEL_P: dbgreg_out = p;
`REGSEL_PCH: dbgreg_out = q_pch;
`REGSEL_PCL: dbgreg_out = q_pcl;
`REGSEL_S: dbgreg_out = q_s;
default: dbgreg_out = 8'hxx;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A311OI_BEHAVIORAL_PP_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a311oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
// Local signals
wire B1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311OI_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_TB_V
`define SKY130_FD_SC_HVL__NOR3_TB_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__nor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hvl__nor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_TB_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iobdg_int_mondo_addr_dec.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg_int_mondo_addr_dec
// Description: Logic to generate address to
// index the mondo data table.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module iobdg_int_mondo_addr_dec (/*AUTOARG*/
// Outputs
creg_mdata0_dec, creg_mdata1_dec, creg_mbusy_dec, mondo_data_addr,
addr_invld,
// Inputs
addr_in, thr_id_in
);
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
input [`IOB_ADDR_WIDTH-1:0] addr_in;
input [`IOB_CPUTHR_INDEX-1:0] thr_id_in;
output creg_mdata0_dec;
output creg_mdata1_dec;
output creg_mbusy_dec;
output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr;
output addr_invld;
wire creg_mdata0_alias_dec;
wire creg_mdata1_alias_dec;
wire creg_mbusy_alias_dec;
wire creg_mdata0_proper_dec;
wire creg_mdata1_proper_dec;
wire creg_mbusy_proper_dec;
wire use_thr_addr;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
// Assertion: Decode signals should be mutually exclusive.
/*****************************************************************
* Decode for Mondo Data0, Mondo Data1, Mondo Busy access
* Assumption: addr_in is within the IOB_INT_CSR range
*****************************************************************/
// Decode alias address (what software normally uses)
assign creg_mdata0_alias_dec =
(addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0]
== `IOB_CREG_MDATA0_ALIAS);
assign creg_mdata1_alias_dec =
(addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0]
== `IOB_CREG_MDATA1_ALIAS);
assign creg_mbusy_alias_dec =
(addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0]
== `IOB_CREG_MBUSY_ALIAS);
// Decode proper address (what the TAP has to use)
assign creg_mdata0_proper_dec =
((addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0] & `IOB_THR_ADDR_MASK)
== `IOB_CREG_MDATA0);
assign creg_mdata1_proper_dec =
((addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0] & `IOB_THR_ADDR_MASK)
== `IOB_CREG_MDATA1);
assign creg_mbusy_proper_dec =
((addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0] & `IOB_THR_ADDR_MASK)
== `IOB_CREG_MBUSY);
// Combine proper and alias decode results
assign creg_mdata0_dec = creg_mdata0_proper_dec | creg_mdata0_alias_dec;
assign creg_mdata1_dec = creg_mdata1_proper_dec | creg_mdata1_alias_dec;
assign creg_mbusy_dec = creg_mbusy_proper_dec | creg_mbusy_alias_dec;
assign use_thr_addr = creg_mdata0_alias_dec |
creg_mdata1_alias_dec |
creg_mbusy_alias_dec;
// Use thread ID as index into array if request comes from software
// Use the address directly if request comes from TAP
assign mondo_data_addr = use_thr_addr ? thr_id_in :
addr_in[`IOB_MONDO_DATA_INDEX-1+3:3];
/*****************************************************************
* Assert address invalid if no register address match
*****************************************************************/
assign addr_invld = ~creg_mdata0_dec &
~creg_mdata1_dec &
~creg_mbusy_dec;
endmodule // iobdg_int_mondo_addr_dec
|
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_ps2, input_i2c, input_switches, input_eth_rx, input_buttons, input_timer_stb, input_rs232_rx_stb, input_ps2_stb, input_i2c_stb, input_switches_stb, input_eth_rx_stb, input_buttons_stb, input_timer_ack, input_rs232_rx_ack, input_ps2_ack, input_i2c_ack, input_switches_ack, input_eth_rx_ack, input_buttons_ack, output_seven_segment_annode, output_eth_tx, output_rs232_tx, output_leds, output_audio, output_led_g, output_seven_segment_cathode, output_led_b, output_i2c, output_vga, output_led_r, output_seven_segment_annode_stb, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_audio_stb, output_led_g_stb, output_seven_segment_cathode_stb, output_led_b_stb, output_i2c_stb, output_vga_stb, output_led_r_stb, output_seven_segment_annode_ack, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack, output_audio_ack, output_led_g_ack, output_seven_segment_cathode_ack, output_led_b_ack, output_i2c_ack, output_vga_ack, output_led_r_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
input [31:0] input_i2c;
input input_i2c_stb;
output input_i2c_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
output [31:0] output_seven_segment_annode;
output output_seven_segment_annode_stb;
input output_seven_segment_annode_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_audio;
output output_audio_stb;
input output_audio_ack;
output [31:0] output_led_g;
output output_led_g_stb;
input output_led_g_ack;
output [31:0] output_seven_segment_cathode;
output output_seven_segment_cathode_stb;
input output_seven_segment_cathode_ack;
output [31:0] output_led_b;
output output_led_b_stb;
input output_led_b_ack;
output [31:0] output_i2c;
output output_i2c_stb;
input output_i2c_ack;
output [31:0] output_vga;
output output_vga_stb;
input output_vga_ack;
output [31:0] output_led_r;
output output_led_r_stb;
input output_led_r_ack;
wire exception_139931276207744;
wire exception_139931276329976;
wire exception_139931273691576;
wire exception_139931279256392;
wire exception_139931273476792;
wire exception_139931279285064;
wire exception_139931284115112;
wire exception_139931283339240;
wire exception_139931274721040;
wire exception_139931279910528;
wire exception_139931279158952;
wire exception_139931276720176;
wire exception_139931279933952;
wire exception_139931278247408;
wire exception_139931279929216;
wire exception_139931284950696;
wire exception_139931275440568;
main_0 main_0_139931276207744(
.clk(clk),
.rst(rst),
.exception(exception_139931276207744),
.output_rs232_out(output_rs232_tx),
.output_rs232_out_stb(output_rs232_tx_stb),
.output_rs232_out_ack(output_rs232_tx_ack),
.output_vga_out(output_vga),
.output_vga_out_stb(output_vga_stb),
.output_vga_out_ack(output_vga_ack));
main_1 main_1_139931276329976(
.clk(clk),
.rst(rst),
.exception(exception_139931276329976),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_2 main_2_139931273691576(
.clk(clk),
.rst(rst),
.exception(exception_139931273691576),
.input_in(input_rs232_rx),
.input_in_stb(input_rs232_rx_stb),
.input_in_ack(input_rs232_rx_ack));
main_3 main_3_139931279256392(
.clk(clk),
.rst(rst),
.exception(exception_139931279256392),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_4 main_4_139931273476792(
.clk(clk),
.rst(rst),
.exception(exception_139931273476792),
.input_in(input_i2c),
.input_in_stb(input_i2c_stb),
.input_in_ack(input_i2c_ack));
main_5 main_5_139931279285064(
.clk(clk),
.rst(rst),
.exception(exception_139931279285064),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_6 main_6_139931284115112(
.clk(clk),
.rst(rst),
.exception(exception_139931284115112),
.input_in(input_eth_rx),
.input_in_stb(input_eth_rx_stb),
.input_in_ack(input_eth_rx_ack));
main_7 main_7_139931283339240(
.clk(clk),
.rst(rst),
.exception(exception_139931283339240),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_8 main_8_139931274721040(
.clk(clk),
.rst(rst),
.exception(exception_139931274721040),
.output_out(output_seven_segment_annode),
.output_out_stb(output_seven_segment_annode_stb),
.output_out_ack(output_seven_segment_annode_ack));
main_9 main_9_139931279910528(
.clk(clk),
.rst(rst),
.exception(exception_139931279910528),
.output_out(output_eth_tx),
.output_out_stb(output_eth_tx_stb),
.output_out_ack(output_eth_tx_ack));
main_10 main_10_139931279158952(
.clk(clk),
.rst(rst),
.exception(exception_139931279158952),
.output_out(output_leds),
.output_out_stb(output_leds_stb),
.output_out_ack(output_leds_ack));
main_11 main_11_139931276720176(
.clk(clk),
.rst(rst),
.exception(exception_139931276720176),
.output_out(output_audio),
.output_out_stb(output_audio_stb),
.output_out_ack(output_audio_ack));
main_12 main_12_139931279933952(
.clk(clk),
.rst(rst),
.exception(exception_139931279933952),
.output_out(output_led_g),
.output_out_stb(output_led_g_stb),
.output_out_ack(output_led_g_ack));
main_13 main_13_139931278247408(
.clk(clk),
.rst(rst),
.exception(exception_139931278247408),
.output_out(output_seven_segment_cathode),
.output_out_stb(output_seven_segment_cathode_stb),
.output_out_ack(output_seven_segment_cathode_ack));
main_14 main_14_139931279929216(
.clk(clk),
.rst(rst),
.exception(exception_139931279929216),
.output_out(output_led_b),
.output_out_stb(output_led_b_stb),
.output_out_ack(output_led_b_ack));
main_15 main_15_139931284950696(
.clk(clk),
.rst(rst),
.exception(exception_139931284950696),
.output_out(output_i2c),
.output_out_stb(output_i2c_stb),
.output_out_ack(output_i2c_ack));
main_16 main_16_139931275440568(
.clk(clk),
.rst(rst),
.exception(exception_139931275440568),
.output_out(output_led_r),
.output_out_stb(output_led_r_stb),
.output_out_ack(output_led_r_ack));
assign exception = exception_139931276207744 || exception_139931276329976 || exception_139931273691576 || exception_139931279256392 || exception_139931273476792 || exception_139931279285064 || exception_139931284115112 || exception_139931283339240 || exception_139931274721040 || exception_139931279910528 || exception_139931279158952 || exception_139931276720176 || exception_139931279933952 || exception_139931278247408 || exception_139931279929216 || exception_139931284950696 || exception_139931275440568;
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module cmd_seq_core #(
parameter ABUSWIDTH = 16,
parameter OUTPUTS = 1, // from (0 : 8]
parameter CMD_MEM_SIZE = 2048 // max. 8192-1 bytes
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
input wire BUS_RD,
input wire BUS_WR,
output reg [7:0] BUS_DATA_OUT,
output wire [OUTPUTS-1:0] CMD_CLK_OUT,
input wire CMD_CLK_IN,
input wire CMD_EXT_START_FLAG,
output wire CMD_EXT_START_ENABLE,
output wire [OUTPUTS-1:0] CMD_DATA,
output reg CMD_READY,
output reg CMD_START_FLAG
);
localparam VERSION = 1;
generate
if (OUTPUTS > 8) begin
illegal_outputs_parameter non_existing_module();
end
endgenerate
generate
if (CMD_MEM_SIZE > 8191) begin
illegal_outputs_parameter non_existing_module();
end
endgenerate
// IEEE Std 1800-2009
// generate
// if (CONDITION > MAX_ALLOWED) begin
// $error("%m ** Illegal Condition ** CONDITION(%d) > MAX_ALLOWED(%d)", CONDITION, MAX_ALLOWED);
// end
// endgenerate
`include "../includes/log2func.v"
localparam CMD_ADDR_SIZE = `CLOG2(CMD_MEM_SIZE);
wire SOFT_RST; //0
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
// reset sync
// when write to addr = 0 then reset
reg RST_FF, RST_FF2, BUS_RST_FF, BUS_RST_FF2;
always @(posedge BUS_CLK) begin
RST_FF <= SOFT_RST;
RST_FF2 <= RST_FF;
BUS_RST_FF <= BUS_RST;
BUS_RST_FF2 <= BUS_RST_FF;
end
wire SOFT_RST_FLAG;
assign SOFT_RST_FLAG = ~RST_FF2 & RST_FF;
wire BUS_RST_FLAG;
assign BUS_RST_FLAG = BUS_RST_FF2 & ~BUS_RST_FF; // trailing edge
wire RST;
assign RST = BUS_RST_FLAG | SOFT_RST_FLAG;
wire RST_CMD_CLK;
flag_domain_crossing cmd_rst_flag_domain_crossing (
.CLK_A(BUS_CLK),
.CLK_B(CMD_CLK_IN),
.FLAG_IN_CLK_A(RST),
.FLAG_OUT_CLK_B(RST_CMD_CLK)
);
wire CONF_START; // 1
assign CONF_START = (BUS_ADD==1 && BUS_WR);
wire CONF_START_FLAG_SYNC;
flag_domain_crossing conf_start_flag_domain_crossing (
.CLK_A(BUS_CLK),
.CLK_B(CMD_CLK_IN),
.FLAG_IN_CLK_A(CONF_START),
.FLAG_OUT_CLK_B(CONF_START_FLAG_SYNC)
);
reg [0:0] CONF_READY; // 1
wire CONF_EN_EXT_START, CONF_DIS_CLOCK_GATE, CONF_DIS_CMD_PULSE; // 2
wire [1:0] CONF_OUTPUT_MODE; // 2 Mode == 0: posedge, 1: negedge, 2: Manchester Code according to IEEE 802.3, 3: Manchester Code according to G.E. Thomas aka Biphase-L or Manchester-II
wire [15:0] CONF_CMD_SIZE; // 3 - 4
wire [31:0] CONF_REPEAT_COUNT; // 5 - 8
wire [15:0] CONF_START_REPEAT; // 9 - 10
wire [15:0] CONF_STOP_REPEAT; // 11 - 12
wire [7:0] CONF_OUTPUT_ENABLE; //13
// ATTENTION:
// -(CONF_CMD_SIZE - CONF_START_REPEAT - CONF_STOP_REPEAT) must be greater than or equal to 2
// - CONF_START_REPEAT must be greater than or equal to 2
// - CONF_STOP_REPEAT must be greater than or equal to 2
reg [7:0] status_regs [13:0];
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0;
status_regs[1] <= 0;
status_regs[2] <= 8'b0000_0000;
status_regs[3] <= 0;
status_regs[4] <= 0;
status_regs[5] <= 8'd1; // CONF_REPEAT_COUNT, repeat once by default
status_regs[6] <= 0;
status_regs[7] <= 0;
status_regs[8] <= 0;
status_regs[9] <= 0; // CONF_START_REPEAT
status_regs[10] <= 0;
status_regs[11] <= 0;// CONF_STOP_REPEAT
status_regs[12] <= 0;
status_regs[13] <= 8'hff; //OUTPUT_EN
end
else if(BUS_WR && BUS_ADD < 14)
status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN;
end
assign CONF_CMD_SIZE = {status_regs[4], status_regs[3]};
assign CONF_REPEAT_COUNT = {status_regs[8], status_regs[7], status_regs[6], status_regs[5]};
assign CONF_START_REPEAT = {status_regs[10], status_regs[9]};
assign CONF_STOP_REPEAT = {status_regs[12], status_regs[11]};
assign CONF_OUTPUT_ENABLE = status_regs[13];
assign CONF_DIS_CMD_PULSE = status_regs[2][4];
assign CONF_DIS_CLOCK_GATE = status_regs[2][3];
assign CONF_OUTPUT_MODE = status_regs[2][2:1];
assign CONF_EN_EXT_START = status_regs[2][0];
three_stage_synchronizer conf_en_ext_start_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_EN_EXT_START),
.OUT(CMD_EXT_START_ENABLE)
);
wire [15:0] CONF_CMD_SIZE_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(16)
) cmd_size_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_CMD_SIZE),
.OUT(CONF_CMD_SIZE_CMD_CLK)
);
wire [31:0] CONF_REPEAT_COUNT_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(32)
) repeat_cnt_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_REPEAT_COUNT),
.OUT(CONF_REPEAT_COUNT_CMD_CLK)
);
wire [15:0] CONF_START_REPEAT_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(16)
) start_repeat_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_START_REPEAT),
.OUT(CONF_START_REPEAT_CMD_CLK)
);
wire [15:0] CONF_STOP_REPEAT_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(16)
) stop_repeat_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_STOP_REPEAT),
.OUT(CONF_STOP_REPEAT_CMD_CLK)
);
wire [OUTPUTS-1:0] CONF_OUTPUT_ENABLE_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(OUTPUTS)
) conf_output_enable_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_OUTPUT_ENABLE[OUTPUTS-1:0]),
.OUT(CONF_OUTPUT_ENABLE_CMD_CLK)
);
wire CONF_DIS_CMD_PULSE_CMD_CLK;
three_stage_synchronizer conf_dis_cmd_pulse_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_DIS_CMD_PULSE),
.OUT(CONF_DIS_CMD_PULSE_CMD_CLK)
);
wire CONF_DIS_CLOCK_GATE_CMD_CLK;
three_stage_synchronizer conf_dis_clock_gate_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_DIS_CLOCK_GATE),
.OUT(CONF_DIS_CLOCK_GATE_CMD_CLK)
);
wire [1:0] CONF_OUTPUT_MODE_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(2)
) conf_output_mode_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_OUTPUT_MODE),
.OUT(CONF_OUTPUT_MODE_CMD_CLK)
);
wire [7:0] CMD_MEM_DATA;
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= {7'b0, CONF_READY};
else if(BUS_ADD < 14)
BUS_DATA_OUT <= status_regs[BUS_ADD[3:0]];
else if(BUS_ADD < 16)
BUS_DATA_OUT <= 8'b0;
else if(BUS_ADD < (16 + CMD_MEM_SIZE))
BUS_DATA_OUT <= CMD_MEM_DATA;
end
end
// (* RAM_STYLE="{BLOCK}" *)
reg [7:0] cmd_mem [0:CMD_MEM_SIZE-1];
always @(posedge BUS_CLK) begin
if (BUS_WR && BUS_ADD >= 16 && BUS_ADD < (16 + CMD_MEM_SIZE))
cmd_mem[BUS_ADD - 16] <= BUS_DATA_IN;
end
reg [CMD_ADDR_SIZE-1:0] CMD_MEM_ADD;
assign CMD_MEM_DATA = cmd_mem[BUS_RD && BUS_ADD >= 16 && BUS_ADD < (16 + CMD_MEM_SIZE) ? (BUS_ADD - 16) : CMD_MEM_ADD];
wire EXT_START_FLAG;
assign EXT_START_FLAG = (CMD_EXT_START_FLAG & CMD_EXT_START_ENABLE);
wire send_cmd;
assign send_cmd = CONF_START_FLAG_SYNC | EXT_START_FLAG;
localparam WAIT = 0, SEND = 1;
reg [15:0] cnt;
reg [31:0] repeat_cnt;
reg state, next_state;
always @(posedge CMD_CLK_IN)
if (RST_CMD_CLK)
state <= WAIT;
else
state <= next_state;
// reg END_SEQ_REP_NEXT, END_SEQ_REP;
// always @(*) begin
// if((repeat_cnt < CONF_REPEAT_COUNT_CMD_CLK || CONF_REPEAT_COUNT_CMD_CLK == 0) && cnt == CONF_CMD_SIZE_CMD_CLK - 1 - CONF_STOP_REPEAT_CMD_CLK && !END_SEQ_REP)
// END_SEQ_REP_NEXT = 1;
// else
// END_SEQ_REP_NEXT = 0;
// end
// always @(posedge CMD_CLK_IN)
// END_SEQ_REP <= END_SEQ_REP_NEXT;
reg START_STOP_REPEAT_OK;
always @(posedge CMD_CLK_IN)
if ((CONF_START_REPEAT_CMD_CLK + CONF_STOP_REPEAT_CMD_CLK) > CONF_CMD_SIZE_CMD_CLK)
START_STOP_REPEAT_OK <= 1'b0;
else
START_STOP_REPEAT_OK <= 1'b1;
reg [31:0] SET_REPEAT_COUNT;
always @(posedge CMD_CLK_IN)
if (CONF_START_REPEAT_CMD_CLK + CONF_STOP_REPEAT_CMD_CLK == CONF_CMD_SIZE_CMD_CLK)
SET_REPEAT_COUNT <= 1;
else
SET_REPEAT_COUNT <= CONF_REPEAT_COUNT_CMD_CLK;
always @(*) begin
case (state)
WAIT:
if (send_cmd && CONF_CMD_SIZE_CMD_CLK != 0 && START_STOP_REPEAT_OK)
next_state = SEND;
else
next_state = WAIT;
SEND:
if (cnt >= CONF_CMD_SIZE_CMD_CLK && repeat_cnt >= SET_REPEAT_COUNT && SET_REPEAT_COUNT != 0)
next_state = WAIT;
else
next_state = SEND;
default:
next_state = WAIT;
endcase
end
always @(posedge CMD_CLK_IN) begin
if (RST_CMD_CLK) begin
cnt <= 0;
end else begin
if (next_state == WAIT) begin
cnt <= 0; // TODO: adding start value here
end else begin
if ((repeat_cnt < SET_REPEAT_COUNT || SET_REPEAT_COUNT == 0) && (cnt == CONF_CMD_SIZE_CMD_CLK - CONF_STOP_REPEAT_CMD_CLK - 1)) begin
cnt <= CONF_START_REPEAT_CMD_CLK;
end else begin
cnt <= cnt + 1;
end
end
end
end
always @(posedge CMD_CLK_IN) begin
if (RST_CMD_CLK)
repeat_cnt <= 1;
else
if (next_state == WAIT)
repeat_cnt <= 1;
else if ((next_state == SEND) && (cnt == CONF_CMD_SIZE_CMD_CLK - CONF_STOP_REPEAT_CMD_CLK - 1))
repeat_cnt <= repeat_cnt + 1;
end
// always @(posedge CMD_CLK_IN) begin
// if (RST_CMD_CLK) begin
// CMD_MEM_ADD <= 0;
// end else begin
// CMD_MEM_ADD <= cnt / 8;
// end
// end
// reg cmd_data_ser;
// always @(posedge CMD_CLK_IN) begin
// if (state == WAIT)
// cmd_data_ser <= 1'b0;
// else
// cmd_data_ser <= CMD_MEM_DATA[7 - ((cnt_buf) % 8)];
// end
always @(posedge CMD_CLK_IN) begin
if (RST_CMD_CLK) begin
CMD_MEM_ADD <= 0;
end else begin
if (cnt == CONF_CMD_SIZE_CMD_CLK - CONF_STOP_REPEAT_CMD_CLK - 1 && repeat_cnt < SET_REPEAT_COUNT && SET_REPEAT_COUNT != 0) begin
CMD_MEM_ADD <= CONF_START_REPEAT_CMD_CLK / 8;
end else begin
// if ()
CMD_MEM_ADD <= (cnt + 1) / 8;
end
end
end
reg [7:0] CMD_MEM_DATA_BUF;
always @(posedge CMD_CLK_IN) begin
CMD_MEM_DATA_BUF <= CMD_MEM_DATA;
end
reg [15:0] cnt_buf;
always @(posedge CMD_CLK_IN) begin
cnt_buf <= cnt;
end
reg cmd_data_ser;
always @(posedge CMD_CLK_IN) begin
if (state == WAIT)
cmd_data_ser <= 1'b0;
else
cmd_data_ser <= CMD_MEM_DATA_BUF[7 - ((cnt_buf) % 8)];
end
reg [OUTPUTS-1:0] cmd_data_neg;
reg [OUTPUTS-1:0] cmd_data_pos;
always @(negedge CMD_CLK_IN)
cmd_data_neg <= {OUTPUTS{cmd_data_ser}} & CONF_OUTPUT_ENABLE_CMD_CLK;
always @(posedge CMD_CLK_IN)
cmd_data_pos <= {OUTPUTS{cmd_data_ser}} & CONF_OUTPUT_ENABLE_CMD_CLK;
genvar k;
generate
for (k = 0; k < OUTPUTS; k = k + 1) begin: gen
ODDR MANCHESTER_CODE_INST (
.Q(CMD_DATA[k]),
.C(CMD_CLK_IN),
.CE(1'b1),
.D1((CONF_OUTPUT_MODE_CMD_CLK == 2'b00) ? cmd_data_pos[k] : ((CONF_OUTPUT_MODE_CMD_CLK == 2'b01) ? cmd_data_neg[k] : ((CONF_OUTPUT_MODE_CMD_CLK == 2'b10) ? ~cmd_data_pos[k] : cmd_data_pos[k]))),
.D2((CONF_OUTPUT_MODE_CMD_CLK == 2'b00) ? cmd_data_pos[k] : ((CONF_OUTPUT_MODE_CMD_CLK == 2'b01) ? cmd_data_neg[k] : ((CONF_OUTPUT_MODE_CMD_CLK == 2'b10) ? cmd_data_pos[k] : ~cmd_data_pos[k]))),
.R(1'b0),
.S(1'b0)
);
ODDR CMD_CLK_FORWARDING_INST (
.Q(CMD_CLK_OUT[k]),
.C(CMD_CLK_IN),
.CE(1'b1),
.D1(1'b1),
.D2(1'b0),
.R(CONF_DIS_CLOCK_GATE_CMD_CLK),
.S(1'b0)
);
end
endgenerate
// ready signal
always @(posedge CMD_CLK_IN)
CMD_READY <= ~next_state;
// command start flag
reg CMD_START_SIGNAL;
always @(posedge CMD_CLK_IN)
if (state == SEND && cnt_buf == CONF_START_REPEAT_CMD_CLK && CONF_DIS_CMD_PULSE_CMD_CLK == 1'b0)
CMD_START_SIGNAL <= 1'b1;
else
CMD_START_SIGNAL <= 1'b0;
reg CMD_START_SIGNAL_FF, CMD_START_SIGNAL_FF2;
always @(posedge CMD_CLK_IN) begin
CMD_START_SIGNAL_FF <= CMD_START_SIGNAL;
CMD_START_SIGNAL_FF2 <= CMD_START_SIGNAL_FF;
end
always @(posedge CMD_CLK_IN)
if (CONF_OUTPUT_MODE_CMD_CLK == 2'b00)
CMD_START_FLAG <= ~CMD_START_SIGNAL_FF2 & CMD_START_SIGNAL_FF; // delay by 1, 180 degree phase shifted data in output mode 0
else
CMD_START_FLAG <= ~CMD_START_SIGNAL_FF & CMD_START_SIGNAL;
// command start flag
reg CMD_BUSY_FLAG;
always @(posedge CMD_CLK_IN)
if (state != next_state && next_state == SEND)
CMD_BUSY_FLAG <= 1'b1;
else
CMD_BUSY_FLAG <= 1'b0;
// ready flag
reg CMD_READY_FLAG;
always @(posedge CMD_CLK_IN)
if (state != next_state && next_state == WAIT)
CMD_READY_FLAG <= 1'b1;
else
CMD_READY_FLAG <= 1'b0;
wire CMD_BUSY_FLAG_BUS_CLK;
flag_domain_crossing cmd_busy_flag_domain_crossing (
.CLK_A(CMD_CLK_IN),
.CLK_B(BUS_CLK),
.FLAG_IN_CLK_A(CMD_BUSY_FLAG),
.FLAG_OUT_CLK_B(CMD_BUSY_FLAG_BUS_CLK)
);
wire CMD_READY_FLAG_BUS_CLK;
flag_domain_crossing cmd_ready_flag_domain_crossing (
.CLK_A(CMD_CLK_IN),
.CLK_B(BUS_CLK),
.FLAG_IN_CLK_A(CMD_READY_FLAG),
.FLAG_OUT_CLK_B(CMD_READY_FLAG_BUS_CLK)
);
always @(posedge BUS_CLK)
if(RST)
CONF_READY <= 1;
else
if(CMD_BUSY_FLAG_BUS_CLK || CONF_START)
CONF_READY <= 0;
else if(CMD_READY_FLAG_BUS_CLK)
CONF_READY <= 1;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Rose-Hulman Institute of Technology
// Engineer: Adam Michael
// Date: 10/1/2015
// Summary: A basic distributed RAM.
//////////////////////////////////////////////////////////////////////////////////
module RAM40x7bits(Address, Din, Clock, Reset, WriteEnabled, Dout);
input [5:0] Address;
input [6:0] Din;
input Reset;
input Clock, WriteEnabled;
output [6:0] Dout;
reg [6:0] Data [39:0];
always@(posedge Clock or posedge Reset)
if (Reset == 1) begin // This spells out
Data[0] <= "E"; // ECE333 Fall 2015 Digital Systems
Data[1] <= "C";
Data[2] <= "E";
Data[3] <= "3";
Data[4] <= "3";
Data[5] <= "3";
Data[6] <= " ";
Data[7] <= "F";
Data[8] <= "a";
Data[9] <= "l";
Data[10] <= "l";
Data[11] <= " ";
Data[12] <= "2";
Data[13] <= "0";
Data[14] <= "1";
Data[15] <= "5";
Data[16] <= " ";
Data[17] <= "D";
Data[18] <= "i";
Data[19] <= "g";
Data[20] <= "i";
Data[21] <= "t";
Data[22] <= "a";
Data[23] <= "l";
Data[24] <= " ";
Data[25] <= "S";
Data[26] <= "y";
Data[27] <= "s";
Data[28] <= "t";
Data[29] <= "e";
Data[30] <= "m";
Data[31] <= "s";
Data[32] <= "\n";
Data[33] <= "\r";
end
else if (WriteEnabled == 1) Data[Address] <= Din;
assign Dout = Data[Address];
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* UDP ethernet frame receiver (IP frame in, UDP frame out)
*/
module udp_ip_rx
(
input wire clk,
input wire rst,
/*
* IP frame input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [7:0] s_ip_payload_axis_tdata,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* UDP frame output
*/
output wire m_udp_hdr_valid,
input wire m_udp_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [15:0] m_udp_source_port,
output wire [15:0] m_udp_dest_port,
output wire [15:0] m_udp_length,
output wire [15:0] m_udp_checksum,
output wire [7:0] m_udp_payload_axis_tdata,
output wire m_udp_payload_axis_tvalid,
input wire m_udp_payload_axis_tready,
output wire m_udp_payload_axis_tlast,
output wire m_udp_payload_axis_tuser,
/*
* Status signals
*/
output wire busy,
output wire error_header_early_termination,
output wire error_payload_early_termination
);
/*
UDP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0800) 2 octets
Version (4) 4 bits
IHL (5-15) 4 bits
DSCP (0) 6 bits
ECN (0) 2 bits
length 2 octets
identification (0?) 2 octets
flags (010) 3 bits
fragment offset (0) 13 bits
time to live (64?) 1 octet
protocol 1 octet
header checksum 2 octets
source IP 4 octets
destination IP 4 octets
options (IHL-5)*4 octets
source port 2 octets
desination port 2 octets
length 2 octets
checksum 2 octets
payload length octets
This module receives an IP frame with header fields in parallel and payload on
an AXI stream interface, decodes and strips the UDP header fields, then
produces the header fields in parallel along with the UDP payload in a
separate AXI stream.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_HEADER = 3'd1,
STATE_READ_PAYLOAD = 3'd2,
STATE_READ_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_ip_hdr;
reg store_udp_source_port_0;
reg store_udp_source_port_1;
reg store_udp_dest_port_0;
reg store_udp_dest_port_1;
reg store_udp_length_0;
reg store_udp_length_1;
reg store_udp_checksum_0;
reg store_udp_checksum_1;
reg store_last_word;
reg [2:0] hdr_ptr_reg = 3'd0, hdr_ptr_next;
reg [15:0] word_count_reg = 16'd0, word_count_next;
reg [7:0] last_word_data_reg = 8'd0;
reg m_udp_hdr_valid_reg = 1'b0, m_udp_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [3:0] m_ip_version_reg = 4'd0;
reg [3:0] m_ip_ihl_reg = 4'd0;
reg [5:0] m_ip_dscp_reg = 6'd0;
reg [1:0] m_ip_ecn_reg = 2'd0;
reg [15:0] m_ip_length_reg = 16'd0;
reg [15:0] m_ip_identification_reg = 16'd0;
reg [2:0] m_ip_flags_reg = 3'd0;
reg [12:0] m_ip_fragment_offset_reg = 13'd0;
reg [7:0] m_ip_ttl_reg = 8'd0;
reg [7:0] m_ip_protocol_reg = 8'd0;
reg [15:0] m_ip_header_checksum_reg = 16'd0;
reg [31:0] m_ip_source_ip_reg = 32'd0;
reg [31:0] m_ip_dest_ip_reg = 32'd0;
reg [15:0] m_udp_source_port_reg = 16'd0;
reg [15:0] m_udp_dest_port_reg = 16'd0;
reg [15:0] m_udp_length_reg = 16'd0;
reg [15:0] m_udp_checksum_reg = 16'd0;
reg s_ip_hdr_ready_reg = 1'b0, s_ip_hdr_ready_next;
reg s_ip_payload_axis_tready_reg = 1'b0, s_ip_payload_axis_tready_next;
reg busy_reg = 1'b0;
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
// internal datapath
reg [7:0] m_udp_payload_axis_tdata_int;
reg m_udp_payload_axis_tvalid_int;
reg m_udp_payload_axis_tready_int_reg = 1'b0;
reg m_udp_payload_axis_tlast_int;
reg m_udp_payload_axis_tuser_int;
wire m_udp_payload_axis_tready_int_early;
assign s_ip_hdr_ready = s_ip_hdr_ready_reg;
assign s_ip_payload_axis_tready = s_ip_payload_axis_tready_reg;
assign m_udp_hdr_valid = m_udp_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign m_udp_source_port = m_udp_source_port_reg;
assign m_udp_dest_port = m_udp_dest_port_reg;
assign m_udp_length = m_udp_length_reg;
assign m_udp_checksum = m_udp_checksum_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
always @* begin
state_next = STATE_IDLE;
s_ip_hdr_ready_next = 1'b0;
s_ip_payload_axis_tready_next = 1'b0;
store_ip_hdr = 1'b0;
store_udp_source_port_0 = 1'b0;
store_udp_source_port_1 = 1'b0;
store_udp_dest_port_0 = 1'b0;
store_udp_dest_port_1 = 1'b0;
store_udp_length_0 = 1'b0;
store_udp_length_1 = 1'b0;
store_udp_checksum_0 = 1'b0;
store_udp_checksum_1 = 1'b0;
store_last_word = 1'b0;
hdr_ptr_next = hdr_ptr_reg;
word_count_next = word_count_reg;
m_udp_hdr_valid_next = m_udp_hdr_valid_reg && !m_udp_hdr_ready;
error_header_early_termination_next = 1'b0;
error_payload_early_termination_next = 1'b0;
m_udp_payload_axis_tdata_int = 8'd0;
m_udp_payload_axis_tvalid_int = 1'b0;
m_udp_payload_axis_tlast_int = 1'b0;
m_udp_payload_axis_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for header
hdr_ptr_next = 3'd0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
if (s_ip_hdr_ready && s_ip_hdr_valid) begin
s_ip_hdr_ready_next = 1'b0;
s_ip_payload_axis_tready_next = 1'b1;
store_ip_hdr = 1'b1;
state_next = STATE_READ_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ_HEADER: begin
// read header state
s_ip_payload_axis_tready_next = 1'b1;
word_count_next = m_udp_length_reg - 16'd8;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
// word transfer in - store it
hdr_ptr_next = hdr_ptr_reg + 3'd1;
state_next = STATE_READ_HEADER;
case (hdr_ptr_reg)
3'h0: store_udp_source_port_1 = 1'b1;
3'h1: store_udp_source_port_0 = 1'b1;
3'h2: store_udp_dest_port_1 = 1'b1;
3'h3: store_udp_dest_port_0 = 1'b1;
3'h4: store_udp_length_1 = 1'b1;
3'h5: store_udp_length_0 = 1'b1;
3'h6: store_udp_checksum_1 = 1'b1;
3'h7: begin
store_udp_checksum_0 = 1'b1;
m_udp_hdr_valid_next = 1'b1;
s_ip_payload_axis_tready_next = m_udp_payload_axis_tready_int_early;
state_next = STATE_READ_PAYLOAD;
end
endcase
if (s_ip_payload_axis_tlast) begin
error_header_early_termination_next = 1'b1;
m_udp_hdr_valid_next = 1'b0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_READ_HEADER;
end
end
STATE_READ_PAYLOAD: begin
// read payload
s_ip_payload_axis_tready_next = m_udp_payload_axis_tready_int_early;
m_udp_payload_axis_tdata_int = s_ip_payload_axis_tdata;
m_udp_payload_axis_tvalid_int = s_ip_payload_axis_tvalid;
m_udp_payload_axis_tlast_int = s_ip_payload_axis_tlast;
m_udp_payload_axis_tuser_int = s_ip_payload_axis_tuser;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
// word transfer through
word_count_next = word_count_reg - 16'd1;
if (s_ip_payload_axis_tlast) begin
if (word_count_reg != 16'd1) begin
// end of frame, but length does not match
m_udp_payload_axis_tuser_int = 1'b1;
error_payload_early_termination_next = 1'b1;
end
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
if (word_count_reg == 16'd1) begin
store_last_word = 1'b1;
m_udp_payload_axis_tvalid_int = 1'b0;
state_next = STATE_READ_PAYLOAD_LAST;
end else begin
state_next = STATE_READ_PAYLOAD;
end
end
end else begin
state_next = STATE_READ_PAYLOAD;
end
end
STATE_READ_PAYLOAD_LAST: begin
// read and discard until end of frame
s_ip_payload_axis_tready_next = m_udp_payload_axis_tready_int_early;
m_udp_payload_axis_tdata_int = last_word_data_reg;
m_udp_payload_axis_tvalid_int = s_ip_payload_axis_tvalid && s_ip_payload_axis_tlast;
m_udp_payload_axis_tlast_int = s_ip_payload_axis_tlast;
m_udp_payload_axis_tuser_int = s_ip_payload_axis_tuser;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
s_ip_payload_axis_tready_next = 1'b1;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_ip_hdr_ready_reg <= 1'b0;
s_ip_payload_axis_tready_reg <= 1'b0;
m_udp_hdr_valid_reg <= 1'b0;
busy_reg <= 1'b0;
error_header_early_termination_reg <= 1'b0;
error_payload_early_termination_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_ip_hdr_ready_reg <= s_ip_hdr_ready_next;
s_ip_payload_axis_tready_reg <= s_ip_payload_axis_tready_next;
m_udp_hdr_valid_reg <= m_udp_hdr_valid_next;
error_header_early_termination_reg <= error_header_early_termination_next;
error_payload_early_termination_reg <= error_payload_early_termination_next;
busy_reg <= state_next != STATE_IDLE;
end
hdr_ptr_reg <= hdr_ptr_next;
word_count_reg <= word_count_next;
// datapath
if (store_ip_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
m_ip_version_reg <= s_ip_version;
m_ip_ihl_reg <= s_ip_ihl;
m_ip_dscp_reg <= s_ip_dscp;
m_ip_ecn_reg <= s_ip_ecn;
m_ip_length_reg <= s_ip_length;
m_ip_identification_reg <= s_ip_identification;
m_ip_flags_reg <= s_ip_flags;
m_ip_fragment_offset_reg <= s_ip_fragment_offset;
m_ip_ttl_reg <= s_ip_ttl;
m_ip_protocol_reg <= s_ip_protocol;
m_ip_header_checksum_reg <= s_ip_header_checksum;
m_ip_source_ip_reg <= s_ip_source_ip;
m_ip_dest_ip_reg <= s_ip_dest_ip;
end
if (store_last_word) begin
last_word_data_reg <= m_udp_payload_axis_tdata_int;
end
if (store_udp_source_port_0) m_udp_source_port_reg[ 7: 0] <= s_ip_payload_axis_tdata;
if (store_udp_source_port_1) m_udp_source_port_reg[15: 8] <= s_ip_payload_axis_tdata;
if (store_udp_dest_port_0) m_udp_dest_port_reg[ 7: 0] <= s_ip_payload_axis_tdata;
if (store_udp_dest_port_1) m_udp_dest_port_reg[15: 8] <= s_ip_payload_axis_tdata;
if (store_udp_length_0) m_udp_length_reg[ 7: 0] <= s_ip_payload_axis_tdata;
if (store_udp_length_1) m_udp_length_reg[15: 8] <= s_ip_payload_axis_tdata;
if (store_udp_checksum_0) m_udp_checksum_reg[ 7: 0] <= s_ip_payload_axis_tdata;
if (store_udp_checksum_1) m_udp_checksum_reg[15: 8] <= s_ip_payload_axis_tdata;
end
// output datapath logic
reg [7:0] m_udp_payload_axis_tdata_reg = 8'd0;
reg m_udp_payload_axis_tvalid_reg = 1'b0, m_udp_payload_axis_tvalid_next;
reg m_udp_payload_axis_tlast_reg = 1'b0;
reg m_udp_payload_axis_tuser_reg = 1'b0;
reg [7:0] temp_m_udp_payload_axis_tdata_reg = 8'd0;
reg temp_m_udp_payload_axis_tvalid_reg = 1'b0, temp_m_udp_payload_axis_tvalid_next;
reg temp_m_udp_payload_axis_tlast_reg = 1'b0;
reg temp_m_udp_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_udp_payload_int_to_output;
reg store_udp_payload_int_to_temp;
reg store_udp_payload_axis_temp_to_output;
assign m_udp_payload_axis_tdata = m_udp_payload_axis_tdata_reg;
assign m_udp_payload_axis_tvalid = m_udp_payload_axis_tvalid_reg;
assign m_udp_payload_axis_tlast = m_udp_payload_axis_tlast_reg;
assign m_udp_payload_axis_tuser = m_udp_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
store_udp_payload_int_to_output = 1'b0;
store_udp_payload_int_to_temp = 1'b0;
store_udp_payload_axis_temp_to_output = 1'b0;
if (m_udp_payload_axis_tready_int_reg) begin
// input is ready
if (m_udp_payload_axis_tready || !m_udp_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_udp_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_udp_payload_int_to_temp = 1'b1;
end
end else if (m_udp_payload_axis_tready) begin
// input is not ready, but output is ready
m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = 1'b0;
store_udp_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_udp_payload_axis_tvalid_reg <= 1'b0;
m_udp_payload_axis_tready_int_reg <= 1'b0;
temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
end
// datapath
if (store_udp_payload_int_to_output) begin
m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end else if (store_udp_payload_axis_temp_to_output) begin
m_udp_payload_axis_tdata_reg <= temp_m_udp_payload_axis_tdata_reg;
m_udp_payload_axis_tlast_reg <= temp_m_udp_payload_axis_tlast_reg;
m_udp_payload_axis_tuser_reg <= temp_m_udp_payload_axis_tuser_reg;
end
if (store_udp_payload_int_to_temp) begin
temp_m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
temp_m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
temp_m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:22:31 02/18/2016
// Design Name:
// Module Name: sesame
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sesame(
input clk,
input [7:0] sw,
input MISO,
input btnS,
input btnU,
input btnD,
input btnR,
input btnL,
output SS,
output MOSI,
output SCLK,
output reg [2:0] vgaRed,
output reg [2:0] vgaGreen,
output reg [2:1] vgaBlue,
output reg Hsync,
output reg Vsync
);
// Constants
wire [9:0] drawAreaWidth = 240;
wire [9:0] drawAreaHeight = 240;
wire [9:0] drawAreaStartX = 152 + 80;
wire [9:0] drawAreaStartY = 37;
wire [7:0] COLOR_BLACK = 0;
wire [7:0] COLOR_WHITE = 8'b11111111;
wire [7:0] COLOR_PURPLE = 8'b10000010;
wire [7:0] COLOR_PINK = 8'b11101110;
/******************************/
/*********VGA Driver***********/
/******************************/
reg clk_vga = 0;
reg counter_vga = 0;
reg [9:0] vgaX = 0; // VGA Driver's horizontal scanning position, 0-799
reg [9:0] vgaY = 0; // VGA Driver's vertical scanning position, 0-524
wire [9:0] vgaDrawX; // current X position in the draw screen for VGA Driver's scan position, 0-screenWidth
assign vgaDrawX = (vgaX - drawAreaStartX) / 2;
wire [9:0] vgaDrawY; // current Y position in the draw screen for VGA Driver's scan position, 0-screenHeight
assign vgaDrawY = (vgaY - drawAreaStartY) / 2;
// True if VGA scanning position is in the drawing region
wire inDrawArea;
assign inDrawArea = (vgaX >= drawAreaStartX && vgaX < (drawAreaStartX + (drawAreaWidth*2)) &&
vgaY >= drawAreaStartY && vgaY < (drawAreaStartY + (drawAreaHeight*2)));
// True if VGA scanning position is in the screen region
wire inScreenArea;
assign inScreenArea = (vgaX >= 152 && vgaX < 792 && vgaY >= 37 && vgaY < 517);
reg [9:0] cursorX = 100;
reg [9:0] cursorY = 100;
always @(posedge clk)
begin
counter_vga <= ~counter_vga;
end
always @(posedge counter_vga)
begin
clk_vga <= ~clk_vga;
end
// Update Hsync, Vsync, and vga X/Y
always @(posedge clk_vga)
begin
Hsync <= ~(vgaX >= 8 && vgaX < 104);
Vsync <= ~(vgaY >= 2 && vgaY < 4);
vgaX <= vgaX == 799 ? 0 : vgaX + 1; // vgaX goes 0-799 on clk
if (vgaX == 799)
vgaY <= vgaY == 524 ? 0 : vgaY + 1; // vgaY goes 0-524 on ~HSync and clk
end
// Update VGA RGB
always @(posedge clk_vga)
begin
// Feed RGB black when outside screen area
if (~inScreenArea)
begin
update_VGA_RGB(COLOR_BLACK);
end
// When in the draw area, use the pixel map
else if (inDrawArea)
begin
//drawing stamp cursor
if (current_tool == TOOL_STAMP && vgaDrawX >= cursorX - 15 && vgaDrawX < cursorX + 15 && vgaDrawY >= cursorY - 15 && vgaDrawY < cursorY + 15)
begin
stamp_menu_addr <= (vgaDrawX - (cursorX - 15)) + ((vgaDrawY - (cursorY - 15)) * 30);
if (stamp_menu_pixel != 8'b00000011 )
update_VGA_RGB(stamp_menu_pixel);
else
begin
pmop_addr <= vgaDrawX + vgaDrawY * drawAreaWidth;
update_VGA_RGB(pmop_pixel);
end
end
else if (vgaDrawX >= cursorX - pencil_size / 2 && vgaDrawX < cursorX + pencil_size / 2 && vgaDrawY >= cursorY - pencil_size / 2 && vgaDrawY < cursorY + pencil_size / 2)
begin
if (vgaDrawX >= cursorX - (pencil_size-1) / 2 && vgaDrawX < cursorX + (pencil_size-1) / 2 && vgaDrawY >= cursorY - (pencil_size-1) / 2 && vgaDrawY < cursorY + (pencil_size-1) / 2)
update_VGA_RGB(current_tool == TOOL_PENCIL ? sw : COLOR_PINK);
else
update_VGA_RGB(COLOR_BLACK);
end
else
begin
pmop_addr <= vgaDrawX + vgaDrawY * drawAreaWidth;
update_VGA_RGB(pmop_pixel);
end
end
// When outside the draw area, have other logic (draw menus?)
else
begin
// Possibly use vgaX and vgaY to draw menus, with another module to get menu pixels?
update_VGA_RGB(sw);
end
end
// Take in 8 bit color and set VGA colors accordingly
task update_VGA_RGB;
input [7:0] color;
begin
vgaRed = color[7:5];
vgaGreen = color[4:2];
vgaBlue = color[1:0];
end
endtask
/******************************/
/*******Cursor Control*********/
/******************************/
reg [31:0] counter_cursor = 0;
reg clk_cursor = 0; // Ticks at 30 Hz
always @(posedge clk)
begin
counter_cursor <= (counter_cursor == 1666666) ? 0 : counter_cursor + 1;
if (counter_cursor == 0)
clk_cursor <= ~clk_cursor;
end
always @(posedge clk_cursor)
begin
if (joystick_x < 150 && cursorX < drawAreaWidth - 2) cursorX <= cursorX + 2;
else if (joystick_x < 400 && cursorX < drawAreaWidth - 1) cursorX <= cursorX + 1;
if (joystick_x > 850 && cursorX > 2) cursorX <= cursorX - 2;
else if (joystick_x > 600 && cursorX > 1) cursorX <= cursorX - 1;
if (joystick_y < 150 && cursorY > 2) cursorY <= cursorY - 2;
else if (joystick_y < 400 && cursorY > 1) cursorY <= cursorY - 1;
if (joystick_y > 850 && cursorY < drawAreaHeight - 2) cursorY <= cursorY + 2;
else if (joystick_y > 600 && cursorY < drawAreaHeight - 1) cursorY <= cursorY + 1;
end
/******************************/
/********Tool Control**********/
/******************************/
reg [5:0] current_tool = 2;
reg [5:0] old_tool = 0; // Used to go back to current_tool after resetting screen
wire [5:0] TOOL_NONE = 0;
wire [5:0] TOOL_RESET = 1;
wire [5:0] TOOL_PENCIL = 2;
wire [5:0] TOOL_ERASER = 3;
wire [5:0] TOOL_STAMP = 4;
reg is_resetting = 0;
reg is_tool_on = 0;
reg [31:0] reset_counter = 0;
reg [31:0] pencil_size = 4;
reg [31:0] pencil_x = 0;
reg [31:0] pencil_y = 0;
reg [31:0] stamp_size = 30;
reg [31:0] stamp_x = 0;
reg [31:0] stamp_y = 0;
reg [31:0] current_stamp = 4;
reg [31:0] counter_debounce = 0;
wire clk_debounce;
assign clk_debounce = counter_debounce == 166666;
always @(posedge clk)
begin
counter_debounce <= counter_debounce == 166666 ? 0 : counter_debounce + 1;
end
reg btnRdb = 0;
reg btnLdb = 0;
reg btnUdb = 0;
reg btnDdb = 0;
always @(posedge clk_debounce)
begin
btnRdb <= btnR;
btnLdb <= btnL;
btnUdb <= btnU;
btnDdb <= btnD;
end
wire comboLR = btnRdb || btnLdb;
always @(posedge comboLR)
begin
if (btnRdb)
begin
if (current_tool == TOOL_STAMP)
begin
current_stamp <= current_stamp == 6 ? 0 :current_stamp + 1;
end
else
begin
case (pencil_size)
2: pencil_size <= 4;
4: pencil_size <= 6;
endcase
end
end
if (btnLdb)
begin
if (current_tool == TOOL_STAMP)
begin
current_stamp <= current_stamp == 0 ? 6 :current_stamp - 1;
end
else
begin
case (pencil_size)
4: pencil_size <= 2;
6: pencil_size <= 4;
endcase
end
end
end
wire comboUD = btnUdb || btnDdb;
always @(posedge comboUD)
begin
if (btnUdb)
begin
if (current_tool == TOOL_PENCIL) current_tool <= TOOL_STAMP;
if (current_tool == TOOL_ERASER) current_tool <= TOOL_PENCIL;
if (current_tool == TOOL_STAMP) current_tool <= TOOL_ERASER;
end
if (btnDdb)
begin
if (current_tool == TOOL_PENCIL) current_tool <= TOOL_ERASER;
if (current_tool == TOOL_ERASER) current_tool <= TOOL_STAMP;
if (current_tool == TOOL_STAMP) current_tool <= TOOL_PENCIL;
end
end
always @(posedge clk)
begin
// Set current tool
if (btnS && current_tool != TOOL_RESET)
begin
is_resetting <= 1;
reset_counter <= 0;
end
else if (joystick_btn_left)
is_tool_on <= 1;
if (is_resetting)
begin
if (reset_counter == drawAreaWidth * drawAreaHeight)
begin
is_resetting <= 0;
wea <= 0;
end
else
begin
wea <= 1;
dina <= COLOR_WHITE;
pmin_addr <= reset_counter;
reset_counter <= reset_counter + 1;
end
end
if (is_tool_on && current_tool == TOOL_PENCIL)
begin
if (pencil_y == pencil_size)
begin
is_tool_on <= 0;
wea <= 0;
pencil_x <= 0;
pencil_y <= 0;
end
else
begin
wea <= 1;
dina <= sw;
pmin_addr <= (cursorX + pencil_x - pencil_size / 2) + (cursorY + pencil_y - pencil_size / 2) * drawAreaWidth;
if (pencil_x == pencil_size - 1)
begin
pencil_x <= 0;
pencil_y <= pencil_y + 1;
end
else
pencil_x <= pencil_x + 1;
end
end
if (is_tool_on && current_tool == TOOL_ERASER)
begin
if (pencil_y == pencil_size)
begin
is_tool_on <= 0;
wea <= 0;
pencil_x <= 0;
pencil_y <= 0;
end
else
begin
wea <= 1;
dina <= COLOR_WHITE;
pmin_addr <= (cursorX + pencil_x - pencil_size / 2) + (cursorY + pencil_y - pencil_size / 2) * drawAreaWidth;
if (pencil_x == pencil_size - 1)
begin
pencil_x <= 0;
pencil_y <= pencil_y + 1;
end
else
pencil_x <= pencil_x + 1;
end
end
if (is_tool_on && current_tool == TOOL_STAMP)
begin
if (stamp_y == stamp_size)
begin
is_tool_on <= 0;
wea <= 0;
stamp_x <= 0;
stamp_y <= 0;
stamp_draw_addr <= 0;
end
else
begin
stamp_draw_addr <= (stamp_x + (stamp_y * stamp_size));
wea <= stamp_draw_pixel != 8'b00000011;
dina <= stamp_draw_pixel;
pmin_addr <= (cursorX + stamp_x - stamp_size / 2) + (cursorY + stamp_y - stamp_size / 2) * drawAreaWidth;
if (stamp_x == stamp_size)
begin
stamp_x <= 0;
stamp_y <= stamp_y + 1;
end
else
stamp_x <= stamp_x + 1;
end
end
end
/******************************/
/*********Pixel Map ***********/
/******************************/
reg [15:0] pmop_addr;
wire [7:0] pmop_pixel;
reg wea;
reg [15 : 0] pmin_addr;
reg [7 : 0] dina;
pixel_map pixel_map(
.clka(clk), // input clka
.wea(wea), // input [0 : 0] wea
.addra(pmin_addr), // input [15 : 0] addra
.dina(dina), // input [7 : 0] dina
.clkb(clk), // input clkb
.addrb(pmop_addr), // input [15 : 0] addrb
.doutb(pmop_pixel) // output [7 : 0] doutb
);
reg [9:0] stamp_draw_addr = 0;
wire [7:0] stamp_draw_pixel;
reg [9:0] stamp_menu_addr = 0;
wire [7:0] stamp_menu_pixel;
assign stamp_draw_pixel =
current_stamp == 0 ? stamp_draw_pixel_0 :
current_stamp == 1 ? stamp_draw_pixel_1 :
current_stamp == 2 ? stamp_draw_pixel_2 :
current_stamp == 3 ? stamp_draw_pixel_3 :
current_stamp == 4 ? stamp_draw_pixel_4 :
current_stamp == 5 ? stamp_draw_pixel_5 : stamp_draw_pixel_6;
assign stamp_menu_pixel =
current_stamp == 0 ? stamp_menu_pixel_0 :
current_stamp == 1 ? stamp_menu_pixel_1 :
current_stamp == 2 ? stamp_menu_pixel_2 :
current_stamp == 3 ? stamp_menu_pixel_3 :
current_stamp == 4 ? stamp_menu_pixel_4 :
current_stamp == 5 ? stamp_menu_pixel_5 : stamp_menu_pixel_6;
wire [7:0] stamp_draw_pixel_0;
wire [7:0] stamp_menu_pixel_0;
stamp_matt stamp0 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_0), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_0) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_1;
wire [7:0] stamp_menu_pixel_1;
stamp_penguin stamp1 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_1), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_1) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_2;
wire [7:0] stamp_menu_pixel_2;
stamp_jellyfish stamp2 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_2), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_2) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_3;
wire [7:0] stamp_menu_pixel_3;
stamp_cat stamp3 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_3), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_3) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_4;
wire [7:0] stamp_menu_pixel_4;
stamp_taco stamp4 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_4), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_4) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_5;
wire [7:0] stamp_menu_pixel_5;
stamp_mushroom stamp5 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_5), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_5) // output [7 : 0] doutb
);
wire [7:0] stamp_draw_pixel_6;
wire [7:0] stamp_menu_pixel_6;
stamp_heart stamp6 (
.clka(clk), // input clka
.addra(stamp_draw_addr), // input [9 : 0] addra
.douta(stamp_draw_pixel_6), // output [7 : 0] douta
.clkb(clk), // input clkb
.addrb(stamp_menu_addr), // input [9 : 0] addrb
.doutb(stamp_menu_pixel_6) // output [7 : 0] doutb
);
/******************************/
/*********Joystick ***********/
/******************************/
wire SS; // Active low
wire MOSI; // Data transfer from master to slave
wire SCLK; // Serial clock that controls communication
assign MOSI = 0;
// Data read from PmodJSTK
wire [39:0] jstkData;
wire [9 : 0] joystick_y = {jstkData[9:8], jstkData[23:16]};
wire [9 : 0] joystick_x = {jstkData[25:24], jstkData[39:32]};
wire joystick_btn_right = jstkData[1];
wire joystick_btn_left = jstkData[2];
joy joy(
.CLK(clk),
.sndRec(clk_cursor),
.MISO(MISO),
.SS(SS),
.SCLK(SCLK),
.DOUT(jstkData)
);
endmodule
|
//-----------------------------------------------------
// PROYECTO 1 : SD HOST
// Archivo : probadorPhysical.v
// Descripcion : generador de estimulos para el bloque de capa fisica de DATA
// Estudiante : Mario Castresana Avendaño - A41267
//-----------------------------------------------------
module probador(
output reg SD_CLK,
output reg RESET_L,
output reg strobe_IN_DATA_Phy,
output reg ack_IN_DATA_Phy,
output reg [15:0] timeout_Reg_DATA_Phy,
output reg [3:0] blocks_DATA_Phy,
output reg writeRead_DATA_Phy,
output reg multiple_DATA_Phy,
output reg idle_in_DATA_Phy,
output reg transmission_complete_PS_Phy,
output reg reception_complete_SP_Phy,
output reg [31:0] data_read_SP_Phy,
output reg [31:0] dataFromFIFO_FIFO_Phy
);
// Generar CLK
always
begin
#10 SD_CLK= ! SD_CLK;
end
//Generar pruebas
initial begin
//dumps
$dumpfile("PhysicalTest.vcd");
$dumpvars(0,testbench);
// Initialize Inputs
SD_CLK = 0;
writeRead_DATA_Phy = 1;
strobe_IN_DATA_Phy = 1;
ack_IN_DATA_Phy = 0;
timeout_Reg_DATA_Phy = 16'd100;
blocks_DATA_Phy = 4'b1111;
multiple_DATA_Phy = 0;
idle_in_DATA_Phy = 0;
transmission_complete_PS_Phy = 0;
reception_complete_SP_Phy = 0;
data_read_SP_Phy = 32'hCAFECAFE;
dataFromFIFO_FIFO_Phy = 32'hCAFECAFE;
//pulso de RESET_L
#50
RESET_L = 1;
#10
RESET_L = 0;
#30
RESET_L = 1;
//Aqui ya pasa a IDLE
$display("Aqui ya pasa a IDLE");
//pasamos a fifo read
//pasamos al estado LOAD write
$display("Aqui ya pasa a load write, luego a send y wait response");
#100
reception_complete_SP_Phy = 1;
#30
ack_IN_DATA_Phy = 1;
$display("manda el ack y devuelta a IDLE");
#200
$display("-----FIN------");
$finish(2);
end
endmodule
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Thu Mar 31 18:01:07 2016
//Host : lubuntu running 64-bit Ubuntu 15.04
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(AXI_En,
En,
FrameSize,
M_AXIS_tdata,
M_AXIS_tlast,
M_AXIS_tready,
M_AXIS_tstrb,
M_AXIS_tvalid,
S_AXIS_tdata,
S_AXIS_tlast,
S_AXIS_tready,
S_AXIS_tstrb,
S_AXIS_tvalid,
m_axis_aclk,
m_axis_aresetn);
input AXI_En;
input En;
input [7:0]FrameSize;
output [31:0]M_AXIS_tdata;
output M_AXIS_tlast;
input M_AXIS_tready;
output [3:0]M_AXIS_tstrb;
output M_AXIS_tvalid;
input [31:0]S_AXIS_tdata;
input S_AXIS_tlast;
output S_AXIS_tready;
input [3:0]S_AXIS_tstrb;
input S_AXIS_tvalid;
input m_axis_aclk;
input m_axis_aresetn;
wire AXI_En;
wire En;
wire [7:0]FrameSize;
wire [31:0]M_AXIS_tdata;
wire M_AXIS_tlast;
wire M_AXIS_tready;
wire [3:0]M_AXIS_tstrb;
wire M_AXIS_tvalid;
wire [31:0]S_AXIS_tdata;
wire S_AXIS_tlast;
wire S_AXIS_tready;
wire [3:0]S_AXIS_tstrb;
wire S_AXIS_tvalid;
wire m_axis_aclk;
wire m_axis_aresetn;
design_1 design_1_i
(.AXI_En(AXI_En),
.En(En),
.FrameSize(FrameSize),
.M_AXIS_tdata(M_AXIS_tdata),
.M_AXIS_tlast(M_AXIS_tlast),
.M_AXIS_tready(M_AXIS_tready),
.M_AXIS_tstrb(M_AXIS_tstrb),
.M_AXIS_tvalid(M_AXIS_tvalid),
.S_AXIS_tdata(S_AXIS_tdata),
.S_AXIS_tlast(S_AXIS_tlast),
.S_AXIS_tready(S_AXIS_tready),
.S_AXIS_tstrb(S_AXIS_tstrb),
.S_AXIS_tvalid(S_AXIS_tvalid),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTN_SYMBOL_V
`define SKY130_FD_SC_MS__DLRTN_SYMBOL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTN_SYMBOL_V
|
`include "hrfp_defs.vh"
// This module is not used anymore and may not function
// correctly. This is kept here for historical reasons as I may want
// to refer back to this module when implementing double precision
// HRFP_16 numbers.
module hrfp_normalize
#(parameter PIPELINESTAGES=5)
(input wire clk,
input wire [`MSBBIT:0] result_4,
input wire [30:0] mantissa_4,
input wire [7:0] zeroesmask_4,
output reg [30:0] mantissa_5,
output reg [`MSBBIT:0] result_5);
(* KEEP = "SOFT" *) reg [7:0] zeroes;
(* KEEP = "SOFT" *) reg [2:0] expdiff;
(* KEEP = "SOFT" *) reg [1:0] expdiff_mux0;
(* KEEP = "SOFT" *) reg [1:0] expdiff_mux1;
reg expdiff_carryin;
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp0 = (mantissa_4[30:25] == 6'b011111);
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp1 = (mantissa_4[24:19] == 6'b111111);
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp2 = (mantissa_4[18:13] == 6'b111111);
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp3 = (mantissa_4[12:7] == 6'b111111);
(* KEEP = "SOFT" *) wire rounding_will_overflow_tmp4 = (mantissa_4[6:1] == 6'b111111);
wire rounding_will_overflow_tmp5 = (mantissa_4[0] == 1'b1);
(* KEEP = "SOFT" *) wire rounding_will_overflow = rounding_will_overflow_tmp0 &&
rounding_will_overflow_tmp1 &&
rounding_will_overflow_tmp2 &&
rounding_will_overflow_tmp3 &&
rounding_will_overflow_tmp4 &&
rounding_will_overflow_tmp5;
wire overflow_bit = mantissa_4[30];
initial begin
$display("ERROR ERROR ERROR: This file is deprecated and only kept for historical reasons.");
$stop;
end
/*
rounding_will_overflow = 0;
if(mantissa_4[30:5] == 26'h1ffffff) begin
rounding_will_overflow = 1;
end
*/
// (* KEEP = "SOFT" *) reg iszero;
(* KEEP = "SOFT" *) wire iszero = (mantissa_4 == 0);
always @* begin
zeroes[0] = ~|mantissa_4[1:0] && zeroesmask_4[0];
zeroes[1] = ~|mantissa_4[5:2] && zeroesmask_4[1];
zeroes[2] = ~|mantissa_4[9:6] && zeroesmask_4[2];
zeroes[3] = ~|mantissa_4[13:10] && zeroesmask_4[3];
zeroes[4] = ~|mantissa_4[17:14] && zeroesmask_4[4];
zeroes[5] = ~|mantissa_4[21:18] && zeroesmask_4[5];
zeroes[6] = ~|mantissa_4[25:22] && zeroesmask_4[6];
zeroes[7] = ~|mantissa_4[29:26] && zeroesmask_4[7]; // 8 LUTs (confirmed!)
// iszero = 0;
expdiff = 0;
// if(zeroes == 8'b11111111) begin
// iszero = 1;
// end
casez(zeroes)
8'b1111111?: expdiff = 3'b111; // No need to check for 8'b11111111 since iszero is one in that case!
8'b1111110?: expdiff = 3'b110;
8'b111110??: expdiff = 3'b101;
8'b11110???: expdiff = 3'b100;
8'b1110????: expdiff = 3'b011;
8'b110?????: expdiff = 3'b010;
8'b10??????: expdiff = 3'b001;
8'b0???????: expdiff = 3'b000;
endcase // casez (zeroes) // 4 LUTs (?)
casez({overflow_bit,zeroes[3:0]})
5'b1????: expdiff_mux1 = 3;
5'b0111?: expdiff_mux1 = 3;
5'b0110?: expdiff_mux1 = 2;
5'b010??: expdiff_mux1 = 1;
5'b00???: expdiff_mux1 = 0;
endcase // casez (zeroes) // 4 LUTs (?)
casez(zeroes[7:4])
4'b111?: expdiff_mux0 = 3;
4'b110?: expdiff_mux0 = 2;
4'b10??: expdiff_mux0 = 1;
4'b0???: expdiff_mux0 = 0;
endcase // casez (zeroes) // 4 LUTs (?)
expdiff_carryin = overflow_bit;
// if(mantissa_4[30] ) begin
// expdiff = 0; // In this case, expdiff will be ignored.
// end
// In the code below, 30:5 is used to check for rounded
// overflow. expdiff_carryin will be of course be set in this
// case as well. (Both because mantissa_4[30] is set
// (c.f. above) and because the following condition is true.
if(mantissa_4[29:5] == 25'h1ffffff) begin
// expdiff = 0; // Expdiff value doesn't matter in this case!
expdiff_carryin = 1;
end
end // always @ *
(* KEEP = "SOFT" *) reg [30:0] mantissa_mux_0,mantissa_mux_1;
wire [30:0] mantissa_shifted;
wire [30:0] overflow_mantissa = {3'b000, mantissa_4[30:5], |mantissa_4[4:0]};
wire [30:0] overflow_or_normal_mantissa = overflow_bit ? overflow_mantissa : {mantissa_4[1:0], 28'b0};
always @* begin
case(expdiff_mux1[1:0])
3: mantissa_mux_1 = overflow_mantissa; // Corresponds to expdiff = 7
2: mantissa_mux_1 = {mantissa_4[5:0], 24'b0}; // Corresponds to expdiff = 6
1: mantissa_mux_1 = {mantissa_4[9:0], 20'b0}; // Corresponds to expdiff = 5
0: mantissa_mux_1 = {mantissa_4[13:0], 16'b0}; // Corresponds to expdiff = 4
endcase // case (expdiff[1:0])
case(expdiff_mux0[1:0])
3: mantissa_mux_0 = {mantissa_4[17:0], 12'b0}; // Corresponds to expdiff = 3
2: mantissa_mux_0 = {mantissa_4[21:0], 8'b0}; // Corresponds to expdiff = 2
1: mantissa_mux_0 = {mantissa_4[25:0], 4'b0}; // Corresponds to expdiff = 1
0: mantissa_mux_0 = {mantissa_4[29:0]}; // Corresponds to expdiff = 0
endcase // casez (expdiff[1:0])
end // always @ *
/*
// FIXME - very wasteful since this mux is only needed in a few
// cases due to the large number of zeroes in the expression above.
generate
genvar i;
for(i=0; i <= 30; i = i + 1) begin : f7mux
MUXF7 f7(.I0(mantissa_mux_0[i]),
.I1(mantissa_mux_1[i]),
.S(expdiff[2]),
.O(mantissa_shifted[i]));
end
endgenerate
*/
assign mantissa_shifted = (expdiff[2] || overflow_bit) ? mantissa_mux_1 : mantissa_mux_0;
wire [`EXPONENTBITS:0] expdiff_tmp = expdiff_carryin ? 8'b11111111 : expdiff;
always @(posedge clk) begin
result_5 <= result_4;
// $display("Zeroes is %x", zeroes);
// Note: the case where zeroes == 8'b11111111 is handled implicitly since
// the mantissa is all zero in this case. (That is, mantissa_5 will be set to 0,
// regardless of the setting of expdiff!)
// casez (expdiff)
// 7: mantissa_5 <= {mantissa_4[1:0], 28'b0};
// 6: mantissa_5 <= {mantissa_4[5:0], 24'b0};
// 5: mantissa_5 <= {mantissa_4[9:0], 20'b0};
// 4: mantissa_5 <= {mantissa_4[13:0], 16'b0};
// 3: mantissa_5 <= {mantissa_4[17:0], 12'b0};
// 2: mantissa_5 <= {mantissa_4[21:0], 8'b0};
// 1: mantissa_5 <= {mantissa_4[25:0], 4'b0};
// 0: mantissa_5 <= {mantissa_4[29:0]};
// endcase // casez (zeroes)
mantissa_5 <= mantissa_shifted;
// 4-1 mux: 1 LUT
// 8-1 mux: 2 LUT
// 31 bit 8-1 mux: 62 LUTs (less due to use of reset input!)
// This is the same as the statement above but tweaked so that we hopefully get only one adder.
result_5`EXPONENT <= result_4`EXPONENT - expdiff_tmp;
// if(iszero) result_5`EXPSPEC <= 0;
// if(overflow_bit) begin
// result_5`EXPONENT <= result_4`EXPONENT + 1; // This might also overflow but is also handled below during overflow check.
// mantissa_5 <= {3'b000, mantissa_4[30:5], |mantissa_4[4:0] }; // Oops, a 9-1 mux!
// end
// Detect if rounding operation will overflow!
// Note: Since this is an odd number there is no need to check/generate sticky bit (e.g. |mantissa_4[4:0]
if(rounding_will_overflow) begin
mantissa_5 <= {4'b0001, 26'h0}; // Reset/Set input could be used for this...
// result_5`EXPONENT <= result_4`EXPONENT + 1; // Might overflow but this is handled below during the overflow check where the INF bit will be set.
end
// OVERFLOW!
if(result_4`EXPONENT == 63+8'b01000000) begin
// A thorough testing is needed to determine if this works correctly or not.
if(mantissa_4[29] && !result_4`SPECIAL) begin
result_5`IS_INF_OR_NAN <= 1;
result_5`HRFP_IS_NAN <= 0;
end
end
end // always @ (posedge clk)
endmodule
|
module psdos (
input Rx,
input CLKOUT,
output reg Rx_error,
output [7:0] DATA,
output reg DONE
);
reg [8:0] regis;
reg [7:0] regis0;
reg [3:0] i;
reg [3:0] j;
reg [1:0] k;
reg init;
reg DoIt;
//reg NoDoIt;
//reg MakeIt=(DoIt && ~NoDoIt);
initial
begin
i=0;
j=0;
init=0;
regis=0;
regis0=0;
Rx_error=0;
DONE=0;
k=0;
DoIt=1;
//NoDoIt=0;
end
always@(posedge CLKOUT)
begin
if(!Rx&&!i)
begin
init<=1;
DONE=0;
Rx_error=0;
end
// lectura //
// lectura //
// lectura //
if(init)
begin
regis[i]=Rx;
i<=i+1;
if(regis[i]&&(i<8))
begin
j=j+1;
end
end
//=======
if(DoIt)
begin
k<=k+1;
end
//=======
// finalizar //
// finalizar //
// finalizar //
if(i==9)
begin
if(((j%2)&&(regis[8]))||(!(j%2)&&(!regis[8])))
begin
Rx_error=0;
regis0={regis[7:0]};
DONE=1;
end
else
begin
Rx_error=1;
regis0=0;
DONE=0;
end
j=0;
i<=0;
init=0;
end
end
assign DATA=regis0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__NOR2_FUNCTIONAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_2_V
`define SKY130_FD_SC_HDLL__O21BAI_2_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_2_V
|
// ghrd_10as066n2_fpga_m_altera_jtag_avalon_master_171_wqhllki.v
// This file was auto-generated from altera_jtag_avalon_master_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_fpga_m_altera_jtag_avalon_master_171_wqhllki #(
parameter USE_PLI = 0,
parameter PLI_PORT = 50000,
parameter FIFO_DEPTHS = 2
) (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (USE_PLI != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_pli_check ( .error(1'b1) );
end
if (PLI_PORT != 50000)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
pli_port_check ( .error(1'b1) );
end
if (FIFO_DEPTHS != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.EXPORT_JTAG (0),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // input, width = 1, clock.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // output, width = 8, src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // output, width = 1, .valid
.sink_data (p2b_out_bytes_stream_data), // input, width = 8, sink.data
.sink_valid (p2b_out_bytes_stream_valid), // input, width = 1, .valid
.sink_ready (p2b_out_bytes_stream_ready), // output, width = 1, .ready
.resetrequest (master_reset_reset), // output, width = 1, resetrequest.reset
.source_ready (1'b1), // (terminated),
.mgmt_valid (), // (terminated),
.mgmt_channel (), // (terminated),
.mgmt_data (), // (terminated),
.jtag_tck (1'b0), // (terminated),
.jtag_tms (1'b0), // (terminated),
.jtag_tdi (1'b0), // (terminated),
.jtag_tdo (), // (terminated),
.jtag_ena (1'b0), // (terminated),
.jtag_usr1 (1'b0), // (terminated),
.jtag_clr (1'b0), // (terminated),
.jtag_clrn (1'b0), // (terminated),
.jtag_state_tlr (1'b0), // (terminated),
.jtag_state_rti (1'b0), // (terminated),
.jtag_state_sdrs (1'b0), // (terminated),
.jtag_state_cdr (1'b0), // (terminated),
.jtag_state_sdr (1'b0), // (terminated),
.jtag_state_e1dr (1'b0), // (terminated),
.jtag_state_pdr (1'b0), // (terminated),
.jtag_state_e2dr (1'b0), // (terminated),
.jtag_state_udr (1'b0), // (terminated),
.jtag_state_sirs (1'b0), // (terminated),
.jtag_state_cir (1'b0), // (terminated),
.jtag_state_sir (1'b0), // (terminated),
.jtag_state_e1ir (1'b0), // (terminated),
.jtag_state_pir (1'b0), // (terminated),
.jtag_state_e2ir (1'b0), // (terminated),
.jtag_state_uir (1'b0), // (terminated),
.jtag_ir_in (3'b000), // (terminated),
.jtag_irq (), // (terminated),
.jtag_ir_out () // (terminated),
);
ghrd_10as066n2_fpga_m_timing_adapter_171_xf5weri timing_adt (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // input, width = 8, in.data
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // input, width = 1, .valid
.out_data (timing_adt_out_data), // output, width = 8, out.data
.out_valid (timing_adt_out_valid), // output, width = 1, .valid
.out_ready (timing_adt_out_ready) // input, width = 1, .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // input, width = 1, clk.clk
.reset (rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset
.in_data (timing_adt_out_data), // input, width = 8, in.data
.in_valid (timing_adt_out_valid), // input, width = 1, .valid
.in_ready (timing_adt_out_ready), // output, width = 1, .ready
.out_data (fifo_out_data), // output, width = 8, out.data
.out_valid (fifo_out_valid), // output, width = 1, .valid
.out_ready (fifo_out_ready), // input, width = 1, .ready
.csr_address (2'b00), // (terminated),
.csr_read (1'b0), // (terminated),
.csr_write (1'b0), // (terminated),
.csr_readdata (), // (terminated),
.csr_writedata (32'b00000000000000000000000000000000), // (terminated),
.almost_full_data (), // (terminated),
.almost_empty_data (), // (terminated),
.in_startofpacket (1'b0), // (terminated),
.in_endofpacket (1'b0), // (terminated),
.out_startofpacket (), // (terminated),
.out_endofpacket (), // (terminated),
.in_empty (1'b0), // (terminated),
.out_empty (), // (terminated),
.in_error (1'b0), // (terminated),
.out_error (), // (terminated),
.in_channel (1'b0), // (terminated),
.out_channel () // (terminated),
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // output, width = 8, out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // input, width = 1, .ready
.out_valid (b2p_out_packets_stream_valid), // output, width = 1, .valid
.out_data (b2p_out_packets_stream_data), // output, width = 8, .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // output, width = 1, .endofpacket
.in_ready (fifo_out_ready), // output, width = 1, in_bytes_stream.ready
.in_valid (fifo_out_valid), // input, width = 1, .valid
.in_data (fifo_out_data) // input, width = 8, .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // output, width = 1, in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // input, width = 1, .valid
.in_data (p2b_adapter_out_data), // input, width = 8, .data
.in_channel (p2b_adapter_out_channel), // input, width = 8, .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // input, width = 1, .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // input, width = 1, out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // output, width = 1, .valid
.out_data (p2b_out_bytes_stream_data) // output, width = 8, .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // input, width = 1, out_stream.ready
.out_valid (transacto_out_stream_valid), // output, width = 1, .valid
.out_data (transacto_out_stream_data), // output, width = 8, .data
.out_startofpacket (transacto_out_stream_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // output, width = 1, .endofpacket
.in_ready (b2p_adapter_out_ready), // output, width = 1, in_stream.ready
.in_valid (b2p_adapter_out_valid), // input, width = 1, .valid
.in_data (b2p_adapter_out_data), // input, width = 8, .data
.in_startofpacket (b2p_adapter_out_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // input, width = 1, .endofpacket
.address (master_address), // output, width = 32, avalon_master.address
.readdata (master_readdata), // input, width = 32, .readdata
.read (master_read), // output, width = 1, .read
.write (master_write), // output, width = 1, .write
.writedata (master_writedata), // output, width = 32, .writedata
.waitrequest (master_waitrequest), // input, width = 1, .waitrequest
.readdatavalid (master_readdatavalid), // input, width = 1, .readdatavalid
.byteenable (master_byteenable) // output, width = 4, .byteenable
);
ghrd_10as066n2_fpga_m_channel_adapter_171_2swajja b2p_adapter (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
.in_data (b2p_out_packets_stream_data), // input, width = 8, in.data
.in_valid (b2p_out_packets_stream_valid), // input, width = 1, .valid
.in_ready (b2p_out_packets_stream_ready), // output, width = 1, .ready
.in_startofpacket (b2p_out_packets_stream_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // input, width = 1, .endofpacket
.in_channel (b2p_out_packets_stream_channel), // input, width = 8, .channel
.out_data (b2p_adapter_out_data), // output, width = 8, out.data
.out_valid (b2p_adapter_out_valid), // output, width = 1, .valid
.out_ready (b2p_adapter_out_ready), // input, width = 1, .ready
.out_startofpacket (b2p_adapter_out_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // output, width = 1, .endofpacket
);
ghrd_10as066n2_fpga_m_channel_adapter_171_vh2yu6y p2b_adapter (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
.in_data (transacto_out_stream_data), // input, width = 8, in.data
.in_valid (transacto_out_stream_valid), // input, width = 1, .valid
.in_ready (transacto_out_stream_ready), // output, width = 1, .ready
.in_startofpacket (transacto_out_stream_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // input, width = 1, .endofpacket
.out_data (p2b_adapter_out_data), // output, width = 8, out.data
.out_valid (p2b_adapter_out_valid), // output, width = 1, .valid
.out_ready (p2b_adapter_out_ready), // input, width = 1, .ready
.out_startofpacket (p2b_adapter_out_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // output, width = 1, .endofpacket
.out_channel (p2b_adapter_out_channel) // output, width = 8, .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // input, width = 1, reset_in0.reset
.clk (clk_clk), // input, width = 1, clk.clk
.reset_out (rst_controller_reset_out_reset), // output, width = 1, reset_out.reset
.reset_req (), // (terminated),
.reset_req_in0 (1'b0), // (terminated),
.reset_in1 (1'b0), // (terminated),
.reset_req_in1 (1'b0), // (terminated),
.reset_in2 (1'b0), // (terminated),
.reset_req_in2 (1'b0), // (terminated),
.reset_in3 (1'b0), // (terminated),
.reset_req_in3 (1'b0), // (terminated),
.reset_in4 (1'b0), // (terminated),
.reset_req_in4 (1'b0), // (terminated),
.reset_in5 (1'b0), // (terminated),
.reset_req_in5 (1'b0), // (terminated),
.reset_in6 (1'b0), // (terminated),
.reset_req_in6 (1'b0), // (terminated),
.reset_in7 (1'b0), // (terminated),
.reset_req_in7 (1'b0), // (terminated),
.reset_in8 (1'b0), // (terminated),
.reset_req_in8 (1'b0), // (terminated),
.reset_in9 (1'b0), // (terminated),
.reset_req_in9 (1'b0), // (terminated),
.reset_in10 (1'b0), // (terminated),
.reset_req_in10 (1'b0), // (terminated),
.reset_in11 (1'b0), // (terminated),
.reset_req_in11 (1'b0), // (terminated),
.reset_in12 (1'b0), // (terminated),
.reset_req_in12 (1'b0), // (terminated),
.reset_in13 (1'b0), // (terminated),
.reset_req_in13 (1'b0), // (terminated),
.reset_in14 (1'b0), // (terminated),
.reset_req_in14 (1'b0), // (terminated),
.reset_in15 (1'b0), // (terminated),
.reset_req_in15 (1'b0) // (terminated),
);
endmodule
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