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module vga_bw
(
CLOCK_PIXEL,
RESET,
PIXEL,
PIXEL_H,
PIXEL_V,
VGA_RED,
VGA_GREEN,
VGA_BLUE,
VGA_HS,
VGA_VS
);
input CLOCK_PIXEL;
input RESET;
input PIXEL; // black (0) or white (1)
output [10:0] PIXEL_H;
output [10:0] PIXEL_V;
output VGA_RED;
output VGA_GREEN;
output VGA_BLUE;
output VGA_HS;
output VGA_VS;
/* Internal registers for horizontal signal timing */
reg [10:0] hor_reg; // to count up to 975
reg [10:0] hor_pixel; // the next pixel
reg hor_sync;
wire hor_max = (hor_reg == 975); // to tell when a line is full
/* Internal registers for vertical signal timing */
reg [9:0] ver_reg; // to count up to 527
reg [10:0] ver_pixel; // the next pixel
reg ver_sync;
reg red, green, blue;
wire ver_max = (ver_reg == 527); // to tell when a line is full
// visible pixel counter
//reg [15:0] visible_pixel;
/* Running through line */
always @ (posedge CLOCK_PIXEL or posedge RESET) begin
if (RESET) begin
hor_reg <= 0;
ver_reg <= 0;
end
else if (hor_max) begin
hor_reg <= 0;
/* Running through frame */
if (ver_max) begin
ver_reg <= 0;
end else begin
ver_reg <= ver_reg + 1;
end
end else begin
hor_reg <= hor_reg + 1;
end
end
always @ (posedge CLOCK_PIXEL or posedge RESET) begin
if (RESET) begin
hor_sync <= 0;
ver_sync <= 0;
red <= 0;
green <= 0;
blue <= 0;
hor_pixel <= 0;
ver_pixel <= 0;
end
else begin
/* Generating the horizontal sync signal */
if (hor_reg == 840) begin // video (800) + front porch (40)
hor_sync <= 1; // turn on horizontal sync pulse
end else if (hor_reg == 928) begin // video (800) + front porch (40) + Sync Pulse (88)
hor_sync <= 0; // turn off horizontal sync pulse
end
/* Generating the vertical sync signal */
if (ver_reg == 493) begin // LINES: video (480) + front porch (13)
ver_sync <= 1; // turn on vertical sync pulse
end else if (ver_reg == 496) begin // LINES: video (480) + front porch (13) + Sync Pulse (3)
ver_sync <= 0; // turn off vertical sync pulse
end
// black during the porches
if (ver_reg > 480 || hor_reg > 800) begin
red <= 0;
green <= 0;
blue <= 0;
if (ver_reg > 480) begin
ver_pixel <= 0;
end
if (hor_reg > 800) begin
hor_pixel <= 0;
end
end
else begin
hor_pixel <= hor_reg;
ver_pixel <= ver_reg;
// Draw the pixel.
if (PIXEL) begin
// white
red <= 1;
green <= 1;
blue <= 1;
end
else begin
// black
red <= 0;
green <= 0;
blue <= 0;
end
end
end
end
// Send the sync signals to the output.
assign VGA_HS = hor_sync;
assign VGA_VS = ver_sync;
assign VGA_RED = red;
assign VGA_GREEN = green;
assign VGA_BLUE = blue;
assign PIXEL_H = hor_pixel;
assign PIXEL_V = ver_pixel;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:13:58 04/26/2015
// Design Name:
// Module Name: HallwayRight
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HallwayRight(clk_vga, CurrentX, CurrentY, mapData, wall);
input clk_vga;
input [9:0]CurrentX;
input [8:0]CurrentY;
input [7:0]wall;
output [7:0]mapData;
reg [7:0]mColor;
always @(posedge clk_vga) begin
//Top walls
if((CurrentY < 40) && ~(CurrentX < 0)) begin
mColor[7:0] <= wall;
end
//Right side wall
else if(~(CurrentX < 600)) begin
mColor[7:0] <= wall;
end
//Bottom wall
else if((~(CurrentY < 440) && (CurrentX < 260)) || (~(CurrentY < 440) && ~(CurrentX < 380))) begin
mColor[7:0] <= wall;
//floor area - grey
end else
mColor[7:0] <= 8'b10110110;
end
assign mapData = mColor;
endmodule
|
// ****************************************************************************
// Copyright : NUDT.
// ============================================================================
// FILE NAME : outPUT_CTL.v
// CREATE DATE : 2013-12-03
// AUTHOR : ZengQiang
// AUTHOR'S EMAIL : [email protected]
// AUTHOR'S TEL :
// ============================================================================
// RELEASE HISTORY -------------------------------------------------------
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 2013-12-03 ZengQiang Original Verison
// ============================================================================
// KEYWORDS : N/A
// ----------------------------------------------------------------------------
// PURPOSE : SLOTid determine PKT to slot?
// ----------------------------------------------------------------------------
// ============================================================================
// REUSE ISSUES
// Reset Strategy : Async clear,active high
// Clock Domains : clk
// Critical TiminG : N/A
// Instantiations : N/A
// Synthesizable : N/A
// Others : N/A
// ****************************************************************************
module OUTPUT_CTL(
clk,
reset,
in_egress_pkt_wr,
in_egress_pkt,
in_egress_pkt_valid_wr,
in_egress_pkt_valid,
out_egress_pkt_almostfull,
out_slot0_pkt,
out_slot0_pkt_wr,
out_slot0_pkt_valid,
out_slot0_pkt_valid_wr,
in_slot0_pkt_almostfull,
out_slot1_pkt,
out_slot1_pkt_wr,
out_slot1_pkt_valid,
out_slot1_pkt_valid_wr,
in_slot1_pkt_almostfull,
output_receive_pkt_add,
output_discard_error_pkt_add,
output_send_slot0_pkt_add,
output_send_slot1_pkt_add
);
input clk;
input reset;
input in_egress_pkt_wr;
input [133:0] in_egress_pkt;
input in_egress_pkt_valid_wr;
input in_egress_pkt_valid;
output wire out_egress_pkt_almostfull;
output reg [133:0] out_slot0_pkt;
output reg out_slot0_pkt_wr;
output reg out_slot0_pkt_valid;
output reg out_slot0_pkt_valid_wr;
input in_slot0_pkt_almostfull;
output reg [133:0] out_slot1_pkt;
output reg out_slot1_pkt_wr;
output reg out_slot1_pkt_valid;
output reg out_slot1_pkt_valid_wr;
input in_slot1_pkt_almostfull;
output reg output_receive_pkt_add;
output reg output_discard_error_pkt_add;
output reg output_send_slot0_pkt_add;
output reg output_send_slot1_pkt_add;
reg [2:0] xaui_channel;
reg [2:0] current_state;//transmit processed pkt to 4 paths by the outport in the metadata of pkt
parameter idle_s = 3'b000,
discard_s = 3'b001,
transmit_s = 3'b010,
wait_s = 3'b011,
pkt_cut_s = 3'b100;
always@(posedge clk or negedge reset)
if(!reset)
begin
out_slot0_pkt_wr <= 1'b0;
out_slot0_pkt <= 134'b0;
out_slot0_pkt_valid_wr <= 1'b0;
out_slot0_pkt_valid <= 1'b0;
out_slot1_pkt_wr <= 1'b0;
out_slot1_pkt <= 134'b0;
out_slot1_pkt_valid_wr <= 1'b0;
out_slot1_pkt_valid <= 1'b0;
in_egress_pkt_valid_rd <= 1'b0;
in_egress_pkt_rd <= 1'b0;
xaui_channel <= 3'b0;//slot ID
output_receive_pkt_add <= 1'b0;
output_discard_error_pkt_add <= 1'b0;
output_send_slot0_pkt_add <= 1'b0;
output_send_slot1_pkt_add <= 1'b0;
current_state <= idle_s;
end
else
begin
case(current_state)
idle_s:begin//judge and poll pkt from pcietx and iace fifo,and reverse order metadata
out_slot0_pkt_wr <= 1'b0;
out_slot0_pkt <= 134'b0;
out_slot0_pkt_valid_wr <= 1'b0;
out_slot0_pkt_valid <= 1'b0;
out_slot1_pkt_wr <= 1'b0;
out_slot1_pkt <= 134'b0;
out_slot1_pkt_valid_wr <= 1'b0;
out_slot1_pkt_valid <= 1'b0;
output_discard_error_pkt_add <= 1'b0;
output_send_slot0_pkt_add <= 1'b0;
output_send_slot1_pkt_add <= 1'b0;
if(in_egress_pkt_valid_empty == 1'b0) begin//judge and poll pkt from pcietx and iace fifo
if(in_egress_pkt_valid_q == 1'b1) begin
if(in_egress_pkt_q[110] == 1'b0) begin//SLOTid
if(in_slot0_pkt_almostfull == 1'b1) begin
current_state <= idle_s;
end
else begin
in_egress_pkt_rd <= 1'b1;
in_egress_pkt_valid_rd <= 1'b1;
xaui_channel <= in_egress_pkt_q[112:110];//slot ID
output_receive_pkt_add <= 1'b1;
current_state <= transmit_s;
end
end
else begin
if(in_slot1_pkt_almostfull == 1'b1) begin
current_state <= idle_s;
end
else begin
in_egress_pkt_rd <= 1'b1;
in_egress_pkt_valid_rd <= 1'b1;
xaui_channel <= in_egress_pkt_q[112:110];
output_receive_pkt_add <= 1'b1;
current_state <= transmit_s;
end
end
end
else begin
in_egress_pkt_rd <= 1'b1;
in_egress_pkt_valid_rd <= 1'b1;
current_state <= discard_s;
end
end
else
current_state <= idle_s;
end
discard_s:begin//discard the error pkt from pcietx
in_egress_pkt_valid_rd <= 1'b0;
if(in_egress_pkt_q[133:132]==2'b10)
begin
output_discard_error_pkt_add <= 1'b1;
in_egress_pkt_rd <= 1'b0;
current_state <= idle_s;
end
else
begin
current_state<= discard_s;
end
end
transmit_s:begin//transmit pkt body from pcietx
output_receive_pkt_add <= 1'b0;
in_egress_pkt_valid_rd <= 1'b0;
case(xaui_channel[2:0])//slot
3'b000:begin
out_slot0_pkt_wr <=1'b1;
out_slot0_pkt <= in_egress_pkt_q;
if(in_egress_pkt_q[133:132]==2'b10)//pkt tail
begin
in_egress_pkt_rd <= 1'b0;
out_slot0_pkt_valid_wr <= 1'b1;
output_send_slot0_pkt_add <= 1'b1;
out_slot0_pkt_valid <= 1'b1;
current_state<= idle_s;
end
else//pkt head and pkt middle
begin
in_egress_pkt_rd <= 1'b1;
current_state<= transmit_s;
end
end
3'b001:begin
out_slot1_pkt_wr <=1'b1;
out_slot1_pkt <=in_egress_pkt_q;
if(in_egress_pkt_q[133:132]==2'b10)//pkt tail
begin
in_egress_pkt_rd <= 1'b0;
out_slot1_pkt_valid_wr <= 1'b1;
output_send_slot1_pkt_add <= 1'b1;
out_slot1_pkt_valid <= 1'b1;
current_state <= idle_s;
end
else//pkt head and pkt middle
begin
in_egress_pkt_rd <=1'b1;
current_state<= transmit_s;
end
end
endcase
end
endcase
end
wire [7:0] in_egress_pkt_usedw;
assign out_egress_pkt_almostfull = in_egress_pkt_usedw[7];
reg in_egress_pkt_rd;
wire [133:0] in_egress_pkt_q;
fifo_256_134 egress_pkt(
.aclr(!reset),
.clock(clk),
.data(in_egress_pkt),
.rdreq(in_egress_pkt_rd),
.wrreq(in_egress_pkt_wr),
.q(in_egress_pkt_q),
.usedw(in_egress_pkt_usedw)
);
reg in_egress_pkt_valid_rd;
wire in_egress_pkt_valid_empty;
wire in_egress_pkt_valid_q;
fifo_64_1 egress_pkt_valid(
.aclr(!reset),
.clock(clk),
.data(in_egress_pkt_valid),
.rdreq(in_egress_pkt_valid_rd),
.wrreq(in_egress_pkt_valid_wr),
.empty(in_egress_pkt_valid_empty),
.q(in_egress_pkt_valid_q)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CONB_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__CONB_FUNCTIONAL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Name Output
pullup pullup0 (HI );
pulldown pulldown0 (LO );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CONB_FUNCTIONAL_V |
/*
L2 Data Cache
This version will use the Cache as RAM,
0C00_0000 .. 0C00_7FFF
May be accessed either as 128 bit tiles, or as 32 or 64 bit words.
MMIO may only be accessed as 32-bits.
*/
`include "CoreDefs.v"
module Dc2Tile(
/* verilator lint_off UNUSED */
clock, reset,
regInAddr, regInData,
regOutData, regOutOK,
regInOE, regInWR,
regInOp,
memInData, memOutData, memAddr,
memOE, memWR, memOK,
mmioInData, mmioOutData, mmioAddr,
mmioOE, mmioWR, mmioOK
);
input clock; //clock
input reset; //reset
input[63:0] regInAddr; //input PC address
input[127:0] regInData; //input data (store)
input regInOE; //Load
input regInWR; //Store
input[4:0] regInOp; //Operation Size/Type
output[127:0] regOutData; //output data (load)
output[1:0] regOutOK; //set if operation suceeds
input[127:0] memInData; //memory PC data
output[127:0] memOutData; //memory PC data
output[31:0] memAddr; //memory PC address
output memOE; //memory PC output-enable
output memWR; //memory PC output-enable
input[1:0] memOK; //memory PC OK
reg[127:0] tMemOutData; //memory PC data
reg[31:0] tMemAddr; //memory PC address
reg tMemOE; //memory PC output-enable
reg tMemWR; //memory PC output-enable
assign memOutData = tMemOutData;
assign memAddr = tMemAddr;
assign memOE = tMemOE;
assign memWR = tMemWR;
input[31:0] mmioInData; //mmio data in
output[31:0] mmioOutData; //mmio data out
output[31:0] mmioAddr; //mmio address
output mmioOE; //mmio read
output mmioWR; //mmio write
input[1:0] mmioOK; //mmio OK
reg[31:0] tMmioOutData; //mmio data out
reg[31:0] tMmioAddr; //mmio address
reg tMmioOE; //mmio read
reg tMmioWR; //mmio write
assign mmioOutData = tMmioOutData;
assign mmioAddr = tMmioAddr;
assign mmioOE = tMmioOE;
assign mmioWR = tMmioWR;
// (* ram_style="block" *) reg[127:0] memTile[2047:0]; //memory
(* ram_style="block" *) reg[31:0] memTileA[0:2047]; //memory
(* ram_style="block" *) reg[31:0] memTileB[0:2047]; //memory
(* ram_style="block" *) reg[31:0] memTileC[0:2047]; //memory
(* ram_style="block" *) reg[31:0] memTileD[0:2047]; //memory
(* ram_style="block" *) reg[127:0] romTile[255:0]; //ROM
// reg[127:0] tRomTile;
reg[127:0] tRamTile;
reg[10:0] tAccTileIx;
reg[127:0] tMemTile;
reg[127:0] tOutData;
reg[127:0] tNextTile;
reg[10:0] tRegTileIx;
reg[10:0] tNextTileIx;
reg tNextTileSt;
reg[1:0] tRegOutOK;
wire addrIsRam;
assign addrIsRam =
(regInAddr[28:0] >= 29'h0C00_0000) &&
(regInAddr[28:0] <= 29'h1E00_0000) ;
wire addrIsRom;
assign addrIsRom =
(regInAddr[28:0] <= 29'h0010_0000) ;
assign regOutData = tOutData;
assign regOutOK = tRegOutOK;
initial begin
$readmemh("bootrom.txt", romTile);
end
always @*
begin
tMemTile = 0;
tOutData = 0;
tNextTile = 0;
tRegTileIx = regInAddr[14:4];
tNextTileIx = tRegTileIx;
tNextTileSt = 0;
tRegOutOK = 0;
tMemOutData = 0; //memory PC data
tMemAddr = 0; //memory PC address
tMemOE = 0; //memory PC output-enable
tMemWR = 0; //memory PC output-enable
tMmioOutData = 0; //mmio data out
tMmioAddr = 0; //mmio address
tMmioOE = 0; //mmio read
tMmioWR = 0; //mmio write
if(regInOE || regInWR)
begin
$display("DcTile2 %X %d %d", regInAddr, addrIsRom, addrIsRam);
if(addrIsRom)
begin
tMemTile = romTile[tRegTileIx[7:0]];
// tMemTile = tRomTile;
tNextTile = tMemTile;
tRegOutOK = 1;
// tRegOutOK = (tAccTileIx == tRegTileIx) ?
// UMEM_OK_OK : UMEM_OK_HOLD;
$display("Rom: %X", tMemTile);
case(regInOp[1:0])
2'b00:
tOutData=tMemTile;
2'b01:
tOutData=tMemTile;
2'b10: case(regInAddr[3:2])
2'b00: tOutData={96'h0, tMemTile[ 31: 0]};
2'b01: tOutData={96'h0, tMemTile[ 63:32]};
2'b10: tOutData={96'h0, tMemTile[ 95:64]};
2'b11: tOutData={96'h0, tMemTile[127:96]};
endcase
2'b11: begin
if(regInAddr[3])
tOutData={64'h0, tMemTile[127:64]};
else
tOutData={64'h0, tMemTile[ 63: 0]};
end
endcase
$display("Rom: Out=%X", tOutData);
end
else
if(addrIsRam)
begin
// tMemTile = memTile[tRegTileIx];
// tMemTile[ 31: 0] = memTileA[tRegTileIx];
// tMemTile[ 63:32] = memTileB[tRegTileIx];
// tMemTile[ 95:64] = memTileC[tRegTileIx];
// tMemTile[127:96] = memTileD[tRegTileIx];
tMemTile = tRamTile;
tNextTile = tMemTile;
// tRegOutOK = 1;
tRegOutOK = (tAccTileIx == tRegTileIx) ?
UMEM_OK_OK : UMEM_OK_HOLD;
case(regInOp[1:0])
2'b00:
tOutData=tMemTile;
2'b01:
tOutData=tMemTile;
2'b10: case(regInAddr[3:2])
2'b00: tOutData={96'h0, tMemTile[ 31: 0]};
2'b01: tOutData={96'h0, tMemTile[ 63:32]};
2'b10: tOutData={96'h0, tMemTile[ 95:64]};
2'b11: tOutData={96'h0, tMemTile[127:96]};
endcase
2'b11: begin
if(regInAddr[3])
tOutData={64'h0, tMemTile[127:64]};
else
tOutData={64'h0, tMemTile[ 63: 0]};
end
endcase
if(regInWR)
begin
tNextTileIx = tRegTileIx;
tNextTileSt = 1;
case(regInOp[1:0])
2'b00:
tNextTile=regInData;
2'b01:
tNextTile=regInData;
2'b10: case(regInAddr[3:2])
2'b00: tNextTile[ 31: 0] = regInData[31:0];
2'b01: tNextTile[ 63:32] = regInData[31:0];
2'b10: tNextTile[ 95:64] = regInData[31:0];
2'b11: tNextTile[127:96] = regInData[31:0];
endcase
2'b11: begin
if(regInAddr[3])
tNextTile[127:64] = regInData[63:0];
else
tNextTile[ 63: 0] = regInData[63:0];
end
endcase
end
end
else
begin
tMmioOutData = regInData[31:0];
tMmioAddr = regInAddr[31:0];
tMmioOE = regInOE;
tMmioWR = regInWR;
tRegOutOK = mmioOK;
tOutData = { 96'h0, mmioInData[31:0] };
end
end
end
always @ (posedge clock)
begin
// tRomTile <= romTile[tRegTileIx[7:0]];
// tRamTile <= memTile[tRegTileIx];
tRamTile[ 31: 0] <= memTileA[tRegTileIx];
tRamTile[ 63:32] <= memTileB[tRegTileIx];
tRamTile[ 95:64] <= memTileC[tRegTileIx];
tRamTile[127:96] <= memTileD[tRegTileIx];
tAccTileIx <= tRegTileIx;
if(tNextTileSt)
begin
// memTile[tNextTileIx] <= tNextTile;
memTileA[tNextTileIx] <= tNextTile[ 31: 0];
memTileB[tNextTileIx] <= tNextTile[ 63:32];
memTileC[tNextTileIx] <= tNextTile[ 95:64];
memTileD[tNextTileIx] <= tNextTile[127:96];
end
end
endmodule
|
//------------------------------------------------------------------------------
// File : basic_pat_gen.v
// Author : Xilinx Inc.
// -----------------------------------------------------------------------------
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
// Description: This module allows either a user side loopback, with address swapping,
// OR the generation of simple packets. The selection being controlled by a top level input
// which can be sourced fdrom a DIP switch in hardware.
// The packet generation is controlled by simple parameters giving the ability to set the DA,
// SA amd max/min size packets. The data portion of each packet is always a simple
// incrementing pattern.
// When configured to loopback the first 12 bytes of the packet are accepted and then the
// packet is output with/without address swapping. Currently, this is hard wired in the address
// swap logic.
//
//
//------------------------------------------------------------------------------
`timescale 1 ps/1 ps
module basic_pat_gen #(
parameter DEST_ADDR = 48'hda0102030405,
parameter SRC_ADDR = 48'h5a0102030405,
parameter MAX_SIZE = 16'd500,
parameter MIN_SIZE = 16'd64,
parameter ENABLE_VLAN = 1'b0,
parameter VLAN_ID = 12'd2,
parameter VLAN_PRIORITY = 3'd2
)(
input axi_tclk,
input axi_tresetn,
input check_resetn,
input enable_pat_gen,
input enable_pat_chk,
input enable_address_swap,
input [1:0] speed,
// data from the RX data path
input [7:0] rx_axis_tdata,
input rx_axis_tvalid,
input rx_axis_tlast,
input rx_axis_tuser,
output rx_axis_tready,
// data TO the TX data path
output [7:0] tx_axis_tdata,
output tx_axis_tvalid,
output tx_axis_tlast,
input tx_axis_tready,
output frame_error,
output activity_flash
);
wire [7:0] rx_axis_tdata_int;
wire rx_axis_tvalid_int;
wire rx_axis_tlast_int;
wire rx_axis_tready_int;
wire [7:0] pat_gen_tdata;
wire pat_gen_tvalid;
wire pat_gen_tlast;
wire pat_gen_tready;
wire pat_gen_tready_int;
wire [7:0] mux_tdata;
wire mux_tvalid;
wire mux_tlast;
wire mux_tready;
wire [7:0] tx_axis_as_tdata;
wire tx_axis_as_tvalid;
wire tx_axis_as_tlast;
wire tx_axis_as_tready;
assign tx_axis_tdata = tx_axis_as_tdata;
assign tx_axis_tvalid = tx_axis_as_tvalid;
assign tx_axis_tlast = tx_axis_as_tlast;
assign tx_axis_as_tready = tx_axis_tready;
assign pat_gen_tready = pat_gen_tready_int;
// basic packet generator - this has parametisable
// DA and SA fields but the LT and data will be auto-generated
// based on the min/max size parameters - these can be set
// to the same value to obtain a specific packet size or will
// increment from the lower packet size to the upper
axi_pat_gen #(
.DEST_ADDR (DEST_ADDR),
.SRC_ADDR (SRC_ADDR),
.MAX_SIZE (MAX_SIZE),
.MIN_SIZE (MIN_SIZE),
.ENABLE_VLAN (ENABLE_VLAN),
.VLAN_ID (VLAN_ID),
.VLAN_PRIORITY (VLAN_PRIORITY)
) axi_pat_gen (
.axi_tclk (axi_tclk),
.axi_tresetn (axi_tresetn),
.enable_pat_gen (enable_pat_gen),
.speed (speed),
.tdata (pat_gen_tdata),
.tvalid (pat_gen_tvalid),
.tlast (pat_gen_tlast),
.tready (pat_gen_tready)
);
axi_pat_check #(
.DEST_ADDR (DEST_ADDR),
.SRC_ADDR (SRC_ADDR),
.MAX_SIZE (MAX_SIZE),
.MIN_SIZE (MIN_SIZE),
.ENABLE_VLAN (ENABLE_VLAN),
.VLAN_ID (VLAN_ID),
.VLAN_PRIORITY (VLAN_PRIORITY)
) axi_pat_check (
.axi_tclk (axi_tclk),
.axi_tresetn (check_resetn),
.enable_pat_chk (enable_pat_chk),
.speed (speed),
.tdata (rx_axis_tdata),
.tvalid (rx_axis_tvalid),
.tlast (rx_axis_tlast),
.tready (rx_axis_tready),
.tuser (rx_axis_tuser),
.frame_error (frame_error),
.activity_flash (activity_flash)
);
// simple mux between the rx_fifo AXI interface and the pat gen output
// this is not registered as it is passed through a pipeline stage to limit the impact
axi_mux axi_mux(
.mux_select (enable_pat_gen),
.tdata0 (rx_axis_tdata),
.tvalid0 (rx_axis_tvalid),
.tlast0 (rx_axis_tlast),
.tready0 (rx_axis_tready),
.tdata1 (pat_gen_tdata),
.tvalid1 (pat_gen_tvalid),
.tlast1 (pat_gen_tlast),
.tready1 (pat_gen_tready_int),
.tdata (mux_tdata),
.tvalid (mux_tvalid),
.tlast (mux_tlast),
.tready (mux_tready)
);
// a pipeline stage has been added to reduce timing issues and allow
// a pattern generator to be muxed into the path
axi_pipe axi_pipe (
.axi_tclk (axi_tclk),
.axi_tresetn (axi_tresetn),
.rx_axis_fifo_tdata_in (mux_tdata),
.rx_axis_fifo_tvalid_in (mux_tvalid),
.rx_axis_fifo_tlast_in (mux_tlast),
.rx_axis_fifo_tready_in (mux_tready),
.rx_axis_fifo_tdata_out (rx_axis_tdata_int),
.rx_axis_fifo_tvalid_out (rx_axis_tvalid_int),
.rx_axis_fifo_tlast_out (rx_axis_tlast_int),
.rx_axis_fifo_tready_out (rx_axis_tready_int)
);
// address swap module: based around a Dual port distributed ram
// data is written in and the read only starts once the da/sa have been
// stored. Can cope with a gap of one cycle between packets.
address_swap address_swap (
.axi_tclk (axi_tclk),
.axi_tresetn (axi_tresetn),
.enable_address_swap (enable_address_swap),
.rx_axis_fifo_tdata (rx_axis_tdata_int),
.rx_axis_fifo_tvalid (rx_axis_tvalid_int),
.rx_axis_fifo_tlast (rx_axis_tlast_int),
.rx_axis_fifo_tready (rx_axis_tready_int),
.tx_axis_fifo_tdata (tx_axis_as_tdata),
.tx_axis_fifo_tvalid (tx_axis_as_tvalid),
.tx_axis_fifo_tlast (tx_axis_as_tlast),
.tx_axis_fifo_tready (tx_axis_as_tready)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DLXTP_FUNCTIONAL_PP_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTP_FUNCTIONAL_PP_V |
module PushButton_Debouncer#(parameter COUNTER_WIDTH = 16) (
input wire clk,
input wire PB, // "PB" is the glitchy, asynchronous to clk, active low push-button signal
// from which we make three outputs, all synchronous to the clock
output reg PB_state, // 1 as long as the push-button is active (down)
output wire PB_down, // 1 for one clock cycle when the push-button goes down (i.e. just pushed)
output wire PB_up // 1 for one clock cycle when the push-button goes up (i.e. just released)
);
// First use two flip-flops to synchronize the PB signal the "clk" clock domain
reg PB_sync_0; always @(posedge clk) PB_sync_0 <= PB; // invert PB to make PB_sync_0 active high
reg PB_sync_1; always @(posedge clk) PB_sync_1 <= PB_sync_0;
// Next declare a 16-bits counter
reg [COUNTER_WIDTH-1:0] PB_cnt;
// When the push-button is pushed or released, we increment the counter
// The counter has to be maxed out before we decide that the push-button state has changed
wire PB_idle = (PB_state==PB_sync_1);
wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's
always @(posedge clk)
if(PB_idle)
PB_cnt <= 0; // nothing's going on
else
begin
PB_cnt <= PB_cnt + 16'd1; // something's going on, increment the counter
if(PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed!
end
assign PB_down = ~PB_idle & PB_cnt_max & ~PB_state;
assign PB_up = ~PB_idle & PB_cnt_max & PB_state;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXBP_SYMBOL_V
`define SKY130_FD_SC_HD__SEDFXBP_SYMBOL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sedfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{control|Control Signals}}
input DE ,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXBP_SYMBOL_V
|
// --------------------------------------------------
//
// Fake implementation specific memory
//
// Sample implementation specific memory with test ports
// and 2-clock delay on output after read-enable asserted.
//
// --------------------------------------------------
module mem_16nm_ram4x73
(
input wire clk,
input wire ram_wr_en,
input wire [1:0] ram_wr_addr,
input wire [72:0] ram_wr_data,
input wire ram_rd_en,
input wire [1:0] ram_rd_addr,
output wire [72:0] ram_rd_data,
input wire bist_clk,
input wire bist_en,
input wire [1:0] bist_addr,
input wire [72:0] bist_wr_data,
output wire [72:0] bist_rd_data
);
// The memory declaration
reg [72:0] memory [3:0];
reg [72:0] ram_rd_data_i;
always @ (posedge clk) begin
if( ram_wr_en ) begin
memory[ram_wr_addr] <= #0 ram_wr_data;
end
if( ram_rd_en ) begin
ram_rd_data_i <= #0 memory[ram_rd_addr];
end
end
always @ (posedge clk) begin
ram_rd_data <= #0 ram_rd_data_i;
end
// Bist fake logic
always @ (posedge bist_clk ) begin
bist_rd_data <= #0 bist_wr_data;
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file LUTROM.v when simulating
// the core, LUTROM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module LUTROM(
clka,
addra,
douta
);
input clka;
input [12 : 0] addra;
output [17 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("virtex5"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("LUTROM.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(8192),
.C_READ_DEPTH_B(8192),
.C_READ_WIDTH_A(18),
.C_READ_WIDTH_B(18),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(8192),
.C_WRITE_DEPTH_B(8192),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(18),
.C_WRITE_WIDTH_B(18),
.C_XDEVICEFAMILY("virtex5")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/*
* CRC-16 Encoder/Decoder
*
* Calculation of 16-bit cyclic redundancy checks
*
* For more detailed information about CRC-16 for EPC Gen2, refer to annex F of the protocol
*/
`timescale 1us / 1ns
module crc16
(
output reg crc16_check_pass_reg,
output [15:0]crc_16,
input clk_crc16,
input rst_crc16,
input data,
input reply_data,
input sync,
input package_complete,
input en_crc16_for_rpy
);
wire d_in;
reg crc16_check_pass;
reg [15:0]reg_crc;
assign d_in = en_crc16_for_rpy? reply_data : data;
assign crc_16 = ~reg_crc;
always@(*) begin
if(reg_crc == 16'h1d0f) crc16_check_pass = 1'b1;
else crc16_check_pass = 1'b0;
end
always@(posedge clk_crc16 or negedge rst_crc16) begin
if(~rst_crc16) crc16_check_pass_reg <= 1'b0;
else if(package_complete) crc16_check_pass_reg <= crc16_check_pass;
end
always@(posedge clk_crc16 or negedge rst_crc16) begin
if(~rst_crc16) reg_crc <= 16'hffff;
else if(sync | en_crc16_for_rpy) begin
reg_crc[15] <= reg_crc[14];
reg_crc[14] <= reg_crc[13];
reg_crc[13] <= reg_crc[12];
reg_crc[12] <= reg_crc[11] ^ (d_in ^ reg_crc[15]);
reg_crc[11] <= reg_crc[10];
reg_crc[10] <= reg_crc[9];
reg_crc[9] <= reg_crc[8];
reg_crc[8] <= reg_crc[7];
reg_crc[7] <= reg_crc[6];
reg_crc[6] <= reg_crc[5];
reg_crc[5] <= reg_crc[4] ^ (d_in ^ reg_crc[15]);
reg_crc[4] <= reg_crc[3];
reg_crc[3] <= reg_crc[2];
reg_crc[2] <= reg_crc[1];
reg_crc[1] <= reg_crc[0];
reg_crc[0] <= d_in ^ reg_crc[15];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_TB_V
`define SKY130_FD_SC_HD__BUF_TB_V
/**
* buf: Buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__buf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__buf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_TB_V
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* PTP tag insert module
*/
module ptp_tag_insert #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = DATA_WIDTH/8,
parameter TAG_WIDTH = 16,
parameter TAG_OFFSET = 1,
parameter USER_WIDTH = TAG_WIDTH+TAG_OFFSET
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Tag input
*/
input wire [TAG_WIDTH-1:0] s_axis_tag,
input wire s_axis_tag_valid,
output wire s_axis_tag_ready
);
reg [TAG_WIDTH-1:0] tag_reg = {TAG_WIDTH{1'b0}};
reg tag_valid_reg = 1'b0;
reg [USER_WIDTH-1:0] user;
assign s_axis_tready = m_axis_tready && tag_valid_reg;
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = s_axis_tkeep;
assign m_axis_tvalid = s_axis_tvalid && tag_valid_reg;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tuser = user;
assign s_axis_tag_ready = !tag_valid_reg;
always @* begin
user = s_axis_tuser;
user[TAG_OFFSET +: TAG_WIDTH] = tag_reg;
end
always @(posedge clk) begin
if (tag_valid_reg) begin
if (s_axis_tvalid && s_axis_tready && s_axis_tlast) begin
tag_valid_reg <= 1'b0;
end
end else begin
tag_reg <= s_axis_tag;
tag_valid_reg <= s_axis_tag_valid;
end
if (rst) begin
tag_valid_reg <= 1'b0;
end
end
endmodule
|
`timescale 1ns / 1ps
// Name: WcaInterruptIF.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaInterruptIF
(
input wire clock, //High speed logic clock
input wire reset, //Reset functions
input wire [7:0] evtsig, //Up to eight events supported.
output wire cpu_interrupt, // signals the CPU an interrupt occurred.
input wire [11:0] rbusCtrl, // Address and control lines { addr[7:0], readStrobe, writeStrobe, cpuclk }
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter CTRL_ADDR=0; //Interrupt register control address.
//****************************************************
//* Event control
//****************************************************
// MASK WRITE REGISTER( WriteByteRegister)
// Write to this register to set the Event mask. Register is also used to
// clear an event by writing a 0 and 1 to the respective event bit.
//
// bit# | Description
//-------|----------------------------------------------------------
// 0 Enable / Disable Event #0
// 1 Enable / Disable Event #1
// 2 Enable / Disable Event #2
// 3 Enable / Disable Event #3
// 4 Enable / Disable Event #4
// 5 Enable / Disable Event #5
// 6 Enable / Disable Event #6
// 7 Enable / Disable Event #7
//
// STATUS READ REGISTER( ReadByteRegister)
// Read this register to get the Event status.
// bit# | Description
//-------|----------------------------------------------------------
// 0 Event #0 Triggered
// 1 Event #1 Triggered
// 2 Event #2 Triggered
// 3 Event #3 Triggered
// 4 Event #4 Triggered
// 5 Event #5 Triggered
// 6 Event #6 Triggered
// 7 Event #7 Triggered
wire [7:0] evtMask;
wire [7:0] evtStatus;
wire [7:0] evtUpdate;
wire evt;
//Combine all signals into general event indicator.
assign evt = (evtsig[7] & evtMask[7]) | (evtsig[6] & evtMask[6])
| (evtsig[5] & evtMask[5]) | (evtsig[4] & evtMask[4])
| (evtsig[3] & evtMask[3]) | (evtsig[2] & evtMask[2])
| (evtsig[1] & evtMask[1]) | (evtsig[0] & evtMask[0]) ;
//Get the current interrupt state.
assign cpu_interrupt = evtStatus[7] | evtStatus[6]
| evtStatus[5] | evtStatus[4]
| evtStatus[3] | evtStatus[2]
| evtStatus[1] | evtStatus[0];
//Calculate the latest event state update.
assign evtUpdate = (evtStatus | evtsig) & evtMask;
//Get Event Enable Mask.
WcaWriteByteReg #(CTRL_ADDR ) wstatreg
(.reset(reset), .out( evtMask), .rbusCtrl(rbusCtrl), .rbusData(rbusData) );
//Latch current event state into the read status register.
//Override standard disable write on read function to allow
//interrupts to happen while register is being processed.
WcaReadByteReg #(CTRL_ADDR, 1'b1) rstatreg
( .reset(reset), .clock(clock), .enableIn(1'b1), .in(evtUpdate),
.Q( evtStatus), .rbusCtrl(rbusCtrl), .rbusData(rbusData) );
endmodule
|
/**
* This file is part of pyBAR.
*
* pyBAR is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* pyBAR is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with pyBAR. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`default_nettype none
module top (
input wire USER_RESET,
input wire USER_CLOCK,
input wire ETH_COL,
input wire ETH_CRS,
output wire ETH_MDC,
inout wire ETH_MDIO,
output wire ETH_RESET_n,
input wire ETH_RX_CLK,
input wire [3:0] ETH_RX_D,
input wire ETH_RX_DV,
input wire ETH_RX_ER,
input wire ETH_TX_CLK,
output wire [3:0] ETH_TX_D,
output wire ETH_TX_EN,
output wire [3:0] GPIO_LED,
input wire [3:0] GPIO_DIP,
inout wire SDA, SCL,
output wire CMD_CLK, CMD_DATA,
input wire [3:0] DOBOUT
);
wire CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKFBIN, LOCKED;
wire RST, BUS_CLK, BUS_RST, SPI_CLK;
PLL_BASE #(
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(16), // Multiply value for all CLKOUT clock outputs (1-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of the clock feedback output (0.0-360.0).
.CLKIN_PERIOD(25.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30
// MHz).
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
.CLKOUT0_DIVIDE(1), //640 - 320MHz
.CLKOUT1_DIVIDE(32), //25
.CLKOUT2_DIVIDE(64), //10HHz
.CLKOUT3_DIVIDE(16), //40MHz
.CLKOUT4_DIVIDE(4), // 160Mhz
.CLKOUT5_DIVIDE(40), //16Mhz
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT5_PHASE: Output phase relationship for CLKOUT# clock output (-360.0-360.0).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLK_FEEDBACK("CLKFBOUT"), // Clock source to drive CLKFBIN ("CLKFBOUT" or "CLKOUT0")
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "EXTERNAL"
.DIVCLK_DIVIDE(1), // Division value for all output clocks (1-52)
.REF_JITTER(0.1), // Reference Clock Jitter in UI (0.000-0.999).
.RESET_ON_LOSS_OF_LOCK("FALSE") // Must be set to FALSE
)
PLL_BASE_inst (
.CLKFBOUT(CLKFBOUT), // 1-bit output: PLL_BASE feedback output
// CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
.CLKOUT0(CLKOUT0),
.CLKOUT1(CLKOUT1),
.CLKOUT2(CLKOUT2),
.CLKOUT3(CLKOUT3),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.LOCKED(LOCKED), // 1-bit output: PLL_BASE lock status output
.CLKFBIN(CLKFBIN), // 1-bit input: Feedback clock input
.CLKIN(USER_CLOCK), // 1-bit input: Clock input
.RST(USER_RESET) // 1-bit input: Reset input
);
wire RX_CLK, TX_CLK;
assign RST = USER_RESET | !LOCKED;
assign CLKFBIN = CLKFBOUT; //BUFG BUFG_FB ( .O(CLKFBIN), .I(CLKFBOUT) );
BUFG BUFG_BUS ( .O(BUS_CLK), .I(CLKOUT3) );
BUFG BUFG_ETH_RX_CLK ( .O(RX_CLK), .I(ETH_RX_CLK) );
//BUFG BUFG_SPI( .O(SPI_CLK), .I(CLKOUT2) );
BUFG BUFG_ETH_TX_CLK ( .O(TX_CLK), .I(ETH_TX_CLK) );
wire RX_320_CLK, RX_160_CLK, RX_16_CLK;
//BUFG BUFG_RX_320 ( .O(RX_320_CLK), .I(CLKOUT0) );
//assign RX_320_CLK = CLKOUT0;
BUFG BUFG_RX_160 ( .O(RX_160_CLK), .I(CLKOUT4) );
BUFG BUFG_RX_16 ( .O(RX_16_CLK), .I(CLKOUT5) );
//wire CLKOUT0_BUF;
//BUFG BUFG_RX_320 ( .O(CLKOUT0_BUF), .I(CLKOUT0) );
wire CLK40;
assign CLK40 = BUS_CLK;
wire IOCLK, DIVCLK, DIVCLK_BUF, RX_320_IOCE;
/*
BUFIO2 #(
.DIVIDE(4), // DIVCLK divider (1,3-8)
.DIVIDE_BYPASS("TRUE"), // Bypass the divider circuitry (TRUE/FALSE)
.I_INVERT("FALSE"), // Invert clock (TRUE/FALSE)
.USE_DOUBLER("FALSE") // Use doubler circuitry (TRUE/FALSE)
)
BUFIO2_inst (
.DIVCLK(DIVCLK_BUF), // 1-bit output: Divided clock output
.IOCLK(RX_320_CLK), // 1-bit output: I/O output clock
.SERDESSTROBE(RX_320_IOCE), // 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
.I(CLKOUT3_BUF) // 1-bit input: Clock input (connect to IBUFG)
);
BUFG BUFG_DIV ( .O(RX_160_CLK), .I(DIVCLK_BUF) );
*/
BUFPLL #(
.DIVIDE(4), // DIVCLK divider (1-8)
.ENABLE_SYNC("TRUE") // Enable synchrnonization between PLL and GCLK (TRUE/FALSE)
)
BUFPLL_inst (
.IOCLK(RX_320_CLK), // 1-bit output: Output I/O clock
.LOCK(), // 1-bit output: Synchronized LOCK output
.SERDESSTROBE(RX_320_IOCE), // 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
.GCLK(RX_160_CLK), // 1-bit input: BUFG clock input
.LOCKED(LOCKED), // 1-bit input: LOCKED input from PLL
.PLLIN(CLKOUT0) // 1-bit input: Clock input from PLL
);
wire EEPROM_CS, EEPROM_SK, EEPROM_DI;
wire TCP_CLOSE_REQ;
wire RBCP_ACT, RBCP_WE, RBCP_RE;
wire [7:0] RBCP_WD, RBCP_RD;
wire [31:0] RBCP_ADDR;
wire TCP_RX_WR;
wire [7:0] TCP_RX_DATA;
wire [15:0] TCP_RX_WC;
wire RBCP_ACK;
wire TCP_TX_FULL;
wire TCP_TX_WR;
wire [7:0] TCP_TX_DATA;
wire mdio_gem_i;
wire mdio_gem_o;
wire mdio_gem_t;
wire [3:0] ETH_TX_D_NO;
WRAP_SiTCP_GMII_XC6S_16K #(.TIM_PERIOD(50))sitcp(
.CLK(BUS_CLK), // in : System Clock >129MHz
.RST(RST), // in : System reset
// Configuration parameters
.FORCE_DEFAULTn(1'b0), // in : Load default parameters
.EXT_IP_ADDR(32'hc0a80a11), // in : IP address[31:0] //192.168.10.11
.EXT_TCP_PORT(16'd24), // in : TCP port #[15:0]
.EXT_RBCP_PORT(16'd4660), // in : RBCP port #[15:0]
.PHY_ADDR(5'd30), // in : PHY-device MIF address[4:0]
// EEPROM
.EEPROM_CS(), // out : Chip select
.EEPROM_SK(), // out : Serial data clock
.EEPROM_DI(), // out : Serial write data
.EEPROM_DO(1'b0), // in : Serial read data
// user data, intialial values are stored in the EEPROM, 0xFFFF_FC3C-3F
.USR_REG_X3C(), // out : Stored at 0xFFFF_FF3C
.USR_REG_X3D(), // out : Stored at 0xFFFF_FF3D
.USR_REG_X3E(), // out : Stored at 0xFFFF_FF3E
.USR_REG_X3F(), // out : Stored at 0xFFFF_FF3F
// MII interface
.GMII_RSTn(ETH_RESET_n), // out : PHY reset
.GMII_1000M(1'b0), // in : GMII mode (0:MII, 1:GMII)
// TX
.GMII_TX_CLK(TX_CLK), // in : Tx clock
.GMII_TX_EN(ETH_TX_EN), // out : Tx enable
.GMII_TXD({ETH_TX_D_NO,ETH_TX_D}), // out : Tx data[7:0]
.GMII_TX_ER(), // out : TX error
// RX
.GMII_RX_CLK(RX_CLK), // in : Rx clock
.GMII_RX_DV(ETH_RX_DV), // in : Rx data valid
.GMII_RXD({4'b0, ETH_RX_D}), // in : Rx data[7:0]
.GMII_RX_ER(ETH_RX_ER), // in : Rx error
.GMII_CRS(ETH_CRS), // in : Carrier sense
.GMII_COL(ETH_COL), // in : Collision detected
// Management IF
.GMII_MDC(ETH_MDC), // out : Clock for MDIO
.GMII_MDIO_IN(mdio_gem_i), // in : Data
.GMII_MDIO_OUT(mdio_gem_o), // out : Data
.GMII_MDIO_OE(mdio_gem_t), // out : MDIO output enable
// User I/F
.SiTCP_RST(BUS_RST), // out : Reset for SiTCP and related circuits
// TCP connection control
.TCP_OPEN_REQ(1'b0), // in : Reserved input, shoud be 0
.TCP_OPEN_ACK(), // out : Acknowledge for open (=Socket busy)
.TCP_ERROR(), // out : TCP error, its active period is equal to MSL
.TCP_CLOSE_REQ(TCP_CLOSE_REQ), // out : Connection close request
.TCP_CLOSE_ACK(TCP_CLOSE_REQ), // in : Acknowledge for closing
// FIFO I/F
.TCP_RX_WC(TCP_RX_WC), // in : Rx FIFO write count[15:0] (Unused bits should be set 1)
.TCP_RX_WR(TCP_RX_WR), // out : Write enable
.TCP_RX_DATA(TCP_RX_DATA), // out : Write data[7:0]
.TCP_TX_FULL(TCP_TX_FULL), // out : Almost full flag
.TCP_TX_WR(TCP_TX_WR), // in : Write enable
.TCP_TX_DATA(TCP_TX_DATA), // in : Write data[7:0]
// RBCP
.RBCP_ACT(RBCP_ACT), // out : RBCP active
.RBCP_ADDR(RBCP_ADDR), // out : Address[31:0]
.RBCP_WD(RBCP_WD), // out : Data[7:0]
.RBCP_WE(RBCP_WE), // out : Write enable
.RBCP_RE(RBCP_RE), // out : Read enable
.RBCP_ACK(RBCP_ACK), // in : Access acknowledge
.RBCP_RD(RBCP_RD) // in : Read data[7:0]
);
IOBUF i_iobuf_mdio(
.O(mdio_gem_i),
.IO(ETH_MDIO),
.I(mdio_gem_o),
.T(mdio_gem_t)
);
wire BUS_WR, BUS_RD;
wire [31:0] BUS_ADD;
wire [7:0] BUS_DATA;
wire INVALID;
tcp_to_bus itcp_to_bus(
.BUS_RST(BUS_RST),
.BUS_CLK(BUS_CLK),
.TCP_RX_WC(TCP_RX_WC),
.TCP_RX_WR(TCP_RX_WR),
.TCP_RX_DATA(TCP_RX_DATA),
.RBCP_ACT(RBCP_ACT),
.RBCP_ADDR(RBCP_ADDR),
.RBCP_WD(RBCP_WD),
.RBCP_WE(RBCP_WE),
.RBCP_RE(RBCP_RE),
.RBCP_ACK(RBCP_ACK),
.RBCP_RD(RBCP_RD),
.BUS_WR(BUS_WR),
.BUS_RD(BUS_RD),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.INVALID(INVALID)
);
//MODULE ADDRESSES
localparam CMD_BASEADDR = 32'h0000;
localparam CMD_HIGHADDR = 32'h8000-1;
localparam RX4_BASEADDR = 32'h8300;
localparam RX4_HIGHADDR = 32'h8400-1;
localparam RX3_BASEADDR = 32'h8400;
localparam RX3_HIGHADDR = 32'h8500-1;
localparam RX2_BASEADDR = 32'h8500;
localparam RX2_HIGHADDR = 32'h8600-1;
localparam RX1_BASEADDR = 32'h8600;
localparam RX1_HIGHADDR = 32'h8700-1;
localparam GPIO_BASEADDR = 32'h8700;
localparam GPIO_HIGHADDR = 32'h8800-1;
localparam I2C_BASEADDR = 32'h8800;
localparam I2C_HIGHADDR = 32'h8900-1;
// MODULES //
cmd_seq #(
.BASEADDR(CMD_BASEADDR),
.HIGHADDR(CMD_HIGHADDR),
.ABUSWIDTH(32)
) icmd (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CMD_CLK_OUT(CMD_CLK),
.CMD_CLK_IN(CLK40),
.CMD_EXT_START_FLAG(1'b0),
.CMD_EXT_START_ENABLE(),
.CMD_DATA(CMD_DATA),
.CMD_READY(),
.CMD_START_FLAG()
);
wire [3:0] RX_READY, RX_8B10B_DECODER_ERR, RX_FIFO_OVERFLOW_ERR, RX_FIFO_FULL;
wire [3:0] FE_FIFO_READ;
wire [3:0] FE_FIFO_EMPTY;
wire [31:0] FE_FIFO_DATA [3:0];
genvar i;
generate
for (i = 0; i < 1; i = i + 1) begin: rx_gen
fei4_rx #(
.BASEADDR(RX1_BASEADDR-16'h0100*i),
.HIGHADDR(RX1_HIGHADDR-16'h0100*i),
.DSIZE(10),
.DATA_IDENTIFIER(i+1),
.ABUSWIDTH(32)
) i_fei4_rx (
.RX_CLK(RX_160_CLK),
.RX_CLK2X(RX_320_CLK),
.RX_CLK2X_IOCE(RX_320_IOCE),
.DATA_CLK(RX_16_CLK),
.RX_DATA(DOBOUT[i]),
.RX_READY(RX_READY[i]),
.RX_8B10B_DECODER_ERR(RX_8B10B_DECODER_ERR[i]),
.RX_FIFO_OVERFLOW_ERR(RX_FIFO_OVERFLOW_ERR[i]),
.FIFO_CLK(1'b0),
.FIFO_READ(FE_FIFO_READ[i]),
.FIFO_EMPTY(FE_FIFO_EMPTY[i]),
.FIFO_DATA(FE_FIFO_DATA[i]),
.RX_FIFO_FULL(RX_FIFO_FULL[i]),
.RX_ENABLED(),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR)
);
end
endgenerate
/*
gpio
#(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(32),
.IO_WIDTH(8),
.IO_DIRECTION(8'h0f)
) i_gpio
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO({GPIO_DIP, GPIO_LED})
);
*/
wire I2C_CLK, I2C_CLK_PRE;
clock_divider #( .DIVISOR(4000) ) i2c_clkdev ( .CLK(BUS_CLK), .RESET(BUS_RST), .CE(), .CLOCK(I2C_CLK_PRE) );
BUFG BUFG_I2C ( .O(I2C_CLK), .I(I2C_CLK_PRE) );
i2c
#(
.BASEADDR(I2C_BASEADDR),
.HIGHADDR(I2C_HIGHADDR),
.ABUSWIDTH(32),
.MEM_BYTES(8)
) i_i2c
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.I2C_CLK(I2C_CLK),
.I2C_SDA(SDA),
.I2C_SCL(SCL)
);
//assign FE_FIFO_EMPTY[0] = 1;
//assign FE_FIFO_EMPTY[1] = 1;
//assign FE_FIFO_EMPTY[2] = 1;
//assign FE_FIFO_EMPTY[3] = 1;
wire ARB_READY_OUT, ARB_WRITE_OUT;
wire [31:0] ARB_DATA_OUT;
wire [3:0] READ_GRANT;
/*
rrp_arbiter #(
.WIDTH(4)
) i_rrp_arbiter (
.RST(BUS_RST),
.CLK(BUS_CLK),
.WRITE_REQ({~FE_FIFO_EMPTY}),
.HOLD_REQ({4'b0}),
.DATA_IN({FE_FIFO_DATA[3],FE_FIFO_DATA[2],FE_FIFO_DATA[1], FE_FIFO_DATA[0]}),
.READ_GRANT(READ_GRANT),
.READY_OUT(ARB_READY_OUT),
.WRITE_OUT(ARB_WRITE_OUT),
.DATA_OUT(ARB_DATA_OUT)
);
assign FE_FIFO_READ = READ_GRANT[3:0];
*/
assign ARB_DATA_OUT = FE_FIFO_DATA[0];
assign FE_FIFO_READ[0] = ARB_READY_OUT;
assign ARB_WRITE_OUT = ~FE_FIFO_EMPTY[0];
wire FIFO_EMPTY, FIFO_FULL;
fifo_32_to_8 #(.DEPTH(1*256)) i_data_fifo (
.RST(BUS_RST),
.CLK(BUS_CLK),
.WRITE(ARB_WRITE_OUT),
.READ(TCP_TX_WR),
.DATA_IN(ARB_DATA_OUT),
.FULL(FIFO_FULL),
.EMPTY(FIFO_EMPTY),
.DATA_OUT(TCP_TX_DATA)
);
assign ARB_READY_OUT = !FIFO_FULL;
assign TCP_TX_WR = !TCP_TX_FULL && !FIFO_EMPTY;
assign GPIO_LED = RX_READY;
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
module state_machine_counter #(
parameter INTR_TYPE = 1'b1
)(
clk,
reset_n,
pulse_irq_counter_stop,
global_enable_reg,
counter_start,
counter_stop,
enable,
c_idle,
level_reset,
data_store
);
input wire clk;
input wire reset_n;
input wire pulse_irq_counter_stop;
input wire global_enable_reg;
input wire counter_start;
input wire counter_stop;
output reg enable;
output reg level_reset;
output reg data_store;
output reg c_idle;
reg [1:0] state ;
reg [1:0] next_state ;
localparam IDLE =2'b00;
localparam START =2'b01;
localparam STOP =2'b10;
localparam STORE =2'b11;
//State machine Sequential logic
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n) state <= IDLE;
else state<= next_state;
end
//State Machine Transitional conditions
always @(state or counter_start or counter_stop or pulse_irq_counter_stop or global_enable_reg)
begin
case (state)
IDLE: if (counter_start==1'b0 || global_enable_reg == 1'b0 || pulse_irq_counter_stop==1'b1) begin
next_state = IDLE; // active low reset signal
end else begin
next_state = START;
end
START: if (global_enable_reg == 1'b0) begin
next_state = IDLE;
end
else if ((INTR_TYPE == 0 & counter_stop==1'b1) |(INTR_TYPE == 1 & pulse_irq_counter_stop==1'b1))
begin
next_state = STOP;
end
else
begin
next_state = START;
end
STOP: begin
next_state = STORE;
end
STORE: begin
next_state = IDLE;
end
default:next_state = IDLE;
endcase
end
//combo logic function to control counter
always @ (state) begin
case (state)
IDLE: begin
enable = 1'b0;
level_reset = 1'b0;
data_store = 1'b0;
c_idle = 1'b1;
end
START: begin
enable = 1'b1;
level_reset = 1'b1;
data_store = 1'b0;
c_idle = 1'b0;
end
STOP: begin
enable = 1'b0;
level_reset = 1'b1;
data_store = 1'b0;
c_idle = 1'b0;
end
STORE: begin
enable = 1'b0;
level_reset = 1'b1;
data_store = 1'b1;
c_idle = 1'b0;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2AI_4_V
`define SKY130_FD_SC_HDLL__O2BB2AI_4_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2AI_4_V
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2011 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(*i $Id: Zdiv.v 13323 2010-07-24 15:57:30Z herbelin $ i*)
(* Contribution by Claude Marché and Xavier Urbain *)
(** Euclidean Division
Defines first of function that allows Coq to normalize.
Then only after proves the main required property.
*)
Require Export ZArith_base.
Require Import Zbool.
Require Import Omega.
Require Import ZArithRing.
Require Import Zcomplements.
Require Export Setoid.
Open Local Scope Z_scope.
(** * Definitions of Euclidian operations *)
(** Euclidean division of a positive by a integer
(that is supposed to be positive).
Total function than returns an arbitrary value when
divisor is not positive
*)
Unboxed Fixpoint Zdiv_eucl_POS (a:positive) (b:Z) : Z * Z :=
match a with
| xH => if Zge_bool b 2 then (0, 1) else (1, 0)
| xO a' =>
let (q, r) := Zdiv_eucl_POS a' b in
let r' := 2 * r in
if Zgt_bool b r' then (2 * q, r') else (2 * q + 1, r' - b)
| xI a' =>
let (q, r) := Zdiv_eucl_POS a' b in
let r' := 2 * r + 1 in
if Zgt_bool b r' then (2 * q, r') else (2 * q + 1, r' - b)
end.
(** Euclidean division of integers.
Total function than returns (0,0) when dividing by 0.
*)
(**
The pseudo-code is:
if b = 0 : (0,0)
if b <> 0 and a = 0 : (0,0)
if b > 0 and a < 0 : let (q,r) = div_eucl_pos (-a) b in
if r = 0 then (-q,0) else (-(q+1),b-r)
if b < 0 and a < 0 : let (q,r) = div_eucl (-a) (-b) in (q,-r)
if b < 0 and a > 0 : let (q,r) = div_eucl a (-b) in
if r = 0 then (-q,0) else (-(q+1),b+r)
In other word, when b is non-zero, q is chosen to be the greatest integer
smaller or equal to a/b. And sgn(r)=sgn(b) and |r| < |b| (at least when
r is not null).
*)
(* Nota: At least two others conventions also exist for euclidean division.
They all satify the equation a=b*q+r, but differ on the choice of (q,r)
on negative numbers.
* Ocaml uses Round-Toward-Zero division: (-a)/b = a/(-b) = -(a/b).
Hence (-a) mod b = - (a mod b)
a mod (-b) = a mod b
And: |r| < |b| and sgn(r) = sgn(a) (notice the a here instead of b).
* Another solution is to always pick a non-negative remainder:
a=b*q+r with 0 <= r < |b|
*)
Definition Zdiv_eucl (a b:Z) : Z * Z :=
match a, b with
| Z0, _ => (0, 0)
| _, Z0 => (0, 0)
| Zpos a', Zpos _ => Zdiv_eucl_POS a' b
| Zneg a', Zpos _ =>
let (q, r) := Zdiv_eucl_POS a' b in
match r with
| Z0 => (- q, 0)
| _ => (- (q + 1), b - r)
end
| Zneg a', Zneg b' => let (q, r) := Zdiv_eucl_POS a' (Zpos b') in (q, - r)
| Zpos a', Zneg b' =>
let (q, r) := Zdiv_eucl_POS a' (Zpos b') in
match r with
| Z0 => (- q, 0)
| _ => (- (q + 1), b + r)
end
end.
(** Division and modulo are projections of [Zdiv_eucl] *)
Definition Zdiv (a b:Z) : Z := let (q, _) := Zdiv_eucl a b in q.
Definition Zmod (a b:Z) : Z := let (_, r) := Zdiv_eucl a b in r.
(** Syntax *)
Infix "/" := Zdiv : Z_scope.
Infix "mod" := Zmod (at level 40, no associativity) : Z_scope.
(* Tests:
Eval compute in (Zdiv_eucl 7 3).
Eval compute in (Zdiv_eucl (-7) 3).
Eval compute in (Zdiv_eucl 7 (-3)).
Eval compute in (Zdiv_eucl (-7) (-3)).
*)
(** * Main division theorem *)
(** First a lemma for two positive arguments *)
Lemma Z_div_mod_POS :
forall b:Z,
b > 0 ->
forall a:positive,
let (q, r) := Zdiv_eucl_POS a b in Zpos a = b * q + r /\ 0 <= r < b.
Proof.
simple induction a; cbv beta iota delta [Zdiv_eucl_POS] in |- *;
fold Zdiv_eucl_POS in |- *; cbv zeta.
intro p; case (Zdiv_eucl_POS p b); intros q r [H0 H1].
generalize (Zgt_cases b (2 * r + 1)).
case (Zgt_bool b (2 * r + 1));
(rewrite BinInt.Zpos_xI; rewrite H0; split; [ ring | omega ]).
intros p; case (Zdiv_eucl_POS p b); intros q r [H0 H1].
generalize (Zgt_cases b (2 * r)).
case (Zgt_bool b (2 * r)); rewrite BinInt.Zpos_xO;
change (Zpos (xO p)) with (2 * Zpos p) in |- *; rewrite H0;
(split; [ ring | omega ]).
generalize (Zge_cases b 2).
case (Zge_bool b 2); (intros; split; [ try ring | omega ]).
omega.
Qed.
(** Then the usual situation of a positive [b] and no restriction on [a] *)
Theorem Z_div_mod :
forall a b:Z,
b > 0 -> let (q, r) := Zdiv_eucl a b in a = b * q + r /\ 0 <= r < b.
Proof.
intros a b; case a; case b; try (simpl in |- *; intros; omega).
unfold Zdiv_eucl in |- *; intros; apply Z_div_mod_POS; trivial.
intros; discriminate.
intros.
generalize (Z_div_mod_POS (Zpos p) H p0).
unfold Zdiv_eucl in |- *.
case (Zdiv_eucl_POS p0 (Zpos p)).
intros z z0.
case z0.
intros [H1 H2].
split; trivial.
change (Zneg p0) with (- Zpos p0); rewrite H1; ring.
intros p1 [H1 H2].
split; trivial.
change (Zneg p0) with (- Zpos p0); rewrite H1; ring.
generalize (Zorder.Zgt_pos_0 p1); omega.
intros p1 [H1 H2].
split; trivial.
change (Zneg p0) with (- Zpos p0); rewrite H1; ring.
generalize (Zorder.Zlt_neg_0 p1); omega.
intros; discriminate.
Qed.
(** For stating the fully general result, let's give a short name
to the condition on the remainder. *)
Definition Remainder r b := 0 <= r < b \/ b < r <= 0.
(** Another equivalent formulation: *)
Definition Remainder_alt r b := Zabs r < Zabs b /\ Zsgn r <> - Zsgn b.
(* In the last formulation, [ Zsgn r <> - Zsgn b ] is less nice than saying
[ Zsgn r = Zsgn b ], but at least it works even when [r] is null. *)
Lemma Remainder_equiv : forall r b, Remainder r b <-> Remainder_alt r b.
Proof.
intros; unfold Remainder, Remainder_alt; omega with *.
Qed.
Hint Unfold Remainder.
(** Now comes the fully general result about Euclidean division. *)
Theorem Z_div_mod_full :
forall a b:Z,
b <> 0 -> let (q, r) := Zdiv_eucl a b in a = b * q + r /\ Remainder r b.
Proof.
destruct b as [|b|b].
(* b = 0 *)
intro H; elim H; auto.
(* b > 0 *)
intros _.
assert (Zpos b > 0) by auto with zarith.
generalize (Z_div_mod a (Zpos b) H).
destruct Zdiv_eucl as (q,r); intuition; simpl; auto.
(* b < 0 *)
intros _.
assert (Zpos b > 0) by auto with zarith.
generalize (Z_div_mod a (Zpos b) H).
unfold Remainder.
destruct a as [|a|a].
(* a = 0 *)
simpl; intuition.
(* a > 0 *)
unfold Zdiv_eucl; destruct Zdiv_eucl_POS as (q,r).
destruct r as [|r|r]; [ | | omega with *].
rewrite <- Zmult_opp_comm; simpl Zopp; intuition.
rewrite <- Zmult_opp_comm; simpl Zopp.
rewrite Zmult_plus_distr_r; omega with *.
(* a < 0 *)
unfold Zdiv_eucl.
generalize (Z_div_mod_POS (Zpos b) H a).
destruct Zdiv_eucl_POS as (q,r).
destruct r as [|r|r]; change (Zneg b) with (-Zpos b).
rewrite Zmult_opp_comm; omega with *.
rewrite <- Zmult_opp_comm, Zmult_plus_distr_r;
repeat rewrite Zmult_opp_comm; omega.
rewrite Zmult_opp_comm; omega with *.
Qed.
(** The same results as before, stated separately in terms of Zdiv and Zmod *)
Lemma Z_mod_remainder : forall a b:Z, b<>0 -> Remainder (a mod b) b.
Proof.
unfold Zmod; intros a b Hb; generalize (Z_div_mod_full a b Hb); auto.
destruct Zdiv_eucl; tauto.
Qed.
Lemma Z_mod_lt : forall a b:Z, b > 0 -> 0 <= a mod b < b.
Proof.
unfold Zmod; intros a b Hb; generalize (Z_div_mod a b Hb).
destruct Zdiv_eucl; tauto.
Qed.
Lemma Z_mod_neg : forall a b:Z, b < 0 -> b < a mod b <= 0.
Proof.
unfold Zmod; intros a b Hb.
assert (Hb' : b<>0) by (auto with zarith).
generalize (Z_div_mod_full a b Hb').
destruct Zdiv_eucl.
unfold Remainder; intuition.
Qed.
Lemma Z_div_mod_eq_full : forall a b:Z, b <> 0 -> a = b*(a/b) + (a mod b).
Proof.
unfold Zdiv, Zmod; intros a b Hb; generalize (Z_div_mod_full a b Hb).
destruct Zdiv_eucl; tauto.
Qed.
Lemma Z_div_mod_eq : forall a b:Z, b > 0 -> a = b*(a/b) + (a mod b).
Proof.
intros; apply Z_div_mod_eq_full; auto with zarith.
Qed.
Lemma Zmod_eq_full : forall a b:Z, b<>0 -> a mod b = a - (a/b)*b.
Proof.
intros.
rewrite <- Zeq_plus_swap, Zplus_comm, Zmult_comm; symmetry.
apply Z_div_mod_eq_full; auto.
Qed.
Lemma Zmod_eq : forall a b:Z, b>0 -> a mod b = a - (a/b)*b.
Proof.
intros.
rewrite <- Zeq_plus_swap, Zplus_comm, Zmult_comm; symmetry.
apply Z_div_mod_eq; auto.
Qed.
(** Existence theorem *)
Theorem Zdiv_eucl_exist : forall (b:Z)(Hb:b>0)(a:Z),
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < b}.
Proof.
intros b Hb a.
exists (Zdiv_eucl a b).
exact (Z_div_mod a b Hb).
Qed.
Implicit Arguments Zdiv_eucl_exist.
(** Uniqueness theorems *)
Theorem Zdiv_mod_unique :
forall b q1 q2 r1 r2:Z,
0 <= r1 < Zabs b -> 0 <= r2 < Zabs b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof.
intros b q1 q2 r1 r2 Hr1 Hr2 H.
destruct (Z_eq_dec q1 q2) as [Hq|Hq].
split; trivial.
rewrite Hq in H; omega.
elim (Zlt_not_le (Zabs (r2 - r1)) (Zabs b)).
omega with *.
replace (r2-r1) with (b*(q1-q2)) by (rewrite Zmult_minus_distr_l; omega).
replace (Zabs b) with ((Zabs b)*1) by ring.
rewrite Zabs_Zmult.
apply Zmult_le_compat_l; auto with *.
omega with *.
Qed.
Theorem Zdiv_mod_unique_2 :
forall b q1 q2 r1 r2:Z,
Remainder r1 b -> Remainder r2 b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof.
unfold Remainder.
intros b q1 q2 r1 r2 Hr1 Hr2 H.
destruct (Z_eq_dec q1 q2) as [Hq|Hq].
split; trivial.
rewrite Hq in H; omega.
elim (Zlt_not_le (Zabs (r2 - r1)) (Zabs b)).
omega with *.
replace (r2-r1) with (b*(q1-q2)) by (rewrite Zmult_minus_distr_l; omega).
replace (Zabs b) with ((Zabs b)*1) by ring.
rewrite Zabs_Zmult.
apply Zmult_le_compat_l; auto with *.
omega with *.
Qed.
Theorem Zdiv_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> q = a/b.
Proof.
intros.
assert (b <> 0) by (unfold Remainder in *; omega with *).
generalize (Z_div_mod_full a b H1).
unfold Zdiv; destruct Zdiv_eucl as (q',r').
intros (H2,H3); rewrite H2 in H0.
destruct (Zdiv_mod_unique_2 b q q' r r'); auto.
Qed.
Theorem Zdiv_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> q = a/b.
Proof.
intros; eapply Zdiv_unique_full; eauto.
Qed.
Theorem Zmod_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> r = a mod b.
Proof.
intros.
assert (b <> 0) by (unfold Remainder in *; omega with *).
generalize (Z_div_mod_full a b H1).
unfold Zmod; destruct Zdiv_eucl as (q',r').
intros (H2,H3); rewrite H2 in H0.
destruct (Zdiv_mod_unique_2 b q q' r r'); auto.
Qed.
Theorem Zmod_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> r = a mod b.
Proof.
intros; eapply Zmod_unique_full; eauto.
Qed.
(** * Basic values of divisions and modulo. *)
Lemma Zmod_0_l: forall a, 0 mod a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zmod_0_r: forall a, a mod 0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_l: forall a, 0/a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_r: forall a, a/0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zmod_1_r: forall a, a mod 1 = 0.
Proof.
intros; symmetry; apply Zmod_unique with a; auto with zarith.
Qed.
Lemma Zdiv_1_r: forall a, a/1 = a.
Proof.
intros; symmetry; apply Zdiv_unique with 0; auto with zarith.
Qed.
Hint Resolve Zmod_0_l Zmod_0_r Zdiv_0_l Zdiv_0_r Zdiv_1_r Zmod_1_r
: zarith.
Lemma Zdiv_1_l: forall a, 1 < a -> 1/a = 0.
Proof.
intros; symmetry; apply Zdiv_unique with 1; auto with zarith.
Qed.
Lemma Zmod_1_l: forall a, 1 < a -> 1 mod a = 1.
Proof.
intros; symmetry; apply Zmod_unique with 0; auto with zarith.
Qed.
Lemma Z_div_same_full : forall a:Z, a<>0 -> a/a = 1.
Proof.
intros; symmetry; apply Zdiv_unique_full with 0; auto with *; red; omega.
Qed.
Lemma Z_mod_same_full : forall a, a mod a = 0.
Proof.
destruct a; intros; symmetry.
compute; auto.
apply Zmod_unique with 1; auto with *; omega with *.
apply Zmod_unique_full with 1; auto with *; red; omega with *.
Qed.
Lemma Z_mod_mult : forall a b, (a*b) mod b = 0.
Proof.
intros a b; destruct (Z_eq_dec b 0) as [Hb|Hb].
subst; simpl; rewrite Zmod_0_r; auto.
symmetry; apply Zmod_unique_full with a; [ red; omega | ring ].
Qed.
Lemma Z_div_mult_full : forall a b:Z, b <> 0 -> (a*b)/b = a.
Proof.
intros; symmetry; apply Zdiv_unique_full with 0; auto with zarith;
[ red; omega | ring].
Qed.
(** * Order results about Zmod and Zdiv *)
(* Division of positive numbers is positive. *)
Lemma Z_div_pos: forall a b, b > 0 -> 0 <= a -> 0 <= a/b.
Proof.
intros.
rewrite (Z_div_mod_eq a b H) in H0.
assert (H1:=Z_mod_lt a b H).
destruct (Z_lt_le_dec (a/b) 0); auto.
assert (b*(a/b) <= -b).
replace (-b) with (b*-1); [ | ring].
apply Zmult_le_compat_l; auto with zarith.
omega.
Qed.
Lemma Z_div_ge0: forall a b, b > 0 -> a >= 0 -> a/b >=0.
Proof.
intros; generalize (Z_div_pos a b H); auto with zarith.
Qed.
(** As soon as the divisor is greater or equal than 2,
the division is strictly decreasing. *)
Lemma Z_div_lt : forall a b:Z, b >= 2 -> a > 0 -> a/b < a.
Proof.
intros. cut (b > 0); [ intro Hb | omega ].
generalize (Z_div_mod a b Hb).
cut (a >= 0); [ intro Ha | omega ].
generalize (Z_div_ge0 a b Hb Ha).
unfold Zdiv in |- *; case (Zdiv_eucl a b); intros q r H1 [H2 H3].
cut (a >= 2 * q -> q < a); [ intro h; apply h; clear h | intros; omega ].
apply Zge_trans with (b * q).
omega.
auto with zarith.
Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem Zdiv_small: forall a b, 0 <= a < b -> a/b = 0.
Proof.
intros a b H; apply sym_equal; apply Zdiv_unique with a; auto with zarith.
Qed.
(** Same situation, in term of modulo: *)
Theorem Zmod_small: forall a n, 0 <= a < n -> a mod n = a.
Proof.
intros a b H; apply sym_equal; apply Zmod_unique with 0; auto with zarith.
Qed.
(** [Zge] is compatible with a positive division. *)
Lemma Z_div_ge : forall a b c:Z, c > 0 -> a >= b -> a/c >= b/c.
Proof.
intros a b c cPos aGeb.
generalize (Z_div_mod_eq a c cPos).
generalize (Z_mod_lt a c cPos).
generalize (Z_div_mod_eq b c cPos).
generalize (Z_mod_lt b c cPos).
intros.
elim (Z_ge_lt_dec (a / c) (b / c)); trivial.
intro.
absurd (b - a >= 1).
omega.
replace (b-a) with (c * (b/c-a/c) + b mod c - a mod c) by
(symmetry; pattern a at 1; rewrite H2; pattern b at 1; rewrite H0; ring).
assert (c * (b / c - a / c) >= c * 1).
apply Zmult_ge_compat_l.
omega.
omega.
assert (c * 1 = c).
ring.
omega.
Qed.
(** Same, with [Zle]. *)
Lemma Z_div_le : forall a b c:Z, c > 0 -> a <= b -> a/c <= b/c.
Proof.
intros a b c H H0.
apply Zge_le.
apply Z_div_ge; auto with *.
Qed.
(** With our choice of division, rounding of (a/b) is always done toward bottom: *)
Lemma Z_mult_div_ge : forall a b:Z, b > 0 -> b*(a/b) <= a.
Proof.
intros a b H; generalize (Z_div_mod_eq a b H) (Z_mod_lt a b H); omega.
Qed.
Lemma Z_mult_div_ge_neg : forall a b:Z, b < 0 -> b*(a/b) >= a.
Proof.
intros a b H.
generalize (Z_div_mod_eq_full a _ (Zlt_not_eq _ _ H)) (Z_mod_neg a _ H); omega.
Qed.
(** The previous inequalities are exact iff the modulo is zero. *)
Lemma Z_div_exact_full_1 : forall a b:Z, a = b*(a/b) -> a mod b = 0.
Proof.
intros; destruct (Z_eq_dec b 0) as [Hb|Hb].
subst b; simpl in *; subst; auto.
generalize (Z_div_mod_eq_full a b Hb); omega.
Qed.
Lemma Z_div_exact_full_2 : forall a b:Z, b <> 0 -> a mod b = 0 -> a = b*(a/b).
Proof.
intros; generalize (Z_div_mod_eq_full a b H); omega.
Qed.
(** A modulo cannot grow beyond its starting point. *)
Theorem Zmod_le: forall a b, 0 < b -> 0 <= a -> a mod b <= a.
Proof.
intros a b H1 H2; case (Zle_or_lt b a); intros H3.
case (Z_mod_lt a b); auto with zarith.
rewrite Zmod_small; auto with zarith.
Qed.
(** Some additionnal inequalities about Zdiv. *)
Theorem Zdiv_lt_upper_bound:
forall a b q, 0 < b -> a < q*b -> a/b < q.
Proof.
intros a b q H1 H2.
apply Zmult_lt_reg_r with b; auto with zarith.
apply Zle_lt_trans with (2 := H2).
pattern a at 2; rewrite (Z_div_mod_eq a b); auto with zarith.
rewrite (Zmult_comm b); case (Z_mod_lt a b); auto with zarith.
Qed.
Theorem Zdiv_le_upper_bound:
forall a b q, 0 < b -> a <= q*b -> a/b <= q.
Proof.
intros.
rewrite <- (Z_div_mult_full q b); auto with zarith.
apply Z_div_le; auto with zarith.
Qed.
Theorem Zdiv_le_lower_bound:
forall a b q, 0 < b -> q*b <= a -> q <= a/b.
Proof.
intros.
rewrite <- (Z_div_mult_full q b); auto with zarith.
apply Z_div_le; auto with zarith.
Qed.
(** A division of respect opposite monotonicity for the divisor *)
Lemma Zdiv_le_compat_l: forall p q r, 0 <= p -> 0 < q < r ->
p / r <= p / q.
Proof.
intros p q r H H1.
apply Zdiv_le_lower_bound; auto with zarith.
rewrite Zmult_comm.
pattern p at 2; rewrite (Z_div_mod_eq p r); auto with zarith.
apply Zle_trans with (r * (p / r)); auto with zarith.
apply Zmult_le_compat_r; auto with zarith.
apply Zdiv_le_lower_bound; auto with zarith.
case (Z_mod_lt p r); auto with zarith.
Qed.
Theorem Zdiv_sgn: forall a b,
0 <= Zsgn (a/b) * Zsgn a * Zsgn b.
Proof.
destruct a as [ |a|a]; destruct b as [ |b|b]; simpl; auto with zarith;
generalize (Z_div_pos (Zpos a) (Zpos b)); unfold Zdiv, Zdiv_eucl;
destruct Zdiv_eucl_POS as (q,r); destruct r; omega with *.
Qed.
(** * Relations between usual operations and Zmod and Zdiv *)
Lemma Z_mod_plus_full : forall a b c:Z, (a + b * c) mod c = a mod c.
Proof.
intros; destruct (Z_eq_dec c 0) as [Hc|Hc].
subst; do 2 rewrite Zmod_0_r; auto.
symmetry; apply Zmod_unique_full with (a/c+b); auto with zarith.
red; generalize (Z_mod_lt a c)(Z_mod_neg a c); omega.
rewrite Zmult_plus_distr_r, Zmult_comm.
generalize (Z_div_mod_eq_full a c Hc); omega.
Qed.
Lemma Z_div_plus_full : forall a b c:Z, c <> 0 -> (a + b * c) / c = a / c + b.
Proof.
intro; symmetry.
apply Zdiv_unique_full with (a mod c); auto with zarith.
red; generalize (Z_mod_lt a c)(Z_mod_neg a c); omega.
rewrite Zmult_plus_distr_r, Zmult_comm.
generalize (Z_div_mod_eq_full a c H); omega.
Qed.
Theorem Z_div_plus_full_l: forall a b c : Z, b <> 0 -> (a * b + c) / b = a + c / b.
Proof.
intros a b c H; rewrite Zplus_comm; rewrite Z_div_plus_full;
try apply Zplus_comm; auto with zarith.
Qed.
(** [Zopp] and [Zdiv], [Zmod].
Due to the choice of convention for our Euclidean division,
some of the relations about [Zopp] and divisions are rather complex. *)
Lemma Zdiv_opp_opp : forall a b:Z, (-a)/(-b) = a/b.
Proof.
intros [|a|a] [|b|b]; try reflexivity; unfold Zdiv; simpl;
destruct (Zdiv_eucl_POS a (Zpos b)); destruct z0; try reflexivity.
Qed.
Lemma Zmod_opp_opp : forall a b:Z, (-a) mod (-b) = - (a mod b).
Proof.
intros; destruct (Z_eq_dec b 0) as [Hb|Hb].
subst; do 2 rewrite Zmod_0_r; auto.
intros; symmetry.
apply Zmod_unique_full with ((-a)/(-b)); auto.
generalize (Z_mod_remainder a b Hb); destruct 1; [right|left]; omega.
rewrite Zdiv_opp_opp.
pattern a at 1; rewrite (Z_div_mod_eq_full a b Hb); ring.
Qed.
Lemma Z_mod_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a) mod b = 0.
Proof.
intros; destruct (Z_eq_dec b 0) as [Hb|Hb].
subst; rewrite Zmod_0_r; auto.
rewrite Z_div_exact_full_2 with a b; auto.
replace (- (b * (a / b))) with (0 + - (a / b) * b).
rewrite Z_mod_plus_full; auto.
ring.
Qed.
Lemma Z_mod_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a) mod b = b - (a mod b).
Proof.
intros.
assert (b<>0) by (contradict H; subst; rewrite Zmod_0_r; auto).
symmetry; apply Zmod_unique_full with (-1-a/b); auto.
generalize (Z_mod_remainder a b H0); destruct 1; [left|right]; omega.
rewrite Zmult_minus_distr_l.
pattern a at 1; rewrite (Z_div_mod_eq_full a b H0); ring.
Qed.
Lemma Z_mod_zero_opp_r : forall a b:Z, a mod b = 0 -> a mod (-b) = 0.
Proof.
intros.
rewrite <- (Zopp_involutive a).
rewrite Zmod_opp_opp.
rewrite Z_mod_zero_opp_full; auto.
Qed.
Lemma Z_mod_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a mod (-b) = (a mod b) - b.
Proof.
intros.
pattern a at 1; rewrite <- (Zopp_involutive a).
rewrite Zmod_opp_opp.
rewrite Z_mod_nz_opp_full; auto; omega.
Qed.
Lemma Z_div_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a)/b = -(a/b).
Proof.
intros; destruct (Z_eq_dec b 0) as [Hb|Hb].
subst; do 2 rewrite Zdiv_0_r; auto.
symmetry; apply Zdiv_unique_full with 0; auto.
red; omega.
pattern a at 1; rewrite (Z_div_mod_eq_full a b Hb).
rewrite H; ring.
Qed.
Lemma Z_div_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a)/b = -(a/b)-1.
Proof.
intros.
assert (b<>0) by (contradict H; subst; rewrite Zmod_0_r; auto).
symmetry; apply Zdiv_unique_full with (b-a mod b); auto.
generalize (Z_mod_remainder a b H0); destruct 1; [left|right]; omega.
pattern a at 1; rewrite (Z_div_mod_eq_full a b H0); ring.
Qed.
Lemma Z_div_zero_opp_r : forall a b:Z, a mod b = 0 -> a/(-b) = -(a/b).
Proof.
intros.
pattern a at 1; rewrite <- (Zopp_involutive a).
rewrite Zdiv_opp_opp.
rewrite Z_div_zero_opp_full; auto.
Qed.
Lemma Z_div_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a/(-b) = -(a/b)-1.
Proof.
intros.
pattern a at 1; rewrite <- (Zopp_involutive a).
rewrite Zdiv_opp_opp.
rewrite Z_div_nz_opp_full; auto; omega.
Qed.
(** Cancellations. *)
Lemma Zdiv_mult_cancel_r : forall a b c:Z,
c <> 0 -> (a*c)/(b*c) = a/b.
Proof.
assert (X: forall a b c, b > 0 -> c > 0 -> (a*c) / (b*c) = a / b).
intros a b c Hb Hc.
symmetry.
apply Zdiv_unique with ((a mod b)*c); auto with zarith.
destruct (Z_mod_lt a b Hb); split.
apply Zmult_le_0_compat; auto with zarith.
apply Zmult_lt_compat_r; auto with zarith.
pattern a at 1; rewrite (Z_div_mod_eq a b Hb); ring.
intros a b c Hc.
destruct (Z_dec b 0) as [Hb|Hb].
destruct Hb as [Hb|Hb]; destruct (not_Zeq_inf _ _ Hc); auto with *.
rewrite <- (Zdiv_opp_opp a), <- (Zmult_opp_opp b), <-(Zmult_opp_opp a);
auto with *.
rewrite <- (Zdiv_opp_opp a), <- Zdiv_opp_opp, Zopp_mult_distr_l,
Zopp_mult_distr_l; auto with *.
rewrite <- Zdiv_opp_opp, Zopp_mult_distr_r, Zopp_mult_distr_r; auto with *.
rewrite Hb; simpl; do 2 rewrite Zdiv_0_r; auto.
Qed.
Lemma Zdiv_mult_cancel_l : forall a b c:Z,
c<>0 -> (c*a)/(c*b) = a/b.
Proof.
intros.
rewrite (Zmult_comm c a); rewrite (Zmult_comm c b).
apply Zdiv_mult_cancel_r; auto.
Qed.
Lemma Zmult_mod_distr_l: forall a b c,
(c*a) mod (c*b) = c * (a mod b).
Proof.
intros; destruct (Z_eq_dec c 0) as [Hc|Hc].
subst; simpl; rewrite Zmod_0_r; auto.
destruct (Z_eq_dec b 0) as [Hb|Hb].
subst; repeat rewrite Zmult_0_r || rewrite Zmod_0_r; auto.
assert (c*b <> 0).
contradict Hc; eapply Zmult_integral_l; eauto.
rewrite (Zplus_minus_eq _ _ _ (Z_div_mod_eq_full (c*a) (c*b) H)).
rewrite (Zplus_minus_eq _ _ _ (Z_div_mod_eq_full a b Hb)).
rewrite Zdiv_mult_cancel_l; auto with zarith.
ring.
Qed.
Lemma Zmult_mod_distr_r: forall a b c,
(a*c) mod (b*c) = (a mod b) * c.
Proof.
intros; repeat rewrite (fun x => (Zmult_comm x c)).
apply Zmult_mod_distr_l; auto.
Qed.
(** Operations modulo. *)
Theorem Zmod_mod: forall a n, (a mod n) mod n = a mod n.
Proof.
intros; destruct (Z_eq_dec n 0) as [Hb|Hb].
subst; do 2 rewrite Zmod_0_r; auto.
pattern a at 2; rewrite (Z_div_mod_eq_full a n); auto with zarith.
rewrite Zplus_comm; rewrite Zmult_comm.
apply sym_equal; apply Z_mod_plus_full; auto with zarith.
Qed.
Theorem Zmult_mod: forall a b n,
(a * b) mod n = ((a mod n) * (b mod n)) mod n.
Proof.
intros; destruct (Z_eq_dec n 0) as [Hb|Hb].
subst; do 2 rewrite Zmod_0_r; auto.
pattern a at 1; rewrite (Z_div_mod_eq_full a n); auto with zarith.
pattern b at 1; rewrite (Z_div_mod_eq_full b n); auto with zarith.
set (A:=a mod n); set (B:=b mod n); set (A':=a/n); set (B':=b/n).
replace ((n*A' + A) * (n*B' + B))
with (A*B + (A'*B+B'*A+n*A'*B')*n) by ring.
apply Z_mod_plus_full; auto with zarith.
Qed.
Theorem Zplus_mod: forall a b n,
(a + b) mod n = (a mod n + b mod n) mod n.
Proof.
intros; destruct (Z_eq_dec n 0) as [Hb|Hb].
subst; do 2 rewrite Zmod_0_r; auto.
pattern a at 1; rewrite (Z_div_mod_eq_full a n); auto with zarith.
pattern b at 1; rewrite (Z_div_mod_eq_full b n); auto with zarith.
replace ((n * (a / n) + a mod n) + (n * (b / n) + b mod n))
with ((a mod n + b mod n) + (a / n + b / n) * n) by ring.
apply Z_mod_plus_full; auto with zarith.
Qed.
Theorem Zminus_mod: forall a b n,
(a - b) mod n = (a mod n - b mod n) mod n.
Proof.
intros.
replace (a - b) with (a + (-1) * b); auto with zarith.
replace (a mod n - b mod n) with (a mod n + (-1) * (b mod n)); auto with zarith.
rewrite Zplus_mod.
rewrite Zmult_mod.
rewrite Zplus_mod with (b:=(-1) * (b mod n)).
rewrite Zmult_mod.
rewrite Zmult_mod with (b:= b mod n).
repeat rewrite Zmod_mod; auto.
Qed.
Lemma Zplus_mod_idemp_l: forall a b n, (a mod n + b) mod n = (a + b) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zplus_mod_idemp_r: forall a b n, (b + a mod n) mod n = (b + a) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_l: forall a b n, (a mod n - b) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_r: forall a b n, (a - b mod n) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zmult_mod_idemp_l: forall a b n, (a mod n * b) mod n = (a * b) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
Lemma Zmult_mod_idemp_r: forall a b n, (b * (a mod n)) mod n = (b * a) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
(** For a specific number N, equality modulo N is hence a nice setoid
equivalence, compatible with [+], [-] and [*]. *)
Definition eqm N a b := (a mod N = b mod N).
Lemma eqm_refl N : forall a, (eqm N) a a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_sym N : forall a b, (eqm N) a b -> (eqm N) b a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_trans N : forall a b c,
(eqm N) a b -> (eqm N) b c -> (eqm N) a c.
Proof. unfold eqm; eauto with *. Qed.
Add Parametric Relation N : Z (eqm N)
reflexivity proved by (eqm_refl N)
symmetry proved by (eqm_sym N)
transitivity proved by (eqm_trans N) as eqm_setoid.
Add Parametric Morphism N : Zplus
with signature (eqm N) ==> (eqm N) ==> (eqm N) as Zplus_eqm.
Proof.
unfold eqm; intros; rewrite Zplus_mod, H, H0, <- Zplus_mod; auto.
Qed.
Add Parametric Morphism N : Zminus
with signature (eqm N) ==> (eqm N) ==> (eqm N) as Zminus_eqm.
Proof.
unfold eqm; intros; rewrite Zminus_mod, H, H0, <- Zminus_mod; auto.
Qed.
Add Parametric Morphism N : Zmult
with signature (eqm N) ==> (eqm N) ==> (eqm N) as Zmult_eqm.
Proof.
unfold eqm; intros; rewrite Zmult_mod, H, H0, <- Zmult_mod; auto.
Qed.
Add Parametric Morphism N : Zopp
with signature (eqm N) ==> (eqm N) as Zopp_eqm.
Proof.
intros; change ((eqm N) (-x) (-y)) with ((eqm N) (0-x) (0-y)).
rewrite H; red; auto.
Qed.
Lemma Zmod_eqm N : forall a, (eqm N) (a mod N) a.
Proof.
intros; exact (Zmod_mod a N).
Qed.
(* NB: Zmod and Zdiv are not morphisms with respect to eqm.
For instance, let (==) be (eqm 2). Then we have (3 == 1) but:
~ (3 mod 3 == 1 mod 3)
~ (1 mod 3 == 1 mod 1)
~ (3/3 == 1/3)
~ (1/3 == 1/1)
*)
Lemma Zdiv_Zdiv : forall a b c, 0<=b -> 0<=c -> (a/b)/c = a/(b*c).
Proof.
intros a b c Hb Hc.
destruct (Zle_lt_or_eq _ _ Hb); [ | subst; rewrite Zdiv_0_r, Zdiv_0_r, Zdiv_0_l; auto].
destruct (Zle_lt_or_eq _ _ Hc); [ | subst; rewrite Zmult_0_r, Zdiv_0_r, Zdiv_0_r; auto].
pattern a at 2;rewrite (Z_div_mod_eq_full a b);auto with zarith.
pattern (a/b) at 2;rewrite (Z_div_mod_eq_full (a/b) c);auto with zarith.
replace (b * (c * (a / b / c) + (a / b) mod c) + a mod b) with
((a / b / c)*(b * c) + (b * ((a / b) mod c) + a mod b)) by ring.
rewrite Z_div_plus_full_l; auto with zarith.
rewrite (Zdiv_small (b * ((a / b) mod c) + a mod b)).
ring.
split.
apply Zplus_le_0_compat;auto with zarith.
apply Zmult_le_0_compat;auto with zarith.
destruct (Z_mod_lt (a/b) c);auto with zarith.
destruct (Z_mod_lt a b);auto with zarith.
apply Zle_lt_trans with (b * ((a / b) mod c) + (b-1)).
destruct (Z_mod_lt a b);auto with zarith.
apply Zle_lt_trans with (b * (c-1) + (b - 1)).
apply Zplus_le_compat;auto with zarith.
destruct (Z_mod_lt (a/b) c);auto with zarith.
replace (b * (c - 1) + (b - 1)) with (b*c-1);try ring;auto with zarith.
intro H1;
assert (H2: c <> 0) by auto with zarith;
rewrite (Zmult_integral_l _ _ H2 H1) in H; auto with zarith.
Qed.
(** Unfortunately, the previous result isn't always true on negative numbers.
For instance: 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) *)
(** A last inequality: *)
Theorem Zdiv_mult_le:
forall a b c, 0<=a -> 0<=b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof.
intros a b c H1 H2 H3.
destruct (Zle_lt_or_eq _ _ H2);
[ | subst; rewrite Zdiv_0_r, Zdiv_0_r, Zmult_0_r; auto].
case (Z_mod_lt a b); auto with zarith; intros Hu1 Hu2.
case (Z_mod_lt c b); auto with zarith; intros Hv1 Hv2.
apply Zmult_le_reg_r with b; auto with zarith.
rewrite <- Zmult_assoc.
replace (a / b * b) with (a - a mod b).
replace (c * a / b * b) with (c * a - (c * a) mod b).
rewrite Zmult_minus_distr_l.
unfold Zminus; apply Zplus_le_compat_l.
match goal with |- - ?X <= -?Y => assert (Y <= X); auto with zarith end.
apply Zle_trans with ((c mod b) * (a mod b)); auto with zarith.
rewrite Zmult_mod; auto with zarith.
apply (Zmod_le ((c mod b) * (a mod b)) b); auto with zarith.
apply Zmult_le_compat_r; auto with zarith.
apply (Zmod_le c b); auto.
pattern (c * a) at 1; rewrite (Z_div_mod_eq (c * a) b); try ring;
auto with zarith.
pattern a at 1; rewrite (Z_div_mod_eq a b); try ring; auto with zarith.
Qed.
(** Zmod is related to divisibility (see more in Znumtheory) *)
Lemma Zmod_divides : forall a b, b<>0 ->
(a mod b = 0 <-> exists c, a = b*c).
Proof.
split; intros.
exists (a/b).
pattern a at 1; rewrite (Z_div_mod_eq_full a b); auto with zarith.
destruct H0 as [c Hc].
symmetry.
apply Zmod_unique_full with c; auto with zarith.
red; omega with *.
Qed.
(** * Compatibility *)
(** Weaker results kept only for compatibility *)
Lemma Z_mod_same : forall a, a > 0 -> a mod a = 0.
Proof.
intros; apply Z_mod_same_full.
Qed.
Lemma Z_div_same : forall a, a > 0 -> a/a = 1.
Proof.
intros; apply Z_div_same_full; auto with zarith.
Qed.
Lemma Z_div_plus : forall a b c:Z, c > 0 -> (a + b * c) / c = a / c + b.
Proof.
intros; apply Z_div_plus_full; auto with zarith.
Qed.
Lemma Z_div_mult : forall a b:Z, b > 0 -> (a*b)/b = a.
Proof.
intros; apply Z_div_mult_full; auto with zarith.
Qed.
Lemma Z_mod_plus : forall a b c:Z, c > 0 -> (a + b * c) mod c = a mod c.
Proof.
intros; apply Z_mod_plus_full; auto with zarith.
Qed.
Lemma Z_div_exact_1 : forall a b:Z, b > 0 -> a = b*(a/b) -> a mod b = 0.
Proof.
intros; apply Z_div_exact_full_1; auto with zarith.
Qed.
Lemma Z_div_exact_2 : forall a b:Z, b > 0 -> a mod b = 0 -> a = b*(a/b).
Proof.
intros; apply Z_div_exact_full_2; auto with zarith.
Qed.
Lemma Z_mod_zero_opp : forall a b:Z, b > 0 -> a mod b = 0 -> (-a) mod b = 0.
Proof.
intros; apply Z_mod_zero_opp_full; auto with zarith.
Qed.
(** * A direct way to compute Zmod *)
Fixpoint Zmod_POS (a : positive) (b : Z) : Z :=
match a with
| xI a' =>
let r := Zmod_POS a' b in
let r' := (2 * r + 1) in
if Zgt_bool b r' then r' else (r' - b)
| xO a' =>
let r := Zmod_POS a' b in
let r' := (2 * r) in
if Zgt_bool b r' then r' else (r' - b)
| xH => if Zge_bool b 2 then 1 else 0
end.
Definition Zmod' a b :=
match a with
| Z0 => 0
| Zpos a' =>
match b with
| Z0 => 0
| Zpos _ => Zmod_POS a' b
| Zneg b' =>
let r := Zmod_POS a' (Zpos b') in
match r with Z0 => 0 | _ => b + r end
end
| Zneg a' =>
match b with
| Z0 => 0
| Zpos _ =>
let r := Zmod_POS a' b in
match r with Z0 => 0 | _ => b - r end
| Zneg b' => - (Zmod_POS a' (Zpos b'))
end
end.
Theorem Zmod_POS_correct: forall a b, Zmod_POS a b = (snd (Zdiv_eucl_POS a b)).
Proof.
intros a b; elim a; simpl; auto.
intros p Rec; rewrite Rec.
case (Zdiv_eucl_POS p b); intros z1 z2; simpl; auto.
match goal with |- context [Zgt_bool _ ?X] => case (Zgt_bool b X) end; auto.
intros p Rec; rewrite Rec.
case (Zdiv_eucl_POS p b); intros z1 z2; simpl; auto.
match goal with |- context [Zgt_bool _ ?X] => case (Zgt_bool b X) end; auto.
case (Zge_bool b 2); auto.
Qed.
Theorem Zmod'_correct: forall a b, Zmod' a b = Zmod a b.
Proof.
intros a b; unfold Zmod; case a; simpl; auto.
intros p; case b; simpl; auto.
intros p1; refine (Zmod_POS_correct _ _); auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Zdiv_eucl_POS p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p; case b; simpl; auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Zdiv_eucl_POS p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p1; rewrite Zmod_POS_correct; simpl; auto.
case (Zdiv_eucl_POS p (Zpos p1)); auto.
Qed.
(** Another convention is possible for division by negative numbers:
* quotient is always the biggest integer smaller than or equal to a/b
* remainder is hence always positive or null. *)
Theorem Zdiv_eucl_extended :
forall b:Z,
b <> 0 ->
forall a:Z,
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < Zabs b}.
Proof.
intros b Hb a.
elim (Z_le_gt_dec 0 b); intro Hb'.
cut (b > 0); [ intro Hb'' | omega ].
rewrite Zabs_eq; [ apply Zdiv_eucl_exist; assumption | assumption ].
cut (- b > 0); [ intro Hb'' | omega ].
elim (Zdiv_eucl_exist Hb'' a); intros qr.
elim qr; intros q r Hqr.
exists (- q, r).
elim Hqr; intros.
split.
rewrite <- Zmult_opp_comm; assumption.
rewrite Zabs_non_eq; [ assumption | omega ].
Qed.
Implicit Arguments Zdiv_eucl_extended.
(** A third convention: Ocaml.
See files ZOdiv_def.v and ZOdiv.v.
Ocaml uses Round-Toward-Zero division: (-a)/b = a/(-b) = -(a/b).
Hence (-a) mod b = - (a mod b)
a mod (-b) = a mod b
And: |r| < |b| and sgn(r) = sgn(a) (notice the a here instead of b).
*)
|
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// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____65.000______0.000______50.0______507.692____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "SystemClockUnit,clk_wiz_v3_6,{component_name=SystemClockUnit,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module SystemClockUnit
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (20),
.CLKFX_MULTIPLY (13),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk0));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: nco_d.v
// /___/ /\ Timestamp: Tue Nov 19 22:28:14 2013
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog "C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/tmp/_cg/nco_d.ngc" "C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/tmp/_cg/nco_d.v"
// Device : 6slx16csg324-3
// Input file : C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/tmp/_cg/nco_d.ngc
// Output file : C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/tmp/_cg/nco_d.v
// # of Modules : 1
// Design Name : nco_d
// Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module nco_d (
clk, sine
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [15 : 0] sine;
// synthesis translate_off
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
wire sig00000071;
wire sig00000072;
wire sig00000073;
wire sig00000074;
wire sig00000075;
wire sig00000076;
wire sig00000077;
wire sig00000078;
wire sig00000079;
wire sig0000007a;
wire sig0000007b;
wire sig0000007c;
wire sig0000007d;
wire sig0000007e;
wire sig0000007f;
wire sig00000080;
wire sig00000081;
wire sig00000082;
wire sig00000083;
wire sig00000084;
wire sig00000085;
wire sig00000086;
wire sig00000087;
wire sig00000088;
wire sig00000089;
wire sig0000008a;
wire sig0000008b;
wire sig0000008c;
wire sig0000008d;
wire sig0000008e;
wire sig0000008f;
wire sig00000090;
wire sig00000091;
wire sig00000092;
wire sig00000093;
wire sig00000094;
wire sig00000095;
wire sig00000096;
wire sig00000097;
wire sig00000098;
wire sig00000099;
wire sig0000009a;
wire sig0000009b;
wire sig0000009c;
wire sig0000009d;
wire sig0000009e;
wire sig0000009f;
wire sig000000a0;
wire sig000000a1;
wire sig000000a2;
wire sig000000a3;
wire sig000000a4;
wire sig000000a5;
wire sig000000a6;
wire sig000000a7;
wire sig000000a8;
wire sig000000a9;
wire sig000000aa;
wire sig000000ab;
wire sig000000ac;
wire sig000000ad;
wire sig000000ae;
wire sig000000af;
wire sig000000b0;
wire sig000000b1;
wire sig000000b2;
wire sig000000b3;
wire sig000000b4;
wire sig000000b5;
wire sig000000b6;
wire sig000000b7;
wire sig000000b8;
wire sig000000b9;
wire sig000000ba;
wire sig000000bb;
wire sig000000bc;
wire sig000000bd;
wire sig000000be;
wire sig000000bf;
wire sig000000c0;
wire sig000000c1;
wire sig000000c2;
wire sig000000c3;
wire sig000000c4;
wire sig000000c5;
wire sig000000c6;
wire sig000000c7;
wire sig000000c8;
wire sig000000c9;
wire sig000000ca;
wire sig000000cb;
wire sig000000cc;
wire sig000000cd;
wire sig000000ce;
wire sig000000cf;
wire sig000000d0;
wire sig000000d1;
wire sig000000d2;
wire sig000000d3;
wire sig000000d4;
wire sig000000d5;
wire sig000000d6;
wire sig000000d7;
wire sig000000d8;
wire sig000000d9;
wire sig000000da;
wire sig000000db;
wire sig000000dc;
wire sig000000dd;
wire sig000000de;
wire sig000000df;
wire sig000000e0;
wire sig000000e1;
wire sig000000e2;
wire sig000000e3;
wire sig000000e4;
wire sig000000e5;
wire sig000000e6;
wire sig000000e7;
wire sig000000e8;
wire sig000000e9;
wire sig000000ea;
wire sig000000eb;
wire sig000000ec;
wire sig000000ed;
wire sig000000ee;
wire sig000000ef;
wire sig000000f0;
wire sig000000f1;
wire sig000000f2;
wire sig000000f3;
wire sig000000f4;
wire sig000000f5;
wire sig000000f6;
wire sig000000f7;
wire sig000000f8;
wire sig000000f9;
wire sig000000fa;
wire sig000000fb;
wire sig000000fc;
wire sig000000fd;
wire sig000000fe;
wire sig000000ff;
wire sig00000100;
wire sig00000101;
wire sig00000102;
wire sig00000103;
wire sig00000104;
wire sig00000105;
wire sig00000106;
wire sig00000107;
wire sig00000108;
wire sig00000109;
wire sig0000010a;
wire sig0000010b;
wire sig0000010c;
wire sig0000010d;
wire sig0000010e;
wire sig0000010f;
wire sig00000110;
wire sig00000111;
wire sig00000112;
wire sig00000113;
wire sig00000114;
wire sig00000115;
wire sig00000116;
wire sig00000117;
wire sig00000118;
wire sig00000119;
wire sig0000011a;
wire sig0000011b;
wire sig0000011c;
wire sig0000011d;
wire sig0000011e;
wire sig0000011f;
wire sig00000120;
wire sig00000121;
wire sig00000122;
wire sig00000123;
wire sig00000124;
wire sig00000125;
wire sig00000126;
wire sig00000127;
wire sig00000128;
wire sig00000129;
wire sig0000012a;
wire sig0000012b;
wire sig0000012c;
wire sig0000012d;
wire sig0000012e;
wire sig0000012f;
wire sig00000130;
wire sig00000131;
wire sig00000132;
wire sig00000133;
wire sig00000134;
wire sig00000135;
wire sig00000136;
wire sig00000137;
wire sig00000138;
wire sig00000139;
wire sig0000013a;
wire sig0000013b;
wire sig0000013c;
wire sig0000013d;
wire sig0000013e;
wire sig0000013f;
wire sig00000140;
wire sig00000141;
wire sig00000142;
wire sig00000143;
wire sig00000144;
wire sig00000145;
wire sig00000146;
wire sig00000147;
wire sig00000148;
wire \blk00000025/sig00000198 ;
wire \blk00000025/sig00000197 ;
wire \blk00000025/sig00000196 ;
wire \blk00000025/sig00000195 ;
wire \blk00000025/sig00000194 ;
wire \blk00000025/sig00000193 ;
wire \blk00000025/sig00000192 ;
wire \blk00000025/sig00000191 ;
wire \blk00000025/sig00000190 ;
wire \blk00000025/sig0000018f ;
wire \blk00000025/sig0000018e ;
wire \blk00000025/sig0000018d ;
wire \blk00000025/sig0000018c ;
wire \blk00000025/sig0000018b ;
wire \blk00000025/sig0000018a ;
wire \blk00000025/sig00000189 ;
wire \blk00000025/sig00000188 ;
wire \blk00000025/sig00000187 ;
wire \blk00000025/sig00000186 ;
wire \blk00000025/sig00000185 ;
wire \blk00000025/sig00000184 ;
wire \blk00000025/sig00000183 ;
wire \blk00000025/sig00000182 ;
wire \blk00000025/sig00000181 ;
wire \blk00000025/sig00000180 ;
wire \blk00000025/sig0000017f ;
wire \blk00000025/sig0000017e ;
wire \blk00000025/sig0000017d ;
wire \blk00000025/sig0000017c ;
wire \blk00000025/sig0000017b ;
wire \blk00000025/sig0000017a ;
wire \blk00000056/sig000001e9 ;
wire \blk00000056/sig000001e8 ;
wire \blk00000056/sig000001e7 ;
wire \blk00000056/sig000001e6 ;
wire \blk00000056/sig000001e5 ;
wire \blk00000056/sig000001e4 ;
wire \blk00000056/sig000001e3 ;
wire \blk00000056/sig000001e2 ;
wire \blk00000056/sig000001e1 ;
wire \blk00000056/sig000001e0 ;
wire \blk00000056/sig000001df ;
wire \blk00000056/sig000001de ;
wire \blk00000056/sig000001dd ;
wire \blk00000056/sig000001dc ;
wire \blk00000056/sig000001db ;
wire \blk00000056/sig000001da ;
wire \blk00000056/sig000001d9 ;
wire \blk00000056/sig000001d8 ;
wire \blk00000056/sig000001d7 ;
wire \blk00000056/sig000001d6 ;
wire \blk00000056/sig000001d5 ;
wire \blk00000056/sig000001d4 ;
wire \blk00000056/sig000001d3 ;
wire \blk00000056/sig000001d2 ;
wire \blk00000056/sig000001d1 ;
wire \blk00000056/sig000001d0 ;
wire \blk00000056/sig000001cf ;
wire \blk00000056/sig000001ce ;
wire \blk00000056/sig000001cd ;
wire \blk00000056/sig000001cc ;
wire \blk00000056/sig000001cb ;
wire \blk00000087/sig000001ff ;
wire \blk00000087/sig000001fe ;
wire \blk00000087/sig000001fd ;
wire \blk00000087/sig000001fc ;
wire \blk00000087/sig000001fb ;
wire \blk00000087/sig000001fa ;
wire \blk00000087/sig000001f9 ;
wire \blk00000087/sig000001f8 ;
wire \blk00000087/sig000001f7 ;
wire \blk00000087/sig000001f6 ;
wire \blk00000087/sig000001f2 ;
wire \blk00000087/sig000001f1 ;
wire \blk00000087/sig000001f0 ;
wire \blk00000087/sig000001ef ;
wire \blk00000087/sig000001ee ;
wire \blk00000087/sig000001ed ;
wire \blk00000087/sig000001ec ;
wire \NLW_blk0000014d_DIPA<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPA<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPA<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPA<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<4>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<4>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<4>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<4>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<4>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<4>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<4>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<3>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<4>_UNCONNECTED ;
wire NLW_blk00000151_Q15_UNCONNECTED;
wire NLW_blk00000153_Q15_UNCONNECTED;
wire NLW_blk00000155_Q15_UNCONNECTED;
wire NLW_blk00000157_Q15_UNCONNECTED;
wire NLW_blk00000159_Q15_UNCONNECTED;
wire NLW_blk0000015b_Q15_UNCONNECTED;
wire NLW_blk0000015d_Q15_UNCONNECTED;
wire NLW_blk0000015f_Q15_UNCONNECTED;
wire NLW_blk00000161_Q15_UNCONNECTED;
wire NLW_blk00000163_Q15_UNCONNECTED;
wire NLW_blk00000165_Q15_UNCONNECTED;
wire NLW_blk00000167_Q15_UNCONNECTED;
wire NLW_blk00000169_Q15_UNCONNECTED;
wire NLW_blk0000016b_Q15_UNCONNECTED;
wire NLW_blk0000016d_Q15_UNCONNECTED;
wire NLW_blk0000016f_Q15_UNCONNECTED;
wire NLW_blk00000171_Q15_UNCONNECTED;
wire NLW_blk00000173_Q15_UNCONNECTED;
wire NLW_blk00000175_Q15_UNCONNECTED;
wire NLW_blk00000177_Q15_UNCONNECTED;
wire NLW_blk00000179_Q15_UNCONNECTED;
wire NLW_blk0000017b_Q15_UNCONNECTED;
wire NLW_blk0000017d_Q15_UNCONNECTED;
wire NLW_blk0000017f_Q15_UNCONNECTED;
wire NLW_blk00000181_Q15_UNCONNECTED;
wire NLW_blk00000183_Q15_UNCONNECTED;
wire NLW_blk00000185_Q15_UNCONNECTED;
wire NLW_blk00000187_Q15_UNCONNECTED;
wire NLW_blk00000189_Q15_UNCONNECTED;
wire NLW_blk0000018b_Q15_UNCONNECTED;
wire NLW_blk0000018d_Q15_UNCONNECTED;
wire NLW_blk0000018f_Q15_UNCONNECTED;
wire [7 : 0] \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q ;
wire [7 : 0] \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q ;
assign
sine[15] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [7],
sine[14] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [6],
sine[13] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [5],
sine[12] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [4],
sine[11] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [3],
sine[10] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [2],
sine[9] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [1],
sine[8] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [0],
sine[7] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [7],
sine[6] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [6],
sine[5] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [5],
sine[4] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [4],
sine[3] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [3],
sine[2] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [2],
sine[1] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [1],
sine[0] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [0];
VCC blk00000001 (
.P(sig00000001)
);
GND blk00000002 (
.G(sig00000002)
);
FD #(
.INIT ( 1'b0 ))
blk00000003 (
.C(clk),
.D(sig00000003),
.Q(sig00000046)
);
FD #(
.INIT ( 1'b0 ))
blk00000004 (
.C(clk),
.D(sig00000004),
.Q(sig00000045)
);
FD #(
.INIT ( 1'b0 ))
blk00000005 (
.C(clk),
.D(sig00000005),
.Q(sig00000044)
);
FD #(
.INIT ( 1'b0 ))
blk00000006 (
.C(clk),
.D(sig00000006),
.Q(sig00000043)
);
FD #(
.INIT ( 1'b0 ))
blk00000007 (
.C(clk),
.D(sig00000007),
.Q(sig00000042)
);
FD #(
.INIT ( 1'b0 ))
blk00000008 (
.C(clk),
.D(sig00000008),
.Q(sig00000041)
);
FD #(
.INIT ( 1'b0 ))
blk00000009 (
.C(clk),
.D(sig00000009),
.Q(sig00000040)
);
FD #(
.INIT ( 1'b0 ))
blk0000000a (
.C(clk),
.D(sig0000000a),
.Q(sig0000003f)
);
FD #(
.INIT ( 1'b0 ))
blk0000000b (
.C(clk),
.D(sig0000000b),
.Q(sig0000003e)
);
FD #(
.INIT ( 1'b0 ))
blk0000000c (
.C(clk),
.D(sig0000000c),
.Q(sig0000003d)
);
FD #(
.INIT ( 1'b0 ))
blk0000000d (
.C(clk),
.D(sig0000000d),
.Q(sig0000003c)
);
FD #(
.INIT ( 1'b0 ))
blk0000000e (
.C(clk),
.D(sig0000000e),
.Q(sig0000003b)
);
FD #(
.INIT ( 1'b0 ))
blk0000000f (
.C(clk),
.D(sig0000000f),
.Q(sig0000003a)
);
FD #(
.INIT ( 1'b0 ))
blk00000010 (
.C(clk),
.D(sig00000010),
.Q(sig00000039)
);
FD #(
.INIT ( 1'b0 ))
blk00000011 (
.C(clk),
.D(sig00000011),
.Q(sig00000038)
);
FD #(
.INIT ( 1'b0 ))
blk00000012 (
.C(clk),
.D(sig00000012),
.Q(sig00000037)
);
FD #(
.INIT ( 1'b0 ))
blk00000013 (
.C(clk),
.D(sig00000013),
.Q(sig00000036)
);
FD #(
.INIT ( 1'b0 ))
blk00000014 (
.C(clk),
.D(sig00000024),
.Q(sig00000049)
);
FD #(
.INIT ( 1'b0 ))
blk00000015 (
.C(clk),
.D(sig00000023),
.Q(sig00000032)
);
FD #(
.INIT ( 1'b0 ))
blk00000016 (
.C(clk),
.D(sig00000022),
.Q(sig00000031)
);
FD #(
.INIT ( 1'b0 ))
blk00000017 (
.C(clk),
.D(sig00000021),
.Q(sig00000030)
);
FD #(
.INIT ( 1'b0 ))
blk00000018 (
.C(clk),
.D(sig00000020),
.Q(sig0000002f)
);
FD #(
.INIT ( 1'b0 ))
blk00000019 (
.C(clk),
.D(sig0000001f),
.Q(sig0000002e)
);
FD #(
.INIT ( 1'b0 ))
blk0000001a (
.C(clk),
.D(sig0000001e),
.Q(sig0000002d)
);
FD #(
.INIT ( 1'b0 ))
blk0000001b (
.C(clk),
.D(sig0000001d),
.Q(sig0000002c)
);
FD #(
.INIT ( 1'b0 ))
blk0000001c (
.C(clk),
.D(sig0000001c),
.Q(sig0000002b)
);
FD #(
.INIT ( 1'b0 ))
blk0000001d (
.C(clk),
.D(sig0000001b),
.Q(sig0000002a)
);
FD #(
.INIT ( 1'b0 ))
blk0000001e (
.C(clk),
.D(sig0000001a),
.Q(sig00000029)
);
FD #(
.INIT ( 1'b0 ))
blk0000001f (
.C(clk),
.D(sig00000019),
.Q(sig00000028)
);
FD #(
.INIT ( 1'b0 ))
blk00000020 (
.C(clk),
.D(sig00000018),
.Q(sig00000027)
);
FD #(
.INIT ( 1'b0 ))
blk00000021 (
.C(clk),
.D(sig00000017),
.Q(sig00000026)
);
FD #(
.INIT ( 1'b0 ))
blk00000022 (
.C(clk),
.D(sig00000016),
.Q(sig00000025)
);
FD #(
.INIT ( 1'b0 ))
blk00000023 (
.C(clk),
.D(sig00000015),
.Q(sig00000048)
);
FD #(
.INIT ( 1'b0 ))
blk00000024 (
.C(clk),
.D(sig00000014),
.Q(sig00000047)
);
XORCY blk0000009c (
.CI(sig0000005d),
.LI(sig0000007d),
.O(sig00000075)
);
MUXCY blk0000009d (
.CI(sig0000005d),
.DI(sig00000002),
.S(sig0000007d),
.O(sig0000005c)
);
XORCY blk0000009e (
.CI(sig0000005e),
.LI(sig0000007c),
.O(sig00000074)
);
MUXCY blk0000009f (
.CI(sig0000005e),
.DI(sig00000002),
.S(sig0000007c),
.O(sig0000005d)
);
XORCY blk000000a0 (
.CI(sig0000005f),
.LI(sig0000007b),
.O(sig00000073)
);
MUXCY blk000000a1 (
.CI(sig0000005f),
.DI(sig00000002),
.S(sig0000007b),
.O(sig0000005e)
);
XORCY blk000000a2 (
.CI(sig00000060),
.LI(sig0000007a),
.O(sig00000072)
);
MUXCY blk000000a3 (
.CI(sig00000060),
.DI(sig00000002),
.S(sig0000007a),
.O(sig0000005f)
);
XORCY blk000000a4 (
.CI(sig00000061),
.LI(sig00000079),
.O(sig00000071)
);
MUXCY blk000000a5 (
.CI(sig00000061),
.DI(sig00000002),
.S(sig00000079),
.O(sig00000060)
);
XORCY blk000000a6 (
.CI(sig00000062),
.LI(sig00000078),
.O(sig00000070)
);
MUXCY blk000000a7 (
.CI(sig00000062),
.DI(sig00000002),
.S(sig00000078),
.O(sig00000061)
);
XORCY blk000000a8 (
.CI(sig00000063),
.LI(sig00000077),
.O(sig0000006f)
);
MUXCY blk000000a9 (
.CI(sig00000063),
.DI(sig00000002),
.S(sig00000077),
.O(sig00000062)
);
XORCY blk000000aa (
.CI(sig00000064),
.LI(sig00000076),
.O(sig0000006e)
);
MUXCY blk000000ab (
.CI(sig00000064),
.DI(sig00000002),
.S(sig00000076),
.O(sig00000063)
);
MUXCY blk000000ac (
.CI(sig00000002),
.DI(sig00000001),
.S(sig00000065),
.O(sig00000064)
);
XORCY blk000000ad (
.CI(sig00000067),
.LI(sig00000094),
.O(sig0000008d)
);
MUXCY blk000000ae (
.CI(sig00000067),
.DI(sig00000002),
.S(sig00000094),
.O(sig00000066)
);
XORCY blk000000af (
.CI(sig00000068),
.LI(sig00000093),
.O(sig0000008c)
);
MUXCY blk000000b0 (
.CI(sig00000068),
.DI(sig00000002),
.S(sig00000093),
.O(sig00000067)
);
XORCY blk000000b1 (
.CI(sig00000069),
.LI(sig00000092),
.O(sig0000008b)
);
MUXCY blk000000b2 (
.CI(sig00000069),
.DI(sig00000002),
.S(sig00000092),
.O(sig00000068)
);
XORCY blk000000b3 (
.CI(sig0000006a),
.LI(sig00000091),
.O(sig0000008a)
);
MUXCY blk000000b4 (
.CI(sig0000006a),
.DI(sig00000002),
.S(sig00000091),
.O(sig00000069)
);
XORCY blk000000b5 (
.CI(sig0000006b),
.LI(sig00000090),
.O(sig00000089)
);
MUXCY blk000000b6 (
.CI(sig0000006b),
.DI(sig00000002),
.S(sig00000090),
.O(sig0000006a)
);
XORCY blk000000b7 (
.CI(sig0000006c),
.LI(sig0000008f),
.O(sig00000088)
);
MUXCY blk000000b8 (
.CI(sig0000006c),
.DI(sig00000002),
.S(sig0000008f),
.O(sig0000006b)
);
XORCY blk000000b9 (
.CI(sig0000006d),
.LI(sig0000008e),
.O(sig00000087)
);
MUXCY blk000000ba (
.CI(sig0000006d),
.DI(sig00000002),
.S(sig0000008e),
.O(sig0000006c)
);
XORCY blk000000bb (
.CI(sig00000002),
.LI(sig00000127),
.O(sig00000086)
);
MUXCY blk000000bc (
.CI(sig00000002),
.DI(sig0000009c),
.S(sig00000127),
.O(sig0000006d)
);
FD #(
.INIT ( 1'b0 ))
blk000000bd (
.C(clk),
.D(sig000000b6),
.Q(sig000000c2)
);
FD #(
.INIT ( 1'b0 ))
blk000000be (
.C(clk),
.D(sig000000b5),
.Q(sig000000c1)
);
FD #(
.INIT ( 1'b0 ))
blk000000bf (
.C(clk),
.D(sig000000b4),
.Q(sig000000c0)
);
FD #(
.INIT ( 1'b0 ))
blk000000c0 (
.C(clk),
.D(sig000000b3),
.Q(sig000000bf)
);
FD #(
.INIT ( 1'b0 ))
blk000000c1 (
.C(clk),
.D(sig000000b2),
.Q(sig000000be)
);
FD #(
.INIT ( 1'b0 ))
blk000000c2 (
.C(clk),
.D(sig000000b1),
.Q(sig000000bd)
);
FD #(
.INIT ( 1'b0 ))
blk000000c3 (
.C(clk),
.D(sig000000b0),
.Q(sig000000bc)
);
FD #(
.INIT ( 1'b0 ))
blk000000c4 (
.C(clk),
.D(sig000000af),
.Q(sig000000bb)
);
FD #(
.INIT ( 1'b0 ))
blk000000c5 (
.C(clk),
.D(sig000000ae),
.Q(sig000000ba)
);
FD #(
.INIT ( 1'b0 ))
blk000000c6 (
.C(clk),
.D(sig000000ad),
.Q(sig000000b9)
);
FD #(
.INIT ( 1'b0 ))
blk000000c7 (
.C(clk),
.D(sig000000ac),
.Q(sig000000b8)
);
FD #(
.INIT ( 1'b0 ))
blk000000c8 (
.C(clk),
.D(sig000000ab),
.Q(sig000000b7)
);
FD #(
.INIT ( 1'b0 ))
blk000000c9 (
.C(clk),
.D(sig00000124),
.Q(sig0000009c)
);
FD #(
.INIT ( 1'b0 ))
blk000000ca (
.C(clk),
.D(sig00000032),
.Q(sig00000126)
);
FD #(
.INIT ( 1'b0 ))
blk000000cb (
.C(clk),
.D(sig00000031),
.Q(sig00000125)
);
FD #(
.INIT ( 1'b0 ))
blk000000cc (
.C(clk),
.D(sig000000f8),
.Q(sig000000e8)
);
FD #(
.INIT ( 1'b0 ))
blk000000cd (
.C(clk),
.D(sig000000f7),
.Q(sig000000e7)
);
FD #(
.INIT ( 1'b0 ))
blk000000ce (
.C(clk),
.D(sig000000f6),
.Q(sig000000e6)
);
FD #(
.INIT ( 1'b0 ))
blk000000cf (
.C(clk),
.D(sig000000f5),
.Q(sig000000e5)
);
FD #(
.INIT ( 1'b0 ))
blk000000d0 (
.C(clk),
.D(sig000000f4),
.Q(sig000000e4)
);
FD #(
.INIT ( 1'b0 ))
blk000000d1 (
.C(clk),
.D(sig000000f3),
.Q(sig000000e3)
);
FD #(
.INIT ( 1'b0 ))
blk000000d2 (
.C(clk),
.D(sig000000f2),
.Q(sig000000e2)
);
FD #(
.INIT ( 1'b0 ))
blk000000d3 (
.C(clk),
.D(sig000000f1),
.Q(sig000000e1)
);
FD #(
.INIT ( 1'b0 ))
blk000000d4 (
.C(clk),
.D(sig000000a3),
.Q(sig000000f0)
);
FD #(
.INIT ( 1'b0 ))
blk000000d5 (
.C(clk),
.D(sig000000a2),
.Q(sig000000ef)
);
FD #(
.INIT ( 1'b0 ))
blk000000d6 (
.C(clk),
.D(sig000000a1),
.Q(sig000000ee)
);
FD #(
.INIT ( 1'b0 ))
blk000000d7 (
.C(clk),
.D(sig000000a0),
.Q(sig000000ed)
);
FD #(
.INIT ( 1'b0 ))
blk000000d8 (
.C(clk),
.D(sig0000009f),
.Q(sig000000ec)
);
FD #(
.INIT ( 1'b0 ))
blk000000d9 (
.C(clk),
.D(sig0000009e),
.Q(sig000000eb)
);
FD #(
.INIT ( 1'b0 ))
blk000000da (
.C(clk),
.D(sig0000009d),
.Q(sig000000ea)
);
FD #(
.INIT ( 1'b0 ))
blk000000db (
.C(clk),
.D(sig00000053),
.Q(sig000000e9)
);
FD #(
.INIT ( 1'b0 ))
blk000000dc (
.C(clk),
.D(sig00000102),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [7])
);
FD #(
.INIT ( 1'b0 ))
blk000000dd (
.C(clk),
.D(sig00000101),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [6])
);
FD #(
.INIT ( 1'b0 ))
blk000000de (
.C(clk),
.D(sig00000100),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [5])
);
FD #(
.INIT ( 1'b0 ))
blk000000df (
.C(clk),
.D(sig000000ff),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [4])
);
FD #(
.INIT ( 1'b0 ))
blk000000e0 (
.C(clk),
.D(sig000000fe),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [3])
);
FD #(
.INIT ( 1'b0 ))
blk000000e1 (
.C(clk),
.D(sig000000fd),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [2])
);
FD #(
.INIT ( 1'b0 ))
blk000000e2 (
.C(clk),
.D(sig000000fc),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [1])
);
FD #(
.INIT ( 1'b0 ))
blk000000e3 (
.C(clk),
.D(sig000000fb),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [0])
);
FD #(
.INIT ( 1'b0 ))
blk000000e4 (
.C(clk),
.D(sig000000aa),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [7])
);
FD #(
.INIT ( 1'b0 ))
blk000000e5 (
.C(clk),
.D(sig000000a9),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [6])
);
FD #(
.INIT ( 1'b0 ))
blk000000e6 (
.C(clk),
.D(sig000000a8),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [5])
);
FD #(
.INIT ( 1'b0 ))
blk000000e7 (
.C(clk),
.D(sig000000a7),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [4])
);
FD #(
.INIT ( 1'b0 ))
blk000000e8 (
.C(clk),
.D(sig000000a6),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [3])
);
FD #(
.INIT ( 1'b0 ))
blk000000e9 (
.C(clk),
.D(sig000000a5),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [2])
);
FD #(
.INIT ( 1'b0 ))
blk000000ea (
.C(clk),
.D(sig000000a4),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [1])
);
FD #(
.INIT ( 1'b0 ))
blk000000eb (
.C(clk),
.D(sig0000005b),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [0])
);
FD #(
.INIT ( 1'b0 ))
blk000000ec (
.C(clk),
.D(sig00000085),
.Q(sig0000004c)
);
FD #(
.INIT ( 1'b0 ))
blk000000ed (
.C(clk),
.D(sig00000084),
.Q(sig0000004d)
);
FD #(
.INIT ( 1'b0 ))
blk000000ee (
.C(clk),
.D(sig00000083),
.Q(sig0000004e)
);
FD #(
.INIT ( 1'b0 ))
blk000000ef (
.C(clk),
.D(sig00000082),
.Q(sig0000004f)
);
FD #(
.INIT ( 1'b0 ))
blk000000f0 (
.C(clk),
.D(sig00000081),
.Q(sig00000050)
);
FD #(
.INIT ( 1'b0 ))
blk000000f1 (
.C(clk),
.D(sig00000080),
.Q(sig00000051)
);
FD #(
.INIT ( 1'b0 ))
blk000000f2 (
.C(clk),
.D(sig0000007f),
.Q(sig00000052)
);
FD #(
.INIT ( 1'b0 ))
blk000000f3 (
.C(clk),
.D(sig0000007e),
.Q(sig000000fa)
);
FD #(
.INIT ( 1'b0 ))
blk000000f4 (
.C(clk),
.D(sig0000009c),
.Q(sig00000054)
);
FD #(
.INIT ( 1'b0 ))
blk000000f5 (
.C(clk),
.D(sig0000009b),
.Q(sig00000055)
);
FD #(
.INIT ( 1'b0 ))
blk000000f6 (
.C(clk),
.D(sig0000009a),
.Q(sig00000056)
);
FD #(
.INIT ( 1'b0 ))
blk000000f7 (
.C(clk),
.D(sig00000099),
.Q(sig00000057)
);
FD #(
.INIT ( 1'b0 ))
blk000000f8 (
.C(clk),
.D(sig00000098),
.Q(sig00000058)
);
FD #(
.INIT ( 1'b0 ))
blk000000f9 (
.C(clk),
.D(sig00000097),
.Q(sig00000059)
);
FD #(
.INIT ( 1'b0 ))
blk000000fa (
.C(clk),
.D(sig00000096),
.Q(sig0000005a)
);
FD #(
.INIT ( 1'b0 ))
blk000000fb (
.C(clk),
.D(sig00000095),
.Q(sig00000104)
);
FD #(
.INIT ( 1'b0 ))
blk000000fc (
.C(clk),
.D(sig0000005c),
.Q(sig000000f9)
);
FD #(
.INIT ( 1'b0 ))
blk000000fd (
.C(clk),
.D(sig00000075),
.Q(sig000000f8)
);
FD #(
.INIT ( 1'b0 ))
blk000000fe (
.C(clk),
.D(sig00000074),
.Q(sig000000f7)
);
FD #(
.INIT ( 1'b0 ))
blk000000ff (
.C(clk),
.D(sig00000073),
.Q(sig000000f6)
);
FD #(
.INIT ( 1'b0 ))
blk00000100 (
.C(clk),
.D(sig00000072),
.Q(sig000000f5)
);
FD #(
.INIT ( 1'b0 ))
blk00000101 (
.C(clk),
.D(sig00000071),
.Q(sig000000f4)
);
FD #(
.INIT ( 1'b0 ))
blk00000102 (
.C(clk),
.D(sig00000070),
.Q(sig000000f3)
);
FD #(
.INIT ( 1'b0 ))
blk00000103 (
.C(clk),
.D(sig0000006f),
.Q(sig000000f2)
);
FD #(
.INIT ( 1'b0 ))
blk00000104 (
.C(clk),
.D(sig0000006e),
.Q(sig000000f1)
);
FD #(
.INIT ( 1'b0 ))
blk00000105 (
.C(clk),
.D(sig00000066),
.Q(sig00000103)
);
FD #(
.INIT ( 1'b0 ))
blk00000106 (
.C(clk),
.D(sig0000008d),
.Q(sig00000102)
);
FD #(
.INIT ( 1'b0 ))
blk00000107 (
.C(clk),
.D(sig0000008c),
.Q(sig00000101)
);
FD #(
.INIT ( 1'b0 ))
blk00000108 (
.C(clk),
.D(sig0000008b),
.Q(sig00000100)
);
FD #(
.INIT ( 1'b0 ))
blk00000109 (
.C(clk),
.D(sig0000008a),
.Q(sig000000ff)
);
FD #(
.INIT ( 1'b0 ))
blk0000010a (
.C(clk),
.D(sig00000089),
.Q(sig000000fe)
);
FD #(
.INIT ( 1'b0 ))
blk0000010b (
.C(clk),
.D(sig00000088),
.Q(sig000000fd)
);
FD #(
.INIT ( 1'b0 ))
blk0000010c (
.C(clk),
.D(sig00000087),
.Q(sig000000fc)
);
FD #(
.INIT ( 1'b0 ))
blk0000010d (
.C(clk),
.D(sig00000086),
.Q(sig000000fb)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000010e (
.I0(sig00000056),
.I1(sig0000004a),
.O(sig000000a8)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000010f (
.I0(sig0000004e),
.I1(sig0000004b),
.O(sig000000a1)
);
LUT3 #(
.INIT ( 8'hA6 ))
blk00000110 (
.I0(sig00000055),
.I1(sig00000056),
.I2(sig0000004a),
.O(sig000000a9)
);
LUT3 #(
.INIT ( 8'hA6 ))
blk00000111 (
.I0(sig0000004d),
.I1(sig0000004e),
.I2(sig0000004b),
.O(sig000000a2)
);
LUT4 #(
.INIT ( 16'hAA6A ))
blk00000112 (
.I0(sig00000054),
.I1(sig00000055),
.I2(sig00000056),
.I3(sig0000004a),
.O(sig000000aa)
);
LUT4 #(
.INIT ( 16'hAA6A ))
blk00000113 (
.I0(sig0000004c),
.I1(sig0000004d),
.I2(sig0000004e),
.I3(sig0000004b),
.O(sig000000a3)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000114 (
.I0(sig00000115),
.I1(sig00000128),
.O(sig0000008e)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000115 (
.I0(sig00000116),
.I1(sig00000128),
.O(sig0000008f)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000116 (
.I0(sig00000117),
.I1(sig00000128),
.O(sig00000090)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000117 (
.I0(sig00000118),
.I1(sig00000128),
.O(sig00000091)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000118 (
.I0(sig00000119),
.I1(sig00000128),
.O(sig00000092)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000119 (
.I0(sig0000011a),
.I1(sig0000009c),
.O(sig00000093)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011a (
.I0(sig0000011b),
.I1(sig0000009c),
.O(sig00000094)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011b (
.I0(sig0000011c),
.I1(sig0000009c),
.O(sig00000095)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011c (
.I0(sig0000011d),
.I1(sig0000009c),
.O(sig00000096)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011d (
.I0(sig0000011e),
.I1(sig0000009c),
.O(sig00000097)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011e (
.I0(sig0000011f),
.I1(sig0000009c),
.O(sig00000098)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011f (
.I0(sig00000120),
.I1(sig0000009c),
.O(sig00000099)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000120 (
.I0(sig00000121),
.I1(sig0000009c),
.O(sig0000009a)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000121 (
.I0(sig00000122),
.I1(sig0000009c),
.O(sig0000009b)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000122 (
.I0(sig00000025),
.I1(sig00000031),
.O(sig000000ab)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000123 (
.I0(sig0000002f),
.I1(sig00000031),
.O(sig000000b5)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000124 (
.I0(sig00000030),
.I1(sig00000031),
.O(sig000000b6)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000125 (
.I0(sig00000026),
.I1(sig00000031),
.O(sig000000ac)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000126 (
.I0(sig00000027),
.I1(sig00000031),
.O(sig000000ad)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000127 (
.I0(sig00000028),
.I1(sig00000031),
.O(sig000000ae)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000128 (
.I0(sig00000029),
.I1(sig00000031),
.O(sig000000af)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000129 (
.I0(sig0000002a),
.I1(sig00000031),
.O(sig000000b0)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012a (
.I0(sig0000002b),
.I1(sig00000031),
.O(sig000000b1)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012b (
.I0(sig0000002c),
.I1(sig00000031),
.O(sig000000b2)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012c (
.I0(sig0000002d),
.I1(sig00000031),
.O(sig000000b3)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012d (
.I0(sig0000002e),
.I1(sig00000031),
.O(sig000000b4)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012e (
.I0(sig00000123),
.I1(sig0000009c),
.O(sig00000085)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012f (
.I0(sig000000fa),
.I1(sig000000f9),
.O(sig00000053)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000130 (
.I0(sig00000104),
.I1(sig00000103),
.O(sig0000005b)
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
blk00000131 (
.I0(sig00000057),
.I1(sig00000058),
.I2(sig00000059),
.I3(sig0000005a),
.I4(sig00000103),
.I5(sig00000104),
.O(sig0000004a)
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
blk00000132 (
.I0(sig0000004f),
.I1(sig00000050),
.I2(sig00000051),
.I3(sig00000052),
.I4(sig000000f9),
.I5(sig000000fa),
.O(sig0000004b)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000133 (
.I0(sig00000128),
.I1(sig00000123),
.O(sig00000065)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000134 (
.I0(sig00000105),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000076)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000135 (
.I0(sig00000106),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000077)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000136 (
.I0(sig00000107),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000078)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000137 (
.I0(sig00000108),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000079)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000138 (
.I0(sig00000109),
.I1(sig00000128),
.I2(sig00000123),
.O(sig0000007a)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000139 (
.I0(sig0000010a),
.I1(sig00000128),
.I2(sig00000123),
.O(sig0000007b)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000013a (
.I0(sig0000010b),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007c)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000013b (
.I0(sig0000010c),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007d)
);
LUT5 #(
.INIT ( 32'h6AAAAAAA ))
blk0000013c (
.I0(sig00000058),
.I1(sig00000104),
.I2(sig00000103),
.I3(sig0000005a),
.I4(sig00000059),
.O(sig000000a6)
);
LUT6 #(
.INIT ( 64'h6AAAAAAAAAAAAAAA ))
blk0000013d (
.I0(sig00000057),
.I1(sig00000104),
.I2(sig00000103),
.I3(sig0000005a),
.I4(sig00000059),
.I5(sig00000058),
.O(sig000000a7)
);
LUT4 #(
.INIT ( 16'h6AAA ))
blk0000013e (
.I0(sig00000059),
.I1(sig00000104),
.I2(sig00000103),
.I3(sig0000005a),
.O(sig000000a5)
);
LUT5 #(
.INIT ( 32'h6AAAAAAA ))
blk0000013f (
.I0(sig00000050),
.I1(sig000000fa),
.I2(sig000000f9),
.I3(sig00000052),
.I4(sig00000051),
.O(sig0000009f)
);
LUT6 #(
.INIT ( 64'h6AAAAAAAAAAAAAAA ))
blk00000140 (
.I0(sig0000004f),
.I1(sig000000fa),
.I2(sig000000f9),
.I3(sig00000052),
.I4(sig00000051),
.I5(sig00000050),
.O(sig000000a0)
);
LUT4 #(
.INIT ( 16'h6AAA ))
blk00000141 (
.I0(sig00000051),
.I1(sig000000fa),
.I2(sig000000f9),
.I3(sig00000052),
.O(sig0000009e)
);
LUT3 #(
.INIT ( 8'h6A ))
blk00000142 (
.I0(sig00000052),
.I1(sig000000fa),
.I2(sig000000f9),
.O(sig0000009d)
);
LUT3 #(
.INIT ( 8'h6A ))
blk00000143 (
.I0(sig0000005a),
.I1(sig00000104),
.I2(sig00000103),
.O(sig000000a4)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000144 (
.I0(sig0000010d),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007e)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000145 (
.I0(sig0000010e),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007f)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000146 (
.I0(sig0000010f),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000080)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000147 (
.I0(sig00000110),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000081)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000148 (
.I0(sig00000111),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000082)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000149 (
.I0(sig00000112),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000083)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000014a (
.I0(sig00000113),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000084)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000014b (
.I0(sig00000114),
.O(sig00000127)
);
FD #(
.INIT ( 1'b0 ))
blk0000014c (
.C(clk),
.D(sig00000124),
.Q(sig00000128)
);
RAMB16BWER #(
.INIT_00 ( 256'h3332222222222222222222211111111111111111111100000000000000000000 ),
.INIT_01 ( 256'h6666665555555555555555555544444444444444444444433333333333333333 ),
.INIT_02 ( 256'h9999999998888888888888888888877777777777777777777666666666666666 ),
.INIT_03 ( 256'hCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAA999999999999 ),
.INIT_04 ( 256'hFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDCCCCCCCCC ),
.INIT_05 ( 256'h222222222222222211111111111111111111100000000000000000000FFFFFFF ),
.INIT_06 ( 256'h5555555555555555554444444444444444444443333333333333333333332222 ),
.INIT_07 ( 256'h8888888888888888888877777777777777777777766666666666666666666655 ),
.INIT_08 ( 256'hCBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAA999999999999999999998 ),
.INIT_09 ( 256'hFFEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCC ),
.INIT_0A ( 256'h222111111111111111111111000000000000000000000FFFFFFFFFFFFFFFFFFF ),
.INIT_0B ( 256'h5554444444444444444444444333333333333333333333222222222222222222 ),
.INIT_0C ( 256'h8887777777777777777777777666666666666666666666555555555555555555 ),
.INIT_0D ( 256'hBBBAAAAAAAAAAAAAAAAAAAAA9999999999999999999999888888888888888888 ),
.INIT_0E ( 256'hEDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBB ),
.INIT_0F ( 256'h0000000000000000000000FFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEE ),
.INIT_10 ( 256'h3333333333333333333222222222222222222222221111111111111111111111 ),
.INIT_11 ( 256'h6666666666666666555555555555555555555554444444444444444444444333 ),
.INIT_12 ( 256'h9999999999998888888888888888888888877777777777777777777777666666 ),
.INIT_13 ( 256'hCCCCCCCCBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAAAA9999999999 ),
.INIT_14 ( 256'hFFEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCC ),
.INIT_15 ( 256'h1111111111111111111000000000000000000000000FFFFFFFFFFFFFFFFFFFFF ),
.INIT_16 ( 256'h4444444444433333333333333333333333322222222222222222222222211111 ),
.INIT_17 ( 256'h7776666666666666666666666665555555555555555555555554444444444444 ),
.INIT_18 ( 256'h9999999999999999988888888888888888888888887777777777777777777777 ),
.INIT_19 ( 256'hCCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAAAAAAA9999999 ),
.INIT_1A ( 256'hEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCC ),
.INIT_1B ( 256'h1111100000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEE ),
.INIT_1C ( 256'h3333333333333333222222222222222222222222222111111111111111111111 ),
.INIT_1D ( 256'h5555555555555555555555555544444444444444444444444444433333333333 ),
.INIT_1E ( 256'h8888888777777777777777777777777777766666666666666666666666666665 ),
.INIT_1F ( 256'hAAAAAAAAAAAAAAA9999999999999999999999999999888888888888888888888 ),
.INIT_20 ( 256'hCCCCCCCCCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAA ),
.INIT_21 ( 256'hEEEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCC ),
.INIT_22 ( 256'h0000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEEEEE ),
.INIT_23 ( 256'h2222222222222222222222222222221111111111111111111111111111111000 ),
.INIT_24 ( 256'h4444444444444444444444444444443333333333333333333333333333333322 ),
.INIT_25 ( 256'h6666666666666666666666666665555555555555555555555555555555555444 ),
.INIT_26 ( 256'h8888888888888888888888877777777777777777777777777777777776666666 ),
.INIT_27 ( 256'hAAAAAAAAAAAAAAA9999999999999999999999999999999999998888888888888 ),
.INIT_28 ( 256'hCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAA ),
.INIT_29 ( 256'hDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC ),
.INIT_2A ( 256'hFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDD ),
.INIT_2B ( 256'h00000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2C ( 256'h2222222222222221111111111111111111111111111111111111111111100000 ),
.INIT_2D ( 256'h3333333333333333333333333333333332222222222222222222222222222222 ),
.INIT_2E ( 256'h5444444444444444444444444444444444444444444444444433333333333333 ),
.INIT_2F ( 256'h6666666666666555555555555555555555555555555555555555555555555555 ),
.INIT_30 ( 256'h7777777777777777777777766666666666666666666666666666666666666666 ),
.INIT_31 ( 256'h8888888888888888888888888888887777777777777777777777777777777777 ),
.INIT_32 ( 256'h9999999999999999999999999999999999888888888888888888888888888888 ),
.INIT_33 ( 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9999999999999999999999999999999 ),
.INIT_34 ( 256'hBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ),
.INIT_35 ( 256'hCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB ),
.INIT_36 ( 256'hCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC ),
.INIT_37 ( 256'hDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCC ),
.INIT_38 ( 256'hEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD ),
.INIT_39 ( 256'hEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE ),
.INIT_3A ( 256'hFFFFFEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE ),
.INIT_3B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk0000014d (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk0000014d_DIPA<3>_UNCONNECTED , \NLW_blk0000014d_DIPA<2>_UNCONNECTED , \NLW_blk0000014d_DIPA<1>_UNCONNECTED ,
\NLW_blk0000014d_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk0000014d_DOA<31>_UNCONNECTED , \NLW_blk0000014d_DOA<30>_UNCONNECTED , \NLW_blk0000014d_DOA<29>_UNCONNECTED ,
\NLW_blk0000014d_DOA<28>_UNCONNECTED , \NLW_blk0000014d_DOA<27>_UNCONNECTED , \NLW_blk0000014d_DOA<26>_UNCONNECTED ,
\NLW_blk0000014d_DOA<25>_UNCONNECTED , \NLW_blk0000014d_DOA<24>_UNCONNECTED , \NLW_blk0000014d_DOA<23>_UNCONNECTED ,
\NLW_blk0000014d_DOA<22>_UNCONNECTED , \NLW_blk0000014d_DOA<21>_UNCONNECTED , \NLW_blk0000014d_DOA<20>_UNCONNECTED ,
\NLW_blk0000014d_DOA<19>_UNCONNECTED , \NLW_blk0000014d_DOA<18>_UNCONNECTED , \NLW_blk0000014d_DOA<17>_UNCONNECTED ,
\NLW_blk0000014d_DOA<16>_UNCONNECTED , \NLW_blk0000014d_DOA<15>_UNCONNECTED , \NLW_blk0000014d_DOA<14>_UNCONNECTED ,
\NLW_blk0000014d_DOA<13>_UNCONNECTED , \NLW_blk0000014d_DOA<12>_UNCONNECTED , \NLW_blk0000014d_DOA<11>_UNCONNECTED ,
\NLW_blk0000014d_DOA<10>_UNCONNECTED , \NLW_blk0000014d_DOA<9>_UNCONNECTED , \NLW_blk0000014d_DOA<8>_UNCONNECTED ,
\NLW_blk0000014d_DOA<7>_UNCONNECTED , \NLW_blk0000014d_DOA<6>_UNCONNECTED , \NLW_blk0000014d_DOA<5>_UNCONNECTED , \NLW_blk0000014d_DOA<4>_UNCONNECTED
, sig000000dd, sig000000dc, sig000000db, sig000000da}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk0000014d_ADDRA<1>_UNCONNECTED , \NLW_blk0000014d_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk0000014d_ADDRB<1>_UNCONNECTED , \NLW_blk0000014d_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk0000014d_DIB<31>_UNCONNECTED , \NLW_blk0000014d_DIB<30>_UNCONNECTED , \NLW_blk0000014d_DIB<29>_UNCONNECTED ,
\NLW_blk0000014d_DIB<28>_UNCONNECTED , \NLW_blk0000014d_DIB<27>_UNCONNECTED , \NLW_blk0000014d_DIB<26>_UNCONNECTED ,
\NLW_blk0000014d_DIB<25>_UNCONNECTED , \NLW_blk0000014d_DIB<24>_UNCONNECTED , \NLW_blk0000014d_DIB<23>_UNCONNECTED ,
\NLW_blk0000014d_DIB<22>_UNCONNECTED , \NLW_blk0000014d_DIB<21>_UNCONNECTED , \NLW_blk0000014d_DIB<20>_UNCONNECTED ,
\NLW_blk0000014d_DIB<19>_UNCONNECTED , \NLW_blk0000014d_DIB<18>_UNCONNECTED , \NLW_blk0000014d_DIB<17>_UNCONNECTED ,
\NLW_blk0000014d_DIB<16>_UNCONNECTED , \NLW_blk0000014d_DIB<15>_UNCONNECTED , \NLW_blk0000014d_DIB<14>_UNCONNECTED ,
\NLW_blk0000014d_DIB<13>_UNCONNECTED , \NLW_blk0000014d_DIB<12>_UNCONNECTED , \NLW_blk0000014d_DIB<11>_UNCONNECTED ,
\NLW_blk0000014d_DIB<10>_UNCONNECTED , \NLW_blk0000014d_DIB<9>_UNCONNECTED , \NLW_blk0000014d_DIB<8>_UNCONNECTED ,
\NLW_blk0000014d_DIB<7>_UNCONNECTED , \NLW_blk0000014d_DIB<6>_UNCONNECTED , \NLW_blk0000014d_DIB<5>_UNCONNECTED , \NLW_blk0000014d_DIB<4>_UNCONNECTED
, \NLW_blk0000014d_DIB<3>_UNCONNECTED , \NLW_blk0000014d_DIB<2>_UNCONNECTED , \NLW_blk0000014d_DIB<1>_UNCONNECTED ,
\NLW_blk0000014d_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk0000014d_DOPA<3>_UNCONNECTED , \NLW_blk0000014d_DOPA<2>_UNCONNECTED , \NLW_blk0000014d_DOPA<1>_UNCONNECTED ,
\NLW_blk0000014d_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk0000014d_DIPB<3>_UNCONNECTED , \NLW_blk0000014d_DIPB<2>_UNCONNECTED , \NLW_blk0000014d_DIPB<1>_UNCONNECTED ,
\NLW_blk0000014d_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk0000014d_DOPB<3>_UNCONNECTED , \NLW_blk0000014d_DOPB<2>_UNCONNECTED , \NLW_blk0000014d_DOPB<1>_UNCONNECTED ,
\NLW_blk0000014d_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk0000014d_DOB<31>_UNCONNECTED , \NLW_blk0000014d_DOB<30>_UNCONNECTED , \NLW_blk0000014d_DOB<29>_UNCONNECTED ,
\NLW_blk0000014d_DOB<28>_UNCONNECTED , \NLW_blk0000014d_DOB<27>_UNCONNECTED , \NLW_blk0000014d_DOB<26>_UNCONNECTED ,
\NLW_blk0000014d_DOB<25>_UNCONNECTED , \NLW_blk0000014d_DOB<24>_UNCONNECTED , \NLW_blk0000014d_DOB<23>_UNCONNECTED ,
\NLW_blk0000014d_DOB<22>_UNCONNECTED , \NLW_blk0000014d_DOB<21>_UNCONNECTED , \NLW_blk0000014d_DOB<20>_UNCONNECTED ,
\NLW_blk0000014d_DOB<19>_UNCONNECTED , \NLW_blk0000014d_DOB<18>_UNCONNECTED , \NLW_blk0000014d_DOB<17>_UNCONNECTED ,
\NLW_blk0000014d_DOB<16>_UNCONNECTED , \NLW_blk0000014d_DOB<15>_UNCONNECTED , \NLW_blk0000014d_DOB<14>_UNCONNECTED ,
\NLW_blk0000014d_DOB<13>_UNCONNECTED , \NLW_blk0000014d_DOB<12>_UNCONNECTED , \NLW_blk0000014d_DOB<11>_UNCONNECTED ,
\NLW_blk0000014d_DOB<10>_UNCONNECTED , \NLW_blk0000014d_DOB<9>_UNCONNECTED , \NLW_blk0000014d_DOB<8>_UNCONNECTED ,
\NLW_blk0000014d_DOB<7>_UNCONNECTED , \NLW_blk0000014d_DOB<6>_UNCONNECTED , \NLW_blk0000014d_DOB<5>_UNCONNECTED , \NLW_blk0000014d_DOB<4>_UNCONNECTED
, sig000000ce, sig000000cd, sig000000cc, sig000000cb}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk0000014d_DIA<31>_UNCONNECTED , \NLW_blk0000014d_DIA<30>_UNCONNECTED , \NLW_blk0000014d_DIA<29>_UNCONNECTED ,
\NLW_blk0000014d_DIA<28>_UNCONNECTED , \NLW_blk0000014d_DIA<27>_UNCONNECTED , \NLW_blk0000014d_DIA<26>_UNCONNECTED ,
\NLW_blk0000014d_DIA<25>_UNCONNECTED , \NLW_blk0000014d_DIA<24>_UNCONNECTED , \NLW_blk0000014d_DIA<23>_UNCONNECTED ,
\NLW_blk0000014d_DIA<22>_UNCONNECTED , \NLW_blk0000014d_DIA<21>_UNCONNECTED , \NLW_blk0000014d_DIA<20>_UNCONNECTED ,
\NLW_blk0000014d_DIA<19>_UNCONNECTED , \NLW_blk0000014d_DIA<18>_UNCONNECTED , \NLW_blk0000014d_DIA<17>_UNCONNECTED ,
\NLW_blk0000014d_DIA<16>_UNCONNECTED , \NLW_blk0000014d_DIA<15>_UNCONNECTED , \NLW_blk0000014d_DIA<14>_UNCONNECTED ,
\NLW_blk0000014d_DIA<13>_UNCONNECTED , \NLW_blk0000014d_DIA<12>_UNCONNECTED , \NLW_blk0000014d_DIA<11>_UNCONNECTED ,
\NLW_blk0000014d_DIA<10>_UNCONNECTED , \NLW_blk0000014d_DIA<9>_UNCONNECTED , \NLW_blk0000014d_DIA<8>_UNCONNECTED ,
\NLW_blk0000014d_DIA<7>_UNCONNECTED , \NLW_blk0000014d_DIA<6>_UNCONNECTED , \NLW_blk0000014d_DIA<5>_UNCONNECTED , \NLW_blk0000014d_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
RAMB16BWER #(
.INIT_00 ( 256'h110FEDDCBAA987665432210FFEDCBBA9877654432100FEDCCBA9987655432110 ),
.INIT_01 ( 256'h432100FEDDCBA9987665432210FEEDCBBA9877654332100FEDCCBA9887655432 ),
.INIT_02 ( 256'h654332100FEDCCBA9887655432110FEEDCBAA987665433210FFEDCBBA9887654 ),
.INIT_03 ( 256'h87665432210FEEDCBBA9877654432100FEDCCBA9987655432210FEEDCBAA9877 ),
.INIT_04 ( 256'hA9877654432100FEDDCBA9987665432210FFEDCBBA9877654432100FEDDCBA99 ),
.INIT_05 ( 256'hCBA9987655432210FEEDCBBA9877654432100FEDDCBA9987665432210FEEDCBB ),
.INIT_06 ( 256'hDCCBA9987665432210FFEDCBBA9887654432110FEDDCBAA9877654332100FEDC ),
.INIT_07 ( 256'hFEDCCBA9987655432210FEEDCBBA9887654432110FEDDCBAA9877654332100FE ),
.INIT_08 ( 256'h0FEEDCBAA9877654432110FEDDCBAA9877654332100FEDDCBA9987665433210F ),
.INIT_09 ( 256'h10FEEDCBBA9887655432110FEEDCBBA9887655432110FEEDCBBA987765443211 ),
.INIT_0A ( 256'h110FEEDCBBA9887654432110FEEDCBBA9887655432110FEEDCBBA98876554322 ),
.INIT_0B ( 256'h210FFEDCCBA99876654332100FEDDCBAA9877654332100FEDDCBAA9877654432 ),
.INIT_0C ( 256'h210FFEDCCBA99876654332100FEDDCBAA9877654432110FEEDCBBA9887655432 ),
.INIT_0D ( 256'h100FEDDCBAA9877654432210FFEDCCBA99876654332100FEDDCBAA9887655432 ),
.INIT_0E ( 256'h0FFEDDCBAA9877654432210FFEDCCBA99876654432110FEEDCBBA98876654332 ),
.INIT_0F ( 256'hFEDDCBBA98876554332100FEDDCBAA98876554322100FEDDCBAA988765543221 ),
.INIT_10 ( 256'hDCCBA99877654432210FFEDDCBAA98776554322100FEDDCBAA98876554322100 ),
.INIT_11 ( 256'hBA99876654432210FFEDDCBAA98876554332100FEEDCBBA99876654432110FEE ),
.INIT_12 ( 256'h877654432210FFEDDCBBA98876654432110FFEDCCBAA98876554332100FEEDCB ),
.INIT_13 ( 256'h54322100FEEDCCBA998776554322100FEEDCCBA998776554322100FEEDCBBA99 ),
.INIT_14 ( 256'h10FFEDCCBAA98876654432210FFEDDCBBA998776544322100FEEDCBBA9987765 ),
.INIT_15 ( 256'hCBBA998776554332110FFEDCCBAA988766544322100FEEDCBBA9987765543321 ),
.INIT_16 ( 256'h76554332110FFEEDCCBAA98876654332110FFEDDCBBA998776554332110FFEDD ),
.INIT_17 ( 256'h100FEEDCCBAA988766554332110FFEDDCBBA998776554332110FFEDDCBBA9987 ),
.INIT_18 ( 256'hAA988776554332110FFEEDCCBAA988766544332110FFEDDCBBA9987766544322 ),
.INIT_19 ( 256'h332110FFEDDCCBAA988766554332110FFEEDCCBAA9887765543321100FEEDCCB ),
.INIT_1A ( 256'hBBA9987766544322110FFEDDCCBAA9887765543322100FEEDDCBBA9988766544 ),
.INIT_1B ( 256'h22110FFEEDCCBAA9987766544332110FFEEDCCBBA9987766544332110FFEEDCC ),
.INIT_1C ( 256'h9887665543322110FFEEDCCBBA99887665543322100FEEDDCBBAA98877655443 ),
.INIT_1D ( 256'hFEDDCCBAA99887665543322100FFEEDCCBBA99887665544322110FFEEDCCBBA9 ),
.INIT_1E ( 256'h3322100FFEEDCCBBAA98877665443322100FFEEDCCBBAA98877655443321100F ),
.INIT_1F ( 256'h776655433221100FEEDDCCBAA998877655443321100FFEEDCCBBAA9887766544 ),
.INIT_20 ( 256'hAA9988776654433221100FEEDDCCBBAA988776655433221100FFEDDCCBBAA988 ),
.INIT_21 ( 256'hDCCBBA9988776655443322100FFEEDDCCBBAA988776655443321100FFEEDDCCB ),
.INIT_22 ( 256'hEDDCCBBAA9988776655443322110FFEEDDCCBBAA9988776655433221100FFEED ),
.INIT_23 ( 256'hEEDDCCBBAA99887766554433221100FFEEDDCCBBAA9988776655443322110FFE ),
.INIT_24 ( 256'hEDDCCBBAA998877665544433221100FFEEDDCCBBAA99887766554433221100FF ),
.INIT_25 ( 256'hCCBBAA998877766554433221100FFEEEDDCCBBAA998877665544433221100FFE ),
.INIT_26 ( 256'hA9988776665544332211100FFEEDDCCBBBAA998877665554433221100FFFEEDD ),
.INIT_27 ( 256'h665544333221100FFFEEDDCCCBBAA9988877665544433221100FFFEEDDCCBBBA ),
.INIT_28 ( 256'h11100FFFEEDDCCCBBAA999887766655443332211000FFEEDDDCCBBAAA9988776 ),
.INIT_29 ( 256'hCBBBAA9998877766555443322211000FFEEEDDCCBBBAA9998877766554443322 ),
.INIT_2A ( 256'h554443322211100FFFEEDDDCCBBBAA9998877766555443332211100FFFEEDDDC ),
.INIT_2B ( 256'hDDDCCCBBAAA999887776665544433322111000FFEEEDDCCCBBBAA99988777666 ),
.INIT_2C ( 256'h544433222111000FFFEEDDDCCCBBBAA9998887776655544433322111000FFFEE ),
.INIT_2D ( 256'hBAAA99988877766655544433222111000FFFEEEDDDCCCBBBAA99988877766655 ),
.INIT_2E ( 256'h0FFFEEEDDDCCCBBBAAA9998888777666555444333222111000FFFEEEDDDCCCBB ),
.INIT_2F ( 256'h3332222111000FFFFEEEDDDCCCBBBBAAA9998887776666555444333222111100 ),
.INIT_30 ( 256'h66555544433332221111000FFFFEEEDDDDCCCBBBBAAA99988887776665555444 ),
.INIT_31 ( 256'h877776665555444433322221111000FFFFEEEEDDDCCCCBBBBAAA999988877776 ),
.INIT_32 ( 256'h8877776666555544443333222211110000FFFFEEEEDDDDCCCCBBBAAAA9999888 ),
.INIT_33 ( 256'h777666665555444433332222211110000FFFFEEEEEDDDDCCCCBBBBAAAA999988 ),
.INIT_34 ( 256'h555444443333322222111100000FFFFEEEEEDDDDDCCCCBBBBBAAAA9999888887 ),
.INIT_35 ( 256'h2221111100000FFFFFEEEEEDDDDDCCCCCBBBBBAAAAA999998888877777666665 ),
.INIT_36 ( 256'hEDDDDDDCCCCCBBBBBBAAAAAA9999988888877777666666555554444433333322 ),
.INIT_37 ( 256'h88887777776666665555555444444333333222222111111000000FFFFFFEEEEE ),
.INIT_38 ( 256'h1111110000000FFFFFFFEEEEEEEDDDDDDDCCCCCCCBBBBBBBAAAAAA9999999888 ),
.INIT_39 ( 256'h9999998888888887777777766666666555555554444444433333333222222211 ),
.INIT_3A ( 256'h00000FFFFFFFFFFEEEEEEEEEEDDDDDDDDDDCCCCCCCCCBBBBBBBBBAAAAAAAAA99 ),
.INIT_3B ( 256'h6555555555555444444444444333333333333222222222221111111111100000 ),
.INIT_3C ( 256'hAAAAAA9999999999999999888888888888888777777777777776666666666666 ),
.INIT_3D ( 256'hDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAA ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDD ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk0000014e (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk0000014e_DIPA<3>_UNCONNECTED , \NLW_blk0000014e_DIPA<2>_UNCONNECTED , \NLW_blk0000014e_DIPA<1>_UNCONNECTED ,
\NLW_blk0000014e_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk0000014e_DOA<31>_UNCONNECTED , \NLW_blk0000014e_DOA<30>_UNCONNECTED , \NLW_blk0000014e_DOA<29>_UNCONNECTED ,
\NLW_blk0000014e_DOA<28>_UNCONNECTED , \NLW_blk0000014e_DOA<27>_UNCONNECTED , \NLW_blk0000014e_DOA<26>_UNCONNECTED ,
\NLW_blk0000014e_DOA<25>_UNCONNECTED , \NLW_blk0000014e_DOA<24>_UNCONNECTED , \NLW_blk0000014e_DOA<23>_UNCONNECTED ,
\NLW_blk0000014e_DOA<22>_UNCONNECTED , \NLW_blk0000014e_DOA<21>_UNCONNECTED , \NLW_blk0000014e_DOA<20>_UNCONNECTED ,
\NLW_blk0000014e_DOA<19>_UNCONNECTED , \NLW_blk0000014e_DOA<18>_UNCONNECTED , \NLW_blk0000014e_DOA<17>_UNCONNECTED ,
\NLW_blk0000014e_DOA<16>_UNCONNECTED , \NLW_blk0000014e_DOA<15>_UNCONNECTED , \NLW_blk0000014e_DOA<14>_UNCONNECTED ,
\NLW_blk0000014e_DOA<13>_UNCONNECTED , \NLW_blk0000014e_DOA<12>_UNCONNECTED , \NLW_blk0000014e_DOA<11>_UNCONNECTED ,
\NLW_blk0000014e_DOA<10>_UNCONNECTED , \NLW_blk0000014e_DOA<9>_UNCONNECTED , \NLW_blk0000014e_DOA<8>_UNCONNECTED ,
\NLW_blk0000014e_DOA<7>_UNCONNECTED , \NLW_blk0000014e_DOA<6>_UNCONNECTED , \NLW_blk0000014e_DOA<5>_UNCONNECTED , \NLW_blk0000014e_DOA<4>_UNCONNECTED
, sig000000d9, sig000000d8, sig000000d7, sig000000d6}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk0000014e_ADDRA<1>_UNCONNECTED , \NLW_blk0000014e_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk0000014e_ADDRB<1>_UNCONNECTED , \NLW_blk0000014e_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk0000014e_DIB<31>_UNCONNECTED , \NLW_blk0000014e_DIB<30>_UNCONNECTED , \NLW_blk0000014e_DIB<29>_UNCONNECTED ,
\NLW_blk0000014e_DIB<28>_UNCONNECTED , \NLW_blk0000014e_DIB<27>_UNCONNECTED , \NLW_blk0000014e_DIB<26>_UNCONNECTED ,
\NLW_blk0000014e_DIB<25>_UNCONNECTED , \NLW_blk0000014e_DIB<24>_UNCONNECTED , \NLW_blk0000014e_DIB<23>_UNCONNECTED ,
\NLW_blk0000014e_DIB<22>_UNCONNECTED , \NLW_blk0000014e_DIB<21>_UNCONNECTED , \NLW_blk0000014e_DIB<20>_UNCONNECTED ,
\NLW_blk0000014e_DIB<19>_UNCONNECTED , \NLW_blk0000014e_DIB<18>_UNCONNECTED , \NLW_blk0000014e_DIB<17>_UNCONNECTED ,
\NLW_blk0000014e_DIB<16>_UNCONNECTED , \NLW_blk0000014e_DIB<15>_UNCONNECTED , \NLW_blk0000014e_DIB<14>_UNCONNECTED ,
\NLW_blk0000014e_DIB<13>_UNCONNECTED , \NLW_blk0000014e_DIB<12>_UNCONNECTED , \NLW_blk0000014e_DIB<11>_UNCONNECTED ,
\NLW_blk0000014e_DIB<10>_UNCONNECTED , \NLW_blk0000014e_DIB<9>_UNCONNECTED , \NLW_blk0000014e_DIB<8>_UNCONNECTED ,
\NLW_blk0000014e_DIB<7>_UNCONNECTED , \NLW_blk0000014e_DIB<6>_UNCONNECTED , \NLW_blk0000014e_DIB<5>_UNCONNECTED , \NLW_blk0000014e_DIB<4>_UNCONNECTED
, \NLW_blk0000014e_DIB<3>_UNCONNECTED , \NLW_blk0000014e_DIB<2>_UNCONNECTED , \NLW_blk0000014e_DIB<1>_UNCONNECTED ,
\NLW_blk0000014e_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk0000014e_DOPA<3>_UNCONNECTED , \NLW_blk0000014e_DOPA<2>_UNCONNECTED , \NLW_blk0000014e_DOPA<1>_UNCONNECTED ,
\NLW_blk0000014e_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk0000014e_DIPB<3>_UNCONNECTED , \NLW_blk0000014e_DIPB<2>_UNCONNECTED , \NLW_blk0000014e_DIPB<1>_UNCONNECTED ,
\NLW_blk0000014e_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk0000014e_DOPB<3>_UNCONNECTED , \NLW_blk0000014e_DOPB<2>_UNCONNECTED , \NLW_blk0000014e_DOPB<1>_UNCONNECTED ,
\NLW_blk0000014e_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk0000014e_DOB<31>_UNCONNECTED , \NLW_blk0000014e_DOB<30>_UNCONNECTED , \NLW_blk0000014e_DOB<29>_UNCONNECTED ,
\NLW_blk0000014e_DOB<28>_UNCONNECTED , \NLW_blk0000014e_DOB<27>_UNCONNECTED , \NLW_blk0000014e_DOB<26>_UNCONNECTED ,
\NLW_blk0000014e_DOB<25>_UNCONNECTED , \NLW_blk0000014e_DOB<24>_UNCONNECTED , \NLW_blk0000014e_DOB<23>_UNCONNECTED ,
\NLW_blk0000014e_DOB<22>_UNCONNECTED , \NLW_blk0000014e_DOB<21>_UNCONNECTED , \NLW_blk0000014e_DOB<20>_UNCONNECTED ,
\NLW_blk0000014e_DOB<19>_UNCONNECTED , \NLW_blk0000014e_DOB<18>_UNCONNECTED , \NLW_blk0000014e_DOB<17>_UNCONNECTED ,
\NLW_blk0000014e_DOB<16>_UNCONNECTED , \NLW_blk0000014e_DOB<15>_UNCONNECTED , \NLW_blk0000014e_DOB<14>_UNCONNECTED ,
\NLW_blk0000014e_DOB<13>_UNCONNECTED , \NLW_blk0000014e_DOB<12>_UNCONNECTED , \NLW_blk0000014e_DOB<11>_UNCONNECTED ,
\NLW_blk0000014e_DOB<10>_UNCONNECTED , \NLW_blk0000014e_DOB<9>_UNCONNECTED , \NLW_blk0000014e_DOB<8>_UNCONNECTED ,
\NLW_blk0000014e_DOB<7>_UNCONNECTED , \NLW_blk0000014e_DOB<6>_UNCONNECTED , \NLW_blk0000014e_DOB<5>_UNCONNECTED , \NLW_blk0000014e_DOB<4>_UNCONNECTED
, sig000000ca, sig000000c9, sig000000c8, sig000000c7}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk0000014e_DIA<31>_UNCONNECTED , \NLW_blk0000014e_DIA<30>_UNCONNECTED , \NLW_blk0000014e_DIA<29>_UNCONNECTED ,
\NLW_blk0000014e_DIA<28>_UNCONNECTED , \NLW_blk0000014e_DIA<27>_UNCONNECTED , \NLW_blk0000014e_DIA<26>_UNCONNECTED ,
\NLW_blk0000014e_DIA<25>_UNCONNECTED , \NLW_blk0000014e_DIA<24>_UNCONNECTED , \NLW_blk0000014e_DIA<23>_UNCONNECTED ,
\NLW_blk0000014e_DIA<22>_UNCONNECTED , \NLW_blk0000014e_DIA<21>_UNCONNECTED , \NLW_blk0000014e_DIA<20>_UNCONNECTED ,
\NLW_blk0000014e_DIA<19>_UNCONNECTED , \NLW_blk0000014e_DIA<18>_UNCONNECTED , \NLW_blk0000014e_DIA<17>_UNCONNECTED ,
\NLW_blk0000014e_DIA<16>_UNCONNECTED , \NLW_blk0000014e_DIA<15>_UNCONNECTED , \NLW_blk0000014e_DIA<14>_UNCONNECTED ,
\NLW_blk0000014e_DIA<13>_UNCONNECTED , \NLW_blk0000014e_DIA<12>_UNCONNECTED , \NLW_blk0000014e_DIA<11>_UNCONNECTED ,
\NLW_blk0000014e_DIA<10>_UNCONNECTED , \NLW_blk0000014e_DIA<9>_UNCONNECTED , \NLW_blk0000014e_DIA<8>_UNCONNECTED ,
\NLW_blk0000014e_DIA<7>_UNCONNECTED , \NLW_blk0000014e_DIA<6>_UNCONNECTED , \NLW_blk0000014e_DIA<5>_UNCONNECTED , \NLW_blk0000014e_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
RAMB16BWER #(
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h1111111111111111111111111111111111111111111111111111111110000000 ),
.INIT_06 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_07 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_08 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_09 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_0A ( 256'h2222222222222222222222222222222222222222222221111111111111111111 ),
.INIT_0B ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0C ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0D ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0E ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0F ( 256'h3333333333333333333333222222222222222222222222222222222222222222 ),
.INIT_10 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_11 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_12 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_13 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_14 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_15 ( 256'h4444444444444444444444444444444444444444444333333333333333333333 ),
.INIT_16 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_17 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_18 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_19 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_1A ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_1B ( 256'h5555555555555555555555555555555444444444444444444444444444444444 ),
.INIT_1C ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_1D ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_1E ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_1F ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_20 ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_21 ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_22 ( 256'h6666666666666666666666666666555555555555555555555555555555555555 ),
.INIT_23 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_24 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_25 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_26 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_27 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_28 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_29 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_2A ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_2B ( 256'h7777777777777777777777777777777777777766666666666666666666666666 ),
.INIT_2C ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_2D ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_2E ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_2F ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_30 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_31 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_32 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_33 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_34 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_35 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_36 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_37 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_38 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_39 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3A ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3B ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3C ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3D ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3E ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3F ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_A ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_B ( 36'h000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk0000014f (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk0000014f_DIPA<3>_UNCONNECTED , \NLW_blk0000014f_DIPA<2>_UNCONNECTED , \NLW_blk0000014f_DIPA<1>_UNCONNECTED ,
\NLW_blk0000014f_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk0000014f_DOA<31>_UNCONNECTED , \NLW_blk0000014f_DOA<30>_UNCONNECTED , \NLW_blk0000014f_DOA<29>_UNCONNECTED ,
\NLW_blk0000014f_DOA<28>_UNCONNECTED , \NLW_blk0000014f_DOA<27>_UNCONNECTED , \NLW_blk0000014f_DOA<26>_UNCONNECTED ,
\NLW_blk0000014f_DOA<25>_UNCONNECTED , \NLW_blk0000014f_DOA<24>_UNCONNECTED , \NLW_blk0000014f_DOA<23>_UNCONNECTED ,
\NLW_blk0000014f_DOA<22>_UNCONNECTED , \NLW_blk0000014f_DOA<21>_UNCONNECTED , \NLW_blk0000014f_DOA<20>_UNCONNECTED ,
\NLW_blk0000014f_DOA<19>_UNCONNECTED , \NLW_blk0000014f_DOA<18>_UNCONNECTED , \NLW_blk0000014f_DOA<17>_UNCONNECTED ,
\NLW_blk0000014f_DOA<16>_UNCONNECTED , \NLW_blk0000014f_DOA<15>_UNCONNECTED , \NLW_blk0000014f_DOA<14>_UNCONNECTED ,
\NLW_blk0000014f_DOA<13>_UNCONNECTED , \NLW_blk0000014f_DOA<12>_UNCONNECTED , \NLW_blk0000014f_DOA<11>_UNCONNECTED ,
\NLW_blk0000014f_DOA<10>_UNCONNECTED , \NLW_blk0000014f_DOA<9>_UNCONNECTED , \NLW_blk0000014f_DOA<8>_UNCONNECTED ,
\NLW_blk0000014f_DOA<7>_UNCONNECTED , \NLW_blk0000014f_DOA<6>_UNCONNECTED , \NLW_blk0000014f_DOA<5>_UNCONNECTED , \NLW_blk0000014f_DOA<4>_UNCONNECTED
, \NLW_blk0000014f_DOA<3>_UNCONNECTED , sig000000e0, sig000000df, sig000000de}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk0000014f_ADDRA<1>_UNCONNECTED , \NLW_blk0000014f_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk0000014f_ADDRB<1>_UNCONNECTED , \NLW_blk0000014f_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk0000014f_DIB<31>_UNCONNECTED , \NLW_blk0000014f_DIB<30>_UNCONNECTED , \NLW_blk0000014f_DIB<29>_UNCONNECTED ,
\NLW_blk0000014f_DIB<28>_UNCONNECTED , \NLW_blk0000014f_DIB<27>_UNCONNECTED , \NLW_blk0000014f_DIB<26>_UNCONNECTED ,
\NLW_blk0000014f_DIB<25>_UNCONNECTED , \NLW_blk0000014f_DIB<24>_UNCONNECTED , \NLW_blk0000014f_DIB<23>_UNCONNECTED ,
\NLW_blk0000014f_DIB<22>_UNCONNECTED , \NLW_blk0000014f_DIB<21>_UNCONNECTED , \NLW_blk0000014f_DIB<20>_UNCONNECTED ,
\NLW_blk0000014f_DIB<19>_UNCONNECTED , \NLW_blk0000014f_DIB<18>_UNCONNECTED , \NLW_blk0000014f_DIB<17>_UNCONNECTED ,
\NLW_blk0000014f_DIB<16>_UNCONNECTED , \NLW_blk0000014f_DIB<15>_UNCONNECTED , \NLW_blk0000014f_DIB<14>_UNCONNECTED ,
\NLW_blk0000014f_DIB<13>_UNCONNECTED , \NLW_blk0000014f_DIB<12>_UNCONNECTED , \NLW_blk0000014f_DIB<11>_UNCONNECTED ,
\NLW_blk0000014f_DIB<10>_UNCONNECTED , \NLW_blk0000014f_DIB<9>_UNCONNECTED , \NLW_blk0000014f_DIB<8>_UNCONNECTED ,
\NLW_blk0000014f_DIB<7>_UNCONNECTED , \NLW_blk0000014f_DIB<6>_UNCONNECTED , \NLW_blk0000014f_DIB<5>_UNCONNECTED , \NLW_blk0000014f_DIB<4>_UNCONNECTED
, \NLW_blk0000014f_DIB<3>_UNCONNECTED , \NLW_blk0000014f_DIB<2>_UNCONNECTED , \NLW_blk0000014f_DIB<1>_UNCONNECTED ,
\NLW_blk0000014f_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk0000014f_DOPA<3>_UNCONNECTED , \NLW_blk0000014f_DOPA<2>_UNCONNECTED , \NLW_blk0000014f_DOPA<1>_UNCONNECTED ,
\NLW_blk0000014f_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk0000014f_DIPB<3>_UNCONNECTED , \NLW_blk0000014f_DIPB<2>_UNCONNECTED , \NLW_blk0000014f_DIPB<1>_UNCONNECTED ,
\NLW_blk0000014f_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk0000014f_DOPB<3>_UNCONNECTED , \NLW_blk0000014f_DOPB<2>_UNCONNECTED , \NLW_blk0000014f_DOPB<1>_UNCONNECTED ,
\NLW_blk0000014f_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk0000014f_DOB<31>_UNCONNECTED , \NLW_blk0000014f_DOB<30>_UNCONNECTED , \NLW_blk0000014f_DOB<29>_UNCONNECTED ,
\NLW_blk0000014f_DOB<28>_UNCONNECTED , \NLW_blk0000014f_DOB<27>_UNCONNECTED , \NLW_blk0000014f_DOB<26>_UNCONNECTED ,
\NLW_blk0000014f_DOB<25>_UNCONNECTED , \NLW_blk0000014f_DOB<24>_UNCONNECTED , \NLW_blk0000014f_DOB<23>_UNCONNECTED ,
\NLW_blk0000014f_DOB<22>_UNCONNECTED , \NLW_blk0000014f_DOB<21>_UNCONNECTED , \NLW_blk0000014f_DOB<20>_UNCONNECTED ,
\NLW_blk0000014f_DOB<19>_UNCONNECTED , \NLW_blk0000014f_DOB<18>_UNCONNECTED , \NLW_blk0000014f_DOB<17>_UNCONNECTED ,
\NLW_blk0000014f_DOB<16>_UNCONNECTED , \NLW_blk0000014f_DOB<15>_UNCONNECTED , \NLW_blk0000014f_DOB<14>_UNCONNECTED ,
\NLW_blk0000014f_DOB<13>_UNCONNECTED , \NLW_blk0000014f_DOB<12>_UNCONNECTED , \NLW_blk0000014f_DOB<11>_UNCONNECTED ,
\NLW_blk0000014f_DOB<10>_UNCONNECTED , \NLW_blk0000014f_DOB<9>_UNCONNECTED , \NLW_blk0000014f_DOB<8>_UNCONNECTED ,
\NLW_blk0000014f_DOB<7>_UNCONNECTED , \NLW_blk0000014f_DOB<6>_UNCONNECTED , \NLW_blk0000014f_DOB<5>_UNCONNECTED , \NLW_blk0000014f_DOB<4>_UNCONNECTED
, \NLW_blk0000014f_DOB<3>_UNCONNECTED , sig000000d1, sig000000d0, sig000000cf}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk0000014f_DIA<31>_UNCONNECTED , \NLW_blk0000014f_DIA<30>_UNCONNECTED , \NLW_blk0000014f_DIA<29>_UNCONNECTED ,
\NLW_blk0000014f_DIA<28>_UNCONNECTED , \NLW_blk0000014f_DIA<27>_UNCONNECTED , \NLW_blk0000014f_DIA<26>_UNCONNECTED ,
\NLW_blk0000014f_DIA<25>_UNCONNECTED , \NLW_blk0000014f_DIA<24>_UNCONNECTED , \NLW_blk0000014f_DIA<23>_UNCONNECTED ,
\NLW_blk0000014f_DIA<22>_UNCONNECTED , \NLW_blk0000014f_DIA<21>_UNCONNECTED , \NLW_blk0000014f_DIA<20>_UNCONNECTED ,
\NLW_blk0000014f_DIA<19>_UNCONNECTED , \NLW_blk0000014f_DIA<18>_UNCONNECTED , \NLW_blk0000014f_DIA<17>_UNCONNECTED ,
\NLW_blk0000014f_DIA<16>_UNCONNECTED , \NLW_blk0000014f_DIA<15>_UNCONNECTED , \NLW_blk0000014f_DIA<14>_UNCONNECTED ,
\NLW_blk0000014f_DIA<13>_UNCONNECTED , \NLW_blk0000014f_DIA<12>_UNCONNECTED , \NLW_blk0000014f_DIA<11>_UNCONNECTED ,
\NLW_blk0000014f_DIA<10>_UNCONNECTED , \NLW_blk0000014f_DIA<9>_UNCONNECTED , \NLW_blk0000014f_DIA<8>_UNCONNECTED ,
\NLW_blk0000014f_DIA<7>_UNCONNECTED , \NLW_blk0000014f_DIA<6>_UNCONNECTED , \NLW_blk0000014f_DIA<5>_UNCONNECTED , \NLW_blk0000014f_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
RAMB16BWER #(
.INIT_00 ( 256'hE158CF269D047BE158CF369D047BE258CF36AD047BE258CF36AD147BE259CF36 ),
.INIT_01 ( 256'h158CF36AD147BE259C036AD148BF259C037AE148BF269C037AE158BF269D047A ),
.INIT_02 ( 256'h48BF259C037AE158CF369D047BE259C036AD148BF269C037AE158CF269D047BE ),
.INIT_03 ( 256'h59C037AE158CF36AD148BF269D047BE158CF36AD148BF269D047BE158CF36AD1 ),
.INIT_04 ( 256'h58CF36AD148BF26AD148BF269D047BE259C037AE158CF36AD148BF269D047BE2 ),
.INIT_05 ( 256'h259C037BE259C037BE259C037BE259C037BE259C037AE259C037AE158CF37AE1 ),
.INIT_06 ( 256'hCF36AE158C037BE259D047BF269D148BF36AD148CF36AE158C037AE159C037AE ),
.INIT_07 ( 256'h26AD158C037BE269D148BF36AE159C047BF26AD148CF37AE259C047BF269D148 ),
.INIT_08 ( 256'h59C048BF37AE259D148C037BE26AD158C037BF26AD158C047BF26AD158C037BE ),
.INIT_09 ( 256'h37BF36AE269D159C048CF37BF26AE159D148C037BF26AE159D048CF37BE26AD1 ),
.INIT_0A ( 256'hD159D048C048C037BF37BE26AE269D159D148C048BF37BF26AE269D159D048C0 ),
.INIT_0B ( 256'h159D159D159D159D159D159D048C048C048C048BF37BF37BF36AE26AE26AD159 ),
.INIT_0C ( 256'h048C049D159D159D159D159D159D159E26AE26AE26AE26AE26AE26AE26AE26AD ),
.INIT_0D ( 256'h9D159D26AE26BF37BF38C048C049D159D15AE26AE26AE37BF37BF37B048C048C ),
.INIT_0E ( 256'hAF37C048D159E26AF37B048C159D16AE27BF37C048D159D26AE26BF37B048C04 ),
.INIT_0F ( 256'h5AE27B048D15AE27B048D15AE27BF48C159E26BF38C059D26AE37B048C159E26 ),
.INIT_10 ( 256'h8D16AF38C15AE37C059E27B049D16AF38C15AE27B049D16AF38C059E26BF48C1 ),
.INIT_11 ( 256'h48D26BF49D27B049E27B059E27C059E27C059E27C059E27B059E27B049D26BF4 ),
.INIT_12 ( 256'h6B059E38C16BF49E27C15AF48D26B059E37C16AF48D26B049E27C05AE38C16AF ),
.INIT_13 ( 256'h05AF49E38C16B05AF48D27C16AF49E38C16B059E38D26B05AE38D26B05AE38D2 ),
.INIT_14 ( 256'h16B05AF49E38D28D27C16B05AF49E38D27C16B05AF48D27C16B05AF49E38D16B ),
.INIT_15 ( 256'h8D27D27C17C16B16B05A05AF49F49E38E38D27C17C16B05AF5AF49E38D27D27C ),
.INIT_16 ( 256'h4AF5AF5AF5AF5A05A05A05A05A05AF5AF5AF5AF4AF4AF49F49E49E39E38E38D2 ),
.INIT_17 ( 256'h7C27D28D38E39F4AF5A05B06B16B16C17C27D28D28D38E39E39E49E49F49F4AF ),
.INIT_18 ( 256'hE49F5A06C17D28E39F4A05B16C27D38E49F4A05B16C17D28D39E49F5A05B06B1 ),
.INIT_19 ( 256'hA05B17D39F5A06C28E39F5B17C28E4AF5B17C28E49F5B16C28D39F4A06B17D28 ),
.INIT_1A ( 256'hA06C28E4A07D39F5B17D39F5B17D39F5B17D39F5B17D39F5B17D38E4A06C28E4 ),
.INIT_1B ( 256'hE4A17D3A06C39F5C28E5B17D4A06C39F5B28E4A07D39F5C28E4A07D39F5B17E4 ),
.INIT_1C ( 256'h5C29F5C29F6C3906C3906D3906D3906D3906C3906C39F6C29F5C28F5B28E5B17 ),
.INIT_1D ( 256'h06D4A18E5C2906D4A18E5B29F6C3A07D4B18E5B29F6C3906D3A17E4B18E5B28F ),
.INIT_1E ( 256'hD4B28F6D4B29F6D4B29F6D4B28F6D4A18F6C3A17E5C2907D4B28F6D3A17E5C29 ),
.INIT_1F ( 256'hD4B2907E5C4B2907E5C3A18F6D4B2907E6D3A18F6D4B2907E5C3A18F6D3A18F6 ),
.INIT_20 ( 256'hE6D4C3A2908F6D5C3B2908F6D5C3A2907E6D4B3A18F6E5C3A2907E5C4B2907E6 ),
.INIT_21 ( 256'h291808F7E6D5C4B3A291807F6E5D4C3A291807E6D5C4B2A1907F6D5C4B2A1807 ),
.INIT_22 ( 256'h7E6E6E5D5D4C4C3B3B2A29191808F7F6E6D5D4C4B3B2A291808F7E6E5D4C4B3A ),
.INIT_23 ( 256'hC4D5D5D5D5D5D5C4C4C4C4C4C4C4C4C4B3B3B3B3B2A2A2A29191919080807F7F ),
.INIT_24 ( 256'h3B4C4C5D5D6E6E6F7F7F808081919192A2A2A2B3B3B3B3B3C4C4C4C4C4C4C4C4 ),
.INIT_25 ( 256'hA3B4C5D6E7F808192A3B4C5D5E6F7F809192A2B3C4C5D5E6E7F70809191A2A3B ),
.INIT_26 ( 256'h1A3C4D6F7092A3C4D6E7091A3B4D5E6F8092A3C4D5E7F8091A3B4C5D6E708192 ),
.INIT_27 ( 256'h81A3C5E7092B4D6F81A3C5E7092A3C5E7092A3C5E7081A3C5D6F81A2B4D6E709 ),
.INIT_28 ( 256'hF82B4D7092C5E71A3C5F81A3D6F81A4D6F81A4D6F81A3C5F81A3C5E7092B4D6F ),
.INIT_29 ( 256'h5F82B5E81B4E71A4D70A3C6F92C5F81B4E70A3D6F92B5E71A4D6092B5E71A3D6 ),
.INIT_2A ( 256'hA4E81B5F82C6093D70A4D71B4E81B5E82B5F82C5F92C6F92C6F92C6F92C5F82C ),
.INIT_2B ( 256'hE82C60A4F93D71B5F93D71B5F93D60A4E82C60A4E81B5F93D71A4E82C5F93D70 ),
.INIT_2C ( 256'h1B50A4F93E82C71B60A4F93D82C61B5FA4E82D71B5FA4E82C61B5F93D72C60A4 ),
.INIT_2D ( 256'h1C71C61C61B61B60B50B50A5FA4F94E93E83D82D71C61B60A5FA4E93E82D71C6 ),
.INIT_2E ( 256'h0B61C72D82D83E94E94FA4FA50B50B60B61B61C61C71C71C72C72C72C72C72C7 ),
.INIT_2F ( 256'hD94FA50C72D83FA50B61C73E94FA50B61C72D83E94FA50B61C72D83E94FA50B6 ),
.INIT_30 ( 256'h84FB62D84FB62D84FB61D84FA61C83EA50C72E940B61D83FA50C72D94FA51C72 ),
.INIT_31 ( 256'h1C840B73EA62D950C84FB72EA51D84FB72E951C83FB62D940C73EA51C83FA61D ),
.INIT_32 ( 256'h62EA62FB73FB73FB73FB62EA62EA62EA62E951D951D840C840B73FB62EA61D95 ),
.INIT_33 ( 256'h962EB730C851D962EB73FC840D951DA62EB73FB740C840D951D951DA62EA62EA ),
.INIT_34 ( 256'h963FC952EB841DA730C952FB841DA63FC851EA730C851EA730C851EA63FB841D ),
.INIT_35 ( 256'h730DA741EB852EB852FC852FC952FC962FC952FC952FC852EB851EB741DA730D ),
.INIT_36 ( 256'h0EB8530DA752FC9741EB8630DA741FC9630DA741FC9630DA741EB852FC9630DA ),
.INIT_37 ( 256'h7520DB8631EC9742FDA8530DB8631EB9641EC9741FC9741FC9741FC9641EB963 ),
.INIT_38 ( 256'hB86420EB97530ECA8531FCA8631FCA8631FCA8531ECA7530EB9742FDB8631FCA ),
.INIT_39 ( 256'hA97531FDCA86420ECA86531FDB97531FDB97531FDB97530ECA86420EC97531FD ),
.INIT_3A ( 256'h75421FDCA976421FECA975420FDBA865310ECB975420EDB976420EDB975420EC ),
.INIT_3B ( 256'h0EDCB98764320FEDBA9765321FEDBA8764310FDCA9865320FDCA9764310EDBA8 ),
.INIT_3C ( 256'h543210FEDCBA9876543210FEDCBA987654210FEDCBA87654320FEDCB98765321 ),
.INIT_3D ( 256'h66544322100FEEDCCBAA9877655432110FEEDCBAA987655432100FEDCBA98876 ),
.INIT_3E ( 256'h44333222111000FFEEEDDCCCBBAA998887766554433221100FEEDDCCBAA99877 ),
.INIT_3F ( 256'hEEEEEEEEEEEEEEDDDDDDDDDDDCCCCCCCBBBBBBAAAAA999998888777766655554 ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk00000150 (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk00000150_DIPA<3>_UNCONNECTED , \NLW_blk00000150_DIPA<2>_UNCONNECTED , \NLW_blk00000150_DIPA<1>_UNCONNECTED ,
\NLW_blk00000150_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk00000150_DOA<31>_UNCONNECTED , \NLW_blk00000150_DOA<30>_UNCONNECTED , \NLW_blk00000150_DOA<29>_UNCONNECTED ,
\NLW_blk00000150_DOA<28>_UNCONNECTED , \NLW_blk00000150_DOA<27>_UNCONNECTED , \NLW_blk00000150_DOA<26>_UNCONNECTED ,
\NLW_blk00000150_DOA<25>_UNCONNECTED , \NLW_blk00000150_DOA<24>_UNCONNECTED , \NLW_blk00000150_DOA<23>_UNCONNECTED ,
\NLW_blk00000150_DOA<22>_UNCONNECTED , \NLW_blk00000150_DOA<21>_UNCONNECTED , \NLW_blk00000150_DOA<20>_UNCONNECTED ,
\NLW_blk00000150_DOA<19>_UNCONNECTED , \NLW_blk00000150_DOA<18>_UNCONNECTED , \NLW_blk00000150_DOA<17>_UNCONNECTED ,
\NLW_blk00000150_DOA<16>_UNCONNECTED , \NLW_blk00000150_DOA<15>_UNCONNECTED , \NLW_blk00000150_DOA<14>_UNCONNECTED ,
\NLW_blk00000150_DOA<13>_UNCONNECTED , \NLW_blk00000150_DOA<12>_UNCONNECTED , \NLW_blk00000150_DOA<11>_UNCONNECTED ,
\NLW_blk00000150_DOA<10>_UNCONNECTED , \NLW_blk00000150_DOA<9>_UNCONNECTED , \NLW_blk00000150_DOA<8>_UNCONNECTED ,
\NLW_blk00000150_DOA<7>_UNCONNECTED , \NLW_blk00000150_DOA<6>_UNCONNECTED , \NLW_blk00000150_DOA<5>_UNCONNECTED , \NLW_blk00000150_DOA<4>_UNCONNECTED
, sig000000d5, sig000000d4, sig000000d3, sig000000d2}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk00000150_ADDRA<1>_UNCONNECTED , \NLW_blk00000150_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk00000150_ADDRB<1>_UNCONNECTED , \NLW_blk00000150_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk00000150_DIB<31>_UNCONNECTED , \NLW_blk00000150_DIB<30>_UNCONNECTED , \NLW_blk00000150_DIB<29>_UNCONNECTED ,
\NLW_blk00000150_DIB<28>_UNCONNECTED , \NLW_blk00000150_DIB<27>_UNCONNECTED , \NLW_blk00000150_DIB<26>_UNCONNECTED ,
\NLW_blk00000150_DIB<25>_UNCONNECTED , \NLW_blk00000150_DIB<24>_UNCONNECTED , \NLW_blk00000150_DIB<23>_UNCONNECTED ,
\NLW_blk00000150_DIB<22>_UNCONNECTED , \NLW_blk00000150_DIB<21>_UNCONNECTED , \NLW_blk00000150_DIB<20>_UNCONNECTED ,
\NLW_blk00000150_DIB<19>_UNCONNECTED , \NLW_blk00000150_DIB<18>_UNCONNECTED , \NLW_blk00000150_DIB<17>_UNCONNECTED ,
\NLW_blk00000150_DIB<16>_UNCONNECTED , \NLW_blk00000150_DIB<15>_UNCONNECTED , \NLW_blk00000150_DIB<14>_UNCONNECTED ,
\NLW_blk00000150_DIB<13>_UNCONNECTED , \NLW_blk00000150_DIB<12>_UNCONNECTED , \NLW_blk00000150_DIB<11>_UNCONNECTED ,
\NLW_blk00000150_DIB<10>_UNCONNECTED , \NLW_blk00000150_DIB<9>_UNCONNECTED , \NLW_blk00000150_DIB<8>_UNCONNECTED ,
\NLW_blk00000150_DIB<7>_UNCONNECTED , \NLW_blk00000150_DIB<6>_UNCONNECTED , \NLW_blk00000150_DIB<5>_UNCONNECTED , \NLW_blk00000150_DIB<4>_UNCONNECTED
, \NLW_blk00000150_DIB<3>_UNCONNECTED , \NLW_blk00000150_DIB<2>_UNCONNECTED , \NLW_blk00000150_DIB<1>_UNCONNECTED ,
\NLW_blk00000150_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk00000150_DOPA<3>_UNCONNECTED , \NLW_blk00000150_DOPA<2>_UNCONNECTED , \NLW_blk00000150_DOPA<1>_UNCONNECTED ,
\NLW_blk00000150_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000150_DIPB<3>_UNCONNECTED , \NLW_blk00000150_DIPB<2>_UNCONNECTED , \NLW_blk00000150_DIPB<1>_UNCONNECTED ,
\NLW_blk00000150_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000150_DOPB<3>_UNCONNECTED , \NLW_blk00000150_DOPB<2>_UNCONNECTED , \NLW_blk00000150_DOPB<1>_UNCONNECTED ,
\NLW_blk00000150_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000150_DOB<31>_UNCONNECTED , \NLW_blk00000150_DOB<30>_UNCONNECTED , \NLW_blk00000150_DOB<29>_UNCONNECTED ,
\NLW_blk00000150_DOB<28>_UNCONNECTED , \NLW_blk00000150_DOB<27>_UNCONNECTED , \NLW_blk00000150_DOB<26>_UNCONNECTED ,
\NLW_blk00000150_DOB<25>_UNCONNECTED , \NLW_blk00000150_DOB<24>_UNCONNECTED , \NLW_blk00000150_DOB<23>_UNCONNECTED ,
\NLW_blk00000150_DOB<22>_UNCONNECTED , \NLW_blk00000150_DOB<21>_UNCONNECTED , \NLW_blk00000150_DOB<20>_UNCONNECTED ,
\NLW_blk00000150_DOB<19>_UNCONNECTED , \NLW_blk00000150_DOB<18>_UNCONNECTED , \NLW_blk00000150_DOB<17>_UNCONNECTED ,
\NLW_blk00000150_DOB<16>_UNCONNECTED , \NLW_blk00000150_DOB<15>_UNCONNECTED , \NLW_blk00000150_DOB<14>_UNCONNECTED ,
\NLW_blk00000150_DOB<13>_UNCONNECTED , \NLW_blk00000150_DOB<12>_UNCONNECTED , \NLW_blk00000150_DOB<11>_UNCONNECTED ,
\NLW_blk00000150_DOB<10>_UNCONNECTED , \NLW_blk00000150_DOB<9>_UNCONNECTED , \NLW_blk00000150_DOB<8>_UNCONNECTED ,
\NLW_blk00000150_DOB<7>_UNCONNECTED , \NLW_blk00000150_DOB<6>_UNCONNECTED , \NLW_blk00000150_DOB<5>_UNCONNECTED , \NLW_blk00000150_DOB<4>_UNCONNECTED
, sig000000c6, sig000000c5, sig000000c4, sig000000c3}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk00000150_DIA<31>_UNCONNECTED , \NLW_blk00000150_DIA<30>_UNCONNECTED , \NLW_blk00000150_DIA<29>_UNCONNECTED ,
\NLW_blk00000150_DIA<28>_UNCONNECTED , \NLW_blk00000150_DIA<27>_UNCONNECTED , \NLW_blk00000150_DIA<26>_UNCONNECTED ,
\NLW_blk00000150_DIA<25>_UNCONNECTED , \NLW_blk00000150_DIA<24>_UNCONNECTED , \NLW_blk00000150_DIA<23>_UNCONNECTED ,
\NLW_blk00000150_DIA<22>_UNCONNECTED , \NLW_blk00000150_DIA<21>_UNCONNECTED , \NLW_blk00000150_DIA<20>_UNCONNECTED ,
\NLW_blk00000150_DIA<19>_UNCONNECTED , \NLW_blk00000150_DIA<18>_UNCONNECTED , \NLW_blk00000150_DIA<17>_UNCONNECTED ,
\NLW_blk00000150_DIA<16>_UNCONNECTED , \NLW_blk00000150_DIA<15>_UNCONNECTED , \NLW_blk00000150_DIA<14>_UNCONNECTED ,
\NLW_blk00000150_DIA<13>_UNCONNECTED , \NLW_blk00000150_DIA<12>_UNCONNECTED , \NLW_blk00000150_DIA<11>_UNCONNECTED ,
\NLW_blk00000150_DIA<10>_UNCONNECTED , \NLW_blk00000150_DIA<9>_UNCONNECTED , \NLW_blk00000150_DIA<8>_UNCONNECTED ,
\NLW_blk00000150_DIA<7>_UNCONNECTED , \NLW_blk00000150_DIA<6>_UNCONNECTED , \NLW_blk00000150_DIA<5>_UNCONNECTED , \NLW_blk00000150_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000151 (
.A0(sig00000001),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig00000125),
.Q(sig00000129),
.Q15(NLW_blk00000151_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000152 (
.C(clk),
.CE(sig00000001),
.D(sig00000129),
.Q(sig00000123)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000153 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig00000126),
.Q(sig0000012a),
.Q15(NLW_blk00000153_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000154 (
.C(clk),
.CE(sig00000001),
.D(sig0000012a),
.Q(sig00000124)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000155 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d1),
.Q(sig0000012b),
.Q15(NLW_blk00000155_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000156 (
.C(clk),
.CE(sig00000001),
.D(sig0000012b),
.Q(sig00000113)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000157 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d0),
.Q(sig0000012c),
.Q15(NLW_blk00000157_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000158 (
.C(clk),
.CE(sig00000001),
.D(sig0000012c),
.Q(sig00000112)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000159 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cf),
.Q(sig0000012d),
.Q15(NLW_blk00000159_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015a (
.C(clk),
.CE(sig00000001),
.D(sig0000012d),
.Q(sig00000111)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000015b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000ce),
.Q(sig0000012e),
.Q15(NLW_blk0000015b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015c (
.C(clk),
.CE(sig00000001),
.D(sig0000012e),
.Q(sig00000110)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000015d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cd),
.Q(sig0000012f),
.Q15(NLW_blk0000015d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015e (
.C(clk),
.CE(sig00000001),
.D(sig0000012f),
.Q(sig0000010f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000015f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cc),
.Q(sig00000130),
.Q15(NLW_blk0000015f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000160 (
.C(clk),
.CE(sig00000001),
.D(sig00000130),
.Q(sig0000010e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000161 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cb),
.Q(sig00000131),
.Q15(NLW_blk00000161_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000162 (
.C(clk),
.CE(sig00000001),
.D(sig00000131),
.Q(sig0000010d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000163 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000ca),
.Q(sig00000132),
.Q15(NLW_blk00000163_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000164 (
.C(clk),
.CE(sig00000001),
.D(sig00000132),
.Q(sig0000010c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000165 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c9),
.Q(sig00000133),
.Q15(NLW_blk00000165_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000166 (
.C(clk),
.CE(sig00000001),
.D(sig00000133),
.Q(sig0000010b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000167 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c8),
.Q(sig00000134),
.Q15(NLW_blk00000167_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000168 (
.C(clk),
.CE(sig00000001),
.D(sig00000134),
.Q(sig0000010a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000169 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c7),
.Q(sig00000135),
.Q15(NLW_blk00000169_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016a (
.C(clk),
.CE(sig00000001),
.D(sig00000135),
.Q(sig00000109)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000016b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c6),
.Q(sig00000136),
.Q15(NLW_blk0000016b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016c (
.C(clk),
.CE(sig00000001),
.D(sig00000136),
.Q(sig00000108)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000016d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c5),
.Q(sig00000137),
.Q15(NLW_blk0000016d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016e (
.C(clk),
.CE(sig00000001),
.D(sig00000137),
.Q(sig00000107)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000016f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c4),
.Q(sig00000138),
.Q15(NLW_blk0000016f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000170 (
.C(clk),
.CE(sig00000001),
.D(sig00000138),
.Q(sig00000106)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000171 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c3),
.Q(sig00000139),
.Q15(NLW_blk00000171_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000172 (
.C(clk),
.CE(sig00000001),
.D(sig00000139),
.Q(sig00000105)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000173 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000e0),
.Q(sig0000013a),
.Q15(NLW_blk00000173_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000174 (
.C(clk),
.CE(sig00000001),
.D(sig0000013a),
.Q(sig00000122)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000175 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000df),
.Q(sig0000013b),
.Q15(NLW_blk00000175_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000176 (
.C(clk),
.CE(sig00000001),
.D(sig0000013b),
.Q(sig00000121)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000177 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000de),
.Q(sig0000013c),
.Q15(NLW_blk00000177_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000178 (
.C(clk),
.CE(sig00000001),
.D(sig0000013c),
.Q(sig00000120)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000179 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000dd),
.Q(sig0000013d),
.Q15(NLW_blk00000179_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017a (
.C(clk),
.CE(sig00000001),
.D(sig0000013d),
.Q(sig0000011f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000017b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000dc),
.Q(sig0000013e),
.Q15(NLW_blk0000017b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017c (
.C(clk),
.CE(sig00000001),
.D(sig0000013e),
.Q(sig0000011e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000017d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000db),
.Q(sig0000013f),
.Q15(NLW_blk0000017d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017e (
.C(clk),
.CE(sig00000001),
.D(sig0000013f),
.Q(sig0000011d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000017f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000da),
.Q(sig00000140),
.Q15(NLW_blk0000017f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000180 (
.C(clk),
.CE(sig00000001),
.D(sig00000140),
.Q(sig0000011c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000181 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d9),
.Q(sig00000141),
.Q15(NLW_blk00000181_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000182 (
.C(clk),
.CE(sig00000001),
.D(sig00000141),
.Q(sig0000011b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000183 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d8),
.Q(sig00000142),
.Q15(NLW_blk00000183_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000184 (
.C(clk),
.CE(sig00000001),
.D(sig00000142),
.Q(sig0000011a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000185 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d7),
.Q(sig00000143),
.Q15(NLW_blk00000185_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000186 (
.C(clk),
.CE(sig00000001),
.D(sig00000143),
.Q(sig00000119)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000187 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d6),
.Q(sig00000144),
.Q15(NLW_blk00000187_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000188 (
.C(clk),
.CE(sig00000001),
.D(sig00000144),
.Q(sig00000118)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000189 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d5),
.Q(sig00000145),
.Q15(NLW_blk00000189_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018a (
.C(clk),
.CE(sig00000001),
.D(sig00000145),
.Q(sig00000117)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000018b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d4),
.Q(sig00000146),
.Q15(NLW_blk0000018b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018c (
.C(clk),
.CE(sig00000001),
.D(sig00000146),
.Q(sig00000116)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000018d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d3),
.Q(sig00000147),
.Q15(NLW_blk0000018d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018e (
.C(clk),
.CE(sig00000001),
.D(sig00000147),
.Q(sig00000115)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000018f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d2),
.Q(sig00000148),
.Q15(NLW_blk0000018f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000190 (
.C(clk),
.CE(sig00000001),
.D(sig00000148),
.Q(sig00000114)
);
XORCY \blk00000025/blk00000055 (
.CI(\blk00000025/sig00000197 ),
.LI(\blk00000025/sig00000198 ),
.O(sig00000004)
);
MUXCY \blk00000025/blk00000054 (
.CI(\blk00000025/sig00000197 ),
.DI(sig00000045),
.S(\blk00000025/sig00000198 ),
.O(sig00000003)
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000053 (
.I0(sig00000045),
.I1(sig00000002),
.O(\blk00000025/sig00000198 )
);
XORCY \blk00000025/blk00000052 (
.CI(\blk00000025/sig00000195 ),
.LI(\blk00000025/sig00000196 ),
.O(sig00000005)
);
MUXCY \blk00000025/blk00000051 (
.CI(\blk00000025/sig00000195 ),
.DI(sig00000044),
.S(\blk00000025/sig00000196 ),
.O(\blk00000025/sig00000197 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000050 (
.I0(sig00000044),
.I1(sig00000002),
.O(\blk00000025/sig00000196 )
);
XORCY \blk00000025/blk0000004f (
.CI(\blk00000025/sig00000193 ),
.LI(\blk00000025/sig00000194 ),
.O(sig00000006)
);
MUXCY \blk00000025/blk0000004e (
.CI(\blk00000025/sig00000193 ),
.DI(sig00000043),
.S(\blk00000025/sig00000194 ),
.O(\blk00000025/sig00000195 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000004d (
.I0(sig00000043),
.I1(sig00000002),
.O(\blk00000025/sig00000194 )
);
XORCY \blk00000025/blk0000004c (
.CI(\blk00000025/sig00000191 ),
.LI(\blk00000025/sig00000192 ),
.O(sig00000007)
);
MUXCY \blk00000025/blk0000004b (
.CI(\blk00000025/sig00000191 ),
.DI(sig00000042),
.S(\blk00000025/sig00000192 ),
.O(\blk00000025/sig00000193 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000004a (
.I0(sig00000042),
.I1(sig00000002),
.O(\blk00000025/sig00000192 )
);
XORCY \blk00000025/blk00000049 (
.CI(\blk00000025/sig0000018f ),
.LI(\blk00000025/sig00000190 ),
.O(sig00000008)
);
MUXCY \blk00000025/blk00000048 (
.CI(\blk00000025/sig0000018f ),
.DI(sig00000041),
.S(\blk00000025/sig00000190 ),
.O(\blk00000025/sig00000191 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000047 (
.I0(sig00000041),
.I1(sig00000002),
.O(\blk00000025/sig00000190 )
);
XORCY \blk00000025/blk00000046 (
.CI(\blk00000025/sig0000018d ),
.LI(\blk00000025/sig0000018e ),
.O(sig00000009)
);
MUXCY \blk00000025/blk00000045 (
.CI(\blk00000025/sig0000018d ),
.DI(sig00000040),
.S(\blk00000025/sig0000018e ),
.O(\blk00000025/sig0000018f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000044 (
.I0(sig00000040),
.I1(sig00000002),
.O(\blk00000025/sig0000018e )
);
XORCY \blk00000025/blk00000043 (
.CI(\blk00000025/sig0000018b ),
.LI(\blk00000025/sig0000018c ),
.O(sig0000000a)
);
MUXCY \blk00000025/blk00000042 (
.CI(\blk00000025/sig0000018b ),
.DI(sig0000003f),
.S(\blk00000025/sig0000018c ),
.O(\blk00000025/sig0000018d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000041 (
.I0(sig0000003f),
.I1(sig00000002),
.O(\blk00000025/sig0000018c )
);
XORCY \blk00000025/blk00000040 (
.CI(\blk00000025/sig00000189 ),
.LI(\blk00000025/sig0000018a ),
.O(sig0000000b)
);
MUXCY \blk00000025/blk0000003f (
.CI(\blk00000025/sig00000189 ),
.DI(sig0000003e),
.S(\blk00000025/sig0000018a ),
.O(\blk00000025/sig0000018b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000003e (
.I0(sig0000003e),
.I1(sig00000001),
.O(\blk00000025/sig0000018a )
);
XORCY \blk00000025/blk0000003d (
.CI(\blk00000025/sig00000187 ),
.LI(\blk00000025/sig00000188 ),
.O(sig0000000c)
);
MUXCY \blk00000025/blk0000003c (
.CI(\blk00000025/sig00000187 ),
.DI(sig0000003d),
.S(\blk00000025/sig00000188 ),
.O(\blk00000025/sig00000189 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000003b (
.I0(sig0000003d),
.I1(sig00000001),
.O(\blk00000025/sig00000188 )
);
XORCY \blk00000025/blk0000003a (
.CI(\blk00000025/sig00000185 ),
.LI(\blk00000025/sig00000186 ),
.O(sig0000000d)
);
MUXCY \blk00000025/blk00000039 (
.CI(\blk00000025/sig00000185 ),
.DI(sig0000003c),
.S(\blk00000025/sig00000186 ),
.O(\blk00000025/sig00000187 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000038 (
.I0(sig0000003c),
.I1(sig00000002),
.O(\blk00000025/sig00000186 )
);
XORCY \blk00000025/blk00000037 (
.CI(\blk00000025/sig00000183 ),
.LI(\blk00000025/sig00000184 ),
.O(sig0000000e)
);
MUXCY \blk00000025/blk00000036 (
.CI(\blk00000025/sig00000183 ),
.DI(sig0000003b),
.S(\blk00000025/sig00000184 ),
.O(\blk00000025/sig00000185 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000035 (
.I0(sig0000003b),
.I1(sig00000002),
.O(\blk00000025/sig00000184 )
);
XORCY \blk00000025/blk00000034 (
.CI(\blk00000025/sig00000181 ),
.LI(\blk00000025/sig00000182 ),
.O(sig0000000f)
);
MUXCY \blk00000025/blk00000033 (
.CI(\blk00000025/sig00000181 ),
.DI(sig0000003a),
.S(\blk00000025/sig00000182 ),
.O(\blk00000025/sig00000183 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000032 (
.I0(sig00000002),
.I1(sig0000003a),
.O(\blk00000025/sig00000182 )
);
XORCY \blk00000025/blk00000031 (
.CI(\blk00000025/sig0000017f ),
.LI(\blk00000025/sig00000180 ),
.O(sig00000010)
);
MUXCY \blk00000025/blk00000030 (
.CI(\blk00000025/sig0000017f ),
.DI(sig00000039),
.S(\blk00000025/sig00000180 ),
.O(\blk00000025/sig00000181 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000002f (
.I0(sig00000001),
.I1(sig00000039),
.O(\blk00000025/sig00000180 )
);
XORCY \blk00000025/blk0000002e (
.CI(\blk00000025/sig0000017d ),
.LI(\blk00000025/sig0000017e ),
.O(sig00000011)
);
MUXCY \blk00000025/blk0000002d (
.CI(\blk00000025/sig0000017d ),
.DI(sig00000038),
.S(\blk00000025/sig0000017e ),
.O(\blk00000025/sig0000017f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000002c (
.I0(sig00000002),
.I1(sig00000038),
.O(\blk00000025/sig0000017e )
);
XORCY \blk00000025/blk0000002b (
.CI(\blk00000025/sig0000017b ),
.LI(\blk00000025/sig0000017c ),
.O(sig00000012)
);
MUXCY \blk00000025/blk0000002a (
.CI(\blk00000025/sig0000017b ),
.DI(sig00000037),
.S(\blk00000025/sig0000017c ),
.O(\blk00000025/sig0000017d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000029 (
.I0(sig00000001),
.I1(sig00000037),
.O(\blk00000025/sig0000017c )
);
XORCY \blk00000025/blk00000028 (
.CI(sig00000002),
.LI(\blk00000025/sig0000017a ),
.O(sig00000013)
);
MUXCY \blk00000025/blk00000027 (
.CI(sig00000002),
.DI(sig00000036),
.S(\blk00000025/sig0000017a ),
.O(\blk00000025/sig0000017b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000026 (
.I0(sig00000002),
.I1(sig00000036),
.O(\blk00000025/sig0000017a )
);
XORCY \blk00000056/blk00000086 (
.CI(\blk00000056/sig000001e8 ),
.LI(\blk00000056/sig000001e9 ),
.O(sig00000023)
);
MUXCY \blk00000056/blk00000085 (
.CI(\blk00000056/sig000001e8 ),
.DI(sig00000045),
.S(\blk00000056/sig000001e9 ),
.O(sig00000024)
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000084 (
.I0(sig00000045),
.I1(sig00000035),
.O(\blk00000056/sig000001e9 )
);
XORCY \blk00000056/blk00000083 (
.CI(\blk00000056/sig000001e6 ),
.LI(\blk00000056/sig000001e7 ),
.O(sig00000022)
);
MUXCY \blk00000056/blk00000082 (
.CI(\blk00000056/sig000001e6 ),
.DI(sig00000044),
.S(\blk00000056/sig000001e7 ),
.O(\blk00000056/sig000001e8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000081 (
.I0(sig00000044),
.I1(sig00000035),
.O(\blk00000056/sig000001e7 )
);
XORCY \blk00000056/blk00000080 (
.CI(\blk00000056/sig000001e4 ),
.LI(\blk00000056/sig000001e5 ),
.O(sig00000021)
);
MUXCY \blk00000056/blk0000007f (
.CI(\blk00000056/sig000001e4 ),
.DI(sig00000043),
.S(\blk00000056/sig000001e5 ),
.O(\blk00000056/sig000001e6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000007e (
.I0(sig00000043),
.I1(sig00000035),
.O(\blk00000056/sig000001e5 )
);
XORCY \blk00000056/blk0000007d (
.CI(\blk00000056/sig000001e2 ),
.LI(\blk00000056/sig000001e3 ),
.O(sig00000020)
);
MUXCY \blk00000056/blk0000007c (
.CI(\blk00000056/sig000001e2 ),
.DI(sig00000042),
.S(\blk00000056/sig000001e3 ),
.O(\blk00000056/sig000001e4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000007b (
.I0(sig00000042),
.I1(sig00000035),
.O(\blk00000056/sig000001e3 )
);
XORCY \blk00000056/blk0000007a (
.CI(\blk00000056/sig000001e0 ),
.LI(\blk00000056/sig000001e1 ),
.O(sig0000001f)
);
MUXCY \blk00000056/blk00000079 (
.CI(\blk00000056/sig000001e0 ),
.DI(sig00000041),
.S(\blk00000056/sig000001e1 ),
.O(\blk00000056/sig000001e2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000078 (
.I0(sig00000041),
.I1(sig00000035),
.O(\blk00000056/sig000001e1 )
);
XORCY \blk00000056/blk00000077 (
.CI(\blk00000056/sig000001de ),
.LI(\blk00000056/sig000001df ),
.O(sig0000001e)
);
MUXCY \blk00000056/blk00000076 (
.CI(\blk00000056/sig000001de ),
.DI(sig00000040),
.S(\blk00000056/sig000001df ),
.O(\blk00000056/sig000001e0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000075 (
.I0(sig00000040),
.I1(sig00000035),
.O(\blk00000056/sig000001df )
);
XORCY \blk00000056/blk00000074 (
.CI(\blk00000056/sig000001dc ),
.LI(\blk00000056/sig000001dd ),
.O(sig0000001d)
);
MUXCY \blk00000056/blk00000073 (
.CI(\blk00000056/sig000001dc ),
.DI(sig0000003f),
.S(\blk00000056/sig000001dd ),
.O(\blk00000056/sig000001de )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000072 (
.I0(sig0000003f),
.I1(sig00000035),
.O(\blk00000056/sig000001dd )
);
XORCY \blk00000056/blk00000071 (
.CI(\blk00000056/sig000001da ),
.LI(\blk00000056/sig000001db ),
.O(sig0000001c)
);
MUXCY \blk00000056/blk00000070 (
.CI(\blk00000056/sig000001da ),
.DI(sig0000003e),
.S(\blk00000056/sig000001db ),
.O(\blk00000056/sig000001dc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000006f (
.I0(sig0000003e),
.I1(sig00000035),
.O(\blk00000056/sig000001db )
);
XORCY \blk00000056/blk0000006e (
.CI(\blk00000056/sig000001d8 ),
.LI(\blk00000056/sig000001d9 ),
.O(sig0000001b)
);
MUXCY \blk00000056/blk0000006d (
.CI(\blk00000056/sig000001d8 ),
.DI(sig0000003d),
.S(\blk00000056/sig000001d9 ),
.O(\blk00000056/sig000001da )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000006c (
.I0(sig0000003d),
.I1(sig00000035),
.O(\blk00000056/sig000001d9 )
);
XORCY \blk00000056/blk0000006b (
.CI(\blk00000056/sig000001d6 ),
.LI(\blk00000056/sig000001d7 ),
.O(sig0000001a)
);
MUXCY \blk00000056/blk0000006a (
.CI(\blk00000056/sig000001d6 ),
.DI(sig0000003c),
.S(\blk00000056/sig000001d7 ),
.O(\blk00000056/sig000001d8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000069 (
.I0(sig0000003c),
.I1(sig00000035),
.O(\blk00000056/sig000001d7 )
);
XORCY \blk00000056/blk00000068 (
.CI(\blk00000056/sig000001d4 ),
.LI(\blk00000056/sig000001d5 ),
.O(sig00000019)
);
MUXCY \blk00000056/blk00000067 (
.CI(\blk00000056/sig000001d4 ),
.DI(sig0000003b),
.S(\blk00000056/sig000001d5 ),
.O(\blk00000056/sig000001d6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000066 (
.I0(sig0000003b),
.I1(sig00000035),
.O(\blk00000056/sig000001d5 )
);
XORCY \blk00000056/blk00000065 (
.CI(\blk00000056/sig000001d2 ),
.LI(\blk00000056/sig000001d3 ),
.O(sig00000018)
);
MUXCY \blk00000056/blk00000064 (
.CI(\blk00000056/sig000001d2 ),
.DI(sig0000003a),
.S(\blk00000056/sig000001d3 ),
.O(\blk00000056/sig000001d4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000063 (
.I0(sig0000003a),
.I1(sig00000035),
.O(\blk00000056/sig000001d3 )
);
XORCY \blk00000056/blk00000062 (
.CI(\blk00000056/sig000001d0 ),
.LI(\blk00000056/sig000001d1 ),
.O(sig00000017)
);
MUXCY \blk00000056/blk00000061 (
.CI(\blk00000056/sig000001d0 ),
.DI(sig00000039),
.S(\blk00000056/sig000001d1 ),
.O(\blk00000056/sig000001d2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000060 (
.I0(sig00000039),
.I1(sig00000035),
.O(\blk00000056/sig000001d1 )
);
XORCY \blk00000056/blk0000005f (
.CI(\blk00000056/sig000001ce ),
.LI(\blk00000056/sig000001cf ),
.O(sig00000016)
);
MUXCY \blk00000056/blk0000005e (
.CI(\blk00000056/sig000001ce ),
.DI(sig00000038),
.S(\blk00000056/sig000001cf ),
.O(\blk00000056/sig000001d0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000005d (
.I0(sig00000038),
.I1(sig00000035),
.O(\blk00000056/sig000001cf )
);
XORCY \blk00000056/blk0000005c (
.CI(\blk00000056/sig000001cc ),
.LI(\blk00000056/sig000001cd ),
.O(sig00000015)
);
MUXCY \blk00000056/blk0000005b (
.CI(\blk00000056/sig000001cc ),
.DI(sig00000037),
.S(\blk00000056/sig000001cd ),
.O(\blk00000056/sig000001ce )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000005a (
.I0(sig00000037),
.I1(sig00000034),
.O(\blk00000056/sig000001cd )
);
XORCY \blk00000056/blk00000059 (
.CI(sig00000002),
.LI(\blk00000056/sig000001cb ),
.O(sig00000014)
);
MUXCY \blk00000056/blk00000058 (
.CI(sig00000002),
.DI(sig00000036),
.S(\blk00000056/sig000001cb ),
.O(\blk00000056/sig000001cc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000057 (
.I0(sig00000036),
.I1(sig00000033),
.O(\blk00000056/sig000001cb )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk0000009b (
.I0(\blk00000087/sig000001f1 ),
.I1(\blk00000087/sig000001f0 ),
.O(\blk00000087/sig000001ff )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000087/blk0000009a (
.I0(sig00000033),
.I1(\blk00000087/sig000001f1 ),
.I2(\blk00000087/sig000001f0 ),
.O(\blk00000087/sig000001f8 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000099 (
.I0(\blk00000087/sig000001ef ),
.I1(\blk00000087/sig000001ee ),
.O(\blk00000087/sig000001fe )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000087/blk00000098 (
.I0(sig00000034),
.I1(\blk00000087/sig000001ef ),
.I2(\blk00000087/sig000001ee ),
.O(\blk00000087/sig000001f7 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000097 (
.I0(\blk00000087/sig000001ec ),
.I1(\blk00000087/sig000001ed ),
.O(\blk00000087/sig000001fd )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000087/blk00000096 (
.I0(sig00000035),
.I1(\blk00000087/sig000001ec ),
.I2(\blk00000087/sig000001ed ),
.O(\blk00000087/sig000001f6 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000095 (
.I0(sig00000033),
.I1(\blk00000087/sig000001f2 ),
.O(\blk00000087/sig000001fc )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000094 (
.I0(sig00000035),
.I1(\blk00000087/sig000001ef ),
.O(\blk00000087/sig000001fa )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000093 (
.I0(\blk00000087/sig000001f2 ),
.I1(\blk00000087/sig000001ed ),
.O(\blk00000087/sig000001f9 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000092 (
.I0(sig00000034),
.I1(\blk00000087/sig000001f1 ),
.O(\blk00000087/sig000001fb )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000091 (
.C(clk),
.D(\blk00000087/sig000001fd ),
.Q(\blk00000087/sig000001ec )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000090 (
.C(clk),
.D(\blk00000087/sig000001fe ),
.Q(\blk00000087/sig000001ee )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008f (
.C(clk),
.D(\blk00000087/sig000001ff ),
.Q(\blk00000087/sig000001f0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008e (
.C(clk),
.D(\blk00000087/sig000001f9 ),
.Q(\blk00000087/sig000001ed )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008d (
.C(clk),
.D(\blk00000087/sig000001fa ),
.Q(\blk00000087/sig000001ef )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008c (
.C(clk),
.D(\blk00000087/sig000001fb ),
.Q(\blk00000087/sig000001f1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008b (
.C(clk),
.D(\blk00000087/sig000001fc ),
.Q(\blk00000087/sig000001f2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008a (
.C(clk),
.D(\blk00000087/sig000001f6 ),
.Q(sig00000035)
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000089 (
.C(clk),
.D(\blk00000087/sig000001f7 ),
.Q(sig00000034)
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000088 (
.C(clk),
.D(\blk00000087/sig000001f8 ),
.Q(sig00000033)
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2B_SYMBOL_V
`define SKY130_FD_SC_HD__NOR2B_SYMBOL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2B_SYMBOL_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:26 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_nco_0_0/ip_design_nco_0_0_stub.v
// Design : ip_design_nco_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "nco,Vivado 2017.3" *)
module ip_design_nco_0_0(s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_AWVALID, s_axi_AXILiteS_AWREADY, s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB, s_axi_AXILiteS_WVALID, s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_BRESP, s_axi_AXILiteS_BVALID, s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_ARADDR, s_axi_AXILiteS_ARVALID, s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_RDATA, s_axi_AXILiteS_RRESP, s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY, ap_clk, ap_rst_n)
/* synthesis syn_black_box black_box_pad_pin="s_axi_AXILiteS_AWADDR[5:0],s_axi_AXILiteS_AWVALID,s_axi_AXILiteS_AWREADY,s_axi_AXILiteS_WDATA[31:0],s_axi_AXILiteS_WSTRB[3:0],s_axi_AXILiteS_WVALID,s_axi_AXILiteS_WREADY,s_axi_AXILiteS_BRESP[1:0],s_axi_AXILiteS_BVALID,s_axi_AXILiteS_BREADY,s_axi_AXILiteS_ARADDR[5:0],s_axi_AXILiteS_ARVALID,s_axi_AXILiteS_ARREADY,s_axi_AXILiteS_RDATA[31:0],s_axi_AXILiteS_RRESP[1:0],s_axi_AXILiteS_RVALID,s_axi_AXILiteS_RREADY,ap_clk,ap_rst_n" */;
input [5:0]s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [31:0]s_axi_AXILiteS_WDATA;
input [3:0]s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
output [1:0]s_axi_AXILiteS_BRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
input [5:0]s_axi_AXILiteS_ARADDR;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
output [31:0]s_axi_AXILiteS_RDATA;
output [1:0]s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
input ap_clk;
input ap_rst_n;
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the communication channel
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
`include "viterbidec.v"
`include "cencoder.v"
`include "noisegen.v"
`include "xor2.v"
`include "pipe.v"
`include "pipe2.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
// ============================================================
module tb_communication_channel();
/**
* Description of module to model a communication channel
*
* This includes 3 stages in the communications channel
* @stage 1: Data from the transmitter (TX) is encoded.
* @stage 2: Data is "transmitted" across the communication
* channel, and gets corrupted with noise.
* Noise in the communication channel is modeled
* by pseudo-random noise that corrupts some of
* the data bits
* @stage 3: Data is received at the receiver (RX), and is
* subsequently decoded.
*/
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the communication channel
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// ============================================================
// Declare "wire" signals: outputs from the DUT
// Outputs from the communication channel
wire d; // Output data signal
wire [1:0] c; // Encoded data
wire [1:0] cx; // Corrupted encoded data
wire b; // Original data
// -----------------------------------------------------------
// Encoded data output from the convolutional encoder
wire [1:0] r_c;
//wire [255:0] rf;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// ------------------------------------------------------------
// Inputs to the communication channel
//reg [255:0] r; // Original data: 256 stream of bits
reg r[0:255]; // Original data: 256 stream of bits
reg rr;
/**
* Randomly generated number to determine if data bit should
* be corrupted
*/
reg [7:0] e;
reg clock; // Clock input to all flip-flops
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 1st stage of the communication
* channel
*/
// Original data input & input to the convolutional encoder
reg r_b;
// Encoded data output from the convolutional encoder
// reg [1:0] r_c;
/**
* Propagated randomly generated number to determine if data
* bit should be corrupted - propagated value from the input
* to the communications channel
*/
reg [7:0] r_e;
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 2nd stage of the communication
* channel
*/
// Propagated values of the encoded data; also, input to XOR gate
reg [1:0] rr_c;
/**
* Further propagated randomly generated number to determine
* if data bit should be corrupted - propagated value from the
* input to the communications channel
*/
reg [7:0] r_e1;
/**
* Randomly generated error that determines the corruption of
* the data bits
*
* Random number will corrupt the encoded data bits based on
* the XOR operator - invert the bits of the encoded data if
* they are different from the random error bits
*
* Also, input to XOR gate to generated corrupted encoded bits
*/
wire [1:0] r_e2;
/**
* Corrupted encoded data bits - model corruption of data during
* transmission of the data in the communications channel
*/
wire [1:0] r_cx;
// Propagated original data input
reg r_b1;
/** ########################################################
#
# IMPORTANT!!!: MODIFY THE error_level HERE!!!
#
########################################################
***
*
* Error level that will be used to generate noise that will
* be used to corrupt encoded data bits
*
* Randomly generated error bits will be compared with this
* error level
*/
reg [7:0] error_level;
// ------------------------------------------------------------
// Inputs to the 3rd stage of the communication channel
// Further propagated values of the encoded data
reg [1:0] rr_c1;
// Propagated values of the corrupted encoded data
reg [1:0] r_cx1;
// Propagated original data input
reg r_b2;
// Reset signal for the flip-flops and registers
reg rset;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 9'd256;
// ============================================================
// Declare and instantiate modules for the communication channel
/**
* Instantiate an instance of Viterbi decoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "v_d"
*/
viterbi_decoder v_d (
// instance_name(signal name),
// Signal name can be the same as the instance name
d,r_cx1,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the convolutional encoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "enc"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,r_b,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the noise generator so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "ng"
*/
noise_generator ng (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_e1,r_e2,error_level);
// ------------------------------------------------------------
/**
* Instantiate an instance of the 2-bit 2-input XOR gate so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor22"
*/
xor2_2bit xor22 (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c,r_e2,r_cx);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_c"
*/
pipeline_buffer_2bit pipe_c (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c1,c,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_cx"
*/
pipeline_buffer_2bit pipe_cx (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_cx1,cx,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_b"
*/
pipeline_buffer pipe_b (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b2,b,clock,rset);
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clock = 0;
#5 clock = 1;
// Period = 10 clock cycles
end
// ============================================================
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clock)
begin
if(rset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=rr;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 2nd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c<=0;
r_e1<=0;
r_b1<=0;
end
else
begin
rr_c<=r_c;
r_e1<=r_e;
r_b1<=r_b;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 3rd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c1<=0;
r_cx1<=0;
r_b2<=0;
end
else
begin
rr_c1<=rr_c;
r_cx1<=r_cx;
r_b2<=r_b1;
end
end
// ------------------------------------------------------------
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
error_level=8'd5;
rset=1;
// @t=20,
#20
rset=0;
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("testfile.bit",r);
/// $readmemb("testfile.bit",rf);
/**
* IMPORTANT NOTE:
* Start to process inputs from the input file after
* 30 clock cycles
*/
for(count=0;count<size_of_input;count=count+1)
begin
#10
$display("Next");
e=$random;
rr=r[count];
if(rr_c != r_cx)
begin
$display($time,"rr_c NOT EQUAL to r_cx");
end
if(count==150)
begin
rset=1;
end
else if(count==151)
begin
rset=0;
end
end
// Problem with d and error_level
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
`timescale 1ns / 100ps
module QMFIR_uart_top(/*AUTOARG*/
// Outputs
uart_tx,
// Inputs
uart_rx, clk, arst_n
);
output uart_tx;
input uart_rx;
input clk;
input arst_n;
wire arst_n;
wire [15:0] MEMDAT;
wire core_clk;
wire uart_rst_n;
reg init_rst_n;
reg delay;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire reg_we; // From uart_ of QMFIR_uart_if.v
wire [13:0] uart_addr; // From uart_ of QMFIR_uart_if.v
wire [31:0] uart_dout; // From uart_ of QMFIR_uart_if.v
wire uart_mem_re; // From uart_ of QMFIR_uart_if.v
wire uart_mem_we; // From uart_ of QMFIR_uart_if.v
// End of automatics
wire [23:0] uart_mem_i;
reg [23:0] uart_reg_i; //combinatory
//iReg
wire [15:0] ESCR;
wire [15:0] WPTR;
wire [15:0] ICNT;
wire [15:0] FREQ;
wire [15:0] OCNT;
wire [15:0] FCNT;
wire [31:0] firin;
//bram out
wire [15:0] MEMDATR1;
wire [15:0] MEMDATI1;
wire [15:0] MEMDATR2;
wire [15:0] MEMDATI2;
wire [15:0] MEMDATR3;
wire [15:0] MEMDATI3;
wire [15:0] RealOut1;
wire [15:0] RealOut2;
wire [15:0] RealOut3;
wire [15:0] ImagOut1;
wire [15:0] ImagOut2;
wire [15:0] ImagOut3;
//bram in
wire [9:0] mem_addr1;
wire [9:0] mem_addr2;
wire [9:0] mem_addr3;
wire [11:0] bramin_addr;
// qmfir
reg START;
wire DataValid;
// CORE
assign arst = ~arst_n;
assign arst1 = ESCR[0];
assign uart_rst_n = arst_n & init_rst_n;
QMFIR_uart_if uart_(/*AUTOINST*/
// Outputs
.uart_dout (uart_dout[31:0]),
.uart_addr (uart_addr[13:0]),
.uart_mem_we (uart_mem_we),
.uart_mem_re (uart_mem_re),
.reg_we (reg_we),
.uart_tx (uart_tx),
// Inputs
.uart_mem_i (uart_mem_i[23:0]),
.uart_reg_i (uart_reg_i[23:0]),
.clk (core_clk),
.arst_n (uart_rst_n),
.uart_rx (uart_rx));
iReg ireg_ (//outputs
.ESCR(ESCR),
.WPTR(WPTR),
.ICNT(ICNT),
.FREQ(FREQ),
.OCNT(OCNT),
.FCNT(FCNT),
//inputs
.clk(core_clk),
.arst(arst),
.idata(uart_dout[15:0]),
.iaddr(uart_addr),
.iwe(reg_we),
.FIR_WE(DataValid),
.WFIFO_WE(uart_mem_we)
);
BRAM_larg bramin_(//outputs
.doutb(firin), //32 bit
//inputs
.clka(core_clk),
.clkb(core_clk),
.addra(bramin_addr[11:0]), //12 bit
.addrb(FCNT[11:0]), //12 bit
.dina(uart_dout), //32 bit
.wea(uart_mem_we));
QM_FIR QM_FIR(//outputs
.RealOut1 (RealOut1),
.RealOut2 (RealOut2),
.RealOut3 (RealOut3),
.ImagOut1 (ImagOut1),
.ImagOut2 (ImagOut2),
.ImagOut3 (ImagOut3),
.DataValid (DataValid),
//inputs
.CLK (core_clk),
.ARST (arst1),
.InputValid (START),
.dsp_in0 (firin[31:24]),
.dsp_in1 (firin[23:16]),
.dsp_in2 (firin[15:8]),
.dsp_in3 (firin[7:0]),
.newFreq (FREQ[14]),
.freq (FREQ[6:0]));
BRAM BRAM1_ (//outputs
.doutb({MEMDATI1[15:0],MEMDATR1[15:0]}),
//inputs
.clka(core_clk),
.clkb(core_clk),
.addra(WPTR[6:0]),
.addrb(mem_addr1[6:0]),
.dina({ImagOut1[15:0],RealOut1[15:0]}),
.wea(DataValid));
BRAM BRAM2_ (//outputs
.doutb({MEMDATI2[15:0],MEMDATR2[15:0]}),
//inputs
.clka(core_clk),
.clkb(core_clk),
.addra(WPTR[6:0]),
.addrb(mem_addr2[6:0]),
.dina({ImagOut2[15:0],RealOut2[15:0]}),
.wea(DataValid));
BRAM BRAM3_ (//outputs
.doutb({MEMDATI3[15:0],MEMDATR3[15:0]}),
//inputs
.clka(core_clk),
.clkb(core_clk),
.addra(WPTR[6:0]),
.addrb(mem_addr3[6:0]),
.dina({ImagOut3[15:0],RealOut3[15:0]}),
.wea(DataValid));
always @ (posedge core_clk or posedge arst)
if (arst != 1'b0)
START = 1'b0;
else begin
if (ESCR[3]) begin
init_rst_n <= 0; //assert initial UART reset
START = ESCR[3]; //start the filter
end
else begin
init_rst_n <= 1;
START = 1'b0;
end
end
// BRAMin interface
assign bramin_addr[11:0] = {(12){uart_mem_we}} & uart_addr[11:0];
//iReg interface
always @ (/*AS*/ESCR or FCNT or FREQ or ICNT or OCNT or WPTR or uart_addr)
case (uart_addr[2:0])
3'h1: uart_reg_i = {uart_addr[7:0], ESCR[15:0]};
3'h2: uart_reg_i = {uart_addr[7:0], WPTR[15:0]};
3'h3: uart_reg_i = {uart_addr[7:0], ICNT[15:0]};
3'h4: uart_reg_i = {uart_addr[7:0], FREQ[15:0]};
3'h5: uart_reg_i = {uart_addr[7:0], OCNT[15:0]};
3'h6: uart_reg_i = {uart_addr[7:0], FCNT[15:0]};
//default: uart_reg_i = {uart_addr[7:0],16'hDEAD};
endcase // case (uart_addr[2:0])
// BRAM out interface
//read address
assign mem_addr1[6:0] = ((uart_addr[13:11] == 3'h1) | (uart_addr[13:11] == 3'h2)) ? uart_addr[6:0] : 7'b111_1111;
assign mem_addr2[6:0] = ((uart_addr[13:11] == 3'h3) | (uart_addr[13:11] == 3'h4)) ? uart_addr[6:0] : 7'b111_1111;
assign mem_addr3[6:0] = ((uart_addr[13:11] == 3'h5) | (uart_addr[13:11] == 3'h6)) ? uart_addr[6:0] : 7'b111_1111;
//read data
assign MEMDAT[15:0] = (MEMDATR1[15:0] & {16{uart_addr[13:11] == 3'h1}}) |
(MEMDATI1[15:0] & {16{uart_addr[13:11] == 3'h2}}) |
(MEMDATR2[15:0] & {16{uart_addr[13:11] == 3'h3}}) |
(MEMDATI2[15:0] & {16{uart_addr[13:11] == 3'h4}}) |
(MEMDATR3[15:0] & {16{uart_addr[13:11] == 3'h5}}) |
(MEMDATI3[15:0] & {16{uart_addr[13:11] == 3'h6}});
assign uart_mem_i[23:0] = {1'b0,uart_addr[13:11],uart_addr[3:0], MEMDAT[15:0]};
// DCM_BASE: Base Digital Clock Manager Circuit, Virtex-5
//this DCM is used to divide the clock from 100MHz to 62.5MHz (for UART)
DCM_BASE #(
.CLKFX_DIVIDE(8), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(5), // Can be any integer from 2 to 32
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
.CLK_FEEDBACK("NONE") // Specify clock feedback of NONE or 1X
) DCM_BASE_inst (
.CLKFX(core_clk), // DCM CLK synthesis out (M/D)
.CLKIN(clk), // Clock input (from IBUFG, BUFG or DCM)
.RST(arst) // DCM asynchronous reset input
);
// End of DCM_BASE_inst instantiation
endmodule // QMFIR_uart_top
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBN_2_V
`define SKY130_FD_SC_LS__SDFBBN_2_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog wrapper for sdfbbn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfbbn_2 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfbbn_2 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBN_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__NAND2_FUNCTIONAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2_FUNCTIONAL_PP_V |
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 1G Ethernet MAC with TX and RX FIFOs
*/
module eth_mac_1g_fifo #
(
parameter AXIS_DATA_WIDTH = 8,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
input wire logic_clk,
input wire logic_rst,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* GMII interface
*/
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* Control
*/
input wire rx_clk_enable,
input wire tx_clk_enable,
input wire rx_mii_select,
input wire tx_mii_select,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire [7:0] tx_fifo_axis_tdata;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire tx_fifo_axis_tuser;
wire [7:0] rx_fifo_axis_tdata;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire rx_fifo_axis_tuser;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1 = 2'd0;
reg [1:0] rx_sync_reg_2 = 2'd0;
reg [1:0] rx_sync_reg_3 = 2'd0;
reg [1:0] rx_sync_reg_4 = 2'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
eth_mac_1g #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.rx_clk_enable(rx_clk_enable),
.tx_clk_enable(tx_clk_enable),
.rx_mii_select(rx_mii_select),
.tx_mii_select(tx_mii_select),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.ifg_delay(ifg_delay)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(8),
.M_KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(8),
.S_KEEP_ENABLE(0),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_1_V
`define SKY130_FD_SC_LP__CLKINV_1_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_1_V
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY frame sync
*/
module eth_phy_10g_rx_frame_sync #
(
parameter HDR_WIDTH = 2,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8
)
(
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire rx_block_lock
);
parameter BITSLIP_MAX_CYCLES = BITSLIP_HIGH_CYCLES > BITSLIP_LOW_CYCLES ? BITSLIP_HIGH_CYCLES : BITSLIP_LOW_CYCLES;
parameter BITSLIP_COUNT_WIDTH = $clog2(BITSLIP_MAX_CYCLES);
// bus width assertions
initial begin
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
reg [5:0] sh_count_reg = 6'd0, sh_count_next;
reg [3:0] sh_invalid_count_reg = 4'd0, sh_invalid_count_next;
reg [BITSLIP_COUNT_WIDTH-1:0] bitslip_count_reg = 0, bitslip_count_next;
reg serdes_rx_bitslip_reg = 1'b0, serdes_rx_bitslip_next;
reg rx_block_lock_reg = 1'b0, rx_block_lock_next;
assign serdes_rx_bitslip = serdes_rx_bitslip_reg;
assign rx_block_lock = rx_block_lock_reg;
always @* begin
sh_count_next = sh_count_reg;
sh_invalid_count_next = sh_invalid_count_reg;
bitslip_count_next = bitslip_count_reg;
serdes_rx_bitslip_next = serdes_rx_bitslip_reg;
rx_block_lock_next = rx_block_lock_reg;
if (bitslip_count_reg) begin
bitslip_count_next = bitslip_count_reg-1;
end else if (serdes_rx_bitslip_reg) begin
serdes_rx_bitslip_next = 1'b0;
bitslip_count_next = BITSLIP_LOW_CYCLES > 0 ? BITSLIP_LOW_CYCLES-1 : 0;
end else if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header
sh_count_next = sh_count_reg + 1;
if (&sh_count_reg) begin
// valid count overflow, reset
sh_count_next = 0;
sh_invalid_count_next = 0;
if (!sh_invalid_count_reg) begin
rx_block_lock_next = 1'b1;
end
end
end else begin
// invalid header
sh_count_next = sh_count_reg + 1;
sh_invalid_count_next = sh_invalid_count_reg + 1;
if (!rx_block_lock_reg || &sh_invalid_count_reg) begin
// invalid count overflow, lost block lock
sh_count_next = 0;
sh_invalid_count_next = 0;
rx_block_lock_next = 1'b0;
// slip one bit
serdes_rx_bitslip_next = 1'b1;
bitslip_count_next = BITSLIP_HIGH_CYCLES > 0 ? BITSLIP_HIGH_CYCLES-1 : 0;
end else if (&sh_count_reg) begin
// valid count overflow, reset
sh_count_next = 0;
sh_invalid_count_next = 0;
end
end
end
always @(posedge clk) begin
sh_count_reg <= sh_count_next;
sh_invalid_count_reg <= sh_invalid_count_next;
bitslip_count_reg <= bitslip_count_next;
serdes_rx_bitslip_reg <= serdes_rx_bitslip_next;
rx_block_lock_reg <= rx_block_lock_next;
if (rst) begin
sh_count_reg <= 6'd0;
sh_invalid_count_reg <= 4'd0;
bitslip_count_reg <= 0;
serdes_rx_bitslip_reg <= 1'b0;
rx_block_lock_reg <= 1'b0;
end
end
endmodule
`resetall
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_hd__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_hd__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DFXBP_BEHAVIORAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_df_p_no_pg/sky130_fd_sc_hs__u_df_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dfxbp (
VPWR,
VGND,
Q ,
Q_N ,
CLK ,
D
);
// Module ports
input VPWR;
input VGND;
output Q ;
output Q_N ;
input CLK ;
input D ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hs__u_df_p_no_pg u_df_p_no_pg0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXBP_BEHAVIORAL_PP_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Instruction decode ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Majority of instruction decoding is performed here. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_ctrl.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.13 2005/01/13 11:03:43 phoenix
// revert to the old l.sfxxi behavior
//
// Revision 1.12 2005/01/07 09:31:07 andreje
// sign/zero extension for l.sfxxi instructions corrected
//
// Revision 1.11 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.10 2004/05/09 19:49:04 lampret
// Added some l.cust5 custom instructions as example
//
// Revision 1.9 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.8.4.1 2004/02/11 01:40:11 lampret
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
//
// Revision 1.8 2003/04/24 00:16:07 lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.7 2002/09/07 05:42:02 lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.6 2002/03/29 15:16:54 lampret
// Some of the warnings fixed.
//
// Revision 1.5 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.4 2002/01/28 01:15:59 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.3 2002/01/18 14:21:43 lampret
// Fixed 'the NPC single-step fix'.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.14 2001/11/30 18:59:17 simons
// force_dslot_fetch does not work - allways zero.
//
// Revision 1.13 2001/11/20 18:46:15 simons
// Break point bug fixed
//
// Revision 1.12 2001/11/18 08:36:28 lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.11 2001/11/13 10:02:21 lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.10 2001/11/12 01:45:40 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_ctrl(
// Clock and reset
clk, rst,
// Internal i/f
id_freeze, ex_freeze, wb_freeze, flushpipe, if_insn, ex_insn, branch_op, branch_taken,
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op,
wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
cust5_op, cust5_limm,
multicycle, spr_addrimm, wbforw_valid, du_hwbkpt, sig_syscall, sig_trap,
force_dslot_fetch, no_more_dslot, ex_void, id_macrc_op, ex_macrc_op, rfe, except_illegal
);
//
// I/O
//
input clk;
input rst;
input id_freeze;
input ex_freeze;
input wb_freeze;
input flushpipe;
input [31:0] if_insn;
output [31:0] ex_insn;
output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
input branch_taken;
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
output rf_rda;
output rf_rdb;
output [`OR1200_ALUOP_WIDTH-1:0] alu_op;
output [`OR1200_MACOP_WIDTH-1:0] mac_op;
output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
output [31:0] wb_insn;
output [31:0] simm;
output [31:2] branch_addrofs;
output [31:0] lsu_addrofs;
output [`OR1200_SEL_WIDTH-1:0] sel_a;
output [`OR1200_SEL_WIDTH-1:0] sel_b;
output [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
output [`OR1200_COMPOP_WIDTH-1:0] comp_op;
output [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
output [4:0] cust5_op;
output [5:0] cust5_limm;
output [15:0] spr_addrimm;
input wbforw_valid;
input du_hwbkpt;
output sig_syscall;
output sig_trap;
output force_dslot_fetch;
output no_more_dslot;
output ex_void;
output id_macrc_op;
output ex_macrc_op;
output rfe;
output except_illegal;
//
// Internal wires and regs
//
reg [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op;
reg [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
reg [`OR1200_ALUOP_WIDTH-1:0] alu_op;
`ifdef OR1200_MAC_IMPLEMENTED
reg [`OR1200_MACOP_WIDTH-1:0] mac_op;
reg ex_macrc_op;
`else
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
wire ex_macrc_op;
`endif
reg [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
reg [31:0] id_insn;
reg [31:0] ex_insn;
reg [31:0] wb_insn;
reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
reg [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
reg [31:0] lsu_addrofs;
reg [`OR1200_SEL_WIDTH-1:0] sel_a;
reg [`OR1200_SEL_WIDTH-1:0] sel_b;
reg sel_imm;
reg [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
reg [`OR1200_COMPOP_WIDTH-1:0] comp_op;
reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
reg imm_signextend;
reg [15:0] spr_addrimm;
reg sig_syscall;
reg sig_trap;
reg except_illegal;
wire id_void;
//
// Register file read addresses
//
assign rf_addra = if_insn[20:16];
assign rf_addrb = if_insn[15:11];
assign rf_rda = if_insn[31];
assign rf_rdb = if_insn[30];
//
// Force fetch of delay slot instruction when jump/branch is preceeded by load/store
// instructions
//
// SIMON
// assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op));
assign force_dslot_fetch = 1'b0;
assign no_more_dslot = |branch_op & !id_void & branch_taken | (branch_op == `OR1200_BRANCHOP_RFE);
assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
//
// Sign/Zero extension of immediates
//
assign simm = (imm_signextend == 1'b1) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
//
// Sign extension of branch offset
//
assign branch_addrofs = {{4{ex_insn[25]}}, ex_insn[25:0]};
//
// l.macrc in ID stage
//
`ifdef OR1200_MAC_IMPLEMENTED
assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MOVHI) & id_insn[16];
`else
assign id_macrc_op = 1'b0;
`endif
//
// cust5_op, cust5_limm (L immediate)
//
assign cust5_op = ex_insn[4:0];
assign cust5_limm = ex_insn[10:5];
//
//
//
assign rfe = (pre_branch_op == `OR1200_BRANCHOP_RFE) | (branch_op == `OR1200_BRANCHOP_RFE);
//
// Generation of sel_a
//
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
sel_a = `OR1200_SEL_EX_FORW;
else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
sel_a = `OR1200_SEL_WB_FORW;
else
sel_a = `OR1200_SEL_RF;
//
// Generation of sel_b
//
always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
if (sel_imm)
sel_b = `OR1200_SEL_IMM;
else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
sel_b = `OR1200_SEL_EX_FORW;
else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
sel_b = `OR1200_SEL_WB_FORW;
else
sel_b = `OR1200_SEL_RF;
//
// l.macrc in EX stage
//
`ifdef OR1200_MAC_IMPLEMENTED
always @(posedge clk or posedge rst) begin
if (rst)
ex_macrc_op <= #1 1'b0;
else if (!ex_freeze & id_freeze | flushpipe)
ex_macrc_op <= #1 1'b0;
else if (!ex_freeze)
ex_macrc_op <= #1 id_macrc_op;
end
`else
assign ex_macrc_op = 1'b0;
`endif
//
// Decode of spr_addrimm
//
always @(posedge clk or posedge rst) begin
if (rst)
spr_addrimm <= #1 16'h0000;
else if (!ex_freeze & id_freeze | flushpipe)
spr_addrimm <= #1 16'h0000;
else if (!ex_freeze) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.mfspr
`OR1200_OR32_MFSPR:
spr_addrimm <= #1 id_insn[15:0];
// l.mtspr
default:
spr_addrimm <= #1 {id_insn[25:21], id_insn[10:0]};
endcase
end
end
//
// Decode of multicycle
//
always @(id_insn) begin
case (id_insn[31:26]) // synopsys parallel_case
`ifdef UNUSED
// l.lwz
`OR1200_OR32_LWZ:
multicycle = `OR1200_TWO_CYCLES;
// l.lbz
`OR1200_OR32_LBZ:
multicycle = `OR1200_TWO_CYCLES;
// l.lbs
`OR1200_OR32_LBS:
multicycle = `OR1200_TWO_CYCLES;
// l.lhz
`OR1200_OR32_LHZ:
multicycle = `OR1200_TWO_CYCLES;
// l.lhs
`OR1200_OR32_LHS:
multicycle = `OR1200_TWO_CYCLES;
// l.sw
`OR1200_OR32_SW:
multicycle = `OR1200_TWO_CYCLES;
// l.sb
`OR1200_OR32_SB:
multicycle = `OR1200_TWO_CYCLES;
// l.sh
`OR1200_OR32_SH:
multicycle = `OR1200_TWO_CYCLES;
`endif
// ALU instructions except the one with immediate
`OR1200_OR32_ALU:
multicycle = id_insn[`OR1200_ALUMCYC_POS];
// Single cycle instructions
default: begin
multicycle = `OR1200_ONE_CYCLE;
end
endcase
end
//
// Decode of imm_signextend
//
always @(id_insn) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.addi
`OR1200_OR32_ADDI:
imm_signextend = 1'b1;
// l.addic
`OR1200_OR32_ADDIC:
imm_signextend = 1'b1;
// l.xori
`OR1200_OR32_XORI:
imm_signextend = 1'b1;
// l.muli
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_OR32_MULI:
imm_signextend = 1'b1;
`endif
// l.maci
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACI:
imm_signextend = 1'b1;
`endif
// SFXX insns with immediate
`OR1200_OR32_SFXXI:
imm_signextend = 1'b1;
// Instructions with no or zero extended immediate
default: begin
imm_signextend = 1'b0;
end
endcase
end
//
// LSU addr offset
//
always @(lsu_op or ex_insn) begin
lsu_addrofs[10:0] = ex_insn[10:0];
case(lsu_op) // synopsys parallel_case
`OR1200_LSUOP_SW, `OR1200_LSUOP_SH, `OR1200_LSUOP_SB :
lsu_addrofs[31:11] = {{16{ex_insn[25]}}, ex_insn[25:21]};
default :
lsu_addrofs[31:11] = {{16{ex_insn[15]}}, ex_insn[15:11]};
endcase
end
//
// Register file write address
//
always @(posedge clk or posedge rst) begin
if (rst)
rf_addrw <= #1 5'd0;
else if (!ex_freeze & id_freeze)
rf_addrw <= #1 5'd00;
else if (!ex_freeze)
case (pre_branch_op) // synopsys parallel_case
`OR1200_BRANCHOP_JR, `OR1200_BRANCHOP_BAL:
rf_addrw <= #1 5'd09; // link register r9
default:
rf_addrw <= #1 id_insn[25:21];
endcase
end
//
// rf_addrw in wb stage (used in forwarding logic)
//
always @(posedge clk or posedge rst) begin
if (rst)
wb_rfaddrw <= #1 5'd0;
else if (!wb_freeze)
wb_rfaddrw <= #1 rf_addrw;
end
//
// Instruction latch in id_insn
//
always @(posedge clk or posedge rst) begin
if (rst)
id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
else if (flushpipe)
id_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // id_insn[16] must be 1
else if (!id_freeze) begin
id_insn <= #1 if_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: id_insn <= %h", $time, if_insn);
// synopsys translate_on
`endif
end
end
//
// Instruction latch in ex_insn
//
always @(posedge clk or posedge rst) begin
if (rst)
ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
else if (!ex_freeze & id_freeze | flushpipe)
ex_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // ex_insn[16] must be 1
else if (!ex_freeze) begin
ex_insn <= #1 id_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: ex_insn <= %h", $time, id_insn);
// synopsys translate_on
`endif
end
end
//
// Instruction latch in wb_insn
//
always @(posedge clk or posedge rst) begin
if (rst)
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
else if (flushpipe)
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h041_0000}; // wb_insn[16] must be 1
else if (!wb_freeze) begin
wb_insn <= #1 ex_insn;
end
end
//
// Decode of sel_imm
//
always @(posedge clk or posedge rst) begin
if (rst)
sel_imm <= #1 1'b0;
else if (!id_freeze) begin
case (if_insn[31:26]) // synopsys parallel_case
// j.jalr
`OR1200_OR32_JALR:
sel_imm <= #1 1'b0;
// l.jr
`OR1200_OR32_JR:
sel_imm <= #1 1'b0;
// l.rfe
`OR1200_OR32_RFE:
sel_imm <= #1 1'b0;
// l.mfspr
`OR1200_OR32_MFSPR:
sel_imm <= #1 1'b0;
// l.mtspr
`OR1200_OR32_MTSPR:
sel_imm <= #1 1'b0;
// l.sys, l.brk and all three sync insns
`OR1200_OR32_XSYNC:
sel_imm <= #1 1'b0;
// l.mac/l.msb
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACMSB:
sel_imm <= #1 1'b0;
`endif
// l.sw
`OR1200_OR32_SW:
sel_imm <= #1 1'b0;
// l.sb
`OR1200_OR32_SB:
sel_imm <= #1 1'b0;
// l.sh
`OR1200_OR32_SH:
sel_imm <= #1 1'b0;
// ALU instructions except the one with immediate
`OR1200_OR32_ALU:
sel_imm <= #1 1'b0;
// SFXX instructions
`OR1200_OR32_SFXX:
sel_imm <= #1 1'b0;
`ifdef OR1200_OR32_CUST5
// l.cust5 instructions
`OR1200_OR32_CUST5:
sel_imm <= #1 1'b0;
`endif
// l.nop
`OR1200_OR32_NOP:
sel_imm <= #1 1'b0;
// All instructions with immediates
default: begin
sel_imm <= #1 1'b1;
end
endcase
end
end
//
// Decode of except_illegal
//
always @(posedge clk or posedge rst) begin
if (rst)
except_illegal <= #1 1'b0;
else if (!ex_freeze & id_freeze | flushpipe)
except_illegal <= #1 1'b0;
else if (!ex_freeze) begin
case (id_insn[31:26]) // synopsys parallel_case
`OR1200_OR32_J,
`OR1200_OR32_JAL,
`OR1200_OR32_JALR,
`OR1200_OR32_JR,
`OR1200_OR32_BNF,
`OR1200_OR32_BF,
`OR1200_OR32_RFE,
`OR1200_OR32_MOVHI,
`OR1200_OR32_MFSPR,
`OR1200_OR32_XSYNC,
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACI,
`endif
`OR1200_OR32_LWZ,
`OR1200_OR32_LBZ,
`OR1200_OR32_LBS,
`OR1200_OR32_LHZ,
`OR1200_OR32_LHS,
`OR1200_OR32_ADDI,
`OR1200_OR32_ADDIC,
`OR1200_OR32_ANDI,
`OR1200_OR32_ORI,
`OR1200_OR32_XORI,
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_OR32_MULI,
`endif
`OR1200_OR32_SH_ROTI,
`OR1200_OR32_SFXXI,
`OR1200_OR32_MTSPR,
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACMSB,
`endif
`OR1200_OR32_SW,
`OR1200_OR32_SB,
`OR1200_OR32_SH,
`OR1200_OR32_ALU,
`OR1200_OR32_SFXX,
`ifdef OR1200_OR32_CUST5
`OR1200_OR32_CUST5,
`endif
`OR1200_OR32_NOP:
except_illegal <= #1 1'b0;
// Illegal and OR1200 unsupported instructions
default:
except_illegal <= #1 1'b1;
endcase
end
end
//
// Decode of alu_op
//
always @(posedge clk or posedge rst) begin
if (rst)
alu_op <= #1 `OR1200_ALUOP_NOP;
else if (!ex_freeze & id_freeze | flushpipe)
alu_op <= #1 `OR1200_ALUOP_NOP;
else if (!ex_freeze) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.j
`OR1200_OR32_J:
alu_op <= #1 `OR1200_ALUOP_IMM;
// j.jal
`OR1200_OR32_JAL:
alu_op <= #1 `OR1200_ALUOP_IMM;
// l.bnf
`OR1200_OR32_BNF:
alu_op <= #1 `OR1200_ALUOP_NOP;
// l.bf
`OR1200_OR32_BF:
alu_op <= #1 `OR1200_ALUOP_NOP;
// l.movhi
`OR1200_OR32_MOVHI:
alu_op <= #1 `OR1200_ALUOP_MOVHI;
// l.mfspr
`OR1200_OR32_MFSPR:
alu_op <= #1 `OR1200_ALUOP_MFSR;
// l.mtspr
`OR1200_OR32_MTSPR:
alu_op <= #1 `OR1200_ALUOP_MTSR;
// l.addi
`OR1200_OR32_ADDI:
alu_op <= #1 `OR1200_ALUOP_ADD;
// l.addic
`OR1200_OR32_ADDIC:
alu_op <= #1 `OR1200_ALUOP_ADDC;
// l.andi
`OR1200_OR32_ANDI:
alu_op <= #1 `OR1200_ALUOP_AND;
// l.ori
`OR1200_OR32_ORI:
alu_op <= #1 `OR1200_ALUOP_OR;
// l.xori
`OR1200_OR32_XORI:
alu_op <= #1 `OR1200_ALUOP_XOR;
// l.muli
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_OR32_MULI:
alu_op <= #1 `OR1200_ALUOP_MUL;
`endif
// Shift and rotate insns with immediate
`OR1200_OR32_SH_ROTI:
alu_op <= #1 `OR1200_ALUOP_SHROT;
// SFXX insns with immediate
`OR1200_OR32_SFXXI:
alu_op <= #1 `OR1200_ALUOP_COMP;
// ALU instructions except the one with immediate
`OR1200_OR32_ALU:
alu_op <= #1 id_insn[3:0];
// SFXX instructions
`OR1200_OR32_SFXX:
alu_op <= #1 `OR1200_ALUOP_COMP;
`ifdef OR1200_OR32_CUST5
// l.cust5 instructions
`OR1200_OR32_CUST5:
alu_op <= #1 `OR1200_ALUOP_CUST5;
`endif
// Default
default: begin
alu_op <= #1 `OR1200_ALUOP_NOP;
end
endcase
end
end
//
// Decode of mac_op
//
`ifdef OR1200_MAC_IMPLEMENTED
always @(posedge clk or posedge rst) begin
if (rst)
mac_op <= #1 `OR1200_MACOP_NOP;
else if (!ex_freeze & id_freeze | flushpipe)
mac_op <= #1 `OR1200_MACOP_NOP;
else if (!ex_freeze)
case (id_insn[31:26]) // synopsys parallel_case
// l.maci
`OR1200_OR32_MACI:
mac_op <= #1 `OR1200_MACOP_MAC;
// l.nop
`OR1200_OR32_MACMSB:
mac_op <= #1 id_insn[1:0];
// Illegal and OR1200 unsupported instructions
default: begin
mac_op <= #1 `OR1200_MACOP_NOP;
end
endcase
else
mac_op <= #1 `OR1200_MACOP_NOP;
end
`else
assign mac_op = `OR1200_MACOP_NOP;
`endif
//
// Decode of shrot_op
//
always @(posedge clk or posedge rst) begin
if (rst)
shrot_op <= #1 `OR1200_SHROTOP_NOP;
else if (!ex_freeze & id_freeze | flushpipe)
shrot_op <= #1 `OR1200_SHROTOP_NOP;
else if (!ex_freeze) begin
shrot_op <= #1 id_insn[`OR1200_SHROTOP_POS];
end
end
//
// Decode of rfwb_op
//
always @(posedge clk or posedge rst) begin
if (rst)
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
else if (!ex_freeze & id_freeze | flushpipe)
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
else if (!ex_freeze) begin
case (id_insn[31:26]) // synopsys parallel_case
// j.jal
`OR1200_OR32_JAL:
rfwb_op <= #1 `OR1200_RFWBOP_LR;
// j.jalr
`OR1200_OR32_JALR:
rfwb_op <= #1 `OR1200_RFWBOP_LR;
// l.movhi
`OR1200_OR32_MOVHI:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
// l.mfspr
`OR1200_OR32_MFSPR:
rfwb_op <= #1 `OR1200_RFWBOP_SPRS;
// l.lwz
`OR1200_OR32_LWZ:
rfwb_op <= #1 `OR1200_RFWBOP_LSU;
// l.lbz
`OR1200_OR32_LBZ:
rfwb_op <= #1 `OR1200_RFWBOP_LSU;
// l.lbs
`OR1200_OR32_LBS:
rfwb_op <= #1 `OR1200_RFWBOP_LSU;
// l.lhz
`OR1200_OR32_LHZ:
rfwb_op <= #1 `OR1200_RFWBOP_LSU;
// l.lhs
`OR1200_OR32_LHS:
rfwb_op <= #1 `OR1200_RFWBOP_LSU;
// l.addi
`OR1200_OR32_ADDI:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
// l.addic
`OR1200_OR32_ADDIC:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
// l.andi
`OR1200_OR32_ANDI:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
// l.ori
`OR1200_OR32_ORI:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
// l.xori
`OR1200_OR32_XORI:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
// l.muli
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_OR32_MULI:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
`endif
// Shift and rotate insns with immediate
`OR1200_OR32_SH_ROTI:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
// ALU instructions except the one with immediate
`OR1200_OR32_ALU:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
`ifdef OR1200_OR32_CUST5
// l.cust5 instructions
`OR1200_OR32_CUST5:
rfwb_op <= #1 `OR1200_RFWBOP_ALU;
`endif
// Instructions w/o register-file write-back
default: begin
rfwb_op <= #1 `OR1200_RFWBOP_NOP;
end
endcase
end
end
//
// Decode of pre_branch_op
//
always @(posedge clk or posedge rst) begin
if (rst)
pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
else if (flushpipe)
pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
else if (!id_freeze) begin
case (if_insn[31:26]) // synopsys parallel_case
// l.j
`OR1200_OR32_J:
pre_branch_op <= #1 `OR1200_BRANCHOP_BAL;
// j.jal
`OR1200_OR32_JAL:
pre_branch_op <= #1 `OR1200_BRANCHOP_BAL;
// j.jalr
`OR1200_OR32_JALR:
pre_branch_op <= #1 `OR1200_BRANCHOP_JR;
// l.jr
`OR1200_OR32_JR:
pre_branch_op <= #1 `OR1200_BRANCHOP_JR;
// l.bnf
`OR1200_OR32_BNF:
pre_branch_op <= #1 `OR1200_BRANCHOP_BNF;
// l.bf
`OR1200_OR32_BF:
pre_branch_op <= #1 `OR1200_BRANCHOP_BF;
// l.rfe
`OR1200_OR32_RFE:
pre_branch_op <= #1 `OR1200_BRANCHOP_RFE;
// Non branch instructions
default: begin
pre_branch_op <= #1 `OR1200_BRANCHOP_NOP;
end
endcase
end
end
//
// Generation of branch_op
//
always @(posedge clk or posedge rst)
if (rst)
branch_op <= #1 `OR1200_BRANCHOP_NOP;
else if (!ex_freeze & id_freeze | flushpipe)
branch_op <= #1 `OR1200_BRANCHOP_NOP;
else if (!ex_freeze)
branch_op <= #1 pre_branch_op;
//
// Decode of lsu_op
//
always @(posedge clk or posedge rst) begin
if (rst)
lsu_op <= #1 `OR1200_LSUOP_NOP;
else if (!ex_freeze & id_freeze | flushpipe)
lsu_op <= #1 `OR1200_LSUOP_NOP;
else if (!ex_freeze) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.lwz
`OR1200_OR32_LWZ:
lsu_op <= #1 `OR1200_LSUOP_LWZ;
// l.lbz
`OR1200_OR32_LBZ:
lsu_op <= #1 `OR1200_LSUOP_LBZ;
// l.lbs
`OR1200_OR32_LBS:
lsu_op <= #1 `OR1200_LSUOP_LBS;
// l.lhz
`OR1200_OR32_LHZ:
lsu_op <= #1 `OR1200_LSUOP_LHZ;
// l.lhs
`OR1200_OR32_LHS:
lsu_op <= #1 `OR1200_LSUOP_LHS;
// l.sw
`OR1200_OR32_SW:
lsu_op <= #1 `OR1200_LSUOP_SW;
// l.sb
`OR1200_OR32_SB:
lsu_op <= #1 `OR1200_LSUOP_SB;
// l.sh
`OR1200_OR32_SH:
lsu_op <= #1 `OR1200_LSUOP_SH;
// Non load/store instructions
default: begin
lsu_op <= #1 `OR1200_LSUOP_NOP;
end
endcase
end
end
//
// Decode of comp_op
//
always @(posedge clk or posedge rst) begin
if (rst) begin
comp_op <= #1 4'd0;
end else if (!ex_freeze & id_freeze | flushpipe)
comp_op <= #1 4'd0;
else if (!ex_freeze)
comp_op <= #1 id_insn[24:21];
end
//
// Decode of l.sys
//
always @(posedge clk or posedge rst) begin
if (rst)
sig_syscall <= #1 1'b0;
else if (!ex_freeze & id_freeze | flushpipe)
sig_syscall <= #1 1'b0;
else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000})
$display("Generating sig_syscall");
// synopsys translate_on
`endif
sig_syscall <= #1 (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000});
end
end
//
// Decode of l.trap
//
always @(posedge clk or posedge rst) begin
if (rst)
sig_trap <= #1 1'b0;
else if (!ex_freeze & id_freeze | flushpipe)
sig_trap <= #1 1'b0;
else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
$display("Generating sig_trap");
// synopsys translate_on
`endif
sig_trap <= #1 (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
| du_hwbkpt;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_qpll_reset.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_qpll_reset.v
// Description : QPLL Reset Module for 7 Series Transceiver
// Version : 11.4
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- QPLL Reset Module --------------------------------------------------
module pcie3_7x_0_qpll_reset #
(
//---------- Global ------------------------------------
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter BYPASS_COARSE_OVRD = 1 // Bypass coarse frequency override
)
(
//---------- Input -------------------------------------
input QRST_CLK,
input QRST_RST_N,
input QRST_MMCM_LOCK,
input [PCIE_LANE-1:0] QRST_CPLLLOCK,
input [(PCIE_LANE-1)>>2:0]QRST_DRP_DONE,
input [(PCIE_LANE-1)>>2:0]QRST_QPLLLOCK,
input [ 1:0] QRST_RATE,
input [PCIE_LANE-1:0] QRST_QPLLRESET_IN,
input [PCIE_LANE-1:0] QRST_QPLLPD_IN,
//---------- Output ------------------------------------
output QRST_OVRD,
output QRST_DRP_START,
output QRST_QPLLRESET_OUT,
output QRST_QPLLPD_OUT,
output QRST_IDLE,
output [11:0] QRST_FSM
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [(PCIE_LANE-1)>>2:0]qplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllreset_in_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] qpllpd_in_reg2;
//---------- Output Register --------------------------
reg ovrd = 1'd0;
reg qpllreset = 1'd1;
reg qpllpd = 1'd0;
reg [11:0] fsm = 12'd2;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 12'b000000000001;
localparam FSM_WAIT_LOCK = 12'b000000000010;
localparam FSM_MMCM_LOCK = 12'b000000000100;
localparam FSM_DRP_START_NOM = 12'b000000001000;
localparam FSM_DRP_DONE_NOM = 12'b000000010000;
localparam FSM_QPLLLOCK = 12'b000000100000;
localparam FSM_DRP_START_OPT = 12'b000001000000;
localparam FSM_DRP_DONE_OPT = 12'b000010000000;
localparam FSM_QPLL_RESET = 12'b000100000000;
localparam FSM_QPLLLOCK2 = 12'b001000000000;
localparam FSM_QPLL_PDRESET = 12'b010000000000;
localparam FSM_QPLL_PD = 12'b100000000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge QRST_CLK)
begin
if (!QRST_RST_N)
begin
//---------- 1st Stage FF --------------------------
mmcm_lock_reg1 <= 1'd0;
cplllock_reg1 <= {PCIE_LANE{1'd1}};
drp_done_reg1 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
qplllock_reg1 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
rate_reg1 <= 2'd0;
qpllreset_in_reg1 <= {PCIE_LANE{1'd1}};
qpllpd_in_reg1 <= {PCIE_LANE{1'd0}};
//---------- 2nd Stage FF --------------------------
mmcm_lock_reg2 <= 1'd0;
cplllock_reg2 <= {PCIE_LANE{1'd1}};
drp_done_reg2 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
qplllock_reg2 <= {(((PCIE_LANE-1)>>2)+1){1'd0}};
rate_reg2 <= 2'd0;
qpllreset_in_reg2 <= {PCIE_LANE{1'd1}};
qpllpd_in_reg2 <= {PCIE_LANE{1'd0}};
end
else
begin
//---------- 1st Stage FF --------------------------
mmcm_lock_reg1 <= QRST_MMCM_LOCK;
cplllock_reg1 <= QRST_CPLLLOCK;
drp_done_reg1 <= QRST_DRP_DONE;
qplllock_reg1 <= QRST_QPLLLOCK;
rate_reg1 <= QRST_RATE;
qpllreset_in_reg1 <= QRST_QPLLRESET_IN;
qpllpd_in_reg1 <= QRST_QPLLPD_IN;
//---------- 2nd Stage FF --------------------------
mmcm_lock_reg2 <= mmcm_lock_reg1;
cplllock_reg2 <= cplllock_reg1;
drp_done_reg2 <= drp_done_reg1;
qplllock_reg2 <= qplllock_reg1;
rate_reg2 <= rate_reg1;
qpllreset_in_reg2 <= qpllreset_in_reg1;
qpllpd_in_reg2 <= qpllpd_in_reg1;
end
end
//---------- QPLL Reset FSM ----------------------------------------------------
always @ (posedge QRST_CLK)
begin
if (!QRST_RST_N)
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (!QRST_RST_N)
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
ovrd <= ovrd;
qpllreset <= &qpllreset_in_reg2;
qpllpd <= &qpllpd_in_reg2;
end
end
//---------- Wait for CPLL and QPLL to Lose Lock ---
FSM_WAIT_LOCK :
begin
fsm <= ((&(~cplllock_reg2)) && (&(~qplllock_reg2)) ? FSM_MMCM_LOCK : FSM_WAIT_LOCK);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for MMCM and CPLL Lock -----------
FSM_MMCM_LOCK :
begin
fsm <= ((mmcm_lock_reg2 && (&cplllock_reg2)) ? FSM_DRP_START_NOM : FSM_MMCM_LOCK);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Start QPLL DRP for Normal QPLL Lock Mode
FSM_DRP_START_NOM:
begin
fsm <= (&(~drp_done_reg2) ? FSM_DRP_DONE_NOM : FSM_DRP_START_NOM);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL DRP Done ----------------
FSM_DRP_DONE_NOM :
begin
fsm <= (&drp_done_reg2 ? FSM_QPLLLOCK : FSM_DRP_DONE_NOM);
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL Lock --------------------
FSM_QPLLLOCK :
begin
fsm <= (&qplllock_reg2 ? ((BYPASS_COARSE_OVRD == 1) ? FSM_QPLL_PDRESET : FSM_DRP_START_OPT) : FSM_QPLLLOCK);
ovrd <= ovrd;
qpllreset <= 1'd0;
qpllpd <= qpllpd;
end
//---------- Start QPLL DRP for Optimized QPLL Lock Mode
FSM_DRP_START_OPT:
begin
fsm <= (&(~drp_done_reg2) ? FSM_DRP_DONE_OPT : FSM_DRP_START_OPT);
ovrd <= 1'd1;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
//---------- Wait for QPLL DRP Done ----------------
FSM_DRP_DONE_OPT :
begin
if (&drp_done_reg2)
begin
fsm <= ((PCIE_PLL_SEL == "QPLL") ? FSM_QPLL_RESET : FSM_QPLL_PDRESET);
ovrd <= ovrd;
qpllreset <= (PCIE_PLL_SEL == "QPLL");
qpllpd <= qpllpd;
end
else
begin
fsm <= FSM_DRP_DONE_OPT;
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= qpllpd;
end
end
//---------- Reset QPLL ----------------------------
FSM_QPLL_RESET :
begin
fsm <= (&(~qplllock_reg2) ? FSM_QPLLLOCK2 : FSM_QPLL_RESET);
ovrd <= ovrd;
qpllreset <= 1'd1;
qpllpd <= 1'd0;
end
//---------- Wait for QPLL Lock --------------------
FSM_QPLLLOCK2 :
begin
fsm <= (&qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK2);
ovrd <= ovrd;
qpllreset <= 1'd0;
qpllpd <= 1'd0;
end
//---------- Hold QPLL in Reset --------------------
FSM_QPLL_PDRESET :
begin
fsm <= FSM_QPLL_PD;
ovrd <= ovrd;
qpllreset <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0;
qpllpd <= qpllpd;
end
//---------- Power-down QPLL -----------------------
FSM_QPLL_PD :
begin
fsm <= FSM_IDLE;
ovrd <= ovrd;
qpllreset <= qpllreset;
qpllpd <= (PCIE_PLL_SEL == "CPLL") ? (rate_reg2 != 2'd2) : 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_WAIT_LOCK;
ovrd <= 1'd0;
qpllreset <= 1'd0;
qpllpd <= 1'd0;
end
endcase
end
end
//---------- QPLL Lock Output --------------------------------------------------
assign QRST_OVRD = ovrd;
assign QRST_DRP_START = (fsm == FSM_DRP_START_NOM) || (fsm == FSM_DRP_START_OPT);
assign QRST_QPLLRESET_OUT = qpllreset;
assign QRST_QPLLPD_OUT = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);
assign QRST_IDLE = (fsm == FSM_IDLE);
assign QRST_FSM = fsm;
endmodule
|
`timescale 1ns/1ps
//Reads from accumulate buffer and writes directly to indexed location in DRAM
module data_loader #(
parameter DRAM_BASE_ADDR=31'h40000000,
parameter ADDRESS_WIDTH=31,
parameter DATA_WIDTH=32,
parameter BLOCK_SIZE=64
) (
clk,
reset,
//Accumulator port for external writes
accumulate_fifo_read_slave_readdata,
accumulate_fifo_read_slave_waitrequest,
accumulate_fifo_read_slave_read,
//Accumulator for internal writes
accumulator_local_readdata,
accumulator_local_read,
accumulator_local_waitrequest,
//Write interface to write into DDR memory
control_fixed_location,
control_write_base,
control_write_length,
control_go,
control_done,
//user logic
user_write_buffer,
user_buffer_input_data,
user_buffer_full
);
localparam NUM_STATES=6;
localparam STATE_IDLE=0;
localparam STATE_WAIT_READ=1;
localparam STATE_READ_KEY_VAL=2;
localparam STATE_COMPUTE_ADDRESS=3;
localparam STATE_WRITE_DRAM=4;
localparam STATE_WAIT_DONE=5;
////////////Ports///////////////////
input clk;
input reset;
//Read interface to read from accumulator FIFO
input [63: 0] accumulate_fifo_read_slave_readdata;
input accumulate_fifo_read_slave_waitrequest;
output reg accumulate_fifo_read_slave_read;
//Accumulator for local writes
//Signals for local accumulation
input [63:0] accumulator_local_readdata;
input accumulator_local_waitrequest;
output reg accumulator_local_read;
// control inputs and outputs
output wire control_fixed_location;
output reg [ADDRESS_WIDTH-1:0] control_write_base;
output reg [ADDRESS_WIDTH-1:0] control_write_length;
output reg control_go;
input wire control_done;
// user logic inputs and outputs
output reg user_write_buffer;
output reg [DATA_WIDTH-1:0] user_buffer_input_data;
input wire user_buffer_full;
///////////Registers/////////////////////
reg avalonmm_read_slave_read_next;
reg [ADDRESS_WIDTH-1:0] control_write_base_next;
reg [ADDRESS_WIDTH-1:0] control_write_length_next;
reg control_go_next;
reg user_write_buffer_next;
reg [DATA_WIDTH-1:0] user_buffer_input_data_next;
reg [NUM_STATES-1:0] state, state_next;
reg [DATA_WIDTH-1:0] key, val, key_next, val_next;
reg accumulate_fifo_read_slave_read_next;
reg accum_type, accum_type_next;
reg accumulator_local_read_next;
localparam LOCAL=0; //local update
localparam EXT=1; //external update
assign control_fixed_location=1'b0;
always@(*)
begin
accumulate_fifo_read_slave_read_next = 1'b0;
key_next = key;
val_next = val;
control_write_length_next = control_write_length;
control_write_base_next = control_write_base;
control_go_next = 1'b0;
user_buffer_input_data_next = user_buffer_input_data;
user_write_buffer_next = 1'b0;
state_next = state;
accum_type_next = accum_type;
accumulator_local_read_next = 1'b0;
case(state)
STATE_IDLE: begin
if(!accumulate_fifo_read_slave_waitrequest) begin //if fifo is not empty, start reading first key
state_next = STATE_WAIT_READ;
accumulate_fifo_read_slave_read_next = 1'b1;
accum_type_next = EXT;
end
else if(!accumulator_local_waitrequest) begin
state_next = STATE_WAIT_READ;
accumulator_local_read_next = 1'b1;
accum_type_next = LOCAL;
end
else begin
state_next = STATE_IDLE;
end
end
STATE_WAIT_READ: begin
//Issue a sucessive read to get value (The FIFO must have (key,value) pairs
accumulate_fifo_read_slave_read_next = 1'b0;
accumulator_local_read_next = 1'b0;
state_next = STATE_READ_KEY_VAL;
end
STATE_READ_KEY_VAL: begin
if(accum_type==EXT) begin
key_next = accumulate_fifo_read_slave_readdata[63:32];
val_next = accumulate_fifo_read_slave_readdata[31:0];
end
else begin
key_next = accumulator_local_readdata[63:32];
val_next = accumulator_local_readdata[31:0];
end
state_next = STATE_COMPUTE_ADDRESS;
end
STATE_COMPUTE_ADDRESS: begin
control_write_base_next = (DRAM_BASE_ADDR+(key<<BLOCK_SIZE)); //convert key to an addressable location in DDDR2 DRAM [loc=key*64]
control_write_length_next = 4; //write a 32 bit key
control_go_next = 1'b1;
state_next = STATE_WRITE_DRAM;
end
STATE_WRITE_DRAM: begin
if(!user_buffer_full) begin
user_buffer_input_data_next = val;
user_write_buffer_next = 1'b1;
state_next = STATE_WAIT_DONE;
end
end
STATE_WAIT_DONE: begin
if(control_done)
state_next = STATE_IDLE;
end
endcase
end
always@(posedge clk)
begin
if(reset) begin
state <= STATE_IDLE;
accumulate_fifo_read_slave_read <= 1'b0;
key <= 0;
val <= 0;
control_write_length <= 0;
control_write_base <= 0;
control_go <= 0;
user_buffer_input_data <= 0;
user_write_buffer <= 1'b0;
accum_type <= 0;
accumulator_local_read <= 0;
end
else begin
state <= state_next;
accumulate_fifo_read_slave_read <= accumulate_fifo_read_slave_read_next;
key <= key_next;
val <= val_next;
control_write_length <= control_write_length_next;
control_write_base <= control_write_base_next;
control_go <= control_go_next;
user_buffer_input_data <= user_buffer_input_data_next;
user_write_buffer <= user_write_buffer_next;
accum_type <= accum_type_next;
accumulator_local_read <= accumulator_local_read_next;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4_TB_V
`define SKY130_FD_SC_HD__NAND4_TB_V
/**
* nand4: 4-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hd__nand4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_BLACKBOX_V
`define SKY130_FD_SC_LP__A41O_BLACKBOX_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a41o (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_BLACKBOX_V
|
// system.v
// Generated using ACDS version 14.0 200 at 2015.04.26.20:39:34
`timescale 1 ps / 1 ps
module system (
input wire clk_50_clk, // clk_50.clk
input wire reset_50_reset_n, // reset_50.reset_n
output wire kernel_clk_clk, // kernel_clk.clk
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
output wire peripheral_hps_io_emac1_inst_TX_CLK, // peripheral.hps_io_emac1_inst_TX_CLK
output wire peripheral_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire peripheral_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire peripheral_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire peripheral_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire peripheral_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire peripheral_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire peripheral_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire peripheral_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire peripheral_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire peripheral_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire peripheral_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire peripheral_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire peripheral_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire peripheral_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire peripheral_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire peripheral_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire peripheral_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire peripheral_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire peripheral_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
input wire peripheral_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire peripheral_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire peripheral_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire peripheral_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire peripheral_hps_io_gpio_inst_GPIO53 // .hps_io_gpio_inst_GPIO53
);
wire acl_iface_kernel_clk_clk; // acl_iface:kernel_clk_clk -> [Sobel_system:clock, avs_sobel_cra_cra_ring:clk, cra_root:clk, irq_mapper:clk, mm_interconnect_0:acl_iface_kernel_clk_clk, mm_interconnect_1:acl_iface_kernel_clk_clk]
wire acl_iface_kernel_clk2x_clk; // acl_iface:kernel_clk2x_clk -> Sobel_system:clock2x
wire acl_iface_kernel_reset_reset; // acl_iface:kernel_reset_reset_n -> [Sobel_system:resetn, avs_sobel_cra_cra_ring:rst_n, cra_root:rst_n, irq_mapper:reset, mm_interconnect_0:Sobel_system_clock_reset_reset_reset_bridge_in_reset_reset, mm_interconnect_1:cra_root_reset_reset_bridge_in_reset_reset]
wire avs_sobel_cra_cra_ring_ring_in_waitrequest; // avs_sobel_cra_cra_ring:ri_waitrequest -> cra_root:ro_waitrequest
wire [7:0] cra_root_ring_out_byteena; // cra_root:ro_byteena -> avs_sobel_cra_cra_ring:ri_byteena
wire [63:0] cra_root_ring_out_data; // cra_root:ro_data -> avs_sobel_cra_cra_ring:ri_data
wire cra_root_ring_out_write; // cra_root:ro_write -> avs_sobel_cra_cra_ring:ri_write
wire cra_root_ring_out_read; // cra_root:ro_read -> avs_sobel_cra_cra_ring:ri_read
wire [3:0] cra_root_ring_out_addr; // cra_root:ro_addr -> avs_sobel_cra_cra_ring:ri_addr
wire cra_root_ring_out_datavalid; // cra_root:ro_datavalid -> avs_sobel_cra_cra_ring:ri_datavalid
wire avs_sobel_cra_cra_ring_cra_master_waitrequest; // Sobel_system:avs_sobel_cra_waitrequest -> avs_sobel_cra_cra_ring:avm_waitrequest
wire [63:0] avs_sobel_cra_cra_ring_cra_master_writedata; // avs_sobel_cra_cra_ring:avm_writedata -> Sobel_system:avs_sobel_cra_writedata
wire [3:0] avs_sobel_cra_cra_ring_cra_master_address; // avs_sobel_cra_cra_ring:avm_addr -> Sobel_system:avs_sobel_cra_address
wire avs_sobel_cra_cra_ring_cra_master_write; // avs_sobel_cra_cra_ring:avm_write -> Sobel_system:avs_sobel_cra_write
wire avs_sobel_cra_cra_ring_cra_master_read; // avs_sobel_cra_cra_ring:avm_read -> Sobel_system:avs_sobel_cra_read
wire [63:0] avs_sobel_cra_cra_ring_cra_master_readdata; // Sobel_system:avs_sobel_cra_readdata -> avs_sobel_cra_cra_ring:avm_readdata
wire avs_sobel_cra_cra_ring_cra_master_readdatavalid; // Sobel_system:avs_sobel_cra_readdatavalid -> avs_sobel_cra_cra_ring:avm_readdatavalid
wire [7:0] avs_sobel_cra_cra_ring_cra_master_byteenable; // avs_sobel_cra_cra_ring:avm_byteena -> Sobel_system:avs_sobel_cra_byteenable
wire cra_root_ring_in_waitrequest; // cra_root:ri_waitrequest -> avs_sobel_cra_cra_ring:ro_waitrequest
wire [7:0] avs_sobel_cra_cra_ring_ring_out_byteena; // avs_sobel_cra_cra_ring:ro_byteena -> cra_root:ri_byteena
wire [63:0] avs_sobel_cra_cra_ring_ring_out_data; // avs_sobel_cra_cra_ring:ro_data -> cra_root:ri_data
wire avs_sobel_cra_cra_ring_ring_out_write; // avs_sobel_cra_cra_ring:ro_write -> cra_root:ri_write
wire avs_sobel_cra_cra_ring_ring_out_read; // avs_sobel_cra_cra_ring:ro_read -> cra_root:ri_read
wire [3:0] avs_sobel_cra_cra_ring_ring_out_addr; // avs_sobel_cra_cra_ring:ro_addr -> cra_root:ri_addr
wire avs_sobel_cra_cra_ring_ring_out_datavalid; // avs_sobel_cra_cra_ring:ro_datavalid -> cra_root:ri_datavalid
wire sobel_system_avm_memgmem0_port_0_0_rw_waitrequest; // mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_waitrequest -> Sobel_system:avm_memgmem0_port_0_0_rw_waitrequest
wire [4:0] sobel_system_avm_memgmem0_port_0_0_rw_burstcount; // Sobel_system:avm_memgmem0_port_0_0_rw_burstcount -> mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_burstcount
wire [255:0] sobel_system_avm_memgmem0_port_0_0_rw_writedata; // Sobel_system:avm_memgmem0_port_0_0_rw_writedata -> mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_writedata
wire [29:0] sobel_system_avm_memgmem0_port_0_0_rw_address; // Sobel_system:avm_memgmem0_port_0_0_rw_address -> mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_address
wire sobel_system_avm_memgmem0_port_0_0_rw_write; // Sobel_system:avm_memgmem0_port_0_0_rw_write -> mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_write
wire sobel_system_avm_memgmem0_port_0_0_rw_read; // Sobel_system:avm_memgmem0_port_0_0_rw_read -> mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_read
wire [255:0] sobel_system_avm_memgmem0_port_0_0_rw_readdata; // mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_readdata -> Sobel_system:avm_memgmem0_port_0_0_rw_readdata
wire sobel_system_avm_memgmem0_port_0_0_rw_readdatavalid; // mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_readdatavalid -> Sobel_system:avm_memgmem0_port_0_0_rw_readdatavalid
wire [31:0] sobel_system_avm_memgmem0_port_0_0_rw_byteenable; // Sobel_system:avm_memgmem0_port_0_0_rw_byteenable -> mm_interconnect_0:Sobel_system_avm_memgmem0_port_0_0_rw_byteenable
wire mm_interconnect_0_acl_iface_kernel_mem0_waitrequest; // acl_iface:kernel_mem0_waitrequest -> mm_interconnect_0:acl_iface_kernel_mem0_waitrequest
wire [4:0] mm_interconnect_0_acl_iface_kernel_mem0_burstcount; // mm_interconnect_0:acl_iface_kernel_mem0_burstcount -> acl_iface:kernel_mem0_burstcount
wire [255:0] mm_interconnect_0_acl_iface_kernel_mem0_writedata; // mm_interconnect_0:acl_iface_kernel_mem0_writedata -> acl_iface:kernel_mem0_writedata
wire [29:0] mm_interconnect_0_acl_iface_kernel_mem0_address; // mm_interconnect_0:acl_iface_kernel_mem0_address -> acl_iface:kernel_mem0_address
wire mm_interconnect_0_acl_iface_kernel_mem0_write; // mm_interconnect_0:acl_iface_kernel_mem0_write -> acl_iface:kernel_mem0_write
wire mm_interconnect_0_acl_iface_kernel_mem0_read; // mm_interconnect_0:acl_iface_kernel_mem0_read -> acl_iface:kernel_mem0_read
wire [255:0] mm_interconnect_0_acl_iface_kernel_mem0_readdata; // acl_iface:kernel_mem0_readdata -> mm_interconnect_0:acl_iface_kernel_mem0_readdata
wire mm_interconnect_0_acl_iface_kernel_mem0_debugaccess; // mm_interconnect_0:acl_iface_kernel_mem0_debugaccess -> acl_iface:kernel_mem0_debugaccess
wire mm_interconnect_0_acl_iface_kernel_mem0_readdatavalid; // acl_iface:kernel_mem0_readdatavalid -> mm_interconnect_0:acl_iface_kernel_mem0_readdatavalid
wire [31:0] mm_interconnect_0_acl_iface_kernel_mem0_byteenable; // mm_interconnect_0:acl_iface_kernel_mem0_byteenable -> acl_iface:kernel_mem0_byteenable
wire [0:0] acl_iface_kernel_cra_burstcount; // acl_iface:kernel_cra_burstcount -> mm_interconnect_1:acl_iface_kernel_cra_burstcount
wire acl_iface_kernel_cra_waitrequest; // mm_interconnect_1:acl_iface_kernel_cra_waitrequest -> acl_iface:kernel_cra_waitrequest
wire [29:0] acl_iface_kernel_cra_address; // acl_iface:kernel_cra_address -> mm_interconnect_1:acl_iface_kernel_cra_address
wire [63:0] acl_iface_kernel_cra_writedata; // acl_iface:kernel_cra_writedata -> mm_interconnect_1:acl_iface_kernel_cra_writedata
wire acl_iface_kernel_cra_write; // acl_iface:kernel_cra_write -> mm_interconnect_1:acl_iface_kernel_cra_write
wire acl_iface_kernel_cra_read; // acl_iface:kernel_cra_read -> mm_interconnect_1:acl_iface_kernel_cra_read
wire [63:0] acl_iface_kernel_cra_readdata; // mm_interconnect_1:acl_iface_kernel_cra_readdata -> acl_iface:kernel_cra_readdata
wire acl_iface_kernel_cra_debugaccess; // acl_iface:kernel_cra_debugaccess -> mm_interconnect_1:acl_iface_kernel_cra_debugaccess
wire [7:0] acl_iface_kernel_cra_byteenable; // acl_iface:kernel_cra_byteenable -> mm_interconnect_1:acl_iface_kernel_cra_byteenable
wire acl_iface_kernel_cra_readdatavalid; // mm_interconnect_1:acl_iface_kernel_cra_readdatavalid -> acl_iface:kernel_cra_readdatavalid
wire mm_interconnect_1_cra_root_cra_slave_waitrequest; // cra_root:avs_waitrequest -> mm_interconnect_1:cra_root_cra_slave_waitrequest
wire [63:0] mm_interconnect_1_cra_root_cra_slave_writedata; // mm_interconnect_1:cra_root_cra_slave_writedata -> cra_root:avs_writedata
wire [3:0] mm_interconnect_1_cra_root_cra_slave_address; // mm_interconnect_1:cra_root_cra_slave_address -> cra_root:avs_addr
wire mm_interconnect_1_cra_root_cra_slave_write; // mm_interconnect_1:cra_root_cra_slave_write -> cra_root:avs_write
wire mm_interconnect_1_cra_root_cra_slave_read; // mm_interconnect_1:cra_root_cra_slave_read -> cra_root:avs_read
wire [63:0] mm_interconnect_1_cra_root_cra_slave_readdata; // cra_root:avs_readdata -> mm_interconnect_1:cra_root_cra_slave_readdata
wire mm_interconnect_1_cra_root_cra_slave_readdatavalid; // cra_root:avs_readdatavalid -> mm_interconnect_1:cra_root_cra_slave_readdatavalid
wire [7:0] mm_interconnect_1_cra_root_cra_slave_byteenable; // mm_interconnect_1:cra_root_cra_slave_byteenable -> cra_root:avs_byteena
wire irq_mapper_receiver0_irq; // Sobel_system:kernel_irq -> irq_mapper:receiver0_irq
wire [0:0] acl_iface_kernel_irq_irq; // irq_mapper:sender_irq -> acl_iface:kernel_irq_irq
system_acl_iface acl_iface (
.config_clk_clk (clk_50_clk), // config_clk.clk
.reset_n (reset_50_reset_n), // global_reset.reset_n
.kernel_pll_refclk_clk (clk_50_clk), // kernel_pll_refclk.clk
.kernel_clk_clk (acl_iface_kernel_clk_clk), // kernel_clk.clk
.kernel_reset_reset_n (acl_iface_kernel_reset_reset), // kernel_reset.reset_n
.kernel_clk2x_clk (acl_iface_kernel_clk2x_clk), // kernel_clk2x.clk
.kernel_mem0_waitrequest (mm_interconnect_0_acl_iface_kernel_mem0_waitrequest), // kernel_mem0.waitrequest
.kernel_mem0_readdata (mm_interconnect_0_acl_iface_kernel_mem0_readdata), // .readdata
.kernel_mem0_readdatavalid (mm_interconnect_0_acl_iface_kernel_mem0_readdatavalid), // .readdatavalid
.kernel_mem0_burstcount (mm_interconnect_0_acl_iface_kernel_mem0_burstcount), // .burstcount
.kernel_mem0_writedata (mm_interconnect_0_acl_iface_kernel_mem0_writedata), // .writedata
.kernel_mem0_address (mm_interconnect_0_acl_iface_kernel_mem0_address), // .address
.kernel_mem0_write (mm_interconnect_0_acl_iface_kernel_mem0_write), // .write
.kernel_mem0_read (mm_interconnect_0_acl_iface_kernel_mem0_read), // .read
.kernel_mem0_byteenable (mm_interconnect_0_acl_iface_kernel_mem0_byteenable), // .byteenable
.kernel_mem0_debugaccess (mm_interconnect_0_acl_iface_kernel_mem0_debugaccess), // .debugaccess
.acl_kernel_clk_kernel_pll_locked_export (), // acl_kernel_clk_kernel_pll_locked.export
.kernel_clk_snoop_clk (kernel_clk_clk), // kernel_clk_snoop.clk
.memory_mem_a (memory_mem_a), // memory.mem_a
.memory_mem_ba (memory_mem_ba), // .mem_ba
.memory_mem_ck (memory_mem_ck), // .mem_ck
.memory_mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.memory_mem_cke (memory_mem_cke), // .mem_cke
.memory_mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.memory_mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.memory_mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.memory_mem_we_n (memory_mem_we_n), // .mem_we_n
.memory_mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.memory_mem_dq (memory_mem_dq), // .mem_dq
.memory_mem_dqs (memory_mem_dqs), // .mem_dqs
.memory_mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.memory_mem_odt (memory_mem_odt), // .mem_odt
.memory_mem_dm (memory_mem_dm), // .mem_dm
.memory_oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.peripheral_hps_io_emac1_inst_TX_CLK (peripheral_hps_io_emac1_inst_TX_CLK), // peripheral.hps_io_emac1_inst_TX_CLK
.peripheral_hps_io_emac1_inst_TXD0 (peripheral_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.peripheral_hps_io_emac1_inst_TXD1 (peripheral_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.peripheral_hps_io_emac1_inst_TXD2 (peripheral_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.peripheral_hps_io_emac1_inst_TXD3 (peripheral_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.peripheral_hps_io_emac1_inst_RXD0 (peripheral_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.peripheral_hps_io_emac1_inst_MDIO (peripheral_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.peripheral_hps_io_emac1_inst_MDC (peripheral_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.peripheral_hps_io_emac1_inst_RX_CTL (peripheral_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.peripheral_hps_io_emac1_inst_TX_CTL (peripheral_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.peripheral_hps_io_emac1_inst_RX_CLK (peripheral_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.peripheral_hps_io_emac1_inst_RXD1 (peripheral_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.peripheral_hps_io_emac1_inst_RXD2 (peripheral_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.peripheral_hps_io_emac1_inst_RXD3 (peripheral_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.peripheral_hps_io_sdio_inst_CMD (peripheral_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.peripheral_hps_io_sdio_inst_D0 (peripheral_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.peripheral_hps_io_sdio_inst_D1 (peripheral_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.peripheral_hps_io_sdio_inst_CLK (peripheral_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.peripheral_hps_io_sdio_inst_D2 (peripheral_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.peripheral_hps_io_sdio_inst_D3 (peripheral_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.peripheral_hps_io_uart0_inst_RX (peripheral_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.peripheral_hps_io_uart0_inst_TX (peripheral_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.peripheral_hps_io_i2c1_inst_SDA (peripheral_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.peripheral_hps_io_i2c1_inst_SCL (peripheral_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.peripheral_hps_io_gpio_inst_GPIO53 (peripheral_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.acl_internal_memorg_kernel_mode (), // acl_internal_memorg_kernel.mode
.kernel_irq_irq (acl_iface_kernel_irq_irq), // kernel_irq.irq
.kernel_cra_waitrequest (acl_iface_kernel_cra_waitrequest), // kernel_cra.waitrequest
.kernel_cra_readdata (acl_iface_kernel_cra_readdata), // .readdata
.kernel_cra_readdatavalid (acl_iface_kernel_cra_readdatavalid), // .readdatavalid
.kernel_cra_burstcount (acl_iface_kernel_cra_burstcount), // .burstcount
.kernel_cra_writedata (acl_iface_kernel_cra_writedata), // .writedata
.kernel_cra_address (acl_iface_kernel_cra_address), // .address
.kernel_cra_write (acl_iface_kernel_cra_write), // .write
.kernel_cra_read (acl_iface_kernel_cra_read), // .read
.kernel_cra_byteenable (acl_iface_kernel_cra_byteenable), // .byteenable
.kernel_cra_debugaccess (acl_iface_kernel_cra_debugaccess), // .debugaccess
.kernel_interface_acl_bsp_memorg_host_mode () // kernel_interface_acl_bsp_memorg_host.mode
);
Sobel_system sobel_system (
.clock (acl_iface_kernel_clk_clk), // clock_reset.clk
.resetn (acl_iface_kernel_reset_reset), // clock_reset_reset.reset_n
.clock2x (acl_iface_kernel_clk2x_clk), // clock_reset2x.clk
.avs_sobel_cra_read (avs_sobel_cra_cra_ring_cra_master_read), // avs_sobel_cra.read
.avs_sobel_cra_write (avs_sobel_cra_cra_ring_cra_master_write), // .write
.avs_sobel_cra_address (avs_sobel_cra_cra_ring_cra_master_address), // .address
.avs_sobel_cra_writedata (avs_sobel_cra_cra_ring_cra_master_writedata), // .writedata
.avs_sobel_cra_byteenable (avs_sobel_cra_cra_ring_cra_master_byteenable), // .byteenable
.avs_sobel_cra_waitrequest (avs_sobel_cra_cra_ring_cra_master_waitrequest), // .waitrequest
.avs_sobel_cra_readdata (avs_sobel_cra_cra_ring_cra_master_readdata), // .readdata
.avs_sobel_cra_readdatavalid (avs_sobel_cra_cra_ring_cra_master_readdatavalid), // .readdatavalid
.kernel_irq (irq_mapper_receiver0_irq), // kernel_irq.irq
.avm_memgmem0_port_0_0_rw_address (sobel_system_avm_memgmem0_port_0_0_rw_address), // avm_memgmem0_port_0_0_rw.address
.avm_memgmem0_port_0_0_rw_read (sobel_system_avm_memgmem0_port_0_0_rw_read), // .read
.avm_memgmem0_port_0_0_rw_write (sobel_system_avm_memgmem0_port_0_0_rw_write), // .write
.avm_memgmem0_port_0_0_rw_burstcount (sobel_system_avm_memgmem0_port_0_0_rw_burstcount), // .burstcount
.avm_memgmem0_port_0_0_rw_writedata (sobel_system_avm_memgmem0_port_0_0_rw_writedata), // .writedata
.avm_memgmem0_port_0_0_rw_byteenable (sobel_system_avm_memgmem0_port_0_0_rw_byteenable), // .byteenable
.avm_memgmem0_port_0_0_rw_readdata (sobel_system_avm_memgmem0_port_0_0_rw_readdata), // .readdata
.avm_memgmem0_port_0_0_rw_waitrequest (sobel_system_avm_memgmem0_port_0_0_rw_waitrequest), // .waitrequest
.avm_memgmem0_port_0_0_rw_readdatavalid (sobel_system_avm_memgmem0_port_0_0_rw_readdatavalid) // .readdatavalid
);
cra_ring_root #(
.ADDR_W (4),
.DATA_W (64),
.ID_W (0)
) cra_root (
.clk (acl_iface_kernel_clk_clk), // clock.clk
.rst_n (acl_iface_kernel_reset_reset), // reset.reset_n
.avs_write (mm_interconnect_1_cra_root_cra_slave_write), // cra_slave.write
.avs_addr (mm_interconnect_1_cra_root_cra_slave_address), // .address
.avs_byteena (mm_interconnect_1_cra_root_cra_slave_byteenable), // .byteenable
.avs_writedata (mm_interconnect_1_cra_root_cra_slave_writedata), // .writedata
.avs_readdata (mm_interconnect_1_cra_root_cra_slave_readdata), // .readdata
.avs_readdatavalid (mm_interconnect_1_cra_root_cra_slave_readdatavalid), // .readdatavalid
.avs_waitrequest (mm_interconnect_1_cra_root_cra_slave_waitrequest), // .waitrequest
.avs_read (mm_interconnect_1_cra_root_cra_slave_read), // .read
.ri_write (avs_sobel_cra_cra_ring_ring_out_write), // ring_in.write
.ri_addr (avs_sobel_cra_cra_ring_ring_out_addr), // .addr
.ri_byteena (avs_sobel_cra_cra_ring_ring_out_byteena), // .byteena
.ri_data (avs_sobel_cra_cra_ring_ring_out_data), // .data
.ri_read (avs_sobel_cra_cra_ring_ring_out_read), // .read
.ri_datavalid (avs_sobel_cra_cra_ring_ring_out_datavalid), // .datavalid
.ri_waitrequest (cra_root_ring_in_waitrequest), // .waitrequest
.ro_read (cra_root_ring_out_read), // ring_out.read
.ro_write (cra_root_ring_out_write), // .write
.ro_addr (cra_root_ring_out_addr), // .addr
.ro_data (cra_root_ring_out_data), // .data
.ro_byteena (cra_root_ring_out_byteena), // .byteena
.ro_datavalid (cra_root_ring_out_datavalid), // .datavalid
.ro_waitrequest (avs_sobel_cra_cra_ring_ring_in_waitrequest) // .waitrequest
);
cra_ring_node #(
.RING_ADDR_W (4),
.CRA_ADDR_W (4),
.DATA_W (64),
.ID_W (0),
.ID (32'b00000000000000000000000000000000)
) avs_sobel_cra_cra_ring (
.clk (acl_iface_kernel_clk_clk), // clock.clk
.rst_n (acl_iface_kernel_reset_reset), // reset.reset_n
.avm_read (avs_sobel_cra_cra_ring_cra_master_read), // cra_master.read
.avm_write (avs_sobel_cra_cra_ring_cra_master_write), // .write
.avm_addr (avs_sobel_cra_cra_ring_cra_master_address), // .address
.avm_byteena (avs_sobel_cra_cra_ring_cra_master_byteenable), // .byteenable
.avm_writedata (avs_sobel_cra_cra_ring_cra_master_writedata), // .writedata
.avm_readdata (avs_sobel_cra_cra_ring_cra_master_readdata), // .readdata
.avm_readdatavalid (avs_sobel_cra_cra_ring_cra_master_readdatavalid), // .readdatavalid
.avm_waitrequest (avs_sobel_cra_cra_ring_cra_master_waitrequest), // .waitrequest
.ri_read (cra_root_ring_out_read), // ring_in.read
.ri_write (cra_root_ring_out_write), // .write
.ri_addr (cra_root_ring_out_addr), // .addr
.ri_data (cra_root_ring_out_data), // .data
.ri_byteena (cra_root_ring_out_byteena), // .byteena
.ri_datavalid (cra_root_ring_out_datavalid), // .datavalid
.ri_waitrequest (avs_sobel_cra_cra_ring_ring_in_waitrequest), // .waitrequest
.ro_read (avs_sobel_cra_cra_ring_ring_out_read), // ring_out.read
.ro_write (avs_sobel_cra_cra_ring_ring_out_write), // .write
.ro_addr (avs_sobel_cra_cra_ring_ring_out_addr), // .addr
.ro_data (avs_sobel_cra_cra_ring_ring_out_data), // .data
.ro_byteena (avs_sobel_cra_cra_ring_ring_out_byteena), // .byteena
.ro_datavalid (avs_sobel_cra_cra_ring_ring_out_datavalid), // .datavalid
.ro_waitrequest (cra_root_ring_in_waitrequest) // .waitrequest
);
system_mm_interconnect_0 mm_interconnect_0 (
.acl_iface_kernel_clk_clk (acl_iface_kernel_clk_clk), // acl_iface_kernel_clk.clk
.Sobel_system_clock_reset_reset_reset_bridge_in_reset_reset (~acl_iface_kernel_reset_reset), // Sobel_system_clock_reset_reset_reset_bridge_in_reset.reset
.Sobel_system_avm_memgmem0_port_0_0_rw_address (sobel_system_avm_memgmem0_port_0_0_rw_address), // Sobel_system_avm_memgmem0_port_0_0_rw.address
.Sobel_system_avm_memgmem0_port_0_0_rw_waitrequest (sobel_system_avm_memgmem0_port_0_0_rw_waitrequest), // .waitrequest
.Sobel_system_avm_memgmem0_port_0_0_rw_burstcount (sobel_system_avm_memgmem0_port_0_0_rw_burstcount), // .burstcount
.Sobel_system_avm_memgmem0_port_0_0_rw_byteenable (sobel_system_avm_memgmem0_port_0_0_rw_byteenable), // .byteenable
.Sobel_system_avm_memgmem0_port_0_0_rw_read (sobel_system_avm_memgmem0_port_0_0_rw_read), // .read
.Sobel_system_avm_memgmem0_port_0_0_rw_readdata (sobel_system_avm_memgmem0_port_0_0_rw_readdata), // .readdata
.Sobel_system_avm_memgmem0_port_0_0_rw_readdatavalid (sobel_system_avm_memgmem0_port_0_0_rw_readdatavalid), // .readdatavalid
.Sobel_system_avm_memgmem0_port_0_0_rw_write (sobel_system_avm_memgmem0_port_0_0_rw_write), // .write
.Sobel_system_avm_memgmem0_port_0_0_rw_writedata (sobel_system_avm_memgmem0_port_0_0_rw_writedata), // .writedata
.acl_iface_kernel_mem0_address (mm_interconnect_0_acl_iface_kernel_mem0_address), // acl_iface_kernel_mem0.address
.acl_iface_kernel_mem0_write (mm_interconnect_0_acl_iface_kernel_mem0_write), // .write
.acl_iface_kernel_mem0_read (mm_interconnect_0_acl_iface_kernel_mem0_read), // .read
.acl_iface_kernel_mem0_readdata (mm_interconnect_0_acl_iface_kernel_mem0_readdata), // .readdata
.acl_iface_kernel_mem0_writedata (mm_interconnect_0_acl_iface_kernel_mem0_writedata), // .writedata
.acl_iface_kernel_mem0_burstcount (mm_interconnect_0_acl_iface_kernel_mem0_burstcount), // .burstcount
.acl_iface_kernel_mem0_byteenable (mm_interconnect_0_acl_iface_kernel_mem0_byteenable), // .byteenable
.acl_iface_kernel_mem0_readdatavalid (mm_interconnect_0_acl_iface_kernel_mem0_readdatavalid), // .readdatavalid
.acl_iface_kernel_mem0_waitrequest (mm_interconnect_0_acl_iface_kernel_mem0_waitrequest), // .waitrequest
.acl_iface_kernel_mem0_debugaccess (mm_interconnect_0_acl_iface_kernel_mem0_debugaccess) // .debugaccess
);
system_mm_interconnect_1 mm_interconnect_1 (
.acl_iface_kernel_clk_clk (acl_iface_kernel_clk_clk), // acl_iface_kernel_clk.clk
.cra_root_reset_reset_bridge_in_reset_reset (~acl_iface_kernel_reset_reset), // cra_root_reset_reset_bridge_in_reset.reset
.acl_iface_kernel_cra_address (acl_iface_kernel_cra_address), // acl_iface_kernel_cra.address
.acl_iface_kernel_cra_waitrequest (acl_iface_kernel_cra_waitrequest), // .waitrequest
.acl_iface_kernel_cra_burstcount (acl_iface_kernel_cra_burstcount), // .burstcount
.acl_iface_kernel_cra_byteenable (acl_iface_kernel_cra_byteenable), // .byteenable
.acl_iface_kernel_cra_read (acl_iface_kernel_cra_read), // .read
.acl_iface_kernel_cra_readdata (acl_iface_kernel_cra_readdata), // .readdata
.acl_iface_kernel_cra_readdatavalid (acl_iface_kernel_cra_readdatavalid), // .readdatavalid
.acl_iface_kernel_cra_write (acl_iface_kernel_cra_write), // .write
.acl_iface_kernel_cra_writedata (acl_iface_kernel_cra_writedata), // .writedata
.acl_iface_kernel_cra_debugaccess (acl_iface_kernel_cra_debugaccess), // .debugaccess
.cra_root_cra_slave_address (mm_interconnect_1_cra_root_cra_slave_address), // cra_root_cra_slave.address
.cra_root_cra_slave_write (mm_interconnect_1_cra_root_cra_slave_write), // .write
.cra_root_cra_slave_read (mm_interconnect_1_cra_root_cra_slave_read), // .read
.cra_root_cra_slave_readdata (mm_interconnect_1_cra_root_cra_slave_readdata), // .readdata
.cra_root_cra_slave_writedata (mm_interconnect_1_cra_root_cra_slave_writedata), // .writedata
.cra_root_cra_slave_byteenable (mm_interconnect_1_cra_root_cra_slave_byteenable), // .byteenable
.cra_root_cra_slave_readdatavalid (mm_interconnect_1_cra_root_cra_slave_readdatavalid), // .readdatavalid
.cra_root_cra_slave_waitrequest (mm_interconnect_1_cra_root_cra_slave_waitrequest) // .waitrequest
);
system_irq_mapper irq_mapper (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (~acl_iface_kernel_reset_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (acl_iface_kernel_irq_irq) // sender.irq
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLCLKP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLCLKP_FUNCTIONAL_PP_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
// Delay Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (m0 , GATE, clkn, , VPWR, VGND);
and and0 (GCLK , m0, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLCLKP_FUNCTIONAL_PP_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:39 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_lms_pcore_0_0/ip_design_lms_pcore_0_0_sim_netlist.v
// Design : ip_design_lms_pcore_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "ip_design_lms_pcore_0_0,lms_pcore,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lms_pcore,Vivado 2017.3" *)
(* NotValidForBitStream *)
module ip_design_lms_pcore_0_0
(IPCORE_CLK,
IPCORE_RESETN,
AXI4_Lite_ACLK,
AXI4_Lite_ARESETN,
AXI4_Lite_AWADDR,
AXI4_Lite_AWVALID,
AXI4_Lite_WDATA,
AXI4_Lite_WSTRB,
AXI4_Lite_WVALID,
AXI4_Lite_BREADY,
AXI4_Lite_ARADDR,
AXI4_Lite_ARVALID,
AXI4_Lite_RREADY,
AXI4_Lite_AWREADY,
AXI4_Lite_WREADY,
AXI4_Lite_BRESP,
AXI4_Lite_BVALID,
AXI4_Lite_ARREADY,
AXI4_Lite_RDATA,
AXI4_Lite_RRESP,
AXI4_Lite_RVALID);
(* x_interface_info = "xilinx.com:signal:clock:1.0 IPCORE_CLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME IPCORE_CLK, ASSOCIATED_RESET IPCORE_RESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input IPCORE_CLK;
(* x_interface_info = "xilinx.com:signal:reset:1.0 IPCORE_RESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME IPCORE_RESETN, POLARITY ACTIVE_LOW" *) input IPCORE_RESETN;
(* x_interface_info = "xilinx.com:signal:clock:1.0 AXI4_Lite_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME AXI4_Lite_ACLK, ASSOCIATED_RESET AXI4_Lite_ARESETN, ASSOCIATED_BUSIF AXI4_Lite, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input AXI4_Lite_ACLK;
(* x_interface_info = "xilinx.com:signal:reset:1.0 AXI4_Lite_ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME AXI4_Lite_ARESETN, POLARITY ACTIVE_LOW" *) input AXI4_Lite_ARESETN;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME AXI4_Lite, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [15:0]AXI4_Lite_AWADDR;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite AWVALID" *) input AXI4_Lite_AWVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite WDATA" *) input [31:0]AXI4_Lite_WDATA;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite WSTRB" *) input [3:0]AXI4_Lite_WSTRB;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite WVALID" *) input AXI4_Lite_WVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite BREADY" *) input AXI4_Lite_BREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite ARADDR" *) input [15:0]AXI4_Lite_ARADDR;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite ARVALID" *) input AXI4_Lite_ARVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite RREADY" *) input AXI4_Lite_RREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite AWREADY" *) output AXI4_Lite_AWREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite WREADY" *) output AXI4_Lite_WREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite BRESP" *) output [1:0]AXI4_Lite_BRESP;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite BVALID" *) output AXI4_Lite_BVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite ARREADY" *) output AXI4_Lite_ARREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite RDATA" *) output [31:0]AXI4_Lite_RDATA;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite RRESP" *) output [1:0]AXI4_Lite_RRESP;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI4_Lite RVALID" *) output AXI4_Lite_RVALID;
wire \<const0> ;
wire AXI4_Lite_ACLK;
wire [15:0]AXI4_Lite_ARADDR;
wire AXI4_Lite_ARESETN;
wire AXI4_Lite_ARREADY;
wire AXI4_Lite_ARVALID;
wire [15:0]AXI4_Lite_AWADDR;
wire AXI4_Lite_AWREADY;
wire AXI4_Lite_AWVALID;
wire AXI4_Lite_BREADY;
wire AXI4_Lite_BVALID;
wire [30:0]\^AXI4_Lite_RDATA ;
wire AXI4_Lite_RREADY;
wire AXI4_Lite_RVALID;
wire [31:0]AXI4_Lite_WDATA;
wire AXI4_Lite_WREADY;
wire AXI4_Lite_WVALID;
wire IPCORE_CLK;
wire IPCORE_RESETN;
assign AXI4_Lite_BRESP[1] = \<const0> ;
assign AXI4_Lite_BRESP[0] = \<const0> ;
assign AXI4_Lite_RDATA[31] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[30] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[29] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[28] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[27] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[26] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[25] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[24] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[23] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[22] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[21] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[20] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[19] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[18] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[17] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[16] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[15] = \^AXI4_Lite_RDATA [30];
assign AXI4_Lite_RDATA[14:0] = \^AXI4_Lite_RDATA [14:0];
assign AXI4_Lite_RRESP[1] = \<const0> ;
assign AXI4_Lite_RRESP[0] = \<const0> ;
GND GND
(.G(\<const0> ));
ip_design_lms_pcore_0_0_lms_pcore U0
(.AXI4_Lite_ACLK(AXI4_Lite_ACLK),
.AXI4_Lite_ARADDR(AXI4_Lite_ARADDR[15:2]),
.AXI4_Lite_ARESETN(AXI4_Lite_ARESETN),
.AXI4_Lite_ARREADY(AXI4_Lite_ARREADY),
.AXI4_Lite_ARVALID(AXI4_Lite_ARVALID),
.AXI4_Lite_AWADDR(AXI4_Lite_AWADDR[15:2]),
.AXI4_Lite_AWREADY(AXI4_Lite_AWREADY),
.AXI4_Lite_AWVALID(AXI4_Lite_AWVALID),
.AXI4_Lite_BREADY(AXI4_Lite_BREADY),
.AXI4_Lite_BVALID(AXI4_Lite_BVALID),
.AXI4_Lite_RDATA({\^AXI4_Lite_RDATA [30],\^AXI4_Lite_RDATA [14:0]}),
.AXI4_Lite_RREADY(AXI4_Lite_RREADY),
.AXI4_Lite_RVALID(AXI4_Lite_RVALID),
.AXI4_Lite_WDATA(AXI4_Lite_WDATA[15:0]),
.AXI4_Lite_WREADY(AXI4_Lite_WREADY),
.AXI4_Lite_WVALID(AXI4_Lite_WVALID),
.IPCORE_CLK(IPCORE_CLK),
.IPCORE_RESETN(IPCORE_RESETN));
endmodule
(* ORIG_REF_NAME = "LMS" *)
module ip_design_lms_pcore_0_0_LMS
(mul_temp_16,
filter_sum,
\write_reg_x_k_reg[15] ,
cop_dut_enable,
IPCORE_CLK,
AR,
\write_reg_d_k_reg[3] ,
DI,
Q,
\write_reg_d_k_reg[3]_0 ,
\write_reg_d_k_reg[7] ,
\write_reg_d_k_reg[11] ,
S);
output [15:0]mul_temp_16;
output [15:0]filter_sum;
input [15:0]\write_reg_x_k_reg[15] ;
input cop_dut_enable;
input IPCORE_CLK;
input [0:0]AR;
input [2:0]\write_reg_d_k_reg[3] ;
input [0:0]DI;
input [14:0]Q;
input [3:0]\write_reg_d_k_reg[3]_0 ;
input [3:0]\write_reg_d_k_reg[7] ;
input [3:0]\write_reg_d_k_reg[11] ;
input [3:0]S;
wire [0:0]AR;
wire ARG__0_i_1_n_0;
wire ARG__0_n_100;
wire ARG__0_n_101;
wire ARG__0_n_102;
wire ARG__0_n_103;
wire ARG__0_n_104;
wire ARG__0_n_105;
wire ARG__0_n_92;
wire ARG__0_n_93;
wire ARG__0_n_94;
wire ARG__0_n_95;
wire ARG__0_n_96;
wire ARG__0_n_97;
wire ARG__0_n_98;
wire ARG__0_n_99;
wire ARG__10_i_1_n_0;
wire ARG__10_n_100;
wire ARG__10_n_101;
wire ARG__10_n_102;
wire ARG__10_n_103;
wire ARG__10_n_104;
wire ARG__10_n_105;
wire ARG__10_n_92;
wire ARG__10_n_93;
wire ARG__10_n_94;
wire ARG__10_n_95;
wire ARG__10_n_96;
wire ARG__10_n_97;
wire ARG__10_n_98;
wire ARG__10_n_99;
wire ARG__11_i_1_n_0;
wire ARG__11_n_100;
wire ARG__11_n_101;
wire ARG__11_n_102;
wire ARG__11_n_103;
wire ARG__11_n_104;
wire ARG__11_n_105;
wire ARG__11_n_76;
wire ARG__11_n_77;
wire ARG__11_n_78;
wire ARG__11_n_79;
wire ARG__11_n_80;
wire ARG__11_n_81;
wire ARG__11_n_82;
wire ARG__11_n_83;
wire ARG__11_n_84;
wire ARG__11_n_85;
wire ARG__11_n_86;
wire ARG__11_n_87;
wire ARG__11_n_88;
wire ARG__11_n_89;
wire ARG__11_n_90;
wire ARG__11_n_91;
wire ARG__11_n_92;
wire ARG__11_n_93;
wire ARG__11_n_94;
wire ARG__11_n_95;
wire ARG__11_n_96;
wire ARG__11_n_97;
wire ARG__11_n_98;
wire ARG__11_n_99;
wire ARG__12_i_1_n_0;
wire ARG__12_n_100;
wire ARG__12_n_101;
wire ARG__12_n_102;
wire ARG__12_n_103;
wire ARG__12_n_104;
wire ARG__12_n_105;
wire ARG__12_n_92;
wire ARG__12_n_93;
wire ARG__12_n_94;
wire ARG__12_n_95;
wire ARG__12_n_96;
wire ARG__12_n_97;
wire ARG__12_n_98;
wire ARG__12_n_99;
wire ARG__13_i_1_n_0;
wire ARG__13_n_100;
wire ARG__13_n_101;
wire ARG__13_n_102;
wire ARG__13_n_103;
wire ARG__13_n_104;
wire ARG__13_n_105;
wire ARG__13_n_76;
wire ARG__13_n_77;
wire ARG__13_n_78;
wire ARG__13_n_79;
wire ARG__13_n_80;
wire ARG__13_n_81;
wire ARG__13_n_82;
wire ARG__13_n_83;
wire ARG__13_n_84;
wire ARG__13_n_85;
wire ARG__13_n_86;
wire ARG__13_n_87;
wire ARG__13_n_88;
wire ARG__13_n_89;
wire ARG__13_n_90;
wire ARG__13_n_91;
wire ARG__13_n_92;
wire ARG__13_n_93;
wire ARG__13_n_94;
wire ARG__13_n_95;
wire ARG__13_n_96;
wire ARG__13_n_97;
wire ARG__13_n_98;
wire ARG__13_n_99;
wire ARG__14_i_1_n_0;
wire ARG__14_n_100;
wire ARG__14_n_101;
wire ARG__14_n_102;
wire ARG__14_n_103;
wire ARG__14_n_104;
wire ARG__14_n_105;
wire ARG__14_n_92;
wire ARG__14_n_93;
wire ARG__14_n_94;
wire ARG__14_n_95;
wire ARG__14_n_96;
wire ARG__14_n_97;
wire ARG__14_n_98;
wire ARG__14_n_99;
wire ARG__15_i_1_n_0;
wire ARG__15_n_100;
wire ARG__15_n_101;
wire ARG__15_n_102;
wire ARG__15_n_103;
wire ARG__15_n_104;
wire ARG__15_n_105;
wire ARG__15_n_76;
wire ARG__15_n_77;
wire ARG__15_n_78;
wire ARG__15_n_79;
wire ARG__15_n_80;
wire ARG__15_n_81;
wire ARG__15_n_82;
wire ARG__15_n_83;
wire ARG__15_n_84;
wire ARG__15_n_85;
wire ARG__15_n_86;
wire ARG__15_n_87;
wire ARG__15_n_88;
wire ARG__15_n_89;
wire ARG__15_n_90;
wire ARG__15_n_91;
wire ARG__15_n_92;
wire ARG__15_n_93;
wire ARG__15_n_94;
wire ARG__15_n_95;
wire ARG__15_n_96;
wire ARG__15_n_97;
wire ARG__15_n_98;
wire ARG__15_n_99;
wire ARG__16_i_1_n_0;
wire ARG__16_n_100;
wire ARG__16_n_101;
wire ARG__16_n_102;
wire ARG__16_n_103;
wire ARG__16_n_104;
wire ARG__16_n_105;
wire ARG__16_n_92;
wire ARG__16_n_93;
wire ARG__16_n_94;
wire ARG__16_n_95;
wire ARG__16_n_96;
wire ARG__16_n_97;
wire ARG__16_n_98;
wire ARG__16_n_99;
wire ARG__17_i_1_n_0;
wire ARG__17_n_100;
wire ARG__17_n_101;
wire ARG__17_n_102;
wire ARG__17_n_103;
wire ARG__17_n_104;
wire ARG__17_n_105;
wire ARG__17_n_76;
wire ARG__17_n_77;
wire ARG__17_n_78;
wire ARG__17_n_79;
wire ARG__17_n_80;
wire ARG__17_n_81;
wire ARG__17_n_82;
wire ARG__17_n_83;
wire ARG__17_n_84;
wire ARG__17_n_85;
wire ARG__17_n_86;
wire ARG__17_n_87;
wire ARG__17_n_88;
wire ARG__17_n_89;
wire ARG__17_n_90;
wire ARG__17_n_91;
wire ARG__17_n_92;
wire ARG__17_n_93;
wire ARG__17_n_94;
wire ARG__17_n_95;
wire ARG__17_n_96;
wire ARG__17_n_97;
wire ARG__17_n_98;
wire ARG__17_n_99;
wire ARG__18_i_1_n_0;
wire ARG__18_n_100;
wire ARG__18_n_101;
wire ARG__18_n_102;
wire ARG__18_n_103;
wire ARG__18_n_104;
wire ARG__18_n_105;
wire ARG__18_n_92;
wire ARG__18_n_93;
wire ARG__18_n_94;
wire ARG__18_n_95;
wire ARG__18_n_96;
wire ARG__18_n_97;
wire ARG__18_n_98;
wire ARG__18_n_99;
wire ARG__19_i_1_n_0;
wire ARG__19_n_100;
wire ARG__19_n_101;
wire ARG__19_n_102;
wire ARG__19_n_103;
wire ARG__19_n_104;
wire ARG__19_n_105;
wire ARG__19_n_76;
wire ARG__19_n_77;
wire ARG__19_n_78;
wire ARG__19_n_79;
wire ARG__19_n_80;
wire ARG__19_n_81;
wire ARG__19_n_82;
wire ARG__19_n_83;
wire ARG__19_n_84;
wire ARG__19_n_85;
wire ARG__19_n_86;
wire ARG__19_n_87;
wire ARG__19_n_88;
wire ARG__19_n_89;
wire ARG__19_n_90;
wire ARG__19_n_91;
wire ARG__19_n_92;
wire ARG__19_n_93;
wire ARG__19_n_94;
wire ARG__19_n_95;
wire ARG__19_n_96;
wire ARG__19_n_97;
wire ARG__19_n_98;
wire ARG__19_n_99;
wire ARG__1_i_1_n_0;
wire ARG__1_n_100;
wire ARG__1_n_101;
wire ARG__1_n_102;
wire ARG__1_n_103;
wire ARG__1_n_104;
wire ARG__1_n_105;
wire ARG__1_n_76;
wire ARG__1_n_77;
wire ARG__1_n_78;
wire ARG__1_n_79;
wire ARG__1_n_80;
wire ARG__1_n_81;
wire ARG__1_n_82;
wire ARG__1_n_83;
wire ARG__1_n_84;
wire ARG__1_n_85;
wire ARG__1_n_86;
wire ARG__1_n_87;
wire ARG__1_n_88;
wire ARG__1_n_89;
wire ARG__1_n_90;
wire ARG__1_n_91;
wire ARG__1_n_92;
wire ARG__1_n_93;
wire ARG__1_n_94;
wire ARG__1_n_95;
wire ARG__1_n_96;
wire ARG__1_n_97;
wire ARG__1_n_98;
wire ARG__1_n_99;
wire ARG__20_i_1_n_0;
wire ARG__20_n_100;
wire ARG__20_n_101;
wire ARG__20_n_102;
wire ARG__20_n_103;
wire ARG__20_n_104;
wire ARG__20_n_105;
wire ARG__20_n_92;
wire ARG__20_n_93;
wire ARG__20_n_94;
wire ARG__20_n_95;
wire ARG__20_n_96;
wire ARG__20_n_97;
wire ARG__20_n_98;
wire ARG__20_n_99;
wire ARG__21_i_1_n_0;
wire ARG__21_n_100;
wire ARG__21_n_101;
wire ARG__21_n_102;
wire ARG__21_n_103;
wire ARG__21_n_104;
wire ARG__21_n_105;
wire ARG__21_n_76;
wire ARG__21_n_77;
wire ARG__21_n_78;
wire ARG__21_n_79;
wire ARG__21_n_80;
wire ARG__21_n_81;
wire ARG__21_n_82;
wire ARG__21_n_83;
wire ARG__21_n_84;
wire ARG__21_n_85;
wire ARG__21_n_86;
wire ARG__21_n_87;
wire ARG__21_n_88;
wire ARG__21_n_89;
wire ARG__21_n_90;
wire ARG__21_n_91;
wire ARG__21_n_92;
wire ARG__21_n_93;
wire ARG__21_n_94;
wire ARG__21_n_95;
wire ARG__21_n_96;
wire ARG__21_n_97;
wire ARG__21_n_98;
wire ARG__21_n_99;
wire ARG__22_i_1_n_0;
wire ARG__22_n_100;
wire ARG__22_n_101;
wire ARG__22_n_102;
wire ARG__22_n_103;
wire ARG__22_n_104;
wire ARG__22_n_105;
wire ARG__22_n_92;
wire ARG__22_n_93;
wire ARG__22_n_94;
wire ARG__22_n_95;
wire ARG__22_n_96;
wire ARG__22_n_97;
wire ARG__22_n_98;
wire ARG__22_n_99;
wire ARG__23_i_1_n_0;
wire ARG__23_n_100;
wire ARG__23_n_101;
wire ARG__23_n_102;
wire ARG__23_n_103;
wire ARG__23_n_104;
wire ARG__23_n_105;
wire ARG__23_n_76;
wire ARG__23_n_77;
wire ARG__23_n_78;
wire ARG__23_n_79;
wire ARG__23_n_80;
wire ARG__23_n_81;
wire ARG__23_n_82;
wire ARG__23_n_83;
wire ARG__23_n_84;
wire ARG__23_n_85;
wire ARG__23_n_86;
wire ARG__23_n_87;
wire ARG__23_n_88;
wire ARG__23_n_89;
wire ARG__23_n_90;
wire ARG__23_n_91;
wire ARG__23_n_92;
wire ARG__23_n_93;
wire ARG__23_n_94;
wire ARG__23_n_95;
wire ARG__23_n_96;
wire ARG__23_n_97;
wire ARG__23_n_98;
wire ARG__23_n_99;
wire ARG__24_i_1_n_0;
wire ARG__24_n_100;
wire ARG__24_n_101;
wire ARG__24_n_102;
wire ARG__24_n_103;
wire ARG__24_n_104;
wire ARG__24_n_105;
wire ARG__24_n_92;
wire ARG__24_n_93;
wire ARG__24_n_94;
wire ARG__24_n_95;
wire ARG__24_n_96;
wire ARG__24_n_97;
wire ARG__24_n_98;
wire ARG__24_n_99;
wire ARG__25_i_1_n_0;
wire ARG__25_n_100;
wire ARG__25_n_101;
wire ARG__25_n_102;
wire ARG__25_n_103;
wire ARG__25_n_104;
wire ARG__25_n_105;
wire ARG__25_n_76;
wire ARG__25_n_77;
wire ARG__25_n_78;
wire ARG__25_n_79;
wire ARG__25_n_80;
wire ARG__25_n_81;
wire ARG__25_n_82;
wire ARG__25_n_83;
wire ARG__25_n_84;
wire ARG__25_n_85;
wire ARG__25_n_86;
wire ARG__25_n_87;
wire ARG__25_n_88;
wire ARG__25_n_89;
wire ARG__25_n_90;
wire ARG__25_n_91;
wire ARG__25_n_92;
wire ARG__25_n_93;
wire ARG__25_n_94;
wire ARG__25_n_95;
wire ARG__25_n_96;
wire ARG__25_n_97;
wire ARG__25_n_98;
wire ARG__25_n_99;
wire ARG__26_i_1_n_0;
wire ARG__26_n_100;
wire ARG__26_n_101;
wire ARG__26_n_102;
wire ARG__26_n_103;
wire ARG__26_n_104;
wire ARG__26_n_105;
wire ARG__26_n_92;
wire ARG__26_n_93;
wire ARG__26_n_94;
wire ARG__26_n_95;
wire ARG__26_n_96;
wire ARG__26_n_97;
wire ARG__26_n_98;
wire ARG__26_n_99;
wire ARG__27_i_1_n_0;
wire ARG__27_n_100;
wire ARG__27_n_101;
wire ARG__27_n_102;
wire ARG__27_n_103;
wire ARG__27_n_104;
wire ARG__27_n_105;
wire ARG__27_n_76;
wire ARG__27_n_77;
wire ARG__27_n_78;
wire ARG__27_n_79;
wire ARG__27_n_80;
wire ARG__27_n_81;
wire ARG__27_n_82;
wire ARG__27_n_83;
wire ARG__27_n_84;
wire ARG__27_n_85;
wire ARG__27_n_86;
wire ARG__27_n_87;
wire ARG__27_n_88;
wire ARG__27_n_89;
wire ARG__27_n_90;
wire ARG__27_n_91;
wire ARG__27_n_92;
wire ARG__27_n_93;
wire ARG__27_n_94;
wire ARG__27_n_95;
wire ARG__27_n_96;
wire ARG__27_n_97;
wire ARG__27_n_98;
wire ARG__27_n_99;
wire ARG__28_i_1_n_0;
wire ARG__28_n_100;
wire ARG__28_n_101;
wire ARG__28_n_102;
wire ARG__28_n_103;
wire ARG__28_n_104;
wire ARG__28_n_105;
wire ARG__28_n_92;
wire ARG__28_n_93;
wire ARG__28_n_94;
wire ARG__28_n_95;
wire ARG__28_n_96;
wire ARG__28_n_97;
wire ARG__28_n_98;
wire ARG__28_n_99;
wire ARG__29_i_1_n_0;
wire ARG__29_n_100;
wire ARG__29_n_101;
wire ARG__29_n_102;
wire ARG__29_n_103;
wire ARG__29_n_104;
wire ARG__29_n_105;
wire ARG__29_n_76;
wire ARG__29_n_77;
wire ARG__29_n_78;
wire ARG__29_n_79;
wire ARG__29_n_80;
wire ARG__29_n_81;
wire ARG__29_n_82;
wire ARG__29_n_83;
wire ARG__29_n_84;
wire ARG__29_n_85;
wire ARG__29_n_86;
wire ARG__29_n_87;
wire ARG__29_n_88;
wire ARG__29_n_89;
wire ARG__29_n_90;
wire ARG__29_n_91;
wire ARG__29_n_92;
wire ARG__29_n_93;
wire ARG__29_n_94;
wire ARG__29_n_95;
wire ARG__29_n_96;
wire ARG__29_n_97;
wire ARG__29_n_98;
wire ARG__29_n_99;
wire ARG__2_i_1_n_0;
wire ARG__2_n_100;
wire ARG__2_n_101;
wire ARG__2_n_102;
wire ARG__2_n_103;
wire ARG__2_n_104;
wire ARG__2_n_105;
wire ARG__2_n_92;
wire ARG__2_n_93;
wire ARG__2_n_94;
wire ARG__2_n_95;
wire ARG__2_n_96;
wire ARG__2_n_97;
wire ARG__2_n_98;
wire ARG__2_n_99;
wire ARG__30_i_1_n_0;
wire ARG__30_n_100;
wire ARG__30_n_101;
wire ARG__30_n_102;
wire ARG__30_n_103;
wire ARG__30_n_104;
wire ARG__30_n_105;
wire ARG__30_n_92;
wire ARG__30_n_93;
wire ARG__30_n_94;
wire ARG__30_n_95;
wire ARG__30_n_96;
wire ARG__30_n_97;
wire ARG__30_n_98;
wire ARG__30_n_99;
wire [32:17]ARG__31;
wire ARG__3_i_1_n_0;
wire ARG__3_n_100;
wire ARG__3_n_101;
wire ARG__3_n_102;
wire ARG__3_n_103;
wire ARG__3_n_104;
wire ARG__3_n_105;
wire ARG__3_n_76;
wire ARG__3_n_77;
wire ARG__3_n_78;
wire ARG__3_n_79;
wire ARG__3_n_80;
wire ARG__3_n_81;
wire ARG__3_n_82;
wire ARG__3_n_83;
wire ARG__3_n_84;
wire ARG__3_n_85;
wire ARG__3_n_86;
wire ARG__3_n_87;
wire ARG__3_n_88;
wire ARG__3_n_89;
wire ARG__3_n_90;
wire ARG__3_n_91;
wire ARG__3_n_92;
wire ARG__3_n_93;
wire ARG__3_n_94;
wire ARG__3_n_95;
wire ARG__3_n_96;
wire ARG__3_n_97;
wire ARG__3_n_98;
wire ARG__3_n_99;
wire ARG__4_i_1_n_0;
wire ARG__4_n_100;
wire ARG__4_n_101;
wire ARG__4_n_102;
wire ARG__4_n_103;
wire ARG__4_n_104;
wire ARG__4_n_105;
wire ARG__4_n_92;
wire ARG__4_n_93;
wire ARG__4_n_94;
wire ARG__4_n_95;
wire ARG__4_n_96;
wire ARG__4_n_97;
wire ARG__4_n_98;
wire ARG__4_n_99;
wire ARG__5_i_1_n_0;
wire ARG__5_n_100;
wire ARG__5_n_101;
wire ARG__5_n_102;
wire ARG__5_n_103;
wire ARG__5_n_104;
wire ARG__5_n_105;
wire ARG__5_n_76;
wire ARG__5_n_77;
wire ARG__5_n_78;
wire ARG__5_n_79;
wire ARG__5_n_80;
wire ARG__5_n_81;
wire ARG__5_n_82;
wire ARG__5_n_83;
wire ARG__5_n_84;
wire ARG__5_n_85;
wire ARG__5_n_86;
wire ARG__5_n_87;
wire ARG__5_n_88;
wire ARG__5_n_89;
wire ARG__5_n_90;
wire ARG__5_n_91;
wire ARG__5_n_92;
wire ARG__5_n_93;
wire ARG__5_n_94;
wire ARG__5_n_95;
wire ARG__5_n_96;
wire ARG__5_n_97;
wire ARG__5_n_98;
wire ARG__5_n_99;
wire ARG__6_i_1_n_0;
wire ARG__6_n_100;
wire ARG__6_n_101;
wire ARG__6_n_102;
wire ARG__6_n_103;
wire ARG__6_n_104;
wire ARG__6_n_105;
wire ARG__6_n_92;
wire ARG__6_n_93;
wire ARG__6_n_94;
wire ARG__6_n_95;
wire ARG__6_n_96;
wire ARG__6_n_97;
wire ARG__6_n_98;
wire ARG__6_n_99;
wire ARG__7_i_1_n_0;
wire ARG__7_n_100;
wire ARG__7_n_101;
wire ARG__7_n_102;
wire ARG__7_n_103;
wire ARG__7_n_104;
wire ARG__7_n_105;
wire ARG__7_n_76;
wire ARG__7_n_77;
wire ARG__7_n_78;
wire ARG__7_n_79;
wire ARG__7_n_80;
wire ARG__7_n_81;
wire ARG__7_n_82;
wire ARG__7_n_83;
wire ARG__7_n_84;
wire ARG__7_n_85;
wire ARG__7_n_86;
wire ARG__7_n_87;
wire ARG__7_n_88;
wire ARG__7_n_89;
wire ARG__7_n_90;
wire ARG__7_n_91;
wire ARG__7_n_92;
wire ARG__7_n_93;
wire ARG__7_n_94;
wire ARG__7_n_95;
wire ARG__7_n_96;
wire ARG__7_n_97;
wire ARG__7_n_98;
wire ARG__7_n_99;
wire ARG__8_i_1_n_0;
wire ARG__8_n_100;
wire ARG__8_n_101;
wire ARG__8_n_102;
wire ARG__8_n_103;
wire ARG__8_n_104;
wire ARG__8_n_105;
wire ARG__8_n_92;
wire ARG__8_n_93;
wire ARG__8_n_94;
wire ARG__8_n_95;
wire ARG__8_n_96;
wire ARG__8_n_97;
wire ARG__8_n_98;
wire ARG__8_n_99;
wire ARG__9_i_1_n_0;
wire ARG__9_n_100;
wire ARG__9_n_101;
wire ARG__9_n_102;
wire ARG__9_n_103;
wire ARG__9_n_104;
wire ARG__9_n_105;
wire ARG__9_n_76;
wire ARG__9_n_77;
wire ARG__9_n_78;
wire ARG__9_n_79;
wire ARG__9_n_80;
wire ARG__9_n_81;
wire ARG__9_n_82;
wire ARG__9_n_83;
wire ARG__9_n_84;
wire ARG__9_n_85;
wire ARG__9_n_86;
wire ARG__9_n_87;
wire ARG__9_n_88;
wire ARG__9_n_89;
wire ARG__9_n_90;
wire ARG__9_n_91;
wire ARG__9_n_92;
wire ARG__9_n_93;
wire ARG__9_n_94;
wire ARG__9_n_95;
wire ARG__9_n_96;
wire ARG__9_n_97;
wire ARG__9_n_98;
wire ARG__9_n_99;
wire ARG_carry__0_i_2_n_0;
wire ARG_carry__0_i_3_n_0;
wire ARG_carry__0_i_4_n_0;
wire ARG_carry__0_n_0;
wire ARG_carry__0_n_1;
wire ARG_carry__0_n_2;
wire ARG_carry__0_n_3;
wire ARG_carry__1_i_1_n_0;
wire ARG_carry__1_i_2_n_0;
wire ARG_carry__1_i_3_n_0;
wire ARG_carry__1_i_4_n_0;
wire ARG_carry__1_n_0;
wire ARG_carry__1_n_1;
wire ARG_carry__1_n_2;
wire ARG_carry__1_n_3;
wire ARG_carry__2_i_1_n_0;
wire ARG_carry__2_i_2_n_0;
wire ARG_carry__2_i_3_n_0;
wire ARG_carry__2_i_4_n_0;
wire ARG_carry__2_n_0;
wire ARG_carry__2_n_1;
wire ARG_carry__2_n_2;
wire ARG_carry__2_n_3;
wire ARG_carry__3_i_1_n_0;
wire ARG_carry__3_n_3;
wire ARG_carry_n_0;
wire ARG_carry_n_1;
wire ARG_carry_n_2;
wire ARG_carry_n_3;
wire ARG_i_1_n_0;
wire ARG_n_100;
wire ARG_n_101;
wire ARG_n_102;
wire ARG_n_103;
wire ARG_n_104;
wire ARG_n_105;
wire ARG_n_92;
wire ARG_n_93;
wire ARG_n_94;
wire ARG_n_95;
wire ARG_n_96;
wire ARG_n_97;
wire ARG_n_98;
wire ARG_n_99;
wire [0:0]DI;
wire IPCORE_CLK;
wire [14:0]Q;
wire [15:0]RESIZE15;
wire [15:0]RESIZE16;
wire [15:0]RESIZE18;
wire [15:0]RESIZE20;
wire [15:0]RESIZE22;
wire [15:0]RESIZE24;
wire [15:0]RESIZE26;
wire [15:0]RESIZE28;
wire [15:0]RESIZE30;
wire [15:0]RESIZE32;
wire [15:0]RESIZE34;
wire [15:0]RESIZE36;
wire [15:0]RESIZE38;
wire [15:0]RESIZE40;
wire [15:0]RESIZE42;
wire [15:0]RESIZE44;
wire [3:0]S;
wire add_temp_14__0_carry__0_i_1_n_0;
wire add_temp_14__0_carry__0_i_2_n_0;
wire add_temp_14__0_carry__0_i_3_n_0;
wire add_temp_14__0_carry__0_i_4_n_0;
wire add_temp_14__0_carry__0_i_5_n_0;
wire add_temp_14__0_carry__0_i_6_n_0;
wire add_temp_14__0_carry__0_i_7_n_0;
wire add_temp_14__0_carry__0_i_8_n_0;
wire add_temp_14__0_carry__0_n_0;
wire add_temp_14__0_carry__0_n_1;
wire add_temp_14__0_carry__0_n_2;
wire add_temp_14__0_carry__0_n_3;
wire add_temp_14__0_carry__0_n_4;
wire add_temp_14__0_carry__0_n_5;
wire add_temp_14__0_carry__0_n_6;
wire add_temp_14__0_carry__0_n_7;
wire add_temp_14__0_carry__1_i_1_n_0;
wire add_temp_14__0_carry__1_i_2_n_0;
wire add_temp_14__0_carry__1_i_3_n_0;
wire add_temp_14__0_carry__1_i_4_n_0;
wire add_temp_14__0_carry__1_i_5_n_0;
wire add_temp_14__0_carry__1_i_6_n_0;
wire add_temp_14__0_carry__1_i_7_n_0;
wire add_temp_14__0_carry__1_i_8_n_0;
wire add_temp_14__0_carry__1_n_0;
wire add_temp_14__0_carry__1_n_1;
wire add_temp_14__0_carry__1_n_2;
wire add_temp_14__0_carry__1_n_3;
wire add_temp_14__0_carry__1_n_4;
wire add_temp_14__0_carry__1_n_5;
wire add_temp_14__0_carry__1_n_6;
wire add_temp_14__0_carry__1_n_7;
wire add_temp_14__0_carry__2_i_1_n_0;
wire add_temp_14__0_carry__2_i_2_n_0;
wire add_temp_14__0_carry__2_i_3_n_0;
wire add_temp_14__0_carry__2_i_4_n_0;
wire add_temp_14__0_carry__2_i_5_n_0;
wire add_temp_14__0_carry__2_i_6_n_0;
wire add_temp_14__0_carry__2_i_7_n_0;
wire add_temp_14__0_carry__2_n_1;
wire add_temp_14__0_carry__2_n_2;
wire add_temp_14__0_carry__2_n_3;
wire add_temp_14__0_carry__2_n_4;
wire add_temp_14__0_carry__2_n_5;
wire add_temp_14__0_carry__2_n_6;
wire add_temp_14__0_carry__2_n_7;
wire add_temp_14__0_carry_i_1_n_0;
wire add_temp_14__0_carry_i_2_n_0;
wire add_temp_14__0_carry_i_3_n_0;
wire add_temp_14__0_carry_i_4_n_0;
wire add_temp_14__0_carry_i_5_n_0;
wire add_temp_14__0_carry_i_6_n_0;
wire add_temp_14__0_carry_i_7_n_0;
wire add_temp_14__0_carry_n_0;
wire add_temp_14__0_carry_n_1;
wire add_temp_14__0_carry_n_2;
wire add_temp_14__0_carry_n_3;
wire add_temp_14__0_carry_n_4;
wire add_temp_14__0_carry_n_5;
wire add_temp_14__0_carry_n_6;
wire add_temp_14__0_carry_n_7;
wire add_temp_14__138_carry__0_i_1_n_0;
wire add_temp_14__138_carry__0_i_2_n_0;
wire add_temp_14__138_carry__0_i_3_n_0;
wire add_temp_14__138_carry__0_i_4_n_0;
wire add_temp_14__138_carry__0_i_5_n_0;
wire add_temp_14__138_carry__0_i_6_n_0;
wire add_temp_14__138_carry__0_i_7_n_0;
wire add_temp_14__138_carry__0_i_8_n_0;
wire add_temp_14__138_carry__0_n_0;
wire add_temp_14__138_carry__0_n_1;
wire add_temp_14__138_carry__0_n_2;
wire add_temp_14__138_carry__0_n_3;
wire add_temp_14__138_carry__0_n_4;
wire add_temp_14__138_carry__0_n_5;
wire add_temp_14__138_carry__0_n_6;
wire add_temp_14__138_carry__0_n_7;
wire add_temp_14__138_carry__1_i_1_n_0;
wire add_temp_14__138_carry__1_i_2_n_0;
wire add_temp_14__138_carry__1_i_3_n_0;
wire add_temp_14__138_carry__1_i_4_n_0;
wire add_temp_14__138_carry__1_i_5_n_0;
wire add_temp_14__138_carry__1_i_6_n_0;
wire add_temp_14__138_carry__1_i_7_n_0;
wire add_temp_14__138_carry__1_i_8_n_0;
wire add_temp_14__138_carry__1_n_0;
wire add_temp_14__138_carry__1_n_1;
wire add_temp_14__138_carry__1_n_2;
wire add_temp_14__138_carry__1_n_3;
wire add_temp_14__138_carry__1_n_4;
wire add_temp_14__138_carry__1_n_5;
wire add_temp_14__138_carry__1_n_6;
wire add_temp_14__138_carry__1_n_7;
wire add_temp_14__138_carry__2_i_1_n_0;
wire add_temp_14__138_carry__2_i_2_n_0;
wire add_temp_14__138_carry__2_i_3_n_0;
wire add_temp_14__138_carry__2_i_4_n_0;
wire add_temp_14__138_carry__2_i_5_n_0;
wire add_temp_14__138_carry__2_i_6_n_0;
wire add_temp_14__138_carry__2_i_7_n_0;
wire add_temp_14__138_carry__2_n_1;
wire add_temp_14__138_carry__2_n_2;
wire add_temp_14__138_carry__2_n_3;
wire add_temp_14__138_carry__2_n_4;
wire add_temp_14__138_carry__2_n_5;
wire add_temp_14__138_carry__2_n_6;
wire add_temp_14__138_carry__2_n_7;
wire add_temp_14__138_carry_i_1_n_0;
wire add_temp_14__138_carry_i_2_n_0;
wire add_temp_14__138_carry_i_3_n_0;
wire add_temp_14__138_carry_i_4_n_0;
wire add_temp_14__138_carry_i_5_n_0;
wire add_temp_14__138_carry_i_6_n_0;
wire add_temp_14__138_carry_i_7_n_0;
wire add_temp_14__138_carry_n_0;
wire add_temp_14__138_carry_n_1;
wire add_temp_14__138_carry_n_2;
wire add_temp_14__138_carry_n_3;
wire add_temp_14__138_carry_n_4;
wire add_temp_14__138_carry_n_5;
wire add_temp_14__138_carry_n_6;
wire add_temp_14__138_carry_n_7;
wire add_temp_14__184_carry__0_i_1_n_0;
wire add_temp_14__184_carry__0_i_2_n_0;
wire add_temp_14__184_carry__0_i_3_n_0;
wire add_temp_14__184_carry__0_i_4_n_0;
wire add_temp_14__184_carry__0_i_5_n_0;
wire add_temp_14__184_carry__0_i_6_n_0;
wire add_temp_14__184_carry__0_i_7_n_0;
wire add_temp_14__184_carry__0_i_8_n_0;
wire add_temp_14__184_carry__0_n_0;
wire add_temp_14__184_carry__0_n_1;
wire add_temp_14__184_carry__0_n_2;
wire add_temp_14__184_carry__0_n_3;
wire add_temp_14__184_carry__0_n_4;
wire add_temp_14__184_carry__0_n_5;
wire add_temp_14__184_carry__0_n_6;
wire add_temp_14__184_carry__0_n_7;
wire add_temp_14__184_carry__1_i_1_n_0;
wire add_temp_14__184_carry__1_i_2_n_0;
wire add_temp_14__184_carry__1_i_3_n_0;
wire add_temp_14__184_carry__1_i_4_n_0;
wire add_temp_14__184_carry__1_i_5_n_0;
wire add_temp_14__184_carry__1_i_6_n_0;
wire add_temp_14__184_carry__1_i_7_n_0;
wire add_temp_14__184_carry__1_i_8_n_0;
wire add_temp_14__184_carry__1_n_0;
wire add_temp_14__184_carry__1_n_1;
wire add_temp_14__184_carry__1_n_2;
wire add_temp_14__184_carry__1_n_3;
wire add_temp_14__184_carry__1_n_4;
wire add_temp_14__184_carry__1_n_5;
wire add_temp_14__184_carry__1_n_6;
wire add_temp_14__184_carry__1_n_7;
wire add_temp_14__184_carry__2_i_1_n_0;
wire add_temp_14__184_carry__2_i_2_n_0;
wire add_temp_14__184_carry__2_i_3_n_0;
wire add_temp_14__184_carry__2_i_4_n_0;
wire add_temp_14__184_carry__2_i_5_n_0;
wire add_temp_14__184_carry__2_i_6_n_0;
wire add_temp_14__184_carry__2_i_7_n_0;
wire add_temp_14__184_carry__2_n_1;
wire add_temp_14__184_carry__2_n_2;
wire add_temp_14__184_carry__2_n_3;
wire add_temp_14__184_carry__2_n_4;
wire add_temp_14__184_carry__2_n_5;
wire add_temp_14__184_carry__2_n_6;
wire add_temp_14__184_carry__2_n_7;
wire add_temp_14__184_carry_i_1_n_0;
wire add_temp_14__184_carry_i_2_n_0;
wire add_temp_14__184_carry_i_3_n_0;
wire add_temp_14__184_carry_i_4_n_0;
wire add_temp_14__184_carry_i_5_n_0;
wire add_temp_14__184_carry_i_6_n_0;
wire add_temp_14__184_carry_i_7_n_0;
wire add_temp_14__184_carry_n_0;
wire add_temp_14__184_carry_n_1;
wire add_temp_14__184_carry_n_2;
wire add_temp_14__184_carry_n_3;
wire add_temp_14__184_carry_n_4;
wire add_temp_14__184_carry_n_5;
wire add_temp_14__184_carry_n_6;
wire add_temp_14__184_carry_n_7;
wire add_temp_14__230_carry__0_i_1_n_0;
wire add_temp_14__230_carry__0_i_2_n_0;
wire add_temp_14__230_carry__0_i_3_n_0;
wire add_temp_14__230_carry__0_i_4_n_0;
wire add_temp_14__230_carry__0_i_5_n_0;
wire add_temp_14__230_carry__0_i_6_n_0;
wire add_temp_14__230_carry__0_i_7_n_0;
wire add_temp_14__230_carry__0_i_8_n_0;
wire add_temp_14__230_carry__0_n_0;
wire add_temp_14__230_carry__0_n_1;
wire add_temp_14__230_carry__0_n_2;
wire add_temp_14__230_carry__0_n_3;
wire add_temp_14__230_carry__0_n_4;
wire add_temp_14__230_carry__0_n_5;
wire add_temp_14__230_carry__0_n_6;
wire add_temp_14__230_carry__0_n_7;
wire add_temp_14__230_carry__1_i_1_n_0;
wire add_temp_14__230_carry__1_i_2_n_0;
wire add_temp_14__230_carry__1_i_3_n_0;
wire add_temp_14__230_carry__1_i_4_n_0;
wire add_temp_14__230_carry__1_i_5_n_0;
wire add_temp_14__230_carry__1_i_6_n_0;
wire add_temp_14__230_carry__1_i_7_n_0;
wire add_temp_14__230_carry__1_i_8_n_0;
wire add_temp_14__230_carry__1_n_0;
wire add_temp_14__230_carry__1_n_1;
wire add_temp_14__230_carry__1_n_2;
wire add_temp_14__230_carry__1_n_3;
wire add_temp_14__230_carry__1_n_4;
wire add_temp_14__230_carry__1_n_5;
wire add_temp_14__230_carry__1_n_6;
wire add_temp_14__230_carry__1_n_7;
wire add_temp_14__230_carry__2_i_1_n_0;
wire add_temp_14__230_carry__2_i_2_n_0;
wire add_temp_14__230_carry__2_i_3_n_0;
wire add_temp_14__230_carry__2_i_4_n_0;
wire add_temp_14__230_carry__2_i_5_n_0;
wire add_temp_14__230_carry__2_i_6_n_0;
wire add_temp_14__230_carry__2_i_7_n_0;
wire add_temp_14__230_carry__2_n_1;
wire add_temp_14__230_carry__2_n_2;
wire add_temp_14__230_carry__2_n_3;
wire add_temp_14__230_carry__2_n_4;
wire add_temp_14__230_carry__2_n_5;
wire add_temp_14__230_carry__2_n_6;
wire add_temp_14__230_carry__2_n_7;
wire add_temp_14__230_carry_i_1_n_0;
wire add_temp_14__230_carry_i_2_n_0;
wire add_temp_14__230_carry_i_3_n_0;
wire add_temp_14__230_carry_i_4_n_0;
wire add_temp_14__230_carry_i_5_n_0;
wire add_temp_14__230_carry_i_6_n_0;
wire add_temp_14__230_carry_i_7_n_0;
wire add_temp_14__230_carry_n_0;
wire add_temp_14__230_carry_n_1;
wire add_temp_14__230_carry_n_2;
wire add_temp_14__230_carry_n_3;
wire add_temp_14__230_carry_n_4;
wire add_temp_14__230_carry_n_5;
wire add_temp_14__230_carry_n_6;
wire add_temp_14__230_carry_n_7;
wire add_temp_14__278_carry__0_i_10_n_0;
wire add_temp_14__278_carry__0_i_11_n_0;
wire add_temp_14__278_carry__0_i_12_n_0;
wire add_temp_14__278_carry__0_i_1_n_0;
wire add_temp_14__278_carry__0_i_2_n_0;
wire add_temp_14__278_carry__0_i_3_n_0;
wire add_temp_14__278_carry__0_i_4_n_0;
wire add_temp_14__278_carry__0_i_5_n_0;
wire add_temp_14__278_carry__0_i_6_n_0;
wire add_temp_14__278_carry__0_i_7_n_0;
wire add_temp_14__278_carry__0_i_8_n_0;
wire add_temp_14__278_carry__0_i_9_n_0;
wire add_temp_14__278_carry__0_n_0;
wire add_temp_14__278_carry__0_n_1;
wire add_temp_14__278_carry__0_n_2;
wire add_temp_14__278_carry__0_n_3;
wire add_temp_14__278_carry__1_i_10_n_0;
wire add_temp_14__278_carry__1_i_11_n_0;
wire add_temp_14__278_carry__1_i_12_n_0;
wire add_temp_14__278_carry__1_i_1_n_0;
wire add_temp_14__278_carry__1_i_2_n_0;
wire add_temp_14__278_carry__1_i_3_n_0;
wire add_temp_14__278_carry__1_i_4_n_0;
wire add_temp_14__278_carry__1_i_5_n_0;
wire add_temp_14__278_carry__1_i_6_n_0;
wire add_temp_14__278_carry__1_i_7_n_0;
wire add_temp_14__278_carry__1_i_8_n_0;
wire add_temp_14__278_carry__1_i_9_n_0;
wire add_temp_14__278_carry__1_n_0;
wire add_temp_14__278_carry__1_n_1;
wire add_temp_14__278_carry__1_n_2;
wire add_temp_14__278_carry__1_n_3;
wire add_temp_14__278_carry__2_i_10_n_0;
wire add_temp_14__278_carry__2_i_11_n_0;
wire add_temp_14__278_carry__2_i_1_n_0;
wire add_temp_14__278_carry__2_i_2_n_0;
wire add_temp_14__278_carry__2_i_3_n_0;
wire add_temp_14__278_carry__2_i_4_n_0;
wire add_temp_14__278_carry__2_i_5_n_0;
wire add_temp_14__278_carry__2_i_6_n_0;
wire add_temp_14__278_carry__2_i_7_n_0;
wire add_temp_14__278_carry__2_i_8_n_0;
wire add_temp_14__278_carry__2_i_9_n_0;
wire add_temp_14__278_carry__2_n_1;
wire add_temp_14__278_carry__2_n_2;
wire add_temp_14__278_carry__2_n_3;
wire add_temp_14__278_carry_i_10_n_0;
wire add_temp_14__278_carry_i_1_n_0;
wire add_temp_14__278_carry_i_2_n_0;
wire add_temp_14__278_carry_i_3_n_0;
wire add_temp_14__278_carry_i_4_n_0;
wire add_temp_14__278_carry_i_5_n_0;
wire add_temp_14__278_carry_i_6_n_0;
wire add_temp_14__278_carry_i_7_n_0;
wire add_temp_14__278_carry_i_8_n_0;
wire add_temp_14__278_carry_i_9_n_0;
wire add_temp_14__278_carry_n_0;
wire add_temp_14__278_carry_n_1;
wire add_temp_14__278_carry_n_2;
wire add_temp_14__278_carry_n_3;
wire add_temp_14__46_carry__0_i_1_n_0;
wire add_temp_14__46_carry__0_i_2_n_0;
wire add_temp_14__46_carry__0_i_3_n_0;
wire add_temp_14__46_carry__0_i_4_n_0;
wire add_temp_14__46_carry__0_i_5_n_0;
wire add_temp_14__46_carry__0_i_6_n_0;
wire add_temp_14__46_carry__0_i_7_n_0;
wire add_temp_14__46_carry__0_i_8_n_0;
wire add_temp_14__46_carry__0_n_0;
wire add_temp_14__46_carry__0_n_1;
wire add_temp_14__46_carry__0_n_2;
wire add_temp_14__46_carry__0_n_3;
wire add_temp_14__46_carry__0_n_4;
wire add_temp_14__46_carry__0_n_5;
wire add_temp_14__46_carry__0_n_6;
wire add_temp_14__46_carry__0_n_7;
wire add_temp_14__46_carry__1_i_1_n_0;
wire add_temp_14__46_carry__1_i_2_n_0;
wire add_temp_14__46_carry__1_i_3_n_0;
wire add_temp_14__46_carry__1_i_4_n_0;
wire add_temp_14__46_carry__1_i_5_n_0;
wire add_temp_14__46_carry__1_i_6_n_0;
wire add_temp_14__46_carry__1_i_7_n_0;
wire add_temp_14__46_carry__1_i_8_n_0;
wire add_temp_14__46_carry__1_n_0;
wire add_temp_14__46_carry__1_n_1;
wire add_temp_14__46_carry__1_n_2;
wire add_temp_14__46_carry__1_n_3;
wire add_temp_14__46_carry__1_n_4;
wire add_temp_14__46_carry__1_n_5;
wire add_temp_14__46_carry__1_n_6;
wire add_temp_14__46_carry__1_n_7;
wire add_temp_14__46_carry__2_i_1_n_0;
wire add_temp_14__46_carry__2_i_2_n_0;
wire add_temp_14__46_carry__2_i_3_n_0;
wire add_temp_14__46_carry__2_i_4_n_0;
wire add_temp_14__46_carry__2_i_5_n_0;
wire add_temp_14__46_carry__2_i_6_n_0;
wire add_temp_14__46_carry__2_i_7_n_0;
wire add_temp_14__46_carry__2_n_1;
wire add_temp_14__46_carry__2_n_2;
wire add_temp_14__46_carry__2_n_3;
wire add_temp_14__46_carry__2_n_4;
wire add_temp_14__46_carry__2_n_5;
wire add_temp_14__46_carry__2_n_6;
wire add_temp_14__46_carry__2_n_7;
wire add_temp_14__46_carry_i_1_n_0;
wire add_temp_14__46_carry_i_2_n_0;
wire add_temp_14__46_carry_i_3_n_0;
wire add_temp_14__46_carry_i_4_n_0;
wire add_temp_14__46_carry_i_5_n_0;
wire add_temp_14__46_carry_i_6_n_0;
wire add_temp_14__46_carry_i_7_n_0;
wire add_temp_14__46_carry_n_0;
wire add_temp_14__46_carry_n_1;
wire add_temp_14__46_carry_n_2;
wire add_temp_14__46_carry_n_3;
wire add_temp_14__46_carry_n_4;
wire add_temp_14__46_carry_n_5;
wire add_temp_14__46_carry_n_6;
wire add_temp_14__46_carry_n_7;
wire add_temp_14__92_carry__0_i_1_n_0;
wire add_temp_14__92_carry__0_i_2_n_0;
wire add_temp_14__92_carry__0_i_3_n_0;
wire add_temp_14__92_carry__0_i_4_n_0;
wire add_temp_14__92_carry__0_i_5_n_0;
wire add_temp_14__92_carry__0_i_6_n_0;
wire add_temp_14__92_carry__0_i_7_n_0;
wire add_temp_14__92_carry__0_i_8_n_0;
wire add_temp_14__92_carry__0_n_0;
wire add_temp_14__92_carry__0_n_1;
wire add_temp_14__92_carry__0_n_2;
wire add_temp_14__92_carry__0_n_3;
wire add_temp_14__92_carry__0_n_4;
wire add_temp_14__92_carry__0_n_5;
wire add_temp_14__92_carry__0_n_6;
wire add_temp_14__92_carry__0_n_7;
wire add_temp_14__92_carry__1_i_1_n_0;
wire add_temp_14__92_carry__1_i_2_n_0;
wire add_temp_14__92_carry__1_i_3_n_0;
wire add_temp_14__92_carry__1_i_4_n_0;
wire add_temp_14__92_carry__1_i_5_n_0;
wire add_temp_14__92_carry__1_i_6_n_0;
wire add_temp_14__92_carry__1_i_7_n_0;
wire add_temp_14__92_carry__1_i_8_n_0;
wire add_temp_14__92_carry__1_n_0;
wire add_temp_14__92_carry__1_n_1;
wire add_temp_14__92_carry__1_n_2;
wire add_temp_14__92_carry__1_n_3;
wire add_temp_14__92_carry__1_n_4;
wire add_temp_14__92_carry__1_n_5;
wire add_temp_14__92_carry__1_n_6;
wire add_temp_14__92_carry__1_n_7;
wire add_temp_14__92_carry__2_i_1_n_0;
wire add_temp_14__92_carry__2_i_2_n_0;
wire add_temp_14__92_carry__2_i_3_n_0;
wire add_temp_14__92_carry__2_i_4_n_0;
wire add_temp_14__92_carry__2_i_5_n_0;
wire add_temp_14__92_carry__2_i_6_n_0;
wire add_temp_14__92_carry__2_i_7_n_0;
wire add_temp_14__92_carry__2_n_1;
wire add_temp_14__92_carry__2_n_2;
wire add_temp_14__92_carry__2_n_3;
wire add_temp_14__92_carry__2_n_4;
wire add_temp_14__92_carry__2_n_5;
wire add_temp_14__92_carry__2_n_6;
wire add_temp_14__92_carry__2_n_7;
wire add_temp_14__92_carry_i_1_n_0;
wire add_temp_14__92_carry_i_2_n_0;
wire add_temp_14__92_carry_i_3_n_0;
wire add_temp_14__92_carry_i_4_n_0;
wire add_temp_14__92_carry_i_5_n_0;
wire add_temp_14__92_carry_i_6_n_0;
wire add_temp_14__92_carry_i_7_n_0;
wire add_temp_14__92_carry_n_0;
wire add_temp_14__92_carry_n_1;
wire add_temp_14__92_carry_n_2;
wire add_temp_14__92_carry_n_3;
wire add_temp_14__92_carry_n_4;
wire add_temp_14__92_carry_n_5;
wire add_temp_14__92_carry_n_6;
wire add_temp_14__92_carry_n_7;
wire cop_dut_enable;
wire [15:0]\data_pipeline_tmp_reg[0] ;
wire [15:0]\data_pipeline_tmp_reg[10] ;
wire [15:0]\data_pipeline_tmp_reg[11] ;
wire [15:0]\data_pipeline_tmp_reg[12] ;
wire [15:0]\data_pipeline_tmp_reg[13] ;
wire [15:0]\data_pipeline_tmp_reg[14] ;
wire [15:0]\data_pipeline_tmp_reg[1] ;
wire [15:0]\data_pipeline_tmp_reg[2] ;
wire [15:0]\data_pipeline_tmp_reg[3] ;
wire [15:0]\data_pipeline_tmp_reg[4] ;
wire [15:0]\data_pipeline_tmp_reg[5] ;
wire [15:0]\data_pipeline_tmp_reg[6] ;
wire [15:0]\data_pipeline_tmp_reg[7] ;
wire [15:0]\data_pipeline_tmp_reg[8] ;
wire [15:0]\data_pipeline_tmp_reg[9] ;
wire [15:0]filter_sum;
wire [15:0]in;
wire [14:14]\^mul_temp ;
wire [14:14]\^mul_temp_1 ;
wire [14:14]\^mul_temp_10 ;
wire mul_temp_10_n_100;
wire mul_temp_10_n_101;
wire mul_temp_10_n_102;
wire mul_temp_10_n_103;
wire mul_temp_10_n_104;
wire mul_temp_10_n_105;
wire mul_temp_10_n_74;
wire mul_temp_10_n_75;
wire mul_temp_10_n_76;
wire mul_temp_10_n_77;
wire mul_temp_10_n_78;
wire mul_temp_10_n_79;
wire mul_temp_10_n_80;
wire mul_temp_10_n_81;
wire mul_temp_10_n_82;
wire mul_temp_10_n_83;
wire mul_temp_10_n_84;
wire mul_temp_10_n_85;
wire mul_temp_10_n_86;
wire mul_temp_10_n_87;
wire mul_temp_10_n_88;
wire mul_temp_10_n_89;
wire mul_temp_10_n_90;
wire mul_temp_10_n_92;
wire mul_temp_10_n_93;
wire mul_temp_10_n_94;
wire mul_temp_10_n_95;
wire mul_temp_10_n_96;
wire mul_temp_10_n_97;
wire mul_temp_10_n_98;
wire mul_temp_10_n_99;
wire [14:14]\^mul_temp_11 ;
wire mul_temp_11_n_100;
wire mul_temp_11_n_101;
wire mul_temp_11_n_102;
wire mul_temp_11_n_103;
wire mul_temp_11_n_104;
wire mul_temp_11_n_105;
wire mul_temp_11_n_74;
wire mul_temp_11_n_75;
wire mul_temp_11_n_76;
wire mul_temp_11_n_77;
wire mul_temp_11_n_78;
wire mul_temp_11_n_79;
wire mul_temp_11_n_80;
wire mul_temp_11_n_81;
wire mul_temp_11_n_82;
wire mul_temp_11_n_83;
wire mul_temp_11_n_84;
wire mul_temp_11_n_85;
wire mul_temp_11_n_86;
wire mul_temp_11_n_87;
wire mul_temp_11_n_88;
wire mul_temp_11_n_89;
wire mul_temp_11_n_90;
wire mul_temp_11_n_92;
wire mul_temp_11_n_93;
wire mul_temp_11_n_94;
wire mul_temp_11_n_95;
wire mul_temp_11_n_96;
wire mul_temp_11_n_97;
wire mul_temp_11_n_98;
wire mul_temp_11_n_99;
wire [14:14]\^mul_temp_12 ;
wire mul_temp_12_n_100;
wire mul_temp_12_n_101;
wire mul_temp_12_n_102;
wire mul_temp_12_n_103;
wire mul_temp_12_n_104;
wire mul_temp_12_n_105;
wire mul_temp_12_n_74;
wire mul_temp_12_n_75;
wire mul_temp_12_n_76;
wire mul_temp_12_n_77;
wire mul_temp_12_n_78;
wire mul_temp_12_n_79;
wire mul_temp_12_n_80;
wire mul_temp_12_n_81;
wire mul_temp_12_n_82;
wire mul_temp_12_n_83;
wire mul_temp_12_n_84;
wire mul_temp_12_n_85;
wire mul_temp_12_n_86;
wire mul_temp_12_n_87;
wire mul_temp_12_n_88;
wire mul_temp_12_n_89;
wire mul_temp_12_n_90;
wire mul_temp_12_n_92;
wire mul_temp_12_n_93;
wire mul_temp_12_n_94;
wire mul_temp_12_n_95;
wire mul_temp_12_n_96;
wire mul_temp_12_n_97;
wire mul_temp_12_n_98;
wire mul_temp_12_n_99;
wire [14:14]\^mul_temp_13 ;
wire mul_temp_13_n_100;
wire mul_temp_13_n_101;
wire mul_temp_13_n_102;
wire mul_temp_13_n_103;
wire mul_temp_13_n_104;
wire mul_temp_13_n_105;
wire mul_temp_13_n_74;
wire mul_temp_13_n_75;
wire mul_temp_13_n_76;
wire mul_temp_13_n_77;
wire mul_temp_13_n_78;
wire mul_temp_13_n_79;
wire mul_temp_13_n_80;
wire mul_temp_13_n_81;
wire mul_temp_13_n_82;
wire mul_temp_13_n_83;
wire mul_temp_13_n_84;
wire mul_temp_13_n_85;
wire mul_temp_13_n_86;
wire mul_temp_13_n_87;
wire mul_temp_13_n_88;
wire mul_temp_13_n_89;
wire mul_temp_13_n_90;
wire mul_temp_13_n_92;
wire mul_temp_13_n_93;
wire mul_temp_13_n_94;
wire mul_temp_13_n_95;
wire mul_temp_13_n_96;
wire mul_temp_13_n_97;
wire mul_temp_13_n_98;
wire mul_temp_13_n_99;
wire [14:14]\^mul_temp_14 ;
wire mul_temp_14_n_100;
wire mul_temp_14_n_101;
wire mul_temp_14_n_102;
wire mul_temp_14_n_103;
wire mul_temp_14_n_104;
wire mul_temp_14_n_105;
wire mul_temp_14_n_74;
wire mul_temp_14_n_75;
wire mul_temp_14_n_76;
wire mul_temp_14_n_77;
wire mul_temp_14_n_78;
wire mul_temp_14_n_79;
wire mul_temp_14_n_80;
wire mul_temp_14_n_81;
wire mul_temp_14_n_82;
wire mul_temp_14_n_83;
wire mul_temp_14_n_84;
wire mul_temp_14_n_85;
wire mul_temp_14_n_86;
wire mul_temp_14_n_87;
wire mul_temp_14_n_88;
wire mul_temp_14_n_89;
wire mul_temp_14_n_90;
wire mul_temp_14_n_92;
wire mul_temp_14_n_93;
wire mul_temp_14_n_94;
wire mul_temp_14_n_95;
wire mul_temp_14_n_96;
wire mul_temp_14_n_97;
wire mul_temp_14_n_98;
wire mul_temp_14_n_99;
wire [14:14]\^mul_temp_15 ;
wire mul_temp_15_n_100;
wire mul_temp_15_n_101;
wire mul_temp_15_n_102;
wire mul_temp_15_n_103;
wire mul_temp_15_n_104;
wire mul_temp_15_n_105;
wire mul_temp_15_n_74;
wire mul_temp_15_n_75;
wire mul_temp_15_n_76;
wire mul_temp_15_n_77;
wire mul_temp_15_n_78;
wire mul_temp_15_n_79;
wire mul_temp_15_n_80;
wire mul_temp_15_n_81;
wire mul_temp_15_n_82;
wire mul_temp_15_n_83;
wire mul_temp_15_n_84;
wire mul_temp_15_n_85;
wire mul_temp_15_n_86;
wire mul_temp_15_n_87;
wire mul_temp_15_n_88;
wire mul_temp_15_n_89;
wire mul_temp_15_n_90;
wire mul_temp_15_n_92;
wire mul_temp_15_n_93;
wire mul_temp_15_n_94;
wire mul_temp_15_n_95;
wire mul_temp_15_n_96;
wire mul_temp_15_n_97;
wire mul_temp_15_n_98;
wire mul_temp_15_n_99;
wire [15:0]mul_temp_16;
wire [14:14]\^mul_temp_17 ;
wire mul_temp_17_n_100;
wire mul_temp_17_n_101;
wire mul_temp_17_n_102;
wire mul_temp_17_n_103;
wire mul_temp_17_n_104;
wire mul_temp_17_n_105;
wire mul_temp_17_n_74;
wire mul_temp_17_n_75;
wire mul_temp_17_n_76;
wire mul_temp_17_n_77;
wire mul_temp_17_n_78;
wire mul_temp_17_n_79;
wire mul_temp_17_n_80;
wire mul_temp_17_n_81;
wire mul_temp_17_n_82;
wire mul_temp_17_n_83;
wire mul_temp_17_n_84;
wire mul_temp_17_n_85;
wire mul_temp_17_n_86;
wire mul_temp_17_n_87;
wire mul_temp_17_n_88;
wire mul_temp_17_n_89;
wire mul_temp_17_n_90;
wire mul_temp_17_n_92;
wire mul_temp_17_n_93;
wire mul_temp_17_n_94;
wire mul_temp_17_n_95;
wire mul_temp_17_n_96;
wire mul_temp_17_n_97;
wire mul_temp_17_n_98;
wire mul_temp_17_n_99;
wire [14:14]\^mul_temp_18 ;
wire mul_temp_18_n_100;
wire mul_temp_18_n_101;
wire mul_temp_18_n_102;
wire mul_temp_18_n_103;
wire mul_temp_18_n_104;
wire mul_temp_18_n_105;
wire mul_temp_18_n_74;
wire mul_temp_18_n_75;
wire mul_temp_18_n_76;
wire mul_temp_18_n_77;
wire mul_temp_18_n_78;
wire mul_temp_18_n_79;
wire mul_temp_18_n_80;
wire mul_temp_18_n_81;
wire mul_temp_18_n_82;
wire mul_temp_18_n_83;
wire mul_temp_18_n_84;
wire mul_temp_18_n_85;
wire mul_temp_18_n_86;
wire mul_temp_18_n_87;
wire mul_temp_18_n_88;
wire mul_temp_18_n_89;
wire mul_temp_18_n_90;
wire mul_temp_18_n_92;
wire mul_temp_18_n_93;
wire mul_temp_18_n_94;
wire mul_temp_18_n_95;
wire mul_temp_18_n_96;
wire mul_temp_18_n_97;
wire mul_temp_18_n_98;
wire mul_temp_18_n_99;
wire [14:14]\^mul_temp_19 ;
wire mul_temp_19_n_100;
wire mul_temp_19_n_101;
wire mul_temp_19_n_102;
wire mul_temp_19_n_103;
wire mul_temp_19_n_104;
wire mul_temp_19_n_105;
wire mul_temp_19_n_74;
wire mul_temp_19_n_75;
wire mul_temp_19_n_76;
wire mul_temp_19_n_77;
wire mul_temp_19_n_78;
wire mul_temp_19_n_79;
wire mul_temp_19_n_80;
wire mul_temp_19_n_81;
wire mul_temp_19_n_82;
wire mul_temp_19_n_83;
wire mul_temp_19_n_84;
wire mul_temp_19_n_85;
wire mul_temp_19_n_86;
wire mul_temp_19_n_87;
wire mul_temp_19_n_88;
wire mul_temp_19_n_89;
wire mul_temp_19_n_90;
wire mul_temp_19_n_92;
wire mul_temp_19_n_93;
wire mul_temp_19_n_94;
wire mul_temp_19_n_95;
wire mul_temp_19_n_96;
wire mul_temp_19_n_97;
wire mul_temp_19_n_98;
wire mul_temp_19_n_99;
wire mul_temp_1_n_100;
wire mul_temp_1_n_101;
wire mul_temp_1_n_102;
wire mul_temp_1_n_103;
wire mul_temp_1_n_104;
wire mul_temp_1_n_105;
wire mul_temp_1_n_74;
wire mul_temp_1_n_75;
wire mul_temp_1_n_76;
wire mul_temp_1_n_77;
wire mul_temp_1_n_78;
wire mul_temp_1_n_79;
wire mul_temp_1_n_80;
wire mul_temp_1_n_81;
wire mul_temp_1_n_82;
wire mul_temp_1_n_83;
wire mul_temp_1_n_84;
wire mul_temp_1_n_85;
wire mul_temp_1_n_86;
wire mul_temp_1_n_87;
wire mul_temp_1_n_88;
wire mul_temp_1_n_89;
wire mul_temp_1_n_90;
wire mul_temp_1_n_92;
wire mul_temp_1_n_93;
wire mul_temp_1_n_94;
wire mul_temp_1_n_95;
wire mul_temp_1_n_96;
wire mul_temp_1_n_97;
wire mul_temp_1_n_98;
wire mul_temp_1_n_99;
wire [14:14]\^mul_temp_2 ;
wire [14:14]\^mul_temp_20 ;
wire mul_temp_20_n_100;
wire mul_temp_20_n_101;
wire mul_temp_20_n_102;
wire mul_temp_20_n_103;
wire mul_temp_20_n_104;
wire mul_temp_20_n_105;
wire mul_temp_20_n_74;
wire mul_temp_20_n_75;
wire mul_temp_20_n_76;
wire mul_temp_20_n_77;
wire mul_temp_20_n_78;
wire mul_temp_20_n_79;
wire mul_temp_20_n_80;
wire mul_temp_20_n_81;
wire mul_temp_20_n_82;
wire mul_temp_20_n_83;
wire mul_temp_20_n_84;
wire mul_temp_20_n_85;
wire mul_temp_20_n_86;
wire mul_temp_20_n_87;
wire mul_temp_20_n_88;
wire mul_temp_20_n_89;
wire mul_temp_20_n_90;
wire mul_temp_20_n_92;
wire mul_temp_20_n_93;
wire mul_temp_20_n_94;
wire mul_temp_20_n_95;
wire mul_temp_20_n_96;
wire mul_temp_20_n_97;
wire mul_temp_20_n_98;
wire mul_temp_20_n_99;
wire [14:14]\^mul_temp_21 ;
wire mul_temp_21_n_100;
wire mul_temp_21_n_101;
wire mul_temp_21_n_102;
wire mul_temp_21_n_103;
wire mul_temp_21_n_104;
wire mul_temp_21_n_105;
wire mul_temp_21_n_74;
wire mul_temp_21_n_75;
wire mul_temp_21_n_76;
wire mul_temp_21_n_77;
wire mul_temp_21_n_78;
wire mul_temp_21_n_79;
wire mul_temp_21_n_80;
wire mul_temp_21_n_81;
wire mul_temp_21_n_82;
wire mul_temp_21_n_83;
wire mul_temp_21_n_84;
wire mul_temp_21_n_85;
wire mul_temp_21_n_86;
wire mul_temp_21_n_87;
wire mul_temp_21_n_88;
wire mul_temp_21_n_89;
wire mul_temp_21_n_90;
wire mul_temp_21_n_92;
wire mul_temp_21_n_93;
wire mul_temp_21_n_94;
wire mul_temp_21_n_95;
wire mul_temp_21_n_96;
wire mul_temp_21_n_97;
wire mul_temp_21_n_98;
wire mul_temp_21_n_99;
wire [14:14]\^mul_temp_22 ;
wire mul_temp_22_n_100;
wire mul_temp_22_n_101;
wire mul_temp_22_n_102;
wire mul_temp_22_n_103;
wire mul_temp_22_n_104;
wire mul_temp_22_n_105;
wire mul_temp_22_n_74;
wire mul_temp_22_n_75;
wire mul_temp_22_n_76;
wire mul_temp_22_n_77;
wire mul_temp_22_n_78;
wire mul_temp_22_n_79;
wire mul_temp_22_n_80;
wire mul_temp_22_n_81;
wire mul_temp_22_n_82;
wire mul_temp_22_n_83;
wire mul_temp_22_n_84;
wire mul_temp_22_n_85;
wire mul_temp_22_n_86;
wire mul_temp_22_n_87;
wire mul_temp_22_n_88;
wire mul_temp_22_n_89;
wire mul_temp_22_n_90;
wire mul_temp_22_n_92;
wire mul_temp_22_n_93;
wire mul_temp_22_n_94;
wire mul_temp_22_n_95;
wire mul_temp_22_n_96;
wire mul_temp_22_n_97;
wire mul_temp_22_n_98;
wire mul_temp_22_n_99;
wire [14:14]\^mul_temp_23 ;
wire mul_temp_23_n_100;
wire mul_temp_23_n_101;
wire mul_temp_23_n_102;
wire mul_temp_23_n_103;
wire mul_temp_23_n_104;
wire mul_temp_23_n_105;
wire mul_temp_23_n_74;
wire mul_temp_23_n_75;
wire mul_temp_23_n_76;
wire mul_temp_23_n_77;
wire mul_temp_23_n_78;
wire mul_temp_23_n_79;
wire mul_temp_23_n_80;
wire mul_temp_23_n_81;
wire mul_temp_23_n_82;
wire mul_temp_23_n_83;
wire mul_temp_23_n_84;
wire mul_temp_23_n_85;
wire mul_temp_23_n_86;
wire mul_temp_23_n_87;
wire mul_temp_23_n_88;
wire mul_temp_23_n_89;
wire mul_temp_23_n_90;
wire mul_temp_23_n_92;
wire mul_temp_23_n_93;
wire mul_temp_23_n_94;
wire mul_temp_23_n_95;
wire mul_temp_23_n_96;
wire mul_temp_23_n_97;
wire mul_temp_23_n_98;
wire mul_temp_23_n_99;
wire [14:14]\^mul_temp_24 ;
wire mul_temp_24_n_100;
wire mul_temp_24_n_101;
wire mul_temp_24_n_102;
wire mul_temp_24_n_103;
wire mul_temp_24_n_104;
wire mul_temp_24_n_105;
wire mul_temp_24_n_74;
wire mul_temp_24_n_75;
wire mul_temp_24_n_76;
wire mul_temp_24_n_77;
wire mul_temp_24_n_78;
wire mul_temp_24_n_79;
wire mul_temp_24_n_80;
wire mul_temp_24_n_81;
wire mul_temp_24_n_82;
wire mul_temp_24_n_83;
wire mul_temp_24_n_84;
wire mul_temp_24_n_85;
wire mul_temp_24_n_86;
wire mul_temp_24_n_87;
wire mul_temp_24_n_88;
wire mul_temp_24_n_89;
wire mul_temp_24_n_90;
wire mul_temp_24_n_92;
wire mul_temp_24_n_93;
wire mul_temp_24_n_94;
wire mul_temp_24_n_95;
wire mul_temp_24_n_96;
wire mul_temp_24_n_97;
wire mul_temp_24_n_98;
wire mul_temp_24_n_99;
wire [14:14]\^mul_temp_25 ;
wire mul_temp_25_n_100;
wire mul_temp_25_n_101;
wire mul_temp_25_n_102;
wire mul_temp_25_n_103;
wire mul_temp_25_n_104;
wire mul_temp_25_n_105;
wire mul_temp_25_n_74;
wire mul_temp_25_n_75;
wire mul_temp_25_n_76;
wire mul_temp_25_n_77;
wire mul_temp_25_n_78;
wire mul_temp_25_n_79;
wire mul_temp_25_n_80;
wire mul_temp_25_n_81;
wire mul_temp_25_n_82;
wire mul_temp_25_n_83;
wire mul_temp_25_n_84;
wire mul_temp_25_n_85;
wire mul_temp_25_n_86;
wire mul_temp_25_n_87;
wire mul_temp_25_n_88;
wire mul_temp_25_n_89;
wire mul_temp_25_n_90;
wire mul_temp_25_n_92;
wire mul_temp_25_n_93;
wire mul_temp_25_n_94;
wire mul_temp_25_n_95;
wire mul_temp_25_n_96;
wire mul_temp_25_n_97;
wire mul_temp_25_n_98;
wire mul_temp_25_n_99;
wire [14:14]\^mul_temp_26 ;
wire mul_temp_26_n_100;
wire mul_temp_26_n_101;
wire mul_temp_26_n_102;
wire mul_temp_26_n_103;
wire mul_temp_26_n_104;
wire mul_temp_26_n_105;
wire mul_temp_26_n_74;
wire mul_temp_26_n_75;
wire mul_temp_26_n_76;
wire mul_temp_26_n_77;
wire mul_temp_26_n_78;
wire mul_temp_26_n_79;
wire mul_temp_26_n_80;
wire mul_temp_26_n_81;
wire mul_temp_26_n_82;
wire mul_temp_26_n_83;
wire mul_temp_26_n_84;
wire mul_temp_26_n_85;
wire mul_temp_26_n_86;
wire mul_temp_26_n_87;
wire mul_temp_26_n_88;
wire mul_temp_26_n_89;
wire mul_temp_26_n_90;
wire mul_temp_26_n_92;
wire mul_temp_26_n_93;
wire mul_temp_26_n_94;
wire mul_temp_26_n_95;
wire mul_temp_26_n_96;
wire mul_temp_26_n_97;
wire mul_temp_26_n_98;
wire mul_temp_26_n_99;
wire [14:14]\^mul_temp_27 ;
wire mul_temp_27_n_100;
wire mul_temp_27_n_101;
wire mul_temp_27_n_102;
wire mul_temp_27_n_103;
wire mul_temp_27_n_104;
wire mul_temp_27_n_105;
wire mul_temp_27_n_74;
wire mul_temp_27_n_75;
wire mul_temp_27_n_76;
wire mul_temp_27_n_77;
wire mul_temp_27_n_78;
wire mul_temp_27_n_79;
wire mul_temp_27_n_80;
wire mul_temp_27_n_81;
wire mul_temp_27_n_82;
wire mul_temp_27_n_83;
wire mul_temp_27_n_84;
wire mul_temp_27_n_85;
wire mul_temp_27_n_86;
wire mul_temp_27_n_87;
wire mul_temp_27_n_88;
wire mul_temp_27_n_89;
wire mul_temp_27_n_90;
wire mul_temp_27_n_92;
wire mul_temp_27_n_93;
wire mul_temp_27_n_94;
wire mul_temp_27_n_95;
wire mul_temp_27_n_96;
wire mul_temp_27_n_97;
wire mul_temp_27_n_98;
wire mul_temp_27_n_99;
wire [14:14]\^mul_temp_28 ;
wire mul_temp_28_n_100;
wire mul_temp_28_n_101;
wire mul_temp_28_n_102;
wire mul_temp_28_n_103;
wire mul_temp_28_n_104;
wire mul_temp_28_n_105;
wire mul_temp_28_n_74;
wire mul_temp_28_n_75;
wire mul_temp_28_n_76;
wire mul_temp_28_n_77;
wire mul_temp_28_n_78;
wire mul_temp_28_n_79;
wire mul_temp_28_n_80;
wire mul_temp_28_n_81;
wire mul_temp_28_n_82;
wire mul_temp_28_n_83;
wire mul_temp_28_n_84;
wire mul_temp_28_n_85;
wire mul_temp_28_n_86;
wire mul_temp_28_n_87;
wire mul_temp_28_n_88;
wire mul_temp_28_n_89;
wire mul_temp_28_n_90;
wire mul_temp_28_n_92;
wire mul_temp_28_n_93;
wire mul_temp_28_n_94;
wire mul_temp_28_n_95;
wire mul_temp_28_n_96;
wire mul_temp_28_n_97;
wire mul_temp_28_n_98;
wire mul_temp_28_n_99;
wire [14:14]\^mul_temp_29 ;
wire mul_temp_29_n_100;
wire mul_temp_29_n_101;
wire mul_temp_29_n_102;
wire mul_temp_29_n_103;
wire mul_temp_29_n_104;
wire mul_temp_29_n_105;
wire mul_temp_29_n_74;
wire mul_temp_29_n_75;
wire mul_temp_29_n_76;
wire mul_temp_29_n_77;
wire mul_temp_29_n_78;
wire mul_temp_29_n_79;
wire mul_temp_29_n_80;
wire mul_temp_29_n_81;
wire mul_temp_29_n_82;
wire mul_temp_29_n_83;
wire mul_temp_29_n_84;
wire mul_temp_29_n_85;
wire mul_temp_29_n_86;
wire mul_temp_29_n_87;
wire mul_temp_29_n_88;
wire mul_temp_29_n_89;
wire mul_temp_29_n_90;
wire mul_temp_29_n_92;
wire mul_temp_29_n_93;
wire mul_temp_29_n_94;
wire mul_temp_29_n_95;
wire mul_temp_29_n_96;
wire mul_temp_29_n_97;
wire mul_temp_29_n_98;
wire mul_temp_29_n_99;
wire mul_temp_2_n_100;
wire mul_temp_2_n_101;
wire mul_temp_2_n_102;
wire mul_temp_2_n_103;
wire mul_temp_2_n_104;
wire mul_temp_2_n_105;
wire mul_temp_2_n_74;
wire mul_temp_2_n_75;
wire mul_temp_2_n_76;
wire mul_temp_2_n_77;
wire mul_temp_2_n_78;
wire mul_temp_2_n_79;
wire mul_temp_2_n_80;
wire mul_temp_2_n_81;
wire mul_temp_2_n_82;
wire mul_temp_2_n_83;
wire mul_temp_2_n_84;
wire mul_temp_2_n_85;
wire mul_temp_2_n_86;
wire mul_temp_2_n_87;
wire mul_temp_2_n_88;
wire mul_temp_2_n_89;
wire mul_temp_2_n_90;
wire mul_temp_2_n_92;
wire mul_temp_2_n_93;
wire mul_temp_2_n_94;
wire mul_temp_2_n_95;
wire mul_temp_2_n_96;
wire mul_temp_2_n_97;
wire mul_temp_2_n_98;
wire mul_temp_2_n_99;
wire [14:14]\^mul_temp_3 ;
wire [14:14]\^mul_temp_30 ;
wire mul_temp_30_n_100;
wire mul_temp_30_n_101;
wire mul_temp_30_n_102;
wire mul_temp_30_n_103;
wire mul_temp_30_n_104;
wire mul_temp_30_n_105;
wire mul_temp_30_n_74;
wire mul_temp_30_n_75;
wire mul_temp_30_n_76;
wire mul_temp_30_n_77;
wire mul_temp_30_n_78;
wire mul_temp_30_n_79;
wire mul_temp_30_n_80;
wire mul_temp_30_n_81;
wire mul_temp_30_n_82;
wire mul_temp_30_n_83;
wire mul_temp_30_n_84;
wire mul_temp_30_n_85;
wire mul_temp_30_n_86;
wire mul_temp_30_n_87;
wire mul_temp_30_n_88;
wire mul_temp_30_n_89;
wire mul_temp_30_n_90;
wire mul_temp_30_n_92;
wire mul_temp_30_n_93;
wire mul_temp_30_n_94;
wire mul_temp_30_n_95;
wire mul_temp_30_n_96;
wire mul_temp_30_n_97;
wire mul_temp_30_n_98;
wire mul_temp_30_n_99;
wire [14:14]\^mul_temp_31 ;
wire mul_temp_31_n_100;
wire mul_temp_31_n_101;
wire mul_temp_31_n_102;
wire mul_temp_31_n_103;
wire mul_temp_31_n_104;
wire mul_temp_31_n_105;
wire mul_temp_31_n_74;
wire mul_temp_31_n_75;
wire mul_temp_31_n_76;
wire mul_temp_31_n_77;
wire mul_temp_31_n_78;
wire mul_temp_31_n_79;
wire mul_temp_31_n_80;
wire mul_temp_31_n_81;
wire mul_temp_31_n_82;
wire mul_temp_31_n_83;
wire mul_temp_31_n_84;
wire mul_temp_31_n_85;
wire mul_temp_31_n_86;
wire mul_temp_31_n_87;
wire mul_temp_31_n_88;
wire mul_temp_31_n_89;
wire mul_temp_31_n_90;
wire mul_temp_31_n_92;
wire mul_temp_31_n_93;
wire mul_temp_31_n_94;
wire mul_temp_31_n_95;
wire mul_temp_31_n_96;
wire mul_temp_31_n_97;
wire mul_temp_31_n_98;
wire mul_temp_31_n_99;
wire [14:14]\^mul_temp_32 ;
wire mul_temp_32_n_100;
wire mul_temp_32_n_101;
wire mul_temp_32_n_102;
wire mul_temp_32_n_103;
wire mul_temp_32_n_104;
wire mul_temp_32_n_105;
wire mul_temp_32_n_74;
wire mul_temp_32_n_75;
wire mul_temp_32_n_76;
wire mul_temp_32_n_77;
wire mul_temp_32_n_78;
wire mul_temp_32_n_79;
wire mul_temp_32_n_80;
wire mul_temp_32_n_81;
wire mul_temp_32_n_82;
wire mul_temp_32_n_83;
wire mul_temp_32_n_84;
wire mul_temp_32_n_85;
wire mul_temp_32_n_86;
wire mul_temp_32_n_87;
wire mul_temp_32_n_88;
wire mul_temp_32_n_89;
wire mul_temp_32_n_90;
wire mul_temp_32_n_92;
wire mul_temp_32_n_93;
wire mul_temp_32_n_94;
wire mul_temp_32_n_95;
wire mul_temp_32_n_96;
wire mul_temp_32_n_97;
wire mul_temp_32_n_98;
wire mul_temp_32_n_99;
wire mul_temp_3_n_100;
wire mul_temp_3_n_101;
wire mul_temp_3_n_102;
wire mul_temp_3_n_103;
wire mul_temp_3_n_104;
wire mul_temp_3_n_105;
wire mul_temp_3_n_74;
wire mul_temp_3_n_75;
wire mul_temp_3_n_76;
wire mul_temp_3_n_77;
wire mul_temp_3_n_78;
wire mul_temp_3_n_79;
wire mul_temp_3_n_80;
wire mul_temp_3_n_81;
wire mul_temp_3_n_82;
wire mul_temp_3_n_83;
wire mul_temp_3_n_84;
wire mul_temp_3_n_85;
wire mul_temp_3_n_86;
wire mul_temp_3_n_87;
wire mul_temp_3_n_88;
wire mul_temp_3_n_89;
wire mul_temp_3_n_90;
wire mul_temp_3_n_92;
wire mul_temp_3_n_93;
wire mul_temp_3_n_94;
wire mul_temp_3_n_95;
wire mul_temp_3_n_96;
wire mul_temp_3_n_97;
wire mul_temp_3_n_98;
wire mul_temp_3_n_99;
wire [14:14]\^mul_temp_4 ;
wire mul_temp_4_n_100;
wire mul_temp_4_n_101;
wire mul_temp_4_n_102;
wire mul_temp_4_n_103;
wire mul_temp_4_n_104;
wire mul_temp_4_n_105;
wire mul_temp_4_n_74;
wire mul_temp_4_n_75;
wire mul_temp_4_n_76;
wire mul_temp_4_n_77;
wire mul_temp_4_n_78;
wire mul_temp_4_n_79;
wire mul_temp_4_n_80;
wire mul_temp_4_n_81;
wire mul_temp_4_n_82;
wire mul_temp_4_n_83;
wire mul_temp_4_n_84;
wire mul_temp_4_n_85;
wire mul_temp_4_n_86;
wire mul_temp_4_n_87;
wire mul_temp_4_n_88;
wire mul_temp_4_n_89;
wire mul_temp_4_n_90;
wire mul_temp_4_n_92;
wire mul_temp_4_n_93;
wire mul_temp_4_n_94;
wire mul_temp_4_n_95;
wire mul_temp_4_n_96;
wire mul_temp_4_n_97;
wire mul_temp_4_n_98;
wire mul_temp_4_n_99;
wire [14:14]\^mul_temp_5 ;
wire mul_temp_5_n_100;
wire mul_temp_5_n_101;
wire mul_temp_5_n_102;
wire mul_temp_5_n_103;
wire mul_temp_5_n_104;
wire mul_temp_5_n_105;
wire mul_temp_5_n_74;
wire mul_temp_5_n_75;
wire mul_temp_5_n_76;
wire mul_temp_5_n_77;
wire mul_temp_5_n_78;
wire mul_temp_5_n_79;
wire mul_temp_5_n_80;
wire mul_temp_5_n_81;
wire mul_temp_5_n_82;
wire mul_temp_5_n_83;
wire mul_temp_5_n_84;
wire mul_temp_5_n_85;
wire mul_temp_5_n_86;
wire mul_temp_5_n_87;
wire mul_temp_5_n_88;
wire mul_temp_5_n_89;
wire mul_temp_5_n_90;
wire mul_temp_5_n_92;
wire mul_temp_5_n_93;
wire mul_temp_5_n_94;
wire mul_temp_5_n_95;
wire mul_temp_5_n_96;
wire mul_temp_5_n_97;
wire mul_temp_5_n_98;
wire mul_temp_5_n_99;
wire [14:14]\^mul_temp_6 ;
wire mul_temp_6_n_100;
wire mul_temp_6_n_101;
wire mul_temp_6_n_102;
wire mul_temp_6_n_103;
wire mul_temp_6_n_104;
wire mul_temp_6_n_105;
wire mul_temp_6_n_74;
wire mul_temp_6_n_75;
wire mul_temp_6_n_76;
wire mul_temp_6_n_77;
wire mul_temp_6_n_78;
wire mul_temp_6_n_79;
wire mul_temp_6_n_80;
wire mul_temp_6_n_81;
wire mul_temp_6_n_82;
wire mul_temp_6_n_83;
wire mul_temp_6_n_84;
wire mul_temp_6_n_85;
wire mul_temp_6_n_86;
wire mul_temp_6_n_87;
wire mul_temp_6_n_88;
wire mul_temp_6_n_89;
wire mul_temp_6_n_90;
wire mul_temp_6_n_92;
wire mul_temp_6_n_93;
wire mul_temp_6_n_94;
wire mul_temp_6_n_95;
wire mul_temp_6_n_96;
wire mul_temp_6_n_97;
wire mul_temp_6_n_98;
wire mul_temp_6_n_99;
wire [14:14]\^mul_temp_7 ;
wire mul_temp_7_n_100;
wire mul_temp_7_n_101;
wire mul_temp_7_n_102;
wire mul_temp_7_n_103;
wire mul_temp_7_n_104;
wire mul_temp_7_n_105;
wire mul_temp_7_n_74;
wire mul_temp_7_n_75;
wire mul_temp_7_n_76;
wire mul_temp_7_n_77;
wire mul_temp_7_n_78;
wire mul_temp_7_n_79;
wire mul_temp_7_n_80;
wire mul_temp_7_n_81;
wire mul_temp_7_n_82;
wire mul_temp_7_n_83;
wire mul_temp_7_n_84;
wire mul_temp_7_n_85;
wire mul_temp_7_n_86;
wire mul_temp_7_n_87;
wire mul_temp_7_n_88;
wire mul_temp_7_n_89;
wire mul_temp_7_n_90;
wire mul_temp_7_n_92;
wire mul_temp_7_n_93;
wire mul_temp_7_n_94;
wire mul_temp_7_n_95;
wire mul_temp_7_n_96;
wire mul_temp_7_n_97;
wire mul_temp_7_n_98;
wire mul_temp_7_n_99;
wire [14:14]\^mul_temp_8 ;
wire mul_temp_8_n_100;
wire mul_temp_8_n_101;
wire mul_temp_8_n_102;
wire mul_temp_8_n_103;
wire mul_temp_8_n_104;
wire mul_temp_8_n_105;
wire mul_temp_8_n_74;
wire mul_temp_8_n_75;
wire mul_temp_8_n_76;
wire mul_temp_8_n_77;
wire mul_temp_8_n_78;
wire mul_temp_8_n_79;
wire mul_temp_8_n_80;
wire mul_temp_8_n_81;
wire mul_temp_8_n_82;
wire mul_temp_8_n_83;
wire mul_temp_8_n_84;
wire mul_temp_8_n_85;
wire mul_temp_8_n_86;
wire mul_temp_8_n_87;
wire mul_temp_8_n_88;
wire mul_temp_8_n_89;
wire mul_temp_8_n_90;
wire mul_temp_8_n_92;
wire mul_temp_8_n_93;
wire mul_temp_8_n_94;
wire mul_temp_8_n_95;
wire mul_temp_8_n_96;
wire mul_temp_8_n_97;
wire mul_temp_8_n_98;
wire mul_temp_8_n_99;
wire [14:14]\^mul_temp_9 ;
wire mul_temp_9_n_100;
wire mul_temp_9_n_101;
wire mul_temp_9_n_102;
wire mul_temp_9_n_103;
wire mul_temp_9_n_104;
wire mul_temp_9_n_105;
wire mul_temp_9_n_74;
wire mul_temp_9_n_75;
wire mul_temp_9_n_76;
wire mul_temp_9_n_77;
wire mul_temp_9_n_78;
wire mul_temp_9_n_79;
wire mul_temp_9_n_80;
wire mul_temp_9_n_81;
wire mul_temp_9_n_82;
wire mul_temp_9_n_83;
wire mul_temp_9_n_84;
wire mul_temp_9_n_85;
wire mul_temp_9_n_86;
wire mul_temp_9_n_87;
wire mul_temp_9_n_88;
wire mul_temp_9_n_89;
wire mul_temp_9_n_90;
wire mul_temp_9_n_92;
wire mul_temp_9_n_93;
wire mul_temp_9_n_94;
wire mul_temp_9_n_95;
wire mul_temp_9_n_96;
wire mul_temp_9_n_97;
wire mul_temp_9_n_98;
wire mul_temp_9_n_99;
wire mul_temp_n_100;
wire mul_temp_n_101;
wire mul_temp_n_102;
wire mul_temp_n_103;
wire mul_temp_n_104;
wire mul_temp_n_105;
wire mul_temp_n_74;
wire mul_temp_n_75;
wire mul_temp_n_76;
wire mul_temp_n_77;
wire mul_temp_n_78;
wire mul_temp_n_79;
wire mul_temp_n_80;
wire mul_temp_n_81;
wire mul_temp_n_82;
wire mul_temp_n_83;
wire mul_temp_n_84;
wire mul_temp_n_85;
wire mul_temp_n_86;
wire mul_temp_n_87;
wire mul_temp_n_88;
wire mul_temp_n_89;
wire mul_temp_n_90;
wire mul_temp_n_92;
wire mul_temp_n_93;
wire mul_temp_n_94;
wire mul_temp_n_95;
wire mul_temp_n_96;
wire mul_temp_n_97;
wire mul_temp_n_98;
wire mul_temp_n_99;
wire sub_temp_carry__0_n_0;
wire sub_temp_carry__0_n_1;
wire sub_temp_carry__0_n_2;
wire sub_temp_carry__0_n_3;
wire sub_temp_carry__1_n_0;
wire sub_temp_carry__1_n_1;
wire sub_temp_carry__1_n_2;
wire sub_temp_carry__1_n_3;
wire sub_temp_carry__2_n_1;
wire sub_temp_carry__2_n_2;
wire sub_temp_carry__2_n_3;
wire sub_temp_carry_n_0;
wire sub_temp_carry_n_1;
wire sub_temp_carry_n_2;
wire sub_temp_carry_n_3;
wire \weight[0][0]_i_2_n_0 ;
wire \weight[0][0]_i_3_n_0 ;
wire \weight[0][0]_i_4_n_0 ;
wire \weight[0][0]_i_5_n_0 ;
wire \weight[0][12]_i_2_n_0 ;
wire \weight[0][12]_i_3_n_0 ;
wire \weight[0][12]_i_4_n_0 ;
wire \weight[0][12]_i_5_n_0 ;
wire \weight[0][4]_i_2_n_0 ;
wire \weight[0][4]_i_3_n_0 ;
wire \weight[0][4]_i_4_n_0 ;
wire \weight[0][4]_i_5_n_0 ;
wire \weight[0][8]_i_2_n_0 ;
wire \weight[0][8]_i_3_n_0 ;
wire \weight[0][8]_i_4_n_0 ;
wire \weight[0][8]_i_5_n_0 ;
wire \weight[10][0]_i_2_n_0 ;
wire \weight[10][0]_i_3_n_0 ;
wire \weight[10][0]_i_4_n_0 ;
wire \weight[10][0]_i_5_n_0 ;
wire \weight[10][12]_i_2_n_0 ;
wire \weight[10][12]_i_3_n_0 ;
wire \weight[10][12]_i_4_n_0 ;
wire \weight[10][12]_i_5_n_0 ;
wire \weight[10][4]_i_2_n_0 ;
wire \weight[10][4]_i_3_n_0 ;
wire \weight[10][4]_i_4_n_0 ;
wire \weight[10][4]_i_5_n_0 ;
wire \weight[10][8]_i_2_n_0 ;
wire \weight[10][8]_i_3_n_0 ;
wire \weight[10][8]_i_4_n_0 ;
wire \weight[10][8]_i_5_n_0 ;
wire \weight[11][0]_i_2_n_0 ;
wire \weight[11][0]_i_3_n_0 ;
wire \weight[11][0]_i_4_n_0 ;
wire \weight[11][0]_i_5_n_0 ;
wire \weight[11][12]_i_2_n_0 ;
wire \weight[11][12]_i_3_n_0 ;
wire \weight[11][12]_i_4_n_0 ;
wire \weight[11][12]_i_5_n_0 ;
wire \weight[11][4]_i_2_n_0 ;
wire \weight[11][4]_i_3_n_0 ;
wire \weight[11][4]_i_4_n_0 ;
wire \weight[11][4]_i_5_n_0 ;
wire \weight[11][8]_i_2_n_0 ;
wire \weight[11][8]_i_3_n_0 ;
wire \weight[11][8]_i_4_n_0 ;
wire \weight[11][8]_i_5_n_0 ;
wire \weight[12][0]_i_2_n_0 ;
wire \weight[12][0]_i_3_n_0 ;
wire \weight[12][0]_i_4_n_0 ;
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wire \weight_reg[15][8]_i_1_n_7 ;
wire [15:0]\weight_reg[15]_14 ;
wire \weight_reg[1][0]_i_1_n_0 ;
wire \weight_reg[1][0]_i_1_n_1 ;
wire \weight_reg[1][0]_i_1_n_2 ;
wire \weight_reg[1][0]_i_1_n_3 ;
wire \weight_reg[1][0]_i_1_n_4 ;
wire \weight_reg[1][0]_i_1_n_5 ;
wire \weight_reg[1][0]_i_1_n_6 ;
wire \weight_reg[1][0]_i_1_n_7 ;
wire \weight_reg[1][12]_i_1_n_1 ;
wire \weight_reg[1][12]_i_1_n_2 ;
wire \weight_reg[1][12]_i_1_n_3 ;
wire \weight_reg[1][12]_i_1_n_4 ;
wire \weight_reg[1][12]_i_1_n_5 ;
wire \weight_reg[1][12]_i_1_n_6 ;
wire \weight_reg[1][12]_i_1_n_7 ;
wire \weight_reg[1][4]_i_1_n_0 ;
wire \weight_reg[1][4]_i_1_n_1 ;
wire \weight_reg[1][4]_i_1_n_2 ;
wire \weight_reg[1][4]_i_1_n_3 ;
wire \weight_reg[1][4]_i_1_n_4 ;
wire \weight_reg[1][4]_i_1_n_5 ;
wire \weight_reg[1][4]_i_1_n_6 ;
wire \weight_reg[1][4]_i_1_n_7 ;
wire \weight_reg[1][8]_i_1_n_0 ;
wire \weight_reg[1][8]_i_1_n_1 ;
wire \weight_reg[1][8]_i_1_n_2 ;
wire \weight_reg[1][8]_i_1_n_3 ;
wire \weight_reg[1][8]_i_1_n_4 ;
wire \weight_reg[1][8]_i_1_n_5 ;
wire \weight_reg[1][8]_i_1_n_6 ;
wire \weight_reg[1][8]_i_1_n_7 ;
wire [15:0]\weight_reg[1]_0 ;
wire \weight_reg[2][0]_i_1_n_0 ;
wire \weight_reg[2][0]_i_1_n_1 ;
wire \weight_reg[2][0]_i_1_n_2 ;
wire \weight_reg[2][0]_i_1_n_3 ;
wire \weight_reg[2][0]_i_1_n_4 ;
wire \weight_reg[2][0]_i_1_n_5 ;
wire \weight_reg[2][0]_i_1_n_6 ;
wire \weight_reg[2][0]_i_1_n_7 ;
wire \weight_reg[2][12]_i_1_n_1 ;
wire \weight_reg[2][12]_i_1_n_2 ;
wire \weight_reg[2][12]_i_1_n_3 ;
wire \weight_reg[2][12]_i_1_n_4 ;
wire \weight_reg[2][12]_i_1_n_5 ;
wire \weight_reg[2][12]_i_1_n_6 ;
wire \weight_reg[2][12]_i_1_n_7 ;
wire \weight_reg[2][4]_i_1_n_0 ;
wire \weight_reg[2][4]_i_1_n_1 ;
wire \weight_reg[2][4]_i_1_n_2 ;
wire \weight_reg[2][4]_i_1_n_3 ;
wire \weight_reg[2][4]_i_1_n_4 ;
wire \weight_reg[2][4]_i_1_n_5 ;
wire \weight_reg[2][4]_i_1_n_6 ;
wire \weight_reg[2][4]_i_1_n_7 ;
wire \weight_reg[2][8]_i_1_n_0 ;
wire \weight_reg[2][8]_i_1_n_1 ;
wire \weight_reg[2][8]_i_1_n_2 ;
wire \weight_reg[2][8]_i_1_n_3 ;
wire \weight_reg[2][8]_i_1_n_4 ;
wire \weight_reg[2][8]_i_1_n_5 ;
wire \weight_reg[2][8]_i_1_n_6 ;
wire \weight_reg[2][8]_i_1_n_7 ;
wire [15:0]\weight_reg[2]_1 ;
wire \weight_reg[3][0]_i_1_n_0 ;
wire \weight_reg[3][0]_i_1_n_1 ;
wire \weight_reg[3][0]_i_1_n_2 ;
wire \weight_reg[3][0]_i_1_n_3 ;
wire \weight_reg[3][0]_i_1_n_4 ;
wire \weight_reg[3][0]_i_1_n_5 ;
wire \weight_reg[3][0]_i_1_n_6 ;
wire \weight_reg[3][0]_i_1_n_7 ;
wire \weight_reg[3][12]_i_1_n_1 ;
wire \weight_reg[3][12]_i_1_n_2 ;
wire \weight_reg[3][12]_i_1_n_3 ;
wire \weight_reg[3][12]_i_1_n_4 ;
wire \weight_reg[3][12]_i_1_n_5 ;
wire \weight_reg[3][12]_i_1_n_6 ;
wire \weight_reg[3][12]_i_1_n_7 ;
wire \weight_reg[3][4]_i_1_n_0 ;
wire \weight_reg[3][4]_i_1_n_1 ;
wire \weight_reg[3][4]_i_1_n_2 ;
wire \weight_reg[3][4]_i_1_n_3 ;
wire \weight_reg[3][4]_i_1_n_4 ;
wire \weight_reg[3][4]_i_1_n_5 ;
wire \weight_reg[3][4]_i_1_n_6 ;
wire \weight_reg[3][4]_i_1_n_7 ;
wire \weight_reg[3][8]_i_1_n_0 ;
wire \weight_reg[3][8]_i_1_n_1 ;
wire \weight_reg[3][8]_i_1_n_2 ;
wire \weight_reg[3][8]_i_1_n_3 ;
wire \weight_reg[3][8]_i_1_n_4 ;
wire \weight_reg[3][8]_i_1_n_5 ;
wire \weight_reg[3][8]_i_1_n_6 ;
wire \weight_reg[3][8]_i_1_n_7 ;
wire [15:0]\weight_reg[3]_2 ;
wire \weight_reg[4][0]_i_1_n_0 ;
wire \weight_reg[4][0]_i_1_n_1 ;
wire \weight_reg[4][0]_i_1_n_2 ;
wire \weight_reg[4][0]_i_1_n_3 ;
wire \weight_reg[4][0]_i_1_n_4 ;
wire \weight_reg[4][0]_i_1_n_5 ;
wire \weight_reg[4][0]_i_1_n_6 ;
wire \weight_reg[4][0]_i_1_n_7 ;
wire \weight_reg[4][12]_i_1_n_1 ;
wire \weight_reg[4][12]_i_1_n_2 ;
wire \weight_reg[4][12]_i_1_n_3 ;
wire \weight_reg[4][12]_i_1_n_4 ;
wire \weight_reg[4][12]_i_1_n_5 ;
wire \weight_reg[4][12]_i_1_n_6 ;
wire \weight_reg[4][12]_i_1_n_7 ;
wire \weight_reg[4][4]_i_1_n_0 ;
wire \weight_reg[4][4]_i_1_n_1 ;
wire \weight_reg[4][4]_i_1_n_2 ;
wire \weight_reg[4][4]_i_1_n_3 ;
wire \weight_reg[4][4]_i_1_n_4 ;
wire \weight_reg[4][4]_i_1_n_5 ;
wire \weight_reg[4][4]_i_1_n_6 ;
wire \weight_reg[4][4]_i_1_n_7 ;
wire \weight_reg[4][8]_i_1_n_0 ;
wire \weight_reg[4][8]_i_1_n_1 ;
wire \weight_reg[4][8]_i_1_n_2 ;
wire \weight_reg[4][8]_i_1_n_3 ;
wire \weight_reg[4][8]_i_1_n_4 ;
wire \weight_reg[4][8]_i_1_n_5 ;
wire \weight_reg[4][8]_i_1_n_6 ;
wire \weight_reg[4][8]_i_1_n_7 ;
wire [15:0]\weight_reg[4]_3 ;
wire \weight_reg[5][0]_i_1_n_0 ;
wire \weight_reg[5][0]_i_1_n_1 ;
wire \weight_reg[5][0]_i_1_n_2 ;
wire \weight_reg[5][0]_i_1_n_3 ;
wire \weight_reg[5][0]_i_1_n_4 ;
wire \weight_reg[5][0]_i_1_n_5 ;
wire \weight_reg[5][0]_i_1_n_6 ;
wire \weight_reg[5][0]_i_1_n_7 ;
wire \weight_reg[5][12]_i_1_n_1 ;
wire \weight_reg[5][12]_i_1_n_2 ;
wire \weight_reg[5][12]_i_1_n_3 ;
wire \weight_reg[5][12]_i_1_n_4 ;
wire \weight_reg[5][12]_i_1_n_5 ;
wire \weight_reg[5][12]_i_1_n_6 ;
wire \weight_reg[5][12]_i_1_n_7 ;
wire \weight_reg[5][4]_i_1_n_0 ;
wire \weight_reg[5][4]_i_1_n_1 ;
wire \weight_reg[5][4]_i_1_n_2 ;
wire \weight_reg[5][4]_i_1_n_3 ;
wire \weight_reg[5][4]_i_1_n_4 ;
wire \weight_reg[5][4]_i_1_n_5 ;
wire \weight_reg[5][4]_i_1_n_6 ;
wire \weight_reg[5][4]_i_1_n_7 ;
wire \weight_reg[5][8]_i_1_n_0 ;
wire \weight_reg[5][8]_i_1_n_1 ;
wire \weight_reg[5][8]_i_1_n_2 ;
wire \weight_reg[5][8]_i_1_n_3 ;
wire \weight_reg[5][8]_i_1_n_4 ;
wire \weight_reg[5][8]_i_1_n_5 ;
wire \weight_reg[5][8]_i_1_n_6 ;
wire \weight_reg[5][8]_i_1_n_7 ;
wire [15:0]\weight_reg[5]_4 ;
wire \weight_reg[6][0]_i_1_n_0 ;
wire \weight_reg[6][0]_i_1_n_1 ;
wire \weight_reg[6][0]_i_1_n_2 ;
wire \weight_reg[6][0]_i_1_n_3 ;
wire \weight_reg[6][0]_i_1_n_4 ;
wire \weight_reg[6][0]_i_1_n_5 ;
wire \weight_reg[6][0]_i_1_n_6 ;
wire \weight_reg[6][0]_i_1_n_7 ;
wire \weight_reg[6][12]_i_1_n_1 ;
wire \weight_reg[6][12]_i_1_n_2 ;
wire \weight_reg[6][12]_i_1_n_3 ;
wire \weight_reg[6][12]_i_1_n_4 ;
wire \weight_reg[6][12]_i_1_n_5 ;
wire \weight_reg[6][12]_i_1_n_6 ;
wire \weight_reg[6][12]_i_1_n_7 ;
wire \weight_reg[6][4]_i_1_n_0 ;
wire \weight_reg[6][4]_i_1_n_1 ;
wire \weight_reg[6][4]_i_1_n_2 ;
wire \weight_reg[6][4]_i_1_n_3 ;
wire \weight_reg[6][4]_i_1_n_4 ;
wire \weight_reg[6][4]_i_1_n_5 ;
wire \weight_reg[6][4]_i_1_n_6 ;
wire \weight_reg[6][4]_i_1_n_7 ;
wire \weight_reg[6][8]_i_1_n_0 ;
wire \weight_reg[6][8]_i_1_n_1 ;
wire \weight_reg[6][8]_i_1_n_2 ;
wire \weight_reg[6][8]_i_1_n_3 ;
wire \weight_reg[6][8]_i_1_n_4 ;
wire \weight_reg[6][8]_i_1_n_5 ;
wire \weight_reg[6][8]_i_1_n_6 ;
wire \weight_reg[6][8]_i_1_n_7 ;
wire [15:0]\weight_reg[6]_5 ;
wire \weight_reg[7][0]_i_1_n_0 ;
wire \weight_reg[7][0]_i_1_n_1 ;
wire \weight_reg[7][0]_i_1_n_2 ;
wire \weight_reg[7][0]_i_1_n_3 ;
wire \weight_reg[7][0]_i_1_n_4 ;
wire \weight_reg[7][0]_i_1_n_5 ;
wire \weight_reg[7][0]_i_1_n_6 ;
wire \weight_reg[7][0]_i_1_n_7 ;
wire \weight_reg[7][12]_i_1_n_1 ;
wire \weight_reg[7][12]_i_1_n_2 ;
wire \weight_reg[7][12]_i_1_n_3 ;
wire \weight_reg[7][12]_i_1_n_4 ;
wire \weight_reg[7][12]_i_1_n_5 ;
wire \weight_reg[7][12]_i_1_n_6 ;
wire \weight_reg[7][12]_i_1_n_7 ;
wire \weight_reg[7][4]_i_1_n_0 ;
wire \weight_reg[7][4]_i_1_n_1 ;
wire \weight_reg[7][4]_i_1_n_2 ;
wire \weight_reg[7][4]_i_1_n_3 ;
wire \weight_reg[7][4]_i_1_n_4 ;
wire \weight_reg[7][4]_i_1_n_5 ;
wire \weight_reg[7][4]_i_1_n_6 ;
wire \weight_reg[7][4]_i_1_n_7 ;
wire \weight_reg[7][8]_i_1_n_0 ;
wire \weight_reg[7][8]_i_1_n_1 ;
wire \weight_reg[7][8]_i_1_n_2 ;
wire \weight_reg[7][8]_i_1_n_3 ;
wire \weight_reg[7][8]_i_1_n_4 ;
wire \weight_reg[7][8]_i_1_n_5 ;
wire \weight_reg[7][8]_i_1_n_6 ;
wire \weight_reg[7][8]_i_1_n_7 ;
wire [15:0]\weight_reg[7]_6 ;
wire \weight_reg[8][0]_i_1_n_0 ;
wire \weight_reg[8][0]_i_1_n_1 ;
wire \weight_reg[8][0]_i_1_n_2 ;
wire \weight_reg[8][0]_i_1_n_3 ;
wire \weight_reg[8][0]_i_1_n_4 ;
wire \weight_reg[8][0]_i_1_n_5 ;
wire \weight_reg[8][0]_i_1_n_6 ;
wire \weight_reg[8][0]_i_1_n_7 ;
wire \weight_reg[8][12]_i_1_n_1 ;
wire \weight_reg[8][12]_i_1_n_2 ;
wire \weight_reg[8][12]_i_1_n_3 ;
wire \weight_reg[8][12]_i_1_n_4 ;
wire \weight_reg[8][12]_i_1_n_5 ;
wire \weight_reg[8][12]_i_1_n_6 ;
wire \weight_reg[8][12]_i_1_n_7 ;
wire \weight_reg[8][4]_i_1_n_0 ;
wire \weight_reg[8][4]_i_1_n_1 ;
wire \weight_reg[8][4]_i_1_n_2 ;
wire \weight_reg[8][4]_i_1_n_3 ;
wire \weight_reg[8][4]_i_1_n_4 ;
wire \weight_reg[8][4]_i_1_n_5 ;
wire \weight_reg[8][4]_i_1_n_6 ;
wire \weight_reg[8][4]_i_1_n_7 ;
wire \weight_reg[8][8]_i_1_n_0 ;
wire \weight_reg[8][8]_i_1_n_1 ;
wire \weight_reg[8][8]_i_1_n_2 ;
wire \weight_reg[8][8]_i_1_n_3 ;
wire \weight_reg[8][8]_i_1_n_4 ;
wire \weight_reg[8][8]_i_1_n_5 ;
wire \weight_reg[8][8]_i_1_n_6 ;
wire \weight_reg[8][8]_i_1_n_7 ;
wire [15:0]\weight_reg[8]_7 ;
wire \weight_reg[9][0]_i_1_n_0 ;
wire \weight_reg[9][0]_i_1_n_1 ;
wire \weight_reg[9][0]_i_1_n_2 ;
wire \weight_reg[9][0]_i_1_n_3 ;
wire \weight_reg[9][0]_i_1_n_4 ;
wire \weight_reg[9][0]_i_1_n_5 ;
wire \weight_reg[9][0]_i_1_n_6 ;
wire \weight_reg[9][0]_i_1_n_7 ;
wire \weight_reg[9][12]_i_1_n_1 ;
wire \weight_reg[9][12]_i_1_n_2 ;
wire \weight_reg[9][12]_i_1_n_3 ;
wire \weight_reg[9][12]_i_1_n_4 ;
wire \weight_reg[9][12]_i_1_n_5 ;
wire \weight_reg[9][12]_i_1_n_6 ;
wire \weight_reg[9][12]_i_1_n_7 ;
wire \weight_reg[9][4]_i_1_n_0 ;
wire \weight_reg[9][4]_i_1_n_1 ;
wire \weight_reg[9][4]_i_1_n_2 ;
wire \weight_reg[9][4]_i_1_n_3 ;
wire \weight_reg[9][4]_i_1_n_4 ;
wire \weight_reg[9][4]_i_1_n_5 ;
wire \weight_reg[9][4]_i_1_n_6 ;
wire \weight_reg[9][4]_i_1_n_7 ;
wire \weight_reg[9][8]_i_1_n_0 ;
wire \weight_reg[9][8]_i_1_n_1 ;
wire \weight_reg[9][8]_i_1_n_2 ;
wire \weight_reg[9][8]_i_1_n_3 ;
wire \weight_reg[9][8]_i_1_n_4 ;
wire \weight_reg[9][8]_i_1_n_5 ;
wire \weight_reg[9][8]_i_1_n_6 ;
wire \weight_reg[9][8]_i_1_n_7 ;
wire [15:0]\weight_reg[9]_8 ;
wire [3:0]\write_reg_d_k_reg[11] ;
wire [2:0]\write_reg_d_k_reg[3] ;
wire [3:0]\write_reg_d_k_reg[3]_0 ;
wire [3:0]\write_reg_d_k_reg[7] ;
wire [15:0]\write_reg_x_k_reg[15] ;
wire NLW_ARG_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG_OVERFLOW_UNCONNECTED;
wire NLW_ARG_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG_P_UNCONNECTED;
wire [47:0]NLW_ARG_PCOUT_UNCONNECTED;
wire NLW_ARG__0_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__0_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__0_OVERFLOW_UNCONNECTED;
wire NLW_ARG__0_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__0_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__0_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__0_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__0_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__0_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__0_P_UNCONNECTED;
wire [47:0]NLW_ARG__0_PCOUT_UNCONNECTED;
wire NLW_ARG__1_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__1_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__1_OVERFLOW_UNCONNECTED;
wire NLW_ARG__1_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__1_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__1_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__1_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__1_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__1_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__1_P_UNCONNECTED;
wire [47:0]NLW_ARG__1_PCOUT_UNCONNECTED;
wire NLW_ARG__10_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__10_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__10_OVERFLOW_UNCONNECTED;
wire NLW_ARG__10_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__10_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__10_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__10_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__10_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__10_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__10_P_UNCONNECTED;
wire [47:0]NLW_ARG__10_PCOUT_UNCONNECTED;
wire NLW_ARG__11_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__11_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__11_OVERFLOW_UNCONNECTED;
wire NLW_ARG__11_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__11_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__11_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__11_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__11_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__11_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__11_P_UNCONNECTED;
wire [47:0]NLW_ARG__11_PCOUT_UNCONNECTED;
wire NLW_ARG__12_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__12_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__12_OVERFLOW_UNCONNECTED;
wire NLW_ARG__12_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__12_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__12_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__12_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__12_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__12_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__12_P_UNCONNECTED;
wire [47:0]NLW_ARG__12_PCOUT_UNCONNECTED;
wire NLW_ARG__13_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__13_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__13_OVERFLOW_UNCONNECTED;
wire NLW_ARG__13_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__13_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__13_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__13_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__13_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__13_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__13_P_UNCONNECTED;
wire [47:0]NLW_ARG__13_PCOUT_UNCONNECTED;
wire NLW_ARG__14_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__14_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__14_OVERFLOW_UNCONNECTED;
wire NLW_ARG__14_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__14_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__14_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__14_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__14_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__14_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__14_P_UNCONNECTED;
wire [47:0]NLW_ARG__14_PCOUT_UNCONNECTED;
wire NLW_ARG__15_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__15_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__15_OVERFLOW_UNCONNECTED;
wire NLW_ARG__15_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__15_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__15_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__15_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__15_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__15_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__15_P_UNCONNECTED;
wire [47:0]NLW_ARG__15_PCOUT_UNCONNECTED;
wire NLW_ARG__16_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__16_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__16_OVERFLOW_UNCONNECTED;
wire NLW_ARG__16_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__16_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__16_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__16_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__16_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__16_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__16_P_UNCONNECTED;
wire [47:0]NLW_ARG__16_PCOUT_UNCONNECTED;
wire NLW_ARG__17_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__17_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__17_OVERFLOW_UNCONNECTED;
wire NLW_ARG__17_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__17_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__17_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__17_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__17_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__17_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__17_P_UNCONNECTED;
wire [47:0]NLW_ARG__17_PCOUT_UNCONNECTED;
wire NLW_ARG__18_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__18_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__18_OVERFLOW_UNCONNECTED;
wire NLW_ARG__18_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__18_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__18_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__18_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__18_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__18_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__18_P_UNCONNECTED;
wire [47:0]NLW_ARG__18_PCOUT_UNCONNECTED;
wire NLW_ARG__19_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__19_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__19_OVERFLOW_UNCONNECTED;
wire NLW_ARG__19_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__19_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__19_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__19_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__19_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__19_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__19_P_UNCONNECTED;
wire [47:0]NLW_ARG__19_PCOUT_UNCONNECTED;
wire NLW_ARG__2_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__2_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__2_OVERFLOW_UNCONNECTED;
wire NLW_ARG__2_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__2_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__2_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__2_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__2_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__2_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__2_P_UNCONNECTED;
wire [47:0]NLW_ARG__2_PCOUT_UNCONNECTED;
wire NLW_ARG__20_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__20_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__20_OVERFLOW_UNCONNECTED;
wire NLW_ARG__20_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__20_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__20_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__20_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__20_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__20_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__20_P_UNCONNECTED;
wire [47:0]NLW_ARG__20_PCOUT_UNCONNECTED;
wire NLW_ARG__21_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__21_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__21_OVERFLOW_UNCONNECTED;
wire NLW_ARG__21_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__21_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__21_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__21_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__21_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__21_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__21_P_UNCONNECTED;
wire [47:0]NLW_ARG__21_PCOUT_UNCONNECTED;
wire NLW_ARG__22_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__22_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__22_OVERFLOW_UNCONNECTED;
wire NLW_ARG__22_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__22_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__22_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__22_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__22_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__22_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__22_P_UNCONNECTED;
wire [47:0]NLW_ARG__22_PCOUT_UNCONNECTED;
wire NLW_ARG__23_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__23_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__23_OVERFLOW_UNCONNECTED;
wire NLW_ARG__23_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__23_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__23_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__23_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__23_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__23_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__23_P_UNCONNECTED;
wire [47:0]NLW_ARG__23_PCOUT_UNCONNECTED;
wire NLW_ARG__24_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__24_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__24_OVERFLOW_UNCONNECTED;
wire NLW_ARG__24_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__24_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__24_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__24_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__24_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__24_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__24_P_UNCONNECTED;
wire [47:0]NLW_ARG__24_PCOUT_UNCONNECTED;
wire NLW_ARG__25_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__25_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__25_OVERFLOW_UNCONNECTED;
wire NLW_ARG__25_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__25_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__25_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__25_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__25_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__25_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__25_P_UNCONNECTED;
wire [47:0]NLW_ARG__25_PCOUT_UNCONNECTED;
wire NLW_ARG__26_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__26_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__26_OVERFLOW_UNCONNECTED;
wire NLW_ARG__26_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__26_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__26_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__26_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__26_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__26_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__26_P_UNCONNECTED;
wire [47:0]NLW_ARG__26_PCOUT_UNCONNECTED;
wire NLW_ARG__27_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__27_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__27_OVERFLOW_UNCONNECTED;
wire NLW_ARG__27_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__27_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__27_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__27_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__27_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__27_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__27_P_UNCONNECTED;
wire [47:0]NLW_ARG__27_PCOUT_UNCONNECTED;
wire NLW_ARG__28_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__28_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__28_OVERFLOW_UNCONNECTED;
wire NLW_ARG__28_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__28_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__28_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__28_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__28_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__28_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__28_P_UNCONNECTED;
wire [47:0]NLW_ARG__28_PCOUT_UNCONNECTED;
wire NLW_ARG__29_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__29_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__29_OVERFLOW_UNCONNECTED;
wire NLW_ARG__29_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__29_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__29_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__29_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__29_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__29_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__29_P_UNCONNECTED;
wire [47:0]NLW_ARG__29_PCOUT_UNCONNECTED;
wire NLW_ARG__3_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__3_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__3_OVERFLOW_UNCONNECTED;
wire NLW_ARG__3_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__3_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__3_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__3_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__3_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__3_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__3_P_UNCONNECTED;
wire [47:0]NLW_ARG__3_PCOUT_UNCONNECTED;
wire NLW_ARG__30_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__30_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__30_OVERFLOW_UNCONNECTED;
wire NLW_ARG__30_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__30_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__30_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__30_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__30_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__30_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__30_P_UNCONNECTED;
wire [47:0]NLW_ARG__30_PCOUT_UNCONNECTED;
wire NLW_ARG__4_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__4_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__4_OVERFLOW_UNCONNECTED;
wire NLW_ARG__4_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__4_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__4_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__4_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__4_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__4_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__4_P_UNCONNECTED;
wire [47:0]NLW_ARG__4_PCOUT_UNCONNECTED;
wire NLW_ARG__5_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__5_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__5_OVERFLOW_UNCONNECTED;
wire NLW_ARG__5_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__5_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__5_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__5_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__5_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__5_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__5_P_UNCONNECTED;
wire [47:0]NLW_ARG__5_PCOUT_UNCONNECTED;
wire NLW_ARG__6_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__6_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__6_OVERFLOW_UNCONNECTED;
wire NLW_ARG__6_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__6_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__6_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__6_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__6_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__6_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__6_P_UNCONNECTED;
wire [47:0]NLW_ARG__6_PCOUT_UNCONNECTED;
wire NLW_ARG__7_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__7_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__7_OVERFLOW_UNCONNECTED;
wire NLW_ARG__7_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__7_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__7_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__7_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__7_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__7_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__7_P_UNCONNECTED;
wire [47:0]NLW_ARG__7_PCOUT_UNCONNECTED;
wire NLW_ARG__8_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__8_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__8_OVERFLOW_UNCONNECTED;
wire NLW_ARG__8_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__8_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__8_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__8_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__8_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__8_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__8_P_UNCONNECTED;
wire [47:0]NLW_ARG__8_PCOUT_UNCONNECTED;
wire NLW_ARG__9_CARRYCASCOUT_UNCONNECTED;
wire NLW_ARG__9_MULTSIGNOUT_UNCONNECTED;
wire NLW_ARG__9_OVERFLOW_UNCONNECTED;
wire NLW_ARG__9_PATTERNBDETECT_UNCONNECTED;
wire NLW_ARG__9_PATTERNDETECT_UNCONNECTED;
wire NLW_ARG__9_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_ARG__9_ACOUT_UNCONNECTED;
wire [17:0]NLW_ARG__9_BCOUT_UNCONNECTED;
wire [3:0]NLW_ARG__9_CARRYOUT_UNCONNECTED;
wire [47:30]NLW_ARG__9_P_UNCONNECTED;
wire [47:0]NLW_ARG__9_PCOUT_UNCONNECTED;
wire [3:0]NLW_ARG_carry_O_UNCONNECTED;
wire [3:1]NLW_ARG_carry__3_CO_UNCONNECTED;
wire [3:2]NLW_ARG_carry__3_O_UNCONNECTED;
wire [3:3]NLW_add_temp_14__0_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_add_temp_14__138_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_add_temp_14__184_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_add_temp_14__230_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_add_temp_14__278_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_add_temp_14__46_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_add_temp_14__92_carry__2_CO_UNCONNECTED;
wire NLW_mul_temp_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_PCOUT_UNCONNECTED;
wire NLW_mul_temp_1_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_1_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_1_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_1_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_1_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_1_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_1_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_1_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_1_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_1_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_1_PCOUT_UNCONNECTED;
wire NLW_mul_temp_10_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_10_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_10_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_10_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_10_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_10_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_10_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_10_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_10_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_10_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_10_PCOUT_UNCONNECTED;
wire NLW_mul_temp_11_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_11_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_11_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_11_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_11_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_11_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_11_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_11_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_11_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_11_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_11_PCOUT_UNCONNECTED;
wire NLW_mul_temp_12_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_12_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_12_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_12_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_12_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_12_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_12_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_12_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_12_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_12_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_12_PCOUT_UNCONNECTED;
wire NLW_mul_temp_13_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_13_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_13_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_13_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_13_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_13_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_13_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_13_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_13_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_13_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_13_PCOUT_UNCONNECTED;
wire NLW_mul_temp_14_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_14_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_14_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_14_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_14_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_14_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_14_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_14_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_14_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_14_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_14_PCOUT_UNCONNECTED;
wire NLW_mul_temp_15_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_15_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_15_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_15_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_15_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_15_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_15_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_15_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_15_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_15_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_15_PCOUT_UNCONNECTED;
wire NLW_mul_temp_17_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_17_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_17_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_17_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_17_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_17_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_17_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_17_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_17_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_17_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_17_PCOUT_UNCONNECTED;
wire NLW_mul_temp_18_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_18_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_18_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_18_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_18_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_18_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_18_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_18_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_18_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_18_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_18_PCOUT_UNCONNECTED;
wire NLW_mul_temp_19_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_19_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_19_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_19_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_19_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_19_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_19_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_19_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_19_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_19_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_19_PCOUT_UNCONNECTED;
wire NLW_mul_temp_2_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_2_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_2_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_2_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_2_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_2_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_2_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_2_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_2_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_2_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_2_PCOUT_UNCONNECTED;
wire NLW_mul_temp_20_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_20_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_20_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_20_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_20_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_20_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_20_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_20_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_20_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_20_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_20_PCOUT_UNCONNECTED;
wire NLW_mul_temp_21_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_21_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_21_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_21_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_21_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_21_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_21_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_21_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_21_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_21_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_21_PCOUT_UNCONNECTED;
wire NLW_mul_temp_22_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_22_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_22_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_22_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_22_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_22_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_22_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_22_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_22_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_22_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_22_PCOUT_UNCONNECTED;
wire NLW_mul_temp_23_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_23_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_23_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_23_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_23_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_23_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_23_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_23_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_23_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_23_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_23_PCOUT_UNCONNECTED;
wire NLW_mul_temp_24_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_24_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_24_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_24_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_24_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_24_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_24_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_24_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_24_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_24_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_24_PCOUT_UNCONNECTED;
wire NLW_mul_temp_25_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_25_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_25_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_25_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_25_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_25_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_25_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_25_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_25_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_25_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_25_PCOUT_UNCONNECTED;
wire NLW_mul_temp_26_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_26_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_26_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_26_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_26_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_26_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_26_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_26_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_26_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_26_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_26_PCOUT_UNCONNECTED;
wire NLW_mul_temp_27_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_27_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_27_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_27_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_27_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_27_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_27_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_27_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_27_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_27_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_27_PCOUT_UNCONNECTED;
wire NLW_mul_temp_28_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_28_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_28_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_28_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_28_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_28_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_28_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_28_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_28_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_28_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_28_PCOUT_UNCONNECTED;
wire NLW_mul_temp_29_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_29_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_29_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_29_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_29_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_29_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_29_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_29_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_29_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_29_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_29_PCOUT_UNCONNECTED;
wire NLW_mul_temp_3_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_3_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_3_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_3_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_3_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_3_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_3_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_3_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_3_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_3_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_3_PCOUT_UNCONNECTED;
wire NLW_mul_temp_30_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_30_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_30_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_30_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_30_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_30_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_30_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_30_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_30_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_30_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_30_PCOUT_UNCONNECTED;
wire NLW_mul_temp_31_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_31_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_31_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_31_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_31_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_31_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_31_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_31_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_31_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_31_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_31_PCOUT_UNCONNECTED;
wire NLW_mul_temp_32_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_32_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_32_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_32_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_32_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_32_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_32_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_32_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_32_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_32_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_32_PCOUT_UNCONNECTED;
wire NLW_mul_temp_4_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_4_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_4_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_4_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_4_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_4_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_4_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_4_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_4_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_4_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_4_PCOUT_UNCONNECTED;
wire NLW_mul_temp_5_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_5_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_5_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_5_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_5_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_5_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_5_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_5_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_5_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_5_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_5_PCOUT_UNCONNECTED;
wire NLW_mul_temp_6_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_6_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_6_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_6_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_6_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_6_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_6_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_6_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_6_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_6_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_6_PCOUT_UNCONNECTED;
wire NLW_mul_temp_7_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_7_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_7_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_7_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_7_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_7_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_7_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_7_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_7_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_7_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_7_PCOUT_UNCONNECTED;
wire NLW_mul_temp_8_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_8_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_8_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_8_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_8_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_8_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_8_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_8_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_8_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_8_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_8_PCOUT_UNCONNECTED;
wire NLW_mul_temp_9_CARRYCASCOUT_UNCONNECTED;
wire NLW_mul_temp_9_MULTSIGNOUT_UNCONNECTED;
wire NLW_mul_temp_9_OVERFLOW_UNCONNECTED;
wire NLW_mul_temp_9_PATTERNBDETECT_UNCONNECTED;
wire NLW_mul_temp_9_PATTERNDETECT_UNCONNECTED;
wire NLW_mul_temp_9_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_mul_temp_9_ACOUT_UNCONNECTED;
wire [17:0]NLW_mul_temp_9_BCOUT_UNCONNECTED;
wire [3:0]NLW_mul_temp_9_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_mul_temp_9_P_UNCONNECTED;
wire [47:0]NLW_mul_temp_9_PCOUT_UNCONNECTED;
wire [3:3]NLW_sub_temp_carry__2_CO_UNCONNECTED;
wire [3:3]\NLW_weight_reg[0][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[10][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[11][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[12][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[13][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[14][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[15][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[1][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[2][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[3][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[4][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[5][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[6][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[7][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[8][12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_weight_reg[9][12]_i_1_CO_UNCONNECTED ;
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG
(.A({\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_18 ,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0,ARG_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG_OVERFLOW_UNCONNECTED),
.P({NLW_ARG_P_UNCONNECTED[47:30],in,ARG_n_92,ARG_n_93,ARG_n_94,ARG_n_95,ARG_n_96,ARG_n_97,ARG_n_98,ARG_n_99,ARG_n_100,ARG_n_101,ARG_n_102,ARG_n_103,ARG_n_104,ARG_n_105}),
.PATTERNBDETECT(NLW_ARG_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__0
(.A({\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__0_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[1]_0 [15],\weight_reg[1]_0 [15],\weight_reg[1]_0 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__0_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_1 ,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0,ARG__0_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__0_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__0_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__0_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__0_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__0_P_UNCONNECTED[47:30],RESIZE16,ARG__0_n_92,ARG__0_n_93,ARG__0_n_94,ARG__0_n_95,ARG__0_n_96,ARG__0_n_97,ARG__0_n_98,ARG__0_n_99,ARG__0_n_100,ARG__0_n_101,ARG__0_n_102,ARG__0_n_103,ARG__0_n_104,ARG__0_n_105}),
.PATTERNBDETECT(NLW_ARG__0_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__0_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__0_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__0_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__0_i_1
(.I0(\^mul_temp_1 ),
.O(ARG__0_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__1
(.A({\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__1_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__1_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_19 ,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0,ARG__1_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__1_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__1_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__1_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__1_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__1_P_UNCONNECTED[47:30],ARG__1_n_76,ARG__1_n_77,ARG__1_n_78,ARG__1_n_79,ARG__1_n_80,ARG__1_n_81,ARG__1_n_82,ARG__1_n_83,ARG__1_n_84,ARG__1_n_85,ARG__1_n_86,ARG__1_n_87,ARG__1_n_88,ARG__1_n_89,ARG__1_n_90,ARG__1_n_91,ARG__1_n_92,ARG__1_n_93,ARG__1_n_94,ARG__1_n_95,ARG__1_n_96,ARG__1_n_97,ARG__1_n_98,ARG__1_n_99,ARG__1_n_100,ARG__1_n_101,ARG__1_n_102,ARG__1_n_103,ARG__1_n_104,ARG__1_n_105}),
.PATTERNBDETECT(NLW_ARG__1_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__1_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__1_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__1_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__10
(.A({\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__10_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[6]_5 [15],\weight_reg[6]_5 [15],\weight_reg[6]_5 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__10_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_6 ,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0,ARG__10_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__10_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__10_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__10_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__10_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__10_P_UNCONNECTED[47:30],RESIZE26,ARG__10_n_92,ARG__10_n_93,ARG__10_n_94,ARG__10_n_95,ARG__10_n_96,ARG__10_n_97,ARG__10_n_98,ARG__10_n_99,ARG__10_n_100,ARG__10_n_101,ARG__10_n_102,ARG__10_n_103,ARG__10_n_104,ARG__10_n_105}),
.PATTERNBDETECT(NLW_ARG__10_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__10_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__10_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__10_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__10_i_1
(.I0(\^mul_temp_6 ),
.O(ARG__10_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__11
(.A({\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__11_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__11_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_24 ,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0,ARG__11_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__11_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__11_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__11_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__11_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__11_P_UNCONNECTED[47:30],ARG__11_n_76,ARG__11_n_77,ARG__11_n_78,ARG__11_n_79,ARG__11_n_80,ARG__11_n_81,ARG__11_n_82,ARG__11_n_83,ARG__11_n_84,ARG__11_n_85,ARG__11_n_86,ARG__11_n_87,ARG__11_n_88,ARG__11_n_89,ARG__11_n_90,ARG__11_n_91,ARG__11_n_92,ARG__11_n_93,ARG__11_n_94,ARG__11_n_95,ARG__11_n_96,ARG__11_n_97,ARG__11_n_98,ARG__11_n_99,ARG__11_n_100,ARG__11_n_101,ARG__11_n_102,ARG__11_n_103,ARG__11_n_104,ARG__11_n_105}),
.PATTERNBDETECT(NLW_ARG__11_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__11_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__11_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__11_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__11_i_1
(.I0(\^mul_temp_24 ),
.O(ARG__11_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__12
(.A({\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__12_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[7]_6 [15],\weight_reg[7]_6 [15],\weight_reg[7]_6 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__12_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_7 ,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0,ARG__12_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__12_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__12_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__12_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__12_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__12_P_UNCONNECTED[47:30],RESIZE28,ARG__12_n_92,ARG__12_n_93,ARG__12_n_94,ARG__12_n_95,ARG__12_n_96,ARG__12_n_97,ARG__12_n_98,ARG__12_n_99,ARG__12_n_100,ARG__12_n_101,ARG__12_n_102,ARG__12_n_103,ARG__12_n_104,ARG__12_n_105}),
.PATTERNBDETECT(NLW_ARG__12_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__12_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__12_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__12_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__12_i_1
(.I0(\^mul_temp_7 ),
.O(ARG__12_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__13
(.A({\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__13_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__13_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_25 ,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0,ARG__13_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__13_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__13_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__13_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__13_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__13_P_UNCONNECTED[47:30],ARG__13_n_76,ARG__13_n_77,ARG__13_n_78,ARG__13_n_79,ARG__13_n_80,ARG__13_n_81,ARG__13_n_82,ARG__13_n_83,ARG__13_n_84,ARG__13_n_85,ARG__13_n_86,ARG__13_n_87,ARG__13_n_88,ARG__13_n_89,ARG__13_n_90,ARG__13_n_91,ARG__13_n_92,ARG__13_n_93,ARG__13_n_94,ARG__13_n_95,ARG__13_n_96,ARG__13_n_97,ARG__13_n_98,ARG__13_n_99,ARG__13_n_100,ARG__13_n_101,ARG__13_n_102,ARG__13_n_103,ARG__13_n_104,ARG__13_n_105}),
.PATTERNBDETECT(NLW_ARG__13_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__13_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__13_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__13_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__13_i_1
(.I0(\^mul_temp_25 ),
.O(ARG__13_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__14
(.A({\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__14_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[8]_7 [15],\weight_reg[8]_7 [15],\weight_reg[8]_7 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__14_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_8 ,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0,ARG__14_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__14_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__14_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__14_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__14_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__14_P_UNCONNECTED[47:30],RESIZE30,ARG__14_n_92,ARG__14_n_93,ARG__14_n_94,ARG__14_n_95,ARG__14_n_96,ARG__14_n_97,ARG__14_n_98,ARG__14_n_99,ARG__14_n_100,ARG__14_n_101,ARG__14_n_102,ARG__14_n_103,ARG__14_n_104,ARG__14_n_105}),
.PATTERNBDETECT(NLW_ARG__14_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__14_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__14_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__14_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__14_i_1
(.I0(\^mul_temp_8 ),
.O(ARG__14_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__15
(.A({\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__15_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__15_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_26 ,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0,ARG__15_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__15_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__15_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__15_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__15_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__15_P_UNCONNECTED[47:30],ARG__15_n_76,ARG__15_n_77,ARG__15_n_78,ARG__15_n_79,ARG__15_n_80,ARG__15_n_81,ARG__15_n_82,ARG__15_n_83,ARG__15_n_84,ARG__15_n_85,ARG__15_n_86,ARG__15_n_87,ARG__15_n_88,ARG__15_n_89,ARG__15_n_90,ARG__15_n_91,ARG__15_n_92,ARG__15_n_93,ARG__15_n_94,ARG__15_n_95,ARG__15_n_96,ARG__15_n_97,ARG__15_n_98,ARG__15_n_99,ARG__15_n_100,ARG__15_n_101,ARG__15_n_102,ARG__15_n_103,ARG__15_n_104,ARG__15_n_105}),
.PATTERNBDETECT(NLW_ARG__15_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__15_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__15_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__15_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__15_i_1
(.I0(\^mul_temp_26 ),
.O(ARG__15_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__16
(.A({\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__16_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[9]_8 [15],\weight_reg[9]_8 [15],\weight_reg[9]_8 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__16_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_9 ,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0,ARG__16_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__16_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__16_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__16_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__16_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__16_P_UNCONNECTED[47:30],RESIZE32,ARG__16_n_92,ARG__16_n_93,ARG__16_n_94,ARG__16_n_95,ARG__16_n_96,ARG__16_n_97,ARG__16_n_98,ARG__16_n_99,ARG__16_n_100,ARG__16_n_101,ARG__16_n_102,ARG__16_n_103,ARG__16_n_104,ARG__16_n_105}),
.PATTERNBDETECT(NLW_ARG__16_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__16_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__16_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__16_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__16_i_1
(.I0(\^mul_temp_9 ),
.O(ARG__16_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__17
(.A({\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__17_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__17_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_27 ,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0,ARG__17_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__17_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__17_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__17_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__17_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__17_P_UNCONNECTED[47:30],ARG__17_n_76,ARG__17_n_77,ARG__17_n_78,ARG__17_n_79,ARG__17_n_80,ARG__17_n_81,ARG__17_n_82,ARG__17_n_83,ARG__17_n_84,ARG__17_n_85,ARG__17_n_86,ARG__17_n_87,ARG__17_n_88,ARG__17_n_89,ARG__17_n_90,ARG__17_n_91,ARG__17_n_92,ARG__17_n_93,ARG__17_n_94,ARG__17_n_95,ARG__17_n_96,ARG__17_n_97,ARG__17_n_98,ARG__17_n_99,ARG__17_n_100,ARG__17_n_101,ARG__17_n_102,ARG__17_n_103,ARG__17_n_104,ARG__17_n_105}),
.PATTERNBDETECT(NLW_ARG__17_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__17_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__17_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__17_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__17_i_1
(.I0(\^mul_temp_27 ),
.O(ARG__17_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__18
(.A({\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__18_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[10]_9 [15],\weight_reg[10]_9 [15],\weight_reg[10]_9 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__18_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_10 ,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0,ARG__18_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__18_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__18_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__18_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__18_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__18_P_UNCONNECTED[47:30],RESIZE34,ARG__18_n_92,ARG__18_n_93,ARG__18_n_94,ARG__18_n_95,ARG__18_n_96,ARG__18_n_97,ARG__18_n_98,ARG__18_n_99,ARG__18_n_100,ARG__18_n_101,ARG__18_n_102,ARG__18_n_103,ARG__18_n_104,ARG__18_n_105}),
.PATTERNBDETECT(NLW_ARG__18_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__18_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__18_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__18_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__18_i_1
(.I0(\^mul_temp_10 ),
.O(ARG__18_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__19
(.A({\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__19_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__19_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_28 ,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0,ARG__19_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__19_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__19_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__19_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__19_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__19_P_UNCONNECTED[47:30],ARG__19_n_76,ARG__19_n_77,ARG__19_n_78,ARG__19_n_79,ARG__19_n_80,ARG__19_n_81,ARG__19_n_82,ARG__19_n_83,ARG__19_n_84,ARG__19_n_85,ARG__19_n_86,ARG__19_n_87,ARG__19_n_88,ARG__19_n_89,ARG__19_n_90,ARG__19_n_91,ARG__19_n_92,ARG__19_n_93,ARG__19_n_94,ARG__19_n_95,ARG__19_n_96,ARG__19_n_97,ARG__19_n_98,ARG__19_n_99,ARG__19_n_100,ARG__19_n_101,ARG__19_n_102,ARG__19_n_103,ARG__19_n_104,ARG__19_n_105}),
.PATTERNBDETECT(NLW_ARG__19_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__19_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__19_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__19_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__19_i_1
(.I0(\^mul_temp_28 ),
.O(ARG__19_i_1_n_0));
LUT1 #(
.INIT(2'h1))
ARG__1_i_1
(.I0(\^mul_temp_19 ),
.O(ARG__1_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__2
(.A({\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__2_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[2]_1 [15],\weight_reg[2]_1 [15],\weight_reg[2]_1 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__2_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_2 ,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0,ARG__2_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__2_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__2_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__2_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__2_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__2_P_UNCONNECTED[47:30],RESIZE18,ARG__2_n_92,ARG__2_n_93,ARG__2_n_94,ARG__2_n_95,ARG__2_n_96,ARG__2_n_97,ARG__2_n_98,ARG__2_n_99,ARG__2_n_100,ARG__2_n_101,ARG__2_n_102,ARG__2_n_103,ARG__2_n_104,ARG__2_n_105}),
.PATTERNBDETECT(NLW_ARG__2_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__2_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__2_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__2_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__20
(.A({\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__20_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[11]_10 [15],\weight_reg[11]_10 [15],\weight_reg[11]_10 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__20_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_11 ,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0,ARG__20_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__20_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__20_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__20_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__20_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__20_P_UNCONNECTED[47:30],RESIZE36,ARG__20_n_92,ARG__20_n_93,ARG__20_n_94,ARG__20_n_95,ARG__20_n_96,ARG__20_n_97,ARG__20_n_98,ARG__20_n_99,ARG__20_n_100,ARG__20_n_101,ARG__20_n_102,ARG__20_n_103,ARG__20_n_104,ARG__20_n_105}),
.PATTERNBDETECT(NLW_ARG__20_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__20_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__20_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__20_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__20_i_1
(.I0(\^mul_temp_11 ),
.O(ARG__20_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__21
(.A({\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__21_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__21_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_29 ,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0,ARG__21_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__21_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__21_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__21_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__21_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__21_P_UNCONNECTED[47:30],ARG__21_n_76,ARG__21_n_77,ARG__21_n_78,ARG__21_n_79,ARG__21_n_80,ARG__21_n_81,ARG__21_n_82,ARG__21_n_83,ARG__21_n_84,ARG__21_n_85,ARG__21_n_86,ARG__21_n_87,ARG__21_n_88,ARG__21_n_89,ARG__21_n_90,ARG__21_n_91,ARG__21_n_92,ARG__21_n_93,ARG__21_n_94,ARG__21_n_95,ARG__21_n_96,ARG__21_n_97,ARG__21_n_98,ARG__21_n_99,ARG__21_n_100,ARG__21_n_101,ARG__21_n_102,ARG__21_n_103,ARG__21_n_104,ARG__21_n_105}),
.PATTERNBDETECT(NLW_ARG__21_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__21_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__21_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__21_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__21_i_1
(.I0(\^mul_temp_29 ),
.O(ARG__21_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__22
(.A({\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__22_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[12]_11 [15],\weight_reg[12]_11 [15],\weight_reg[12]_11 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__22_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_12 ,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0,ARG__22_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__22_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__22_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__22_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__22_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__22_P_UNCONNECTED[47:30],RESIZE38,ARG__22_n_92,ARG__22_n_93,ARG__22_n_94,ARG__22_n_95,ARG__22_n_96,ARG__22_n_97,ARG__22_n_98,ARG__22_n_99,ARG__22_n_100,ARG__22_n_101,ARG__22_n_102,ARG__22_n_103,ARG__22_n_104,ARG__22_n_105}),
.PATTERNBDETECT(NLW_ARG__22_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__22_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__22_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__22_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__22_i_1
(.I0(\^mul_temp_12 ),
.O(ARG__22_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__23
(.A({\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__23_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__23_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_30 ,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0,ARG__23_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__23_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__23_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__23_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__23_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__23_P_UNCONNECTED[47:30],ARG__23_n_76,ARG__23_n_77,ARG__23_n_78,ARG__23_n_79,ARG__23_n_80,ARG__23_n_81,ARG__23_n_82,ARG__23_n_83,ARG__23_n_84,ARG__23_n_85,ARG__23_n_86,ARG__23_n_87,ARG__23_n_88,ARG__23_n_89,ARG__23_n_90,ARG__23_n_91,ARG__23_n_92,ARG__23_n_93,ARG__23_n_94,ARG__23_n_95,ARG__23_n_96,ARG__23_n_97,ARG__23_n_98,ARG__23_n_99,ARG__23_n_100,ARG__23_n_101,ARG__23_n_102,ARG__23_n_103,ARG__23_n_104,ARG__23_n_105}),
.PATTERNBDETECT(NLW_ARG__23_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__23_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__23_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__23_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__23_i_1
(.I0(\^mul_temp_30 ),
.O(ARG__23_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__24
(.A({\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__24_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[13]_12 [15],\weight_reg[13]_12 [15],\weight_reg[13]_12 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__24_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_13 ,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0,ARG__24_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__24_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__24_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__24_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__24_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__24_P_UNCONNECTED[47:30],RESIZE40,ARG__24_n_92,ARG__24_n_93,ARG__24_n_94,ARG__24_n_95,ARG__24_n_96,ARG__24_n_97,ARG__24_n_98,ARG__24_n_99,ARG__24_n_100,ARG__24_n_101,ARG__24_n_102,ARG__24_n_103,ARG__24_n_104,ARG__24_n_105}),
.PATTERNBDETECT(NLW_ARG__24_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__24_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__24_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__24_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__24_i_1
(.I0(\^mul_temp_13 ),
.O(ARG__24_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__25
(.A({\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__25_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__25_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_31 ,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0,ARG__25_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__25_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__25_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__25_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__25_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__25_P_UNCONNECTED[47:30],ARG__25_n_76,ARG__25_n_77,ARG__25_n_78,ARG__25_n_79,ARG__25_n_80,ARG__25_n_81,ARG__25_n_82,ARG__25_n_83,ARG__25_n_84,ARG__25_n_85,ARG__25_n_86,ARG__25_n_87,ARG__25_n_88,ARG__25_n_89,ARG__25_n_90,ARG__25_n_91,ARG__25_n_92,ARG__25_n_93,ARG__25_n_94,ARG__25_n_95,ARG__25_n_96,ARG__25_n_97,ARG__25_n_98,ARG__25_n_99,ARG__25_n_100,ARG__25_n_101,ARG__25_n_102,ARG__25_n_103,ARG__25_n_104,ARG__25_n_105}),
.PATTERNBDETECT(NLW_ARG__25_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__25_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__25_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__25_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__25_i_1
(.I0(\^mul_temp_31 ),
.O(ARG__25_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__26
(.A({\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__26_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[14]_13 [15],\weight_reg[14]_13 [15],\weight_reg[14]_13 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__26_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_14 ,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0,ARG__26_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__26_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__26_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__26_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__26_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__26_P_UNCONNECTED[47:30],RESIZE42,ARG__26_n_92,ARG__26_n_93,ARG__26_n_94,ARG__26_n_95,ARG__26_n_96,ARG__26_n_97,ARG__26_n_98,ARG__26_n_99,ARG__26_n_100,ARG__26_n_101,ARG__26_n_102,ARG__26_n_103,ARG__26_n_104,ARG__26_n_105}),
.PATTERNBDETECT(NLW_ARG__26_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__26_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__26_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__26_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__26_i_1
(.I0(\^mul_temp_14 ),
.O(ARG__26_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__27
(.A({\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__27_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__27_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_32 ,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0,ARG__27_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__27_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__27_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__27_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__27_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__27_P_UNCONNECTED[47:30],ARG__27_n_76,ARG__27_n_77,ARG__27_n_78,ARG__27_n_79,ARG__27_n_80,ARG__27_n_81,ARG__27_n_82,ARG__27_n_83,ARG__27_n_84,ARG__27_n_85,ARG__27_n_86,ARG__27_n_87,ARG__27_n_88,ARG__27_n_89,ARG__27_n_90,ARG__27_n_91,ARG__27_n_92,ARG__27_n_93,ARG__27_n_94,ARG__27_n_95,ARG__27_n_96,ARG__27_n_97,ARG__27_n_98,ARG__27_n_99,ARG__27_n_100,ARG__27_n_101,ARG__27_n_102,ARG__27_n_103,ARG__27_n_104,ARG__27_n_105}),
.PATTERNBDETECT(NLW_ARG__27_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__27_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__27_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__27_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__27_i_1
(.I0(\^mul_temp_32 ),
.O(ARG__27_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__28
(.A({\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__28_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[15]_14 [15],\weight_reg[15]_14 [15],\weight_reg[15]_14 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__28_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_15 ,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0,ARG__28_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__28_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__28_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__28_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__28_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__28_P_UNCONNECTED[47:30],RESIZE44,ARG__28_n_92,ARG__28_n_93,ARG__28_n_94,ARG__28_n_95,ARG__28_n_96,ARG__28_n_97,ARG__28_n_98,ARG__28_n_99,ARG__28_n_100,ARG__28_n_101,ARG__28_n_102,ARG__28_n_103,ARG__28_n_104,ARG__28_n_105}),
.PATTERNBDETECT(NLW_ARG__28_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__28_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__28_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__28_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__28_i_1
(.I0(\^mul_temp_15 ),
.O(ARG__28_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__29
(.A({\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__29_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__29_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_17 ,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0,ARG__29_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__29_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__29_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__29_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__29_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__29_P_UNCONNECTED[47:30],ARG__29_n_76,ARG__29_n_77,ARG__29_n_78,ARG__29_n_79,ARG__29_n_80,ARG__29_n_81,ARG__29_n_82,ARG__29_n_83,ARG__29_n_84,ARG__29_n_85,ARG__29_n_86,ARG__29_n_87,ARG__29_n_88,ARG__29_n_89,ARG__29_n_90,ARG__29_n_91,ARG__29_n_92,ARG__29_n_93,ARG__29_n_94,ARG__29_n_95,ARG__29_n_96,ARG__29_n_97,ARG__29_n_98,ARG__29_n_99,ARG__29_n_100,ARG__29_n_101,ARG__29_n_102,ARG__29_n_103,ARG__29_n_104,ARG__29_n_105}),
.PATTERNBDETECT(NLW_ARG__29_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__29_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__29_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__29_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__29_i_1
(.I0(\^mul_temp_17 ),
.O(ARG__29_i_1_n_0));
LUT1 #(
.INIT(2'h1))
ARG__2_i_1
(.I0(\^mul_temp_2 ),
.O(ARG__2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__3
(.A({\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__3_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__3_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_20 ,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0,ARG__3_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__3_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__3_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__3_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__3_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__3_P_UNCONNECTED[47:30],ARG__3_n_76,ARG__3_n_77,ARG__3_n_78,ARG__3_n_79,ARG__3_n_80,ARG__3_n_81,ARG__3_n_82,ARG__3_n_83,ARG__3_n_84,ARG__3_n_85,ARG__3_n_86,ARG__3_n_87,ARG__3_n_88,ARG__3_n_89,ARG__3_n_90,ARG__3_n_91,ARG__3_n_92,ARG__3_n_93,ARG__3_n_94,ARG__3_n_95,ARG__3_n_96,ARG__3_n_97,ARG__3_n_98,ARG__3_n_99,ARG__3_n_100,ARG__3_n_101,ARG__3_n_102,ARG__3_n_103,ARG__3_n_104,ARG__3_n_105}),
.PATTERNBDETECT(NLW_ARG__3_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__3_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__3_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__3_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__30
(.A({\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__30_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[0]_15 [15],\weight_reg[0]_15 [15],\weight_reg[0]_15 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__30_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp ,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0,ARG__30_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__30_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__30_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__30_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__30_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__30_P_UNCONNECTED[47:30],RESIZE15,ARG__30_n_92,ARG__30_n_93,ARG__30_n_94,ARG__30_n_95,ARG__30_n_96,ARG__30_n_97,ARG__30_n_98,ARG__30_n_99,ARG__30_n_100,ARG__30_n_101,ARG__30_n_102,ARG__30_n_103,ARG__30_n_104,ARG__30_n_105}),
.PATTERNBDETECT(NLW_ARG__30_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__30_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__30_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__30_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__30_i_1
(.I0(\^mul_temp ),
.O(ARG__30_i_1_n_0));
LUT1 #(
.INIT(2'h1))
ARG__3_i_1
(.I0(\^mul_temp_20 ),
.O(ARG__3_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__4
(.A({\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__4_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[3]_2 [15],\weight_reg[3]_2 [15],\weight_reg[3]_2 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__4_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_3 ,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0,ARG__4_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__4_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__4_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__4_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__4_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__4_P_UNCONNECTED[47:30],RESIZE20,ARG__4_n_92,ARG__4_n_93,ARG__4_n_94,ARG__4_n_95,ARG__4_n_96,ARG__4_n_97,ARG__4_n_98,ARG__4_n_99,ARG__4_n_100,ARG__4_n_101,ARG__4_n_102,ARG__4_n_103,ARG__4_n_104,ARG__4_n_105}),
.PATTERNBDETECT(NLW_ARG__4_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__4_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__4_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__4_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__4_i_1
(.I0(\^mul_temp_3 ),
.O(ARG__4_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__5
(.A({\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__5_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__5_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_21 ,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0,ARG__5_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__5_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__5_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__5_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__5_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__5_P_UNCONNECTED[47:30],ARG__5_n_76,ARG__5_n_77,ARG__5_n_78,ARG__5_n_79,ARG__5_n_80,ARG__5_n_81,ARG__5_n_82,ARG__5_n_83,ARG__5_n_84,ARG__5_n_85,ARG__5_n_86,ARG__5_n_87,ARG__5_n_88,ARG__5_n_89,ARG__5_n_90,ARG__5_n_91,ARG__5_n_92,ARG__5_n_93,ARG__5_n_94,ARG__5_n_95,ARG__5_n_96,ARG__5_n_97,ARG__5_n_98,ARG__5_n_99,ARG__5_n_100,ARG__5_n_101,ARG__5_n_102,ARG__5_n_103,ARG__5_n_104,ARG__5_n_105}),
.PATTERNBDETECT(NLW_ARG__5_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__5_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__5_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__5_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__5_i_1
(.I0(\^mul_temp_21 ),
.O(ARG__5_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__6
(.A({\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__6_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[4]_3 [15],\weight_reg[4]_3 [15],\weight_reg[4]_3 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__6_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_4 ,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0,ARG__6_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__6_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__6_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__6_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__6_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__6_P_UNCONNECTED[47:30],RESIZE22,ARG__6_n_92,ARG__6_n_93,ARG__6_n_94,ARG__6_n_95,ARG__6_n_96,ARG__6_n_97,ARG__6_n_98,ARG__6_n_99,ARG__6_n_100,ARG__6_n_101,ARG__6_n_102,ARG__6_n_103,ARG__6_n_104,ARG__6_n_105}),
.PATTERNBDETECT(NLW_ARG__6_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__6_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__6_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__6_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__6_i_1
(.I0(\^mul_temp_4 ),
.O(ARG__6_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__7
(.A({\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__7_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__7_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_22 ,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0,ARG__7_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__7_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__7_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__7_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__7_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__7_P_UNCONNECTED[47:30],ARG__7_n_76,ARG__7_n_77,ARG__7_n_78,ARG__7_n_79,ARG__7_n_80,ARG__7_n_81,ARG__7_n_82,ARG__7_n_83,ARG__7_n_84,ARG__7_n_85,ARG__7_n_86,ARG__7_n_87,ARG__7_n_88,ARG__7_n_89,ARG__7_n_90,ARG__7_n_91,ARG__7_n_92,ARG__7_n_93,ARG__7_n_94,ARG__7_n_95,ARG__7_n_96,ARG__7_n_97,ARG__7_n_98,ARG__7_n_99,ARG__7_n_100,ARG__7_n_101,ARG__7_n_102,ARG__7_n_103,ARG__7_n_104,ARG__7_n_105}),
.PATTERNBDETECT(NLW_ARG__7_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__7_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__7_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__7_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__7_i_1
(.I0(\^mul_temp_22 ),
.O(ARG__7_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__8
(.A({\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__8_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[5]_4 [15],\weight_reg[5]_4 [15],\weight_reg[5]_4 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__8_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_5 ,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0,ARG__8_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__8_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__8_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__8_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__8_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__8_P_UNCONNECTED[47:30],RESIZE24,ARG__8_n_92,ARG__8_n_93,ARG__8_n_94,ARG__8_n_95,ARG__8_n_96,ARG__8_n_97,ARG__8_n_98,ARG__8_n_99,ARG__8_n_100,ARG__8_n_101,ARG__8_n_102,ARG__8_n_103,ARG__8_n_104,ARG__8_n_105}),
.PATTERNBDETECT(NLW_ARG__8_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__8_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__8_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__8_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__8_i_1
(.I0(\^mul_temp_5 ),
.O(ARG__8_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
ARG__9
(.A({\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_ARG__9_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_ARG__9_BCOUT_UNCONNECTED[17:0]),
.C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^mul_temp_23 ,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0,ARG__9_i_1_n_0}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_ARG__9_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_ARG__9_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_ARG__9_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_ARG__9_OVERFLOW_UNCONNECTED),
.P({NLW_ARG__9_P_UNCONNECTED[47:30],ARG__9_n_76,ARG__9_n_77,ARG__9_n_78,ARG__9_n_79,ARG__9_n_80,ARG__9_n_81,ARG__9_n_82,ARG__9_n_83,ARG__9_n_84,ARG__9_n_85,ARG__9_n_86,ARG__9_n_87,ARG__9_n_88,ARG__9_n_89,ARG__9_n_90,ARG__9_n_91,ARG__9_n_92,ARG__9_n_93,ARG__9_n_94,ARG__9_n_95,ARG__9_n_96,ARG__9_n_97,ARG__9_n_98,ARG__9_n_99,ARG__9_n_100,ARG__9_n_101,ARG__9_n_102,ARG__9_n_103,ARG__9_n_104,ARG__9_n_105}),
.PATTERNBDETECT(NLW_ARG__9_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_ARG__9_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_ARG__9_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_ARG__9_UNDERFLOW_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ARG__9_i_1
(.I0(\^mul_temp_23 ),
.O(ARG__9_i_1_n_0));
CARRY4 ARG_carry
(.CI(1'b0),
.CO({ARG_carry_n_0,ARG_carry_n_1,ARG_carry_n_2,ARG_carry_n_3}),
.CYINIT(1'b0),
.DI({1'b0,mul_temp_16[1:0],1'b1}),
.O(NLW_ARG_carry_O_UNCONNECTED[3:0]),
.S({mul_temp_16[2],\write_reg_d_k_reg[3] }));
CARRY4 ARG_carry__0
(.CI(ARG_carry_n_0),
.CO({ARG_carry__0_n_0,ARG_carry__0_n_1,ARG_carry__0_n_2,ARG_carry__0_n_3}),
.CYINIT(1'b0),
.DI({mul_temp_16[5],mul_temp_16[3],mul_temp_16[4],DI}),
.O(ARG__31[20:17]),
.S({ARG_carry__0_i_2_n_0,ARG_carry__0_i_3_n_0,ARG_carry__0_i_4_n_0,mul_temp_16[3]}));
LUT2 #(
.INIT(4'h9))
ARG_carry__0_i_2
(.I0(mul_temp_16[5]),
.I1(mul_temp_16[6]),
.O(ARG_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__0_i_3
(.I0(mul_temp_16[3]),
.I1(mul_temp_16[5]),
.O(ARG_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__0_i_4
(.I0(mul_temp_16[3]),
.I1(mul_temp_16[4]),
.O(ARG_carry__0_i_4_n_0));
CARRY4 ARG_carry__1
(.CI(ARG_carry__0_n_0),
.CO({ARG_carry__1_n_0,ARG_carry__1_n_1,ARG_carry__1_n_2,ARG_carry__1_n_3}),
.CYINIT(1'b0),
.DI(mul_temp_16[9:6]),
.O(ARG__31[24:21]),
.S({ARG_carry__1_i_1_n_0,ARG_carry__1_i_2_n_0,ARG_carry__1_i_3_n_0,ARG_carry__1_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
ARG_carry__1_i_1
(.I0(mul_temp_16[9]),
.I1(mul_temp_16[10]),
.O(ARG_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__1_i_2
(.I0(mul_temp_16[8]),
.I1(mul_temp_16[9]),
.O(ARG_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__1_i_3
(.I0(mul_temp_16[7]),
.I1(mul_temp_16[8]),
.O(ARG_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__1_i_4
(.I0(mul_temp_16[6]),
.I1(mul_temp_16[7]),
.O(ARG_carry__1_i_4_n_0));
CARRY4 ARG_carry__2
(.CI(ARG_carry__1_n_0),
.CO({ARG_carry__2_n_0,ARG_carry__2_n_1,ARG_carry__2_n_2,ARG_carry__2_n_3}),
.CYINIT(1'b0),
.DI(mul_temp_16[13:10]),
.O(ARG__31[28:25]),
.S({ARG_carry__2_i_1_n_0,ARG_carry__2_i_2_n_0,ARG_carry__2_i_3_n_0,ARG_carry__2_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
ARG_carry__2_i_1
(.I0(mul_temp_16[13]),
.I1(mul_temp_16[14]),
.O(ARG_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__2_i_2
(.I0(mul_temp_16[12]),
.I1(mul_temp_16[13]),
.O(ARG_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__2_i_3
(.I0(mul_temp_16[11]),
.I1(mul_temp_16[12]),
.O(ARG_carry__2_i_3_n_0));
LUT2 #(
.INIT(4'h9))
ARG_carry__2_i_4
(.I0(mul_temp_16[10]),
.I1(mul_temp_16[11]),
.O(ARG_carry__2_i_4_n_0));
CARRY4 ARG_carry__3
(.CI(ARG_carry__2_n_0),
.CO({NLW_ARG_carry__3_CO_UNCONNECTED[3:1],ARG_carry__3_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,mul_temp_16[14]}),
.O({NLW_ARG_carry__3_O_UNCONNECTED[3:2],ARG__31[32],ARG__31[29]}),
.S({1'b0,1'b0,1'b1,ARG_carry__3_i_1_n_0}));
LUT2 #(
.INIT(4'h9))
ARG_carry__3_i_1
(.I0(mul_temp_16[14]),
.I1(mul_temp_16[15]),
.O(ARG_carry__3_i_1_n_0));
LUT1 #(
.INIT(2'h1))
ARG_i_1
(.I0(\^mul_temp_18 ),
.O(ARG_i_1_n_0));
CARRY4 add_temp_14__0_carry
(.CI(1'b0),
.CO({add_temp_14__0_carry_n_0,add_temp_14__0_carry_n_1,add_temp_14__0_carry_n_2,add_temp_14__0_carry_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__0_carry_i_1_n_0,add_temp_14__0_carry_i_2_n_0,add_temp_14__0_carry_i_3_n_0,1'b0}),
.O({add_temp_14__0_carry_n_4,add_temp_14__0_carry_n_5,add_temp_14__0_carry_n_6,add_temp_14__0_carry_n_7}),
.S({add_temp_14__0_carry_i_4_n_0,add_temp_14__0_carry_i_5_n_0,add_temp_14__0_carry_i_6_n_0,add_temp_14__0_carry_i_7_n_0}));
CARRY4 add_temp_14__0_carry__0
(.CI(add_temp_14__0_carry_n_0),
.CO({add_temp_14__0_carry__0_n_0,add_temp_14__0_carry__0_n_1,add_temp_14__0_carry__0_n_2,add_temp_14__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__0_carry__0_i_1_n_0,add_temp_14__0_carry__0_i_2_n_0,add_temp_14__0_carry__0_i_3_n_0,add_temp_14__0_carry__0_i_4_n_0}),
.O({add_temp_14__0_carry__0_n_4,add_temp_14__0_carry__0_n_5,add_temp_14__0_carry__0_n_6,add_temp_14__0_carry__0_n_7}),
.S({add_temp_14__0_carry__0_i_5_n_0,add_temp_14__0_carry__0_i_6_n_0,add_temp_14__0_carry__0_i_7_n_0,add_temp_14__0_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair6" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__0_i_1
(.I0(RESIZE44[6]),
.I1(RESIZE15[6]),
.I2(RESIZE42[6]),
.O(add_temp_14__0_carry__0_i_1_n_0));
(* HLUTNM = "lutpair5" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__0_i_2
(.I0(RESIZE44[5]),
.I1(RESIZE15[5]),
.I2(RESIZE42[5]),
.O(add_temp_14__0_carry__0_i_2_n_0));
(* HLUTNM = "lutpair4" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__0_i_3
(.I0(RESIZE44[4]),
.I1(RESIZE15[4]),
.I2(RESIZE42[4]),
.O(add_temp_14__0_carry__0_i_3_n_0));
(* HLUTNM = "lutpair3" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__0_i_4
(.I0(RESIZE44[3]),
.I1(RESIZE15[3]),
.I2(RESIZE42[3]),
.O(add_temp_14__0_carry__0_i_4_n_0));
(* HLUTNM = "lutpair7" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__0_i_5
(.I0(RESIZE44[7]),
.I1(RESIZE15[7]),
.I2(RESIZE42[7]),
.I3(add_temp_14__0_carry__0_i_1_n_0),
.O(add_temp_14__0_carry__0_i_5_n_0));
(* HLUTNM = "lutpair6" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__0_i_6
(.I0(RESIZE44[6]),
.I1(RESIZE15[6]),
.I2(RESIZE42[6]),
.I3(add_temp_14__0_carry__0_i_2_n_0),
.O(add_temp_14__0_carry__0_i_6_n_0));
(* HLUTNM = "lutpair5" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__0_i_7
(.I0(RESIZE44[5]),
.I1(RESIZE15[5]),
.I2(RESIZE42[5]),
.I3(add_temp_14__0_carry__0_i_3_n_0),
.O(add_temp_14__0_carry__0_i_7_n_0));
(* HLUTNM = "lutpair4" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__0_i_8
(.I0(RESIZE44[4]),
.I1(RESIZE15[4]),
.I2(RESIZE42[4]),
.I3(add_temp_14__0_carry__0_i_4_n_0),
.O(add_temp_14__0_carry__0_i_8_n_0));
CARRY4 add_temp_14__0_carry__1
(.CI(add_temp_14__0_carry__0_n_0),
.CO({add_temp_14__0_carry__1_n_0,add_temp_14__0_carry__1_n_1,add_temp_14__0_carry__1_n_2,add_temp_14__0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__0_carry__1_i_1_n_0,add_temp_14__0_carry__1_i_2_n_0,add_temp_14__0_carry__1_i_3_n_0,add_temp_14__0_carry__1_i_4_n_0}),
.O({add_temp_14__0_carry__1_n_4,add_temp_14__0_carry__1_n_5,add_temp_14__0_carry__1_n_6,add_temp_14__0_carry__1_n_7}),
.S({add_temp_14__0_carry__1_i_5_n_0,add_temp_14__0_carry__1_i_6_n_0,add_temp_14__0_carry__1_i_7_n_0,add_temp_14__0_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair10" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__1_i_1
(.I0(RESIZE44[10]),
.I1(RESIZE42[10]),
.I2(RESIZE15[10]),
.O(add_temp_14__0_carry__1_i_1_n_0));
(* HLUTNM = "lutpair9" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__1_i_2
(.I0(RESIZE44[9]),
.I1(RESIZE42[9]),
.I2(RESIZE15[9]),
.O(add_temp_14__0_carry__1_i_2_n_0));
(* HLUTNM = "lutpair8" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__1_i_3
(.I0(RESIZE44[8]),
.I1(RESIZE15[8]),
.I2(RESIZE42[8]),
.O(add_temp_14__0_carry__1_i_3_n_0));
(* HLUTNM = "lutpair7" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__1_i_4
(.I0(RESIZE44[7]),
.I1(RESIZE15[7]),
.I2(RESIZE42[7]),
.O(add_temp_14__0_carry__1_i_4_n_0));
(* HLUTNM = "lutpair11" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__1_i_5
(.I0(RESIZE44[11]),
.I1(RESIZE15[11]),
.I2(RESIZE42[11]),
.I3(add_temp_14__0_carry__1_i_1_n_0),
.O(add_temp_14__0_carry__1_i_5_n_0));
(* HLUTNM = "lutpair10" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__1_i_6
(.I0(RESIZE44[10]),
.I1(RESIZE42[10]),
.I2(RESIZE15[10]),
.I3(add_temp_14__0_carry__1_i_2_n_0),
.O(add_temp_14__0_carry__1_i_6_n_0));
(* HLUTNM = "lutpair9" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__1_i_7
(.I0(RESIZE44[9]),
.I1(RESIZE42[9]),
.I2(RESIZE15[9]),
.I3(add_temp_14__0_carry__1_i_3_n_0),
.O(add_temp_14__0_carry__1_i_7_n_0));
(* HLUTNM = "lutpair8" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__1_i_8
(.I0(RESIZE44[8]),
.I1(RESIZE15[8]),
.I2(RESIZE42[8]),
.I3(add_temp_14__0_carry__1_i_4_n_0),
.O(add_temp_14__0_carry__1_i_8_n_0));
CARRY4 add_temp_14__0_carry__2
(.CI(add_temp_14__0_carry__1_n_0),
.CO({NLW_add_temp_14__0_carry__2_CO_UNCONNECTED[3],add_temp_14__0_carry__2_n_1,add_temp_14__0_carry__2_n_2,add_temp_14__0_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,add_temp_14__0_carry__2_i_1_n_0,add_temp_14__0_carry__2_i_2_n_0,add_temp_14__0_carry__2_i_3_n_0}),
.O({add_temp_14__0_carry__2_n_4,add_temp_14__0_carry__2_n_5,add_temp_14__0_carry__2_n_6,add_temp_14__0_carry__2_n_7}),
.S({add_temp_14__0_carry__2_i_4_n_0,add_temp_14__0_carry__2_i_5_n_0,add_temp_14__0_carry__2_i_6_n_0,add_temp_14__0_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair13" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__2_i_1
(.I0(RESIZE15[13]),
.I1(RESIZE42[13]),
.I2(RESIZE44[13]),
.O(add_temp_14__0_carry__2_i_1_n_0));
(* HLUTNM = "lutpair12" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__2_i_2
(.I0(RESIZE44[12]),
.I1(RESIZE15[12]),
.I2(RESIZE42[12]),
.O(add_temp_14__0_carry__2_i_2_n_0));
(* HLUTNM = "lutpair11" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry__2_i_3
(.I0(RESIZE44[11]),
.I1(RESIZE15[11]),
.I2(RESIZE42[11]),
.O(add_temp_14__0_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h17E8E817E81717E8))
add_temp_14__0_carry__2_i_4
(.I0(RESIZE15[14]),
.I1(RESIZE44[14]),
.I2(RESIZE42[14]),
.I3(RESIZE44[15]),
.I4(RESIZE42[15]),
.I5(RESIZE15[15]),
.O(add_temp_14__0_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__2_i_5
(.I0(add_temp_14__0_carry__2_i_1_n_0),
.I1(RESIZE44[14]),
.I2(RESIZE42[14]),
.I3(RESIZE15[14]),
.O(add_temp_14__0_carry__2_i_5_n_0));
(* HLUTNM = "lutpair13" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__2_i_6
(.I0(RESIZE15[13]),
.I1(RESIZE42[13]),
.I2(RESIZE44[13]),
.I3(add_temp_14__0_carry__2_i_2_n_0),
.O(add_temp_14__0_carry__2_i_6_n_0));
(* HLUTNM = "lutpair12" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry__2_i_7
(.I0(RESIZE44[12]),
.I1(RESIZE15[12]),
.I2(RESIZE42[12]),
.I3(add_temp_14__0_carry__2_i_3_n_0),
.O(add_temp_14__0_carry__2_i_7_n_0));
(* HLUTNM = "lutpair2" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry_i_1
(.I0(RESIZE44[2]),
.I1(RESIZE15[2]),
.I2(RESIZE42[2]),
.O(add_temp_14__0_carry_i_1_n_0));
(* HLUTNM = "lutpair1" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry_i_2
(.I0(RESIZE44[1]),
.I1(RESIZE15[1]),
.I2(RESIZE42[1]),
.O(add_temp_14__0_carry_i_2_n_0));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__0_carry_i_3
(.I0(RESIZE44[0]),
.I1(RESIZE15[0]),
.I2(RESIZE42[0]),
.O(add_temp_14__0_carry_i_3_n_0));
(* HLUTNM = "lutpair3" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry_i_4
(.I0(RESIZE44[3]),
.I1(RESIZE15[3]),
.I2(RESIZE42[3]),
.I3(add_temp_14__0_carry_i_1_n_0),
.O(add_temp_14__0_carry_i_4_n_0));
(* HLUTNM = "lutpair2" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry_i_5
(.I0(RESIZE44[2]),
.I1(RESIZE15[2]),
.I2(RESIZE42[2]),
.I3(add_temp_14__0_carry_i_2_n_0),
.O(add_temp_14__0_carry_i_5_n_0));
(* HLUTNM = "lutpair1" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__0_carry_i_6
(.I0(RESIZE44[1]),
.I1(RESIZE15[1]),
.I2(RESIZE42[1]),
.I3(add_temp_14__0_carry_i_3_n_0),
.O(add_temp_14__0_carry_i_6_n_0));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__0_carry_i_7
(.I0(RESIZE44[0]),
.I1(RESIZE15[0]),
.I2(RESIZE42[0]),
.O(add_temp_14__0_carry_i_7_n_0));
CARRY4 add_temp_14__138_carry
(.CI(1'b0),
.CO({add_temp_14__138_carry_n_0,add_temp_14__138_carry_n_1,add_temp_14__138_carry_n_2,add_temp_14__138_carry_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__138_carry_i_1_n_0,add_temp_14__138_carry_i_2_n_0,add_temp_14__138_carry_i_3_n_0,1'b0}),
.O({add_temp_14__138_carry_n_4,add_temp_14__138_carry_n_5,add_temp_14__138_carry_n_6,add_temp_14__138_carry_n_7}),
.S({add_temp_14__138_carry_i_4_n_0,add_temp_14__138_carry_i_5_n_0,add_temp_14__138_carry_i_6_n_0,add_temp_14__138_carry_i_7_n_0}));
CARRY4 add_temp_14__138_carry__0
(.CI(add_temp_14__138_carry_n_0),
.CO({add_temp_14__138_carry__0_n_0,add_temp_14__138_carry__0_n_1,add_temp_14__138_carry__0_n_2,add_temp_14__138_carry__0_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__138_carry__0_i_1_n_0,add_temp_14__138_carry__0_i_2_n_0,add_temp_14__138_carry__0_i_3_n_0,add_temp_14__138_carry__0_i_4_n_0}),
.O({add_temp_14__138_carry__0_n_4,add_temp_14__138_carry__0_n_5,add_temp_14__138_carry__0_n_6,add_temp_14__138_carry__0_n_7}),
.S({add_temp_14__138_carry__0_i_5_n_0,add_temp_14__138_carry__0_i_6_n_0,add_temp_14__138_carry__0_i_7_n_0,add_temp_14__138_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair48" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__0_i_1
(.I0(RESIZE24[6]),
.I1(RESIZE26[6]),
.I2(RESIZE28[6]),
.O(add_temp_14__138_carry__0_i_1_n_0));
(* HLUTNM = "lutpair47" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__0_i_2
(.I0(RESIZE28[5]),
.I1(RESIZE24[5]),
.I2(RESIZE26[5]),
.O(add_temp_14__138_carry__0_i_2_n_0));
(* HLUTNM = "lutpair46" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__0_i_3
(.I0(RESIZE26[4]),
.I1(RESIZE24[4]),
.I2(RESIZE28[4]),
.O(add_temp_14__138_carry__0_i_3_n_0));
(* HLUTNM = "lutpair45" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__0_i_4
(.I0(RESIZE26[3]),
.I1(RESIZE28[3]),
.I2(RESIZE24[3]),
.O(add_temp_14__138_carry__0_i_4_n_0));
(* HLUTNM = "lutpair49" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__0_i_5
(.I0(RESIZE24[7]),
.I1(RESIZE26[7]),
.I2(RESIZE28[7]),
.I3(add_temp_14__138_carry__0_i_1_n_0),
.O(add_temp_14__138_carry__0_i_5_n_0));
(* HLUTNM = "lutpair48" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__0_i_6
(.I0(RESIZE24[6]),
.I1(RESIZE26[6]),
.I2(RESIZE28[6]),
.I3(add_temp_14__138_carry__0_i_2_n_0),
.O(add_temp_14__138_carry__0_i_6_n_0));
(* HLUTNM = "lutpair47" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__0_i_7
(.I0(RESIZE28[5]),
.I1(RESIZE24[5]),
.I2(RESIZE26[5]),
.I3(add_temp_14__138_carry__0_i_3_n_0),
.O(add_temp_14__138_carry__0_i_7_n_0));
(* HLUTNM = "lutpair46" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__0_i_8
(.I0(RESIZE26[4]),
.I1(RESIZE24[4]),
.I2(RESIZE28[4]),
.I3(add_temp_14__138_carry__0_i_4_n_0),
.O(add_temp_14__138_carry__0_i_8_n_0));
CARRY4 add_temp_14__138_carry__1
(.CI(add_temp_14__138_carry__0_n_0),
.CO({add_temp_14__138_carry__1_n_0,add_temp_14__138_carry__1_n_1,add_temp_14__138_carry__1_n_2,add_temp_14__138_carry__1_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__138_carry__1_i_1_n_0,add_temp_14__138_carry__1_i_2_n_0,add_temp_14__138_carry__1_i_3_n_0,add_temp_14__138_carry__1_i_4_n_0}),
.O({add_temp_14__138_carry__1_n_4,add_temp_14__138_carry__1_n_5,add_temp_14__138_carry__1_n_6,add_temp_14__138_carry__1_n_7}),
.S({add_temp_14__138_carry__1_i_5_n_0,add_temp_14__138_carry__1_i_6_n_0,add_temp_14__138_carry__1_i_7_n_0,add_temp_14__138_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair52" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__1_i_1
(.I0(RESIZE24[10]),
.I1(RESIZE26[10]),
.I2(RESIZE28[10]),
.O(add_temp_14__138_carry__1_i_1_n_0));
(* HLUTNM = "lutpair51" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__1_i_2
(.I0(RESIZE24[9]),
.I1(RESIZE26[9]),
.I2(RESIZE28[9]),
.O(add_temp_14__138_carry__1_i_2_n_0));
(* HLUTNM = "lutpair50" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__1_i_3
(.I0(RESIZE24[8]),
.I1(RESIZE26[8]),
.I2(RESIZE28[8]),
.O(add_temp_14__138_carry__1_i_3_n_0));
(* HLUTNM = "lutpair49" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__1_i_4
(.I0(RESIZE24[7]),
.I1(RESIZE26[7]),
.I2(RESIZE28[7]),
.O(add_temp_14__138_carry__1_i_4_n_0));
(* HLUTNM = "lutpair53" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__1_i_5
(.I0(RESIZE24[11]),
.I1(RESIZE26[11]),
.I2(RESIZE28[11]),
.I3(add_temp_14__138_carry__1_i_1_n_0),
.O(add_temp_14__138_carry__1_i_5_n_0));
(* HLUTNM = "lutpair52" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__1_i_6
(.I0(RESIZE24[10]),
.I1(RESIZE26[10]),
.I2(RESIZE28[10]),
.I3(add_temp_14__138_carry__1_i_2_n_0),
.O(add_temp_14__138_carry__1_i_6_n_0));
(* HLUTNM = "lutpair51" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__1_i_7
(.I0(RESIZE24[9]),
.I1(RESIZE26[9]),
.I2(RESIZE28[9]),
.I3(add_temp_14__138_carry__1_i_3_n_0),
.O(add_temp_14__138_carry__1_i_7_n_0));
(* HLUTNM = "lutpair50" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__1_i_8
(.I0(RESIZE24[8]),
.I1(RESIZE26[8]),
.I2(RESIZE28[8]),
.I3(add_temp_14__138_carry__1_i_4_n_0),
.O(add_temp_14__138_carry__1_i_8_n_0));
CARRY4 add_temp_14__138_carry__2
(.CI(add_temp_14__138_carry__1_n_0),
.CO({NLW_add_temp_14__138_carry__2_CO_UNCONNECTED[3],add_temp_14__138_carry__2_n_1,add_temp_14__138_carry__2_n_2,add_temp_14__138_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,add_temp_14__138_carry__2_i_1_n_0,add_temp_14__138_carry__2_i_2_n_0,add_temp_14__138_carry__2_i_3_n_0}),
.O({add_temp_14__138_carry__2_n_4,add_temp_14__138_carry__2_n_5,add_temp_14__138_carry__2_n_6,add_temp_14__138_carry__2_n_7}),
.S({add_temp_14__138_carry__2_i_4_n_0,add_temp_14__138_carry__2_i_5_n_0,add_temp_14__138_carry__2_i_6_n_0,add_temp_14__138_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair55" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__2_i_1
(.I0(RESIZE24[13]),
.I1(RESIZE26[13]),
.I2(RESIZE28[13]),
.O(add_temp_14__138_carry__2_i_1_n_0));
(* HLUTNM = "lutpair54" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__2_i_2
(.I0(RESIZE24[12]),
.I1(RESIZE26[12]),
.I2(RESIZE28[12]),
.O(add_temp_14__138_carry__2_i_2_n_0));
(* HLUTNM = "lutpair53" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry__2_i_3
(.I0(RESIZE24[11]),
.I1(RESIZE26[11]),
.I2(RESIZE28[11]),
.O(add_temp_14__138_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h17E8E817E81717E8))
add_temp_14__138_carry__2_i_4
(.I0(RESIZE28[14]),
.I1(RESIZE26[14]),
.I2(RESIZE24[14]),
.I3(RESIZE26[15]),
.I4(RESIZE24[15]),
.I5(RESIZE28[15]),
.O(add_temp_14__138_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__2_i_5
(.I0(add_temp_14__138_carry__2_i_1_n_0),
.I1(RESIZE26[14]),
.I2(RESIZE24[14]),
.I3(RESIZE28[14]),
.O(add_temp_14__138_carry__2_i_5_n_0));
(* HLUTNM = "lutpair55" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__2_i_6
(.I0(RESIZE24[13]),
.I1(RESIZE26[13]),
.I2(RESIZE28[13]),
.I3(add_temp_14__138_carry__2_i_2_n_0),
.O(add_temp_14__138_carry__2_i_6_n_0));
(* HLUTNM = "lutpair54" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry__2_i_7
(.I0(RESIZE24[12]),
.I1(RESIZE26[12]),
.I2(RESIZE28[12]),
.I3(add_temp_14__138_carry__2_i_3_n_0),
.O(add_temp_14__138_carry__2_i_7_n_0));
(* HLUTNM = "lutpair44" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry_i_1
(.I0(RESIZE26[2]),
.I1(RESIZE28[2]),
.I2(RESIZE24[2]),
.O(add_temp_14__138_carry_i_1_n_0));
(* HLUTNM = "lutpair43" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry_i_2
(.I0(RESIZE26[1]),
.I1(RESIZE28[1]),
.I2(RESIZE24[1]),
.O(add_temp_14__138_carry_i_2_n_0));
(* HLUTNM = "lutpair42" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__138_carry_i_3
(.I0(RESIZE26[0]),
.I1(RESIZE28[0]),
.I2(RESIZE24[0]),
.O(add_temp_14__138_carry_i_3_n_0));
(* HLUTNM = "lutpair45" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry_i_4
(.I0(RESIZE26[3]),
.I1(RESIZE28[3]),
.I2(RESIZE24[3]),
.I3(add_temp_14__138_carry_i_1_n_0),
.O(add_temp_14__138_carry_i_4_n_0));
(* HLUTNM = "lutpair44" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry_i_5
(.I0(RESIZE26[2]),
.I1(RESIZE28[2]),
.I2(RESIZE24[2]),
.I3(add_temp_14__138_carry_i_2_n_0),
.O(add_temp_14__138_carry_i_5_n_0));
(* HLUTNM = "lutpair43" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__138_carry_i_6
(.I0(RESIZE26[1]),
.I1(RESIZE28[1]),
.I2(RESIZE24[1]),
.I3(add_temp_14__138_carry_i_3_n_0),
.O(add_temp_14__138_carry_i_6_n_0));
(* HLUTNM = "lutpair42" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__138_carry_i_7
(.I0(RESIZE26[0]),
.I1(RESIZE28[0]),
.I2(RESIZE24[0]),
.O(add_temp_14__138_carry_i_7_n_0));
CARRY4 add_temp_14__184_carry
(.CI(1'b0),
.CO({add_temp_14__184_carry_n_0,add_temp_14__184_carry_n_1,add_temp_14__184_carry_n_2,add_temp_14__184_carry_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__184_carry_i_1_n_0,add_temp_14__184_carry_i_2_n_0,add_temp_14__184_carry_i_3_n_0,1'b0}),
.O({add_temp_14__184_carry_n_4,add_temp_14__184_carry_n_5,add_temp_14__184_carry_n_6,add_temp_14__184_carry_n_7}),
.S({add_temp_14__184_carry_i_4_n_0,add_temp_14__184_carry_i_5_n_0,add_temp_14__184_carry_i_6_n_0,add_temp_14__184_carry_i_7_n_0}));
CARRY4 add_temp_14__184_carry__0
(.CI(add_temp_14__184_carry_n_0),
.CO({add_temp_14__184_carry__0_n_0,add_temp_14__184_carry__0_n_1,add_temp_14__184_carry__0_n_2,add_temp_14__184_carry__0_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__184_carry__0_i_1_n_0,add_temp_14__184_carry__0_i_2_n_0,add_temp_14__184_carry__0_i_3_n_0,add_temp_14__184_carry__0_i_4_n_0}),
.O({add_temp_14__184_carry__0_n_4,add_temp_14__184_carry__0_n_5,add_temp_14__184_carry__0_n_6,add_temp_14__184_carry__0_n_7}),
.S({add_temp_14__184_carry__0_i_5_n_0,add_temp_14__184_carry__0_i_6_n_0,add_temp_14__184_carry__0_i_7_n_0,add_temp_14__184_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair62" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__0_i_1
(.I0(RESIZE20[6]),
.I1(RESIZE18[6]),
.I2(RESIZE22[6]),
.O(add_temp_14__184_carry__0_i_1_n_0));
(* HLUTNM = "lutpair61" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__0_i_2
(.I0(RESIZE20[5]),
.I1(RESIZE18[5]),
.I2(RESIZE22[5]),
.O(add_temp_14__184_carry__0_i_2_n_0));
(* HLUTNM = "lutpair60" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__0_i_3
(.I0(RESIZE20[4]),
.I1(RESIZE18[4]),
.I2(RESIZE22[4]),
.O(add_temp_14__184_carry__0_i_3_n_0));
(* HLUTNM = "lutpair59" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__0_i_4
(.I0(RESIZE18[3]),
.I1(RESIZE22[3]),
.I2(RESIZE20[3]),
.O(add_temp_14__184_carry__0_i_4_n_0));
(* HLUTNM = "lutpair63" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__0_i_5
(.I0(RESIZE20[7]),
.I1(RESIZE18[7]),
.I2(RESIZE22[7]),
.I3(add_temp_14__184_carry__0_i_1_n_0),
.O(add_temp_14__184_carry__0_i_5_n_0));
(* HLUTNM = "lutpair62" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__0_i_6
(.I0(RESIZE20[6]),
.I1(RESIZE18[6]),
.I2(RESIZE22[6]),
.I3(add_temp_14__184_carry__0_i_2_n_0),
.O(add_temp_14__184_carry__0_i_6_n_0));
(* HLUTNM = "lutpair61" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__0_i_7
(.I0(RESIZE20[5]),
.I1(RESIZE18[5]),
.I2(RESIZE22[5]),
.I3(add_temp_14__184_carry__0_i_3_n_0),
.O(add_temp_14__184_carry__0_i_7_n_0));
(* HLUTNM = "lutpair60" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__0_i_8
(.I0(RESIZE20[4]),
.I1(RESIZE18[4]),
.I2(RESIZE22[4]),
.I3(add_temp_14__184_carry__0_i_4_n_0),
.O(add_temp_14__184_carry__0_i_8_n_0));
CARRY4 add_temp_14__184_carry__1
(.CI(add_temp_14__184_carry__0_n_0),
.CO({add_temp_14__184_carry__1_n_0,add_temp_14__184_carry__1_n_1,add_temp_14__184_carry__1_n_2,add_temp_14__184_carry__1_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__184_carry__1_i_1_n_0,add_temp_14__184_carry__1_i_2_n_0,add_temp_14__184_carry__1_i_3_n_0,add_temp_14__184_carry__1_i_4_n_0}),
.O({add_temp_14__184_carry__1_n_4,add_temp_14__184_carry__1_n_5,add_temp_14__184_carry__1_n_6,add_temp_14__184_carry__1_n_7}),
.S({add_temp_14__184_carry__1_i_5_n_0,add_temp_14__184_carry__1_i_6_n_0,add_temp_14__184_carry__1_i_7_n_0,add_temp_14__184_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair66" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__1_i_1
(.I0(RESIZE18[10]),
.I1(RESIZE22[10]),
.I2(RESIZE20[10]),
.O(add_temp_14__184_carry__1_i_1_n_0));
(* HLUTNM = "lutpair65" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__1_i_2
(.I0(RESIZE18[9]),
.I1(RESIZE22[9]),
.I2(RESIZE20[9]),
.O(add_temp_14__184_carry__1_i_2_n_0));
(* HLUTNM = "lutpair64" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__1_i_3
(.I0(RESIZE18[8]),
.I1(RESIZE22[8]),
.I2(RESIZE20[8]),
.O(add_temp_14__184_carry__1_i_3_n_0));
(* HLUTNM = "lutpair63" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__1_i_4
(.I0(RESIZE20[7]),
.I1(RESIZE18[7]),
.I2(RESIZE22[7]),
.O(add_temp_14__184_carry__1_i_4_n_0));
(* HLUTNM = "lutpair67" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__1_i_5
(.I0(RESIZE18[11]),
.I1(RESIZE22[11]),
.I2(RESIZE20[11]),
.I3(add_temp_14__184_carry__1_i_1_n_0),
.O(add_temp_14__184_carry__1_i_5_n_0));
(* HLUTNM = "lutpair66" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__1_i_6
(.I0(RESIZE18[10]),
.I1(RESIZE22[10]),
.I2(RESIZE20[10]),
.I3(add_temp_14__184_carry__1_i_2_n_0),
.O(add_temp_14__184_carry__1_i_6_n_0));
(* HLUTNM = "lutpair65" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__1_i_7
(.I0(RESIZE18[9]),
.I1(RESIZE22[9]),
.I2(RESIZE20[9]),
.I3(add_temp_14__184_carry__1_i_3_n_0),
.O(add_temp_14__184_carry__1_i_7_n_0));
(* HLUTNM = "lutpair64" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__1_i_8
(.I0(RESIZE18[8]),
.I1(RESIZE22[8]),
.I2(RESIZE20[8]),
.I3(add_temp_14__184_carry__1_i_4_n_0),
.O(add_temp_14__184_carry__1_i_8_n_0));
CARRY4 add_temp_14__184_carry__2
(.CI(add_temp_14__184_carry__1_n_0),
.CO({NLW_add_temp_14__184_carry__2_CO_UNCONNECTED[3],add_temp_14__184_carry__2_n_1,add_temp_14__184_carry__2_n_2,add_temp_14__184_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,add_temp_14__184_carry__2_i_1_n_0,add_temp_14__184_carry__2_i_2_n_0,add_temp_14__184_carry__2_i_3_n_0}),
.O({add_temp_14__184_carry__2_n_4,add_temp_14__184_carry__2_n_5,add_temp_14__184_carry__2_n_6,add_temp_14__184_carry__2_n_7}),
.S({add_temp_14__184_carry__2_i_4_n_0,add_temp_14__184_carry__2_i_5_n_0,add_temp_14__184_carry__2_i_6_n_0,add_temp_14__184_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair69" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__2_i_1
(.I0(RESIZE18[13]),
.I1(RESIZE22[13]),
.I2(RESIZE20[13]),
.O(add_temp_14__184_carry__2_i_1_n_0));
(* HLUTNM = "lutpair68" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__2_i_2
(.I0(RESIZE18[12]),
.I1(RESIZE22[12]),
.I2(RESIZE20[12]),
.O(add_temp_14__184_carry__2_i_2_n_0));
(* HLUTNM = "lutpair67" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry__2_i_3
(.I0(RESIZE18[11]),
.I1(RESIZE22[11]),
.I2(RESIZE20[11]),
.O(add_temp_14__184_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h17E8E817E81717E8))
add_temp_14__184_carry__2_i_4
(.I0(RESIZE20[14]),
.I1(RESIZE22[14]),
.I2(RESIZE18[14]),
.I3(RESIZE20[15]),
.I4(RESIZE18[15]),
.I5(RESIZE22[15]),
.O(add_temp_14__184_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__2_i_5
(.I0(add_temp_14__184_carry__2_i_1_n_0),
.I1(RESIZE20[14]),
.I2(RESIZE18[14]),
.I3(RESIZE22[14]),
.O(add_temp_14__184_carry__2_i_5_n_0));
(* HLUTNM = "lutpair69" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__2_i_6
(.I0(RESIZE18[13]),
.I1(RESIZE22[13]),
.I2(RESIZE20[13]),
.I3(add_temp_14__184_carry__2_i_2_n_0),
.O(add_temp_14__184_carry__2_i_6_n_0));
(* HLUTNM = "lutpair68" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry__2_i_7
(.I0(RESIZE18[12]),
.I1(RESIZE22[12]),
.I2(RESIZE20[12]),
.I3(add_temp_14__184_carry__2_i_3_n_0),
.O(add_temp_14__184_carry__2_i_7_n_0));
(* HLUTNM = "lutpair58" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry_i_1
(.I0(RESIZE22[2]),
.I1(RESIZE18[2]),
.I2(RESIZE20[2]),
.O(add_temp_14__184_carry_i_1_n_0));
(* HLUTNM = "lutpair57" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry_i_2
(.I0(RESIZE20[1]),
.I1(RESIZE18[1]),
.I2(RESIZE22[1]),
.O(add_temp_14__184_carry_i_2_n_0));
(* HLUTNM = "lutpair56" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__184_carry_i_3
(.I0(RESIZE18[0]),
.I1(RESIZE22[0]),
.I2(RESIZE20[0]),
.O(add_temp_14__184_carry_i_3_n_0));
(* HLUTNM = "lutpair59" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry_i_4
(.I0(RESIZE18[3]),
.I1(RESIZE22[3]),
.I2(RESIZE20[3]),
.I3(add_temp_14__184_carry_i_1_n_0),
.O(add_temp_14__184_carry_i_4_n_0));
(* HLUTNM = "lutpair58" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry_i_5
(.I0(RESIZE22[2]),
.I1(RESIZE18[2]),
.I2(RESIZE20[2]),
.I3(add_temp_14__184_carry_i_2_n_0),
.O(add_temp_14__184_carry_i_5_n_0));
(* HLUTNM = "lutpair57" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__184_carry_i_6
(.I0(RESIZE20[1]),
.I1(RESIZE18[1]),
.I2(RESIZE22[1]),
.I3(add_temp_14__184_carry_i_3_n_0),
.O(add_temp_14__184_carry_i_6_n_0));
(* HLUTNM = "lutpair56" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__184_carry_i_7
(.I0(RESIZE18[0]),
.I1(RESIZE22[0]),
.I2(RESIZE20[0]),
.O(add_temp_14__184_carry_i_7_n_0));
CARRY4 add_temp_14__230_carry
(.CI(1'b0),
.CO({add_temp_14__230_carry_n_0,add_temp_14__230_carry_n_1,add_temp_14__230_carry_n_2,add_temp_14__230_carry_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__230_carry_i_1_n_0,add_temp_14__230_carry_i_2_n_0,add_temp_14__230_carry_i_3_n_0,1'b0}),
.O({add_temp_14__230_carry_n_4,add_temp_14__230_carry_n_5,add_temp_14__230_carry_n_6,add_temp_14__230_carry_n_7}),
.S({add_temp_14__230_carry_i_4_n_0,add_temp_14__230_carry_i_5_n_0,add_temp_14__230_carry_i_6_n_0,add_temp_14__230_carry_i_7_n_0}));
CARRY4 add_temp_14__230_carry__0
(.CI(add_temp_14__230_carry_n_0),
.CO({add_temp_14__230_carry__0_n_0,add_temp_14__230_carry__0_n_1,add_temp_14__230_carry__0_n_2,add_temp_14__230_carry__0_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__230_carry__0_i_1_n_0,add_temp_14__230_carry__0_i_2_n_0,add_temp_14__230_carry__0_i_3_n_0,add_temp_14__230_carry__0_i_4_n_0}),
.O({add_temp_14__230_carry__0_n_4,add_temp_14__230_carry__0_n_5,add_temp_14__230_carry__0_n_6,add_temp_14__230_carry__0_n_7}),
.S({add_temp_14__230_carry__0_i_5_n_0,add_temp_14__230_carry__0_i_6_n_0,add_temp_14__230_carry__0_i_7_n_0,add_temp_14__230_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair76" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__0_i_1
(.I0(RESIZE16[6]),
.I1(add_temp_14__0_carry__0_n_5),
.I2(add_temp_14__46_carry__0_n_5),
.O(add_temp_14__230_carry__0_i_1_n_0));
(* HLUTNM = "lutpair75" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__0_i_2
(.I0(RESIZE16[5]),
.I1(add_temp_14__46_carry__0_n_6),
.I2(add_temp_14__0_carry__0_n_6),
.O(add_temp_14__230_carry__0_i_2_n_0));
(* HLUTNM = "lutpair74" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__0_i_3
(.I0(add_temp_14__0_carry__0_n_7),
.I1(add_temp_14__46_carry__0_n_7),
.I2(RESIZE16[4]),
.O(add_temp_14__230_carry__0_i_3_n_0));
(* HLUTNM = "lutpair73" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__0_i_4
(.I0(add_temp_14__0_carry_n_4),
.I1(add_temp_14__46_carry_n_4),
.I2(RESIZE16[3]),
.O(add_temp_14__230_carry__0_i_4_n_0));
(* HLUTNM = "lutpair77" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__0_i_5
(.I0(add_temp_14__0_carry__0_n_4),
.I1(add_temp_14__46_carry__0_n_4),
.I2(RESIZE16[7]),
.I3(add_temp_14__230_carry__0_i_1_n_0),
.O(add_temp_14__230_carry__0_i_5_n_0));
(* HLUTNM = "lutpair76" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__0_i_6
(.I0(RESIZE16[6]),
.I1(add_temp_14__0_carry__0_n_5),
.I2(add_temp_14__46_carry__0_n_5),
.I3(add_temp_14__230_carry__0_i_2_n_0),
.O(add_temp_14__230_carry__0_i_6_n_0));
(* HLUTNM = "lutpair75" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__0_i_7
(.I0(RESIZE16[5]),
.I1(add_temp_14__46_carry__0_n_6),
.I2(add_temp_14__0_carry__0_n_6),
.I3(add_temp_14__230_carry__0_i_3_n_0),
.O(add_temp_14__230_carry__0_i_7_n_0));
(* HLUTNM = "lutpair74" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__0_i_8
(.I0(add_temp_14__0_carry__0_n_7),
.I1(add_temp_14__46_carry__0_n_7),
.I2(RESIZE16[4]),
.I3(add_temp_14__230_carry__0_i_4_n_0),
.O(add_temp_14__230_carry__0_i_8_n_0));
CARRY4 add_temp_14__230_carry__1
(.CI(add_temp_14__230_carry__0_n_0),
.CO({add_temp_14__230_carry__1_n_0,add_temp_14__230_carry__1_n_1,add_temp_14__230_carry__1_n_2,add_temp_14__230_carry__1_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__230_carry__1_i_1_n_0,add_temp_14__230_carry__1_i_2_n_0,add_temp_14__230_carry__1_i_3_n_0,add_temp_14__230_carry__1_i_4_n_0}),
.O({add_temp_14__230_carry__1_n_4,add_temp_14__230_carry__1_n_5,add_temp_14__230_carry__1_n_6,add_temp_14__230_carry__1_n_7}),
.S({add_temp_14__230_carry__1_i_5_n_0,add_temp_14__230_carry__1_i_6_n_0,add_temp_14__230_carry__1_i_7_n_0,add_temp_14__230_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair80" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__1_i_1
(.I0(RESIZE16[10]),
.I1(add_temp_14__0_carry__1_n_5),
.I2(add_temp_14__46_carry__1_n_5),
.O(add_temp_14__230_carry__1_i_1_n_0));
(* HLUTNM = "lutpair79" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__1_i_2
(.I0(add_temp_14__0_carry__1_n_6),
.I1(add_temp_14__46_carry__1_n_6),
.I2(RESIZE16[9]),
.O(add_temp_14__230_carry__1_i_2_n_0));
(* HLUTNM = "lutpair78" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__1_i_3
(.I0(add_temp_14__0_carry__1_n_7),
.I1(RESIZE16[8]),
.I2(add_temp_14__46_carry__1_n_7),
.O(add_temp_14__230_carry__1_i_3_n_0));
(* HLUTNM = "lutpair77" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__1_i_4
(.I0(add_temp_14__0_carry__0_n_4),
.I1(add_temp_14__46_carry__0_n_4),
.I2(RESIZE16[7]),
.O(add_temp_14__230_carry__1_i_4_n_0));
(* HLUTNM = "lutpair81" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__1_i_5
(.I0(RESIZE16[11]),
.I1(add_temp_14__0_carry__1_n_4),
.I2(add_temp_14__46_carry__1_n_4),
.I3(add_temp_14__230_carry__1_i_1_n_0),
.O(add_temp_14__230_carry__1_i_5_n_0));
(* HLUTNM = "lutpair80" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__1_i_6
(.I0(RESIZE16[10]),
.I1(add_temp_14__0_carry__1_n_5),
.I2(add_temp_14__46_carry__1_n_5),
.I3(add_temp_14__230_carry__1_i_2_n_0),
.O(add_temp_14__230_carry__1_i_6_n_0));
(* HLUTNM = "lutpair79" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__1_i_7
(.I0(add_temp_14__0_carry__1_n_6),
.I1(add_temp_14__46_carry__1_n_6),
.I2(RESIZE16[9]),
.I3(add_temp_14__230_carry__1_i_3_n_0),
.O(add_temp_14__230_carry__1_i_7_n_0));
(* HLUTNM = "lutpair78" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__1_i_8
(.I0(add_temp_14__0_carry__1_n_7),
.I1(RESIZE16[8]),
.I2(add_temp_14__46_carry__1_n_7),
.I3(add_temp_14__230_carry__1_i_4_n_0),
.O(add_temp_14__230_carry__1_i_8_n_0));
CARRY4 add_temp_14__230_carry__2
(.CI(add_temp_14__230_carry__1_n_0),
.CO({NLW_add_temp_14__230_carry__2_CO_UNCONNECTED[3],add_temp_14__230_carry__2_n_1,add_temp_14__230_carry__2_n_2,add_temp_14__230_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,add_temp_14__230_carry__2_i_1_n_0,add_temp_14__230_carry__2_i_2_n_0,add_temp_14__230_carry__2_i_3_n_0}),
.O({add_temp_14__230_carry__2_n_4,add_temp_14__230_carry__2_n_5,add_temp_14__230_carry__2_n_6,add_temp_14__230_carry__2_n_7}),
.S({add_temp_14__230_carry__2_i_4_n_0,add_temp_14__230_carry__2_i_5_n_0,add_temp_14__230_carry__2_i_6_n_0,add_temp_14__230_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair83" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__2_i_1
(.I0(RESIZE16[13]),
.I1(add_temp_14__0_carry__2_n_6),
.I2(add_temp_14__46_carry__2_n_6),
.O(add_temp_14__230_carry__2_i_1_n_0));
(* HLUTNM = "lutpair82" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__2_i_2
(.I0(RESIZE16[12]),
.I1(add_temp_14__0_carry__2_n_7),
.I2(add_temp_14__46_carry__2_n_7),
.O(add_temp_14__230_carry__2_i_2_n_0));
(* HLUTNM = "lutpair81" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry__2_i_3
(.I0(RESIZE16[11]),
.I1(add_temp_14__0_carry__1_n_4),
.I2(add_temp_14__46_carry__1_n_4),
.O(add_temp_14__230_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h17E8E817E81717E8))
add_temp_14__230_carry__2_i_4
(.I0(add_temp_14__46_carry__2_n_5),
.I1(add_temp_14__0_carry__2_n_5),
.I2(RESIZE16[14]),
.I3(add_temp_14__0_carry__2_n_4),
.I4(add_temp_14__46_carry__2_n_4),
.I5(RESIZE16[15]),
.O(add_temp_14__230_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__2_i_5
(.I0(add_temp_14__230_carry__2_i_1_n_0),
.I1(add_temp_14__0_carry__2_n_5),
.I2(add_temp_14__46_carry__2_n_5),
.I3(RESIZE16[14]),
.O(add_temp_14__230_carry__2_i_5_n_0));
(* HLUTNM = "lutpair83" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__2_i_6
(.I0(RESIZE16[13]),
.I1(add_temp_14__0_carry__2_n_6),
.I2(add_temp_14__46_carry__2_n_6),
.I3(add_temp_14__230_carry__2_i_2_n_0),
.O(add_temp_14__230_carry__2_i_6_n_0));
(* HLUTNM = "lutpair82" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry__2_i_7
(.I0(RESIZE16[12]),
.I1(add_temp_14__0_carry__2_n_7),
.I2(add_temp_14__46_carry__2_n_7),
.I3(add_temp_14__230_carry__2_i_3_n_0),
.O(add_temp_14__230_carry__2_i_7_n_0));
(* HLUTNM = "lutpair72" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry_i_1
(.I0(add_temp_14__46_carry_n_5),
.I1(add_temp_14__0_carry_n_5),
.I2(RESIZE16[2]),
.O(add_temp_14__230_carry_i_1_n_0));
(* HLUTNM = "lutpair71" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry_i_2
(.I0(add_temp_14__0_carry_n_6),
.I1(RESIZE16[1]),
.I2(add_temp_14__46_carry_n_6),
.O(add_temp_14__230_carry_i_2_n_0));
(* HLUTNM = "lutpair70" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__230_carry_i_3
(.I0(add_temp_14__46_carry_n_7),
.I1(add_temp_14__0_carry_n_7),
.I2(RESIZE16[0]),
.O(add_temp_14__230_carry_i_3_n_0));
(* HLUTNM = "lutpair73" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry_i_4
(.I0(add_temp_14__0_carry_n_4),
.I1(add_temp_14__46_carry_n_4),
.I2(RESIZE16[3]),
.I3(add_temp_14__230_carry_i_1_n_0),
.O(add_temp_14__230_carry_i_4_n_0));
(* HLUTNM = "lutpair72" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry_i_5
(.I0(add_temp_14__46_carry_n_5),
.I1(add_temp_14__0_carry_n_5),
.I2(RESIZE16[2]),
.I3(add_temp_14__230_carry_i_2_n_0),
.O(add_temp_14__230_carry_i_5_n_0));
(* HLUTNM = "lutpair71" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__230_carry_i_6
(.I0(add_temp_14__0_carry_n_6),
.I1(RESIZE16[1]),
.I2(add_temp_14__46_carry_n_6),
.I3(add_temp_14__230_carry_i_3_n_0),
.O(add_temp_14__230_carry_i_6_n_0));
(* HLUTNM = "lutpair70" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__230_carry_i_7
(.I0(add_temp_14__46_carry_n_7),
.I1(add_temp_14__0_carry_n_7),
.I2(RESIZE16[0]),
.O(add_temp_14__230_carry_i_7_n_0));
CARRY4 add_temp_14__278_carry
(.CI(1'b0),
.CO({add_temp_14__278_carry_n_0,add_temp_14__278_carry_n_1,add_temp_14__278_carry_n_2,add_temp_14__278_carry_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__278_carry_i_1_n_0,add_temp_14__278_carry_i_2_n_0,add_temp_14__278_carry_i_3_n_0,add_temp_14__92_carry_n_7}),
.O(filter_sum[3:0]),
.S({add_temp_14__278_carry_i_4_n_0,add_temp_14__278_carry_i_5_n_0,add_temp_14__278_carry_i_6_n_0,add_temp_14__278_carry_i_7_n_0}));
CARRY4 add_temp_14__278_carry__0
(.CI(add_temp_14__278_carry_n_0),
.CO({add_temp_14__278_carry__0_n_0,add_temp_14__278_carry__0_n_1,add_temp_14__278_carry__0_n_2,add_temp_14__278_carry__0_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__278_carry__0_i_1_n_0,add_temp_14__278_carry__0_i_2_n_0,add_temp_14__278_carry__0_i_3_n_0,add_temp_14__278_carry__0_i_4_n_0}),
.O(filter_sum[7:4]),
.S({add_temp_14__278_carry__0_i_5_n_0,add_temp_14__278_carry__0_i_6_n_0,add_temp_14__278_carry__0_i_7_n_0,add_temp_14__278_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry__0_i_1
(.I0(add_temp_14__138_carry__0_n_5),
.I1(add_temp_14__230_carry__0_n_5),
.I2(add_temp_14__184_carry__0_n_5),
.I3(add_temp_14__278_carry__0_i_9_n_0),
.I4(add_temp_14__92_carry__0_n_5),
.O(add_temp_14__278_carry__0_i_1_n_0));
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry__0_i_10
(.I0(add_temp_14__230_carry__0_n_7),
.I1(add_temp_14__184_carry__0_n_7),
.I2(add_temp_14__138_carry__0_n_7),
.O(add_temp_14__278_carry__0_i_10_n_0));
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry__0_i_11
(.I0(add_temp_14__230_carry_n_4),
.I1(add_temp_14__184_carry_n_4),
.I2(add_temp_14__138_carry_n_4),
.O(add_temp_14__278_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h96))
add_temp_14__278_carry__0_i_12
(.I0(add_temp_14__138_carry__0_n_4),
.I1(add_temp_14__230_carry__0_n_4),
.I2(add_temp_14__184_carry__0_n_4),
.O(add_temp_14__278_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry__0_i_2
(.I0(add_temp_14__138_carry__0_n_6),
.I1(add_temp_14__230_carry__0_n_6),
.I2(add_temp_14__184_carry__0_n_6),
.I3(add_temp_14__278_carry__0_i_10_n_0),
.I4(add_temp_14__92_carry__0_n_6),
.O(add_temp_14__278_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry__0_i_3
(.I0(add_temp_14__138_carry__0_n_7),
.I1(add_temp_14__230_carry__0_n_7),
.I2(add_temp_14__184_carry__0_n_7),
.I3(add_temp_14__278_carry__0_i_11_n_0),
.I4(add_temp_14__92_carry__0_n_7),
.O(add_temp_14__278_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry__0_i_4
(.I0(add_temp_14__138_carry_n_4),
.I1(add_temp_14__230_carry_n_4),
.I2(add_temp_14__184_carry_n_4),
.I3(add_temp_14__278_carry_i_9_n_0),
.I4(add_temp_14__92_carry_n_4),
.O(add_temp_14__278_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h6969699669969696))
add_temp_14__278_carry__0_i_5
(.I0(add_temp_14__278_carry__0_i_1_n_0),
.I1(add_temp_14__278_carry__0_i_12_n_0),
.I2(add_temp_14__92_carry__0_n_4),
.I3(add_temp_14__138_carry__0_n_5),
.I4(add_temp_14__184_carry__0_n_5),
.I5(add_temp_14__230_carry__0_n_5),
.O(add_temp_14__278_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry__0_i_6
(.I0(add_temp_14__278_carry__0_i_2_n_0),
.I1(add_temp_14__184_carry__0_n_5),
.I2(add_temp_14__230_carry__0_n_5),
.I3(add_temp_14__138_carry__0_n_5),
.I4(add_temp_14__92_carry__0_n_5),
.I5(add_temp_14__278_carry__0_i_9_n_0),
.O(add_temp_14__278_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry__0_i_7
(.I0(add_temp_14__278_carry__0_i_3_n_0),
.I1(add_temp_14__184_carry__0_n_6),
.I2(add_temp_14__230_carry__0_n_6),
.I3(add_temp_14__138_carry__0_n_6),
.I4(add_temp_14__92_carry__0_n_6),
.I5(add_temp_14__278_carry__0_i_10_n_0),
.O(add_temp_14__278_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry__0_i_8
(.I0(add_temp_14__278_carry__0_i_4_n_0),
.I1(add_temp_14__184_carry__0_n_7),
.I2(add_temp_14__230_carry__0_n_7),
.I3(add_temp_14__138_carry__0_n_7),
.I4(add_temp_14__92_carry__0_n_7),
.I5(add_temp_14__278_carry__0_i_11_n_0),
.O(add_temp_14__278_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry__0_i_9
(.I0(add_temp_14__138_carry__0_n_6),
.I1(add_temp_14__184_carry__0_n_6),
.I2(add_temp_14__230_carry__0_n_6),
.O(add_temp_14__278_carry__0_i_9_n_0));
CARRY4 add_temp_14__278_carry__1
(.CI(add_temp_14__278_carry__0_n_0),
.CO({add_temp_14__278_carry__1_n_0,add_temp_14__278_carry__1_n_1,add_temp_14__278_carry__1_n_2,add_temp_14__278_carry__1_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__278_carry__1_i_1_n_0,add_temp_14__278_carry__1_i_2_n_0,add_temp_14__278_carry__1_i_3_n_0,add_temp_14__278_carry__1_i_4_n_0}),
.O(filter_sum[11:8]),
.S({add_temp_14__278_carry__1_i_5_n_0,add_temp_14__278_carry__1_i_6_n_0,add_temp_14__278_carry__1_i_7_n_0,add_temp_14__278_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry__1_i_1
(.I0(add_temp_14__138_carry__1_n_5),
.I1(add_temp_14__230_carry__1_n_5),
.I2(add_temp_14__184_carry__1_n_5),
.I3(add_temp_14__278_carry__1_i_9_n_0),
.I4(add_temp_14__92_carry__1_n_5),
.O(add_temp_14__278_carry__1_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry__1_i_10
(.I0(add_temp_14__184_carry__1_n_7),
.I1(add_temp_14__138_carry__1_n_7),
.I2(add_temp_14__230_carry__1_n_7),
.O(add_temp_14__278_carry__1_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__278_carry__1_i_11
(.I0(add_temp_14__138_carry__1_n_7),
.I1(add_temp_14__230_carry__1_n_7),
.I2(add_temp_14__184_carry__1_n_7),
.O(add_temp_14__278_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h96))
add_temp_14__278_carry__1_i_12
(.I0(add_temp_14__138_carry__1_n_4),
.I1(add_temp_14__230_carry__1_n_4),
.I2(add_temp_14__184_carry__1_n_4),
.O(add_temp_14__278_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry__1_i_2
(.I0(add_temp_14__138_carry__1_n_6),
.I1(add_temp_14__230_carry__1_n_6),
.I2(add_temp_14__184_carry__1_n_6),
.I3(add_temp_14__278_carry__1_i_10_n_0),
.I4(add_temp_14__92_carry__1_n_6),
.O(add_temp_14__278_carry__1_i_2_n_0));
LUT5 #(
.INIT(32'hFEEAA880))
add_temp_14__278_carry__1_i_3
(.I0(add_temp_14__92_carry__1_n_7),
.I1(add_temp_14__138_carry__0_n_4),
.I2(add_temp_14__184_carry__0_n_4),
.I3(add_temp_14__230_carry__0_n_4),
.I4(add_temp_14__278_carry__1_i_11_n_0),
.O(add_temp_14__278_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'hFEEAA880))
add_temp_14__278_carry__1_i_4
(.I0(add_temp_14__92_carry__0_n_4),
.I1(add_temp_14__230_carry__0_n_5),
.I2(add_temp_14__184_carry__0_n_5),
.I3(add_temp_14__138_carry__0_n_5),
.I4(add_temp_14__278_carry__0_i_12_n_0),
.O(add_temp_14__278_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'h6969699669969696))
add_temp_14__278_carry__1_i_5
(.I0(add_temp_14__278_carry__1_i_1_n_0),
.I1(add_temp_14__278_carry__1_i_12_n_0),
.I2(add_temp_14__92_carry__1_n_4),
.I3(add_temp_14__230_carry__1_n_5),
.I4(add_temp_14__184_carry__1_n_5),
.I5(add_temp_14__138_carry__1_n_5),
.O(add_temp_14__278_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry__1_i_6
(.I0(add_temp_14__278_carry__1_i_2_n_0),
.I1(add_temp_14__184_carry__1_n_5),
.I2(add_temp_14__230_carry__1_n_5),
.I3(add_temp_14__138_carry__1_n_5),
.I4(add_temp_14__92_carry__1_n_5),
.I5(add_temp_14__278_carry__1_i_9_n_0),
.O(add_temp_14__278_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry__1_i_7
(.I0(add_temp_14__278_carry__1_i_3_n_0),
.I1(add_temp_14__184_carry__1_n_6),
.I2(add_temp_14__230_carry__1_n_6),
.I3(add_temp_14__138_carry__1_n_6),
.I4(add_temp_14__92_carry__1_n_6),
.I5(add_temp_14__278_carry__1_i_10_n_0),
.O(add_temp_14__278_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'h6969699669969696))
add_temp_14__278_carry__1_i_8
(.I0(add_temp_14__278_carry__1_i_4_n_0),
.I1(add_temp_14__278_carry__1_i_11_n_0),
.I2(add_temp_14__92_carry__1_n_7),
.I3(add_temp_14__230_carry__0_n_4),
.I4(add_temp_14__184_carry__0_n_4),
.I5(add_temp_14__138_carry__0_n_4),
.O(add_temp_14__278_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry__1_i_9
(.I0(add_temp_14__184_carry__1_n_6),
.I1(add_temp_14__230_carry__1_n_6),
.I2(add_temp_14__138_carry__1_n_6),
.O(add_temp_14__278_carry__1_i_9_n_0));
CARRY4 add_temp_14__278_carry__2
(.CI(add_temp_14__278_carry__1_n_0),
.CO({NLW_add_temp_14__278_carry__2_CO_UNCONNECTED[3],add_temp_14__278_carry__2_n_1,add_temp_14__278_carry__2_n_2,add_temp_14__278_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,add_temp_14__278_carry__2_i_1_n_0,add_temp_14__278_carry__2_i_2_n_0,add_temp_14__278_carry__2_i_3_n_0}),
.O(filter_sum[15:12]),
.S({add_temp_14__278_carry__2_i_4_n_0,add_temp_14__278_carry__2_i_5_n_0,add_temp_14__278_carry__2_i_6_n_0,add_temp_14__278_carry__2_i_7_n_0}));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry__2_i_1
(.I0(add_temp_14__138_carry__2_n_6),
.I1(add_temp_14__230_carry__2_n_6),
.I2(add_temp_14__184_carry__2_n_6),
.I3(add_temp_14__278_carry__2_i_8_n_0),
.I4(add_temp_14__92_carry__2_n_6),
.O(add_temp_14__278_carry__2_i_1_n_0));
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry__2_i_10
(.I0(add_temp_14__184_carry__2_n_6),
.I1(add_temp_14__230_carry__2_n_6),
.I2(add_temp_14__138_carry__2_n_6),
.O(add_temp_14__278_carry__2_i_10_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__278_carry__2_i_11
(.I0(add_temp_14__184_carry__2_n_4),
.I1(add_temp_14__230_carry__2_n_4),
.I2(add_temp_14__138_carry__2_n_4),
.I3(add_temp_14__92_carry__2_n_4),
.O(add_temp_14__278_carry__2_i_11_n_0));
LUT5 #(
.INIT(32'hFEEAA880))
add_temp_14__278_carry__2_i_2
(.I0(add_temp_14__92_carry__2_n_7),
.I1(add_temp_14__138_carry__1_n_4),
.I2(add_temp_14__184_carry__1_n_4),
.I3(add_temp_14__230_carry__1_n_4),
.I4(add_temp_14__278_carry__2_i_9_n_0),
.O(add_temp_14__278_carry__2_i_2_n_0));
LUT5 #(
.INIT(32'hFEEAA880))
add_temp_14__278_carry__2_i_3
(.I0(add_temp_14__92_carry__1_n_4),
.I1(add_temp_14__138_carry__1_n_5),
.I2(add_temp_14__184_carry__1_n_5),
.I3(add_temp_14__230_carry__1_n_5),
.I4(add_temp_14__278_carry__1_i_12_n_0),
.O(add_temp_14__278_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'hE187871E871E1E78))
add_temp_14__278_carry__2_i_4
(.I0(add_temp_14__92_carry__2_n_5),
.I1(add_temp_14__278_carry__2_i_10_n_0),
.I2(add_temp_14__278_carry__2_i_11_n_0),
.I3(add_temp_14__138_carry__2_n_5),
.I4(add_temp_14__184_carry__2_n_5),
.I5(add_temp_14__230_carry__2_n_5),
.O(add_temp_14__278_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry__2_i_5
(.I0(add_temp_14__278_carry__2_i_1_n_0),
.I1(add_temp_14__184_carry__2_n_5),
.I2(add_temp_14__230_carry__2_n_5),
.I3(add_temp_14__138_carry__2_n_5),
.I4(add_temp_14__92_carry__2_n_5),
.I5(add_temp_14__278_carry__2_i_10_n_0),
.O(add_temp_14__278_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry__2_i_6
(.I0(add_temp_14__278_carry__2_i_2_n_0),
.I1(add_temp_14__184_carry__2_n_6),
.I2(add_temp_14__230_carry__2_n_6),
.I3(add_temp_14__138_carry__2_n_6),
.I4(add_temp_14__92_carry__2_n_6),
.I5(add_temp_14__278_carry__2_i_8_n_0),
.O(add_temp_14__278_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'h6969699669969696))
add_temp_14__278_carry__2_i_7
(.I0(add_temp_14__278_carry__2_i_3_n_0),
.I1(add_temp_14__278_carry__2_i_9_n_0),
.I2(add_temp_14__92_carry__2_n_7),
.I3(add_temp_14__230_carry__1_n_4),
.I4(add_temp_14__184_carry__1_n_4),
.I5(add_temp_14__138_carry__1_n_4),
.O(add_temp_14__278_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry__2_i_8
(.I0(add_temp_14__184_carry__2_n_7),
.I1(add_temp_14__138_carry__2_n_7),
.I2(add_temp_14__230_carry__2_n_7),
.O(add_temp_14__278_carry__2_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__278_carry__2_i_9
(.I0(add_temp_14__138_carry__2_n_7),
.I1(add_temp_14__230_carry__2_n_7),
.I2(add_temp_14__184_carry__2_n_7),
.O(add_temp_14__278_carry__2_i_9_n_0));
LUT5 #(
.INIT(32'hFF969600))
add_temp_14__278_carry_i_1
(.I0(add_temp_14__138_carry_n_5),
.I1(add_temp_14__230_carry_n_5),
.I2(add_temp_14__184_carry_n_5),
.I3(add_temp_14__278_carry_i_8_n_0),
.I4(add_temp_14__92_carry_n_5),
.O(add_temp_14__278_carry_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__278_carry_i_10
(.I0(add_temp_14__138_carry_n_5),
.I1(add_temp_14__230_carry_n_5),
.I2(add_temp_14__184_carry_n_5),
.O(add_temp_14__278_carry_i_10_n_0));
LUT5 #(
.INIT(32'h96696996))
add_temp_14__278_carry_i_2
(.I0(add_temp_14__278_carry_i_8_n_0),
.I1(add_temp_14__92_carry_n_5),
.I2(add_temp_14__138_carry_n_5),
.I3(add_temp_14__230_carry_n_5),
.I4(add_temp_14__184_carry_n_5),
.O(add_temp_14__278_carry_i_2_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__278_carry_i_3
(.I0(add_temp_14__184_carry_n_6),
.I1(add_temp_14__230_carry_n_6),
.I2(add_temp_14__138_carry_n_6),
.I3(add_temp_14__92_carry_n_6),
.O(add_temp_14__278_carry_i_3_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
add_temp_14__278_carry_i_4
(.I0(add_temp_14__278_carry_i_1_n_0),
.I1(add_temp_14__184_carry_n_4),
.I2(add_temp_14__230_carry_n_4),
.I3(add_temp_14__138_carry_n_4),
.I4(add_temp_14__92_carry_n_4),
.I5(add_temp_14__278_carry_i_9_n_0),
.O(add_temp_14__278_carry_i_4_n_0));
LUT6 #(
.INIT(64'h6999999699969666))
add_temp_14__278_carry_i_5
(.I0(add_temp_14__278_carry_i_10_n_0),
.I1(add_temp_14__92_carry_n_5),
.I2(add_temp_14__138_carry_n_6),
.I3(add_temp_14__230_carry_n_6),
.I4(add_temp_14__184_carry_n_6),
.I5(add_temp_14__92_carry_n_6),
.O(add_temp_14__278_carry_i_5_n_0));
LUT4 #(
.INIT(16'h566A))
add_temp_14__278_carry_i_6
(.I0(add_temp_14__278_carry_i_3_n_0),
.I1(add_temp_14__230_carry_n_7),
.I2(add_temp_14__184_carry_n_7),
.I3(add_temp_14__138_carry_n_7),
.O(add_temp_14__278_carry_i_6_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__278_carry_i_7
(.I0(add_temp_14__184_carry_n_7),
.I1(add_temp_14__230_carry_n_7),
.I2(add_temp_14__138_carry_n_7),
.I3(add_temp_14__92_carry_n_7),
.O(add_temp_14__278_carry_i_7_n_0));
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry_i_8
(.I0(add_temp_14__138_carry_n_6),
.I1(add_temp_14__230_carry_n_6),
.I2(add_temp_14__184_carry_n_6),
.O(add_temp_14__278_carry_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__278_carry_i_9
(.I0(add_temp_14__184_carry_n_5),
.I1(add_temp_14__138_carry_n_5),
.I2(add_temp_14__230_carry_n_5),
.O(add_temp_14__278_carry_i_9_n_0));
CARRY4 add_temp_14__46_carry
(.CI(1'b0),
.CO({add_temp_14__46_carry_n_0,add_temp_14__46_carry_n_1,add_temp_14__46_carry_n_2,add_temp_14__46_carry_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__46_carry_i_1_n_0,add_temp_14__46_carry_i_2_n_0,add_temp_14__46_carry_i_3_n_0,1'b0}),
.O({add_temp_14__46_carry_n_4,add_temp_14__46_carry_n_5,add_temp_14__46_carry_n_6,add_temp_14__46_carry_n_7}),
.S({add_temp_14__46_carry_i_4_n_0,add_temp_14__46_carry_i_5_n_0,add_temp_14__46_carry_i_6_n_0,add_temp_14__46_carry_i_7_n_0}));
CARRY4 add_temp_14__46_carry__0
(.CI(add_temp_14__46_carry_n_0),
.CO({add_temp_14__46_carry__0_n_0,add_temp_14__46_carry__0_n_1,add_temp_14__46_carry__0_n_2,add_temp_14__46_carry__0_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__46_carry__0_i_1_n_0,add_temp_14__46_carry__0_i_2_n_0,add_temp_14__46_carry__0_i_3_n_0,add_temp_14__46_carry__0_i_4_n_0}),
.O({add_temp_14__46_carry__0_n_4,add_temp_14__46_carry__0_n_5,add_temp_14__46_carry__0_n_6,add_temp_14__46_carry__0_n_7}),
.S({add_temp_14__46_carry__0_i_5_n_0,add_temp_14__46_carry__0_i_6_n_0,add_temp_14__46_carry__0_i_7_n_0,add_temp_14__46_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair20" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__0_i_1
(.I0(RESIZE38[6]),
.I1(RESIZE40[6]),
.I2(RESIZE36[6]),
.O(add_temp_14__46_carry__0_i_1_n_0));
(* HLUTNM = "lutpair19" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__0_i_2
(.I0(RESIZE38[5]),
.I1(RESIZE40[5]),
.I2(RESIZE36[5]),
.O(add_temp_14__46_carry__0_i_2_n_0));
(* HLUTNM = "lutpair18" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__0_i_3
(.I0(RESIZE38[4]),
.I1(RESIZE40[4]),
.I2(RESIZE36[4]),
.O(add_temp_14__46_carry__0_i_3_n_0));
(* HLUTNM = "lutpair17" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__0_i_4
(.I0(RESIZE38[3]),
.I1(RESIZE40[3]),
.I2(RESIZE36[3]),
.O(add_temp_14__46_carry__0_i_4_n_0));
(* HLUTNM = "lutpair21" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__0_i_5
(.I0(RESIZE38[7]),
.I1(RESIZE40[7]),
.I2(RESIZE36[7]),
.I3(add_temp_14__46_carry__0_i_1_n_0),
.O(add_temp_14__46_carry__0_i_5_n_0));
(* HLUTNM = "lutpair20" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__0_i_6
(.I0(RESIZE38[6]),
.I1(RESIZE40[6]),
.I2(RESIZE36[6]),
.I3(add_temp_14__46_carry__0_i_2_n_0),
.O(add_temp_14__46_carry__0_i_6_n_0));
(* HLUTNM = "lutpair19" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__0_i_7
(.I0(RESIZE38[5]),
.I1(RESIZE40[5]),
.I2(RESIZE36[5]),
.I3(add_temp_14__46_carry__0_i_3_n_0),
.O(add_temp_14__46_carry__0_i_7_n_0));
(* HLUTNM = "lutpair18" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__0_i_8
(.I0(RESIZE38[4]),
.I1(RESIZE40[4]),
.I2(RESIZE36[4]),
.I3(add_temp_14__46_carry__0_i_4_n_0),
.O(add_temp_14__46_carry__0_i_8_n_0));
CARRY4 add_temp_14__46_carry__1
(.CI(add_temp_14__46_carry__0_n_0),
.CO({add_temp_14__46_carry__1_n_0,add_temp_14__46_carry__1_n_1,add_temp_14__46_carry__1_n_2,add_temp_14__46_carry__1_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__46_carry__1_i_1_n_0,add_temp_14__46_carry__1_i_2_n_0,add_temp_14__46_carry__1_i_3_n_0,add_temp_14__46_carry__1_i_4_n_0}),
.O({add_temp_14__46_carry__1_n_4,add_temp_14__46_carry__1_n_5,add_temp_14__46_carry__1_n_6,add_temp_14__46_carry__1_n_7}),
.S({add_temp_14__46_carry__1_i_5_n_0,add_temp_14__46_carry__1_i_6_n_0,add_temp_14__46_carry__1_i_7_n_0,add_temp_14__46_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair24" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__1_i_1
(.I0(RESIZE40[10]),
.I1(RESIZE36[10]),
.I2(RESIZE38[10]),
.O(add_temp_14__46_carry__1_i_1_n_0));
(* HLUTNM = "lutpair23" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__1_i_2
(.I0(RESIZE38[9]),
.I1(RESIZE40[9]),
.I2(RESIZE36[9]),
.O(add_temp_14__46_carry__1_i_2_n_0));
(* HLUTNM = "lutpair22" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__1_i_3
(.I0(RESIZE38[8]),
.I1(RESIZE40[8]),
.I2(RESIZE36[8]),
.O(add_temp_14__46_carry__1_i_3_n_0));
(* HLUTNM = "lutpair21" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__1_i_4
(.I0(RESIZE38[7]),
.I1(RESIZE40[7]),
.I2(RESIZE36[7]),
.O(add_temp_14__46_carry__1_i_4_n_0));
(* HLUTNM = "lutpair25" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__1_i_5
(.I0(RESIZE36[11]),
.I1(RESIZE38[11]),
.I2(RESIZE40[11]),
.I3(add_temp_14__46_carry__1_i_1_n_0),
.O(add_temp_14__46_carry__1_i_5_n_0));
(* HLUTNM = "lutpair24" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__1_i_6
(.I0(RESIZE40[10]),
.I1(RESIZE36[10]),
.I2(RESIZE38[10]),
.I3(add_temp_14__46_carry__1_i_2_n_0),
.O(add_temp_14__46_carry__1_i_6_n_0));
(* HLUTNM = "lutpair23" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__1_i_7
(.I0(RESIZE38[9]),
.I1(RESIZE40[9]),
.I2(RESIZE36[9]),
.I3(add_temp_14__46_carry__1_i_3_n_0),
.O(add_temp_14__46_carry__1_i_7_n_0));
(* HLUTNM = "lutpair22" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__1_i_8
(.I0(RESIZE38[8]),
.I1(RESIZE40[8]),
.I2(RESIZE36[8]),
.I3(add_temp_14__46_carry__1_i_4_n_0),
.O(add_temp_14__46_carry__1_i_8_n_0));
CARRY4 add_temp_14__46_carry__2
(.CI(add_temp_14__46_carry__1_n_0),
.CO({NLW_add_temp_14__46_carry__2_CO_UNCONNECTED[3],add_temp_14__46_carry__2_n_1,add_temp_14__46_carry__2_n_2,add_temp_14__46_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,add_temp_14__46_carry__2_i_1_n_0,add_temp_14__46_carry__2_i_2_n_0,add_temp_14__46_carry__2_i_3_n_0}),
.O({add_temp_14__46_carry__2_n_4,add_temp_14__46_carry__2_n_5,add_temp_14__46_carry__2_n_6,add_temp_14__46_carry__2_n_7}),
.S({add_temp_14__46_carry__2_i_4_n_0,add_temp_14__46_carry__2_i_5_n_0,add_temp_14__46_carry__2_i_6_n_0,add_temp_14__46_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair27" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__2_i_1
(.I0(RESIZE36[13]),
.I1(RESIZE38[13]),
.I2(RESIZE40[13]),
.O(add_temp_14__46_carry__2_i_1_n_0));
(* HLUTNM = "lutpair26" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__2_i_2
(.I0(RESIZE36[12]),
.I1(RESIZE38[12]),
.I2(RESIZE40[12]),
.O(add_temp_14__46_carry__2_i_2_n_0));
(* HLUTNM = "lutpair25" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry__2_i_3
(.I0(RESIZE36[11]),
.I1(RESIZE38[11]),
.I2(RESIZE40[11]),
.O(add_temp_14__46_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h17E8E817E81717E8))
add_temp_14__46_carry__2_i_4
(.I0(RESIZE40[14]),
.I1(RESIZE38[14]),
.I2(RESIZE36[14]),
.I3(RESIZE38[15]),
.I4(RESIZE36[15]),
.I5(RESIZE40[15]),
.O(add_temp_14__46_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__2_i_5
(.I0(add_temp_14__46_carry__2_i_1_n_0),
.I1(RESIZE38[14]),
.I2(RESIZE36[14]),
.I3(RESIZE40[14]),
.O(add_temp_14__46_carry__2_i_5_n_0));
(* HLUTNM = "lutpair27" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__2_i_6
(.I0(RESIZE36[13]),
.I1(RESIZE38[13]),
.I2(RESIZE40[13]),
.I3(add_temp_14__46_carry__2_i_2_n_0),
.O(add_temp_14__46_carry__2_i_6_n_0));
(* HLUTNM = "lutpair26" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry__2_i_7
(.I0(RESIZE36[12]),
.I1(RESIZE38[12]),
.I2(RESIZE40[12]),
.I3(add_temp_14__46_carry__2_i_3_n_0),
.O(add_temp_14__46_carry__2_i_7_n_0));
(* HLUTNM = "lutpair16" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry_i_1
(.I0(RESIZE38[2]),
.I1(RESIZE40[2]),
.I2(RESIZE36[2]),
.O(add_temp_14__46_carry_i_1_n_0));
(* HLUTNM = "lutpair15" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry_i_2
(.I0(RESIZE38[1]),
.I1(RESIZE40[1]),
.I2(RESIZE36[1]),
.O(add_temp_14__46_carry_i_2_n_0));
(* HLUTNM = "lutpair14" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__46_carry_i_3
(.I0(RESIZE38[0]),
.I1(RESIZE40[0]),
.I2(RESIZE36[0]),
.O(add_temp_14__46_carry_i_3_n_0));
(* HLUTNM = "lutpair17" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry_i_4
(.I0(RESIZE38[3]),
.I1(RESIZE40[3]),
.I2(RESIZE36[3]),
.I3(add_temp_14__46_carry_i_1_n_0),
.O(add_temp_14__46_carry_i_4_n_0));
(* HLUTNM = "lutpair16" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry_i_5
(.I0(RESIZE38[2]),
.I1(RESIZE40[2]),
.I2(RESIZE36[2]),
.I3(add_temp_14__46_carry_i_2_n_0),
.O(add_temp_14__46_carry_i_5_n_0));
(* HLUTNM = "lutpair15" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__46_carry_i_6
(.I0(RESIZE38[1]),
.I1(RESIZE40[1]),
.I2(RESIZE36[1]),
.I3(add_temp_14__46_carry_i_3_n_0),
.O(add_temp_14__46_carry_i_6_n_0));
(* HLUTNM = "lutpair14" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__46_carry_i_7
(.I0(RESIZE38[0]),
.I1(RESIZE40[0]),
.I2(RESIZE36[0]),
.O(add_temp_14__46_carry_i_7_n_0));
CARRY4 add_temp_14__92_carry
(.CI(1'b0),
.CO({add_temp_14__92_carry_n_0,add_temp_14__92_carry_n_1,add_temp_14__92_carry_n_2,add_temp_14__92_carry_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__92_carry_i_1_n_0,add_temp_14__92_carry_i_2_n_0,add_temp_14__92_carry_i_3_n_0,1'b0}),
.O({add_temp_14__92_carry_n_4,add_temp_14__92_carry_n_5,add_temp_14__92_carry_n_6,add_temp_14__92_carry_n_7}),
.S({add_temp_14__92_carry_i_4_n_0,add_temp_14__92_carry_i_5_n_0,add_temp_14__92_carry_i_6_n_0,add_temp_14__92_carry_i_7_n_0}));
CARRY4 add_temp_14__92_carry__0
(.CI(add_temp_14__92_carry_n_0),
.CO({add_temp_14__92_carry__0_n_0,add_temp_14__92_carry__0_n_1,add_temp_14__92_carry__0_n_2,add_temp_14__92_carry__0_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__92_carry__0_i_1_n_0,add_temp_14__92_carry__0_i_2_n_0,add_temp_14__92_carry__0_i_3_n_0,add_temp_14__92_carry__0_i_4_n_0}),
.O({add_temp_14__92_carry__0_n_4,add_temp_14__92_carry__0_n_5,add_temp_14__92_carry__0_n_6,add_temp_14__92_carry__0_n_7}),
.S({add_temp_14__92_carry__0_i_5_n_0,add_temp_14__92_carry__0_i_6_n_0,add_temp_14__92_carry__0_i_7_n_0,add_temp_14__92_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair34" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__0_i_1
(.I0(RESIZE32[6]),
.I1(RESIZE34[6]),
.I2(RESIZE30[6]),
.O(add_temp_14__92_carry__0_i_1_n_0));
(* HLUTNM = "lutpair33" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__0_i_2
(.I0(RESIZE32[5]),
.I1(RESIZE34[5]),
.I2(RESIZE30[5]),
.O(add_temp_14__92_carry__0_i_2_n_0));
(* HLUTNM = "lutpair32" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__0_i_3
(.I0(RESIZE32[4]),
.I1(RESIZE34[4]),
.I2(RESIZE30[4]),
.O(add_temp_14__92_carry__0_i_3_n_0));
(* HLUTNM = "lutpair31" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__0_i_4
(.I0(RESIZE32[3]),
.I1(RESIZE34[3]),
.I2(RESIZE30[3]),
.O(add_temp_14__92_carry__0_i_4_n_0));
(* HLUTNM = "lutpair35" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__0_i_5
(.I0(RESIZE34[7]),
.I1(RESIZE30[7]),
.I2(RESIZE32[7]),
.I3(add_temp_14__92_carry__0_i_1_n_0),
.O(add_temp_14__92_carry__0_i_5_n_0));
(* HLUTNM = "lutpair34" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__0_i_6
(.I0(RESIZE32[6]),
.I1(RESIZE34[6]),
.I2(RESIZE30[6]),
.I3(add_temp_14__92_carry__0_i_2_n_0),
.O(add_temp_14__92_carry__0_i_6_n_0));
(* HLUTNM = "lutpair33" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__0_i_7
(.I0(RESIZE32[5]),
.I1(RESIZE34[5]),
.I2(RESIZE30[5]),
.I3(add_temp_14__92_carry__0_i_3_n_0),
.O(add_temp_14__92_carry__0_i_7_n_0));
(* HLUTNM = "lutpair32" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__0_i_8
(.I0(RESIZE32[4]),
.I1(RESIZE34[4]),
.I2(RESIZE30[4]),
.I3(add_temp_14__92_carry__0_i_4_n_0),
.O(add_temp_14__92_carry__0_i_8_n_0));
CARRY4 add_temp_14__92_carry__1
(.CI(add_temp_14__92_carry__0_n_0),
.CO({add_temp_14__92_carry__1_n_0,add_temp_14__92_carry__1_n_1,add_temp_14__92_carry__1_n_2,add_temp_14__92_carry__1_n_3}),
.CYINIT(1'b0),
.DI({add_temp_14__92_carry__1_i_1_n_0,add_temp_14__92_carry__1_i_2_n_0,add_temp_14__92_carry__1_i_3_n_0,add_temp_14__92_carry__1_i_4_n_0}),
.O({add_temp_14__92_carry__1_n_4,add_temp_14__92_carry__1_n_5,add_temp_14__92_carry__1_n_6,add_temp_14__92_carry__1_n_7}),
.S({add_temp_14__92_carry__1_i_5_n_0,add_temp_14__92_carry__1_i_6_n_0,add_temp_14__92_carry__1_i_7_n_0,add_temp_14__92_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair38" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__1_i_1
(.I0(RESIZE30[10]),
.I1(RESIZE32[10]),
.I2(RESIZE34[10]),
.O(add_temp_14__92_carry__1_i_1_n_0));
(* HLUTNM = "lutpair37" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__1_i_2
(.I0(RESIZE30[9]),
.I1(RESIZE32[9]),
.I2(RESIZE34[9]),
.O(add_temp_14__92_carry__1_i_2_n_0));
(* HLUTNM = "lutpair36" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__1_i_3
(.I0(RESIZE30[8]),
.I1(RESIZE32[8]),
.I2(RESIZE34[8]),
.O(add_temp_14__92_carry__1_i_3_n_0));
(* HLUTNM = "lutpair35" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__1_i_4
(.I0(RESIZE34[7]),
.I1(RESIZE30[7]),
.I2(RESIZE32[7]),
.O(add_temp_14__92_carry__1_i_4_n_0));
(* HLUTNM = "lutpair39" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__1_i_5
(.I0(RESIZE30[11]),
.I1(RESIZE32[11]),
.I2(RESIZE34[11]),
.I3(add_temp_14__92_carry__1_i_1_n_0),
.O(add_temp_14__92_carry__1_i_5_n_0));
(* HLUTNM = "lutpair38" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__1_i_6
(.I0(RESIZE30[10]),
.I1(RESIZE32[10]),
.I2(RESIZE34[10]),
.I3(add_temp_14__92_carry__1_i_2_n_0),
.O(add_temp_14__92_carry__1_i_6_n_0));
(* HLUTNM = "lutpair37" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__1_i_7
(.I0(RESIZE30[9]),
.I1(RESIZE32[9]),
.I2(RESIZE34[9]),
.I3(add_temp_14__92_carry__1_i_3_n_0),
.O(add_temp_14__92_carry__1_i_7_n_0));
(* HLUTNM = "lutpair36" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__1_i_8
(.I0(RESIZE30[8]),
.I1(RESIZE32[8]),
.I2(RESIZE34[8]),
.I3(add_temp_14__92_carry__1_i_4_n_0),
.O(add_temp_14__92_carry__1_i_8_n_0));
CARRY4 add_temp_14__92_carry__2
(.CI(add_temp_14__92_carry__1_n_0),
.CO({NLW_add_temp_14__92_carry__2_CO_UNCONNECTED[3],add_temp_14__92_carry__2_n_1,add_temp_14__92_carry__2_n_2,add_temp_14__92_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,add_temp_14__92_carry__2_i_1_n_0,add_temp_14__92_carry__2_i_2_n_0,add_temp_14__92_carry__2_i_3_n_0}),
.O({add_temp_14__92_carry__2_n_4,add_temp_14__92_carry__2_n_5,add_temp_14__92_carry__2_n_6,add_temp_14__92_carry__2_n_7}),
.S({add_temp_14__92_carry__2_i_4_n_0,add_temp_14__92_carry__2_i_5_n_0,add_temp_14__92_carry__2_i_6_n_0,add_temp_14__92_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair41" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__2_i_1
(.I0(RESIZE30[13]),
.I1(RESIZE32[13]),
.I2(RESIZE34[13]),
.O(add_temp_14__92_carry__2_i_1_n_0));
(* HLUTNM = "lutpair40" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__2_i_2
(.I0(RESIZE30[12]),
.I1(RESIZE32[12]),
.I2(RESIZE34[12]),
.O(add_temp_14__92_carry__2_i_2_n_0));
(* HLUTNM = "lutpair39" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry__2_i_3
(.I0(RESIZE30[11]),
.I1(RESIZE32[11]),
.I2(RESIZE34[11]),
.O(add_temp_14__92_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h17E8E817E81717E8))
add_temp_14__92_carry__2_i_4
(.I0(RESIZE34[14]),
.I1(RESIZE32[14]),
.I2(RESIZE30[14]),
.I3(RESIZE32[15]),
.I4(RESIZE30[15]),
.I5(RESIZE34[15]),
.O(add_temp_14__92_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__2_i_5
(.I0(add_temp_14__92_carry__2_i_1_n_0),
.I1(RESIZE32[14]),
.I2(RESIZE30[14]),
.I3(RESIZE34[14]),
.O(add_temp_14__92_carry__2_i_5_n_0));
(* HLUTNM = "lutpair41" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__2_i_6
(.I0(RESIZE30[13]),
.I1(RESIZE32[13]),
.I2(RESIZE34[13]),
.I3(add_temp_14__92_carry__2_i_2_n_0),
.O(add_temp_14__92_carry__2_i_6_n_0));
(* HLUTNM = "lutpair40" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry__2_i_7
(.I0(RESIZE30[12]),
.I1(RESIZE32[12]),
.I2(RESIZE34[12]),
.I3(add_temp_14__92_carry__2_i_3_n_0),
.O(add_temp_14__92_carry__2_i_7_n_0));
(* HLUTNM = "lutpair30" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry_i_1
(.I0(RESIZE32[2]),
.I1(RESIZE34[2]),
.I2(RESIZE30[2]),
.O(add_temp_14__92_carry_i_1_n_0));
(* HLUTNM = "lutpair29" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry_i_2
(.I0(RESIZE32[1]),
.I1(RESIZE34[1]),
.I2(RESIZE30[1]),
.O(add_temp_14__92_carry_i_2_n_0));
(* HLUTNM = "lutpair28" *)
LUT3 #(
.INIT(8'hE8))
add_temp_14__92_carry_i_3
(.I0(RESIZE32[0]),
.I1(RESIZE34[0]),
.I2(RESIZE30[0]),
.O(add_temp_14__92_carry_i_3_n_0));
(* HLUTNM = "lutpair31" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry_i_4
(.I0(RESIZE32[3]),
.I1(RESIZE34[3]),
.I2(RESIZE30[3]),
.I3(add_temp_14__92_carry_i_1_n_0),
.O(add_temp_14__92_carry_i_4_n_0));
(* HLUTNM = "lutpair30" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry_i_5
(.I0(RESIZE32[2]),
.I1(RESIZE34[2]),
.I2(RESIZE30[2]),
.I3(add_temp_14__92_carry_i_2_n_0),
.O(add_temp_14__92_carry_i_5_n_0));
(* HLUTNM = "lutpair29" *)
LUT4 #(
.INIT(16'h6996))
add_temp_14__92_carry_i_6
(.I0(RESIZE32[1]),
.I1(RESIZE34[1]),
.I2(RESIZE30[1]),
.I3(add_temp_14__92_carry_i_3_n_0),
.O(add_temp_14__92_carry_i_6_n_0));
(* HLUTNM = "lutpair28" *)
LUT3 #(
.INIT(8'h96))
add_temp_14__92_carry_i_7
(.I0(RESIZE32[0]),
.I1(RESIZE34[0]),
.I2(RESIZE30[0]),
.O(add_temp_14__92_carry_i_7_n_0));
FDCE \data_pipeline_tmp_reg[0][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [0]),
.Q(\data_pipeline_tmp_reg[0] [0]));
FDCE \data_pipeline_tmp_reg[0][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [10]),
.Q(\data_pipeline_tmp_reg[0] [10]));
FDCE \data_pipeline_tmp_reg[0][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [11]),
.Q(\data_pipeline_tmp_reg[0] [11]));
FDCE \data_pipeline_tmp_reg[0][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [12]),
.Q(\data_pipeline_tmp_reg[0] [12]));
FDCE \data_pipeline_tmp_reg[0][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [13]),
.Q(\data_pipeline_tmp_reg[0] [13]));
FDCE \data_pipeline_tmp_reg[0][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [14]),
.Q(\data_pipeline_tmp_reg[0] [14]));
FDCE \data_pipeline_tmp_reg[0][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [15]),
.Q(\data_pipeline_tmp_reg[0] [15]));
FDCE \data_pipeline_tmp_reg[0][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [1]),
.Q(\data_pipeline_tmp_reg[0] [1]));
FDCE \data_pipeline_tmp_reg[0][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [2]),
.Q(\data_pipeline_tmp_reg[0] [2]));
FDCE \data_pipeline_tmp_reg[0][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [3]),
.Q(\data_pipeline_tmp_reg[0] [3]));
FDCE \data_pipeline_tmp_reg[0][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [4]),
.Q(\data_pipeline_tmp_reg[0] [4]));
FDCE \data_pipeline_tmp_reg[0][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [5]),
.Q(\data_pipeline_tmp_reg[0] [5]));
FDCE \data_pipeline_tmp_reg[0][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [6]),
.Q(\data_pipeline_tmp_reg[0] [6]));
FDCE \data_pipeline_tmp_reg[0][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [7]),
.Q(\data_pipeline_tmp_reg[0] [7]));
FDCE \data_pipeline_tmp_reg[0][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [8]),
.Q(\data_pipeline_tmp_reg[0] [8]));
FDCE \data_pipeline_tmp_reg[0][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[1] [9]),
.Q(\data_pipeline_tmp_reg[0] [9]));
FDCE \data_pipeline_tmp_reg[10][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [0]),
.Q(\data_pipeline_tmp_reg[10] [0]));
FDCE \data_pipeline_tmp_reg[10][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [10]),
.Q(\data_pipeline_tmp_reg[10] [10]));
FDCE \data_pipeline_tmp_reg[10][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [11]),
.Q(\data_pipeline_tmp_reg[10] [11]));
FDCE \data_pipeline_tmp_reg[10][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [12]),
.Q(\data_pipeline_tmp_reg[10] [12]));
FDCE \data_pipeline_tmp_reg[10][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [13]),
.Q(\data_pipeline_tmp_reg[10] [13]));
FDCE \data_pipeline_tmp_reg[10][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [14]),
.Q(\data_pipeline_tmp_reg[10] [14]));
FDCE \data_pipeline_tmp_reg[10][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [15]),
.Q(\data_pipeline_tmp_reg[10] [15]));
FDCE \data_pipeline_tmp_reg[10][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [1]),
.Q(\data_pipeline_tmp_reg[10] [1]));
FDCE \data_pipeline_tmp_reg[10][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [2]),
.Q(\data_pipeline_tmp_reg[10] [2]));
FDCE \data_pipeline_tmp_reg[10][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [3]),
.Q(\data_pipeline_tmp_reg[10] [3]));
FDCE \data_pipeline_tmp_reg[10][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [4]),
.Q(\data_pipeline_tmp_reg[10] [4]));
FDCE \data_pipeline_tmp_reg[10][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [5]),
.Q(\data_pipeline_tmp_reg[10] [5]));
FDCE \data_pipeline_tmp_reg[10][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [6]),
.Q(\data_pipeline_tmp_reg[10] [6]));
FDCE \data_pipeline_tmp_reg[10][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [7]),
.Q(\data_pipeline_tmp_reg[10] [7]));
FDCE \data_pipeline_tmp_reg[10][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [8]),
.Q(\data_pipeline_tmp_reg[10] [8]));
FDCE \data_pipeline_tmp_reg[10][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[11] [9]),
.Q(\data_pipeline_tmp_reg[10] [9]));
FDCE \data_pipeline_tmp_reg[11][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [0]),
.Q(\data_pipeline_tmp_reg[11] [0]));
FDCE \data_pipeline_tmp_reg[11][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [10]),
.Q(\data_pipeline_tmp_reg[11] [10]));
FDCE \data_pipeline_tmp_reg[11][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [11]),
.Q(\data_pipeline_tmp_reg[11] [11]));
FDCE \data_pipeline_tmp_reg[11][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [12]),
.Q(\data_pipeline_tmp_reg[11] [12]));
FDCE \data_pipeline_tmp_reg[11][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [13]),
.Q(\data_pipeline_tmp_reg[11] [13]));
FDCE \data_pipeline_tmp_reg[11][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [14]),
.Q(\data_pipeline_tmp_reg[11] [14]));
FDCE \data_pipeline_tmp_reg[11][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [15]),
.Q(\data_pipeline_tmp_reg[11] [15]));
FDCE \data_pipeline_tmp_reg[11][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [1]),
.Q(\data_pipeline_tmp_reg[11] [1]));
FDCE \data_pipeline_tmp_reg[11][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [2]),
.Q(\data_pipeline_tmp_reg[11] [2]));
FDCE \data_pipeline_tmp_reg[11][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [3]),
.Q(\data_pipeline_tmp_reg[11] [3]));
FDCE \data_pipeline_tmp_reg[11][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [4]),
.Q(\data_pipeline_tmp_reg[11] [4]));
FDCE \data_pipeline_tmp_reg[11][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [5]),
.Q(\data_pipeline_tmp_reg[11] [5]));
FDCE \data_pipeline_tmp_reg[11][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [6]),
.Q(\data_pipeline_tmp_reg[11] [6]));
FDCE \data_pipeline_tmp_reg[11][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [7]),
.Q(\data_pipeline_tmp_reg[11] [7]));
FDCE \data_pipeline_tmp_reg[11][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [8]),
.Q(\data_pipeline_tmp_reg[11] [8]));
FDCE \data_pipeline_tmp_reg[11][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[12] [9]),
.Q(\data_pipeline_tmp_reg[11] [9]));
FDCE \data_pipeline_tmp_reg[12][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [0]),
.Q(\data_pipeline_tmp_reg[12] [0]));
FDCE \data_pipeline_tmp_reg[12][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [10]),
.Q(\data_pipeline_tmp_reg[12] [10]));
FDCE \data_pipeline_tmp_reg[12][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [11]),
.Q(\data_pipeline_tmp_reg[12] [11]));
FDCE \data_pipeline_tmp_reg[12][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [12]),
.Q(\data_pipeline_tmp_reg[12] [12]));
FDCE \data_pipeline_tmp_reg[12][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [13]),
.Q(\data_pipeline_tmp_reg[12] [13]));
FDCE \data_pipeline_tmp_reg[12][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [14]),
.Q(\data_pipeline_tmp_reg[12] [14]));
FDCE \data_pipeline_tmp_reg[12][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [15]),
.Q(\data_pipeline_tmp_reg[12] [15]));
FDCE \data_pipeline_tmp_reg[12][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [1]),
.Q(\data_pipeline_tmp_reg[12] [1]));
FDCE \data_pipeline_tmp_reg[12][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [2]),
.Q(\data_pipeline_tmp_reg[12] [2]));
FDCE \data_pipeline_tmp_reg[12][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [3]),
.Q(\data_pipeline_tmp_reg[12] [3]));
FDCE \data_pipeline_tmp_reg[12][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [4]),
.Q(\data_pipeline_tmp_reg[12] [4]));
FDCE \data_pipeline_tmp_reg[12][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [5]),
.Q(\data_pipeline_tmp_reg[12] [5]));
FDCE \data_pipeline_tmp_reg[12][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [6]),
.Q(\data_pipeline_tmp_reg[12] [6]));
FDCE \data_pipeline_tmp_reg[12][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [7]),
.Q(\data_pipeline_tmp_reg[12] [7]));
FDCE \data_pipeline_tmp_reg[12][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [8]),
.Q(\data_pipeline_tmp_reg[12] [8]));
FDCE \data_pipeline_tmp_reg[12][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[13] [9]),
.Q(\data_pipeline_tmp_reg[12] [9]));
FDCE \data_pipeline_tmp_reg[13][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [0]),
.Q(\data_pipeline_tmp_reg[13] [0]));
FDCE \data_pipeline_tmp_reg[13][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [10]),
.Q(\data_pipeline_tmp_reg[13] [10]));
FDCE \data_pipeline_tmp_reg[13][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [11]),
.Q(\data_pipeline_tmp_reg[13] [11]));
FDCE \data_pipeline_tmp_reg[13][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [12]),
.Q(\data_pipeline_tmp_reg[13] [12]));
FDCE \data_pipeline_tmp_reg[13][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [13]),
.Q(\data_pipeline_tmp_reg[13] [13]));
FDCE \data_pipeline_tmp_reg[13][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [14]),
.Q(\data_pipeline_tmp_reg[13] [14]));
FDCE \data_pipeline_tmp_reg[13][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [15]),
.Q(\data_pipeline_tmp_reg[13] [15]));
FDCE \data_pipeline_tmp_reg[13][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [1]),
.Q(\data_pipeline_tmp_reg[13] [1]));
FDCE \data_pipeline_tmp_reg[13][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [2]),
.Q(\data_pipeline_tmp_reg[13] [2]));
FDCE \data_pipeline_tmp_reg[13][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [3]),
.Q(\data_pipeline_tmp_reg[13] [3]));
FDCE \data_pipeline_tmp_reg[13][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [4]),
.Q(\data_pipeline_tmp_reg[13] [4]));
FDCE \data_pipeline_tmp_reg[13][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [5]),
.Q(\data_pipeline_tmp_reg[13] [5]));
FDCE \data_pipeline_tmp_reg[13][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [6]),
.Q(\data_pipeline_tmp_reg[13] [6]));
FDCE \data_pipeline_tmp_reg[13][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [7]),
.Q(\data_pipeline_tmp_reg[13] [7]));
FDCE \data_pipeline_tmp_reg[13][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [8]),
.Q(\data_pipeline_tmp_reg[13] [8]));
FDCE \data_pipeline_tmp_reg[13][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[14] [9]),
.Q(\data_pipeline_tmp_reg[13] [9]));
FDCE \data_pipeline_tmp_reg[14][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [0]),
.Q(\data_pipeline_tmp_reg[14] [0]));
FDCE \data_pipeline_tmp_reg[14][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [10]),
.Q(\data_pipeline_tmp_reg[14] [10]));
FDCE \data_pipeline_tmp_reg[14][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [11]),
.Q(\data_pipeline_tmp_reg[14] [11]));
FDCE \data_pipeline_tmp_reg[14][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [12]),
.Q(\data_pipeline_tmp_reg[14] [12]));
FDCE \data_pipeline_tmp_reg[14][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [13]),
.Q(\data_pipeline_tmp_reg[14] [13]));
FDCE \data_pipeline_tmp_reg[14][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [14]),
.Q(\data_pipeline_tmp_reg[14] [14]));
FDCE \data_pipeline_tmp_reg[14][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [15]),
.Q(\data_pipeline_tmp_reg[14] [15]));
FDCE \data_pipeline_tmp_reg[14][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [1]),
.Q(\data_pipeline_tmp_reg[14] [1]));
FDCE \data_pipeline_tmp_reg[14][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [2]),
.Q(\data_pipeline_tmp_reg[14] [2]));
FDCE \data_pipeline_tmp_reg[14][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [3]),
.Q(\data_pipeline_tmp_reg[14] [3]));
FDCE \data_pipeline_tmp_reg[14][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [4]),
.Q(\data_pipeline_tmp_reg[14] [4]));
FDCE \data_pipeline_tmp_reg[14][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [5]),
.Q(\data_pipeline_tmp_reg[14] [5]));
FDCE \data_pipeline_tmp_reg[14][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [6]),
.Q(\data_pipeline_tmp_reg[14] [6]));
FDCE \data_pipeline_tmp_reg[14][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [7]),
.Q(\data_pipeline_tmp_reg[14] [7]));
FDCE \data_pipeline_tmp_reg[14][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [8]),
.Q(\data_pipeline_tmp_reg[14] [8]));
FDCE \data_pipeline_tmp_reg[14][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\write_reg_x_k_reg[15] [9]),
.Q(\data_pipeline_tmp_reg[14] [9]));
FDCE \data_pipeline_tmp_reg[1][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [0]),
.Q(\data_pipeline_tmp_reg[1] [0]));
FDCE \data_pipeline_tmp_reg[1][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [10]),
.Q(\data_pipeline_tmp_reg[1] [10]));
FDCE \data_pipeline_tmp_reg[1][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [11]),
.Q(\data_pipeline_tmp_reg[1] [11]));
FDCE \data_pipeline_tmp_reg[1][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [12]),
.Q(\data_pipeline_tmp_reg[1] [12]));
FDCE \data_pipeline_tmp_reg[1][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [13]),
.Q(\data_pipeline_tmp_reg[1] [13]));
FDCE \data_pipeline_tmp_reg[1][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [14]),
.Q(\data_pipeline_tmp_reg[1] [14]));
FDCE \data_pipeline_tmp_reg[1][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [15]),
.Q(\data_pipeline_tmp_reg[1] [15]));
FDCE \data_pipeline_tmp_reg[1][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [1]),
.Q(\data_pipeline_tmp_reg[1] [1]));
FDCE \data_pipeline_tmp_reg[1][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [2]),
.Q(\data_pipeline_tmp_reg[1] [2]));
FDCE \data_pipeline_tmp_reg[1][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [3]),
.Q(\data_pipeline_tmp_reg[1] [3]));
FDCE \data_pipeline_tmp_reg[1][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [4]),
.Q(\data_pipeline_tmp_reg[1] [4]));
FDCE \data_pipeline_tmp_reg[1][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [5]),
.Q(\data_pipeline_tmp_reg[1] [5]));
FDCE \data_pipeline_tmp_reg[1][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [6]),
.Q(\data_pipeline_tmp_reg[1] [6]));
FDCE \data_pipeline_tmp_reg[1][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [7]),
.Q(\data_pipeline_tmp_reg[1] [7]));
FDCE \data_pipeline_tmp_reg[1][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [8]),
.Q(\data_pipeline_tmp_reg[1] [8]));
FDCE \data_pipeline_tmp_reg[1][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[2] [9]),
.Q(\data_pipeline_tmp_reg[1] [9]));
FDCE \data_pipeline_tmp_reg[2][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [0]),
.Q(\data_pipeline_tmp_reg[2] [0]));
FDCE \data_pipeline_tmp_reg[2][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [10]),
.Q(\data_pipeline_tmp_reg[2] [10]));
FDCE \data_pipeline_tmp_reg[2][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [11]),
.Q(\data_pipeline_tmp_reg[2] [11]));
FDCE \data_pipeline_tmp_reg[2][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [12]),
.Q(\data_pipeline_tmp_reg[2] [12]));
FDCE \data_pipeline_tmp_reg[2][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [13]),
.Q(\data_pipeline_tmp_reg[2] [13]));
FDCE \data_pipeline_tmp_reg[2][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [14]),
.Q(\data_pipeline_tmp_reg[2] [14]));
FDCE \data_pipeline_tmp_reg[2][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [15]),
.Q(\data_pipeline_tmp_reg[2] [15]));
FDCE \data_pipeline_tmp_reg[2][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [1]),
.Q(\data_pipeline_tmp_reg[2] [1]));
FDCE \data_pipeline_tmp_reg[2][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [2]),
.Q(\data_pipeline_tmp_reg[2] [2]));
FDCE \data_pipeline_tmp_reg[2][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [3]),
.Q(\data_pipeline_tmp_reg[2] [3]));
FDCE \data_pipeline_tmp_reg[2][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [4]),
.Q(\data_pipeline_tmp_reg[2] [4]));
FDCE \data_pipeline_tmp_reg[2][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [5]),
.Q(\data_pipeline_tmp_reg[2] [5]));
FDCE \data_pipeline_tmp_reg[2][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [6]),
.Q(\data_pipeline_tmp_reg[2] [6]));
FDCE \data_pipeline_tmp_reg[2][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [7]),
.Q(\data_pipeline_tmp_reg[2] [7]));
FDCE \data_pipeline_tmp_reg[2][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [8]),
.Q(\data_pipeline_tmp_reg[2] [8]));
FDCE \data_pipeline_tmp_reg[2][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[3] [9]),
.Q(\data_pipeline_tmp_reg[2] [9]));
FDCE \data_pipeline_tmp_reg[3][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [0]),
.Q(\data_pipeline_tmp_reg[3] [0]));
FDCE \data_pipeline_tmp_reg[3][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [10]),
.Q(\data_pipeline_tmp_reg[3] [10]));
FDCE \data_pipeline_tmp_reg[3][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [11]),
.Q(\data_pipeline_tmp_reg[3] [11]));
FDCE \data_pipeline_tmp_reg[3][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [12]),
.Q(\data_pipeline_tmp_reg[3] [12]));
FDCE \data_pipeline_tmp_reg[3][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [13]),
.Q(\data_pipeline_tmp_reg[3] [13]));
FDCE \data_pipeline_tmp_reg[3][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [14]),
.Q(\data_pipeline_tmp_reg[3] [14]));
FDCE \data_pipeline_tmp_reg[3][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [15]),
.Q(\data_pipeline_tmp_reg[3] [15]));
FDCE \data_pipeline_tmp_reg[3][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [1]),
.Q(\data_pipeline_tmp_reg[3] [1]));
FDCE \data_pipeline_tmp_reg[3][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [2]),
.Q(\data_pipeline_tmp_reg[3] [2]));
FDCE \data_pipeline_tmp_reg[3][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [3]),
.Q(\data_pipeline_tmp_reg[3] [3]));
FDCE \data_pipeline_tmp_reg[3][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [4]),
.Q(\data_pipeline_tmp_reg[3] [4]));
FDCE \data_pipeline_tmp_reg[3][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [5]),
.Q(\data_pipeline_tmp_reg[3] [5]));
FDCE \data_pipeline_tmp_reg[3][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [6]),
.Q(\data_pipeline_tmp_reg[3] [6]));
FDCE \data_pipeline_tmp_reg[3][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [7]),
.Q(\data_pipeline_tmp_reg[3] [7]));
FDCE \data_pipeline_tmp_reg[3][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [8]),
.Q(\data_pipeline_tmp_reg[3] [8]));
FDCE \data_pipeline_tmp_reg[3][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[4] [9]),
.Q(\data_pipeline_tmp_reg[3] [9]));
FDCE \data_pipeline_tmp_reg[4][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [0]),
.Q(\data_pipeline_tmp_reg[4] [0]));
FDCE \data_pipeline_tmp_reg[4][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [10]),
.Q(\data_pipeline_tmp_reg[4] [10]));
FDCE \data_pipeline_tmp_reg[4][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [11]),
.Q(\data_pipeline_tmp_reg[4] [11]));
FDCE \data_pipeline_tmp_reg[4][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [12]),
.Q(\data_pipeline_tmp_reg[4] [12]));
FDCE \data_pipeline_tmp_reg[4][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [13]),
.Q(\data_pipeline_tmp_reg[4] [13]));
FDCE \data_pipeline_tmp_reg[4][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [14]),
.Q(\data_pipeline_tmp_reg[4] [14]));
FDCE \data_pipeline_tmp_reg[4][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [15]),
.Q(\data_pipeline_tmp_reg[4] [15]));
FDCE \data_pipeline_tmp_reg[4][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [1]),
.Q(\data_pipeline_tmp_reg[4] [1]));
FDCE \data_pipeline_tmp_reg[4][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [2]),
.Q(\data_pipeline_tmp_reg[4] [2]));
FDCE \data_pipeline_tmp_reg[4][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [3]),
.Q(\data_pipeline_tmp_reg[4] [3]));
FDCE \data_pipeline_tmp_reg[4][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [4]),
.Q(\data_pipeline_tmp_reg[4] [4]));
FDCE \data_pipeline_tmp_reg[4][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [5]),
.Q(\data_pipeline_tmp_reg[4] [5]));
FDCE \data_pipeline_tmp_reg[4][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [6]),
.Q(\data_pipeline_tmp_reg[4] [6]));
FDCE \data_pipeline_tmp_reg[4][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [7]),
.Q(\data_pipeline_tmp_reg[4] [7]));
FDCE \data_pipeline_tmp_reg[4][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [8]),
.Q(\data_pipeline_tmp_reg[4] [8]));
FDCE \data_pipeline_tmp_reg[4][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[5] [9]),
.Q(\data_pipeline_tmp_reg[4] [9]));
FDCE \data_pipeline_tmp_reg[5][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [0]),
.Q(\data_pipeline_tmp_reg[5] [0]));
FDCE \data_pipeline_tmp_reg[5][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [10]),
.Q(\data_pipeline_tmp_reg[5] [10]));
FDCE \data_pipeline_tmp_reg[5][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [11]),
.Q(\data_pipeline_tmp_reg[5] [11]));
FDCE \data_pipeline_tmp_reg[5][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [12]),
.Q(\data_pipeline_tmp_reg[5] [12]));
FDCE \data_pipeline_tmp_reg[5][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [13]),
.Q(\data_pipeline_tmp_reg[5] [13]));
FDCE \data_pipeline_tmp_reg[5][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [14]),
.Q(\data_pipeline_tmp_reg[5] [14]));
FDCE \data_pipeline_tmp_reg[5][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [15]),
.Q(\data_pipeline_tmp_reg[5] [15]));
FDCE \data_pipeline_tmp_reg[5][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [1]),
.Q(\data_pipeline_tmp_reg[5] [1]));
FDCE \data_pipeline_tmp_reg[5][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [2]),
.Q(\data_pipeline_tmp_reg[5] [2]));
FDCE \data_pipeline_tmp_reg[5][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [3]),
.Q(\data_pipeline_tmp_reg[5] [3]));
FDCE \data_pipeline_tmp_reg[5][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [4]),
.Q(\data_pipeline_tmp_reg[5] [4]));
FDCE \data_pipeline_tmp_reg[5][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [5]),
.Q(\data_pipeline_tmp_reg[5] [5]));
FDCE \data_pipeline_tmp_reg[5][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [6]),
.Q(\data_pipeline_tmp_reg[5] [6]));
FDCE \data_pipeline_tmp_reg[5][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [7]),
.Q(\data_pipeline_tmp_reg[5] [7]));
FDCE \data_pipeline_tmp_reg[5][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [8]),
.Q(\data_pipeline_tmp_reg[5] [8]));
FDCE \data_pipeline_tmp_reg[5][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[6] [9]),
.Q(\data_pipeline_tmp_reg[5] [9]));
FDCE \data_pipeline_tmp_reg[6][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [0]),
.Q(\data_pipeline_tmp_reg[6] [0]));
FDCE \data_pipeline_tmp_reg[6][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [10]),
.Q(\data_pipeline_tmp_reg[6] [10]));
FDCE \data_pipeline_tmp_reg[6][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [11]),
.Q(\data_pipeline_tmp_reg[6] [11]));
FDCE \data_pipeline_tmp_reg[6][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [12]),
.Q(\data_pipeline_tmp_reg[6] [12]));
FDCE \data_pipeline_tmp_reg[6][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [13]),
.Q(\data_pipeline_tmp_reg[6] [13]));
FDCE \data_pipeline_tmp_reg[6][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [14]),
.Q(\data_pipeline_tmp_reg[6] [14]));
FDCE \data_pipeline_tmp_reg[6][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [15]),
.Q(\data_pipeline_tmp_reg[6] [15]));
FDCE \data_pipeline_tmp_reg[6][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [1]),
.Q(\data_pipeline_tmp_reg[6] [1]));
FDCE \data_pipeline_tmp_reg[6][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [2]),
.Q(\data_pipeline_tmp_reg[6] [2]));
FDCE \data_pipeline_tmp_reg[6][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [3]),
.Q(\data_pipeline_tmp_reg[6] [3]));
FDCE \data_pipeline_tmp_reg[6][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [4]),
.Q(\data_pipeline_tmp_reg[6] [4]));
FDCE \data_pipeline_tmp_reg[6][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [5]),
.Q(\data_pipeline_tmp_reg[6] [5]));
FDCE \data_pipeline_tmp_reg[6][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [6]),
.Q(\data_pipeline_tmp_reg[6] [6]));
FDCE \data_pipeline_tmp_reg[6][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [7]),
.Q(\data_pipeline_tmp_reg[6] [7]));
FDCE \data_pipeline_tmp_reg[6][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [8]),
.Q(\data_pipeline_tmp_reg[6] [8]));
FDCE \data_pipeline_tmp_reg[6][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[7] [9]),
.Q(\data_pipeline_tmp_reg[6] [9]));
FDCE \data_pipeline_tmp_reg[7][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [0]),
.Q(\data_pipeline_tmp_reg[7] [0]));
FDCE \data_pipeline_tmp_reg[7][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [10]),
.Q(\data_pipeline_tmp_reg[7] [10]));
FDCE \data_pipeline_tmp_reg[7][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [11]),
.Q(\data_pipeline_tmp_reg[7] [11]));
FDCE \data_pipeline_tmp_reg[7][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [12]),
.Q(\data_pipeline_tmp_reg[7] [12]));
FDCE \data_pipeline_tmp_reg[7][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [13]),
.Q(\data_pipeline_tmp_reg[7] [13]));
FDCE \data_pipeline_tmp_reg[7][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [14]),
.Q(\data_pipeline_tmp_reg[7] [14]));
FDCE \data_pipeline_tmp_reg[7][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [15]),
.Q(\data_pipeline_tmp_reg[7] [15]));
FDCE \data_pipeline_tmp_reg[7][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [1]),
.Q(\data_pipeline_tmp_reg[7] [1]));
FDCE \data_pipeline_tmp_reg[7][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [2]),
.Q(\data_pipeline_tmp_reg[7] [2]));
FDCE \data_pipeline_tmp_reg[7][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [3]),
.Q(\data_pipeline_tmp_reg[7] [3]));
FDCE \data_pipeline_tmp_reg[7][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [4]),
.Q(\data_pipeline_tmp_reg[7] [4]));
FDCE \data_pipeline_tmp_reg[7][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [5]),
.Q(\data_pipeline_tmp_reg[7] [5]));
FDCE \data_pipeline_tmp_reg[7][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [6]),
.Q(\data_pipeline_tmp_reg[7] [6]));
FDCE \data_pipeline_tmp_reg[7][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [7]),
.Q(\data_pipeline_tmp_reg[7] [7]));
FDCE \data_pipeline_tmp_reg[7][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [8]),
.Q(\data_pipeline_tmp_reg[7] [8]));
FDCE \data_pipeline_tmp_reg[7][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[8] [9]),
.Q(\data_pipeline_tmp_reg[7] [9]));
FDCE \data_pipeline_tmp_reg[8][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [0]),
.Q(\data_pipeline_tmp_reg[8] [0]));
FDCE \data_pipeline_tmp_reg[8][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [10]),
.Q(\data_pipeline_tmp_reg[8] [10]));
FDCE \data_pipeline_tmp_reg[8][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [11]),
.Q(\data_pipeline_tmp_reg[8] [11]));
FDCE \data_pipeline_tmp_reg[8][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [12]),
.Q(\data_pipeline_tmp_reg[8] [12]));
FDCE \data_pipeline_tmp_reg[8][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [13]),
.Q(\data_pipeline_tmp_reg[8] [13]));
FDCE \data_pipeline_tmp_reg[8][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [14]),
.Q(\data_pipeline_tmp_reg[8] [14]));
FDCE \data_pipeline_tmp_reg[8][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [15]),
.Q(\data_pipeline_tmp_reg[8] [15]));
FDCE \data_pipeline_tmp_reg[8][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [1]),
.Q(\data_pipeline_tmp_reg[8] [1]));
FDCE \data_pipeline_tmp_reg[8][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [2]),
.Q(\data_pipeline_tmp_reg[8] [2]));
FDCE \data_pipeline_tmp_reg[8][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [3]),
.Q(\data_pipeline_tmp_reg[8] [3]));
FDCE \data_pipeline_tmp_reg[8][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [4]),
.Q(\data_pipeline_tmp_reg[8] [4]));
FDCE \data_pipeline_tmp_reg[8][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [5]),
.Q(\data_pipeline_tmp_reg[8] [5]));
FDCE \data_pipeline_tmp_reg[8][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [6]),
.Q(\data_pipeline_tmp_reg[8] [6]));
FDCE \data_pipeline_tmp_reg[8][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [7]),
.Q(\data_pipeline_tmp_reg[8] [7]));
FDCE \data_pipeline_tmp_reg[8][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [8]),
.Q(\data_pipeline_tmp_reg[8] [8]));
FDCE \data_pipeline_tmp_reg[8][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[9] [9]),
.Q(\data_pipeline_tmp_reg[8] [9]));
FDCE \data_pipeline_tmp_reg[9][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [0]),
.Q(\data_pipeline_tmp_reg[9] [0]));
FDCE \data_pipeline_tmp_reg[9][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [10]),
.Q(\data_pipeline_tmp_reg[9] [10]));
FDCE \data_pipeline_tmp_reg[9][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [11]),
.Q(\data_pipeline_tmp_reg[9] [11]));
FDCE \data_pipeline_tmp_reg[9][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [12]),
.Q(\data_pipeline_tmp_reg[9] [12]));
FDCE \data_pipeline_tmp_reg[9][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [13]),
.Q(\data_pipeline_tmp_reg[9] [13]));
FDCE \data_pipeline_tmp_reg[9][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [14]),
.Q(\data_pipeline_tmp_reg[9] [14]));
FDCE \data_pipeline_tmp_reg[9][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [15]),
.Q(\data_pipeline_tmp_reg[9] [15]));
FDCE \data_pipeline_tmp_reg[9][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [1]),
.Q(\data_pipeline_tmp_reg[9] [1]));
FDCE \data_pipeline_tmp_reg[9][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [2]),
.Q(\data_pipeline_tmp_reg[9] [2]));
FDCE \data_pipeline_tmp_reg[9][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [3]),
.Q(\data_pipeline_tmp_reg[9] [3]));
FDCE \data_pipeline_tmp_reg[9][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [4]),
.Q(\data_pipeline_tmp_reg[9] [4]));
FDCE \data_pipeline_tmp_reg[9][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [5]),
.Q(\data_pipeline_tmp_reg[9] [5]));
FDCE \data_pipeline_tmp_reg[9][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [6]),
.Q(\data_pipeline_tmp_reg[9] [6]));
FDCE \data_pipeline_tmp_reg[9][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [7]),
.Q(\data_pipeline_tmp_reg[9] [7]));
FDCE \data_pipeline_tmp_reg[9][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [8]),
.Q(\data_pipeline_tmp_reg[9] [8]));
FDCE \data_pipeline_tmp_reg[9][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\data_pipeline_tmp_reg[10] [9]),
.Q(\data_pipeline_tmp_reg[9] [9]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp
(.A({\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[0]_15 [15],\weight_reg[0]_15 [15],\weight_reg[0]_15 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_P_UNCONNECTED[47:32],mul_temp_n_74,mul_temp_n_75,mul_temp_n_76,mul_temp_n_77,mul_temp_n_78,mul_temp_n_79,mul_temp_n_80,mul_temp_n_81,mul_temp_n_82,mul_temp_n_83,mul_temp_n_84,mul_temp_n_85,mul_temp_n_86,mul_temp_n_87,mul_temp_n_88,mul_temp_n_89,mul_temp_n_90,\^mul_temp ,mul_temp_n_92,mul_temp_n_93,mul_temp_n_94,mul_temp_n_95,mul_temp_n_96,mul_temp_n_97,mul_temp_n_98,mul_temp_n_99,mul_temp_n_100,mul_temp_n_101,mul_temp_n_102,mul_temp_n_103,mul_temp_n_104,mul_temp_n_105}),
.PATTERNBDETECT(NLW_mul_temp_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_1
(.A({\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_1_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[1]_0 [15],\weight_reg[1]_0 [15],\weight_reg[1]_0 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_1_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_1_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_1_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_1_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_1_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_1_P_UNCONNECTED[47:32],mul_temp_1_n_74,mul_temp_1_n_75,mul_temp_1_n_76,mul_temp_1_n_77,mul_temp_1_n_78,mul_temp_1_n_79,mul_temp_1_n_80,mul_temp_1_n_81,mul_temp_1_n_82,mul_temp_1_n_83,mul_temp_1_n_84,mul_temp_1_n_85,mul_temp_1_n_86,mul_temp_1_n_87,mul_temp_1_n_88,mul_temp_1_n_89,mul_temp_1_n_90,\^mul_temp_1 ,mul_temp_1_n_92,mul_temp_1_n_93,mul_temp_1_n_94,mul_temp_1_n_95,mul_temp_1_n_96,mul_temp_1_n_97,mul_temp_1_n_98,mul_temp_1_n_99,mul_temp_1_n_100,mul_temp_1_n_101,mul_temp_1_n_102,mul_temp_1_n_103,mul_temp_1_n_104,mul_temp_1_n_105}),
.PATTERNBDETECT(NLW_mul_temp_1_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_1_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_1_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_1_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_10
(.A({\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_10_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[10]_9 [15],\weight_reg[10]_9 [15],\weight_reg[10]_9 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_10_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_10_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_10_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_10_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_10_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_10_P_UNCONNECTED[47:32],mul_temp_10_n_74,mul_temp_10_n_75,mul_temp_10_n_76,mul_temp_10_n_77,mul_temp_10_n_78,mul_temp_10_n_79,mul_temp_10_n_80,mul_temp_10_n_81,mul_temp_10_n_82,mul_temp_10_n_83,mul_temp_10_n_84,mul_temp_10_n_85,mul_temp_10_n_86,mul_temp_10_n_87,mul_temp_10_n_88,mul_temp_10_n_89,mul_temp_10_n_90,\^mul_temp_10 ,mul_temp_10_n_92,mul_temp_10_n_93,mul_temp_10_n_94,mul_temp_10_n_95,mul_temp_10_n_96,mul_temp_10_n_97,mul_temp_10_n_98,mul_temp_10_n_99,mul_temp_10_n_100,mul_temp_10_n_101,mul_temp_10_n_102,mul_temp_10_n_103,mul_temp_10_n_104,mul_temp_10_n_105}),
.PATTERNBDETECT(NLW_mul_temp_10_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_10_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_10_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_10_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_11
(.A({\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_11_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[11]_10 [15],\weight_reg[11]_10 [15],\weight_reg[11]_10 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_11_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_11_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_11_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_11_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_11_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_11_P_UNCONNECTED[47:32],mul_temp_11_n_74,mul_temp_11_n_75,mul_temp_11_n_76,mul_temp_11_n_77,mul_temp_11_n_78,mul_temp_11_n_79,mul_temp_11_n_80,mul_temp_11_n_81,mul_temp_11_n_82,mul_temp_11_n_83,mul_temp_11_n_84,mul_temp_11_n_85,mul_temp_11_n_86,mul_temp_11_n_87,mul_temp_11_n_88,mul_temp_11_n_89,mul_temp_11_n_90,\^mul_temp_11 ,mul_temp_11_n_92,mul_temp_11_n_93,mul_temp_11_n_94,mul_temp_11_n_95,mul_temp_11_n_96,mul_temp_11_n_97,mul_temp_11_n_98,mul_temp_11_n_99,mul_temp_11_n_100,mul_temp_11_n_101,mul_temp_11_n_102,mul_temp_11_n_103,mul_temp_11_n_104,mul_temp_11_n_105}),
.PATTERNBDETECT(NLW_mul_temp_11_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_11_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_11_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_11_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_12
(.A({\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_12_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[12]_11 [15],\weight_reg[12]_11 [15],\weight_reg[12]_11 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_12_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_12_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_12_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_12_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_12_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_12_P_UNCONNECTED[47:32],mul_temp_12_n_74,mul_temp_12_n_75,mul_temp_12_n_76,mul_temp_12_n_77,mul_temp_12_n_78,mul_temp_12_n_79,mul_temp_12_n_80,mul_temp_12_n_81,mul_temp_12_n_82,mul_temp_12_n_83,mul_temp_12_n_84,mul_temp_12_n_85,mul_temp_12_n_86,mul_temp_12_n_87,mul_temp_12_n_88,mul_temp_12_n_89,mul_temp_12_n_90,\^mul_temp_12 ,mul_temp_12_n_92,mul_temp_12_n_93,mul_temp_12_n_94,mul_temp_12_n_95,mul_temp_12_n_96,mul_temp_12_n_97,mul_temp_12_n_98,mul_temp_12_n_99,mul_temp_12_n_100,mul_temp_12_n_101,mul_temp_12_n_102,mul_temp_12_n_103,mul_temp_12_n_104,mul_temp_12_n_105}),
.PATTERNBDETECT(NLW_mul_temp_12_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_12_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_12_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_12_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_13
(.A({\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_13_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[13]_12 [15],\weight_reg[13]_12 [15],\weight_reg[13]_12 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_13_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_13_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_13_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_13_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_13_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_13_P_UNCONNECTED[47:32],mul_temp_13_n_74,mul_temp_13_n_75,mul_temp_13_n_76,mul_temp_13_n_77,mul_temp_13_n_78,mul_temp_13_n_79,mul_temp_13_n_80,mul_temp_13_n_81,mul_temp_13_n_82,mul_temp_13_n_83,mul_temp_13_n_84,mul_temp_13_n_85,mul_temp_13_n_86,mul_temp_13_n_87,mul_temp_13_n_88,mul_temp_13_n_89,mul_temp_13_n_90,\^mul_temp_13 ,mul_temp_13_n_92,mul_temp_13_n_93,mul_temp_13_n_94,mul_temp_13_n_95,mul_temp_13_n_96,mul_temp_13_n_97,mul_temp_13_n_98,mul_temp_13_n_99,mul_temp_13_n_100,mul_temp_13_n_101,mul_temp_13_n_102,mul_temp_13_n_103,mul_temp_13_n_104,mul_temp_13_n_105}),
.PATTERNBDETECT(NLW_mul_temp_13_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_13_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_13_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_13_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_14
(.A({\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_14_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[14]_13 [15],\weight_reg[14]_13 [15],\weight_reg[14]_13 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_14_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_14_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_14_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_14_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_14_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_14_P_UNCONNECTED[47:32],mul_temp_14_n_74,mul_temp_14_n_75,mul_temp_14_n_76,mul_temp_14_n_77,mul_temp_14_n_78,mul_temp_14_n_79,mul_temp_14_n_80,mul_temp_14_n_81,mul_temp_14_n_82,mul_temp_14_n_83,mul_temp_14_n_84,mul_temp_14_n_85,mul_temp_14_n_86,mul_temp_14_n_87,mul_temp_14_n_88,mul_temp_14_n_89,mul_temp_14_n_90,\^mul_temp_14 ,mul_temp_14_n_92,mul_temp_14_n_93,mul_temp_14_n_94,mul_temp_14_n_95,mul_temp_14_n_96,mul_temp_14_n_97,mul_temp_14_n_98,mul_temp_14_n_99,mul_temp_14_n_100,mul_temp_14_n_101,mul_temp_14_n_102,mul_temp_14_n_103,mul_temp_14_n_104,mul_temp_14_n_105}),
.PATTERNBDETECT(NLW_mul_temp_14_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_14_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_14_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_14_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_15
(.A({\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_15_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[15]_14 [15],\weight_reg[15]_14 [15],\weight_reg[15]_14 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_15_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_15_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_15_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_15_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_15_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_15_P_UNCONNECTED[47:32],mul_temp_15_n_74,mul_temp_15_n_75,mul_temp_15_n_76,mul_temp_15_n_77,mul_temp_15_n_78,mul_temp_15_n_79,mul_temp_15_n_80,mul_temp_15_n_81,mul_temp_15_n_82,mul_temp_15_n_83,mul_temp_15_n_84,mul_temp_15_n_85,mul_temp_15_n_86,mul_temp_15_n_87,mul_temp_15_n_88,mul_temp_15_n_89,mul_temp_15_n_90,\^mul_temp_15 ,mul_temp_15_n_92,mul_temp_15_n_93,mul_temp_15_n_94,mul_temp_15_n_95,mul_temp_15_n_96,mul_temp_15_n_97,mul_temp_15_n_98,mul_temp_15_n_99,mul_temp_15_n_100,mul_temp_15_n_101,mul_temp_15_n_102,mul_temp_15_n_103,mul_temp_15_n_104,mul_temp_15_n_105}),
.PATTERNBDETECT(NLW_mul_temp_15_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_15_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_15_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_15_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_17
(.A({\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] [15],\data_pipeline_tmp_reg[0] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_17_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_17_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_17_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_17_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_17_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_17_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_17_P_UNCONNECTED[47:32],mul_temp_17_n_74,mul_temp_17_n_75,mul_temp_17_n_76,mul_temp_17_n_77,mul_temp_17_n_78,mul_temp_17_n_79,mul_temp_17_n_80,mul_temp_17_n_81,mul_temp_17_n_82,mul_temp_17_n_83,mul_temp_17_n_84,mul_temp_17_n_85,mul_temp_17_n_86,mul_temp_17_n_87,mul_temp_17_n_88,mul_temp_17_n_89,mul_temp_17_n_90,\^mul_temp_17 ,mul_temp_17_n_92,mul_temp_17_n_93,mul_temp_17_n_94,mul_temp_17_n_95,mul_temp_17_n_96,mul_temp_17_n_97,mul_temp_17_n_98,mul_temp_17_n_99,mul_temp_17_n_100,mul_temp_17_n_101,mul_temp_17_n_102,mul_temp_17_n_103,mul_temp_17_n_104,mul_temp_17_n_105}),
.PATTERNBDETECT(NLW_mul_temp_17_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_17_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_17_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_17_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_18
(.A({\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] [15],\data_pipeline_tmp_reg[1] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_18_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_18_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_18_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_18_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_18_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_18_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_18_P_UNCONNECTED[47:32],mul_temp_18_n_74,mul_temp_18_n_75,mul_temp_18_n_76,mul_temp_18_n_77,mul_temp_18_n_78,mul_temp_18_n_79,mul_temp_18_n_80,mul_temp_18_n_81,mul_temp_18_n_82,mul_temp_18_n_83,mul_temp_18_n_84,mul_temp_18_n_85,mul_temp_18_n_86,mul_temp_18_n_87,mul_temp_18_n_88,mul_temp_18_n_89,mul_temp_18_n_90,\^mul_temp_18 ,mul_temp_18_n_92,mul_temp_18_n_93,mul_temp_18_n_94,mul_temp_18_n_95,mul_temp_18_n_96,mul_temp_18_n_97,mul_temp_18_n_98,mul_temp_18_n_99,mul_temp_18_n_100,mul_temp_18_n_101,mul_temp_18_n_102,mul_temp_18_n_103,mul_temp_18_n_104,mul_temp_18_n_105}),
.PATTERNBDETECT(NLW_mul_temp_18_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_18_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_18_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_18_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_19
(.A({\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_19_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_19_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_19_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_19_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_19_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_19_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_19_P_UNCONNECTED[47:32],mul_temp_19_n_74,mul_temp_19_n_75,mul_temp_19_n_76,mul_temp_19_n_77,mul_temp_19_n_78,mul_temp_19_n_79,mul_temp_19_n_80,mul_temp_19_n_81,mul_temp_19_n_82,mul_temp_19_n_83,mul_temp_19_n_84,mul_temp_19_n_85,mul_temp_19_n_86,mul_temp_19_n_87,mul_temp_19_n_88,mul_temp_19_n_89,mul_temp_19_n_90,\^mul_temp_19 ,mul_temp_19_n_92,mul_temp_19_n_93,mul_temp_19_n_94,mul_temp_19_n_95,mul_temp_19_n_96,mul_temp_19_n_97,mul_temp_19_n_98,mul_temp_19_n_99,mul_temp_19_n_100,mul_temp_19_n_101,mul_temp_19_n_102,mul_temp_19_n_103,mul_temp_19_n_104,mul_temp_19_n_105}),
.PATTERNBDETECT(NLW_mul_temp_19_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_19_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_19_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_19_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_2
(.A({\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] [15],\data_pipeline_tmp_reg[2] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_2_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[2]_1 [15],\weight_reg[2]_1 [15],\weight_reg[2]_1 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_2_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_2_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_2_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_2_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_2_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_2_P_UNCONNECTED[47:32],mul_temp_2_n_74,mul_temp_2_n_75,mul_temp_2_n_76,mul_temp_2_n_77,mul_temp_2_n_78,mul_temp_2_n_79,mul_temp_2_n_80,mul_temp_2_n_81,mul_temp_2_n_82,mul_temp_2_n_83,mul_temp_2_n_84,mul_temp_2_n_85,mul_temp_2_n_86,mul_temp_2_n_87,mul_temp_2_n_88,mul_temp_2_n_89,mul_temp_2_n_90,\^mul_temp_2 ,mul_temp_2_n_92,mul_temp_2_n_93,mul_temp_2_n_94,mul_temp_2_n_95,mul_temp_2_n_96,mul_temp_2_n_97,mul_temp_2_n_98,mul_temp_2_n_99,mul_temp_2_n_100,mul_temp_2_n_101,mul_temp_2_n_102,mul_temp_2_n_103,mul_temp_2_n_104,mul_temp_2_n_105}),
.PATTERNBDETECT(NLW_mul_temp_2_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_2_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_2_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_2_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_20
(.A({\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_20_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_20_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_20_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_20_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_20_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_20_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_20_P_UNCONNECTED[47:32],mul_temp_20_n_74,mul_temp_20_n_75,mul_temp_20_n_76,mul_temp_20_n_77,mul_temp_20_n_78,mul_temp_20_n_79,mul_temp_20_n_80,mul_temp_20_n_81,mul_temp_20_n_82,mul_temp_20_n_83,mul_temp_20_n_84,mul_temp_20_n_85,mul_temp_20_n_86,mul_temp_20_n_87,mul_temp_20_n_88,mul_temp_20_n_89,mul_temp_20_n_90,\^mul_temp_20 ,mul_temp_20_n_92,mul_temp_20_n_93,mul_temp_20_n_94,mul_temp_20_n_95,mul_temp_20_n_96,mul_temp_20_n_97,mul_temp_20_n_98,mul_temp_20_n_99,mul_temp_20_n_100,mul_temp_20_n_101,mul_temp_20_n_102,mul_temp_20_n_103,mul_temp_20_n_104,mul_temp_20_n_105}),
.PATTERNBDETECT(NLW_mul_temp_20_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_20_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_20_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_20_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_21
(.A({\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_21_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_21_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_21_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_21_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_21_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_21_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_21_P_UNCONNECTED[47:32],mul_temp_21_n_74,mul_temp_21_n_75,mul_temp_21_n_76,mul_temp_21_n_77,mul_temp_21_n_78,mul_temp_21_n_79,mul_temp_21_n_80,mul_temp_21_n_81,mul_temp_21_n_82,mul_temp_21_n_83,mul_temp_21_n_84,mul_temp_21_n_85,mul_temp_21_n_86,mul_temp_21_n_87,mul_temp_21_n_88,mul_temp_21_n_89,mul_temp_21_n_90,\^mul_temp_21 ,mul_temp_21_n_92,mul_temp_21_n_93,mul_temp_21_n_94,mul_temp_21_n_95,mul_temp_21_n_96,mul_temp_21_n_97,mul_temp_21_n_98,mul_temp_21_n_99,mul_temp_21_n_100,mul_temp_21_n_101,mul_temp_21_n_102,mul_temp_21_n_103,mul_temp_21_n_104,mul_temp_21_n_105}),
.PATTERNBDETECT(NLW_mul_temp_21_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_21_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_21_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_21_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_22
(.A({\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_22_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_22_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_22_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_22_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_22_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_22_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_22_P_UNCONNECTED[47:32],mul_temp_22_n_74,mul_temp_22_n_75,mul_temp_22_n_76,mul_temp_22_n_77,mul_temp_22_n_78,mul_temp_22_n_79,mul_temp_22_n_80,mul_temp_22_n_81,mul_temp_22_n_82,mul_temp_22_n_83,mul_temp_22_n_84,mul_temp_22_n_85,mul_temp_22_n_86,mul_temp_22_n_87,mul_temp_22_n_88,mul_temp_22_n_89,mul_temp_22_n_90,\^mul_temp_22 ,mul_temp_22_n_92,mul_temp_22_n_93,mul_temp_22_n_94,mul_temp_22_n_95,mul_temp_22_n_96,mul_temp_22_n_97,mul_temp_22_n_98,mul_temp_22_n_99,mul_temp_22_n_100,mul_temp_22_n_101,mul_temp_22_n_102,mul_temp_22_n_103,mul_temp_22_n_104,mul_temp_22_n_105}),
.PATTERNBDETECT(NLW_mul_temp_22_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_22_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_22_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_22_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_23
(.A({\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_23_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_23_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_23_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_23_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_23_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_23_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_23_P_UNCONNECTED[47:32],mul_temp_23_n_74,mul_temp_23_n_75,mul_temp_23_n_76,mul_temp_23_n_77,mul_temp_23_n_78,mul_temp_23_n_79,mul_temp_23_n_80,mul_temp_23_n_81,mul_temp_23_n_82,mul_temp_23_n_83,mul_temp_23_n_84,mul_temp_23_n_85,mul_temp_23_n_86,mul_temp_23_n_87,mul_temp_23_n_88,mul_temp_23_n_89,mul_temp_23_n_90,\^mul_temp_23 ,mul_temp_23_n_92,mul_temp_23_n_93,mul_temp_23_n_94,mul_temp_23_n_95,mul_temp_23_n_96,mul_temp_23_n_97,mul_temp_23_n_98,mul_temp_23_n_99,mul_temp_23_n_100,mul_temp_23_n_101,mul_temp_23_n_102,mul_temp_23_n_103,mul_temp_23_n_104,mul_temp_23_n_105}),
.PATTERNBDETECT(NLW_mul_temp_23_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_23_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_23_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_23_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_24
(.A({\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_24_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_24_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_24_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_24_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_24_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_24_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_24_P_UNCONNECTED[47:32],mul_temp_24_n_74,mul_temp_24_n_75,mul_temp_24_n_76,mul_temp_24_n_77,mul_temp_24_n_78,mul_temp_24_n_79,mul_temp_24_n_80,mul_temp_24_n_81,mul_temp_24_n_82,mul_temp_24_n_83,mul_temp_24_n_84,mul_temp_24_n_85,mul_temp_24_n_86,mul_temp_24_n_87,mul_temp_24_n_88,mul_temp_24_n_89,mul_temp_24_n_90,\^mul_temp_24 ,mul_temp_24_n_92,mul_temp_24_n_93,mul_temp_24_n_94,mul_temp_24_n_95,mul_temp_24_n_96,mul_temp_24_n_97,mul_temp_24_n_98,mul_temp_24_n_99,mul_temp_24_n_100,mul_temp_24_n_101,mul_temp_24_n_102,mul_temp_24_n_103,mul_temp_24_n_104,mul_temp_24_n_105}),
.PATTERNBDETECT(NLW_mul_temp_24_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_24_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_24_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_24_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_25
(.A({\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_25_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_25_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_25_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_25_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_25_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_25_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_25_P_UNCONNECTED[47:32],mul_temp_25_n_74,mul_temp_25_n_75,mul_temp_25_n_76,mul_temp_25_n_77,mul_temp_25_n_78,mul_temp_25_n_79,mul_temp_25_n_80,mul_temp_25_n_81,mul_temp_25_n_82,mul_temp_25_n_83,mul_temp_25_n_84,mul_temp_25_n_85,mul_temp_25_n_86,mul_temp_25_n_87,mul_temp_25_n_88,mul_temp_25_n_89,mul_temp_25_n_90,\^mul_temp_25 ,mul_temp_25_n_92,mul_temp_25_n_93,mul_temp_25_n_94,mul_temp_25_n_95,mul_temp_25_n_96,mul_temp_25_n_97,mul_temp_25_n_98,mul_temp_25_n_99,mul_temp_25_n_100,mul_temp_25_n_101,mul_temp_25_n_102,mul_temp_25_n_103,mul_temp_25_n_104,mul_temp_25_n_105}),
.PATTERNBDETECT(NLW_mul_temp_25_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_25_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_25_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_25_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_26
(.A({\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_26_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_26_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_26_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_26_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_26_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_26_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_26_P_UNCONNECTED[47:32],mul_temp_26_n_74,mul_temp_26_n_75,mul_temp_26_n_76,mul_temp_26_n_77,mul_temp_26_n_78,mul_temp_26_n_79,mul_temp_26_n_80,mul_temp_26_n_81,mul_temp_26_n_82,mul_temp_26_n_83,mul_temp_26_n_84,mul_temp_26_n_85,mul_temp_26_n_86,mul_temp_26_n_87,mul_temp_26_n_88,mul_temp_26_n_89,mul_temp_26_n_90,\^mul_temp_26 ,mul_temp_26_n_92,mul_temp_26_n_93,mul_temp_26_n_94,mul_temp_26_n_95,mul_temp_26_n_96,mul_temp_26_n_97,mul_temp_26_n_98,mul_temp_26_n_99,mul_temp_26_n_100,mul_temp_26_n_101,mul_temp_26_n_102,mul_temp_26_n_103,mul_temp_26_n_104,mul_temp_26_n_105}),
.PATTERNBDETECT(NLW_mul_temp_26_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_26_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_26_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_26_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_27
(.A({\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] [15],\data_pipeline_tmp_reg[10] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_27_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_27_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_27_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_27_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_27_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_27_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_27_P_UNCONNECTED[47:32],mul_temp_27_n_74,mul_temp_27_n_75,mul_temp_27_n_76,mul_temp_27_n_77,mul_temp_27_n_78,mul_temp_27_n_79,mul_temp_27_n_80,mul_temp_27_n_81,mul_temp_27_n_82,mul_temp_27_n_83,mul_temp_27_n_84,mul_temp_27_n_85,mul_temp_27_n_86,mul_temp_27_n_87,mul_temp_27_n_88,mul_temp_27_n_89,mul_temp_27_n_90,\^mul_temp_27 ,mul_temp_27_n_92,mul_temp_27_n_93,mul_temp_27_n_94,mul_temp_27_n_95,mul_temp_27_n_96,mul_temp_27_n_97,mul_temp_27_n_98,mul_temp_27_n_99,mul_temp_27_n_100,mul_temp_27_n_101,mul_temp_27_n_102,mul_temp_27_n_103,mul_temp_27_n_104,mul_temp_27_n_105}),
.PATTERNBDETECT(NLW_mul_temp_27_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_27_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_27_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_27_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_28
(.A({\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] [15],\data_pipeline_tmp_reg[11] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_28_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_28_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_28_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_28_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_28_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_28_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_28_P_UNCONNECTED[47:32],mul_temp_28_n_74,mul_temp_28_n_75,mul_temp_28_n_76,mul_temp_28_n_77,mul_temp_28_n_78,mul_temp_28_n_79,mul_temp_28_n_80,mul_temp_28_n_81,mul_temp_28_n_82,mul_temp_28_n_83,mul_temp_28_n_84,mul_temp_28_n_85,mul_temp_28_n_86,mul_temp_28_n_87,mul_temp_28_n_88,mul_temp_28_n_89,mul_temp_28_n_90,\^mul_temp_28 ,mul_temp_28_n_92,mul_temp_28_n_93,mul_temp_28_n_94,mul_temp_28_n_95,mul_temp_28_n_96,mul_temp_28_n_97,mul_temp_28_n_98,mul_temp_28_n_99,mul_temp_28_n_100,mul_temp_28_n_101,mul_temp_28_n_102,mul_temp_28_n_103,mul_temp_28_n_104,mul_temp_28_n_105}),
.PATTERNBDETECT(NLW_mul_temp_28_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_28_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_28_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_28_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_29
(.A({\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] [15],\data_pipeline_tmp_reg[12] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_29_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_29_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_29_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_29_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_29_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_29_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_29_P_UNCONNECTED[47:32],mul_temp_29_n_74,mul_temp_29_n_75,mul_temp_29_n_76,mul_temp_29_n_77,mul_temp_29_n_78,mul_temp_29_n_79,mul_temp_29_n_80,mul_temp_29_n_81,mul_temp_29_n_82,mul_temp_29_n_83,mul_temp_29_n_84,mul_temp_29_n_85,mul_temp_29_n_86,mul_temp_29_n_87,mul_temp_29_n_88,mul_temp_29_n_89,mul_temp_29_n_90,\^mul_temp_29 ,mul_temp_29_n_92,mul_temp_29_n_93,mul_temp_29_n_94,mul_temp_29_n_95,mul_temp_29_n_96,mul_temp_29_n_97,mul_temp_29_n_98,mul_temp_29_n_99,mul_temp_29_n_100,mul_temp_29_n_101,mul_temp_29_n_102,mul_temp_29_n_103,mul_temp_29_n_104,mul_temp_29_n_105}),
.PATTERNBDETECT(NLW_mul_temp_29_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_29_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_29_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_29_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_3
(.A({\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] [15],\data_pipeline_tmp_reg[3] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_3_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[3]_2 [15],\weight_reg[3]_2 [15],\weight_reg[3]_2 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_3_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_3_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_3_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_3_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_3_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_3_P_UNCONNECTED[47:32],mul_temp_3_n_74,mul_temp_3_n_75,mul_temp_3_n_76,mul_temp_3_n_77,mul_temp_3_n_78,mul_temp_3_n_79,mul_temp_3_n_80,mul_temp_3_n_81,mul_temp_3_n_82,mul_temp_3_n_83,mul_temp_3_n_84,mul_temp_3_n_85,mul_temp_3_n_86,mul_temp_3_n_87,mul_temp_3_n_88,mul_temp_3_n_89,mul_temp_3_n_90,\^mul_temp_3 ,mul_temp_3_n_92,mul_temp_3_n_93,mul_temp_3_n_94,mul_temp_3_n_95,mul_temp_3_n_96,mul_temp_3_n_97,mul_temp_3_n_98,mul_temp_3_n_99,mul_temp_3_n_100,mul_temp_3_n_101,mul_temp_3_n_102,mul_temp_3_n_103,mul_temp_3_n_104,mul_temp_3_n_105}),
.PATTERNBDETECT(NLW_mul_temp_3_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_3_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_3_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_3_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_30
(.A({\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] [15],\data_pipeline_tmp_reg[13] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_30_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_30_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_30_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_30_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_30_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_30_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_30_P_UNCONNECTED[47:32],mul_temp_30_n_74,mul_temp_30_n_75,mul_temp_30_n_76,mul_temp_30_n_77,mul_temp_30_n_78,mul_temp_30_n_79,mul_temp_30_n_80,mul_temp_30_n_81,mul_temp_30_n_82,mul_temp_30_n_83,mul_temp_30_n_84,mul_temp_30_n_85,mul_temp_30_n_86,mul_temp_30_n_87,mul_temp_30_n_88,mul_temp_30_n_89,mul_temp_30_n_90,\^mul_temp_30 ,mul_temp_30_n_92,mul_temp_30_n_93,mul_temp_30_n_94,mul_temp_30_n_95,mul_temp_30_n_96,mul_temp_30_n_97,mul_temp_30_n_98,mul_temp_30_n_99,mul_temp_30_n_100,mul_temp_30_n_101,mul_temp_30_n_102,mul_temp_30_n_103,mul_temp_30_n_104,mul_temp_30_n_105}),
.PATTERNBDETECT(NLW_mul_temp_30_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_30_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_30_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_30_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_31
(.A({\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] [15],\data_pipeline_tmp_reg[14] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_31_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_31_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_31_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_31_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_31_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_31_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_31_P_UNCONNECTED[47:32],mul_temp_31_n_74,mul_temp_31_n_75,mul_temp_31_n_76,mul_temp_31_n_77,mul_temp_31_n_78,mul_temp_31_n_79,mul_temp_31_n_80,mul_temp_31_n_81,mul_temp_31_n_82,mul_temp_31_n_83,mul_temp_31_n_84,mul_temp_31_n_85,mul_temp_31_n_86,mul_temp_31_n_87,mul_temp_31_n_88,mul_temp_31_n_89,mul_temp_31_n_90,\^mul_temp_31 ,mul_temp_31_n_92,mul_temp_31_n_93,mul_temp_31_n_94,mul_temp_31_n_95,mul_temp_31_n_96,mul_temp_31_n_97,mul_temp_31_n_98,mul_temp_31_n_99,mul_temp_31_n_100,mul_temp_31_n_101,mul_temp_31_n_102,mul_temp_31_n_103,mul_temp_31_n_104,mul_temp_31_n_105}),
.PATTERNBDETECT(NLW_mul_temp_31_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_31_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_31_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_31_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_32
(.A({\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] [15],\write_reg_x_k_reg[15] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_32_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[32],ARG__31[29:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_32_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_32_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_32_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_32_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_32_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_32_P_UNCONNECTED[47:32],mul_temp_32_n_74,mul_temp_32_n_75,mul_temp_32_n_76,mul_temp_32_n_77,mul_temp_32_n_78,mul_temp_32_n_79,mul_temp_32_n_80,mul_temp_32_n_81,mul_temp_32_n_82,mul_temp_32_n_83,mul_temp_32_n_84,mul_temp_32_n_85,mul_temp_32_n_86,mul_temp_32_n_87,mul_temp_32_n_88,mul_temp_32_n_89,mul_temp_32_n_90,\^mul_temp_32 ,mul_temp_32_n_92,mul_temp_32_n_93,mul_temp_32_n_94,mul_temp_32_n_95,mul_temp_32_n_96,mul_temp_32_n_97,mul_temp_32_n_98,mul_temp_32_n_99,mul_temp_32_n_100,mul_temp_32_n_101,mul_temp_32_n_102,mul_temp_32_n_103,mul_temp_32_n_104,mul_temp_32_n_105}),
.PATTERNBDETECT(NLW_mul_temp_32_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_32_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_32_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_32_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_4
(.A({\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] [15],\data_pipeline_tmp_reg[4] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_4_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[4]_3 [15],\weight_reg[4]_3 [15],\weight_reg[4]_3 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_4_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_4_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_4_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_4_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_4_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_4_P_UNCONNECTED[47:32],mul_temp_4_n_74,mul_temp_4_n_75,mul_temp_4_n_76,mul_temp_4_n_77,mul_temp_4_n_78,mul_temp_4_n_79,mul_temp_4_n_80,mul_temp_4_n_81,mul_temp_4_n_82,mul_temp_4_n_83,mul_temp_4_n_84,mul_temp_4_n_85,mul_temp_4_n_86,mul_temp_4_n_87,mul_temp_4_n_88,mul_temp_4_n_89,mul_temp_4_n_90,\^mul_temp_4 ,mul_temp_4_n_92,mul_temp_4_n_93,mul_temp_4_n_94,mul_temp_4_n_95,mul_temp_4_n_96,mul_temp_4_n_97,mul_temp_4_n_98,mul_temp_4_n_99,mul_temp_4_n_100,mul_temp_4_n_101,mul_temp_4_n_102,mul_temp_4_n_103,mul_temp_4_n_104,mul_temp_4_n_105}),
.PATTERNBDETECT(NLW_mul_temp_4_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_4_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_4_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_4_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_5
(.A({\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] [15],\data_pipeline_tmp_reg[5] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_5_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[5]_4 [15],\weight_reg[5]_4 [15],\weight_reg[5]_4 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_5_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_5_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_5_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_5_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_5_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_5_P_UNCONNECTED[47:32],mul_temp_5_n_74,mul_temp_5_n_75,mul_temp_5_n_76,mul_temp_5_n_77,mul_temp_5_n_78,mul_temp_5_n_79,mul_temp_5_n_80,mul_temp_5_n_81,mul_temp_5_n_82,mul_temp_5_n_83,mul_temp_5_n_84,mul_temp_5_n_85,mul_temp_5_n_86,mul_temp_5_n_87,mul_temp_5_n_88,mul_temp_5_n_89,mul_temp_5_n_90,\^mul_temp_5 ,mul_temp_5_n_92,mul_temp_5_n_93,mul_temp_5_n_94,mul_temp_5_n_95,mul_temp_5_n_96,mul_temp_5_n_97,mul_temp_5_n_98,mul_temp_5_n_99,mul_temp_5_n_100,mul_temp_5_n_101,mul_temp_5_n_102,mul_temp_5_n_103,mul_temp_5_n_104,mul_temp_5_n_105}),
.PATTERNBDETECT(NLW_mul_temp_5_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_5_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_5_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_5_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_6
(.A({\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] [15],\data_pipeline_tmp_reg[6] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_6_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[6]_5 [15],\weight_reg[6]_5 [15],\weight_reg[6]_5 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_6_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_6_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_6_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_6_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_6_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_6_P_UNCONNECTED[47:32],mul_temp_6_n_74,mul_temp_6_n_75,mul_temp_6_n_76,mul_temp_6_n_77,mul_temp_6_n_78,mul_temp_6_n_79,mul_temp_6_n_80,mul_temp_6_n_81,mul_temp_6_n_82,mul_temp_6_n_83,mul_temp_6_n_84,mul_temp_6_n_85,mul_temp_6_n_86,mul_temp_6_n_87,mul_temp_6_n_88,mul_temp_6_n_89,mul_temp_6_n_90,\^mul_temp_6 ,mul_temp_6_n_92,mul_temp_6_n_93,mul_temp_6_n_94,mul_temp_6_n_95,mul_temp_6_n_96,mul_temp_6_n_97,mul_temp_6_n_98,mul_temp_6_n_99,mul_temp_6_n_100,mul_temp_6_n_101,mul_temp_6_n_102,mul_temp_6_n_103,mul_temp_6_n_104,mul_temp_6_n_105}),
.PATTERNBDETECT(NLW_mul_temp_6_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_6_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_6_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_6_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_7
(.A({\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] [15],\data_pipeline_tmp_reg[7] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_7_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[7]_6 [15],\weight_reg[7]_6 [15],\weight_reg[7]_6 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_7_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_7_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_7_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_7_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_7_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_7_P_UNCONNECTED[47:32],mul_temp_7_n_74,mul_temp_7_n_75,mul_temp_7_n_76,mul_temp_7_n_77,mul_temp_7_n_78,mul_temp_7_n_79,mul_temp_7_n_80,mul_temp_7_n_81,mul_temp_7_n_82,mul_temp_7_n_83,mul_temp_7_n_84,mul_temp_7_n_85,mul_temp_7_n_86,mul_temp_7_n_87,mul_temp_7_n_88,mul_temp_7_n_89,mul_temp_7_n_90,\^mul_temp_7 ,mul_temp_7_n_92,mul_temp_7_n_93,mul_temp_7_n_94,mul_temp_7_n_95,mul_temp_7_n_96,mul_temp_7_n_97,mul_temp_7_n_98,mul_temp_7_n_99,mul_temp_7_n_100,mul_temp_7_n_101,mul_temp_7_n_102,mul_temp_7_n_103,mul_temp_7_n_104,mul_temp_7_n_105}),
.PATTERNBDETECT(NLW_mul_temp_7_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_7_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_7_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_7_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_8
(.A({\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] [15],\data_pipeline_tmp_reg[8] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_8_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[8]_7 [15],\weight_reg[8]_7 [15],\weight_reg[8]_7 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_8_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_8_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_8_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_8_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_8_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_8_P_UNCONNECTED[47:32],mul_temp_8_n_74,mul_temp_8_n_75,mul_temp_8_n_76,mul_temp_8_n_77,mul_temp_8_n_78,mul_temp_8_n_79,mul_temp_8_n_80,mul_temp_8_n_81,mul_temp_8_n_82,mul_temp_8_n_83,mul_temp_8_n_84,mul_temp_8_n_85,mul_temp_8_n_86,mul_temp_8_n_87,mul_temp_8_n_88,mul_temp_8_n_89,mul_temp_8_n_90,\^mul_temp_8 ,mul_temp_8_n_92,mul_temp_8_n_93,mul_temp_8_n_94,mul_temp_8_n_95,mul_temp_8_n_96,mul_temp_8_n_97,mul_temp_8_n_98,mul_temp_8_n_99,mul_temp_8_n_100,mul_temp_8_n_101,mul_temp_8_n_102,mul_temp_8_n_103,mul_temp_8_n_104,mul_temp_8_n_105}),
.PATTERNBDETECT(NLW_mul_temp_8_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_8_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_8_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_8_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
mul_temp_9
(.A({\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] [15],\data_pipeline_tmp_reg[9] }),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_mul_temp_9_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({\weight_reg[9]_8 [15],\weight_reg[9]_8 [15],\weight_reg[9]_8 }),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_mul_temp_9_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_mul_temp_9_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_mul_temp_9_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_mul_temp_9_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_mul_temp_9_OVERFLOW_UNCONNECTED),
.P({NLW_mul_temp_9_P_UNCONNECTED[47:32],mul_temp_9_n_74,mul_temp_9_n_75,mul_temp_9_n_76,mul_temp_9_n_77,mul_temp_9_n_78,mul_temp_9_n_79,mul_temp_9_n_80,mul_temp_9_n_81,mul_temp_9_n_82,mul_temp_9_n_83,mul_temp_9_n_84,mul_temp_9_n_85,mul_temp_9_n_86,mul_temp_9_n_87,mul_temp_9_n_88,mul_temp_9_n_89,mul_temp_9_n_90,\^mul_temp_9 ,mul_temp_9_n_92,mul_temp_9_n_93,mul_temp_9_n_94,mul_temp_9_n_95,mul_temp_9_n_96,mul_temp_9_n_97,mul_temp_9_n_98,mul_temp_9_n_99,mul_temp_9_n_100,mul_temp_9_n_101,mul_temp_9_n_102,mul_temp_9_n_103,mul_temp_9_n_104,mul_temp_9_n_105}),
.PATTERNBDETECT(NLW_mul_temp_9_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_mul_temp_9_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT(NLW_mul_temp_9_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_mul_temp_9_UNDERFLOW_UNCONNECTED));
CARRY4 sub_temp_carry
(.CI(1'b0),
.CO({sub_temp_carry_n_0,sub_temp_carry_n_1,sub_temp_carry_n_2,sub_temp_carry_n_3}),
.CYINIT(1'b1),
.DI(Q[3:0]),
.O(mul_temp_16[3:0]),
.S(\write_reg_d_k_reg[3]_0 ));
CARRY4 sub_temp_carry__0
(.CI(sub_temp_carry_n_0),
.CO({sub_temp_carry__0_n_0,sub_temp_carry__0_n_1,sub_temp_carry__0_n_2,sub_temp_carry__0_n_3}),
.CYINIT(1'b0),
.DI(Q[7:4]),
.O(mul_temp_16[7:4]),
.S(\write_reg_d_k_reg[7] ));
CARRY4 sub_temp_carry__1
(.CI(sub_temp_carry__0_n_0),
.CO({sub_temp_carry__1_n_0,sub_temp_carry__1_n_1,sub_temp_carry__1_n_2,sub_temp_carry__1_n_3}),
.CYINIT(1'b0),
.DI(Q[11:8]),
.O(mul_temp_16[11:8]),
.S(\write_reg_d_k_reg[11] ));
CARRY4 sub_temp_carry__2
(.CI(sub_temp_carry__1_n_0),
.CO({NLW_sub_temp_carry__2_CO_UNCONNECTED[3],sub_temp_carry__2_n_1,sub_temp_carry__2_n_2,sub_temp_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Q[14:12]}),
.O(mul_temp_16[15:12]),
.S(S));
LUT2 #(
.INIT(4'h6))
\weight[0][0]_i_2
(.I0(ARG__29_n_88),
.I1(\weight_reg[0]_15 [3]),
.O(\weight[0][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][0]_i_3
(.I0(ARG__29_n_89),
.I1(\weight_reg[0]_15 [2]),
.O(\weight[0][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][0]_i_4
(.I0(ARG__29_n_90),
.I1(\weight_reg[0]_15 [1]),
.O(\weight[0][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][0]_i_5
(.I0(ARG__29_n_91),
.I1(\weight_reg[0]_15 [0]),
.O(\weight[0][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][12]_i_2
(.I0(ARG__29_n_76),
.I1(\weight_reg[0]_15 [15]),
.O(\weight[0][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][12]_i_3
(.I0(ARG__29_n_77),
.I1(\weight_reg[0]_15 [14]),
.O(\weight[0][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][12]_i_4
(.I0(ARG__29_n_78),
.I1(\weight_reg[0]_15 [13]),
.O(\weight[0][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][12]_i_5
(.I0(ARG__29_n_79),
.I1(\weight_reg[0]_15 [12]),
.O(\weight[0][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][4]_i_2
(.I0(ARG__29_n_84),
.I1(\weight_reg[0]_15 [7]),
.O(\weight[0][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][4]_i_3
(.I0(ARG__29_n_85),
.I1(\weight_reg[0]_15 [6]),
.O(\weight[0][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][4]_i_4
(.I0(ARG__29_n_86),
.I1(\weight_reg[0]_15 [5]),
.O(\weight[0][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][4]_i_5
(.I0(ARG__29_n_87),
.I1(\weight_reg[0]_15 [4]),
.O(\weight[0][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][8]_i_2
(.I0(ARG__29_n_80),
.I1(\weight_reg[0]_15 [11]),
.O(\weight[0][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][8]_i_3
(.I0(ARG__29_n_81),
.I1(\weight_reg[0]_15 [10]),
.O(\weight[0][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][8]_i_4
(.I0(ARG__29_n_82),
.I1(\weight_reg[0]_15 [9]),
.O(\weight[0][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[0][8]_i_5
(.I0(ARG__29_n_83),
.I1(\weight_reg[0]_15 [8]),
.O(\weight[0][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][0]_i_2
(.I0(ARG__17_n_88),
.I1(\weight_reg[10]_9 [3]),
.O(\weight[10][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][0]_i_3
(.I0(ARG__17_n_89),
.I1(\weight_reg[10]_9 [2]),
.O(\weight[10][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][0]_i_4
(.I0(ARG__17_n_90),
.I1(\weight_reg[10]_9 [1]),
.O(\weight[10][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][0]_i_5
(.I0(ARG__17_n_91),
.I1(\weight_reg[10]_9 [0]),
.O(\weight[10][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][12]_i_2
(.I0(ARG__17_n_76),
.I1(\weight_reg[10]_9 [15]),
.O(\weight[10][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][12]_i_3
(.I0(ARG__17_n_77),
.I1(\weight_reg[10]_9 [14]),
.O(\weight[10][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][12]_i_4
(.I0(ARG__17_n_78),
.I1(\weight_reg[10]_9 [13]),
.O(\weight[10][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][12]_i_5
(.I0(ARG__17_n_79),
.I1(\weight_reg[10]_9 [12]),
.O(\weight[10][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][4]_i_2
(.I0(ARG__17_n_84),
.I1(\weight_reg[10]_9 [7]),
.O(\weight[10][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][4]_i_3
(.I0(ARG__17_n_85),
.I1(\weight_reg[10]_9 [6]),
.O(\weight[10][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][4]_i_4
(.I0(ARG__17_n_86),
.I1(\weight_reg[10]_9 [5]),
.O(\weight[10][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][4]_i_5
(.I0(ARG__17_n_87),
.I1(\weight_reg[10]_9 [4]),
.O(\weight[10][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][8]_i_2
(.I0(ARG__17_n_80),
.I1(\weight_reg[10]_9 [11]),
.O(\weight[10][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][8]_i_3
(.I0(ARG__17_n_81),
.I1(\weight_reg[10]_9 [10]),
.O(\weight[10][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][8]_i_4
(.I0(ARG__17_n_82),
.I1(\weight_reg[10]_9 [9]),
.O(\weight[10][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[10][8]_i_5
(.I0(ARG__17_n_83),
.I1(\weight_reg[10]_9 [8]),
.O(\weight[10][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][0]_i_2
(.I0(ARG__19_n_88),
.I1(\weight_reg[11]_10 [3]),
.O(\weight[11][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][0]_i_3
(.I0(ARG__19_n_89),
.I1(\weight_reg[11]_10 [2]),
.O(\weight[11][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][0]_i_4
(.I0(ARG__19_n_90),
.I1(\weight_reg[11]_10 [1]),
.O(\weight[11][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][0]_i_5
(.I0(ARG__19_n_91),
.I1(\weight_reg[11]_10 [0]),
.O(\weight[11][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][12]_i_2
(.I0(ARG__19_n_76),
.I1(\weight_reg[11]_10 [15]),
.O(\weight[11][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][12]_i_3
(.I0(ARG__19_n_77),
.I1(\weight_reg[11]_10 [14]),
.O(\weight[11][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][12]_i_4
(.I0(ARG__19_n_78),
.I1(\weight_reg[11]_10 [13]),
.O(\weight[11][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][12]_i_5
(.I0(ARG__19_n_79),
.I1(\weight_reg[11]_10 [12]),
.O(\weight[11][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][4]_i_2
(.I0(ARG__19_n_84),
.I1(\weight_reg[11]_10 [7]),
.O(\weight[11][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][4]_i_3
(.I0(ARG__19_n_85),
.I1(\weight_reg[11]_10 [6]),
.O(\weight[11][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][4]_i_4
(.I0(ARG__19_n_86),
.I1(\weight_reg[11]_10 [5]),
.O(\weight[11][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][4]_i_5
(.I0(ARG__19_n_87),
.I1(\weight_reg[11]_10 [4]),
.O(\weight[11][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][8]_i_2
(.I0(ARG__19_n_80),
.I1(\weight_reg[11]_10 [11]),
.O(\weight[11][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][8]_i_3
(.I0(ARG__19_n_81),
.I1(\weight_reg[11]_10 [10]),
.O(\weight[11][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][8]_i_4
(.I0(ARG__19_n_82),
.I1(\weight_reg[11]_10 [9]),
.O(\weight[11][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[11][8]_i_5
(.I0(ARG__19_n_83),
.I1(\weight_reg[11]_10 [8]),
.O(\weight[11][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][0]_i_2
(.I0(ARG__21_n_88),
.I1(\weight_reg[12]_11 [3]),
.O(\weight[12][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][0]_i_3
(.I0(ARG__21_n_89),
.I1(\weight_reg[12]_11 [2]),
.O(\weight[12][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][0]_i_4
(.I0(ARG__21_n_90),
.I1(\weight_reg[12]_11 [1]),
.O(\weight[12][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][0]_i_5
(.I0(ARG__21_n_91),
.I1(\weight_reg[12]_11 [0]),
.O(\weight[12][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][12]_i_2
(.I0(ARG__21_n_76),
.I1(\weight_reg[12]_11 [15]),
.O(\weight[12][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][12]_i_3
(.I0(ARG__21_n_77),
.I1(\weight_reg[12]_11 [14]),
.O(\weight[12][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][12]_i_4
(.I0(ARG__21_n_78),
.I1(\weight_reg[12]_11 [13]),
.O(\weight[12][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][12]_i_5
(.I0(ARG__21_n_79),
.I1(\weight_reg[12]_11 [12]),
.O(\weight[12][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][4]_i_2
(.I0(ARG__21_n_84),
.I1(\weight_reg[12]_11 [7]),
.O(\weight[12][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][4]_i_3
(.I0(ARG__21_n_85),
.I1(\weight_reg[12]_11 [6]),
.O(\weight[12][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][4]_i_4
(.I0(ARG__21_n_86),
.I1(\weight_reg[12]_11 [5]),
.O(\weight[12][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][4]_i_5
(.I0(ARG__21_n_87),
.I1(\weight_reg[12]_11 [4]),
.O(\weight[12][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][8]_i_2
(.I0(ARG__21_n_80),
.I1(\weight_reg[12]_11 [11]),
.O(\weight[12][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][8]_i_3
(.I0(ARG__21_n_81),
.I1(\weight_reg[12]_11 [10]),
.O(\weight[12][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][8]_i_4
(.I0(ARG__21_n_82),
.I1(\weight_reg[12]_11 [9]),
.O(\weight[12][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[12][8]_i_5
(.I0(ARG__21_n_83),
.I1(\weight_reg[12]_11 [8]),
.O(\weight[12][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][0]_i_2
(.I0(ARG__23_n_88),
.I1(\weight_reg[13]_12 [3]),
.O(\weight[13][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][0]_i_3
(.I0(ARG__23_n_89),
.I1(\weight_reg[13]_12 [2]),
.O(\weight[13][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][0]_i_4
(.I0(ARG__23_n_90),
.I1(\weight_reg[13]_12 [1]),
.O(\weight[13][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][0]_i_5
(.I0(ARG__23_n_91),
.I1(\weight_reg[13]_12 [0]),
.O(\weight[13][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][12]_i_2
(.I0(ARG__23_n_76),
.I1(\weight_reg[13]_12 [15]),
.O(\weight[13][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][12]_i_3
(.I0(ARG__23_n_77),
.I1(\weight_reg[13]_12 [14]),
.O(\weight[13][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][12]_i_4
(.I0(ARG__23_n_78),
.I1(\weight_reg[13]_12 [13]),
.O(\weight[13][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][12]_i_5
(.I0(ARG__23_n_79),
.I1(\weight_reg[13]_12 [12]),
.O(\weight[13][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][4]_i_2
(.I0(ARG__23_n_84),
.I1(\weight_reg[13]_12 [7]),
.O(\weight[13][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][4]_i_3
(.I0(ARG__23_n_85),
.I1(\weight_reg[13]_12 [6]),
.O(\weight[13][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][4]_i_4
(.I0(ARG__23_n_86),
.I1(\weight_reg[13]_12 [5]),
.O(\weight[13][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][4]_i_5
(.I0(ARG__23_n_87),
.I1(\weight_reg[13]_12 [4]),
.O(\weight[13][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][8]_i_2
(.I0(ARG__23_n_80),
.I1(\weight_reg[13]_12 [11]),
.O(\weight[13][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][8]_i_3
(.I0(ARG__23_n_81),
.I1(\weight_reg[13]_12 [10]),
.O(\weight[13][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][8]_i_4
(.I0(ARG__23_n_82),
.I1(\weight_reg[13]_12 [9]),
.O(\weight[13][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[13][8]_i_5
(.I0(ARG__23_n_83),
.I1(\weight_reg[13]_12 [8]),
.O(\weight[13][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][0]_i_2
(.I0(ARG__25_n_88),
.I1(\weight_reg[14]_13 [3]),
.O(\weight[14][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][0]_i_3
(.I0(ARG__25_n_89),
.I1(\weight_reg[14]_13 [2]),
.O(\weight[14][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][0]_i_4
(.I0(ARG__25_n_90),
.I1(\weight_reg[14]_13 [1]),
.O(\weight[14][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][0]_i_5
(.I0(ARG__25_n_91),
.I1(\weight_reg[14]_13 [0]),
.O(\weight[14][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][12]_i_2
(.I0(ARG__25_n_76),
.I1(\weight_reg[14]_13 [15]),
.O(\weight[14][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][12]_i_3
(.I0(ARG__25_n_77),
.I1(\weight_reg[14]_13 [14]),
.O(\weight[14][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][12]_i_4
(.I0(ARG__25_n_78),
.I1(\weight_reg[14]_13 [13]),
.O(\weight[14][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][12]_i_5
(.I0(ARG__25_n_79),
.I1(\weight_reg[14]_13 [12]),
.O(\weight[14][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][4]_i_2
(.I0(ARG__25_n_84),
.I1(\weight_reg[14]_13 [7]),
.O(\weight[14][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][4]_i_3
(.I0(ARG__25_n_85),
.I1(\weight_reg[14]_13 [6]),
.O(\weight[14][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][4]_i_4
(.I0(ARG__25_n_86),
.I1(\weight_reg[14]_13 [5]),
.O(\weight[14][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][4]_i_5
(.I0(ARG__25_n_87),
.I1(\weight_reg[14]_13 [4]),
.O(\weight[14][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][8]_i_2
(.I0(ARG__25_n_80),
.I1(\weight_reg[14]_13 [11]),
.O(\weight[14][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][8]_i_3
(.I0(ARG__25_n_81),
.I1(\weight_reg[14]_13 [10]),
.O(\weight[14][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][8]_i_4
(.I0(ARG__25_n_82),
.I1(\weight_reg[14]_13 [9]),
.O(\weight[14][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[14][8]_i_5
(.I0(ARG__25_n_83),
.I1(\weight_reg[14]_13 [8]),
.O(\weight[14][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][0]_i_2
(.I0(ARG__27_n_88),
.I1(\weight_reg[15]_14 [3]),
.O(\weight[15][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][0]_i_3
(.I0(ARG__27_n_89),
.I1(\weight_reg[15]_14 [2]),
.O(\weight[15][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][0]_i_4
(.I0(ARG__27_n_90),
.I1(\weight_reg[15]_14 [1]),
.O(\weight[15][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][0]_i_5
(.I0(ARG__27_n_91),
.I1(\weight_reg[15]_14 [0]),
.O(\weight[15][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][12]_i_2
(.I0(ARG__27_n_76),
.I1(\weight_reg[15]_14 [15]),
.O(\weight[15][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][12]_i_3
(.I0(ARG__27_n_77),
.I1(\weight_reg[15]_14 [14]),
.O(\weight[15][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][12]_i_4
(.I0(ARG__27_n_78),
.I1(\weight_reg[15]_14 [13]),
.O(\weight[15][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][12]_i_5
(.I0(ARG__27_n_79),
.I1(\weight_reg[15]_14 [12]),
.O(\weight[15][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][4]_i_2
(.I0(ARG__27_n_84),
.I1(\weight_reg[15]_14 [7]),
.O(\weight[15][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][4]_i_3
(.I0(ARG__27_n_85),
.I1(\weight_reg[15]_14 [6]),
.O(\weight[15][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][4]_i_4
(.I0(ARG__27_n_86),
.I1(\weight_reg[15]_14 [5]),
.O(\weight[15][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][4]_i_5
(.I0(ARG__27_n_87),
.I1(\weight_reg[15]_14 [4]),
.O(\weight[15][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][8]_i_2
(.I0(ARG__27_n_80),
.I1(\weight_reg[15]_14 [11]),
.O(\weight[15][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][8]_i_3
(.I0(ARG__27_n_81),
.I1(\weight_reg[15]_14 [10]),
.O(\weight[15][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][8]_i_4
(.I0(ARG__27_n_82),
.I1(\weight_reg[15]_14 [9]),
.O(\weight[15][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[15][8]_i_5
(.I0(ARG__27_n_83),
.I1(\weight_reg[15]_14 [8]),
.O(\weight[15][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][0]_i_2
(.I0(in[3]),
.I1(\weight_reg[1]_0 [3]),
.O(\weight[1][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][0]_i_3
(.I0(in[2]),
.I1(\weight_reg[1]_0 [2]),
.O(\weight[1][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][0]_i_4
(.I0(in[1]),
.I1(\weight_reg[1]_0 [1]),
.O(\weight[1][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][0]_i_5
(.I0(in[0]),
.I1(\weight_reg[1]_0 [0]),
.O(\weight[1][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][12]_i_2
(.I0(in[15]),
.I1(\weight_reg[1]_0 [15]),
.O(\weight[1][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][12]_i_3
(.I0(in[14]),
.I1(\weight_reg[1]_0 [14]),
.O(\weight[1][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][12]_i_4
(.I0(in[13]),
.I1(\weight_reg[1]_0 [13]),
.O(\weight[1][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][12]_i_5
(.I0(in[12]),
.I1(\weight_reg[1]_0 [12]),
.O(\weight[1][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][4]_i_2
(.I0(in[7]),
.I1(\weight_reg[1]_0 [7]),
.O(\weight[1][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][4]_i_3
(.I0(in[6]),
.I1(\weight_reg[1]_0 [6]),
.O(\weight[1][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][4]_i_4
(.I0(in[5]),
.I1(\weight_reg[1]_0 [5]),
.O(\weight[1][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][4]_i_5
(.I0(in[4]),
.I1(\weight_reg[1]_0 [4]),
.O(\weight[1][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][8]_i_2
(.I0(in[11]),
.I1(\weight_reg[1]_0 [11]),
.O(\weight[1][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][8]_i_3
(.I0(in[10]),
.I1(\weight_reg[1]_0 [10]),
.O(\weight[1][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][8]_i_4
(.I0(in[9]),
.I1(\weight_reg[1]_0 [9]),
.O(\weight[1][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[1][8]_i_5
(.I0(in[8]),
.I1(\weight_reg[1]_0 [8]),
.O(\weight[1][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][0]_i_2
(.I0(ARG__1_n_88),
.I1(\weight_reg[2]_1 [3]),
.O(\weight[2][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][0]_i_3
(.I0(ARG__1_n_89),
.I1(\weight_reg[2]_1 [2]),
.O(\weight[2][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][0]_i_4
(.I0(ARG__1_n_90),
.I1(\weight_reg[2]_1 [1]),
.O(\weight[2][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][0]_i_5
(.I0(ARG__1_n_91),
.I1(\weight_reg[2]_1 [0]),
.O(\weight[2][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][12]_i_2
(.I0(ARG__1_n_76),
.I1(\weight_reg[2]_1 [15]),
.O(\weight[2][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][12]_i_3
(.I0(ARG__1_n_77),
.I1(\weight_reg[2]_1 [14]),
.O(\weight[2][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][12]_i_4
(.I0(ARG__1_n_78),
.I1(\weight_reg[2]_1 [13]),
.O(\weight[2][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][12]_i_5
(.I0(ARG__1_n_79),
.I1(\weight_reg[2]_1 [12]),
.O(\weight[2][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][4]_i_2
(.I0(ARG__1_n_84),
.I1(\weight_reg[2]_1 [7]),
.O(\weight[2][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][4]_i_3
(.I0(ARG__1_n_85),
.I1(\weight_reg[2]_1 [6]),
.O(\weight[2][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][4]_i_4
(.I0(ARG__1_n_86),
.I1(\weight_reg[2]_1 [5]),
.O(\weight[2][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][4]_i_5
(.I0(ARG__1_n_87),
.I1(\weight_reg[2]_1 [4]),
.O(\weight[2][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][8]_i_2
(.I0(ARG__1_n_80),
.I1(\weight_reg[2]_1 [11]),
.O(\weight[2][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][8]_i_3
(.I0(ARG__1_n_81),
.I1(\weight_reg[2]_1 [10]),
.O(\weight[2][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][8]_i_4
(.I0(ARG__1_n_82),
.I1(\weight_reg[2]_1 [9]),
.O(\weight[2][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[2][8]_i_5
(.I0(ARG__1_n_83),
.I1(\weight_reg[2]_1 [8]),
.O(\weight[2][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][0]_i_2
(.I0(ARG__3_n_88),
.I1(\weight_reg[3]_2 [3]),
.O(\weight[3][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][0]_i_3
(.I0(ARG__3_n_89),
.I1(\weight_reg[3]_2 [2]),
.O(\weight[3][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][0]_i_4
(.I0(ARG__3_n_90),
.I1(\weight_reg[3]_2 [1]),
.O(\weight[3][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][0]_i_5
(.I0(ARG__3_n_91),
.I1(\weight_reg[3]_2 [0]),
.O(\weight[3][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][12]_i_2
(.I0(ARG__3_n_76),
.I1(\weight_reg[3]_2 [15]),
.O(\weight[3][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][12]_i_3
(.I0(ARG__3_n_77),
.I1(\weight_reg[3]_2 [14]),
.O(\weight[3][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][12]_i_4
(.I0(ARG__3_n_78),
.I1(\weight_reg[3]_2 [13]),
.O(\weight[3][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][12]_i_5
(.I0(ARG__3_n_79),
.I1(\weight_reg[3]_2 [12]),
.O(\weight[3][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][4]_i_2
(.I0(ARG__3_n_84),
.I1(\weight_reg[3]_2 [7]),
.O(\weight[3][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][4]_i_3
(.I0(ARG__3_n_85),
.I1(\weight_reg[3]_2 [6]),
.O(\weight[3][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][4]_i_4
(.I0(ARG__3_n_86),
.I1(\weight_reg[3]_2 [5]),
.O(\weight[3][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][4]_i_5
(.I0(ARG__3_n_87),
.I1(\weight_reg[3]_2 [4]),
.O(\weight[3][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][8]_i_2
(.I0(ARG__3_n_80),
.I1(\weight_reg[3]_2 [11]),
.O(\weight[3][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][8]_i_3
(.I0(ARG__3_n_81),
.I1(\weight_reg[3]_2 [10]),
.O(\weight[3][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][8]_i_4
(.I0(ARG__3_n_82),
.I1(\weight_reg[3]_2 [9]),
.O(\weight[3][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[3][8]_i_5
(.I0(ARG__3_n_83),
.I1(\weight_reg[3]_2 [8]),
.O(\weight[3][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][0]_i_2
(.I0(ARG__5_n_88),
.I1(\weight_reg[4]_3 [3]),
.O(\weight[4][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][0]_i_3
(.I0(ARG__5_n_89),
.I1(\weight_reg[4]_3 [2]),
.O(\weight[4][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][0]_i_4
(.I0(ARG__5_n_90),
.I1(\weight_reg[4]_3 [1]),
.O(\weight[4][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][0]_i_5
(.I0(ARG__5_n_91),
.I1(\weight_reg[4]_3 [0]),
.O(\weight[4][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][12]_i_2
(.I0(ARG__5_n_76),
.I1(\weight_reg[4]_3 [15]),
.O(\weight[4][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][12]_i_3
(.I0(ARG__5_n_77),
.I1(\weight_reg[4]_3 [14]),
.O(\weight[4][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][12]_i_4
(.I0(ARG__5_n_78),
.I1(\weight_reg[4]_3 [13]),
.O(\weight[4][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][12]_i_5
(.I0(ARG__5_n_79),
.I1(\weight_reg[4]_3 [12]),
.O(\weight[4][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][4]_i_2
(.I0(ARG__5_n_84),
.I1(\weight_reg[4]_3 [7]),
.O(\weight[4][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][4]_i_3
(.I0(ARG__5_n_85),
.I1(\weight_reg[4]_3 [6]),
.O(\weight[4][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][4]_i_4
(.I0(ARG__5_n_86),
.I1(\weight_reg[4]_3 [5]),
.O(\weight[4][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][4]_i_5
(.I0(ARG__5_n_87),
.I1(\weight_reg[4]_3 [4]),
.O(\weight[4][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][8]_i_2
(.I0(ARG__5_n_80),
.I1(\weight_reg[4]_3 [11]),
.O(\weight[4][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][8]_i_3
(.I0(ARG__5_n_81),
.I1(\weight_reg[4]_3 [10]),
.O(\weight[4][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][8]_i_4
(.I0(ARG__5_n_82),
.I1(\weight_reg[4]_3 [9]),
.O(\weight[4][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[4][8]_i_5
(.I0(ARG__5_n_83),
.I1(\weight_reg[4]_3 [8]),
.O(\weight[4][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][0]_i_2
(.I0(ARG__7_n_88),
.I1(\weight_reg[5]_4 [3]),
.O(\weight[5][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][0]_i_3
(.I0(ARG__7_n_89),
.I1(\weight_reg[5]_4 [2]),
.O(\weight[5][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][0]_i_4
(.I0(ARG__7_n_90),
.I1(\weight_reg[5]_4 [1]),
.O(\weight[5][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][0]_i_5
(.I0(ARG__7_n_91),
.I1(\weight_reg[5]_4 [0]),
.O(\weight[5][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][12]_i_2
(.I0(ARG__7_n_76),
.I1(\weight_reg[5]_4 [15]),
.O(\weight[5][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][12]_i_3
(.I0(ARG__7_n_77),
.I1(\weight_reg[5]_4 [14]),
.O(\weight[5][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][12]_i_4
(.I0(ARG__7_n_78),
.I1(\weight_reg[5]_4 [13]),
.O(\weight[5][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][12]_i_5
(.I0(ARG__7_n_79),
.I1(\weight_reg[5]_4 [12]),
.O(\weight[5][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][4]_i_2
(.I0(ARG__7_n_84),
.I1(\weight_reg[5]_4 [7]),
.O(\weight[5][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][4]_i_3
(.I0(ARG__7_n_85),
.I1(\weight_reg[5]_4 [6]),
.O(\weight[5][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][4]_i_4
(.I0(ARG__7_n_86),
.I1(\weight_reg[5]_4 [5]),
.O(\weight[5][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][4]_i_5
(.I0(ARG__7_n_87),
.I1(\weight_reg[5]_4 [4]),
.O(\weight[5][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][8]_i_2
(.I0(ARG__7_n_80),
.I1(\weight_reg[5]_4 [11]),
.O(\weight[5][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][8]_i_3
(.I0(ARG__7_n_81),
.I1(\weight_reg[5]_4 [10]),
.O(\weight[5][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][8]_i_4
(.I0(ARG__7_n_82),
.I1(\weight_reg[5]_4 [9]),
.O(\weight[5][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[5][8]_i_5
(.I0(ARG__7_n_83),
.I1(\weight_reg[5]_4 [8]),
.O(\weight[5][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][0]_i_2
(.I0(ARG__9_n_88),
.I1(\weight_reg[6]_5 [3]),
.O(\weight[6][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][0]_i_3
(.I0(ARG__9_n_89),
.I1(\weight_reg[6]_5 [2]),
.O(\weight[6][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][0]_i_4
(.I0(ARG__9_n_90),
.I1(\weight_reg[6]_5 [1]),
.O(\weight[6][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][0]_i_5
(.I0(ARG__9_n_91),
.I1(\weight_reg[6]_5 [0]),
.O(\weight[6][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][12]_i_2
(.I0(ARG__9_n_76),
.I1(\weight_reg[6]_5 [15]),
.O(\weight[6][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][12]_i_3
(.I0(ARG__9_n_77),
.I1(\weight_reg[6]_5 [14]),
.O(\weight[6][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][12]_i_4
(.I0(ARG__9_n_78),
.I1(\weight_reg[6]_5 [13]),
.O(\weight[6][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][12]_i_5
(.I0(ARG__9_n_79),
.I1(\weight_reg[6]_5 [12]),
.O(\weight[6][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][4]_i_2
(.I0(ARG__9_n_84),
.I1(\weight_reg[6]_5 [7]),
.O(\weight[6][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][4]_i_3
(.I0(ARG__9_n_85),
.I1(\weight_reg[6]_5 [6]),
.O(\weight[6][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][4]_i_4
(.I0(ARG__9_n_86),
.I1(\weight_reg[6]_5 [5]),
.O(\weight[6][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][4]_i_5
(.I0(ARG__9_n_87),
.I1(\weight_reg[6]_5 [4]),
.O(\weight[6][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][8]_i_2
(.I0(ARG__9_n_80),
.I1(\weight_reg[6]_5 [11]),
.O(\weight[6][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][8]_i_3
(.I0(ARG__9_n_81),
.I1(\weight_reg[6]_5 [10]),
.O(\weight[6][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][8]_i_4
(.I0(ARG__9_n_82),
.I1(\weight_reg[6]_5 [9]),
.O(\weight[6][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[6][8]_i_5
(.I0(ARG__9_n_83),
.I1(\weight_reg[6]_5 [8]),
.O(\weight[6][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][0]_i_2
(.I0(ARG__11_n_88),
.I1(\weight_reg[7]_6 [3]),
.O(\weight[7][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][0]_i_3
(.I0(ARG__11_n_89),
.I1(\weight_reg[7]_6 [2]),
.O(\weight[7][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][0]_i_4
(.I0(ARG__11_n_90),
.I1(\weight_reg[7]_6 [1]),
.O(\weight[7][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][0]_i_5
(.I0(ARG__11_n_91),
.I1(\weight_reg[7]_6 [0]),
.O(\weight[7][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][12]_i_2
(.I0(ARG__11_n_76),
.I1(\weight_reg[7]_6 [15]),
.O(\weight[7][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][12]_i_3
(.I0(ARG__11_n_77),
.I1(\weight_reg[7]_6 [14]),
.O(\weight[7][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][12]_i_4
(.I0(ARG__11_n_78),
.I1(\weight_reg[7]_6 [13]),
.O(\weight[7][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][12]_i_5
(.I0(ARG__11_n_79),
.I1(\weight_reg[7]_6 [12]),
.O(\weight[7][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][4]_i_2
(.I0(ARG__11_n_84),
.I1(\weight_reg[7]_6 [7]),
.O(\weight[7][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][4]_i_3
(.I0(ARG__11_n_85),
.I1(\weight_reg[7]_6 [6]),
.O(\weight[7][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][4]_i_4
(.I0(ARG__11_n_86),
.I1(\weight_reg[7]_6 [5]),
.O(\weight[7][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][4]_i_5
(.I0(ARG__11_n_87),
.I1(\weight_reg[7]_6 [4]),
.O(\weight[7][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][8]_i_2
(.I0(ARG__11_n_80),
.I1(\weight_reg[7]_6 [11]),
.O(\weight[7][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][8]_i_3
(.I0(ARG__11_n_81),
.I1(\weight_reg[7]_6 [10]),
.O(\weight[7][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][8]_i_4
(.I0(ARG__11_n_82),
.I1(\weight_reg[7]_6 [9]),
.O(\weight[7][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[7][8]_i_5
(.I0(ARG__11_n_83),
.I1(\weight_reg[7]_6 [8]),
.O(\weight[7][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][0]_i_2
(.I0(ARG__13_n_88),
.I1(\weight_reg[8]_7 [3]),
.O(\weight[8][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][0]_i_3
(.I0(ARG__13_n_89),
.I1(\weight_reg[8]_7 [2]),
.O(\weight[8][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][0]_i_4
(.I0(ARG__13_n_90),
.I1(\weight_reg[8]_7 [1]),
.O(\weight[8][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][0]_i_5
(.I0(ARG__13_n_91),
.I1(\weight_reg[8]_7 [0]),
.O(\weight[8][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][12]_i_2
(.I0(ARG__13_n_76),
.I1(\weight_reg[8]_7 [15]),
.O(\weight[8][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][12]_i_3
(.I0(ARG__13_n_77),
.I1(\weight_reg[8]_7 [14]),
.O(\weight[8][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][12]_i_4
(.I0(ARG__13_n_78),
.I1(\weight_reg[8]_7 [13]),
.O(\weight[8][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][12]_i_5
(.I0(ARG__13_n_79),
.I1(\weight_reg[8]_7 [12]),
.O(\weight[8][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][4]_i_2
(.I0(ARG__13_n_84),
.I1(\weight_reg[8]_7 [7]),
.O(\weight[8][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][4]_i_3
(.I0(ARG__13_n_85),
.I1(\weight_reg[8]_7 [6]),
.O(\weight[8][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][4]_i_4
(.I0(ARG__13_n_86),
.I1(\weight_reg[8]_7 [5]),
.O(\weight[8][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][4]_i_5
(.I0(ARG__13_n_87),
.I1(\weight_reg[8]_7 [4]),
.O(\weight[8][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][8]_i_2
(.I0(ARG__13_n_80),
.I1(\weight_reg[8]_7 [11]),
.O(\weight[8][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][8]_i_3
(.I0(ARG__13_n_81),
.I1(\weight_reg[8]_7 [10]),
.O(\weight[8][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][8]_i_4
(.I0(ARG__13_n_82),
.I1(\weight_reg[8]_7 [9]),
.O(\weight[8][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[8][8]_i_5
(.I0(ARG__13_n_83),
.I1(\weight_reg[8]_7 [8]),
.O(\weight[8][8]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][0]_i_2
(.I0(ARG__15_n_88),
.I1(\weight_reg[9]_8 [3]),
.O(\weight[9][0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][0]_i_3
(.I0(ARG__15_n_89),
.I1(\weight_reg[9]_8 [2]),
.O(\weight[9][0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][0]_i_4
(.I0(ARG__15_n_90),
.I1(\weight_reg[9]_8 [1]),
.O(\weight[9][0]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][0]_i_5
(.I0(ARG__15_n_91),
.I1(\weight_reg[9]_8 [0]),
.O(\weight[9][0]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][12]_i_2
(.I0(ARG__15_n_76),
.I1(\weight_reg[9]_8 [15]),
.O(\weight[9][12]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][12]_i_3
(.I0(ARG__15_n_77),
.I1(\weight_reg[9]_8 [14]),
.O(\weight[9][12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][12]_i_4
(.I0(ARG__15_n_78),
.I1(\weight_reg[9]_8 [13]),
.O(\weight[9][12]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][12]_i_5
(.I0(ARG__15_n_79),
.I1(\weight_reg[9]_8 [12]),
.O(\weight[9][12]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][4]_i_2
(.I0(ARG__15_n_84),
.I1(\weight_reg[9]_8 [7]),
.O(\weight[9][4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][4]_i_3
(.I0(ARG__15_n_85),
.I1(\weight_reg[9]_8 [6]),
.O(\weight[9][4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][4]_i_4
(.I0(ARG__15_n_86),
.I1(\weight_reg[9]_8 [5]),
.O(\weight[9][4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][4]_i_5
(.I0(ARG__15_n_87),
.I1(\weight_reg[9]_8 [4]),
.O(\weight[9][4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][8]_i_2
(.I0(ARG__15_n_80),
.I1(\weight_reg[9]_8 [11]),
.O(\weight[9][8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][8]_i_3
(.I0(ARG__15_n_81),
.I1(\weight_reg[9]_8 [10]),
.O(\weight[9][8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][8]_i_4
(.I0(ARG__15_n_82),
.I1(\weight_reg[9]_8 [9]),
.O(\weight[9][8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\weight[9][8]_i_5
(.I0(ARG__15_n_83),
.I1(\weight_reg[9]_8 [8]),
.O(\weight[9][8]_i_5_n_0 ));
FDCE \weight_reg[0][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][0]_i_1_n_7 ),
.Q(\weight_reg[0]_15 [0]));
CARRY4 \weight_reg[0][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[0][0]_i_1_n_0 ,\weight_reg[0][0]_i_1_n_1 ,\weight_reg[0][0]_i_1_n_2 ,\weight_reg[0][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__29_n_88,ARG__29_n_89,ARG__29_n_90,ARG__29_n_91}),
.O({\weight_reg[0][0]_i_1_n_4 ,\weight_reg[0][0]_i_1_n_5 ,\weight_reg[0][0]_i_1_n_6 ,\weight_reg[0][0]_i_1_n_7 }),
.S({\weight[0][0]_i_2_n_0 ,\weight[0][0]_i_3_n_0 ,\weight[0][0]_i_4_n_0 ,\weight[0][0]_i_5_n_0 }));
FDCE \weight_reg[0][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][8]_i_1_n_5 ),
.Q(\weight_reg[0]_15 [10]));
FDCE \weight_reg[0][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][8]_i_1_n_4 ),
.Q(\weight_reg[0]_15 [11]));
FDCE \weight_reg[0][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][12]_i_1_n_7 ),
.Q(\weight_reg[0]_15 [12]));
CARRY4 \weight_reg[0][12]_i_1
(.CI(\weight_reg[0][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[0][12]_i_1_CO_UNCONNECTED [3],\weight_reg[0][12]_i_1_n_1 ,\weight_reg[0][12]_i_1_n_2 ,\weight_reg[0][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__29_n_77,ARG__29_n_78,ARG__29_n_79}),
.O({\weight_reg[0][12]_i_1_n_4 ,\weight_reg[0][12]_i_1_n_5 ,\weight_reg[0][12]_i_1_n_6 ,\weight_reg[0][12]_i_1_n_7 }),
.S({\weight[0][12]_i_2_n_0 ,\weight[0][12]_i_3_n_0 ,\weight[0][12]_i_4_n_0 ,\weight[0][12]_i_5_n_0 }));
FDCE \weight_reg[0][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][12]_i_1_n_6 ),
.Q(\weight_reg[0]_15 [13]));
FDCE \weight_reg[0][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][12]_i_1_n_5 ),
.Q(\weight_reg[0]_15 [14]));
FDCE \weight_reg[0][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][12]_i_1_n_4 ),
.Q(\weight_reg[0]_15 [15]));
FDCE \weight_reg[0][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][0]_i_1_n_6 ),
.Q(\weight_reg[0]_15 [1]));
FDCE \weight_reg[0][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][0]_i_1_n_5 ),
.Q(\weight_reg[0]_15 [2]));
FDCE \weight_reg[0][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][0]_i_1_n_4 ),
.Q(\weight_reg[0]_15 [3]));
FDCE \weight_reg[0][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][4]_i_1_n_7 ),
.Q(\weight_reg[0]_15 [4]));
CARRY4 \weight_reg[0][4]_i_1
(.CI(\weight_reg[0][0]_i_1_n_0 ),
.CO({\weight_reg[0][4]_i_1_n_0 ,\weight_reg[0][4]_i_1_n_1 ,\weight_reg[0][4]_i_1_n_2 ,\weight_reg[0][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__29_n_84,ARG__29_n_85,ARG__29_n_86,ARG__29_n_87}),
.O({\weight_reg[0][4]_i_1_n_4 ,\weight_reg[0][4]_i_1_n_5 ,\weight_reg[0][4]_i_1_n_6 ,\weight_reg[0][4]_i_1_n_7 }),
.S({\weight[0][4]_i_2_n_0 ,\weight[0][4]_i_3_n_0 ,\weight[0][4]_i_4_n_0 ,\weight[0][4]_i_5_n_0 }));
FDCE \weight_reg[0][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][4]_i_1_n_6 ),
.Q(\weight_reg[0]_15 [5]));
FDCE \weight_reg[0][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][4]_i_1_n_5 ),
.Q(\weight_reg[0]_15 [6]));
FDCE \weight_reg[0][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][4]_i_1_n_4 ),
.Q(\weight_reg[0]_15 [7]));
FDCE \weight_reg[0][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][8]_i_1_n_7 ),
.Q(\weight_reg[0]_15 [8]));
CARRY4 \weight_reg[0][8]_i_1
(.CI(\weight_reg[0][4]_i_1_n_0 ),
.CO({\weight_reg[0][8]_i_1_n_0 ,\weight_reg[0][8]_i_1_n_1 ,\weight_reg[0][8]_i_1_n_2 ,\weight_reg[0][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__29_n_80,ARG__29_n_81,ARG__29_n_82,ARG__29_n_83}),
.O({\weight_reg[0][8]_i_1_n_4 ,\weight_reg[0][8]_i_1_n_5 ,\weight_reg[0][8]_i_1_n_6 ,\weight_reg[0][8]_i_1_n_7 }),
.S({\weight[0][8]_i_2_n_0 ,\weight[0][8]_i_3_n_0 ,\weight[0][8]_i_4_n_0 ,\weight[0][8]_i_5_n_0 }));
FDCE \weight_reg[0][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[0][8]_i_1_n_6 ),
.Q(\weight_reg[0]_15 [9]));
FDCE \weight_reg[10][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][0]_i_1_n_7 ),
.Q(\weight_reg[10]_9 [0]));
CARRY4 \weight_reg[10][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[10][0]_i_1_n_0 ,\weight_reg[10][0]_i_1_n_1 ,\weight_reg[10][0]_i_1_n_2 ,\weight_reg[10][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__17_n_88,ARG__17_n_89,ARG__17_n_90,ARG__17_n_91}),
.O({\weight_reg[10][0]_i_1_n_4 ,\weight_reg[10][0]_i_1_n_5 ,\weight_reg[10][0]_i_1_n_6 ,\weight_reg[10][0]_i_1_n_7 }),
.S({\weight[10][0]_i_2_n_0 ,\weight[10][0]_i_3_n_0 ,\weight[10][0]_i_4_n_0 ,\weight[10][0]_i_5_n_0 }));
FDCE \weight_reg[10][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][8]_i_1_n_5 ),
.Q(\weight_reg[10]_9 [10]));
FDCE \weight_reg[10][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][8]_i_1_n_4 ),
.Q(\weight_reg[10]_9 [11]));
FDCE \weight_reg[10][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][12]_i_1_n_7 ),
.Q(\weight_reg[10]_9 [12]));
CARRY4 \weight_reg[10][12]_i_1
(.CI(\weight_reg[10][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[10][12]_i_1_CO_UNCONNECTED [3],\weight_reg[10][12]_i_1_n_1 ,\weight_reg[10][12]_i_1_n_2 ,\weight_reg[10][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__17_n_77,ARG__17_n_78,ARG__17_n_79}),
.O({\weight_reg[10][12]_i_1_n_4 ,\weight_reg[10][12]_i_1_n_5 ,\weight_reg[10][12]_i_1_n_6 ,\weight_reg[10][12]_i_1_n_7 }),
.S({\weight[10][12]_i_2_n_0 ,\weight[10][12]_i_3_n_0 ,\weight[10][12]_i_4_n_0 ,\weight[10][12]_i_5_n_0 }));
FDCE \weight_reg[10][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][12]_i_1_n_6 ),
.Q(\weight_reg[10]_9 [13]));
FDCE \weight_reg[10][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][12]_i_1_n_5 ),
.Q(\weight_reg[10]_9 [14]));
FDCE \weight_reg[10][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][12]_i_1_n_4 ),
.Q(\weight_reg[10]_9 [15]));
FDCE \weight_reg[10][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][0]_i_1_n_6 ),
.Q(\weight_reg[10]_9 [1]));
FDCE \weight_reg[10][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][0]_i_1_n_5 ),
.Q(\weight_reg[10]_9 [2]));
FDCE \weight_reg[10][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][0]_i_1_n_4 ),
.Q(\weight_reg[10]_9 [3]));
FDCE \weight_reg[10][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][4]_i_1_n_7 ),
.Q(\weight_reg[10]_9 [4]));
CARRY4 \weight_reg[10][4]_i_1
(.CI(\weight_reg[10][0]_i_1_n_0 ),
.CO({\weight_reg[10][4]_i_1_n_0 ,\weight_reg[10][4]_i_1_n_1 ,\weight_reg[10][4]_i_1_n_2 ,\weight_reg[10][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__17_n_84,ARG__17_n_85,ARG__17_n_86,ARG__17_n_87}),
.O({\weight_reg[10][4]_i_1_n_4 ,\weight_reg[10][4]_i_1_n_5 ,\weight_reg[10][4]_i_1_n_6 ,\weight_reg[10][4]_i_1_n_7 }),
.S({\weight[10][4]_i_2_n_0 ,\weight[10][4]_i_3_n_0 ,\weight[10][4]_i_4_n_0 ,\weight[10][4]_i_5_n_0 }));
FDCE \weight_reg[10][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][4]_i_1_n_6 ),
.Q(\weight_reg[10]_9 [5]));
FDCE \weight_reg[10][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][4]_i_1_n_5 ),
.Q(\weight_reg[10]_9 [6]));
FDCE \weight_reg[10][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][4]_i_1_n_4 ),
.Q(\weight_reg[10]_9 [7]));
FDCE \weight_reg[10][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][8]_i_1_n_7 ),
.Q(\weight_reg[10]_9 [8]));
CARRY4 \weight_reg[10][8]_i_1
(.CI(\weight_reg[10][4]_i_1_n_0 ),
.CO({\weight_reg[10][8]_i_1_n_0 ,\weight_reg[10][8]_i_1_n_1 ,\weight_reg[10][8]_i_1_n_2 ,\weight_reg[10][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__17_n_80,ARG__17_n_81,ARG__17_n_82,ARG__17_n_83}),
.O({\weight_reg[10][8]_i_1_n_4 ,\weight_reg[10][8]_i_1_n_5 ,\weight_reg[10][8]_i_1_n_6 ,\weight_reg[10][8]_i_1_n_7 }),
.S({\weight[10][8]_i_2_n_0 ,\weight[10][8]_i_3_n_0 ,\weight[10][8]_i_4_n_0 ,\weight[10][8]_i_5_n_0 }));
FDCE \weight_reg[10][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[10][8]_i_1_n_6 ),
.Q(\weight_reg[10]_9 [9]));
FDCE \weight_reg[11][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][0]_i_1_n_7 ),
.Q(\weight_reg[11]_10 [0]));
CARRY4 \weight_reg[11][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[11][0]_i_1_n_0 ,\weight_reg[11][0]_i_1_n_1 ,\weight_reg[11][0]_i_1_n_2 ,\weight_reg[11][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__19_n_88,ARG__19_n_89,ARG__19_n_90,ARG__19_n_91}),
.O({\weight_reg[11][0]_i_1_n_4 ,\weight_reg[11][0]_i_1_n_5 ,\weight_reg[11][0]_i_1_n_6 ,\weight_reg[11][0]_i_1_n_7 }),
.S({\weight[11][0]_i_2_n_0 ,\weight[11][0]_i_3_n_0 ,\weight[11][0]_i_4_n_0 ,\weight[11][0]_i_5_n_0 }));
FDCE \weight_reg[11][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][8]_i_1_n_5 ),
.Q(\weight_reg[11]_10 [10]));
FDCE \weight_reg[11][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][8]_i_1_n_4 ),
.Q(\weight_reg[11]_10 [11]));
FDCE \weight_reg[11][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][12]_i_1_n_7 ),
.Q(\weight_reg[11]_10 [12]));
CARRY4 \weight_reg[11][12]_i_1
(.CI(\weight_reg[11][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[11][12]_i_1_CO_UNCONNECTED [3],\weight_reg[11][12]_i_1_n_1 ,\weight_reg[11][12]_i_1_n_2 ,\weight_reg[11][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__19_n_77,ARG__19_n_78,ARG__19_n_79}),
.O({\weight_reg[11][12]_i_1_n_4 ,\weight_reg[11][12]_i_1_n_5 ,\weight_reg[11][12]_i_1_n_6 ,\weight_reg[11][12]_i_1_n_7 }),
.S({\weight[11][12]_i_2_n_0 ,\weight[11][12]_i_3_n_0 ,\weight[11][12]_i_4_n_0 ,\weight[11][12]_i_5_n_0 }));
FDCE \weight_reg[11][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][12]_i_1_n_6 ),
.Q(\weight_reg[11]_10 [13]));
FDCE \weight_reg[11][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][12]_i_1_n_5 ),
.Q(\weight_reg[11]_10 [14]));
FDCE \weight_reg[11][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][12]_i_1_n_4 ),
.Q(\weight_reg[11]_10 [15]));
FDCE \weight_reg[11][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][0]_i_1_n_6 ),
.Q(\weight_reg[11]_10 [1]));
FDCE \weight_reg[11][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][0]_i_1_n_5 ),
.Q(\weight_reg[11]_10 [2]));
FDCE \weight_reg[11][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][0]_i_1_n_4 ),
.Q(\weight_reg[11]_10 [3]));
FDCE \weight_reg[11][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][4]_i_1_n_7 ),
.Q(\weight_reg[11]_10 [4]));
CARRY4 \weight_reg[11][4]_i_1
(.CI(\weight_reg[11][0]_i_1_n_0 ),
.CO({\weight_reg[11][4]_i_1_n_0 ,\weight_reg[11][4]_i_1_n_1 ,\weight_reg[11][4]_i_1_n_2 ,\weight_reg[11][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__19_n_84,ARG__19_n_85,ARG__19_n_86,ARG__19_n_87}),
.O({\weight_reg[11][4]_i_1_n_4 ,\weight_reg[11][4]_i_1_n_5 ,\weight_reg[11][4]_i_1_n_6 ,\weight_reg[11][4]_i_1_n_7 }),
.S({\weight[11][4]_i_2_n_0 ,\weight[11][4]_i_3_n_0 ,\weight[11][4]_i_4_n_0 ,\weight[11][4]_i_5_n_0 }));
FDCE \weight_reg[11][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][4]_i_1_n_6 ),
.Q(\weight_reg[11]_10 [5]));
FDCE \weight_reg[11][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][4]_i_1_n_5 ),
.Q(\weight_reg[11]_10 [6]));
FDCE \weight_reg[11][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][4]_i_1_n_4 ),
.Q(\weight_reg[11]_10 [7]));
FDCE \weight_reg[11][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][8]_i_1_n_7 ),
.Q(\weight_reg[11]_10 [8]));
CARRY4 \weight_reg[11][8]_i_1
(.CI(\weight_reg[11][4]_i_1_n_0 ),
.CO({\weight_reg[11][8]_i_1_n_0 ,\weight_reg[11][8]_i_1_n_1 ,\weight_reg[11][8]_i_1_n_2 ,\weight_reg[11][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__19_n_80,ARG__19_n_81,ARG__19_n_82,ARG__19_n_83}),
.O({\weight_reg[11][8]_i_1_n_4 ,\weight_reg[11][8]_i_1_n_5 ,\weight_reg[11][8]_i_1_n_6 ,\weight_reg[11][8]_i_1_n_7 }),
.S({\weight[11][8]_i_2_n_0 ,\weight[11][8]_i_3_n_0 ,\weight[11][8]_i_4_n_0 ,\weight[11][8]_i_5_n_0 }));
FDCE \weight_reg[11][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[11][8]_i_1_n_6 ),
.Q(\weight_reg[11]_10 [9]));
FDCE \weight_reg[12][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][0]_i_1_n_7 ),
.Q(\weight_reg[12]_11 [0]));
CARRY4 \weight_reg[12][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[12][0]_i_1_n_0 ,\weight_reg[12][0]_i_1_n_1 ,\weight_reg[12][0]_i_1_n_2 ,\weight_reg[12][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__21_n_88,ARG__21_n_89,ARG__21_n_90,ARG__21_n_91}),
.O({\weight_reg[12][0]_i_1_n_4 ,\weight_reg[12][0]_i_1_n_5 ,\weight_reg[12][0]_i_1_n_6 ,\weight_reg[12][0]_i_1_n_7 }),
.S({\weight[12][0]_i_2_n_0 ,\weight[12][0]_i_3_n_0 ,\weight[12][0]_i_4_n_0 ,\weight[12][0]_i_5_n_0 }));
FDCE \weight_reg[12][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][8]_i_1_n_5 ),
.Q(\weight_reg[12]_11 [10]));
FDCE \weight_reg[12][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][8]_i_1_n_4 ),
.Q(\weight_reg[12]_11 [11]));
FDCE \weight_reg[12][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][12]_i_1_n_7 ),
.Q(\weight_reg[12]_11 [12]));
CARRY4 \weight_reg[12][12]_i_1
(.CI(\weight_reg[12][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[12][12]_i_1_CO_UNCONNECTED [3],\weight_reg[12][12]_i_1_n_1 ,\weight_reg[12][12]_i_1_n_2 ,\weight_reg[12][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__21_n_77,ARG__21_n_78,ARG__21_n_79}),
.O({\weight_reg[12][12]_i_1_n_4 ,\weight_reg[12][12]_i_1_n_5 ,\weight_reg[12][12]_i_1_n_6 ,\weight_reg[12][12]_i_1_n_7 }),
.S({\weight[12][12]_i_2_n_0 ,\weight[12][12]_i_3_n_0 ,\weight[12][12]_i_4_n_0 ,\weight[12][12]_i_5_n_0 }));
FDCE \weight_reg[12][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][12]_i_1_n_6 ),
.Q(\weight_reg[12]_11 [13]));
FDCE \weight_reg[12][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][12]_i_1_n_5 ),
.Q(\weight_reg[12]_11 [14]));
FDCE \weight_reg[12][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][12]_i_1_n_4 ),
.Q(\weight_reg[12]_11 [15]));
FDCE \weight_reg[12][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][0]_i_1_n_6 ),
.Q(\weight_reg[12]_11 [1]));
FDCE \weight_reg[12][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][0]_i_1_n_5 ),
.Q(\weight_reg[12]_11 [2]));
FDCE \weight_reg[12][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][0]_i_1_n_4 ),
.Q(\weight_reg[12]_11 [3]));
FDCE \weight_reg[12][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][4]_i_1_n_7 ),
.Q(\weight_reg[12]_11 [4]));
CARRY4 \weight_reg[12][4]_i_1
(.CI(\weight_reg[12][0]_i_1_n_0 ),
.CO({\weight_reg[12][4]_i_1_n_0 ,\weight_reg[12][4]_i_1_n_1 ,\weight_reg[12][4]_i_1_n_2 ,\weight_reg[12][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__21_n_84,ARG__21_n_85,ARG__21_n_86,ARG__21_n_87}),
.O({\weight_reg[12][4]_i_1_n_4 ,\weight_reg[12][4]_i_1_n_5 ,\weight_reg[12][4]_i_1_n_6 ,\weight_reg[12][4]_i_1_n_7 }),
.S({\weight[12][4]_i_2_n_0 ,\weight[12][4]_i_3_n_0 ,\weight[12][4]_i_4_n_0 ,\weight[12][4]_i_5_n_0 }));
FDCE \weight_reg[12][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][4]_i_1_n_6 ),
.Q(\weight_reg[12]_11 [5]));
FDCE \weight_reg[12][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][4]_i_1_n_5 ),
.Q(\weight_reg[12]_11 [6]));
FDCE \weight_reg[12][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][4]_i_1_n_4 ),
.Q(\weight_reg[12]_11 [7]));
FDCE \weight_reg[12][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][8]_i_1_n_7 ),
.Q(\weight_reg[12]_11 [8]));
CARRY4 \weight_reg[12][8]_i_1
(.CI(\weight_reg[12][4]_i_1_n_0 ),
.CO({\weight_reg[12][8]_i_1_n_0 ,\weight_reg[12][8]_i_1_n_1 ,\weight_reg[12][8]_i_1_n_2 ,\weight_reg[12][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__21_n_80,ARG__21_n_81,ARG__21_n_82,ARG__21_n_83}),
.O({\weight_reg[12][8]_i_1_n_4 ,\weight_reg[12][8]_i_1_n_5 ,\weight_reg[12][8]_i_1_n_6 ,\weight_reg[12][8]_i_1_n_7 }),
.S({\weight[12][8]_i_2_n_0 ,\weight[12][8]_i_3_n_0 ,\weight[12][8]_i_4_n_0 ,\weight[12][8]_i_5_n_0 }));
FDCE \weight_reg[12][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[12][8]_i_1_n_6 ),
.Q(\weight_reg[12]_11 [9]));
FDCE \weight_reg[13][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][0]_i_1_n_7 ),
.Q(\weight_reg[13]_12 [0]));
CARRY4 \weight_reg[13][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[13][0]_i_1_n_0 ,\weight_reg[13][0]_i_1_n_1 ,\weight_reg[13][0]_i_1_n_2 ,\weight_reg[13][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__23_n_88,ARG__23_n_89,ARG__23_n_90,ARG__23_n_91}),
.O({\weight_reg[13][0]_i_1_n_4 ,\weight_reg[13][0]_i_1_n_5 ,\weight_reg[13][0]_i_1_n_6 ,\weight_reg[13][0]_i_1_n_7 }),
.S({\weight[13][0]_i_2_n_0 ,\weight[13][0]_i_3_n_0 ,\weight[13][0]_i_4_n_0 ,\weight[13][0]_i_5_n_0 }));
FDCE \weight_reg[13][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][8]_i_1_n_5 ),
.Q(\weight_reg[13]_12 [10]));
FDCE \weight_reg[13][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][8]_i_1_n_4 ),
.Q(\weight_reg[13]_12 [11]));
FDCE \weight_reg[13][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][12]_i_1_n_7 ),
.Q(\weight_reg[13]_12 [12]));
CARRY4 \weight_reg[13][12]_i_1
(.CI(\weight_reg[13][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[13][12]_i_1_CO_UNCONNECTED [3],\weight_reg[13][12]_i_1_n_1 ,\weight_reg[13][12]_i_1_n_2 ,\weight_reg[13][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__23_n_77,ARG__23_n_78,ARG__23_n_79}),
.O({\weight_reg[13][12]_i_1_n_4 ,\weight_reg[13][12]_i_1_n_5 ,\weight_reg[13][12]_i_1_n_6 ,\weight_reg[13][12]_i_1_n_7 }),
.S({\weight[13][12]_i_2_n_0 ,\weight[13][12]_i_3_n_0 ,\weight[13][12]_i_4_n_0 ,\weight[13][12]_i_5_n_0 }));
FDCE \weight_reg[13][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][12]_i_1_n_6 ),
.Q(\weight_reg[13]_12 [13]));
FDCE \weight_reg[13][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][12]_i_1_n_5 ),
.Q(\weight_reg[13]_12 [14]));
FDCE \weight_reg[13][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][12]_i_1_n_4 ),
.Q(\weight_reg[13]_12 [15]));
FDCE \weight_reg[13][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][0]_i_1_n_6 ),
.Q(\weight_reg[13]_12 [1]));
FDCE \weight_reg[13][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][0]_i_1_n_5 ),
.Q(\weight_reg[13]_12 [2]));
FDCE \weight_reg[13][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][0]_i_1_n_4 ),
.Q(\weight_reg[13]_12 [3]));
FDCE \weight_reg[13][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][4]_i_1_n_7 ),
.Q(\weight_reg[13]_12 [4]));
CARRY4 \weight_reg[13][4]_i_1
(.CI(\weight_reg[13][0]_i_1_n_0 ),
.CO({\weight_reg[13][4]_i_1_n_0 ,\weight_reg[13][4]_i_1_n_1 ,\weight_reg[13][4]_i_1_n_2 ,\weight_reg[13][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__23_n_84,ARG__23_n_85,ARG__23_n_86,ARG__23_n_87}),
.O({\weight_reg[13][4]_i_1_n_4 ,\weight_reg[13][4]_i_1_n_5 ,\weight_reg[13][4]_i_1_n_6 ,\weight_reg[13][4]_i_1_n_7 }),
.S({\weight[13][4]_i_2_n_0 ,\weight[13][4]_i_3_n_0 ,\weight[13][4]_i_4_n_0 ,\weight[13][4]_i_5_n_0 }));
FDCE \weight_reg[13][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][4]_i_1_n_6 ),
.Q(\weight_reg[13]_12 [5]));
FDCE \weight_reg[13][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][4]_i_1_n_5 ),
.Q(\weight_reg[13]_12 [6]));
FDCE \weight_reg[13][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][4]_i_1_n_4 ),
.Q(\weight_reg[13]_12 [7]));
FDCE \weight_reg[13][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][8]_i_1_n_7 ),
.Q(\weight_reg[13]_12 [8]));
CARRY4 \weight_reg[13][8]_i_1
(.CI(\weight_reg[13][4]_i_1_n_0 ),
.CO({\weight_reg[13][8]_i_1_n_0 ,\weight_reg[13][8]_i_1_n_1 ,\weight_reg[13][8]_i_1_n_2 ,\weight_reg[13][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__23_n_80,ARG__23_n_81,ARG__23_n_82,ARG__23_n_83}),
.O({\weight_reg[13][8]_i_1_n_4 ,\weight_reg[13][8]_i_1_n_5 ,\weight_reg[13][8]_i_1_n_6 ,\weight_reg[13][8]_i_1_n_7 }),
.S({\weight[13][8]_i_2_n_0 ,\weight[13][8]_i_3_n_0 ,\weight[13][8]_i_4_n_0 ,\weight[13][8]_i_5_n_0 }));
FDCE \weight_reg[13][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[13][8]_i_1_n_6 ),
.Q(\weight_reg[13]_12 [9]));
FDCE \weight_reg[14][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][0]_i_1_n_7 ),
.Q(\weight_reg[14]_13 [0]));
CARRY4 \weight_reg[14][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[14][0]_i_1_n_0 ,\weight_reg[14][0]_i_1_n_1 ,\weight_reg[14][0]_i_1_n_2 ,\weight_reg[14][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__25_n_88,ARG__25_n_89,ARG__25_n_90,ARG__25_n_91}),
.O({\weight_reg[14][0]_i_1_n_4 ,\weight_reg[14][0]_i_1_n_5 ,\weight_reg[14][0]_i_1_n_6 ,\weight_reg[14][0]_i_1_n_7 }),
.S({\weight[14][0]_i_2_n_0 ,\weight[14][0]_i_3_n_0 ,\weight[14][0]_i_4_n_0 ,\weight[14][0]_i_5_n_0 }));
FDCE \weight_reg[14][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][8]_i_1_n_5 ),
.Q(\weight_reg[14]_13 [10]));
FDCE \weight_reg[14][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][8]_i_1_n_4 ),
.Q(\weight_reg[14]_13 [11]));
FDCE \weight_reg[14][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][12]_i_1_n_7 ),
.Q(\weight_reg[14]_13 [12]));
CARRY4 \weight_reg[14][12]_i_1
(.CI(\weight_reg[14][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[14][12]_i_1_CO_UNCONNECTED [3],\weight_reg[14][12]_i_1_n_1 ,\weight_reg[14][12]_i_1_n_2 ,\weight_reg[14][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__25_n_77,ARG__25_n_78,ARG__25_n_79}),
.O({\weight_reg[14][12]_i_1_n_4 ,\weight_reg[14][12]_i_1_n_5 ,\weight_reg[14][12]_i_1_n_6 ,\weight_reg[14][12]_i_1_n_7 }),
.S({\weight[14][12]_i_2_n_0 ,\weight[14][12]_i_3_n_0 ,\weight[14][12]_i_4_n_0 ,\weight[14][12]_i_5_n_0 }));
FDCE \weight_reg[14][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][12]_i_1_n_6 ),
.Q(\weight_reg[14]_13 [13]));
FDCE \weight_reg[14][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][12]_i_1_n_5 ),
.Q(\weight_reg[14]_13 [14]));
FDCE \weight_reg[14][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][12]_i_1_n_4 ),
.Q(\weight_reg[14]_13 [15]));
FDCE \weight_reg[14][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][0]_i_1_n_6 ),
.Q(\weight_reg[14]_13 [1]));
FDCE \weight_reg[14][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][0]_i_1_n_5 ),
.Q(\weight_reg[14]_13 [2]));
FDCE \weight_reg[14][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][0]_i_1_n_4 ),
.Q(\weight_reg[14]_13 [3]));
FDCE \weight_reg[14][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][4]_i_1_n_7 ),
.Q(\weight_reg[14]_13 [4]));
CARRY4 \weight_reg[14][4]_i_1
(.CI(\weight_reg[14][0]_i_1_n_0 ),
.CO({\weight_reg[14][4]_i_1_n_0 ,\weight_reg[14][4]_i_1_n_1 ,\weight_reg[14][4]_i_1_n_2 ,\weight_reg[14][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__25_n_84,ARG__25_n_85,ARG__25_n_86,ARG__25_n_87}),
.O({\weight_reg[14][4]_i_1_n_4 ,\weight_reg[14][4]_i_1_n_5 ,\weight_reg[14][4]_i_1_n_6 ,\weight_reg[14][4]_i_1_n_7 }),
.S({\weight[14][4]_i_2_n_0 ,\weight[14][4]_i_3_n_0 ,\weight[14][4]_i_4_n_0 ,\weight[14][4]_i_5_n_0 }));
FDCE \weight_reg[14][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][4]_i_1_n_6 ),
.Q(\weight_reg[14]_13 [5]));
FDCE \weight_reg[14][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][4]_i_1_n_5 ),
.Q(\weight_reg[14]_13 [6]));
FDCE \weight_reg[14][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][4]_i_1_n_4 ),
.Q(\weight_reg[14]_13 [7]));
FDCE \weight_reg[14][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][8]_i_1_n_7 ),
.Q(\weight_reg[14]_13 [8]));
CARRY4 \weight_reg[14][8]_i_1
(.CI(\weight_reg[14][4]_i_1_n_0 ),
.CO({\weight_reg[14][8]_i_1_n_0 ,\weight_reg[14][8]_i_1_n_1 ,\weight_reg[14][8]_i_1_n_2 ,\weight_reg[14][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__25_n_80,ARG__25_n_81,ARG__25_n_82,ARG__25_n_83}),
.O({\weight_reg[14][8]_i_1_n_4 ,\weight_reg[14][8]_i_1_n_5 ,\weight_reg[14][8]_i_1_n_6 ,\weight_reg[14][8]_i_1_n_7 }),
.S({\weight[14][8]_i_2_n_0 ,\weight[14][8]_i_3_n_0 ,\weight[14][8]_i_4_n_0 ,\weight[14][8]_i_5_n_0 }));
FDCE \weight_reg[14][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[14][8]_i_1_n_6 ),
.Q(\weight_reg[14]_13 [9]));
FDCE \weight_reg[15][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][0]_i_1_n_7 ),
.Q(\weight_reg[15]_14 [0]));
CARRY4 \weight_reg[15][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[15][0]_i_1_n_0 ,\weight_reg[15][0]_i_1_n_1 ,\weight_reg[15][0]_i_1_n_2 ,\weight_reg[15][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__27_n_88,ARG__27_n_89,ARG__27_n_90,ARG__27_n_91}),
.O({\weight_reg[15][0]_i_1_n_4 ,\weight_reg[15][0]_i_1_n_5 ,\weight_reg[15][0]_i_1_n_6 ,\weight_reg[15][0]_i_1_n_7 }),
.S({\weight[15][0]_i_2_n_0 ,\weight[15][0]_i_3_n_0 ,\weight[15][0]_i_4_n_0 ,\weight[15][0]_i_5_n_0 }));
FDCE \weight_reg[15][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][8]_i_1_n_5 ),
.Q(\weight_reg[15]_14 [10]));
FDCE \weight_reg[15][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][8]_i_1_n_4 ),
.Q(\weight_reg[15]_14 [11]));
FDCE \weight_reg[15][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][12]_i_1_n_7 ),
.Q(\weight_reg[15]_14 [12]));
CARRY4 \weight_reg[15][12]_i_1
(.CI(\weight_reg[15][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[15][12]_i_1_CO_UNCONNECTED [3],\weight_reg[15][12]_i_1_n_1 ,\weight_reg[15][12]_i_1_n_2 ,\weight_reg[15][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__27_n_77,ARG__27_n_78,ARG__27_n_79}),
.O({\weight_reg[15][12]_i_1_n_4 ,\weight_reg[15][12]_i_1_n_5 ,\weight_reg[15][12]_i_1_n_6 ,\weight_reg[15][12]_i_1_n_7 }),
.S({\weight[15][12]_i_2_n_0 ,\weight[15][12]_i_3_n_0 ,\weight[15][12]_i_4_n_0 ,\weight[15][12]_i_5_n_0 }));
FDCE \weight_reg[15][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][12]_i_1_n_6 ),
.Q(\weight_reg[15]_14 [13]));
FDCE \weight_reg[15][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][12]_i_1_n_5 ),
.Q(\weight_reg[15]_14 [14]));
FDCE \weight_reg[15][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][12]_i_1_n_4 ),
.Q(\weight_reg[15]_14 [15]));
FDCE \weight_reg[15][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][0]_i_1_n_6 ),
.Q(\weight_reg[15]_14 [1]));
FDCE \weight_reg[15][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][0]_i_1_n_5 ),
.Q(\weight_reg[15]_14 [2]));
FDCE \weight_reg[15][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][0]_i_1_n_4 ),
.Q(\weight_reg[15]_14 [3]));
FDCE \weight_reg[15][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][4]_i_1_n_7 ),
.Q(\weight_reg[15]_14 [4]));
CARRY4 \weight_reg[15][4]_i_1
(.CI(\weight_reg[15][0]_i_1_n_0 ),
.CO({\weight_reg[15][4]_i_1_n_0 ,\weight_reg[15][4]_i_1_n_1 ,\weight_reg[15][4]_i_1_n_2 ,\weight_reg[15][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__27_n_84,ARG__27_n_85,ARG__27_n_86,ARG__27_n_87}),
.O({\weight_reg[15][4]_i_1_n_4 ,\weight_reg[15][4]_i_1_n_5 ,\weight_reg[15][4]_i_1_n_6 ,\weight_reg[15][4]_i_1_n_7 }),
.S({\weight[15][4]_i_2_n_0 ,\weight[15][4]_i_3_n_0 ,\weight[15][4]_i_4_n_0 ,\weight[15][4]_i_5_n_0 }));
FDCE \weight_reg[15][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][4]_i_1_n_6 ),
.Q(\weight_reg[15]_14 [5]));
FDCE \weight_reg[15][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][4]_i_1_n_5 ),
.Q(\weight_reg[15]_14 [6]));
FDCE \weight_reg[15][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][4]_i_1_n_4 ),
.Q(\weight_reg[15]_14 [7]));
FDCE \weight_reg[15][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][8]_i_1_n_7 ),
.Q(\weight_reg[15]_14 [8]));
CARRY4 \weight_reg[15][8]_i_1
(.CI(\weight_reg[15][4]_i_1_n_0 ),
.CO({\weight_reg[15][8]_i_1_n_0 ,\weight_reg[15][8]_i_1_n_1 ,\weight_reg[15][8]_i_1_n_2 ,\weight_reg[15][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__27_n_80,ARG__27_n_81,ARG__27_n_82,ARG__27_n_83}),
.O({\weight_reg[15][8]_i_1_n_4 ,\weight_reg[15][8]_i_1_n_5 ,\weight_reg[15][8]_i_1_n_6 ,\weight_reg[15][8]_i_1_n_7 }),
.S({\weight[15][8]_i_2_n_0 ,\weight[15][8]_i_3_n_0 ,\weight[15][8]_i_4_n_0 ,\weight[15][8]_i_5_n_0 }));
FDCE \weight_reg[15][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[15][8]_i_1_n_6 ),
.Q(\weight_reg[15]_14 [9]));
FDCE \weight_reg[1][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][0]_i_1_n_7 ),
.Q(\weight_reg[1]_0 [0]));
CARRY4 \weight_reg[1][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[1][0]_i_1_n_0 ,\weight_reg[1][0]_i_1_n_1 ,\weight_reg[1][0]_i_1_n_2 ,\weight_reg[1][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(in[3:0]),
.O({\weight_reg[1][0]_i_1_n_4 ,\weight_reg[1][0]_i_1_n_5 ,\weight_reg[1][0]_i_1_n_6 ,\weight_reg[1][0]_i_1_n_7 }),
.S({\weight[1][0]_i_2_n_0 ,\weight[1][0]_i_3_n_0 ,\weight[1][0]_i_4_n_0 ,\weight[1][0]_i_5_n_0 }));
FDCE \weight_reg[1][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][8]_i_1_n_5 ),
.Q(\weight_reg[1]_0 [10]));
FDCE \weight_reg[1][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][8]_i_1_n_4 ),
.Q(\weight_reg[1]_0 [11]));
FDCE \weight_reg[1][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][12]_i_1_n_7 ),
.Q(\weight_reg[1]_0 [12]));
CARRY4 \weight_reg[1][12]_i_1
(.CI(\weight_reg[1][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[1][12]_i_1_CO_UNCONNECTED [3],\weight_reg[1][12]_i_1_n_1 ,\weight_reg[1][12]_i_1_n_2 ,\weight_reg[1][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,in[14:12]}),
.O({\weight_reg[1][12]_i_1_n_4 ,\weight_reg[1][12]_i_1_n_5 ,\weight_reg[1][12]_i_1_n_6 ,\weight_reg[1][12]_i_1_n_7 }),
.S({\weight[1][12]_i_2_n_0 ,\weight[1][12]_i_3_n_0 ,\weight[1][12]_i_4_n_0 ,\weight[1][12]_i_5_n_0 }));
FDCE \weight_reg[1][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][12]_i_1_n_6 ),
.Q(\weight_reg[1]_0 [13]));
FDCE \weight_reg[1][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][12]_i_1_n_5 ),
.Q(\weight_reg[1]_0 [14]));
FDCE \weight_reg[1][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][12]_i_1_n_4 ),
.Q(\weight_reg[1]_0 [15]));
FDCE \weight_reg[1][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][0]_i_1_n_6 ),
.Q(\weight_reg[1]_0 [1]));
FDCE \weight_reg[1][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][0]_i_1_n_5 ),
.Q(\weight_reg[1]_0 [2]));
FDCE \weight_reg[1][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][0]_i_1_n_4 ),
.Q(\weight_reg[1]_0 [3]));
FDCE \weight_reg[1][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][4]_i_1_n_7 ),
.Q(\weight_reg[1]_0 [4]));
CARRY4 \weight_reg[1][4]_i_1
(.CI(\weight_reg[1][0]_i_1_n_0 ),
.CO({\weight_reg[1][4]_i_1_n_0 ,\weight_reg[1][4]_i_1_n_1 ,\weight_reg[1][4]_i_1_n_2 ,\weight_reg[1][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(in[7:4]),
.O({\weight_reg[1][4]_i_1_n_4 ,\weight_reg[1][4]_i_1_n_5 ,\weight_reg[1][4]_i_1_n_6 ,\weight_reg[1][4]_i_1_n_7 }),
.S({\weight[1][4]_i_2_n_0 ,\weight[1][4]_i_3_n_0 ,\weight[1][4]_i_4_n_0 ,\weight[1][4]_i_5_n_0 }));
FDCE \weight_reg[1][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][4]_i_1_n_6 ),
.Q(\weight_reg[1]_0 [5]));
FDCE \weight_reg[1][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][4]_i_1_n_5 ),
.Q(\weight_reg[1]_0 [6]));
FDCE \weight_reg[1][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][4]_i_1_n_4 ),
.Q(\weight_reg[1]_0 [7]));
FDCE \weight_reg[1][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][8]_i_1_n_7 ),
.Q(\weight_reg[1]_0 [8]));
CARRY4 \weight_reg[1][8]_i_1
(.CI(\weight_reg[1][4]_i_1_n_0 ),
.CO({\weight_reg[1][8]_i_1_n_0 ,\weight_reg[1][8]_i_1_n_1 ,\weight_reg[1][8]_i_1_n_2 ,\weight_reg[1][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(in[11:8]),
.O({\weight_reg[1][8]_i_1_n_4 ,\weight_reg[1][8]_i_1_n_5 ,\weight_reg[1][8]_i_1_n_6 ,\weight_reg[1][8]_i_1_n_7 }),
.S({\weight[1][8]_i_2_n_0 ,\weight[1][8]_i_3_n_0 ,\weight[1][8]_i_4_n_0 ,\weight[1][8]_i_5_n_0 }));
FDCE \weight_reg[1][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[1][8]_i_1_n_6 ),
.Q(\weight_reg[1]_0 [9]));
FDCE \weight_reg[2][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][0]_i_1_n_7 ),
.Q(\weight_reg[2]_1 [0]));
CARRY4 \weight_reg[2][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[2][0]_i_1_n_0 ,\weight_reg[2][0]_i_1_n_1 ,\weight_reg[2][0]_i_1_n_2 ,\weight_reg[2][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__1_n_88,ARG__1_n_89,ARG__1_n_90,ARG__1_n_91}),
.O({\weight_reg[2][0]_i_1_n_4 ,\weight_reg[2][0]_i_1_n_5 ,\weight_reg[2][0]_i_1_n_6 ,\weight_reg[2][0]_i_1_n_7 }),
.S({\weight[2][0]_i_2_n_0 ,\weight[2][0]_i_3_n_0 ,\weight[2][0]_i_4_n_0 ,\weight[2][0]_i_5_n_0 }));
FDCE \weight_reg[2][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][8]_i_1_n_5 ),
.Q(\weight_reg[2]_1 [10]));
FDCE \weight_reg[2][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][8]_i_1_n_4 ),
.Q(\weight_reg[2]_1 [11]));
FDCE \weight_reg[2][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][12]_i_1_n_7 ),
.Q(\weight_reg[2]_1 [12]));
CARRY4 \weight_reg[2][12]_i_1
(.CI(\weight_reg[2][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[2][12]_i_1_CO_UNCONNECTED [3],\weight_reg[2][12]_i_1_n_1 ,\weight_reg[2][12]_i_1_n_2 ,\weight_reg[2][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__1_n_77,ARG__1_n_78,ARG__1_n_79}),
.O({\weight_reg[2][12]_i_1_n_4 ,\weight_reg[2][12]_i_1_n_5 ,\weight_reg[2][12]_i_1_n_6 ,\weight_reg[2][12]_i_1_n_7 }),
.S({\weight[2][12]_i_2_n_0 ,\weight[2][12]_i_3_n_0 ,\weight[2][12]_i_4_n_0 ,\weight[2][12]_i_5_n_0 }));
FDCE \weight_reg[2][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][12]_i_1_n_6 ),
.Q(\weight_reg[2]_1 [13]));
FDCE \weight_reg[2][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][12]_i_1_n_5 ),
.Q(\weight_reg[2]_1 [14]));
FDCE \weight_reg[2][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][12]_i_1_n_4 ),
.Q(\weight_reg[2]_1 [15]));
FDCE \weight_reg[2][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][0]_i_1_n_6 ),
.Q(\weight_reg[2]_1 [1]));
FDCE \weight_reg[2][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][0]_i_1_n_5 ),
.Q(\weight_reg[2]_1 [2]));
FDCE \weight_reg[2][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][0]_i_1_n_4 ),
.Q(\weight_reg[2]_1 [3]));
FDCE \weight_reg[2][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][4]_i_1_n_7 ),
.Q(\weight_reg[2]_1 [4]));
CARRY4 \weight_reg[2][4]_i_1
(.CI(\weight_reg[2][0]_i_1_n_0 ),
.CO({\weight_reg[2][4]_i_1_n_0 ,\weight_reg[2][4]_i_1_n_1 ,\weight_reg[2][4]_i_1_n_2 ,\weight_reg[2][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__1_n_84,ARG__1_n_85,ARG__1_n_86,ARG__1_n_87}),
.O({\weight_reg[2][4]_i_1_n_4 ,\weight_reg[2][4]_i_1_n_5 ,\weight_reg[2][4]_i_1_n_6 ,\weight_reg[2][4]_i_1_n_7 }),
.S({\weight[2][4]_i_2_n_0 ,\weight[2][4]_i_3_n_0 ,\weight[2][4]_i_4_n_0 ,\weight[2][4]_i_5_n_0 }));
FDCE \weight_reg[2][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][4]_i_1_n_6 ),
.Q(\weight_reg[2]_1 [5]));
FDCE \weight_reg[2][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][4]_i_1_n_5 ),
.Q(\weight_reg[2]_1 [6]));
FDCE \weight_reg[2][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][4]_i_1_n_4 ),
.Q(\weight_reg[2]_1 [7]));
FDCE \weight_reg[2][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][8]_i_1_n_7 ),
.Q(\weight_reg[2]_1 [8]));
CARRY4 \weight_reg[2][8]_i_1
(.CI(\weight_reg[2][4]_i_1_n_0 ),
.CO({\weight_reg[2][8]_i_1_n_0 ,\weight_reg[2][8]_i_1_n_1 ,\weight_reg[2][8]_i_1_n_2 ,\weight_reg[2][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__1_n_80,ARG__1_n_81,ARG__1_n_82,ARG__1_n_83}),
.O({\weight_reg[2][8]_i_1_n_4 ,\weight_reg[2][8]_i_1_n_5 ,\weight_reg[2][8]_i_1_n_6 ,\weight_reg[2][8]_i_1_n_7 }),
.S({\weight[2][8]_i_2_n_0 ,\weight[2][8]_i_3_n_0 ,\weight[2][8]_i_4_n_0 ,\weight[2][8]_i_5_n_0 }));
FDCE \weight_reg[2][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[2][8]_i_1_n_6 ),
.Q(\weight_reg[2]_1 [9]));
FDCE \weight_reg[3][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][0]_i_1_n_7 ),
.Q(\weight_reg[3]_2 [0]));
CARRY4 \weight_reg[3][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[3][0]_i_1_n_0 ,\weight_reg[3][0]_i_1_n_1 ,\weight_reg[3][0]_i_1_n_2 ,\weight_reg[3][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__3_n_88,ARG__3_n_89,ARG__3_n_90,ARG__3_n_91}),
.O({\weight_reg[3][0]_i_1_n_4 ,\weight_reg[3][0]_i_1_n_5 ,\weight_reg[3][0]_i_1_n_6 ,\weight_reg[3][0]_i_1_n_7 }),
.S({\weight[3][0]_i_2_n_0 ,\weight[3][0]_i_3_n_0 ,\weight[3][0]_i_4_n_0 ,\weight[3][0]_i_5_n_0 }));
FDCE \weight_reg[3][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][8]_i_1_n_5 ),
.Q(\weight_reg[3]_2 [10]));
FDCE \weight_reg[3][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][8]_i_1_n_4 ),
.Q(\weight_reg[3]_2 [11]));
FDCE \weight_reg[3][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][12]_i_1_n_7 ),
.Q(\weight_reg[3]_2 [12]));
CARRY4 \weight_reg[3][12]_i_1
(.CI(\weight_reg[3][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[3][12]_i_1_CO_UNCONNECTED [3],\weight_reg[3][12]_i_1_n_1 ,\weight_reg[3][12]_i_1_n_2 ,\weight_reg[3][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__3_n_77,ARG__3_n_78,ARG__3_n_79}),
.O({\weight_reg[3][12]_i_1_n_4 ,\weight_reg[3][12]_i_1_n_5 ,\weight_reg[3][12]_i_1_n_6 ,\weight_reg[3][12]_i_1_n_7 }),
.S({\weight[3][12]_i_2_n_0 ,\weight[3][12]_i_3_n_0 ,\weight[3][12]_i_4_n_0 ,\weight[3][12]_i_5_n_0 }));
FDCE \weight_reg[3][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][12]_i_1_n_6 ),
.Q(\weight_reg[3]_2 [13]));
FDCE \weight_reg[3][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][12]_i_1_n_5 ),
.Q(\weight_reg[3]_2 [14]));
FDCE \weight_reg[3][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][12]_i_1_n_4 ),
.Q(\weight_reg[3]_2 [15]));
FDCE \weight_reg[3][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][0]_i_1_n_6 ),
.Q(\weight_reg[3]_2 [1]));
FDCE \weight_reg[3][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][0]_i_1_n_5 ),
.Q(\weight_reg[3]_2 [2]));
FDCE \weight_reg[3][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][0]_i_1_n_4 ),
.Q(\weight_reg[3]_2 [3]));
FDCE \weight_reg[3][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][4]_i_1_n_7 ),
.Q(\weight_reg[3]_2 [4]));
CARRY4 \weight_reg[3][4]_i_1
(.CI(\weight_reg[3][0]_i_1_n_0 ),
.CO({\weight_reg[3][4]_i_1_n_0 ,\weight_reg[3][4]_i_1_n_1 ,\weight_reg[3][4]_i_1_n_2 ,\weight_reg[3][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__3_n_84,ARG__3_n_85,ARG__3_n_86,ARG__3_n_87}),
.O({\weight_reg[3][4]_i_1_n_4 ,\weight_reg[3][4]_i_1_n_5 ,\weight_reg[3][4]_i_1_n_6 ,\weight_reg[3][4]_i_1_n_7 }),
.S({\weight[3][4]_i_2_n_0 ,\weight[3][4]_i_3_n_0 ,\weight[3][4]_i_4_n_0 ,\weight[3][4]_i_5_n_0 }));
FDCE \weight_reg[3][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][4]_i_1_n_6 ),
.Q(\weight_reg[3]_2 [5]));
FDCE \weight_reg[3][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][4]_i_1_n_5 ),
.Q(\weight_reg[3]_2 [6]));
FDCE \weight_reg[3][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][4]_i_1_n_4 ),
.Q(\weight_reg[3]_2 [7]));
FDCE \weight_reg[3][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][8]_i_1_n_7 ),
.Q(\weight_reg[3]_2 [8]));
CARRY4 \weight_reg[3][8]_i_1
(.CI(\weight_reg[3][4]_i_1_n_0 ),
.CO({\weight_reg[3][8]_i_1_n_0 ,\weight_reg[3][8]_i_1_n_1 ,\weight_reg[3][8]_i_1_n_2 ,\weight_reg[3][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__3_n_80,ARG__3_n_81,ARG__3_n_82,ARG__3_n_83}),
.O({\weight_reg[3][8]_i_1_n_4 ,\weight_reg[3][8]_i_1_n_5 ,\weight_reg[3][8]_i_1_n_6 ,\weight_reg[3][8]_i_1_n_7 }),
.S({\weight[3][8]_i_2_n_0 ,\weight[3][8]_i_3_n_0 ,\weight[3][8]_i_4_n_0 ,\weight[3][8]_i_5_n_0 }));
FDCE \weight_reg[3][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[3][8]_i_1_n_6 ),
.Q(\weight_reg[3]_2 [9]));
FDCE \weight_reg[4][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][0]_i_1_n_7 ),
.Q(\weight_reg[4]_3 [0]));
CARRY4 \weight_reg[4][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[4][0]_i_1_n_0 ,\weight_reg[4][0]_i_1_n_1 ,\weight_reg[4][0]_i_1_n_2 ,\weight_reg[4][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__5_n_88,ARG__5_n_89,ARG__5_n_90,ARG__5_n_91}),
.O({\weight_reg[4][0]_i_1_n_4 ,\weight_reg[4][0]_i_1_n_5 ,\weight_reg[4][0]_i_1_n_6 ,\weight_reg[4][0]_i_1_n_7 }),
.S({\weight[4][0]_i_2_n_0 ,\weight[4][0]_i_3_n_0 ,\weight[4][0]_i_4_n_0 ,\weight[4][0]_i_5_n_0 }));
FDCE \weight_reg[4][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][8]_i_1_n_5 ),
.Q(\weight_reg[4]_3 [10]));
FDCE \weight_reg[4][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][8]_i_1_n_4 ),
.Q(\weight_reg[4]_3 [11]));
FDCE \weight_reg[4][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][12]_i_1_n_7 ),
.Q(\weight_reg[4]_3 [12]));
CARRY4 \weight_reg[4][12]_i_1
(.CI(\weight_reg[4][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[4][12]_i_1_CO_UNCONNECTED [3],\weight_reg[4][12]_i_1_n_1 ,\weight_reg[4][12]_i_1_n_2 ,\weight_reg[4][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__5_n_77,ARG__5_n_78,ARG__5_n_79}),
.O({\weight_reg[4][12]_i_1_n_4 ,\weight_reg[4][12]_i_1_n_5 ,\weight_reg[4][12]_i_1_n_6 ,\weight_reg[4][12]_i_1_n_7 }),
.S({\weight[4][12]_i_2_n_0 ,\weight[4][12]_i_3_n_0 ,\weight[4][12]_i_4_n_0 ,\weight[4][12]_i_5_n_0 }));
FDCE \weight_reg[4][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][12]_i_1_n_6 ),
.Q(\weight_reg[4]_3 [13]));
FDCE \weight_reg[4][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][12]_i_1_n_5 ),
.Q(\weight_reg[4]_3 [14]));
FDCE \weight_reg[4][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][12]_i_1_n_4 ),
.Q(\weight_reg[4]_3 [15]));
FDCE \weight_reg[4][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][0]_i_1_n_6 ),
.Q(\weight_reg[4]_3 [1]));
FDCE \weight_reg[4][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][0]_i_1_n_5 ),
.Q(\weight_reg[4]_3 [2]));
FDCE \weight_reg[4][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][0]_i_1_n_4 ),
.Q(\weight_reg[4]_3 [3]));
FDCE \weight_reg[4][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][4]_i_1_n_7 ),
.Q(\weight_reg[4]_3 [4]));
CARRY4 \weight_reg[4][4]_i_1
(.CI(\weight_reg[4][0]_i_1_n_0 ),
.CO({\weight_reg[4][4]_i_1_n_0 ,\weight_reg[4][4]_i_1_n_1 ,\weight_reg[4][4]_i_1_n_2 ,\weight_reg[4][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__5_n_84,ARG__5_n_85,ARG__5_n_86,ARG__5_n_87}),
.O({\weight_reg[4][4]_i_1_n_4 ,\weight_reg[4][4]_i_1_n_5 ,\weight_reg[4][4]_i_1_n_6 ,\weight_reg[4][4]_i_1_n_7 }),
.S({\weight[4][4]_i_2_n_0 ,\weight[4][4]_i_3_n_0 ,\weight[4][4]_i_4_n_0 ,\weight[4][4]_i_5_n_0 }));
FDCE \weight_reg[4][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][4]_i_1_n_6 ),
.Q(\weight_reg[4]_3 [5]));
FDCE \weight_reg[4][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][4]_i_1_n_5 ),
.Q(\weight_reg[4]_3 [6]));
FDCE \weight_reg[4][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][4]_i_1_n_4 ),
.Q(\weight_reg[4]_3 [7]));
FDCE \weight_reg[4][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][8]_i_1_n_7 ),
.Q(\weight_reg[4]_3 [8]));
CARRY4 \weight_reg[4][8]_i_1
(.CI(\weight_reg[4][4]_i_1_n_0 ),
.CO({\weight_reg[4][8]_i_1_n_0 ,\weight_reg[4][8]_i_1_n_1 ,\weight_reg[4][8]_i_1_n_2 ,\weight_reg[4][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__5_n_80,ARG__5_n_81,ARG__5_n_82,ARG__5_n_83}),
.O({\weight_reg[4][8]_i_1_n_4 ,\weight_reg[4][8]_i_1_n_5 ,\weight_reg[4][8]_i_1_n_6 ,\weight_reg[4][8]_i_1_n_7 }),
.S({\weight[4][8]_i_2_n_0 ,\weight[4][8]_i_3_n_0 ,\weight[4][8]_i_4_n_0 ,\weight[4][8]_i_5_n_0 }));
FDCE \weight_reg[4][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[4][8]_i_1_n_6 ),
.Q(\weight_reg[4]_3 [9]));
FDCE \weight_reg[5][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][0]_i_1_n_7 ),
.Q(\weight_reg[5]_4 [0]));
CARRY4 \weight_reg[5][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[5][0]_i_1_n_0 ,\weight_reg[5][0]_i_1_n_1 ,\weight_reg[5][0]_i_1_n_2 ,\weight_reg[5][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__7_n_88,ARG__7_n_89,ARG__7_n_90,ARG__7_n_91}),
.O({\weight_reg[5][0]_i_1_n_4 ,\weight_reg[5][0]_i_1_n_5 ,\weight_reg[5][0]_i_1_n_6 ,\weight_reg[5][0]_i_1_n_7 }),
.S({\weight[5][0]_i_2_n_0 ,\weight[5][0]_i_3_n_0 ,\weight[5][0]_i_4_n_0 ,\weight[5][0]_i_5_n_0 }));
FDCE \weight_reg[5][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][8]_i_1_n_5 ),
.Q(\weight_reg[5]_4 [10]));
FDCE \weight_reg[5][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][8]_i_1_n_4 ),
.Q(\weight_reg[5]_4 [11]));
FDCE \weight_reg[5][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][12]_i_1_n_7 ),
.Q(\weight_reg[5]_4 [12]));
CARRY4 \weight_reg[5][12]_i_1
(.CI(\weight_reg[5][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[5][12]_i_1_CO_UNCONNECTED [3],\weight_reg[5][12]_i_1_n_1 ,\weight_reg[5][12]_i_1_n_2 ,\weight_reg[5][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__7_n_77,ARG__7_n_78,ARG__7_n_79}),
.O({\weight_reg[5][12]_i_1_n_4 ,\weight_reg[5][12]_i_1_n_5 ,\weight_reg[5][12]_i_1_n_6 ,\weight_reg[5][12]_i_1_n_7 }),
.S({\weight[5][12]_i_2_n_0 ,\weight[5][12]_i_3_n_0 ,\weight[5][12]_i_4_n_0 ,\weight[5][12]_i_5_n_0 }));
FDCE \weight_reg[5][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][12]_i_1_n_6 ),
.Q(\weight_reg[5]_4 [13]));
FDCE \weight_reg[5][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][12]_i_1_n_5 ),
.Q(\weight_reg[5]_4 [14]));
FDCE \weight_reg[5][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][12]_i_1_n_4 ),
.Q(\weight_reg[5]_4 [15]));
FDCE \weight_reg[5][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][0]_i_1_n_6 ),
.Q(\weight_reg[5]_4 [1]));
FDCE \weight_reg[5][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][0]_i_1_n_5 ),
.Q(\weight_reg[5]_4 [2]));
FDCE \weight_reg[5][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][0]_i_1_n_4 ),
.Q(\weight_reg[5]_4 [3]));
FDCE \weight_reg[5][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][4]_i_1_n_7 ),
.Q(\weight_reg[5]_4 [4]));
CARRY4 \weight_reg[5][4]_i_1
(.CI(\weight_reg[5][0]_i_1_n_0 ),
.CO({\weight_reg[5][4]_i_1_n_0 ,\weight_reg[5][4]_i_1_n_1 ,\weight_reg[5][4]_i_1_n_2 ,\weight_reg[5][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__7_n_84,ARG__7_n_85,ARG__7_n_86,ARG__7_n_87}),
.O({\weight_reg[5][4]_i_1_n_4 ,\weight_reg[5][4]_i_1_n_5 ,\weight_reg[5][4]_i_1_n_6 ,\weight_reg[5][4]_i_1_n_7 }),
.S({\weight[5][4]_i_2_n_0 ,\weight[5][4]_i_3_n_0 ,\weight[5][4]_i_4_n_0 ,\weight[5][4]_i_5_n_0 }));
FDCE \weight_reg[5][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][4]_i_1_n_6 ),
.Q(\weight_reg[5]_4 [5]));
FDCE \weight_reg[5][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][4]_i_1_n_5 ),
.Q(\weight_reg[5]_4 [6]));
FDCE \weight_reg[5][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][4]_i_1_n_4 ),
.Q(\weight_reg[5]_4 [7]));
FDCE \weight_reg[5][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][8]_i_1_n_7 ),
.Q(\weight_reg[5]_4 [8]));
CARRY4 \weight_reg[5][8]_i_1
(.CI(\weight_reg[5][4]_i_1_n_0 ),
.CO({\weight_reg[5][8]_i_1_n_0 ,\weight_reg[5][8]_i_1_n_1 ,\weight_reg[5][8]_i_1_n_2 ,\weight_reg[5][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__7_n_80,ARG__7_n_81,ARG__7_n_82,ARG__7_n_83}),
.O({\weight_reg[5][8]_i_1_n_4 ,\weight_reg[5][8]_i_1_n_5 ,\weight_reg[5][8]_i_1_n_6 ,\weight_reg[5][8]_i_1_n_7 }),
.S({\weight[5][8]_i_2_n_0 ,\weight[5][8]_i_3_n_0 ,\weight[5][8]_i_4_n_0 ,\weight[5][8]_i_5_n_0 }));
FDCE \weight_reg[5][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[5][8]_i_1_n_6 ),
.Q(\weight_reg[5]_4 [9]));
FDCE \weight_reg[6][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][0]_i_1_n_7 ),
.Q(\weight_reg[6]_5 [0]));
CARRY4 \weight_reg[6][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[6][0]_i_1_n_0 ,\weight_reg[6][0]_i_1_n_1 ,\weight_reg[6][0]_i_1_n_2 ,\weight_reg[6][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__9_n_88,ARG__9_n_89,ARG__9_n_90,ARG__9_n_91}),
.O({\weight_reg[6][0]_i_1_n_4 ,\weight_reg[6][0]_i_1_n_5 ,\weight_reg[6][0]_i_1_n_6 ,\weight_reg[6][0]_i_1_n_7 }),
.S({\weight[6][0]_i_2_n_0 ,\weight[6][0]_i_3_n_0 ,\weight[6][0]_i_4_n_0 ,\weight[6][0]_i_5_n_0 }));
FDCE \weight_reg[6][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][8]_i_1_n_5 ),
.Q(\weight_reg[6]_5 [10]));
FDCE \weight_reg[6][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][8]_i_1_n_4 ),
.Q(\weight_reg[6]_5 [11]));
FDCE \weight_reg[6][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][12]_i_1_n_7 ),
.Q(\weight_reg[6]_5 [12]));
CARRY4 \weight_reg[6][12]_i_1
(.CI(\weight_reg[6][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[6][12]_i_1_CO_UNCONNECTED [3],\weight_reg[6][12]_i_1_n_1 ,\weight_reg[6][12]_i_1_n_2 ,\weight_reg[6][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__9_n_77,ARG__9_n_78,ARG__9_n_79}),
.O({\weight_reg[6][12]_i_1_n_4 ,\weight_reg[6][12]_i_1_n_5 ,\weight_reg[6][12]_i_1_n_6 ,\weight_reg[6][12]_i_1_n_7 }),
.S({\weight[6][12]_i_2_n_0 ,\weight[6][12]_i_3_n_0 ,\weight[6][12]_i_4_n_0 ,\weight[6][12]_i_5_n_0 }));
FDCE \weight_reg[6][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][12]_i_1_n_6 ),
.Q(\weight_reg[6]_5 [13]));
FDCE \weight_reg[6][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][12]_i_1_n_5 ),
.Q(\weight_reg[6]_5 [14]));
FDCE \weight_reg[6][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][12]_i_1_n_4 ),
.Q(\weight_reg[6]_5 [15]));
FDCE \weight_reg[6][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][0]_i_1_n_6 ),
.Q(\weight_reg[6]_5 [1]));
FDCE \weight_reg[6][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][0]_i_1_n_5 ),
.Q(\weight_reg[6]_5 [2]));
FDCE \weight_reg[6][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][0]_i_1_n_4 ),
.Q(\weight_reg[6]_5 [3]));
FDCE \weight_reg[6][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][4]_i_1_n_7 ),
.Q(\weight_reg[6]_5 [4]));
CARRY4 \weight_reg[6][4]_i_1
(.CI(\weight_reg[6][0]_i_1_n_0 ),
.CO({\weight_reg[6][4]_i_1_n_0 ,\weight_reg[6][4]_i_1_n_1 ,\weight_reg[6][4]_i_1_n_2 ,\weight_reg[6][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__9_n_84,ARG__9_n_85,ARG__9_n_86,ARG__9_n_87}),
.O({\weight_reg[6][4]_i_1_n_4 ,\weight_reg[6][4]_i_1_n_5 ,\weight_reg[6][4]_i_1_n_6 ,\weight_reg[6][4]_i_1_n_7 }),
.S({\weight[6][4]_i_2_n_0 ,\weight[6][4]_i_3_n_0 ,\weight[6][4]_i_4_n_0 ,\weight[6][4]_i_5_n_0 }));
FDCE \weight_reg[6][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][4]_i_1_n_6 ),
.Q(\weight_reg[6]_5 [5]));
FDCE \weight_reg[6][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][4]_i_1_n_5 ),
.Q(\weight_reg[6]_5 [6]));
FDCE \weight_reg[6][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][4]_i_1_n_4 ),
.Q(\weight_reg[6]_5 [7]));
FDCE \weight_reg[6][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][8]_i_1_n_7 ),
.Q(\weight_reg[6]_5 [8]));
CARRY4 \weight_reg[6][8]_i_1
(.CI(\weight_reg[6][4]_i_1_n_0 ),
.CO({\weight_reg[6][8]_i_1_n_0 ,\weight_reg[6][8]_i_1_n_1 ,\weight_reg[6][8]_i_1_n_2 ,\weight_reg[6][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__9_n_80,ARG__9_n_81,ARG__9_n_82,ARG__9_n_83}),
.O({\weight_reg[6][8]_i_1_n_4 ,\weight_reg[6][8]_i_1_n_5 ,\weight_reg[6][8]_i_1_n_6 ,\weight_reg[6][8]_i_1_n_7 }),
.S({\weight[6][8]_i_2_n_0 ,\weight[6][8]_i_3_n_0 ,\weight[6][8]_i_4_n_0 ,\weight[6][8]_i_5_n_0 }));
FDCE \weight_reg[6][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[6][8]_i_1_n_6 ),
.Q(\weight_reg[6]_5 [9]));
FDCE \weight_reg[7][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][0]_i_1_n_7 ),
.Q(\weight_reg[7]_6 [0]));
CARRY4 \weight_reg[7][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[7][0]_i_1_n_0 ,\weight_reg[7][0]_i_1_n_1 ,\weight_reg[7][0]_i_1_n_2 ,\weight_reg[7][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__11_n_88,ARG__11_n_89,ARG__11_n_90,ARG__11_n_91}),
.O({\weight_reg[7][0]_i_1_n_4 ,\weight_reg[7][0]_i_1_n_5 ,\weight_reg[7][0]_i_1_n_6 ,\weight_reg[7][0]_i_1_n_7 }),
.S({\weight[7][0]_i_2_n_0 ,\weight[7][0]_i_3_n_0 ,\weight[7][0]_i_4_n_0 ,\weight[7][0]_i_5_n_0 }));
FDCE \weight_reg[7][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][8]_i_1_n_5 ),
.Q(\weight_reg[7]_6 [10]));
FDCE \weight_reg[7][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][8]_i_1_n_4 ),
.Q(\weight_reg[7]_6 [11]));
FDCE \weight_reg[7][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][12]_i_1_n_7 ),
.Q(\weight_reg[7]_6 [12]));
CARRY4 \weight_reg[7][12]_i_1
(.CI(\weight_reg[7][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[7][12]_i_1_CO_UNCONNECTED [3],\weight_reg[7][12]_i_1_n_1 ,\weight_reg[7][12]_i_1_n_2 ,\weight_reg[7][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__11_n_77,ARG__11_n_78,ARG__11_n_79}),
.O({\weight_reg[7][12]_i_1_n_4 ,\weight_reg[7][12]_i_1_n_5 ,\weight_reg[7][12]_i_1_n_6 ,\weight_reg[7][12]_i_1_n_7 }),
.S({\weight[7][12]_i_2_n_0 ,\weight[7][12]_i_3_n_0 ,\weight[7][12]_i_4_n_0 ,\weight[7][12]_i_5_n_0 }));
FDCE \weight_reg[7][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][12]_i_1_n_6 ),
.Q(\weight_reg[7]_6 [13]));
FDCE \weight_reg[7][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][12]_i_1_n_5 ),
.Q(\weight_reg[7]_6 [14]));
FDCE \weight_reg[7][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][12]_i_1_n_4 ),
.Q(\weight_reg[7]_6 [15]));
FDCE \weight_reg[7][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][0]_i_1_n_6 ),
.Q(\weight_reg[7]_6 [1]));
FDCE \weight_reg[7][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][0]_i_1_n_5 ),
.Q(\weight_reg[7]_6 [2]));
FDCE \weight_reg[7][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][0]_i_1_n_4 ),
.Q(\weight_reg[7]_6 [3]));
FDCE \weight_reg[7][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][4]_i_1_n_7 ),
.Q(\weight_reg[7]_6 [4]));
CARRY4 \weight_reg[7][4]_i_1
(.CI(\weight_reg[7][0]_i_1_n_0 ),
.CO({\weight_reg[7][4]_i_1_n_0 ,\weight_reg[7][4]_i_1_n_1 ,\weight_reg[7][4]_i_1_n_2 ,\weight_reg[7][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__11_n_84,ARG__11_n_85,ARG__11_n_86,ARG__11_n_87}),
.O({\weight_reg[7][4]_i_1_n_4 ,\weight_reg[7][4]_i_1_n_5 ,\weight_reg[7][4]_i_1_n_6 ,\weight_reg[7][4]_i_1_n_7 }),
.S({\weight[7][4]_i_2_n_0 ,\weight[7][4]_i_3_n_0 ,\weight[7][4]_i_4_n_0 ,\weight[7][4]_i_5_n_0 }));
FDCE \weight_reg[7][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][4]_i_1_n_6 ),
.Q(\weight_reg[7]_6 [5]));
FDCE \weight_reg[7][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][4]_i_1_n_5 ),
.Q(\weight_reg[7]_6 [6]));
FDCE \weight_reg[7][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][4]_i_1_n_4 ),
.Q(\weight_reg[7]_6 [7]));
FDCE \weight_reg[7][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][8]_i_1_n_7 ),
.Q(\weight_reg[7]_6 [8]));
CARRY4 \weight_reg[7][8]_i_1
(.CI(\weight_reg[7][4]_i_1_n_0 ),
.CO({\weight_reg[7][8]_i_1_n_0 ,\weight_reg[7][8]_i_1_n_1 ,\weight_reg[7][8]_i_1_n_2 ,\weight_reg[7][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__11_n_80,ARG__11_n_81,ARG__11_n_82,ARG__11_n_83}),
.O({\weight_reg[7][8]_i_1_n_4 ,\weight_reg[7][8]_i_1_n_5 ,\weight_reg[7][8]_i_1_n_6 ,\weight_reg[7][8]_i_1_n_7 }),
.S({\weight[7][8]_i_2_n_0 ,\weight[7][8]_i_3_n_0 ,\weight[7][8]_i_4_n_0 ,\weight[7][8]_i_5_n_0 }));
FDCE \weight_reg[7][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[7][8]_i_1_n_6 ),
.Q(\weight_reg[7]_6 [9]));
FDCE \weight_reg[8][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][0]_i_1_n_7 ),
.Q(\weight_reg[8]_7 [0]));
CARRY4 \weight_reg[8][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[8][0]_i_1_n_0 ,\weight_reg[8][0]_i_1_n_1 ,\weight_reg[8][0]_i_1_n_2 ,\weight_reg[8][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__13_n_88,ARG__13_n_89,ARG__13_n_90,ARG__13_n_91}),
.O({\weight_reg[8][0]_i_1_n_4 ,\weight_reg[8][0]_i_1_n_5 ,\weight_reg[8][0]_i_1_n_6 ,\weight_reg[8][0]_i_1_n_7 }),
.S({\weight[8][0]_i_2_n_0 ,\weight[8][0]_i_3_n_0 ,\weight[8][0]_i_4_n_0 ,\weight[8][0]_i_5_n_0 }));
FDCE \weight_reg[8][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][8]_i_1_n_5 ),
.Q(\weight_reg[8]_7 [10]));
FDCE \weight_reg[8][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][8]_i_1_n_4 ),
.Q(\weight_reg[8]_7 [11]));
FDCE \weight_reg[8][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][12]_i_1_n_7 ),
.Q(\weight_reg[8]_7 [12]));
CARRY4 \weight_reg[8][12]_i_1
(.CI(\weight_reg[8][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[8][12]_i_1_CO_UNCONNECTED [3],\weight_reg[8][12]_i_1_n_1 ,\weight_reg[8][12]_i_1_n_2 ,\weight_reg[8][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__13_n_77,ARG__13_n_78,ARG__13_n_79}),
.O({\weight_reg[8][12]_i_1_n_4 ,\weight_reg[8][12]_i_1_n_5 ,\weight_reg[8][12]_i_1_n_6 ,\weight_reg[8][12]_i_1_n_7 }),
.S({\weight[8][12]_i_2_n_0 ,\weight[8][12]_i_3_n_0 ,\weight[8][12]_i_4_n_0 ,\weight[8][12]_i_5_n_0 }));
FDCE \weight_reg[8][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][12]_i_1_n_6 ),
.Q(\weight_reg[8]_7 [13]));
FDCE \weight_reg[8][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][12]_i_1_n_5 ),
.Q(\weight_reg[8]_7 [14]));
FDCE \weight_reg[8][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][12]_i_1_n_4 ),
.Q(\weight_reg[8]_7 [15]));
FDCE \weight_reg[8][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][0]_i_1_n_6 ),
.Q(\weight_reg[8]_7 [1]));
FDCE \weight_reg[8][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][0]_i_1_n_5 ),
.Q(\weight_reg[8]_7 [2]));
FDCE \weight_reg[8][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][0]_i_1_n_4 ),
.Q(\weight_reg[8]_7 [3]));
FDCE \weight_reg[8][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][4]_i_1_n_7 ),
.Q(\weight_reg[8]_7 [4]));
CARRY4 \weight_reg[8][4]_i_1
(.CI(\weight_reg[8][0]_i_1_n_0 ),
.CO({\weight_reg[8][4]_i_1_n_0 ,\weight_reg[8][4]_i_1_n_1 ,\weight_reg[8][4]_i_1_n_2 ,\weight_reg[8][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__13_n_84,ARG__13_n_85,ARG__13_n_86,ARG__13_n_87}),
.O({\weight_reg[8][4]_i_1_n_4 ,\weight_reg[8][4]_i_1_n_5 ,\weight_reg[8][4]_i_1_n_6 ,\weight_reg[8][4]_i_1_n_7 }),
.S({\weight[8][4]_i_2_n_0 ,\weight[8][4]_i_3_n_0 ,\weight[8][4]_i_4_n_0 ,\weight[8][4]_i_5_n_0 }));
FDCE \weight_reg[8][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][4]_i_1_n_6 ),
.Q(\weight_reg[8]_7 [5]));
FDCE \weight_reg[8][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][4]_i_1_n_5 ),
.Q(\weight_reg[8]_7 [6]));
FDCE \weight_reg[8][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][4]_i_1_n_4 ),
.Q(\weight_reg[8]_7 [7]));
FDCE \weight_reg[8][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][8]_i_1_n_7 ),
.Q(\weight_reg[8]_7 [8]));
CARRY4 \weight_reg[8][8]_i_1
(.CI(\weight_reg[8][4]_i_1_n_0 ),
.CO({\weight_reg[8][8]_i_1_n_0 ,\weight_reg[8][8]_i_1_n_1 ,\weight_reg[8][8]_i_1_n_2 ,\weight_reg[8][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__13_n_80,ARG__13_n_81,ARG__13_n_82,ARG__13_n_83}),
.O({\weight_reg[8][8]_i_1_n_4 ,\weight_reg[8][8]_i_1_n_5 ,\weight_reg[8][8]_i_1_n_6 ,\weight_reg[8][8]_i_1_n_7 }),
.S({\weight[8][8]_i_2_n_0 ,\weight[8][8]_i_3_n_0 ,\weight[8][8]_i_4_n_0 ,\weight[8][8]_i_5_n_0 }));
FDCE \weight_reg[8][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[8][8]_i_1_n_6 ),
.Q(\weight_reg[8]_7 [9]));
FDCE \weight_reg[9][0]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][0]_i_1_n_7 ),
.Q(\weight_reg[9]_8 [0]));
CARRY4 \weight_reg[9][0]_i_1
(.CI(1'b0),
.CO({\weight_reg[9][0]_i_1_n_0 ,\weight_reg[9][0]_i_1_n_1 ,\weight_reg[9][0]_i_1_n_2 ,\weight_reg[9][0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__15_n_88,ARG__15_n_89,ARG__15_n_90,ARG__15_n_91}),
.O({\weight_reg[9][0]_i_1_n_4 ,\weight_reg[9][0]_i_1_n_5 ,\weight_reg[9][0]_i_1_n_6 ,\weight_reg[9][0]_i_1_n_7 }),
.S({\weight[9][0]_i_2_n_0 ,\weight[9][0]_i_3_n_0 ,\weight[9][0]_i_4_n_0 ,\weight[9][0]_i_5_n_0 }));
FDCE \weight_reg[9][10]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][8]_i_1_n_5 ),
.Q(\weight_reg[9]_8 [10]));
FDCE \weight_reg[9][11]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][8]_i_1_n_4 ),
.Q(\weight_reg[9]_8 [11]));
FDCE \weight_reg[9][12]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][12]_i_1_n_7 ),
.Q(\weight_reg[9]_8 [12]));
CARRY4 \weight_reg[9][12]_i_1
(.CI(\weight_reg[9][8]_i_1_n_0 ),
.CO({\NLW_weight_reg[9][12]_i_1_CO_UNCONNECTED [3],\weight_reg[9][12]_i_1_n_1 ,\weight_reg[9][12]_i_1_n_2 ,\weight_reg[9][12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,ARG__15_n_77,ARG__15_n_78,ARG__15_n_79}),
.O({\weight_reg[9][12]_i_1_n_4 ,\weight_reg[9][12]_i_1_n_5 ,\weight_reg[9][12]_i_1_n_6 ,\weight_reg[9][12]_i_1_n_7 }),
.S({\weight[9][12]_i_2_n_0 ,\weight[9][12]_i_3_n_0 ,\weight[9][12]_i_4_n_0 ,\weight[9][12]_i_5_n_0 }));
FDCE \weight_reg[9][13]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][12]_i_1_n_6 ),
.Q(\weight_reg[9]_8 [13]));
FDCE \weight_reg[9][14]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][12]_i_1_n_5 ),
.Q(\weight_reg[9]_8 [14]));
FDCE \weight_reg[9][15]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][12]_i_1_n_4 ),
.Q(\weight_reg[9]_8 [15]));
FDCE \weight_reg[9][1]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][0]_i_1_n_6 ),
.Q(\weight_reg[9]_8 [1]));
FDCE \weight_reg[9][2]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][0]_i_1_n_5 ),
.Q(\weight_reg[9]_8 [2]));
FDCE \weight_reg[9][3]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][0]_i_1_n_4 ),
.Q(\weight_reg[9]_8 [3]));
FDCE \weight_reg[9][4]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][4]_i_1_n_7 ),
.Q(\weight_reg[9]_8 [4]));
CARRY4 \weight_reg[9][4]_i_1
(.CI(\weight_reg[9][0]_i_1_n_0 ),
.CO({\weight_reg[9][4]_i_1_n_0 ,\weight_reg[9][4]_i_1_n_1 ,\weight_reg[9][4]_i_1_n_2 ,\weight_reg[9][4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__15_n_84,ARG__15_n_85,ARG__15_n_86,ARG__15_n_87}),
.O({\weight_reg[9][4]_i_1_n_4 ,\weight_reg[9][4]_i_1_n_5 ,\weight_reg[9][4]_i_1_n_6 ,\weight_reg[9][4]_i_1_n_7 }),
.S({\weight[9][4]_i_2_n_0 ,\weight[9][4]_i_3_n_0 ,\weight[9][4]_i_4_n_0 ,\weight[9][4]_i_5_n_0 }));
FDCE \weight_reg[9][5]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][4]_i_1_n_6 ),
.Q(\weight_reg[9]_8 [5]));
FDCE \weight_reg[9][6]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][4]_i_1_n_5 ),
.Q(\weight_reg[9]_8 [6]));
FDCE \weight_reg[9][7]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][4]_i_1_n_4 ),
.Q(\weight_reg[9]_8 [7]));
FDCE \weight_reg[9][8]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][8]_i_1_n_7 ),
.Q(\weight_reg[9]_8 [8]));
CARRY4 \weight_reg[9][8]_i_1
(.CI(\weight_reg[9][4]_i_1_n_0 ),
.CO({\weight_reg[9][8]_i_1_n_0 ,\weight_reg[9][8]_i_1_n_1 ,\weight_reg[9][8]_i_1_n_2 ,\weight_reg[9][8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({ARG__15_n_80,ARG__15_n_81,ARG__15_n_82,ARG__15_n_83}),
.O({\weight_reg[9][8]_i_1_n_4 ,\weight_reg[9][8]_i_1_n_5 ,\weight_reg[9][8]_i_1_n_6 ,\weight_reg[9][8]_i_1_n_7 }),
.S({\weight[9][8]_i_2_n_0 ,\weight[9][8]_i_3_n_0 ,\weight[9][8]_i_4_n_0 ,\weight[9][8]_i_5_n_0 }));
FDCE \weight_reg[9][9]
(.C(IPCORE_CLK),
.CE(cop_dut_enable),
.CLR(AR),
.D(\weight_reg[9][8]_i_1_n_6 ),
.Q(\weight_reg[9]_8 [9]));
endmodule
(* ORIG_REF_NAME = "lms_pcore" *)
module ip_design_lms_pcore_0_0_lms_pcore
(AXI4_Lite_WREADY,
AXI4_Lite_BVALID,
AXI4_Lite_RVALID,
AXI4_Lite_RDATA,
AXI4_Lite_ARREADY,
AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID,
AXI4_Lite_WVALID,
AXI4_Lite_ARESETN,
IPCORE_RESETN,
AXI4_Lite_WDATA,
AXI4_Lite_ACLK,
AXI4_Lite_AWADDR,
IPCORE_CLK,
AXI4_Lite_ARVALID,
AXI4_Lite_ARADDR,
AXI4_Lite_RREADY,
AXI4_Lite_BREADY);
output AXI4_Lite_WREADY;
output AXI4_Lite_BVALID;
output AXI4_Lite_RVALID;
output [15:0]AXI4_Lite_RDATA;
output AXI4_Lite_ARREADY;
output AXI4_Lite_AWREADY;
input AXI4_Lite_AWVALID;
input AXI4_Lite_WVALID;
input AXI4_Lite_ARESETN;
input IPCORE_RESETN;
input [15:0]AXI4_Lite_WDATA;
input AXI4_Lite_ACLK;
input [13:0]AXI4_Lite_AWADDR;
input IPCORE_CLK;
input AXI4_Lite_ARVALID;
input [13:0]AXI4_Lite_ARADDR;
input AXI4_Lite_RREADY;
input AXI4_Lite_BREADY;
wire AXI4_Lite_ACLK;
wire [13:0]AXI4_Lite_ARADDR;
wire AXI4_Lite_ARESETN;
wire AXI4_Lite_ARREADY;
wire AXI4_Lite_ARVALID;
wire [13:0]AXI4_Lite_AWADDR;
wire AXI4_Lite_AWREADY;
wire AXI4_Lite_AWVALID;
wire AXI4_Lite_BREADY;
wire AXI4_Lite_BVALID;
wire [15:0]AXI4_Lite_RDATA;
wire AXI4_Lite_RREADY;
wire AXI4_Lite_RVALID;
wire [15:0]AXI4_Lite_WDATA;
wire AXI4_Lite_WREADY;
wire AXI4_Lite_WVALID;
wire IPCORE_CLK;
wire IPCORE_RESETN;
wire cop_dut_enable;
wire cop_out_ready;
wire [1:0]cp_controller_cpstate;
wire [15:0]filter_sum;
wire [15:0]\u_LMS/mul_temp_16 ;
wire u_lms_pcore_axi_lite_inst_n_0;
wire u_lms_pcore_axi_lite_inst_n_24;
wire u_lms_pcore_axi_lite_inst_n_25;
wire u_lms_pcore_axi_lite_inst_n_26;
wire u_lms_pcore_axi_lite_inst_n_27;
wire u_lms_pcore_axi_lite_inst_n_28;
wire u_lms_pcore_axi_lite_inst_n_29;
wire u_lms_pcore_axi_lite_inst_n_30;
wire u_lms_pcore_axi_lite_inst_n_31;
wire u_lms_pcore_axi_lite_inst_n_32;
wire u_lms_pcore_axi_lite_inst_n_33;
wire u_lms_pcore_axi_lite_inst_n_34;
wire u_lms_pcore_axi_lite_inst_n_35;
wire u_lms_pcore_axi_lite_inst_n_36;
wire u_lms_pcore_axi_lite_inst_n_37;
wire u_lms_pcore_axi_lite_inst_n_38;
wire u_lms_pcore_axi_lite_inst_n_39;
wire u_lms_pcore_axi_lite_inst_n_40;
wire u_lms_pcore_axi_lite_inst_n_5;
wire u_lms_pcore_axi_lite_inst_n_6;
wire u_lms_pcore_axi_lite_inst_n_7;
wire u_lms_pcore_axi_lite_inst_n_8;
wire write_reg_axi_enable;
wire [14:0]write_reg_d_k;
wire [15:0]write_reg_x_k;
ip_design_lms_pcore_0_0_lms_pcore_axi_lite u_lms_pcore_axi_lite_inst
(.ARG__28(write_reg_x_k),
.ARG__29({u_lms_pcore_axi_lite_inst_n_37,u_lms_pcore_axi_lite_inst_n_38,u_lms_pcore_axi_lite_inst_n_39}),
.AXI4_Lite_ACLK(AXI4_Lite_ACLK),
.AXI4_Lite_ARADDR(AXI4_Lite_ARADDR),
.AXI4_Lite_ARESETN(AXI4_Lite_ARESETN),
.AXI4_Lite_ARREADY(AXI4_Lite_ARREADY),
.AXI4_Lite_ARVALID(AXI4_Lite_ARVALID),
.AXI4_Lite_AWADDR(AXI4_Lite_AWADDR),
.AXI4_Lite_AWREADY(AXI4_Lite_AWREADY),
.AXI4_Lite_AWVALID(AXI4_Lite_AWVALID),
.AXI4_Lite_BREADY(AXI4_Lite_BREADY),
.AXI4_Lite_BVALID(AXI4_Lite_BVALID),
.AXI4_Lite_RDATA(AXI4_Lite_RDATA),
.AXI4_Lite_RREADY(AXI4_Lite_RREADY),
.AXI4_Lite_RVALID(AXI4_Lite_RVALID),
.AXI4_Lite_WDATA(AXI4_Lite_WDATA),
.AXI4_Lite_WREADY(AXI4_Lite_WREADY),
.AXI4_Lite_WVALID(AXI4_Lite_WVALID),
.DI(u_lms_pcore_axi_lite_inst_n_36),
.IPCORE_RESETN(IPCORE_RESETN),
.Q(write_reg_d_k),
.S({u_lms_pcore_axi_lite_inst_n_5,u_lms_pcore_axi_lite_inst_n_6,u_lms_pcore_axi_lite_inst_n_7,u_lms_pcore_axi_lite_inst_n_8}),
.cop_out_ready(cop_out_ready),
.cp_controller_cpstate(cp_controller_cpstate),
.\cp_controller_cpstate_reg[0] (u_lms_pcore_axi_lite_inst_n_40),
.filter_sum(filter_sum),
.mul_temp_16(\u_LMS/mul_temp_16 ),
.\sync_reg_e_k_reg[11] ({u_lms_pcore_axi_lite_inst_n_24,u_lms_pcore_axi_lite_inst_n_25,u_lms_pcore_axi_lite_inst_n_26,u_lms_pcore_axi_lite_inst_n_27}),
.\sync_reg_e_k_reg[3] ({u_lms_pcore_axi_lite_inst_n_32,u_lms_pcore_axi_lite_inst_n_33,u_lms_pcore_axi_lite_inst_n_34,u_lms_pcore_axi_lite_inst_n_35}),
.\sync_reg_e_k_reg[7] ({u_lms_pcore_axi_lite_inst_n_28,u_lms_pcore_axi_lite_inst_n_29,u_lms_pcore_axi_lite_inst_n_30,u_lms_pcore_axi_lite_inst_n_31}),
.write_reg_axi_enable(write_reg_axi_enable),
.write_reg_axi_enable_reg(u_lms_pcore_axi_lite_inst_n_0));
ip_design_lms_pcore_0_0_lms_pcore_cop u_lms_pcore_cop_inst
(.AR(u_lms_pcore_axi_lite_inst_n_0),
.IPCORE_CLK(IPCORE_CLK),
.cop_dut_enable(cop_dut_enable),
.cop_out_ready(cop_out_ready),
.cp_controller_cpstate(cp_controller_cpstate),
.strobe_reg_cop_in_strobe_reg(u_lms_pcore_axi_lite_inst_n_40),
.write_reg_axi_enable(write_reg_axi_enable));
ip_design_lms_pcore_0_0_lms_pcore_dut u_lms_pcore_dut_inst
(.AR(u_lms_pcore_axi_lite_inst_n_0),
.DI(u_lms_pcore_axi_lite_inst_n_36),
.IPCORE_CLK(IPCORE_CLK),
.Q(write_reg_d_k),
.S({u_lms_pcore_axi_lite_inst_n_5,u_lms_pcore_axi_lite_inst_n_6,u_lms_pcore_axi_lite_inst_n_7,u_lms_pcore_axi_lite_inst_n_8}),
.cop_dut_enable(cop_dut_enable),
.filter_sum(filter_sum),
.mul_temp_16(\u_LMS/mul_temp_16 ),
.\write_reg_d_k_reg[11] ({u_lms_pcore_axi_lite_inst_n_24,u_lms_pcore_axi_lite_inst_n_25,u_lms_pcore_axi_lite_inst_n_26,u_lms_pcore_axi_lite_inst_n_27}),
.\write_reg_d_k_reg[3] ({u_lms_pcore_axi_lite_inst_n_37,u_lms_pcore_axi_lite_inst_n_38,u_lms_pcore_axi_lite_inst_n_39}),
.\write_reg_d_k_reg[3]_0 ({u_lms_pcore_axi_lite_inst_n_32,u_lms_pcore_axi_lite_inst_n_33,u_lms_pcore_axi_lite_inst_n_34,u_lms_pcore_axi_lite_inst_n_35}),
.\write_reg_d_k_reg[7] ({u_lms_pcore_axi_lite_inst_n_28,u_lms_pcore_axi_lite_inst_n_29,u_lms_pcore_axi_lite_inst_n_30,u_lms_pcore_axi_lite_inst_n_31}),
.\write_reg_x_k_reg[15] (write_reg_x_k));
endmodule
(* ORIG_REF_NAME = "lms_pcore_addr_decoder" *)
module ip_design_lms_pcore_0_0_lms_pcore_addr_decoder
(read_reg_cop_out_ready,
write_reg_axi_enable,
S,
Q,
\sync_reg_e_k_reg[11]_0 ,
\sync_reg_e_k_reg[7]_0 ,
\sync_reg_e_k_reg[3]_0 ,
DI,
ARG__29,
\cp_controller_cpstate_reg[0] ,
ARG__28,
\AXI4_Lite_RDATA_tmp_reg[31] ,
strobe_sw_cop_in_strobe,
AXI4_Lite_ACLK,
AR,
cop_out_ready,
\wdata_reg[0] ,
filter_sum,
mul_temp_16,
cp_controller_cpstate,
E,
\wdata_reg[15] ,
wr_enb_1_reg);
output read_reg_cop_out_ready;
output write_reg_axi_enable;
output [3:0]S;
output [14:0]Q;
output [3:0]\sync_reg_e_k_reg[11]_0 ;
output [3:0]\sync_reg_e_k_reg[7]_0 ;
output [3:0]\sync_reg_e_k_reg[3]_0 ;
output [0:0]DI;
output [2:0]ARG__29;
output \cp_controller_cpstate_reg[0] ;
output [15:0]ARG__28;
output [15:0]\AXI4_Lite_RDATA_tmp_reg[31] ;
input strobe_sw_cop_in_strobe;
input AXI4_Lite_ACLK;
input [0:0]AR;
input cop_out_ready;
input \wdata_reg[0] ;
input [15:0]filter_sum;
input [15:0]mul_temp_16;
input [1:0]cp_controller_cpstate;
input [0:0]E;
input [15:0]\wdata_reg[15] ;
input [0:0]wr_enb_1_reg;
wire [0:0]AR;
wire [15:0]ARG__28;
wire [2:0]ARG__29;
wire AXI4_Lite_ACLK;
wire [15:0]\AXI4_Lite_RDATA_tmp_reg[31] ;
wire [0:0]DI;
wire [0:0]E;
wire [14:0]Q;
wire [3:0]S;
wire cop_out_ready;
wire [1:0]cp_controller_cpstate;
wire \cp_controller_cpstate_reg[0] ;
wire [15:0]filter_sum;
wire in_strobe;
wire [15:0]mul_temp_16;
wire read_reg_cop_out_ready;
wire strobe_sw_cop_in_strobe;
wire [3:0]\sync_reg_e_k_reg[11]_0 ;
wire [3:0]\sync_reg_e_k_reg[3]_0 ;
wire [3:0]\sync_reg_e_k_reg[7]_0 ;
wire \wdata_reg[0] ;
wire [15:0]\wdata_reg[15] ;
wire [0:0]wr_enb_1_reg;
wire write_reg_axi_enable;
wire [15:15]write_reg_d_k;
LUT1 #(
.INIT(2'h1))
ARG_carry__0_i_1
(.I0(mul_temp_16[3]),
.O(DI));
LUT1 #(
.INIT(2'h1))
ARG_carry_i_1
(.I0(mul_temp_16[1]),
.O(ARG__29[2]));
LUT1 #(
.INIT(2'h1))
ARG_carry_i_2
(.I0(mul_temp_16[0]),
.O(ARG__29[1]));
LUT1 #(
.INIT(2'h1))
ARG_carry_i_3
(.I0(mul_temp_16[3]),
.O(ARG__29[0]));
LUT4 #(
.INIT(16'h0F20))
\cp_controller_cpstate[0]_i_1
(.I0(in_strobe),
.I1(cp_controller_cpstate[1]),
.I2(write_reg_axi_enable),
.I3(cp_controller_cpstate[0]),
.O(\cp_controller_cpstate_reg[0] ));
FDCE read_reg_cop_out_ready_reg
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.CLR(AR),
.D(cop_out_ready),
.Q(read_reg_cop_out_ready));
FDCE strobe_reg_cop_in_strobe_reg
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.CLR(AR),
.D(strobe_sw_cop_in_strobe),
.Q(in_strobe));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__0_i_1
(.I0(Q[7]),
.I1(filter_sum[7]),
.O(\sync_reg_e_k_reg[7]_0 [3]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__0_i_2
(.I0(Q[6]),
.I1(filter_sum[6]),
.O(\sync_reg_e_k_reg[7]_0 [2]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__0_i_3
(.I0(Q[5]),
.I1(filter_sum[5]),
.O(\sync_reg_e_k_reg[7]_0 [1]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__0_i_4
(.I0(Q[4]),
.I1(filter_sum[4]),
.O(\sync_reg_e_k_reg[7]_0 [0]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__1_i_1
(.I0(Q[11]),
.I1(filter_sum[11]),
.O(\sync_reg_e_k_reg[11]_0 [3]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__1_i_2
(.I0(Q[10]),
.I1(filter_sum[10]),
.O(\sync_reg_e_k_reg[11]_0 [2]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__1_i_3
(.I0(Q[9]),
.I1(filter_sum[9]),
.O(\sync_reg_e_k_reg[11]_0 [1]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__1_i_4
(.I0(Q[8]),
.I1(filter_sum[8]),
.O(\sync_reg_e_k_reg[11]_0 [0]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__2_i_1
(.I0(write_reg_d_k),
.I1(filter_sum[15]),
.O(S[3]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__2_i_2
(.I0(Q[14]),
.I1(filter_sum[14]),
.O(S[2]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__2_i_3
(.I0(Q[13]),
.I1(filter_sum[13]),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry__2_i_4
(.I0(Q[12]),
.I1(filter_sum[12]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry_i_1
(.I0(Q[3]),
.I1(filter_sum[3]),
.O(\sync_reg_e_k_reg[3]_0 [3]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry_i_2
(.I0(Q[2]),
.I1(filter_sum[2]),
.O(\sync_reg_e_k_reg[3]_0 [2]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry_i_3
(.I0(Q[1]),
.I1(filter_sum[1]),
.O(\sync_reg_e_k_reg[3]_0 [1]));
LUT2 #(
.INIT(4'h9))
sub_temp_carry_i_4
(.I0(Q[0]),
.I1(filter_sum[0]),
.O(\sync_reg_e_k_reg[3]_0 [0]));
FDCE \sync_reg_e_k_reg[0]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[0]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [0]));
FDCE \sync_reg_e_k_reg[10]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[10]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [10]));
FDCE \sync_reg_e_k_reg[11]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[11]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [11]));
FDCE \sync_reg_e_k_reg[12]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[12]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [12]));
FDCE \sync_reg_e_k_reg[13]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[13]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [13]));
FDCE \sync_reg_e_k_reg[14]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[14]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [14]));
FDCE \sync_reg_e_k_reg[15]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[15]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [15]));
FDCE \sync_reg_e_k_reg[1]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[1]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [1]));
FDCE \sync_reg_e_k_reg[2]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[2]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [2]));
FDCE \sync_reg_e_k_reg[3]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[3]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [3]));
FDCE \sync_reg_e_k_reg[4]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[4]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [4]));
FDCE \sync_reg_e_k_reg[5]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[5]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [5]));
FDCE \sync_reg_e_k_reg[6]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[6]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [6]));
FDCE \sync_reg_e_k_reg[7]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[7]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [7]));
FDCE \sync_reg_e_k_reg[8]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[8]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [8]));
FDCE \sync_reg_e_k_reg[9]
(.C(AXI4_Lite_ACLK),
.CE(in_strobe),
.CLR(AR),
.D(mul_temp_16[9]),
.Q(\AXI4_Lite_RDATA_tmp_reg[31] [9]));
FDPE write_reg_axi_enable_reg
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.D(\wdata_reg[0] ),
.PRE(AR),
.Q(write_reg_axi_enable));
FDCE \write_reg_d_k_reg[0]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [0]),
.Q(Q[0]));
FDCE \write_reg_d_k_reg[10]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [10]),
.Q(Q[10]));
FDCE \write_reg_d_k_reg[11]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [11]),
.Q(Q[11]));
FDCE \write_reg_d_k_reg[12]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [12]),
.Q(Q[12]));
FDCE \write_reg_d_k_reg[13]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [13]),
.Q(Q[13]));
FDCE \write_reg_d_k_reg[14]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [14]),
.Q(Q[14]));
FDCE \write_reg_d_k_reg[15]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [15]),
.Q(write_reg_d_k));
FDCE \write_reg_d_k_reg[1]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [1]),
.Q(Q[1]));
FDCE \write_reg_d_k_reg[2]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [2]),
.Q(Q[2]));
FDCE \write_reg_d_k_reg[3]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [3]),
.Q(Q[3]));
FDCE \write_reg_d_k_reg[4]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [4]),
.Q(Q[4]));
FDCE \write_reg_d_k_reg[5]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [5]),
.Q(Q[5]));
FDCE \write_reg_d_k_reg[6]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [6]),
.Q(Q[6]));
FDCE \write_reg_d_k_reg[7]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [7]),
.Q(Q[7]));
FDCE \write_reg_d_k_reg[8]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [8]),
.Q(Q[8]));
FDCE \write_reg_d_k_reg[9]
(.C(AXI4_Lite_ACLK),
.CE(wr_enb_1_reg),
.CLR(AR),
.D(\wdata_reg[15] [9]),
.Q(Q[9]));
FDCE \write_reg_x_k_reg[0]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [0]),
.Q(ARG__28[0]));
FDCE \write_reg_x_k_reg[10]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [10]),
.Q(ARG__28[10]));
FDCE \write_reg_x_k_reg[11]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [11]),
.Q(ARG__28[11]));
FDCE \write_reg_x_k_reg[12]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [12]),
.Q(ARG__28[12]));
FDCE \write_reg_x_k_reg[13]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [13]),
.Q(ARG__28[13]));
FDCE \write_reg_x_k_reg[14]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [14]),
.Q(ARG__28[14]));
FDCE \write_reg_x_k_reg[15]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [15]),
.Q(ARG__28[15]));
FDCE \write_reg_x_k_reg[1]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [1]),
.Q(ARG__28[1]));
FDCE \write_reg_x_k_reg[2]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [2]),
.Q(ARG__28[2]));
FDCE \write_reg_x_k_reg[3]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [3]),
.Q(ARG__28[3]));
FDCE \write_reg_x_k_reg[4]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [4]),
.Q(ARG__28[4]));
FDCE \write_reg_x_k_reg[5]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [5]),
.Q(ARG__28[5]));
FDCE \write_reg_x_k_reg[6]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [6]),
.Q(ARG__28[6]));
FDCE \write_reg_x_k_reg[7]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [7]),
.Q(ARG__28[7]));
FDCE \write_reg_x_k_reg[8]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [8]),
.Q(ARG__28[8]));
FDCE \write_reg_x_k_reg[9]
(.C(AXI4_Lite_ACLK),
.CE(E),
.CLR(AR),
.D(\wdata_reg[15] [9]),
.Q(ARG__28[9]));
endmodule
(* ORIG_REF_NAME = "lms_pcore_axi_lite" *)
module ip_design_lms_pcore_0_0_lms_pcore_axi_lite
(write_reg_axi_enable_reg,
AXI4_Lite_RVALID,
write_reg_axi_enable,
AXI4_Lite_WREADY,
AXI4_Lite_BVALID,
S,
Q,
\sync_reg_e_k_reg[11] ,
\sync_reg_e_k_reg[7] ,
\sync_reg_e_k_reg[3] ,
DI,
ARG__29,
\cp_controller_cpstate_reg[0] ,
ARG__28,
AXI4_Lite_RDATA,
AXI4_Lite_AWREADY,
AXI4_Lite_ARREADY,
AXI4_Lite_ACLK,
cop_out_ready,
AXI4_Lite_AWVALID,
AXI4_Lite_WVALID,
AXI4_Lite_ARESETN,
IPCORE_RESETN,
filter_sum,
mul_temp_16,
cp_controller_cpstate,
AXI4_Lite_WDATA,
AXI4_Lite_AWADDR,
AXI4_Lite_BREADY,
AXI4_Lite_ARVALID,
AXI4_Lite_ARADDR,
AXI4_Lite_RREADY);
output write_reg_axi_enable_reg;
output AXI4_Lite_RVALID;
output write_reg_axi_enable;
output AXI4_Lite_WREADY;
output AXI4_Lite_BVALID;
output [3:0]S;
output [14:0]Q;
output [3:0]\sync_reg_e_k_reg[11] ;
output [3:0]\sync_reg_e_k_reg[7] ;
output [3:0]\sync_reg_e_k_reg[3] ;
output [0:0]DI;
output [2:0]ARG__29;
output \cp_controller_cpstate_reg[0] ;
output [15:0]ARG__28;
output [15:0]AXI4_Lite_RDATA;
output AXI4_Lite_AWREADY;
output AXI4_Lite_ARREADY;
input AXI4_Lite_ACLK;
input cop_out_ready;
input AXI4_Lite_AWVALID;
input AXI4_Lite_WVALID;
input AXI4_Lite_ARESETN;
input IPCORE_RESETN;
input [15:0]filter_sum;
input [15:0]mul_temp_16;
input [1:0]cp_controller_cpstate;
input [15:0]AXI4_Lite_WDATA;
input [13:0]AXI4_Lite_AWADDR;
input AXI4_Lite_BREADY;
input AXI4_Lite_ARVALID;
input [13:0]AXI4_Lite_ARADDR;
input AXI4_Lite_RREADY;
wire [15:0]ARG__28;
wire [2:0]ARG__29;
wire AXI4_Lite_ACLK;
wire [13:0]AXI4_Lite_ARADDR;
wire AXI4_Lite_ARESETN;
wire AXI4_Lite_ARREADY;
wire AXI4_Lite_ARVALID;
wire [13:0]AXI4_Lite_AWADDR;
wire AXI4_Lite_AWREADY;
wire AXI4_Lite_AWVALID;
wire AXI4_Lite_BREADY;
wire AXI4_Lite_BVALID;
wire [15:0]AXI4_Lite_RDATA;
wire AXI4_Lite_RREADY;
wire AXI4_Lite_RVALID;
wire [15:0]AXI4_Lite_WDATA;
wire AXI4_Lite_WREADY;
wire AXI4_Lite_WVALID;
wire [0:0]DI;
wire IPCORE_RESETN;
wire [14:0]Q;
wire [3:0]S;
wire cop_out_ready;
wire [1:0]cp_controller_cpstate;
wire \cp_controller_cpstate_reg[0] ;
wire [15:0]filter_sum;
wire [15:0]mul_temp_16;
wire read_reg_cop_out_ready;
wire reg_enb_d_k;
wire reg_enb_x_k;
wire strobe_sw_cop_in_strobe;
wire [15:0]sync_reg_e_k;
wire [3:0]\sync_reg_e_k_reg[11] ;
wire [3:0]\sync_reg_e_k_reg[3] ;
wire [3:0]\sync_reg_e_k_reg[7] ;
wire [0:0]top_data_write;
wire u_lms_pcore_axi_lite_module_inst_n_10;
wire u_lms_pcore_axi_lite_module_inst_n_11;
wire u_lms_pcore_axi_lite_module_inst_n_12;
wire u_lms_pcore_axi_lite_module_inst_n_13;
wire u_lms_pcore_axi_lite_module_inst_n_14;
wire u_lms_pcore_axi_lite_module_inst_n_15;
wire u_lms_pcore_axi_lite_module_inst_n_16;
wire u_lms_pcore_axi_lite_module_inst_n_17;
wire u_lms_pcore_axi_lite_module_inst_n_18;
wire u_lms_pcore_axi_lite_module_inst_n_19;
wire u_lms_pcore_axi_lite_module_inst_n_4;
wire u_lms_pcore_axi_lite_module_inst_n_5;
wire u_lms_pcore_axi_lite_module_inst_n_6;
wire u_lms_pcore_axi_lite_module_inst_n_7;
wire u_lms_pcore_axi_lite_module_inst_n_8;
wire u_lms_pcore_axi_lite_module_inst_n_9;
wire write_reg_axi_enable;
wire write_reg_axi_enable_reg;
ip_design_lms_pcore_0_0_lms_pcore_addr_decoder u_lms_pcore_addr_decoder_inst
(.AR(write_reg_axi_enable_reg),
.ARG__28(ARG__28),
.ARG__29(ARG__29),
.AXI4_Lite_ACLK(AXI4_Lite_ACLK),
.\AXI4_Lite_RDATA_tmp_reg[31] (sync_reg_e_k),
.DI(DI),
.E(reg_enb_x_k),
.Q(Q),
.S(S),
.cop_out_ready(cop_out_ready),
.cp_controller_cpstate(cp_controller_cpstate),
.\cp_controller_cpstate_reg[0] (\cp_controller_cpstate_reg[0] ),
.filter_sum(filter_sum),
.mul_temp_16(mul_temp_16),
.read_reg_cop_out_ready(read_reg_cop_out_ready),
.strobe_sw_cop_in_strobe(strobe_sw_cop_in_strobe),
.\sync_reg_e_k_reg[11]_0 (\sync_reg_e_k_reg[11] ),
.\sync_reg_e_k_reg[3]_0 (\sync_reg_e_k_reg[3] ),
.\sync_reg_e_k_reg[7]_0 (\sync_reg_e_k_reg[7] ),
.\wdata_reg[0] (u_lms_pcore_axi_lite_module_inst_n_4),
.\wdata_reg[15] ({u_lms_pcore_axi_lite_module_inst_n_5,u_lms_pcore_axi_lite_module_inst_n_6,u_lms_pcore_axi_lite_module_inst_n_7,u_lms_pcore_axi_lite_module_inst_n_8,u_lms_pcore_axi_lite_module_inst_n_9,u_lms_pcore_axi_lite_module_inst_n_10,u_lms_pcore_axi_lite_module_inst_n_11,u_lms_pcore_axi_lite_module_inst_n_12,u_lms_pcore_axi_lite_module_inst_n_13,u_lms_pcore_axi_lite_module_inst_n_14,u_lms_pcore_axi_lite_module_inst_n_15,u_lms_pcore_axi_lite_module_inst_n_16,u_lms_pcore_axi_lite_module_inst_n_17,u_lms_pcore_axi_lite_module_inst_n_18,u_lms_pcore_axi_lite_module_inst_n_19,top_data_write}),
.wr_enb_1_reg(reg_enb_d_k),
.write_reg_axi_enable(write_reg_axi_enable));
ip_design_lms_pcore_0_0_lms_pcore_axi_lite_module u_lms_pcore_axi_lite_module_inst
(.AXI4_Lite_ACLK(AXI4_Lite_ACLK),
.AXI4_Lite_ARADDR(AXI4_Lite_ARADDR),
.AXI4_Lite_ARESETN(AXI4_Lite_ARESETN),
.AXI4_Lite_ARREADY(AXI4_Lite_ARREADY),
.AXI4_Lite_ARVALID(AXI4_Lite_ARVALID),
.AXI4_Lite_AWADDR(AXI4_Lite_AWADDR),
.AXI4_Lite_AWREADY(AXI4_Lite_AWREADY),
.AXI4_Lite_AWVALID(AXI4_Lite_AWVALID),
.AXI4_Lite_BREADY(AXI4_Lite_BREADY),
.AXI4_Lite_BVALID(AXI4_Lite_BVALID),
.AXI4_Lite_RDATA(AXI4_Lite_RDATA),
.AXI4_Lite_RREADY(AXI4_Lite_RREADY),
.AXI4_Lite_RVALID(AXI4_Lite_RVALID),
.AXI4_Lite_WDATA(AXI4_Lite_WDATA),
.AXI4_Lite_WREADY(AXI4_Lite_WREADY),
.AXI4_Lite_WVALID(AXI4_Lite_WVALID),
.E(reg_enb_x_k),
.IPCORE_RESETN(IPCORE_RESETN),
.Q({u_lms_pcore_axi_lite_module_inst_n_5,u_lms_pcore_axi_lite_module_inst_n_6,u_lms_pcore_axi_lite_module_inst_n_7,u_lms_pcore_axi_lite_module_inst_n_8,u_lms_pcore_axi_lite_module_inst_n_9,u_lms_pcore_axi_lite_module_inst_n_10,u_lms_pcore_axi_lite_module_inst_n_11,u_lms_pcore_axi_lite_module_inst_n_12,u_lms_pcore_axi_lite_module_inst_n_13,u_lms_pcore_axi_lite_module_inst_n_14,u_lms_pcore_axi_lite_module_inst_n_15,u_lms_pcore_axi_lite_module_inst_n_16,u_lms_pcore_axi_lite_module_inst_n_17,u_lms_pcore_axi_lite_module_inst_n_18,u_lms_pcore_axi_lite_module_inst_n_19,top_data_write}),
.read_reg_cop_out_ready(read_reg_cop_out_ready),
.strobe_sw_cop_in_strobe(strobe_sw_cop_in_strobe),
.\sync_reg_e_k_reg[15] (sync_reg_e_k),
.write_reg_axi_enable(write_reg_axi_enable),
.write_reg_axi_enable_reg(write_reg_axi_enable_reg),
.write_reg_axi_enable_reg_0(u_lms_pcore_axi_lite_module_inst_n_4),
.\write_reg_d_k_reg[15] (reg_enb_d_k));
endmodule
(* ORIG_REF_NAME = "lms_pcore_axi_lite_module" *)
module ip_design_lms_pcore_0_0_lms_pcore_axi_lite_module
(AXI4_Lite_RVALID,
write_reg_axi_enable_reg,
AXI4_Lite_WREADY,
AXI4_Lite_BVALID,
write_reg_axi_enable_reg_0,
Q,
AXI4_Lite_RDATA,
AXI4_Lite_AWREADY,
strobe_sw_cop_in_strobe,
\write_reg_d_k_reg[15] ,
E,
AXI4_Lite_ARREADY,
AXI4_Lite_ACLK,
AXI4_Lite_AWVALID,
AXI4_Lite_WVALID,
AXI4_Lite_ARESETN,
IPCORE_RESETN,
write_reg_axi_enable,
AXI4_Lite_WDATA,
AXI4_Lite_AWADDR,
AXI4_Lite_BREADY,
\sync_reg_e_k_reg[15] ,
AXI4_Lite_ARVALID,
AXI4_Lite_ARADDR,
read_reg_cop_out_ready,
AXI4_Lite_RREADY);
output AXI4_Lite_RVALID;
output write_reg_axi_enable_reg;
output AXI4_Lite_WREADY;
output AXI4_Lite_BVALID;
output write_reg_axi_enable_reg_0;
output [15:0]Q;
output [15:0]AXI4_Lite_RDATA;
output AXI4_Lite_AWREADY;
output strobe_sw_cop_in_strobe;
output [0:0]\write_reg_d_k_reg[15] ;
output [0:0]E;
output AXI4_Lite_ARREADY;
input AXI4_Lite_ACLK;
input AXI4_Lite_AWVALID;
input AXI4_Lite_WVALID;
input AXI4_Lite_ARESETN;
input IPCORE_RESETN;
input write_reg_axi_enable;
input [15:0]AXI4_Lite_WDATA;
input [13:0]AXI4_Lite_AWADDR;
input AXI4_Lite_BREADY;
input [15:0]\sync_reg_e_k_reg[15] ;
input AXI4_Lite_ARVALID;
input [13:0]AXI4_Lite_ARADDR;
input read_reg_cop_out_ready;
input AXI4_Lite_RREADY;
wire AXI4_Lite_ACLK;
wire [13:0]AXI4_Lite_ARADDR;
wire AXI4_Lite_ARESETN;
wire AXI4_Lite_ARREADY;
wire AXI4_Lite_ARVALID;
wire [13:0]AXI4_Lite_AWADDR;
wire AXI4_Lite_AWREADY;
wire AXI4_Lite_AWVALID;
wire AXI4_Lite_BREADY;
wire AXI4_Lite_BVALID;
wire [15:0]AXI4_Lite_RDATA;
wire \AXI4_Lite_RDATA_tmp[0]_i_2_n_0 ;
wire \AXI4_Lite_RDATA_tmp[0]_i_3_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_10_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_11_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_12_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ;
wire \AXI4_Lite_RDATA_tmp[31]_i_9_n_0 ;
wire AXI4_Lite_RREADY;
wire AXI4_Lite_RVALID;
wire [15:0]AXI4_Lite_WDATA;
wire AXI4_Lite_WREADY;
wire AXI4_Lite_WVALID;
wire [0:0]E;
wire IPCORE_RESETN;
wire [15:0]Q;
wire aw_transfer;
wire \axi_lite_rstate[0]_i_1_n_0 ;
wire [1:0]axi_lite_wstate;
wire \axi_lite_wstate[0]_i_1_n_0 ;
wire \axi_lite_wstate_next_inferred__1/i__n_0 ;
wire [31:0]data_read;
wire read_reg_cop_out_ready;
wire reset;
wire [13:0]sel0;
wire soft_reset;
wire soft_reset_i_2_n_0;
wire soft_reset_i_3_n_0;
wire soft_reset_i_4_n_0;
wire strobe_reg_cop_in_strobe_i_3_n_0;
wire strobe_sw;
wire strobe_sw_cop_in_strobe;
wire [15:0]\sync_reg_e_k_reg[15] ;
wire top_rd_enb;
wire top_wr_enb;
wire w_transfer;
wire write_reg_axi_enable;
wire write_reg_axi_enable_i_2_n_0;
wire write_reg_axi_enable_reg;
wire write_reg_axi_enable_reg_0;
wire [0:0]\write_reg_d_k_reg[15] ;
LUT1 #(
.INIT(2'h1))
AXI4_Lite_ARREADY_INST_0
(.I0(AXI4_Lite_RVALID),
.O(AXI4_Lite_ARREADY));
LUT2 #(
.INIT(4'h1))
AXI4_Lite_AWREADY_INST_0
(.I0(axi_lite_wstate[0]),
.I1(axi_lite_wstate[1]),
.O(AXI4_Lite_AWREADY));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
AXI4_Lite_BVALID_INST_0
(.I0(axi_lite_wstate[1]),
.I1(axi_lite_wstate[0]),
.O(AXI4_Lite_BVALID));
LUT6 #(
.INIT(64'h00008CCC00008000))
\AXI4_Lite_RDATA_tmp[0]_i_1
(.I0(\sync_reg_e_k_reg[15] [0]),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[0]_i_2_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I5(\AXI4_Lite_RDATA_tmp[0]_i_3_n_0 ),
.O(data_read[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h000ACC0A))
\AXI4_Lite_RDATA_tmp[0]_i_2
(.I0(sel0[6]),
.I1(AXI4_Lite_ARADDR[6]),
.I2(sel0[0]),
.I3(AXI4_Lite_ARVALID),
.I4(AXI4_Lite_ARADDR[0]),
.O(\AXI4_Lite_RDATA_tmp[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000B80000000000))
\AXI4_Lite_RDATA_tmp[0]_i_3
(.I0(AXI4_Lite_ARADDR[0]),
.I1(AXI4_Lite_ARVALID),
.I2(sel0[0]),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I5(read_reg_cop_out_ready),
.O(\AXI4_Lite_RDATA_tmp[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[10]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [10]),
.O(data_read[10]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[11]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [11]),
.O(data_read[11]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[12]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [12]),
.O(data_read[12]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[13]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [13]),
.O(data_read[13]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[14]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [14]),
.O(data_read[14]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[1]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [1]),
.O(data_read[1]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[2]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [2]),
.O(data_read[2]));
LUT2 #(
.INIT(4'h2))
\AXI4_Lite_RDATA_tmp[31]_i_1
(.I0(AXI4_Lite_ARVALID),
.I1(AXI4_Lite_RVALID),
.O(top_rd_enb));
LUT5 #(
.INIT(32'hFFEEF0EE))
\AXI4_Lite_RDATA_tmp[31]_i_10
(.I0(sel0[5]),
.I1(sel0[4]),
.I2(AXI4_Lite_ARADDR[5]),
.I3(AXI4_Lite_ARVALID),
.I4(AXI4_Lite_ARADDR[4]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_10_n_0 ));
LUT5 #(
.INIT(32'hFFEEF0EE))
\AXI4_Lite_RDATA_tmp[31]_i_11
(.I0(sel0[3]),
.I1(sel0[2]),
.I2(AXI4_Lite_ARADDR[3]),
.I3(AXI4_Lite_ARVALID),
.I4(AXI4_Lite_ARADDR[2]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_11_n_0 ));
LUT5 #(
.INIT(32'hFFEEF0EE))
\AXI4_Lite_RDATA_tmp[31]_i_12
(.I0(sel0[9]),
.I1(sel0[8]),
.I2(AXI4_Lite_ARADDR[9]),
.I3(AXI4_Lite_ARVALID),
.I4(AXI4_Lite_ARADDR[8]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_12_n_0 ));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[31]_i_2
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [15]),
.O(data_read[31]));
LUT1 #(
.INIT(2'h1))
\AXI4_Lite_RDATA_tmp[31]_i_3
(.I0(AXI4_Lite_ARESETN),
.O(reset));
LUT6 #(
.INIT(64'hFFFFEFEFFFFAEFEA))
\AXI4_Lite_RDATA_tmp[31]_i_4
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_9_n_0 ),
.I1(AXI4_Lite_ARADDR[10]),
.I2(AXI4_Lite_ARVALID),
.I3(sel0[10]),
.I4(AXI4_Lite_ARADDR[11]),
.I5(sel0[11]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hB8))
\AXI4_Lite_RDATA_tmp[31]_i_5
(.I0(AXI4_Lite_ARADDR[1]),
.I1(AXI4_Lite_ARVALID),
.I2(sel0[1]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\AXI4_Lite_RDATA_tmp[31]_i_6
(.I0(AXI4_Lite_ARADDR[6]),
.I1(AXI4_Lite_ARVALID),
.I2(sel0[6]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\AXI4_Lite_RDATA_tmp[31]_i_7
(.I0(AXI4_Lite_ARADDR[0]),
.I1(AXI4_Lite_ARVALID),
.I2(sel0[0]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ));
LUT5 #(
.INIT(32'h00011101))
\AXI4_Lite_RDATA_tmp[31]_i_8
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_10_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_11_n_0 ),
.I2(sel0[7]),
.I3(AXI4_Lite_ARVALID),
.I4(AXI4_Lite_ARADDR[7]),
.O(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFBBFCB8))
\AXI4_Lite_RDATA_tmp[31]_i_9
(.I0(AXI4_Lite_ARADDR[13]),
.I1(AXI4_Lite_ARVALID),
.I2(sel0[13]),
.I3(AXI4_Lite_ARADDR[12]),
.I4(sel0[12]),
.I5(\AXI4_Lite_RDATA_tmp[31]_i_12_n_0 ),
.O(\AXI4_Lite_RDATA_tmp[31]_i_9_n_0 ));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[3]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [3]),
.O(data_read[3]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[4]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [4]),
.O(data_read[4]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[5]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [5]),
.O(data_read[5]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[6]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [6]),
.O(data_read[6]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[7]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [7]),
.O(data_read[7]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[8]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [8]),
.O(data_read[8]));
LUT6 #(
.INIT(64'h0040000000000000))
\AXI4_Lite_RDATA_tmp[9]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I5(\sync_reg_e_k_reg[15] [9]),
.O(data_read[9]));
FDCE \AXI4_Lite_RDATA_tmp_reg[0]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[0]),
.Q(AXI4_Lite_RDATA[0]));
FDCE \AXI4_Lite_RDATA_tmp_reg[10]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[10]),
.Q(AXI4_Lite_RDATA[10]));
FDCE \AXI4_Lite_RDATA_tmp_reg[11]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[11]),
.Q(AXI4_Lite_RDATA[11]));
FDCE \AXI4_Lite_RDATA_tmp_reg[12]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[12]),
.Q(AXI4_Lite_RDATA[12]));
FDCE \AXI4_Lite_RDATA_tmp_reg[13]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[13]),
.Q(AXI4_Lite_RDATA[13]));
FDCE \AXI4_Lite_RDATA_tmp_reg[14]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[14]),
.Q(AXI4_Lite_RDATA[14]));
FDCE \AXI4_Lite_RDATA_tmp_reg[1]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[1]),
.Q(AXI4_Lite_RDATA[1]));
FDCE \AXI4_Lite_RDATA_tmp_reg[2]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[2]),
.Q(AXI4_Lite_RDATA[2]));
FDCE \AXI4_Lite_RDATA_tmp_reg[31]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[31]),
.Q(AXI4_Lite_RDATA[15]));
FDCE \AXI4_Lite_RDATA_tmp_reg[3]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[3]),
.Q(AXI4_Lite_RDATA[3]));
FDCE \AXI4_Lite_RDATA_tmp_reg[4]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[4]),
.Q(AXI4_Lite_RDATA[4]));
FDCE \AXI4_Lite_RDATA_tmp_reg[5]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[5]),
.Q(AXI4_Lite_RDATA[5]));
FDCE \AXI4_Lite_RDATA_tmp_reg[6]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[6]),
.Q(AXI4_Lite_RDATA[6]));
FDCE \AXI4_Lite_RDATA_tmp_reg[7]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[7]),
.Q(AXI4_Lite_RDATA[7]));
FDCE \AXI4_Lite_RDATA_tmp_reg[8]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[8]),
.Q(AXI4_Lite_RDATA[8]));
FDCE \AXI4_Lite_RDATA_tmp_reg[9]
(.C(AXI4_Lite_ACLK),
.CE(top_rd_enb),
.CLR(reset),
.D(data_read[9]),
.Q(AXI4_Lite_RDATA[9]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
AXI4_Lite_WREADY_INST_0
(.I0(axi_lite_wstate[0]),
.I1(axi_lite_wstate[1]),
.O(AXI4_Lite_WREADY));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h74))
\axi_lite_rstate[0]_i_1
(.I0(AXI4_Lite_RREADY),
.I1(AXI4_Lite_RVALID),
.I2(AXI4_Lite_ARVALID),
.O(\axi_lite_rstate[0]_i_1_n_0 ));
FDCE \axi_lite_rstate_reg[0]
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.CLR(reset),
.D(\axi_lite_rstate[0]_i_1_n_0 ),
.Q(AXI4_Lite_RVALID));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h002E))
\axi_lite_wstate[0]_i_1
(.I0(AXI4_Lite_AWVALID),
.I1(axi_lite_wstate[0]),
.I2(AXI4_Lite_WVALID),
.I3(axi_lite_wstate[1]),
.O(\axi_lite_wstate[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0838))
\axi_lite_wstate_next_inferred__1/i_
(.I0(AXI4_Lite_WVALID),
.I1(axi_lite_wstate[0]),
.I2(axi_lite_wstate[1]),
.I3(AXI4_Lite_BREADY),
.O(\axi_lite_wstate_next_inferred__1/i__n_0 ));
FDCE \axi_lite_wstate_reg[0]
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.CLR(reset),
.D(\axi_lite_wstate[0]_i_1_n_0 ),
.Q(axi_lite_wstate[0]));
FDCE \axi_lite_wstate_reg[1]
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.CLR(reset),
.D(\axi_lite_wstate_next_inferred__1/i__n_0 ),
.Q(axi_lite_wstate[1]));
LUT6 #(
.INIT(64'h0000000200000000))
soft_reset_i_1
(.I0(soft_reset_i_2_n_0),
.I1(sel0[1]),
.I2(sel0[0]),
.I3(sel0[7]),
.I4(sel0[6]),
.I5(soft_reset_i_3_n_0),
.O(strobe_sw));
LUT4 #(
.INIT(16'h0001))
soft_reset_i_2
(.I0(sel0[13]),
.I1(sel0[12]),
.I2(sel0[11]),
.I3(sel0[10]),
.O(soft_reset_i_2_n_0));
LUT5 #(
.INIT(32'h00010000))
soft_reset_i_3
(.I0(sel0[2]),
.I1(sel0[3]),
.I2(sel0[8]),
.I3(sel0[9]),
.I4(soft_reset_i_4_n_0),
.O(soft_reset_i_3_n_0));
LUT4 #(
.INIT(16'h0008))
soft_reset_i_4
(.I0(top_wr_enb),
.I1(Q[0]),
.I2(sel0[5]),
.I3(sel0[4]),
.O(soft_reset_i_4_n_0));
FDCE soft_reset_reg
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.CLR(reset),
.D(strobe_sw),
.Q(soft_reset));
LUT6 #(
.INIT(64'h0000000020000000))
strobe_reg_cop_in_strobe_i_1
(.I0(Q[0]),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I2(strobe_reg_cop_in_strobe_i_3_n_0),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I4(top_wr_enb),
.I5(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.O(strobe_sw_cop_in_strobe));
LUT3 #(
.INIT(8'hDF))
strobe_reg_cop_in_strobe_i_2
(.I0(AXI4_Lite_ARESETN),
.I1(soft_reset),
.I2(IPCORE_RESETN),
.O(write_reg_axi_enable_reg));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h000ACC0A))
strobe_reg_cop_in_strobe_i_3
(.I0(sel0[1]),
.I1(AXI4_Lite_ARADDR[1]),
.I2(sel0[0]),
.I3(AXI4_Lite_ARVALID),
.I4(AXI4_Lite_ARADDR[0]),
.O(strobe_reg_cop_in_strobe_i_3_n_0));
LUT3 #(
.INIT(8'h02))
\waddr[15]_i_1
(.I0(AXI4_Lite_AWVALID),
.I1(axi_lite_wstate[1]),
.I2(axi_lite_wstate[0]),
.O(aw_transfer));
FDCE \waddr_reg[10]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[8]),
.Q(sel0[8]));
FDCE \waddr_reg[11]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[9]),
.Q(sel0[9]));
FDCE \waddr_reg[12]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[10]),
.Q(sel0[10]));
FDCE \waddr_reg[13]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[11]),
.Q(sel0[11]));
FDCE \waddr_reg[14]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[12]),
.Q(sel0[12]));
FDCE \waddr_reg[15]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[13]),
.Q(sel0[13]));
FDCE \waddr_reg[2]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[0]),
.Q(sel0[0]));
FDCE \waddr_reg[3]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[1]),
.Q(sel0[1]));
FDCE \waddr_reg[4]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[2]),
.Q(sel0[2]));
FDCE \waddr_reg[5]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[3]),
.Q(sel0[3]));
FDCE \waddr_reg[6]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[4]),
.Q(sel0[4]));
FDCE \waddr_reg[7]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[5]),
.Q(sel0[5]));
FDCE \waddr_reg[8]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[6]),
.Q(sel0[6]));
FDCE \waddr_reg[9]
(.C(AXI4_Lite_ACLK),
.CE(aw_transfer),
.CLR(reset),
.D(AXI4_Lite_AWADDR[7]),
.Q(sel0[7]));
LUT3 #(
.INIT(8'h20))
\wdata[15]_i_1
(.I0(AXI4_Lite_WVALID),
.I1(axi_lite_wstate[1]),
.I2(axi_lite_wstate[0]),
.O(w_transfer));
FDCE \wdata_reg[0]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[0]),
.Q(Q[0]));
FDCE \wdata_reg[10]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[10]),
.Q(Q[10]));
FDCE \wdata_reg[11]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[11]),
.Q(Q[11]));
FDCE \wdata_reg[12]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[12]),
.Q(Q[12]));
FDCE \wdata_reg[13]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[13]),
.Q(Q[13]));
FDCE \wdata_reg[14]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[14]),
.Q(Q[14]));
FDCE \wdata_reg[15]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[15]),
.Q(Q[15]));
FDCE \wdata_reg[1]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[1]),
.Q(Q[1]));
FDCE \wdata_reg[2]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[2]),
.Q(Q[2]));
FDCE \wdata_reg[3]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[3]),
.Q(Q[3]));
FDCE \wdata_reg[4]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[4]),
.Q(Q[4]));
FDCE \wdata_reg[5]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[5]),
.Q(Q[5]));
FDCE \wdata_reg[6]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[6]),
.Q(Q[6]));
FDCE \wdata_reg[7]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[7]),
.Q(Q[7]));
FDCE \wdata_reg[8]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[8]),
.Q(Q[8]));
FDCE \wdata_reg[9]
(.C(AXI4_Lite_ACLK),
.CE(w_transfer),
.CLR(reset),
.D(AXI4_Lite_WDATA[9]),
.Q(Q[9]));
FDCE wr_enb_1_reg
(.C(AXI4_Lite_ACLK),
.CE(1'b1),
.CLR(reset),
.D(w_transfer),
.Q(top_wr_enb));
LUT6 #(
.INIT(64'hFFFFBFFF00008000))
write_reg_axi_enable_i_1
(.I0(Q[0]),
.I1(write_reg_axi_enable_i_2_n_0),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I3(top_wr_enb),
.I4(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.I5(write_reg_axi_enable),
.O(write_reg_axi_enable_reg_0));
LUT6 #(
.INIT(64'h0000000047034400))
write_reg_axi_enable_i_2
(.I0(AXI4_Lite_ARADDR[6]),
.I1(AXI4_Lite_ARVALID),
.I2(sel0[6]),
.I3(AXI4_Lite_ARADDR[0]),
.I4(sel0[0]),
.I5(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.O(write_reg_axi_enable_i_2_n_0));
LUT6 #(
.INIT(64'h0000000040000000))
\write_reg_d_k[15]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I4(top_wr_enb),
.I5(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.O(\write_reg_d_k_reg[15] ));
LUT6 #(
.INIT(64'h0000000004000000))
\write_reg_x_k[15]_i_1
(.I0(\AXI4_Lite_RDATA_tmp[31]_i_5_n_0 ),
.I1(\AXI4_Lite_RDATA_tmp[31]_i_6_n_0 ),
.I2(\AXI4_Lite_RDATA_tmp[31]_i_7_n_0 ),
.I3(\AXI4_Lite_RDATA_tmp[31]_i_8_n_0 ),
.I4(top_wr_enb),
.I5(\AXI4_Lite_RDATA_tmp[31]_i_4_n_0 ),
.O(E));
endmodule
(* ORIG_REF_NAME = "lms_pcore_cop" *)
module ip_design_lms_pcore_0_0_lms_pcore_cop
(cp_controller_cpstate,
cop_out_ready,
cop_dut_enable,
strobe_reg_cop_in_strobe_reg,
IPCORE_CLK,
AR,
write_reg_axi_enable);
output [1:0]cp_controller_cpstate;
output cop_out_ready;
output cop_dut_enable;
input strobe_reg_cop_in_strobe_reg;
input IPCORE_CLK;
input [0:0]AR;
input write_reg_axi_enable;
wire [0:0]AR;
wire IPCORE_CLK;
wire cop_dut_enable;
wire cop_out_ready;
wire [1:0]cp_controller_cpstate;
wire \cp_controller_cpstate[1]_i_1_n_0 ;
wire strobe_reg_cop_in_strobe_reg;
wire write_reg_axi_enable;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h38))
\cp_controller_cpstate[1]_i_1
(.I0(cp_controller_cpstate[0]),
.I1(write_reg_axi_enable),
.I2(cp_controller_cpstate[1]),
.O(\cp_controller_cpstate[1]_i_1_n_0 ));
FDCE \cp_controller_cpstate_reg[0]
(.C(IPCORE_CLK),
.CE(1'b1),
.CLR(AR),
.D(strobe_reg_cop_in_strobe_reg),
.Q(cp_controller_cpstate[0]));
FDCE \cp_controller_cpstate_reg[1]
(.C(IPCORE_CLK),
.CE(1'b1),
.CLR(AR),
.D(\cp_controller_cpstate[1]_i_1_n_0 ),
.Q(cp_controller_cpstate[1]));
LUT2 #(
.INIT(4'h2))
\data_pipeline_tmp[14][15]_i_1
(.I0(cp_controller_cpstate[0]),
.I1(cp_controller_cpstate[1]),
.O(cop_dut_enable));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h1))
read_reg_cop_out_ready_i_1
(.I0(cp_controller_cpstate[0]),
.I1(cp_controller_cpstate[1]),
.O(cop_out_ready));
endmodule
(* ORIG_REF_NAME = "lms_pcore_dut" *)
module ip_design_lms_pcore_0_0_lms_pcore_dut
(mul_temp_16,
filter_sum,
\write_reg_x_k_reg[15] ,
cop_dut_enable,
IPCORE_CLK,
AR,
\write_reg_d_k_reg[3] ,
DI,
Q,
\write_reg_d_k_reg[3]_0 ,
\write_reg_d_k_reg[7] ,
\write_reg_d_k_reg[11] ,
S);
output [15:0]mul_temp_16;
output [15:0]filter_sum;
input [15:0]\write_reg_x_k_reg[15] ;
input cop_dut_enable;
input IPCORE_CLK;
input [0:0]AR;
input [2:0]\write_reg_d_k_reg[3] ;
input [0:0]DI;
input [14:0]Q;
input [3:0]\write_reg_d_k_reg[3]_0 ;
input [3:0]\write_reg_d_k_reg[7] ;
input [3:0]\write_reg_d_k_reg[11] ;
input [3:0]S;
wire [0:0]AR;
wire [0:0]DI;
wire IPCORE_CLK;
wire [14:0]Q;
wire [3:0]S;
wire cop_dut_enable;
wire [15:0]filter_sum;
wire [15:0]mul_temp_16;
wire [3:0]\write_reg_d_k_reg[11] ;
wire [2:0]\write_reg_d_k_reg[3] ;
wire [3:0]\write_reg_d_k_reg[3]_0 ;
wire [3:0]\write_reg_d_k_reg[7] ;
wire [15:0]\write_reg_x_k_reg[15] ;
ip_design_lms_pcore_0_0_LMS u_LMS
(.AR(AR),
.DI(DI),
.IPCORE_CLK(IPCORE_CLK),
.Q(Q),
.S(S),
.cop_dut_enable(cop_dut_enable),
.filter_sum(filter_sum),
.mul_temp_16(mul_temp_16),
.\write_reg_d_k_reg[11] (\write_reg_d_k_reg[11] ),
.\write_reg_d_k_reg[3] (\write_reg_d_k_reg[3] ),
.\write_reg_d_k_reg[3]_0 (\write_reg_d_k_reg[3]_0 ),
.\write_reg_d_k_reg[7] (\write_reg_d_k_reg[7] ),
.\write_reg_x_k_reg[15] (\write_reg_x_k_reg[15] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13.07.2017 13:29:14
// Design Name:
// Module Name: t_mem
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module t_mem;
// Inputs
reg [31:0] writedata, aluresultin, pcbranch1;
reg [4:0] writereg1;
reg branch, memwrite, memtoreg1, regwrite1, zerowire, clk;
// Outputs
wire [31:0] readdata, aluresultout, pcbranch2;
wire [4:0] writereg2;
wire regwrite2, memtoreg2, pcsrc;
// Instantiate the Unit Under Test
memoryaccess uut (
.ReadDataM( readdata ), .ALUResultOut( aluresultout ), .PCBranchM2( pcbranch2 ),
.WriteRegM2( writereg2 ),
.RegWriteM2( regwrite2 ), .MemToRegM2( memtoreg2 ), .PCSrcM( pcsrc ),
.WriteDataM( writedata ), .ALUResultIn( aluresultin ), .PCBranchM1( pcbranch1 ),
.WriteRegM1( writereg1 ),
.BranchM( branch ), .MemWriteM( memwrite ), .MemToRegM1( memtoreg1 ),
.RegWriteM1( regwrite1 ),
.ZerowireM( zerowire ), .clk( clk )
);
// Intialise the clock
initial begin
clk = 0;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
// Initialise inputs
writedata = 0; aluresultin = 0; pcbranch1 = 0;
writereg1 = 0;
branch = 0; memwrite = 0; memtoreg1 = 0; regwrite1 = 0; zerowire = 0; clk = 0;
// Wait 100 ns for global resets
#100;
// Test zerowire + branch and PCBranch
#10 zerowire = 0; branch = 0; pcbranch1 = 32'h00000008; //expected output pcsrc = 0; pcbranch2 = 32'h00000008;
#20 zerowire = 0; branch = 1; pcbranch1 = 32'h00000008; //expected output pcsrc = 0; pcbranch2 = 32'h00000008;
#20 zerowire = 1; branch = 0; pcbranch1 = 32'h00000008; //expected output pcsrc = 0; pcbranch2 = 32'h00000008;
#20 zerowire = 1; branch = 1; pcbranch1 = 32'h00000008; //expected output pcsrc = 1; pcbranch2 = 32'h00000008;
// Test ALUResultIn for when MemWrite = 0 and MemWrite = 1;
#20 aluresultin = 32'h00000001; memwrite = 1; writedata = 32'hFFFFFFFF;
// expected output aluresultout = 32'h00000001; dmem stores value FFFFFFFF into address 32'h00000001
#20 aluresultin = 32'h00000001; memwrite = 0; writedata = 32'hAAAAAAAA; // expected output aluresultout = 32'h00000001; readdata = 32'hFFFFFFFF;
// Test read function of dmem
// Test follow-through signals
#20 writereg1 = 5'b01000; memtoreg1 = 1; regwrite1 = 1; // expected output writereg2 = 5'b01000; memtoreg2 = 1; regwrite2 = 1;
#20 writereg1 = 5'b01001; memtoreg1 = 0; regwrite1 = 0; // expected output writereg2 = 5'b01001; memtoreg2 = 0; regwrite2 = 0;
end
endmodule
|
module qdiv #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] i_dividend,
input [N-1:0] i_divisor,
input i_start,
input i_clk,
output [N-1:0] o_quotient_out,
output o_complete,
output o_overflow
);
reg [2*N+Q-3:0] reg_working_quotient; // Our working copy of the quotient
reg [N-1:0] reg_quotient; // Final quotient
reg [N-2+Q:0] reg_working_dividend; // Working copy of the dividend
reg [2*N+Q-3:0] reg_working_divisor; // Working copy of the divisor
reg [N-1:0] reg_count; // This is obviously a lot bigger than it needs to be, as we only need
// count to N-1+Q but, computing that number of bits requires a
// logarithm (base 2), and I don't know how to do that in a
// way that will work for everyone
reg reg_done; // Computation completed flag
reg reg_sign; // The quotient's sign bit
reg reg_overflow; // Overflow flag
initial reg_done = 1'b1; // Initial state is to not be doing anything
initial reg_overflow = 1'b0; // And there should be no woverflow present
initial reg_sign = 1'b0; // And the sign should be positive
initial reg_working_quotient = 0;
initial reg_quotient = 0;
initial reg_working_dividend = 0;
initial reg_working_divisor = 0;
initial reg_count = 0;
assign o_quotient_out[N-2:0] = reg_quotient[N-2:0]; // The division results
assign o_quotient_out[N-1] = reg_sign; // The sign of the quotient
assign o_complete = reg_done;
assign o_overflow = reg_overflow;
always @( posedge i_clk ) begin
if( reg_done && i_start ) begin // This is our startup condition
// Need to check for a divide by zero right here, I think....
reg_done <= 1'b0; // We're not done
reg_count <= N+Q-1; // Set the count
reg_working_quotient <= 0; // Clear out the quotient register
reg_working_dividend <= 0; // Clear out the dividend register
reg_working_divisor <= 0; // Clear out the divisor register
reg_overflow <= 1'b0; // Clear the overflow register
reg_working_dividend[N+Q-2:Q] <= i_dividend[N-2:0]; // Left-align the dividend in its working register
reg_working_divisor[2*N+Q-3:N+Q-1] <= i_divisor[N-2:0]; // Left-align the divisor into its working register
reg_sign <= i_dividend[N-1] ^ i_divisor[N-1]; // Set the sign bit
end
else if(!reg_done) begin
reg_working_divisor <= reg_working_divisor >> 1; // Right shift the divisor (that is, divide it by two - aka reduce the divisor)
reg_count <= reg_count - 1; // Decrement the count
// If the dividend is greater than the divisor
if(reg_working_dividend >= reg_working_divisor) begin
reg_working_quotient[reg_count] <= 1'b1; // Set the quotient bit
reg_working_dividend <= reg_working_dividend - reg_working_divisor; // and subtract the divisor from the dividend
end
//stop condition
if(reg_count == 0) begin
reg_done <= 1'b1; // If we're done, it's time to tell the calling process
reg_quotient <= reg_working_quotient; // Move in our working copy to the outside world
if (reg_working_quotient[2*N+Q-3:N]>0)
reg_overflow <= 1'b1;
end
else
reg_count <= reg_count - 1;
end
end
endmodule |
module SimpleRam
#(parameter BUS_WIDTH = 8, parameter SIZE = 512, parameter ADDRESS_WIDTH = 32)
(
input wire clk,
input wire reset,
input wire [ADDRESS_WIDTH-1:0] addrA,
input wire [BUS_WIDTH-1:0] dataIn,
input wire writeEnable,
input wire [ADDRESS_WIDTH-1:0] addrB,
output reg [BUS_WIDTH-1:0] outA,
output reg [BUS_WIDTH-1:0] outB,
output reg busyA,
output reg busyB
);
reg [BUS_WIDTH-1:0] memory[0:SIZE-1];
reg [BUS_WIDTH-1:0] lastAddrA = 0;
reg [BUS_WIDTH-1:0] lastAddrB = 0;
// Counter variable for initialization
integer i;
// For debugging
always @(posedge reset) $writememh("ram.hex", memory);
always @(clk)
begin
if(writeEnable)
begin
outA <= dataIn;
memory[addrA] <= dataIn;
end
if(addrA != lastAddrA)
busyA <= 1;
if(addrB != lastAddrB)
busyA <= 1;
if(~writeEnable)
begin
busyA <= 0;
outA <= memory[addrA];
busyB <= 0;
outB <= memory[addrB];
end
lastAddrA = addrA;
lastAddrB = addrB;
if(reset)
begin
busyA <= 1;
busyB <= 1;
outA <= 0;
outB <= 0;
for(i = 0; i < SIZE; i=i+1)
memory[i] <= 0;
end
end
endmodule
|
`timescale 1ns / 1ps
module DE0_NANO_SOC_Default();
wire [31:0] cpuDataOut;
wire [31:0] cpuDataIn;
wire [31:0] cpuDataInAddr;
wire [31:0] cpuDataOutAddr;
wire cpuWrEn;
wire [31:0] instrBus;
wire [31:0] pcBus;
wire [31:0] CPU_StatusBus;
wire forceRoot;
wire flushing;
wire [31:0] instrCacheAddr;
wire [31:0] instrCacheData;
wire [31:0] dataOutFlowCtrl;
wire [31:0] dataOutUART;
wire [31:0] dataOutDataCache;
wire [31:0] IRQBus;
wire [31:0] uartStatus;
reg clk;
reg rst;
wire TxD;
assign IRQBus = 0;
assign IRQBus[0] = uartStatus[2]; // RX buffer ready
assign IRQBus[1] = uartStatus[1]; // TX complete
wolfcore CPU(
.dataOutput(cpuDataOut),
.dataInput(cpuDataIn),
.dataInAddr(cpuDataInAddr),
.dataOutAddr(cpuDataOutAddr),
.dataWrEn(cpuWrEn),
.instrInput(instrBus),
.pc(pcBus),
.CPU_Status(CPU_StatusBus),
.rst(rst),
.clk(clk),
.forceRoot(forceRoot),
.flushing(flushing)
);
flowController instrCtrl(
.rst(rst),
.clk(clk),
.pc(pcBus),
.CPU_Status(CPU_StatusBus),
.flushing(flushing),
.instrOut(instrBus),
.forceRoot(forceRoot),
.memAddr(instrCacheAddr),
.instrIn(instrCacheData),
.IRQ(IRQBus),
.inputAddr(cpuDataOutAddr),
.outputAddr(cpuDataInAddr),
.inputData(cpuDataOut),
.outputData(dataOutFlowCtrl),
.wrEn(cpuWrEn)
);
progMem instrCache(
.instrOutput(instrCacheData),
.instrAddress(instrCacheAddr),
.clk(clk)
);
dataController dataCache(
.dataIn(cpuDataOut),
.dataInAddr(cpuDataOutAddr),
.dataOut(dataOutDataCache),
.dataOutAddr(cpuDataInAddr),
.wren(cpuWrEn),
.clk(clk)
);
UART testUART(
.clk(clk),
.rst(rst),
.RxD(1'b0),
.TxD(TxD),
.inputData(cpuDataOut),
.inputAddr(cpuDataOutAddr),
.outputData(dataOutUART),
.outputAddr(cpuDataInAddr),
.wren(cpuWrEn),
.uartStatus(uartStatus)
);
outputDataMux dataMux(
.outputAddr(cpuDataInAddr),
.outputDataUART(dataOutUART),
.outputDataFlowCtrl(dataOutFlowCtrl),
.outputDataDataCache(dataOutDataCache),
.outputData(cpuDataIn)
);
initial begin
clk = 1'b0;
forever begin
#1
clk = ~clk;
end
end
initial begin
rst = 1'b1;
#10
rst = 1'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21OI_BLACKBOX_V
`define SKY130_FD_SC_HD__A21OI_BLACKBOX_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21oi (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21OI_BLACKBOX_V
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sp_co_ord_delay (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
phi_0_0_0_V_read,
phi_0_0_1_V_read,
phi_0_1_0_V_read,
phi_0_1_1_V_read,
phi_0_2_0_V_read,
phi_0_2_1_V_read,
phi_0_3_0_V_read,
phi_0_3_1_V_read,
phi_0_4_0_V_read,
phi_0_4_1_V_read,
phi_0_5_0_V_read,
phi_0_5_1_V_read,
phi_0_6_0_V_read,
phi_0_6_1_V_read,
phi_0_7_0_V_read,
phi_0_7_1_V_read,
phi_0_8_0_V_read,
phi_0_8_1_V_read,
phi_1_0_0_V_read,
phi_1_0_1_V_read,
phi_1_1_0_V_read,
phi_1_1_1_V_read,
phi_1_2_0_V_read,
phi_1_2_1_V_read,
phi_1_3_0_V_read,
phi_1_3_1_V_read,
phi_1_4_0_V_read,
phi_1_4_1_V_read,
phi_1_5_0_V_read,
phi_1_5_1_V_read,
phi_1_6_0_V_read,
phi_1_6_1_V_read,
phi_1_7_0_V_read,
phi_1_7_1_V_read,
phi_1_8_0_V_read,
phi_1_8_1_V_read,
phi_2_0_0_V_read,
phi_2_0_1_V_read,
phi_2_1_0_V_read,
phi_2_1_1_V_read,
phi_2_2_0_V_read,
phi_2_2_1_V_read,
phi_2_3_0_V_read,
phi_2_3_1_V_read,
phi_2_4_0_V_read,
phi_2_4_1_V_read,
phi_2_5_0_V_read,
phi_2_5_1_V_read,
phi_2_6_0_V_read,
phi_2_6_1_V_read,
phi_2_7_0_V_read,
phi_2_7_1_V_read,
phi_2_8_0_V_read,
phi_2_8_1_V_read,
phi_3_0_0_V_read,
phi_3_0_1_V_read,
phi_3_1_0_V_read,
phi_3_1_1_V_read,
phi_3_2_0_V_read,
phi_3_2_1_V_read,
phi_3_3_0_V_read,
phi_3_3_1_V_read,
phi_3_4_0_V_read,
phi_3_4_1_V_read,
phi_3_5_0_V_read,
phi_3_5_1_V_read,
phi_3_6_0_V_read,
phi_3_6_1_V_read,
phi_3_7_0_V_read,
phi_3_7_1_V_read,
phi_3_8_0_V_read,
phi_3_8_1_V_read,
phi_4_0_0_V_read,
phi_4_0_1_V_read,
phi_4_1_0_V_read,
phi_4_1_1_V_read,
phi_4_2_0_V_read,
phi_4_2_1_V_read,
phi_4_3_0_V_read,
phi_4_3_1_V_read,
phi_4_4_0_V_read,
phi_4_4_1_V_read,
phi_4_5_0_V_read,
phi_4_5_1_V_read,
phi_4_6_0_V_read,
phi_4_6_1_V_read,
phi_4_7_0_V_read,
phi_4_7_1_V_read,
phi_4_8_0_V_read,
phi_4_8_1_V_read,
cpati_0_0_0_V_read,
cpati_0_0_1_V_read,
cpati_0_1_0_V_read,
cpati_0_1_1_V_read,
cpati_0_2_0_V_read,
cpati_0_2_1_V_read,
cpati_0_3_0_V_read,
cpati_0_3_1_V_read,
cpati_0_4_0_V_read,
cpati_0_4_1_V_read,
cpati_0_5_0_V_read,
cpati_0_5_1_V_read,
cpati_0_6_0_V_read,
cpati_0_6_1_V_read,
cpati_0_7_0_V_read,
cpati_0_7_1_V_read,
cpati_0_8_0_V_read,
cpati_0_8_1_V_read,
cpati_1_0_0_V_read,
cpati_1_0_1_V_read,
cpati_1_1_0_V_read,
cpati_1_1_1_V_read,
cpati_1_2_0_V_read,
cpati_1_2_1_V_read,
cpati_1_3_0_V_read,
cpati_1_3_1_V_read,
cpati_1_4_0_V_read,
cpati_1_4_1_V_read,
cpati_1_5_0_V_read,
cpati_1_5_1_V_read,
cpati_1_6_0_V_read,
cpati_1_6_1_V_read,
cpati_1_7_0_V_read,
cpati_1_7_1_V_read,
cpati_1_8_0_V_read,
cpati_1_8_1_V_read,
cpati_2_0_0_V_read,
cpati_2_0_1_V_read,
cpati_2_1_0_V_read,
cpati_2_1_1_V_read,
cpati_2_2_0_V_read,
cpati_2_2_1_V_read,
cpati_2_3_0_V_read,
cpati_2_3_1_V_read,
cpati_2_4_0_V_read,
cpati_2_4_1_V_read,
cpati_2_5_0_V_read,
cpati_2_5_1_V_read,
cpati_2_6_0_V_read,
cpati_2_6_1_V_read,
cpati_2_7_0_V_read,
cpati_2_7_1_V_read,
cpati_2_8_0_V_read,
cpati_2_8_1_V_read,
cpati_3_0_0_V_read,
cpati_3_0_1_V_read,
cpati_3_1_0_V_read,
cpati_3_1_1_V_read,
cpati_3_2_0_V_read,
cpati_3_2_1_V_read,
cpati_3_3_0_V_read,
cpati_3_3_1_V_read,
cpati_3_4_0_V_read,
cpati_3_4_1_V_read,
cpati_3_5_0_V_read,
cpati_3_5_1_V_read,
cpati_3_6_0_V_read,
cpati_3_6_1_V_read,
cpati_3_7_0_V_read,
cpati_3_7_1_V_read,
cpati_3_8_0_V_read,
cpati_3_8_1_V_read,
cpati_4_0_0_V_read,
cpati_4_0_1_V_read,
cpati_4_1_0_V_read,
cpati_4_1_1_V_read,
cpati_4_2_0_V_read,
cpati_4_2_1_V_read,
cpati_4_3_0_V_read,
cpati_4_3_1_V_read,
cpati_4_4_0_V_read,
cpati_4_4_1_V_read,
cpati_4_5_0_V_read,
cpati_4_5_1_V_read,
cpati_4_6_0_V_read,
cpati_4_6_1_V_read,
cpati_4_7_0_V_read,
cpati_4_7_1_V_read,
cpati_4_8_0_V_read,
cpati_4_8_1_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3,
ap_return_4,
ap_return_5,
ap_return_6,
ap_return_7,
ap_return_8,
ap_return_9,
ap_return_10,
ap_return_11,
ap_return_12,
ap_return_13,
ap_return_14,
ap_return_15,
ap_return_16,
ap_return_17,
ap_return_18,
ap_return_19,
ap_return_20,
ap_return_21,
ap_return_22,
ap_return_23,
ap_return_24,
ap_return_25,
ap_return_26,
ap_return_27,
ap_return_28,
ap_return_29,
ap_return_30,
ap_return_31,
ap_return_32,
ap_return_33,
ap_return_34,
ap_return_35,
ap_return_36,
ap_return_37
);
parameter ap_ST_pp0_stg0_fsm_0 = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [11:0] phi_0_0_0_V_read;
input [11:0] phi_0_0_1_V_read;
input [11:0] phi_0_1_0_V_read;
input [11:0] phi_0_1_1_V_read;
input [11:0] phi_0_2_0_V_read;
input [11:0] phi_0_2_1_V_read;
input [11:0] phi_0_3_0_V_read;
input [11:0] phi_0_3_1_V_read;
input [11:0] phi_0_4_0_V_read;
input [11:0] phi_0_4_1_V_read;
input [11:0] phi_0_5_0_V_read;
input [11:0] phi_0_5_1_V_read;
input [11:0] phi_0_6_0_V_read;
input [11:0] phi_0_6_1_V_read;
input [11:0] phi_0_7_0_V_read;
input [11:0] phi_0_7_1_V_read;
input [11:0] phi_0_8_0_V_read;
input [11:0] phi_0_8_1_V_read;
input [11:0] phi_1_0_0_V_read;
input [11:0] phi_1_0_1_V_read;
input [11:0] phi_1_1_0_V_read;
input [11:0] phi_1_1_1_V_read;
input [11:0] phi_1_2_0_V_read;
input [11:0] phi_1_2_1_V_read;
input [11:0] phi_1_3_0_V_read;
input [11:0] phi_1_3_1_V_read;
input [11:0] phi_1_4_0_V_read;
input [11:0] phi_1_4_1_V_read;
input [11:0] phi_1_5_0_V_read;
input [11:0] phi_1_5_1_V_read;
input [11:0] phi_1_6_0_V_read;
input [11:0] phi_1_6_1_V_read;
input [11:0] phi_1_7_0_V_read;
input [11:0] phi_1_7_1_V_read;
input [11:0] phi_1_8_0_V_read;
input [11:0] phi_1_8_1_V_read;
input [11:0] phi_2_0_0_V_read;
input [11:0] phi_2_0_1_V_read;
input [11:0] phi_2_1_0_V_read;
input [11:0] phi_2_1_1_V_read;
input [11:0] phi_2_2_0_V_read;
input [11:0] phi_2_2_1_V_read;
input [11:0] phi_2_3_0_V_read;
input [11:0] phi_2_3_1_V_read;
input [11:0] phi_2_4_0_V_read;
input [11:0] phi_2_4_1_V_read;
input [11:0] phi_2_5_0_V_read;
input [11:0] phi_2_5_1_V_read;
input [11:0] phi_2_6_0_V_read;
input [11:0] phi_2_6_1_V_read;
input [11:0] phi_2_7_0_V_read;
input [11:0] phi_2_7_1_V_read;
input [11:0] phi_2_8_0_V_read;
input [11:0] phi_2_8_1_V_read;
input [11:0] phi_3_0_0_V_read;
input [11:0] phi_3_0_1_V_read;
input [11:0] phi_3_1_0_V_read;
input [11:0] phi_3_1_1_V_read;
input [11:0] phi_3_2_0_V_read;
input [11:0] phi_3_2_1_V_read;
input [11:0] phi_3_3_0_V_read;
input [11:0] phi_3_3_1_V_read;
input [11:0] phi_3_4_0_V_read;
input [11:0] phi_3_4_1_V_read;
input [11:0] phi_3_5_0_V_read;
input [11:0] phi_3_5_1_V_read;
input [11:0] phi_3_6_0_V_read;
input [11:0] phi_3_6_1_V_read;
input [11:0] phi_3_7_0_V_read;
input [11:0] phi_3_7_1_V_read;
input [11:0] phi_3_8_0_V_read;
input [11:0] phi_3_8_1_V_read;
input [11:0] phi_4_0_0_V_read;
input [11:0] phi_4_0_1_V_read;
input [11:0] phi_4_1_0_V_read;
input [11:0] phi_4_1_1_V_read;
input [11:0] phi_4_2_0_V_read;
input [11:0] phi_4_2_1_V_read;
input [11:0] phi_4_3_0_V_read;
input [11:0] phi_4_3_1_V_read;
input [11:0] phi_4_4_0_V_read;
input [11:0] phi_4_4_1_V_read;
input [11:0] phi_4_5_0_V_read;
input [11:0] phi_4_5_1_V_read;
input [11:0] phi_4_6_0_V_read;
input [11:0] phi_4_6_1_V_read;
input [11:0] phi_4_7_0_V_read;
input [11:0] phi_4_7_1_V_read;
input [11:0] phi_4_8_0_V_read;
input [11:0] phi_4_8_1_V_read;
input [3:0] cpati_0_0_0_V_read;
input [3:0] cpati_0_0_1_V_read;
input [3:0] cpati_0_1_0_V_read;
input [3:0] cpati_0_1_1_V_read;
input [3:0] cpati_0_2_0_V_read;
input [3:0] cpati_0_2_1_V_read;
input [3:0] cpati_0_3_0_V_read;
input [3:0] cpati_0_3_1_V_read;
input [3:0] cpati_0_4_0_V_read;
input [3:0] cpati_0_4_1_V_read;
input [3:0] cpati_0_5_0_V_read;
input [3:0] cpati_0_5_1_V_read;
input [3:0] cpati_0_6_0_V_read;
input [3:0] cpati_0_6_1_V_read;
input [3:0] cpati_0_7_0_V_read;
input [3:0] cpati_0_7_1_V_read;
input [3:0] cpati_0_8_0_V_read;
input [3:0] cpati_0_8_1_V_read;
input [3:0] cpati_1_0_0_V_read;
input [3:0] cpati_1_0_1_V_read;
input [3:0] cpati_1_1_0_V_read;
input [3:0] cpati_1_1_1_V_read;
input [3:0] cpati_1_2_0_V_read;
input [3:0] cpati_1_2_1_V_read;
input [3:0] cpati_1_3_0_V_read;
input [3:0] cpati_1_3_1_V_read;
input [3:0] cpati_1_4_0_V_read;
input [3:0] cpati_1_4_1_V_read;
input [3:0] cpati_1_5_0_V_read;
input [3:0] cpati_1_5_1_V_read;
input [3:0] cpati_1_6_0_V_read;
input [3:0] cpati_1_6_1_V_read;
input [3:0] cpati_1_7_0_V_read;
input [3:0] cpati_1_7_1_V_read;
input [3:0] cpati_1_8_0_V_read;
input [3:0] cpati_1_8_1_V_read;
input [3:0] cpati_2_0_0_V_read;
input [3:0] cpati_2_0_1_V_read;
input [3:0] cpati_2_1_0_V_read;
input [3:0] cpati_2_1_1_V_read;
input [3:0] cpati_2_2_0_V_read;
input [3:0] cpati_2_2_1_V_read;
input [3:0] cpati_2_3_0_V_read;
input [3:0] cpati_2_3_1_V_read;
input [3:0] cpati_2_4_0_V_read;
input [3:0] cpati_2_4_1_V_read;
input [3:0] cpati_2_5_0_V_read;
input [3:0] cpati_2_5_1_V_read;
input [3:0] cpati_2_6_0_V_read;
input [3:0] cpati_2_6_1_V_read;
input [3:0] cpati_2_7_0_V_read;
input [3:0] cpati_2_7_1_V_read;
input [3:0] cpati_2_8_0_V_read;
input [3:0] cpati_2_8_1_V_read;
input [3:0] cpati_3_0_0_V_read;
input [3:0] cpati_3_0_1_V_read;
input [3:0] cpati_3_1_0_V_read;
input [3:0] cpati_3_1_1_V_read;
input [3:0] cpati_3_2_0_V_read;
input [3:0] cpati_3_2_1_V_read;
input [3:0] cpati_3_3_0_V_read;
input [3:0] cpati_3_3_1_V_read;
input [3:0] cpati_3_4_0_V_read;
input [3:0] cpati_3_4_1_V_read;
input [3:0] cpati_3_5_0_V_read;
input [3:0] cpati_3_5_1_V_read;
input [3:0] cpati_3_6_0_V_read;
input [3:0] cpati_3_6_1_V_read;
input [3:0] cpati_3_7_0_V_read;
input [3:0] cpati_3_7_1_V_read;
input [3:0] cpati_3_8_0_V_read;
input [3:0] cpati_3_8_1_V_read;
input [3:0] cpati_4_0_0_V_read;
input [3:0] cpati_4_0_1_V_read;
input [3:0] cpati_4_1_0_V_read;
input [3:0] cpati_4_1_1_V_read;
input [3:0] cpati_4_2_0_V_read;
input [3:0] cpati_4_2_1_V_read;
input [3:0] cpati_4_3_0_V_read;
input [3:0] cpati_4_3_1_V_read;
input [3:0] cpati_4_4_0_V_read;
input [3:0] cpati_4_4_1_V_read;
input [3:0] cpati_4_5_0_V_read;
input [3:0] cpati_4_5_1_V_read;
input [3:0] cpati_4_6_0_V_read;
input [3:0] cpati_4_6_1_V_read;
input [3:0] cpati_4_7_0_V_read;
input [3:0] cpati_4_7_1_V_read;
input [3:0] cpati_4_8_0_V_read;
input [3:0] cpati_4_8_1_V_read;
output [11:0] ap_return_0;
output [11:0] ap_return_1;
output [11:0] ap_return_2;
output [11:0] ap_return_3;
output [11:0] ap_return_4;
output [11:0] ap_return_5;
output [11:0] ap_return_6;
output [11:0] ap_return_7;
output [11:0] ap_return_8;
output [6:0] ap_return_9;
output [6:0] ap_return_10;
output [6:0] ap_return_11;
output [6:0] ap_return_12;
output [6:0] ap_return_13;
output [6:0] ap_return_14;
output [6:0] ap_return_15;
output [6:0] ap_return_16;
output [6:0] ap_return_17;
output [6:0] ap_return_18;
output [6:0] ap_return_19;
output [6:0] ap_return_20;
output [6:0] ap_return_21;
output [6:0] ap_return_22;
output [6:0] ap_return_23;
output [6:0] ap_return_24;
output [6:0] ap_return_25;
output [6:0] ap_return_26;
output [6:0] ap_return_27;
output [6:0] ap_return_28;
output [3:0] ap_return_29;
output [3:0] ap_return_30;
output [3:0] ap_return_31;
output [3:0] ap_return_32;
output [3:0] ap_return_33;
output [3:0] ap_return_34;
output [3:0] ap_return_35;
output [3:0] ap_return_36;
output [3:0] ap_return_37;
reg ap_done;
reg ap_idle;
reg ap_ready;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
reg ap_sig_cseq_ST_pp0_stg0_fsm_0;
reg ap_sig_18;
wire ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it3;
reg grp_sp_co_ord_delay_actual_fu_2538_ap_start;
wire grp_sp_co_ord_delay_actual_fu_2538_ap_done;
wire grp_sp_co_ord_delay_actual_fu_2538_ap_idle;
wire grp_sp_co_ord_delay_actual_fu_2538_ap_ready;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_0;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_1;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_2;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_3;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_4;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_5;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_6;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_7;
wire [11:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_8;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_9;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_10;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_11;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_12;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_13;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_14;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_15;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_16;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_17;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_18;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_19;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_20;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_21;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_22;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_23;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_24;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_25;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_26;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_27;
wire [6:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_28;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_29;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_30;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_31;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_32;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_33;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_34;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_35;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_36;
wire [3:0] grp_sp_co_ord_delay_actual_fu_2538_ap_return_37;
reg [0:0] ap_NS_fsm;
reg ap_sig_grp_sp_co_ord_delay_actual_fu_2538_ap_start;
reg ap_sig_pprstidle_pp0;
// power-on initialization
initial begin
#0 ap_CS_fsm = 1'b1;
#0 ap_reg_ppiten_pp0_it1 = 1'b0;
#0 ap_reg_ppiten_pp0_it2 = 1'b0;
#0 ap_reg_ppiten_pp0_it3 = 1'b0;
end
sp_co_ord_delay_actual grp_sp_co_ord_delay_actual_fu_2538(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(grp_sp_co_ord_delay_actual_fu_2538_ap_start),
.ap_done(grp_sp_co_ord_delay_actual_fu_2538_ap_done),
.ap_idle(grp_sp_co_ord_delay_actual_fu_2538_ap_idle),
.ap_ready(grp_sp_co_ord_delay_actual_fu_2538_ap_ready),
.phi_0_0_0_V_read(phi_0_0_0_V_read),
.phi_0_0_1_V_read(phi_0_0_1_V_read),
.phi_0_1_0_V_read(phi_0_1_0_V_read),
.phi_0_1_1_V_read(phi_0_1_1_V_read),
.phi_0_2_0_V_read(phi_0_2_0_V_read),
.phi_0_2_1_V_read(phi_0_2_1_V_read),
.phi_0_3_0_V_read(phi_0_3_0_V_read),
.phi_0_3_1_V_read(phi_0_3_1_V_read),
.phi_0_4_0_V_read(phi_0_4_0_V_read),
.phi_0_4_1_V_read(phi_0_4_1_V_read),
.phi_0_5_0_V_read(phi_0_5_0_V_read),
.phi_0_5_1_V_read(phi_0_5_1_V_read),
.phi_0_6_0_V_read(phi_0_6_0_V_read),
.phi_0_6_1_V_read(phi_0_6_1_V_read),
.phi_0_7_0_V_read(phi_0_7_0_V_read),
.phi_0_7_1_V_read(phi_0_7_1_V_read),
.phi_0_8_0_V_read(phi_0_8_0_V_read),
.phi_0_8_1_V_read(phi_0_8_1_V_read),
.phi_1_0_0_V_read(phi_1_0_0_V_read),
.phi_1_0_1_V_read(phi_1_0_1_V_read),
.phi_1_1_0_V_read(phi_1_1_0_V_read),
.phi_1_1_1_V_read(phi_1_1_1_V_read),
.phi_1_2_0_V_read(phi_1_2_0_V_read),
.phi_1_2_1_V_read(phi_1_2_1_V_read),
.phi_1_3_0_V_read(phi_1_3_0_V_read),
.phi_1_3_1_V_read(phi_1_3_1_V_read),
.phi_1_4_0_V_read(phi_1_4_0_V_read),
.phi_1_4_1_V_read(phi_1_4_1_V_read),
.phi_1_5_0_V_read(phi_1_5_0_V_read),
.phi_1_5_1_V_read(phi_1_5_1_V_read),
.phi_1_6_0_V_read(phi_1_6_0_V_read),
.phi_1_6_1_V_read(phi_1_6_1_V_read),
.phi_1_7_0_V_read(phi_1_7_0_V_read),
.phi_1_7_1_V_read(phi_1_7_1_V_read),
.phi_1_8_0_V_read(phi_1_8_0_V_read),
.phi_1_8_1_V_read(phi_1_8_1_V_read),
.phi_2_0_0_V_read(phi_2_0_0_V_read),
.phi_2_0_1_V_read(phi_2_0_1_V_read),
.phi_2_1_0_V_read(phi_2_1_0_V_read),
.phi_2_1_1_V_read(phi_2_1_1_V_read),
.phi_2_2_0_V_read(phi_2_2_0_V_read),
.phi_2_2_1_V_read(phi_2_2_1_V_read),
.phi_2_3_0_V_read(phi_2_3_0_V_read),
.phi_2_3_1_V_read(phi_2_3_1_V_read),
.phi_2_4_0_V_read(phi_2_4_0_V_read),
.phi_2_4_1_V_read(phi_2_4_1_V_read),
.phi_2_5_0_V_read(phi_2_5_0_V_read),
.phi_2_5_1_V_read(phi_2_5_1_V_read),
.phi_2_6_0_V_read(phi_2_6_0_V_read),
.phi_2_6_1_V_read(phi_2_6_1_V_read),
.phi_2_7_0_V_read(phi_2_7_0_V_read),
.phi_2_7_1_V_read(phi_2_7_1_V_read),
.phi_2_8_0_V_read(phi_2_8_0_V_read),
.phi_2_8_1_V_read(phi_2_8_1_V_read),
.phi_3_0_0_V_read(phi_3_0_0_V_read),
.phi_3_0_1_V_read(phi_3_0_1_V_read),
.phi_3_1_0_V_read(phi_3_1_0_V_read),
.phi_3_1_1_V_read(phi_3_1_1_V_read),
.phi_3_2_0_V_read(phi_3_2_0_V_read),
.phi_3_2_1_V_read(phi_3_2_1_V_read),
.phi_3_3_0_V_read(phi_3_3_0_V_read),
.phi_3_3_1_V_read(phi_3_3_1_V_read),
.phi_3_4_0_V_read(phi_3_4_0_V_read),
.phi_3_4_1_V_read(phi_3_4_1_V_read),
.phi_3_5_0_V_read(phi_3_5_0_V_read),
.phi_3_5_1_V_read(phi_3_5_1_V_read),
.phi_3_6_0_V_read(phi_3_6_0_V_read),
.phi_3_6_1_V_read(phi_3_6_1_V_read),
.phi_3_7_0_V_read(phi_3_7_0_V_read),
.phi_3_7_1_V_read(phi_3_7_1_V_read),
.phi_3_8_0_V_read(phi_3_8_0_V_read),
.phi_3_8_1_V_read(phi_3_8_1_V_read),
.phi_4_0_0_V_read(phi_4_0_0_V_read),
.phi_4_0_1_V_read(phi_4_0_1_V_read),
.phi_4_1_0_V_read(phi_4_1_0_V_read),
.phi_4_1_1_V_read(phi_4_1_1_V_read),
.phi_4_2_0_V_read(phi_4_2_0_V_read),
.phi_4_2_1_V_read(phi_4_2_1_V_read),
.phi_4_3_0_V_read(phi_4_3_0_V_read),
.phi_4_3_1_V_read(phi_4_3_1_V_read),
.phi_4_4_0_V_read(phi_4_4_0_V_read),
.phi_4_4_1_V_read(phi_4_4_1_V_read),
.phi_4_5_0_V_read(phi_4_5_0_V_read),
.phi_4_5_1_V_read(phi_4_5_1_V_read),
.phi_4_6_0_V_read(phi_4_6_0_V_read),
.phi_4_6_1_V_read(phi_4_6_1_V_read),
.phi_4_7_0_V_read(phi_4_7_0_V_read),
.phi_4_7_1_V_read(phi_4_7_1_V_read),
.phi_4_8_0_V_read(phi_4_8_0_V_read),
.phi_4_8_1_V_read(phi_4_8_1_V_read),
.cpati_0_0_0_V_read(cpati_0_0_0_V_read),
.cpati_0_0_1_V_read(cpati_0_0_1_V_read),
.cpati_0_1_0_V_read(cpati_0_1_0_V_read),
.cpati_0_1_1_V_read(cpati_0_1_1_V_read),
.cpati_0_2_0_V_read(cpati_0_2_0_V_read),
.cpati_0_2_1_V_read(cpati_0_2_1_V_read),
.cpati_0_3_0_V_read(cpati_0_3_0_V_read),
.cpati_0_3_1_V_read(cpati_0_3_1_V_read),
.cpati_0_4_0_V_read(cpati_0_4_0_V_read),
.cpati_0_4_1_V_read(cpati_0_4_1_V_read),
.cpati_0_5_0_V_read(cpati_0_5_0_V_read),
.cpati_0_5_1_V_read(cpati_0_5_1_V_read),
.cpati_0_6_0_V_read(cpati_0_6_0_V_read),
.cpati_0_6_1_V_read(cpati_0_6_1_V_read),
.cpati_0_7_0_V_read(cpati_0_7_0_V_read),
.cpati_0_7_1_V_read(cpati_0_7_1_V_read),
.cpati_0_8_0_V_read(cpati_0_8_0_V_read),
.cpati_0_8_1_V_read(cpati_0_8_1_V_read),
.cpati_1_0_0_V_read(cpati_1_0_0_V_read),
.cpati_1_0_1_V_read(cpati_1_0_1_V_read),
.cpati_1_1_0_V_read(cpati_1_1_0_V_read),
.cpati_1_1_1_V_read(cpati_1_1_1_V_read),
.cpati_1_2_0_V_read(cpati_1_2_0_V_read),
.cpati_1_2_1_V_read(cpati_1_2_1_V_read),
.cpati_1_3_0_V_read(cpati_1_3_0_V_read),
.cpati_1_3_1_V_read(cpati_1_3_1_V_read),
.cpati_1_4_0_V_read(cpati_1_4_0_V_read),
.cpati_1_4_1_V_read(cpati_1_4_1_V_read),
.cpati_1_5_0_V_read(cpati_1_5_0_V_read),
.cpati_1_5_1_V_read(cpati_1_5_1_V_read),
.cpati_1_6_0_V_read(cpati_1_6_0_V_read),
.cpati_1_6_1_V_read(cpati_1_6_1_V_read),
.cpati_1_7_0_V_read(cpati_1_7_0_V_read),
.cpati_1_7_1_V_read(cpati_1_7_1_V_read),
.cpati_1_8_0_V_read(cpati_1_8_0_V_read),
.cpati_1_8_1_V_read(cpati_1_8_1_V_read),
.cpati_2_0_0_V_read(cpati_2_0_0_V_read),
.cpati_2_0_1_V_read(cpati_2_0_1_V_read),
.cpati_2_1_0_V_read(cpati_2_1_0_V_read),
.cpati_2_1_1_V_read(cpati_2_1_1_V_read),
.cpati_2_2_0_V_read(cpati_2_2_0_V_read),
.cpati_2_2_1_V_read(cpati_2_2_1_V_read),
.cpati_2_3_0_V_read(cpati_2_3_0_V_read),
.cpati_2_3_1_V_read(cpati_2_3_1_V_read),
.cpati_2_4_0_V_read(cpati_2_4_0_V_read),
.cpati_2_4_1_V_read(cpati_2_4_1_V_read),
.cpati_2_5_0_V_read(cpati_2_5_0_V_read),
.cpati_2_5_1_V_read(cpati_2_5_1_V_read),
.cpati_2_6_0_V_read(cpati_2_6_0_V_read),
.cpati_2_6_1_V_read(cpati_2_6_1_V_read),
.cpati_2_7_0_V_read(cpati_2_7_0_V_read),
.cpati_2_7_1_V_read(cpati_2_7_1_V_read),
.cpati_2_8_0_V_read(cpati_2_8_0_V_read),
.cpati_2_8_1_V_read(cpati_2_8_1_V_read),
.cpati_3_0_0_V_read(cpati_3_0_0_V_read),
.cpati_3_0_1_V_read(cpati_3_0_1_V_read),
.cpati_3_1_0_V_read(cpati_3_1_0_V_read),
.cpati_3_1_1_V_read(cpati_3_1_1_V_read),
.cpati_3_2_0_V_read(cpati_3_2_0_V_read),
.cpati_3_2_1_V_read(cpati_3_2_1_V_read),
.cpati_3_3_0_V_read(cpati_3_3_0_V_read),
.cpati_3_3_1_V_read(cpati_3_3_1_V_read),
.cpati_3_4_0_V_read(cpati_3_4_0_V_read),
.cpati_3_4_1_V_read(cpati_3_4_1_V_read),
.cpati_3_5_0_V_read(cpati_3_5_0_V_read),
.cpati_3_5_1_V_read(cpati_3_5_1_V_read),
.cpati_3_6_0_V_read(cpati_3_6_0_V_read),
.cpati_3_6_1_V_read(cpati_3_6_1_V_read),
.cpati_3_7_0_V_read(cpati_3_7_0_V_read),
.cpati_3_7_1_V_read(cpati_3_7_1_V_read),
.cpati_3_8_0_V_read(cpati_3_8_0_V_read),
.cpati_3_8_1_V_read(cpati_3_8_1_V_read),
.cpati_4_0_0_V_read(cpati_4_0_0_V_read),
.cpati_4_0_1_V_read(cpati_4_0_1_V_read),
.cpati_4_1_0_V_read(cpati_4_1_0_V_read),
.cpati_4_1_1_V_read(cpati_4_1_1_V_read),
.cpati_4_2_0_V_read(cpati_4_2_0_V_read),
.cpati_4_2_1_V_read(cpati_4_2_1_V_read),
.cpati_4_3_0_V_read(cpati_4_3_0_V_read),
.cpati_4_3_1_V_read(cpati_4_3_1_V_read),
.cpati_4_4_0_V_read(cpati_4_4_0_V_read),
.cpati_4_4_1_V_read(cpati_4_4_1_V_read),
.cpati_4_5_0_V_read(cpati_4_5_0_V_read),
.cpati_4_5_1_V_read(cpati_4_5_1_V_read),
.cpati_4_6_0_V_read(cpati_4_6_0_V_read),
.cpati_4_6_1_V_read(cpati_4_6_1_V_read),
.cpati_4_7_0_V_read(cpati_4_7_0_V_read),
.cpati_4_7_1_V_read(cpati_4_7_1_V_read),
.cpati_4_8_0_V_read(cpati_4_8_0_V_read),
.cpati_4_8_1_V_read(cpati_4_8_1_V_read),
.ap_return_0(grp_sp_co_ord_delay_actual_fu_2538_ap_return_0),
.ap_return_1(grp_sp_co_ord_delay_actual_fu_2538_ap_return_1),
.ap_return_2(grp_sp_co_ord_delay_actual_fu_2538_ap_return_2),
.ap_return_3(grp_sp_co_ord_delay_actual_fu_2538_ap_return_3),
.ap_return_4(grp_sp_co_ord_delay_actual_fu_2538_ap_return_4),
.ap_return_5(grp_sp_co_ord_delay_actual_fu_2538_ap_return_5),
.ap_return_6(grp_sp_co_ord_delay_actual_fu_2538_ap_return_6),
.ap_return_7(grp_sp_co_ord_delay_actual_fu_2538_ap_return_7),
.ap_return_8(grp_sp_co_ord_delay_actual_fu_2538_ap_return_8),
.ap_return_9(grp_sp_co_ord_delay_actual_fu_2538_ap_return_9),
.ap_return_10(grp_sp_co_ord_delay_actual_fu_2538_ap_return_10),
.ap_return_11(grp_sp_co_ord_delay_actual_fu_2538_ap_return_11),
.ap_return_12(grp_sp_co_ord_delay_actual_fu_2538_ap_return_12),
.ap_return_13(grp_sp_co_ord_delay_actual_fu_2538_ap_return_13),
.ap_return_14(grp_sp_co_ord_delay_actual_fu_2538_ap_return_14),
.ap_return_15(grp_sp_co_ord_delay_actual_fu_2538_ap_return_15),
.ap_return_16(grp_sp_co_ord_delay_actual_fu_2538_ap_return_16),
.ap_return_17(grp_sp_co_ord_delay_actual_fu_2538_ap_return_17),
.ap_return_18(grp_sp_co_ord_delay_actual_fu_2538_ap_return_18),
.ap_return_19(grp_sp_co_ord_delay_actual_fu_2538_ap_return_19),
.ap_return_20(grp_sp_co_ord_delay_actual_fu_2538_ap_return_20),
.ap_return_21(grp_sp_co_ord_delay_actual_fu_2538_ap_return_21),
.ap_return_22(grp_sp_co_ord_delay_actual_fu_2538_ap_return_22),
.ap_return_23(grp_sp_co_ord_delay_actual_fu_2538_ap_return_23),
.ap_return_24(grp_sp_co_ord_delay_actual_fu_2538_ap_return_24),
.ap_return_25(grp_sp_co_ord_delay_actual_fu_2538_ap_return_25),
.ap_return_26(grp_sp_co_ord_delay_actual_fu_2538_ap_return_26),
.ap_return_27(grp_sp_co_ord_delay_actual_fu_2538_ap_return_27),
.ap_return_28(grp_sp_co_ord_delay_actual_fu_2538_ap_return_28),
.ap_return_29(grp_sp_co_ord_delay_actual_fu_2538_ap_return_29),
.ap_return_30(grp_sp_co_ord_delay_actual_fu_2538_ap_return_30),
.ap_return_31(grp_sp_co_ord_delay_actual_fu_2538_ap_return_31),
.ap_return_32(grp_sp_co_ord_delay_actual_fu_2538_ap_return_32),
.ap_return_33(grp_sp_co_ord_delay_actual_fu_2538_ap_return_33),
.ap_return_34(grp_sp_co_ord_delay_actual_fu_2538_ap_return_34),
.ap_return_35(grp_sp_co_ord_delay_actual_fu_2538_ap_return_35),
.ap_return_36(grp_sp_co_ord_delay_actual_fu_2538_ap_return_36),
.ap_return_37(grp_sp_co_ord_delay_actual_fu_2538_ap_return_37)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= 1'b0;
end else begin
if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_start;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= 1'b0;
end else begin
if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= 1'b0;
end else begin
if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
end
always @ (*) begin
if ((((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0)) | ((1'b1 == ap_reg_ppiten_pp0_it3) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b0 == ap_reg_ppiten_pp0_it0) & (1'b0 == ap_reg_ppiten_pp0_it1) & (1'b0 == ap_reg_ppiten_pp0_it2) & (1'b0 == ap_reg_ppiten_pp0_it3))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (ap_sig_18) begin
ap_sig_cseq_ST_pp0_stg0_fsm_0 = 1'b1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~(ap_start == 1'b0))) begin
ap_sig_grp_sp_co_ord_delay_actual_fu_2538_ap_start = 1'b1;
end else begin
ap_sig_grp_sp_co_ord_delay_actual_fu_2538_ap_start = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b0 == ap_reg_ppiten_pp0_it0) & (1'b0 == ap_reg_ppiten_pp0_it1) & (1'b0 == ap_reg_ppiten_pp0_it2))) begin
ap_sig_pprstidle_pp0 = 1'b1;
end else begin
ap_sig_pprstidle_pp0 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_sig_grp_sp_co_ord_delay_actual_fu_2538_ap_start)) begin
grp_sp_co_ord_delay_actual_fu_2538_ap_start = ap_sig_grp_sp_co_ord_delay_actual_fu_2538_ap_start;
end else begin
grp_sp_co_ord_delay_actual_fu_2538_ap_start = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_pp0_stg0_fsm_0 : begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_0;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_reg_ppiten_pp0_it0 = ap_start;
assign ap_return_0 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_0;
assign ap_return_1 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_1;
assign ap_return_10 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_10;
assign ap_return_11 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_11;
assign ap_return_12 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_12;
assign ap_return_13 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_13;
assign ap_return_14 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_14;
assign ap_return_15 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_15;
assign ap_return_16 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_16;
assign ap_return_17 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_17;
assign ap_return_18 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_18;
assign ap_return_19 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_19;
assign ap_return_2 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_2;
assign ap_return_20 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_20;
assign ap_return_21 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_21;
assign ap_return_22 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_22;
assign ap_return_23 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_23;
assign ap_return_24 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_24;
assign ap_return_25 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_25;
assign ap_return_26 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_26;
assign ap_return_27 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_27;
assign ap_return_28 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_28;
assign ap_return_29 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_29;
assign ap_return_3 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_3;
assign ap_return_30 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_30;
assign ap_return_31 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_31;
assign ap_return_32 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_32;
assign ap_return_33 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_33;
assign ap_return_34 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_34;
assign ap_return_35 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_35;
assign ap_return_36 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_36;
assign ap_return_37 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_37;
assign ap_return_4 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_4;
assign ap_return_5 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_5;
assign ap_return_6 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_6;
assign ap_return_7 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_7;
assign ap_return_8 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_8;
assign ap_return_9 = grp_sp_co_ord_delay_actual_fu_2538_ap_return_9;
always @ (*) begin
ap_sig_18 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1);
end
endmodule //sp_co_ord_delay
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/20/2014 10:35:44 AM
// Design Name:
// Module Name: memcached_flash_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mcdSingleDramPCIe
#(parameter DRAM_WIDTH = 512,
parameter FLASH_WIDTH = 64,
// parameter DRAM_CMD_WIDTH = 24,
parameter DRAM_CMD_WIDTH = 40,
parameter FLASH_CMD_WIDTH = 48)
(
input clk,
input aresetn,
// Memcached Pipeline Input and Output Streams
output AXI_M_Stream_TVALID,
input AXI_M_Stream_TREADY,
output[63:0] AXI_M_Stream_TDATA,
output[7:0] AXI_M_Stream_TKEEP,
output[111:0] AXI_M_Stream_TUSER,
output AXI_M_Stream_TLAST,
input AXI_S_Stream_TVALID,
output AXI_S_Stream_TREADY,
input[63:0] AXI_S_Stream_TDATA,
input[7:0] AXI_S_Stream_TKEEP,
input[111:0] AXI_S_Stream_TUSER,
input AXI_S_Stream_TLAST,
//stats signals
input [31:0] stats0,
input [31:0] stats1,
//pcie interface
input [31: 0] pcie_axi_AWADDR,
input pcie_axi_AWVALID,
output pcie_axi_AWREADY,
//data write
input [31: 0] pcie_axi_WDATA,
input [3: 0] pcie_axi_WSTRB,
input pcie_axi_WVALID,
output pcie_axi_WREADY,
//write response (handhake)
output [1:0] pcie_axi_BRESP,
output pcie_axi_BVALID,
input pcie_axi_BREADY,
//address read
input [31: 0] pcie_axi_ARADDR,
input pcie_axi_ARVALID,
output pcie_axi_ARREADY,
//data read
output [31: 0] pcie_axi_RDATA,
output [1:0] pcie_axi_RRESP,
output pcie_axi_RVALID,
input pcie_axi_RREADY,
input pcieClk,
input pcie_user_lnk_up,
//signals to DRAM memory interface
//ht stream interface signals
output ht_s_axis_read_cmd_tvalid,
input ht_s_axis_read_cmd_tready,
output[71:0] ht_s_axis_read_cmd_tdata,
//read status
input ht_m_axis_read_sts_tvalid,
output ht_m_axis_read_sts_tready,
input[7:0] ht_m_axis_read_sts_tdata,
//read stream
input[511:0] ht_m_axis_read_tdata,
input[63:0] ht_m_axis_read_tkeep,
input ht_m_axis_read_tlast,
input ht_m_axis_read_tvalid,
output ht_m_axis_read_tready,
//write commands
output ht_s_axis_write_cmd_tvalid,
input ht_s_axis_write_cmd_tready,
output[71:0] ht_s_axis_write_cmd_tdata,
//write status
input ht_m_axis_write_sts_tvalid,
output ht_m_axis_write_sts_tready,
input[7:0] ht_m_axis_write_sts_tdata,
//write stream
output[511:0] ht_s_axis_write_tdata,
output[63:0] ht_s_axis_write_tkeep,
output ht_s_axis_write_tlast,
output ht_s_axis_write_tvalid,
input ht_s_axis_write_tready,
//vs stream interface signals
output vs_s_axis_read_cmd_tvalid,
input vs_s_axis_read_cmd_tready,
output[71:0] vs_s_axis_read_cmd_tdata,
//read status
input vs_m_axis_read_sts_tvalid,
output vs_m_axis_read_sts_tready,
input[7:0] vs_m_axis_read_sts_tdata,
//read stream
input[511:0] vs_m_axis_read_tdata,
input[63:0] vs_m_axis_read_tkeep,
input vs_m_axis_read_tlast,
input vs_m_axis_read_tvalid,
output vs_m_axis_read_tready,
//write commands
output vs_s_axis_write_cmd_tvalid,
input vs_s_axis_write_cmd_tready,
output[71:0] vs_s_axis_write_cmd_tdata,
//write status
input vs_m_axis_write_sts_tvalid,
output vs_m_axis_write_sts_tready,
input[7:0] vs_m_axis_write_sts_tdata,
//write stream
output[511:0] vs_s_axis_write_tdata,
output[63:0] vs_s_axis_write_tkeep,
output vs_s_axis_write_tlast,
output vs_s_axis_write_tvalid,
input vs_s_axis_write_tready
);
//DRAM model connections
wire[DRAM_WIDTH-1: 0] ht_dramRdData_data;
wire ht_dramRdData_valid;
wire ht_dramRdData_ready;
// ht_cmd_dramRdData: Push Output, 16b
wire[DRAM_CMD_WIDTH-1:0] ht_cmd_dramRdData_data;
wire ht_cmd_dramRdData_valid;
wire ht_cmd_dramRdData_ready;
// ht_dramWrData: Push Output, 512b
wire[DRAM_WIDTH-1:0] ht_dramWrData_data;
wire ht_dramWrData_valid;
wire ht_dramWrData_ready;
// ht_cmd_dramWrData: Push Output, 16b
wire[DRAM_CMD_WIDTH-1:0] ht_cmd_dramWrData_data;
wire ht_cmd_dramWrData_valid;
wire ht_cmd_dramWrData_ready;
// upd_cmd_dramRdData: Push Output, 16b
wire[DRAM_CMD_WIDTH-1:0] upd_cmd_dramRdData_data;
wire upd_cmd_dramRdData_valid;
wire upd_cmd_dramRdData_ready;
// upd_cmd_dramWrData: Push Output, 16b
wire[DRAM_CMD_WIDTH-1:0] upd_cmd_dramWrData_data;
wire upd_cmd_dramWrData_valid;
wire upd_cmd_dramWrData_ready;
// Update Flash Connection
// upd_flashRdData: Pull Input, 64b
wire[FLASH_WIDTH-1:0] flashValueStoreMemRdData_data;
wire flashValueStoreMemRdData_valid;
wire flashValueStoreMemRdData_ready;
// upd_cmd_flashRdData: Push Output, 48b
wire[FLASH_CMD_WIDTH-1:0] flashValueStoreMemRdCmd_data;
wire flashValueStoreMemRdCmd_valid;
wire flashValueStoreMemRdCmd_ready;
// upd_flashWrData: Push Output, 64b
wire[FLASH_WIDTH-1:0] flashValueStoreMemWrData_data;
wire flashValueStoreMemWrData_valid;
wire flashValueStoreMemWrData_ready;
// upd_cmd_flashWrData: Push Output, 48b
wire[FLASH_CMD_WIDTH-1:0] flashValueStoreMemWrCmd_data;
wire flashValueStoreMemWrCmd_valid;
wire flashValueStoreMemWrCmd_ready;
//dram memory path
wire dramValueStoreMemRdCmd_V_TVALID;
wire [DRAM_CMD_WIDTH-1:0] dramValueStoreMemRdCmd_V_TDATA;
wire dramValueStoreMemRdCmd_V_TREADY;
wire dramValueStoreMemRdData_V_V_TVALID;
wire [511:0] dramValueStoreMemRdData_V_V_TDATA;
wire dramValueStoreMemRdData_V_V_TREADY;
wire dramValueStoreMemWrCmd_V_TVALID;
wire [DRAM_CMD_WIDTH-1:0] dramValueStoreMemWrCmd_V_TDATA;
wire dramValueStoreMemWrCmd_V_TREADY;
wire dramValueStoreMemWrData_V_V_TVALID;
wire [511:0] dramValueStoreMemWrData_V_V_TDATA;
wire dramValueStoreMemWrData_V_V_TREADY;
//////////////////Memory Allocation Signals//////////////////////////////////////////-
wire[31:0] memcached2memAllocation_data; // Address reclamation
wire memcached2memAllocation_valid;
wire memcached2memAllocation_ready;
wire[31:0] memAllocation2memcached_dram_data; // Address assignment for DRAM
wire memAllocation2memcached_dram_valid;
wire memAllocation2memcached_dram_ready;
wire[31:0] memAllocation2memcached_flash_data; // Address assignment for SSD
wire memAllocation2memcached_flash_valid;
wire memAllocation2memcached_flash_ready;
//flush related signals
wire flushReq_V;
wire flushAck_V;
wire flushDone_V;
flashModel flash_vs(
.rdCmdIn_V_TVALID(flashValueStoreMemRdCmd_valid),
.rdCmdIn_V_TREADY(flashValueStoreMemRdCmd_ready),
.rdCmdIn_V_TDATA(flashValueStoreMemRdCmd_data),
.rdDataOut_V_V_TVALID(flashValueStoreMemRdData_valid),
.rdDataOut_V_V_TREADY(flashValueStoreMemRdData_ready),
.rdDataOut_V_V_TDATA(flashValueStoreMemRdData_data),
.wrCmdIn_V_TVALID(flashValueStoreMemWrCmd_valid),
.wrCmdIn_V_TREADY(flashValueStoreMemWrCmd_ready),
.wrCmdIn_V_TDATA(flashValueStoreMemWrCmd_data),
.wrDataIn_V_V_TVALID(flashValueStoreMemWrData_valid),
.wrDataIn_V_V_TREADY(flashValueStoreMemWrData_ready),
.wrDataIn_V_V_TDATA(flashValueStoreMemWrData_data),
.ap_rst_n(aresetn),
.ap_clk(clk)
);
readconverter_top ht_dram_read_converter(
.dmRdCmd_V_TVALID(ht_s_axis_read_cmd_tvalid),
.dmRdCmd_V_TREADY(ht_s_axis_read_cmd_tready),
.dmRdCmd_V_TDATA(ht_s_axis_read_cmd_tdata),
.dmRdData_V_TVALID(ht_m_axis_read_tvalid),
.dmRdData_V_TREADY(ht_m_axis_read_tready),
.dmRdData_V_TDATA(ht_m_axis_read_tdata),
.dmRdData_V_TKEEP(ht_m_axis_read_tkeep),
.dmRdData_V_TLAST(ht_m_axis_read_tlast),
.dmRdStatus_V_V_TVALID(ht_m_axis_read_sts_tvalid),
.dmRdStatus_V_V_TREADY(ht_m_axis_read_sts_tready),
.dmRdStatus_V_V_TDATA(ht_m_axis_read_sts_tdata),
.memRdCmd_V_TVALID(ht_cmd_dramRdData_valid),
.memRdCmd_V_TREADY(ht_cmd_dramRdData_ready),
.memRdCmd_V_TDATA(ht_cmd_dramRdData_data),
.memRdData_V_V_TVALID(ht_dramRdData_valid),
.memRdData_V_V_TREADY(ht_dramRdData_ready),
.memRdData_V_V_TDATA(ht_dramRdData_data),
.aresetn(aresetn),
.aclk(clk)
);
writeconverter_top ht_dram_write_converter(
.dmWrCmd_V_TVALID(ht_s_axis_write_cmd_tvalid),
.dmWrCmd_V_TREADY(ht_s_axis_write_cmd_tready),
.dmWrCmd_V_TDATA(ht_s_axis_write_cmd_tdata),
.dmWrData_V_TVALID(ht_s_axis_write_tvalid),
.dmWrData_V_TREADY(ht_s_axis_write_tready),
.dmWrData_V_TDATA(ht_s_axis_write_tdata),
.dmWrData_V_TKEEP(ht_s_axis_write_tkeep),
.dmWrData_V_TLAST(ht_s_axis_write_tlast),
.dmWrStatus_V_V_TVALID(ht_m_axis_write_sts_tvalid),
.dmWrStatus_V_V_TREADY(ht_m_axis_write_sts_tready),
.dmWrStatus_V_V_TDATA(ht_m_axis_write_sts_tdata),
.memWrCmd_V_TVALID(ht_cmd_dramWrData_valid),
.memWrCmd_V_TREADY(ht_cmd_dramWrData_ready),
.memWrCmd_V_TDATA(ht_cmd_dramWrData_data),
.memWrData_V_V_TVALID(ht_dramWrData_valid),
.memWrData_V_V_TREADY(ht_dramWrData_ready),
.memWrData_V_V_TDATA(ht_dramWrData_data),
.aresetn(aresetn),
.aclk(clk)
);
readconverter_top vs_dram_read_converter(
.dmRdCmd_V_TVALID(vs_s_axis_read_cmd_tvalid),
.dmRdCmd_V_TREADY(vs_s_axis_read_cmd_tready),
.dmRdCmd_V_TDATA(vs_s_axis_read_cmd_tdata),
.dmRdData_V_TVALID(vs_m_axis_read_tvalid),
.dmRdData_V_TREADY(vs_m_axis_read_tready),
.dmRdData_V_TDATA(vs_m_axis_read_tdata),
.dmRdData_V_TKEEP(vs_m_axis_read_tkeep),
.dmRdData_V_TLAST(vs_m_axis_read_tlast),
.dmRdStatus_V_V_TVALID(vs_m_axis_read_sts_tvalid),
.dmRdStatus_V_V_TREADY(vs_m_axis_read_sts_tready),
.dmRdStatus_V_V_TDATA(vs_m_axis_read_sts_tdata),
.memRdCmd_V_TVALID(dramValueStoreMemRdCmd_V_TVALID),
.memRdCmd_V_TREADY(dramValueStoreMemRdCmd_V_TREADY),
.memRdCmd_V_TDATA(dramValueStoreMemRdCmd_V_TDATA),
.memRdData_V_V_TVALID(dramValueStoreMemRdData_V_V_TVALID),
.memRdData_V_V_TREADY(dramValueStoreMemRdData_V_V_TREADY),
.memRdData_V_V_TDATA(dramValueStoreMemRdData_V_V_TDATA),
.aresetn(aresetn),
.aclk(clk)
);
writeconverter_top vs_dram_write_converter(
.dmWrCmd_V_TVALID(vs_s_axis_write_cmd_tvalid),
.dmWrCmd_V_TREADY(vs_s_axis_write_cmd_tready),
.dmWrCmd_V_TDATA(vs_s_axis_write_cmd_tdata),
.dmWrData_V_TVALID(vs_s_axis_write_tvalid),
.dmWrData_V_TREADY(vs_s_axis_write_tready),
.dmWrData_V_TDATA(vs_s_axis_write_tdata),
.dmWrData_V_TKEEP(vs_s_axis_write_tkeep),
.dmWrData_V_TLAST(vs_s_axis_write_tlast),
.dmWrStatus_V_V_TVALID(vs_m_axis_write_sts_tvalid),
.dmWrStatus_V_V_TREADY(vs_m_axis_write_sts_tready),
.dmWrStatus_V_V_TDATA(vs_m_axis_write_sts_tdata),
.memWrCmd_V_TVALID(dramValueStoreMemWrCmd_V_TVALID),
.memWrCmd_V_TREADY(dramValueStoreMemWrCmd_V_TREADY),
.memWrCmd_V_TDATA(dramValueStoreMemWrCmd_V_TDATA),
.memWrData_V_V_TVALID(dramValueStoreMemWrData_V_V_TVALID),
.memWrData_V_V_TREADY(dramValueStoreMemWrData_V_V_TREADY),
.memWrData_V_V_TDATA(dramValueStoreMemWrData_V_V_TDATA),
.aresetn(aresetn),
.aclk(clk)
);
//pciE instantiation
pcie_mem_alloc #(.REVISION(32'h12000006)) pcie_mem_alloc_inst (
.ACLK(clk),
.Axi_resetn(aresetn),
.stats0_data (stats0),
.stats1_data (stats1),
.stats2_data (32'h0),
.stats3_data (32'h0),
.pcie_axi_AWADDR(pcie_axi_AWADDR),
.pcie_axi_AWVALID(pcie_axi_AWVALID),
.pcie_axi_AWREADY(pcie_axi_AWREADY),
.pcie_axi_WDATA(pcie_axi_WDATA),
.pcie_axi_WSTRB(pcie_axi_WSTRB),
.pcie_axi_WVALID(pcie_axi_WVALID),
.pcie_axi_WREADY(pcie_axi_WREADY),
.pcie_axi_BRESP(pcie_axi_BRESP),
.pcie_axi_BVALID(pcie_axi_BVALID),
.pcie_axi_BREADY(pcie_axi_BREADY),
.pcie_axi_ARADDR(pcie_axi_ARADDR),
.pcie_axi_ARVALID(pcie_axi_ARVALID),
.pcie_axi_ARREADY(pcie_axi_ARREADY),
.pcie_axi_RDATA(pcie_axi_RDATA),
.pcie_axi_RRESP(pcie_axi_RRESP),
.pcie_axi_RVALID(pcie_axi_RVALID),
.pcie_axi_RREADY(pcie_axi_RREADY),
.pcieClk(pcieClk),
.pcie_user_lnk_up(pcie_user_lnk_up),
.memcached2memAllocation_data(memcached2memAllocation_data), // Address reclamation axis input 32
.memcached2memAllocation_valid(memcached2memAllocation_valid),
.memcached2memAllocation_ready(memcached2memAllocation_ready),
.memAllocation2memcached_dram_data(memAllocation2memcached_dram_data), // Address assignment for DRAM axis output 32
.memAllocation2memcached_dram_valid(memAllocation2memcached_dram_valid),
.memAllocation2memcached_dram_ready(memAllocation2memcached_dram_ready),
.memAllocation2memcached_flash_data(memAllocation2memcached_flash_data), // Address assignment for SSD axis output 32
.memAllocation2memcached_flash_valid(memAllocation2memcached_flash_valid),
.memAllocation2memcached_flash_ready(memAllocation2memcached_flash_ready),
.flushReq(flushReq_V),
.flushAck(flushAck_V),
.flushDone(flushDone_V)
);
//memcached Pipeline Instantiation
//memcached_bin_flash_ip myMemcachedPipeline (
memcachedPipeline myMemcachedPipeline(//use the one from synplify
.hashTableMemRdCmd_V_TVALID(ht_cmd_dramRdData_valid),
.hashTableMemRdCmd_V_TREADY(ht_cmd_dramRdData_ready),
.hashTableMemRdCmd_V_TDATA(ht_cmd_dramRdData_data),
.hashTableMemRdData_V_V_TVALID(ht_dramRdData_valid),
.hashTableMemRdData_V_V_TREADY(ht_dramRdData_ready),
.hashTableMemRdData_V_V_TDATA(ht_dramRdData_data),
.hashTableMemWrCmd_V_TVALID(ht_cmd_dramWrData_valid),
.hashTableMemWrCmd_V_TREADY(ht_cmd_dramWrData_ready),
.hashTableMemWrCmd_V_TDATA(ht_cmd_dramWrData_data),
.hashTableMemWrData_V_V_TVALID(ht_dramWrData_valid),
.hashTableMemWrData_V_V_TREADY(ht_dramWrData_ready),
.hashTableMemWrData_V_V_TDATA(ht_dramWrData_data),
.inData_TVALID(AXI_S_Stream_TVALID),
.inData_TREADY(AXI_S_Stream_TREADY),
.inData_TDATA(AXI_S_Stream_TDATA),
.inData_TUSER(AXI_S_Stream_TUSER),
.inData_TKEEP(AXI_S_Stream_TKEEP),
.inData_TLAST(AXI_S_Stream_TLAST),
.outData_TVALID(AXI_M_Stream_TVALID),
.outData_TREADY(AXI_M_Stream_TREADY),
.outData_TDATA(AXI_M_Stream_TDATA),
.outData_TUSER(AXI_M_Stream_TUSER),
.outData_TKEEP(AXI_M_Stream_TKEEP),
.outData_TLAST(AXI_M_Stream_TLAST),
.flashValueStoreMemRdCmd_V_TVALID(flashValueStoreMemRdCmd_valid),
.flashValueStoreMemRdCmd_V_TREADY(flashValueStoreMemRdCmd_ready),
.flashValueStoreMemRdCmd_V_TDATA(flashValueStoreMemRdCmd_data),
.flashValueStoreMemRdData_V_V_TVALID(flashValueStoreMemRdData_valid),
.flashValueStoreMemRdData_V_V_TREADY(flashValueStoreMemRdData_ready),
.flashValueStoreMemRdData_V_V_TDATA(flashValueStoreMemRdData_data),
.flashValueStoreMemWrCmd_V_TVALID(flashValueStoreMemWrCmd_valid),
.flashValueStoreMemWrCmd_V_TREADY(flashValueStoreMemWrCmd_ready),
.flashValueStoreMemWrCmd_V_TDATA(flashValueStoreMemWrCmd_data),
.flashValueStoreMemWrData_V_V_TVALID(flashValueStoreMemWrData_valid),
.flashValueStoreMemWrData_V_V_TREADY(flashValueStoreMemWrData_ready),
.flashValueStoreMemWrData_V_V_TDATA (flashValueStoreMemWrData_data),
.addressReturnOut_V_V_TDATA(memcached2memAllocation_data),
.addressReturnOut_V_V_TVALID(memcached2memAllocation_valid),
.addressReturnOut_V_V_TREADY(memcached2memAllocation_ready),
.addressAssignDramIn_V_V_TDATA(memAllocation2memcached_dram_data),
.addressAssignDramIn_V_V_TVALID(memAllocation2memcached_dram_valid),
.addressAssignDramIn_V_V_TREADY(memAllocation2memcached_dram_ready),
.addressAssignFlashIn_V_V_TDATA(memAllocation2memcached_flash_data),
.addressAssignFlashIn_V_V_TVALID(memAllocation2memcached_flash_valid),
.addressAssignFlashIn_V_V_TREADY(memAllocation2memcached_flash_ready),
//.aresetn(aresetn),
//.aclk(clk),
.ap_rst_n(aresetn),
.ap_clk(clk),
.dramValueStoreMemRdCmd_V_TVALID(dramValueStoreMemRdCmd_V_TVALID),
.dramValueStoreMemRdCmd_V_TDATA(dramValueStoreMemRdCmd_V_TDATA),
.dramValueStoreMemRdCmd_V_TREADY(dramValueStoreMemRdCmd_V_TREADY),
.dramValueStoreMemRdData_V_V_TVALID(dramValueStoreMemRdData_V_V_TVALID),
.dramValueStoreMemRdData_V_V_TDATA(dramValueStoreMemRdData_V_V_TDATA),
.dramValueStoreMemRdData_V_V_TREADY(dramValueStoreMemRdData_V_V_TREADY),
.dramValueStoreMemWrCmd_V_TVALID(dramValueStoreMemWrCmd_V_TVALID),
.dramValueStoreMemWrCmd_V_TDATA(dramValueStoreMemWrCmd_V_TDATA),
.dramValueStoreMemWrCmd_V_TREADY(dramValueStoreMemWrCmd_V_TREADY),
.dramValueStoreMemWrData_V_V_TVALID(dramValueStoreMemWrData_V_V_TVALID),
.dramValueStoreMemWrData_V_V_TDATA(dramValueStoreMemWrData_V_V_TDATA),
.dramValueStoreMemWrData_V_V_TREADY(dramValueStoreMemWrData_V_V_TREADY),
.flushReq_V(flushReq_V),
.flushAck_V(flushAck_V),
.flushDone_V(flushDone_V)
);
/* ------------------------------------------------------------ */
/* ChipScope Debugging */
/* ------------------------------------------------------------ */
//chipscope debugging
/*
reg [255:0] data;
reg [31:0] trig0;
wire [35:0] control0, control1;
wire vio_reset; //active high
chipscope_icon icon0
(
.CONTROL0 (control0),
.CONTROL1 (control1)
);
chipscope_ila ila0
(
.CLK (clk),
.CONTROL (control0),
.TRIG0 (trig0),
.DATA (data)
);
chipscope_vio vio0
(
.CONTROL(control1),
.ASYNC_OUT(vio_reset)
);
always @(posedge clk) begin
data[39:0] <= ht_cmd_dramRdData_data;
data[79:40] <= dramValueStoreMemRdCmd_V_TDATA;
data[80] <= ht_cmd_dramRdData_valid;
data[81] <= ht_cmd_dramRdData_ready;
data[82] <= ht_dramRdData_valid;
data[83] <= ht_dramRdData_ready;
data[84] <= ht_s_axis_read_cmd_tvalid;
data[85] <= ht_s_axis_read_cmd_tready;
data[86] <= ht_m_axis_read_tvalid;
data[87] <= ht_m_axis_read_tready;
data[88] <= ht_m_axis_read_tkeep;
data[89] <= ht_m_axis_read_tlast;
data[90] <= ht_m_axis_read_sts_tvalid;
data[91] <= ht_m_axis_read_sts_tready;
data[92] <= dramValueStoreMemRdCmd_V_TVALID;
data[93] <= dramValueStoreMemRdCmd_V_TREADY;
data[94] <= dramValueStoreMemRdData_V_V_TVALID;
data[95] <= dramValueStoreMemRdData_V_V_TREADY;
data[96] <= vs_s_axis_read_cmd_tvalid;
data[97] <= vs_s_axis_read_cmd_tready;
data[98] <= vs_m_axis_read_tvalid;
data[99] <= vs_m_axis_read_tready;
data[100] <= vs_m_axis_read_tkeep;
data[101] <= vs_m_axis_read_tlast;
data[102] <= vs_m_axis_read_sts_tvalid;
data[103] <= vs_m_axis_read_sts_tready;
data[104] <= link_initialized_clk156;
data[105] <= ncq_idle_clk156;
data[106] <= fin_read_sig_clk156;
trig0[0] <= ht_cmd_dramRdData_valid;
trig0[1] <= ht_cmd_dramRdData_ready;
trig0[2] <= ht_dramRdData_valid;
trig0[3] <= ht_dramRdData_ready;
trig0[4] <= ht_s_axis_read_cmd_tvalid;
trig0[5] <= ht_s_axis_read_cmd_tready;
trig0[6] <= ht_m_axis_read_tvalid;
trig0[7] <= ht_m_axis_read_tready;
trig0[8] <= ht_m_axis_read_tkeep;
trig0[9] <= ht_m_axis_read_tlast;
trig0[10] <= ht_m_axis_read_sts_tvalid;
trig0[11] <= ht_m_axis_read_sts_tready;
trig0[12] <= dramValueStoreMemRdCmd_V_TVALID;
trig0[13] <= dramValueStoreMemRdCmd_V_TREADY;
trig0[14] <= dramValueStoreMemRdData_V_V_TVALID;
trig0[15] <= dramValueStoreMemRdData_V_V_TREADY;
trig0[16] <= vs_s_axis_read_cmd_tvalid;
trig0[17] <= vs_s_axis_read_cmd_tready;
trig0[18] <= vs_m_axis_read_tvalid;
trig0[19] <= vs_m_axis_read_tready;
trig0[20] <= vs_m_axis_read_tkeep;
trig0[21] <= vs_m_axis_read_tlast;
trig0[22] <= vs_m_axis_read_sts_tvalid;
trig0[23] <= vs_m_axis_read_sts_tready;
end*/
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*/
`include "control.h"
/**
* Behavioral model for the carry-save adder
*
* Reference:
* Neil Weste and David Harris, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*/
module csa (reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
// Defining integers: integer [name_of_integer] = value;
// Indicates the number of bits that have been shifted
integer sgn;
/**
* Indicates the number of iterations for adding a multiplier
* so that these additions resemble the multiplication/shift
* operation with this currently enumerated bit of the
* multiplicand
*/
integer cnt;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
/**
* Temporary reg(s) to contain the partial products during
* multiplication
*/
reg [0:127] p_pdt;
// Temporary reg variables for WW=8, for 8-bit multiplication
reg [0:15] p_pdt8a;
reg [0:15] p_pdt8a2;
reg [0:7] p_pdt8a3;
reg [0:15] p_pdt8b;
reg [0:15] p_pdt8b2;
reg [0:15] p_pdt8c;
reg [0:15] p_pdt8c2;
reg [0:15] p_pdt8d;
reg [0:15] p_pdt8d2;
reg [0:15] p_pdt8e;
reg [0:15] p_pdt8e2;
reg [0:15] p_pdt8f;
reg [0:15] p_pdt8f2;
reg [0:15] p_pdt8g;
reg [0:15] p_pdt8g2;
reg [0:15] p_pdt8h;
reg [0:15] p_pdt8h2;
// Temporary reg variables for WW=16, for 16-bit multiplication
reg [0:31] p_pdt16a;
reg [0:31] p_pdt16a2;
reg [0:31] p_pdt16a3;
reg [0:31] p_pdt16b;
reg [0:31] p_pdt16b2;
reg [0:31] p_pdt16c;
reg [0:31] p_pdt16c2;
reg [0:31] p_pdt16d;
reg [0:31] p_pdt16d2;
// ===============================================================
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
$display("reg_A",reg_A);
$display("reg_B",reg_B);
p_pdt=128'd0;
p_pdt8a=16'd0;
p_pdt8a2=16'd0;
p_pdt8a3=8'd0;
p_pdt8b=16'd0;
p_pdt8b2=16'd0;
p_pdt8c=16'd0;
p_pdt8c2=16'd0;
p_pdt8d=16'd0;
p_pdt8d2=16'd0;
p_pdt8e=16'd0;
p_pdt8e2=16'd0;
p_pdt8f=16'd0;
p_pdt8f2=16'd0;
p_pdt8g=16'd0;
p_pdt8g2=16'd0;
p_pdt8h=16'd0;
p_pdt8h2=16'd0;
p_pdt16a=32'd0;
p_pdt16a2=32'd0;
p_pdt16a3=32'd0;
p_pdt16b=32'd0;
p_pdt16b2=32'd0;
p_pdt16c=32'd0;
p_pdt16c2=32'd0;
p_pdt16d=32'd0;
p_pdt16d2=32'd0;
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
// ======================================================
// Unsigned Multiplication - odd subfields
`aluwmulou:
begin
case(ctrl_ww)
(`w8+2'd1): // aluwmulou AND `w8
begin
p_pdt8a[8:15]=reg_A[8:15];
p_pdt8a[0:7]=8'd0;
p_pdt8a2[0:15]={{8{1'b0}},reg_B[8:15]};
$display("reg_A[8:15]",reg_A[8:15]);
$display("p_pdt8a2[0:15]",p_pdt8a2[0:15]);
$display("reg_B[8:15]",reg_B[8:15]);
$display("p_pdt8a[0:15]",p_pdt8a[0:15]);
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[0:15]=p_pdt[0:15]+((p_pdt8a[sgn]==1'd1)?(p_pdt8a2<<(8'd15-sgn)):16'b0);
end
result[0:15]=p_pdt[0:15];
p_pdt8b[8:15]=reg_A[24:31];
p_pdt8b[0:7]=8'd0;
p_pdt8b2[0:15]={{8{1'b0}},reg_B[24:31]};
$display("reg_A[24:31]",reg_A[24:31]);
$display("p_pdt8b2[0:15]",p_pdt8b2[0:15]);
$display("reg_B[24:31]",reg_B[24:31]);
$display("p_pdt8b[0:15]",p_pdt8b[0:15]);
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[16:31]=p_pdt[16:31]+((p_pdt8b[sgn]==1'd1)?(p_pdt8b2<<(8'd15-sgn)):16'b0);
end
result[16:31]=p_pdt[16:31];
p_pdt8c[8:15]=reg_A[40:47];
p_pdt8c[0:7]=8'd0;
p_pdt8c2[0:15]={{8{1'b0}},reg_B[40:47]};
$display("reg_A[40:47]",reg_A[40:47]);
$display("p_pdt8c2[0:15]",p_pdt8c2[0:15]);
$display("reg_B[40:47]",reg_B[40:47]);
$display("p_pdt8c[0:15]",p_pdt8c[0:15]);
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[32:47]=p_pdt[32:47]+((p_pdt8c[sgn]==1'd1)?(p_pdt8c2<<(8'd15-sgn)):16'b0);
$display("p_pdt[32:47]",p_pdt[32:47]);
end
result[32:47]=p_pdt[32:47];
p_pdt8d[8:15]=reg_A[56:63];
p_pdt8d[0:7]=8'd0;
p_pdt8d2[0:15]={{8{1'b0}},reg_B[56:63]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[48:63]=p_pdt[48:63]+((p_pdt8d[sgn]==1'd1)?(p_pdt8d2<<(8'd15-sgn)):16'b0);
end
result[48:63]=p_pdt[48:63];
p_pdt8e[8:15]=reg_A[72:79];
p_pdt8e[0:7]=8'd0;
p_pdt8e2[0:15]={{8{1'b0}},reg_B[72:79]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[64:79]=p_pdt[64:79]+((p_pdt8e[sgn]==1'd1)?(p_pdt8e2<<(8'd15-sgn)):16'b0);
end
result[64:79]=p_pdt[64:79];
p_pdt8f[8:15]=reg_A[88:95];
p_pdt8f[0:7]=8'd0;
p_pdt8f2[0:15]={{8{1'b0}},reg_B[88:95]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[80:95]=p_pdt[80:95]+((p_pdt8f[sgn]==1'd1)?(p_pdt8f2<<(8'd15-sgn)):16'b0);
end
result[80:95]=p_pdt[80:95];
p_pdt8g[8:15]=reg_A[104:111];
p_pdt8g[0:7]=8'd0;
p_pdt8g2[0:15]={{8{1'b0}},reg_B[104:111]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[96:111]=p_pdt[96:111]+((p_pdt8g[sgn]==1'd1)?(p_pdt8g2<<(8'd15-sgn)):16'b0);
end
result[96:111]=p_pdt[96:111];
p_pdt8h[8:15]=reg_A[120:127];
p_pdt8h[0:7]=8'd0;
p_pdt8h2[0:15]={{8{1'b0}},reg_B[120:127]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[112:127]=p_pdt[112:127]+((p_pdt8h[sgn]==1'd1)?(p_pdt8h2<<(8'd15-sgn)):16'b0);
end
result[112:127]=p_pdt[112:127];
end
(`w16+2'b01): // aluwmulou AND `w16
begin
p_pdt16a[0:31]={{16{1'b0}},reg_B[16:31]};
p_pdt16a2[0:31]={{16{1'b0}},reg_A[16:31]};
p_pdt16b[0:31]={{16{1'b0}},reg_B[48:63]};
p_pdt16b2[0:31]={{16{1'b0}},reg_A[48:63]};
p_pdt16c[0:31]={{16{1'b0}},reg_B[80:95]};
p_pdt16c2[0:31]={{16{1'b0}},reg_A[80:95]};
p_pdt16d[0:31]={{16{1'b0}},reg_B[112:127]};
p_pdt16d2[0:31]={{16{1'b0}},reg_A[112:127]};
for(sgn=31; sgn>=16; sgn=sgn-1)
begin
p_pdt[0:31]=p_pdt[0:31]+((p_pdt16a[sgn]==1'd1)?(p_pdt16a2<<(16'd31-sgn)):32'd0);
p_pdt[32:63]=p_pdt[32:63]+((p_pdt16b[sgn]==1'd1)?(p_pdt16b2<<(16'd31-sgn)):32'd0);
p_pdt[64:95]=p_pdt[64:95]+((p_pdt16c[sgn]==1'd1)?(p_pdt16c2<<(16'd31-sgn)):32'd0);
p_pdt[96:127]=p_pdt[96:127]+((p_pdt16d[sgn]==1'd1)?(p_pdt16d2<<(16'd31-sgn)):32'd0);
end
result[0:31]=p_pdt[0:31];
result[32:63]=p_pdt[32:63];
result[64:95]=p_pdt[64:95];
result[96:127]=p_pdt[96:127];
end
default: // aluwmulou AND Default
begin
result=128'd0;
end
endcase
end
default:
begin
// Default arithmetic/logic operation
result=128'd0;
end
endcase
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: ip_lpm.v
// Project: NF2.1
// Description: Finds the longest prefix match of the incoming IP address
// gives the ip of the next hop and the output port
//
///////////////////////////////////////////////////////////////////////////////
module ip_lpm
#(parameter DATA_WIDTH = 64,
parameter NUM_QUEUES = 5,
parameter LUT_DEPTH = `ROUTER_OP_LUT_ROUTE_TABLE_DEPTH,
parameter LUT_DEPTH_BITS = log2(LUT_DEPTH)
)
(// --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
// --- Interface to arp_lut
output reg [31:0] next_hop_ip,
output reg [NUM_QUEUES-1:0] lpm_output_port,
output reg lpm_vld,
output reg lpm_hit,
// --- Interface to preprocess block
input word_IP_SRC_DST,
input word_IP_DST_LO,
// --- Interface to registers
// --- Read port
input [LUT_DEPTH_BITS-1:0] lpm_rd_addr, // address in table to read
input lpm_rd_req, // request a read
output [31:0] lpm_rd_ip, // ip to match in the CAM
output [31:0] lpm_rd_mask, // subnet mask
output [NUM_QUEUES-1:0] lpm_rd_oq, // output queue
output [31:0] lpm_rd_next_hop_ip, // ip addr of next hop
output lpm_rd_ack, // pulses high
// --- Write port
input [LUT_DEPTH_BITS-1:0] lpm_wr_addr,
input lpm_wr_req,
input [NUM_QUEUES-1:0] lpm_wr_oq,
input [31:0] lpm_wr_next_hop_ip, // ip addr of next hop
input [31:0] lpm_wr_ip, // data to match in the CAM
input [31:0] lpm_wr_mask,
output lpm_wr_ack,
// --- Misc
output ready_out,
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//---------------------- Wires and regs----------------------------
wire cam_busy;
wire cam_match;
wire [LUT_DEPTH-1:0] cam_match_addr;
wire [31:0] cam_cmp_din, cam_cmp_data_mask;
wire [31:0] cam_din, cam_data_mask;
wire cam_we;
wire [LUT_DEPTH_BITS-1:0] cam_wr_addr;
wire [NUM_QUEUES-1:0] lookup_port_result;
wire [31:0] next_hop_ip_result;
reg dst_ip_vld;
reg [31:0] dst_ip;
wire [31:0] lpm_rd_mask_inverted;
//------------------------- Modules-------------------------------
assign lpm_rd_mask = ~lpm_rd_mask_inverted;
// 1 cycle read latency, 16 cycles write latency
// priority encoded for the smallest address.
/*
srl_cam_unencoded_32x32 lpm_cam
(
// Outputs
.busy (cam_busy),
.match (cam_match),
.match_addr (cam_match_addr),
// Inputs
.clk (clk),
.cmp_din (cam_cmp_din),
.din (cam_din),
.cmp_data_mask (cam_cmp_data_mask),
.data_mask (cam_data_mask),
.we (cam_we),
.wr_addr (cam_wr_addr));
*/
wire ready_reg;
ram_based_cam lpm_cam
(
.clk(clk),
.rst(reset),
.start_write(cam_we),
.waddr(cam_wr_addr),
.wdata(cam_din),
.wcare(cam_data_mask),
.lookup_data(cam_cmp_din),
.match_lines(cam_match_addr),
.ready(ready_reg),
.match_found(cam_match)
);
assign cam_busy = 1'b0;
assign ready_out = ready_reg;
unencoded_cam_lut_sm_lpm
#(.CMP_WIDTH (32), // IPv4 addr width
.DATA_WIDTH (32+NUM_QUEUES), // next hop ip and output queue
.LUT_DEPTH (LUT_DEPTH),
.DEFAULT_DATA (1)
) cam_lut_sm_lpm
(// --- Interface for lookups
.lookup_req (dst_ip_vld),
.lookup_cmp_data (dst_ip),
.lookup_cmp_dmask (32'h0),
.lookup_ack (lpm_vld_result),
.lookup_hit (lpm_hit_result),
.lookup_data ({lookup_port_result, next_hop_ip_result}),
// --- Interface to registers
// --- Read port
.rd_addr (lpm_rd_addr), // address in table to read
.rd_req (lpm_rd_req), // request a read
.rd_data ({lpm_rd_oq, lpm_rd_next_hop_ip}), // data found for the entry
.rd_cmp_data (lpm_rd_ip), // matching data for the entry
.rd_cmp_dmask (lpm_rd_mask_inverted), // don't cares entry
.rd_ack (lpm_rd_ack), // pulses high
// --- Write port
.wr_addr (lpm_wr_addr),
.wr_req (lpm_wr_req),
.wr_data ({lpm_wr_oq, lpm_wr_next_hop_ip}), // data found for the entry
.wr_cmp_data (lpm_wr_ip), // matching data for the entry
.wr_cmp_dmask (~lpm_wr_mask), // don't cares for the entry
.wr_ack (lpm_wr_ack),
// --- CAM interface
.cam_busy (cam_busy),
.cam_match (cam_match),
.cam_match_addr (cam_match_addr),
.cam_cmp_din (cam_cmp_din),
.cam_din (cam_din),
.cam_we (cam_we),
.cam_wr_addr (cam_wr_addr),
.cam_cmp_data_mask (cam_cmp_data_mask),
.cam_data_mask (cam_data_mask),
// --- Misc
.reset (reset),
.clk (clk));
//------------------------- Logic --------------------------------
/*****************************************************************
* find the dst IP address and do the lookup
*****************************************************************/
always @(posedge clk) begin
if(reset) begin
dst_ip <= 0;
dst_ip_vld <= 0;
end
else begin
if(word_IP_SRC_DST) begin
dst_ip[31:16] <= in_data[15:0];
end
if(word_IP_DST_LO) begin
dst_ip[15:0] <= in_data[DATA_WIDTH-1:DATA_WIDTH-16];
dst_ip_vld <= 1;
end
else begin
dst_ip_vld <= 0;
end
end // else: !if(reset)
end // always @ (posedge clk)
/*****************************************************************
* latch the outputs
*****************************************************************/
always @(posedge clk) begin
lpm_output_port <= lookup_port_result;
next_hop_ip <= (next_hop_ip_result == 0) ? dst_ip : next_hop_ip_result;
lpm_hit <= lpm_hit_result;
if(reset) begin
lpm_vld <= 0;
end
else begin
lpm_vld <= lpm_vld_result;
end // else: !if(reset)
end // always @ (posedge clk)
endmodule // ip_lpm
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_time (clock, reset, enable, start_event, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter num_cks = 1;
parameter action_on_new_start = `OVL_ACTION_ON_NEW_START_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event;
input test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_TIME";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if (~((action_on_new_start == `OVL_IGNORE_NEW_START) ||
(action_on_new_start == `OVL_RESET_ON_NEW_START) ||
(action_on_new_start == `OVL_ERROR_ON_NEW_START)))
begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal value set for parameter action_on_new_start");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/assert_time_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_time_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_time_psl_logic.v"
`else
`endmodule // ovl_time
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S4S_BLACKBOX_V
`define SKY130_FD_SC_MS__DLYMETAL6S4S_BLACKBOX_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlymetal6s4s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S4S_BLACKBOX_V
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
//
// There are two modes:
// - lf_ed_toggle_mode == 0: the output is set low (resp. high) when a low
// (resp. high) edge/peak is detected, with hysteresis
// - lf_ed_toggle_mode == 1: the output is toggling whenever an edge/peak
// is detected.
// That way you can detect two consecutive edges/peaks at the same level (L/H)
//
// Output:
// - ssp_frame (wired to TIOA1 on the arm) for the edge detection/state
// - ssp_clk: cross_lo
`include "lp20khz_1MSa_iir_filter.v"
`include "lf_edge_detect.v"
module lo_edge_detect(
input pck0, input pck_divclk,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk,
output ssp_frame, input ssp_dout, output ssp_clk,
input cross_lo,
output dbg,
input lf_field,
input lf_ed_toggle_mode, input [7:0] lf_ed_threshold
);
wire tag_modulation = ssp_dout & !lf_field;
wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
// No logic, straight through.
assign pwr_oe1 = 1'b0; // not used in LF mode
assign pwr_oe3 = 1'b0; // base antenna load = 33 Ohms
// when modulating, add another 33 Ohms and 10k Ohms in parallel:
assign pwr_oe2 = tag_modulation;
assign pwr_oe4 = tag_modulation;
assign ssp_clk = cross_lo;
assign pwr_lo = reader_modulation;
assign pwr_hi = 1'b0;
// filter the ADC values
wire data_rdy;
wire [7:0] adc_filtered;
assign adc_clk = pck0;
lp20khz_1MSa_iir_filter adc_filter(pck0, adc_d, data_rdy, adc_filtered);
// detect edges
wire [7:0] high_threshold, highz_threshold, lowz_threshold, low_threshold;
wire [7:0] max, min;
wire edge_state, edge_toggle;
lf_edge_detect lf_ed(pck0, adc_filtered, lf_ed_threshold,
max, min,
high_threshold, highz_threshold, lowz_threshold, low_threshold,
edge_state, edge_toggle);
assign dbg = lf_ed_toggle_mode ? edge_toggle : edge_state;
assign ssp_frame = lf_ed_toggle_mode ? edge_toggle : edge_state;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41OI_BLACKBOX_V
`define SKY130_FD_SC_HD__A41OI_BLACKBOX_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a41oi (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41OI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111A_M_V
`define SKY130_FD_SC_LP__O2111A_M_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111a_m (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111a_m (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111A_M_V
|
`timescale 1ns/1ps
//-----------------------------------------------------------------------------
// Title : KPU pipeline control logic
// Project : KPU
//-----------------------------------------------------------------------------
// File : ctrl.v
// Author : acorallo <[email protected]>
// Created : 17.12.2016
//-----------------------------------------------------------------------------
// Description :
// Execution stage implementation file for KPU
//-----------------------------------------------------------------------------
// This file is part of KPU.
// KPU is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// KPU is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY;
// without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with KPU. If not, see <http://www.gnu.org/licenses/>.
//
// Copyright (c) 2016 2017 by Andrea Corallo.
//------------------------------------------------------------------------------
// Modification history :
// 22.12.2016 : created
// 3.4.2017 : renamed ex.v -> ctrl.v
//-----------------------------------------------------------------------------
`ifndef _ctrl
`define _ctrl
`include "kpu_conf.v"
module pipe_fw_ctrl(
input wire wr_reg_3_i, wr_reg_4_i,
input wire [`N-1:0] rs1_2_i, rs2_2_i,
input wire [`N-1:0] data_out_3_i,
input wire [`N-1:0] data_4_i,
input wire [4:0] rs1_n_2_i, rs2_n_2_i,
input wire [4:0] reg_wr_n_3_i,
input wire [4:0] reg_wr_n_4_i,
output reg [`N-1:0] rs1_2_o, rs2_2_o
);
//////////////////
// RS 1 forward //
//////////////////
always @(*) begin
if (reg_wr_n_3_i == rs1_n_2_i && wr_reg_3_i == 1'b1)
// Back forward from MEM stage
rs1_2_o = data_out_3_i;
else if (reg_wr_n_4_i == rs1_n_2_i && wr_reg_4_i == 1'b1)
// Back forward from WB stage
rs1_2_o = data_4_i;
else
rs1_2_o = rs1_2_i;
end
//////////////////
// RS 2 forward //
//////////////////
always @(*) begin
if (reg_wr_n_3_i == rs2_n_2_i &&
wr_reg_3_i == 1'b1)
// Back forward from MEM stage
rs2_2_o = data_out_3_i;
else if (reg_wr_n_4_i == rs2_n_2_i &&
wr_reg_4_i == 1'b1)
// Back forward from WB stage
rs2_2_o = data_4_i;
else
rs2_2_o = rs2_2_i;
end
endmodule
module pipe_stall_ctrl(
input wire [5:0] op_1_i,
input wire alu_rrr_op_1_i,
input wire alu_rri_op_1_i,
input wire load_op_2_i,
input wire [4:0] rd_n_1_i,
input wire [4:0] rs1_n_1_i,
input wire [4:0] rs2_n_1_i,
input wire [4:0] rd_n_2_i,
output reg stall_o);
reg stall_t_1, stall_t_2;
// Type 1 stall management
always @(*) begin
stall_t_1 = 1'b0;
if (load_op_2_i) begin
// Load instruction in EX
if (alu_rrr_op_1_i && // RRR ALU inst
(rd_n_2_i == rs1_n_1_i || rd_n_2_i == rs2_n_1_i))
stall_t_1 = 1'b1; // insert stall
else if (alu_rri_op_1_i && // RRI ALU inst
rd_n_2_i == rs1_n_1_i)
stall_t_1 = 1'b1; // insert stall
end
end
// Type 2 stall management
always @(*) begin
stall_t_2 = 1'h0;
if (load_op_2_i) begin
case (op_1_i)
`LDW_OP, `LDH_OP, `LDHU_OP, `LDB_OP,
`LDBU_OP, `MOV_OP: begin // LD MOV
if (rd_n_2_i == rs1_n_1_i)
stall_t_2 = 1'b1; // stall
end
`STW_OP, `STH_OP, `STHU_OP, `STB_OP,
`STBU_OP: begin // ST
if (rd_n_2_i == rd_n_1_i ||
rd_n_2_i == rs1_n_1_i)
stall_t_2 = 1'b1; // stall
end
`STAW_OP: begin // STAW
if (rd_n_2_i == rd_n_1_i)
stall_t_2 = 1'b1; // stall
end
endcase
end
end
always @(*)
stall_o = stall_t_1 || stall_t_2;
endmodule
`endif // `ifndef _ctrl
|
`include "defines.v"
module ctrl(
input wire rst,
input wire[31:0] excepttype_i,
input wire[`RegBus] cp0_epc_i,
input wire stallreq_from_id,
//À´×ÔÖ´Ðн׶εÄÔÝÍ£ÇëÇó
input wire stallreq_from_ex,
input wire branch_from_id,
output reg[`RegBus] new_pc,
output reg flush,
output reg[5:0] stall
);
always @ (*) begin
if(rst == `RstEnable) begin
stall <= 6'b000000;
flush <= 1'b0;
new_pc <= `ZeroWord;
end else if(excepttype_i != `ZeroWord) begin
flush <= 1'b1;
stall <= 6'b000000;
case (excepttype_i)
32'h00000001: begin //interrupt
new_pc <= 32'h4;
end
32'h00000008: begin //syscall
new_pc <= 32'h4;
end
32'h0000000a: begin //inst_invalid
new_pc <= 32'h00000040;
end
32'h0000000d: begin //trap
new_pc <= 32'h4;
end
32'h0000000c: begin //break
new_pc <= 32'h4;
end
32'h0000000e: begin //eret
new_pc <= cp0_epc_i;
end
default : begin
end
endcase
end else if(stallreq_from_ex == `Stop) begin
stall <= 6'b001111;
flush <= 1'b0;
end else if(stallreq_from_id == `Stop) begin
stall <= 6'b000111;
flush <= 1'b0;
end else if(branch_from_id == `Branch) begin
stall <= 6'b000010;
flush <= 1'b0;
end else begin
stall <= 6'b000000;
flush <= 1'b0;
new_pc <= `ZeroWord;
end //if
end //always
endmodule |
// ICNBC functions
// Copyright (c) 2014 Dominic Spill, Tariq Bashir
// This file is part of Unambiguous Encapsulation
// License: GPL v2
//
`timescale 1ns/1ps
module icnbc
#(parameter N = 3,
parameter depth=1024,
parameter width=N, //same as N
parameter addr_sz=$clog2(depth)
)
(input clk,
input rst, //positive reset
input [N-1:0] n,
input [N/2-1:0] min_ld,
input start,
output reg [3:0] codes [N-1:0]
);
localparam [2:0]
IDLE = 0,
CALC_LD = 1,
CLOCK_CALC_LD = 2,
FIND_CODE = 3,
RD_MEM = 4,
OUTPUT_CODES = 5,
CLOCK_OUTPUT_CODES = 6,
DONE = 7;
reg [2:0] state, nxt_state;
reg [3:0] counterl[N-1:0], nxt_counterl[N-1:0], counterh[N-1:0], nxt_counterh[N-1:0];
reg [addr_sz-1:0] codelength, nxt_codelength;
reg [addr_sz-1:0] count, nxt_count;
//sequential block
always @(posedge clk)
if(rst)
begin
state <= #1 IDLE;
counterl <= #1 0;
codelength <= #1 0;
count <= #1 0;
counterh <= #1 0;
end
else
begin
state <= #1 nxt_state;
counterl <= #1 nxt_counterl;
counterh <= #1 nxt_counterh;
codelength <= #1 nxt_codelength;
count <= #1 nxt_count;
end
reg [3:0] summation [N-1:0];
reg [3:0] candidate [N-1:0];
reg wr_en, rd_en;
reg [width-1:0] d_in;
reg [addr_sz-1:0] wr_addr;
reg [width-1:0] d_out;
reg [addr_sz-1:0] rd_addr, r_addr;
reg [width-1:0] code_array[0:depth-1];
//memory
always @(posedge clk)
begin
if (wr_en)
begin
code_array[wr_addr] <= #1 d_in;
end
else if (rd_en)
begin
d_out <= #1 code_array[rd_addr];
end
end // always @ (posedge clk)
//Finite STATE MACHINE
always@*
begin
//defaults
nxt_state = state;
nxt_counterl = counterl;
nxt_counterh = counterh;
nxt_count = count;
nxt_codelength = codelength;
case(state)
IDLE:
begin
if(start)
begin
wr_addr = 0;
wr_en = 1;
d_in = 0;
nxt_codelength = 1;
nxt_state = CALC_LD;
end
end
CALC_LD:
begin
wr_en = 0;
if( (counterh == 1 ) || (codelength == depth -1) )
nxt_state = OUTPUT_CODES;
else
begin
if(counterl == 2**N-1)
nxt_counterh = counterh + 1;
summation = sum(counterl, counterh); //function call
if( summation >= min_ld )
begin
//LD[counterl] = counterl;
candidate = counterl;
nxt_counterl = counterl + 1;
nxt_state = FIND_CODE;
end
else
begin
nxt_counterl = counterl + 1;
nxt_state = CLOCK_CALC_LD;
end
end // else: !if( (counterh == 1 ) || (codelength == depth -1) )
end // case: CALC_LD
CLOCK_CALC_LD:
begin
nxt_state = CALC_LD;
end
FIND_CODE:
begin
if(count < codelength)
begin
rd_en = 1;
rd_addr = count;
nxt_state = RD_MEM;
end
else if(count == codelength)
begin
wr_en = 1;
d_in = candidate;
wr_addr = codelength;
nxt_codelength = codelength + 1;
nxt_count = 0;
nxt_state = CALC_LD;
end
end //FIND_CODE
RD_MEM:
begin
rd_en = 0;
summation = sum(d_out ^ candidate);
if (summation >= min_ld)
begin
nxt_count = count + 1;
nxt_state = FIND_CODE;
end
else
begin
nxt_count = 0;
nxt_state = CALC_LD;
end
end
OUTPUT_CODES:
begin
if( count < codelength)
begin
rd_en = 1;
rd_addr = count;
nxt_count = count + 1;
nxt_state = CLOCK_OUTPUT_CODES;
end
else
nxt_state = DONE;
end // case: OUTPUT_CODE
CLOCK_OUTPUT_CODES:
begin
rd_en = 0;
codes = d_out;
nxt_state = OUTPUT_CODES;
end
DONE:
begin
$display($time,": Done \n");
$finish;
end
endcase // case (state)
end // always@ *
function [N-1:0] sum(
input [3:0] input_vector_a [N-1:0],
input [3:0] input_vector_b [N-1:0]
);
integer k;
reg [N-1:0] temp;
begin
temp = 0;
for(k=0; k < N; k=k+1)
begin
temp = temp + input_vector[k][3:0];
end
sum = temp;
end
endfunction // sum
endmodule // lcbbc
|
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "../framework_defines.vh"
module user_tx_wr_if #(parameter USER_TAG = `AFU_TAG)
(
input wire clk,
input wire rst_n,
input wire reset_interface,
input wire set_if_pipelined,
output wire user_tx_wr_if_empty,
input wire set_if_mem_pipelined,
input wire [57:0] mem_pipeline_addr,
input wire writes_finished,
//--------------------- User RD Request -----------------------------//
// User Module TX RD
input wire [57:0] um_tx_wr_addr,
input wire [USER_TAG-1:0] um_tx_wr_tag,
input wire [511:0] um_tx_data,
input wire um_tx_wr_valid,
output wire um_tx_wr_ready,
// User Module RX RD
output reg [USER_TAG-1:0] um_rx_wr_tag,
output reg um_rx_wr_valid,
//-------------------- to Fthread Controller ------------------------//
output wire usr_arb_tx_wr_valid,
output wire [57:0] usr_arb_tx_wr_addr,
output wire [`IF_TAG-1:0] usr_arb_tx_wr_tag,
output wire [511:0] usr_arb_tx_data,
input wire usr_arb_tx_wr_ready,
input wire usr_arb_rx_wr_valid,
input wire [`IF_TAG-1:0] usr_arb_rx_wr_tag,
output wire [57:0] wif_tx_rd_addr,
output wire [`IF_TAG-1:0] wif_tx_rd_tag,
output wire wif_tx_rd_valid,
input wire wif_tx_rd_ready,
input wire [`IF_TAG-1:0] wif_rx_rd_tag,
input wire [511:0] wif_rx_data,
input wire wif_rx_rd_valid,
//-------------------- To pipeline reader ---------------------------//
input wire usr_pipe_tx_rd_valid,
input wire [`IF_TAG-1:0] usr_pipe_tx_rd_tag,
output wire usr_pipe_tx_rd_ready,
output reg usr_pipe_rx_rd_valid,
output reg [`IF_TAG-1:0] usr_pipe_rx_rd_tag,
output reg [511:0] usr_pipe_rx_data,
input wire usr_pipe_rx_rd_ready
);
wire [512+57+USER_TAG:0] tx_wr_fifo_dout;
wire tx_wr_fifo_valid;
wire tx_wr_fifo_full;
wire tx_wr_fifo_re;
wire tx_wr_fifo_empty;
wire [`IF_TAG-1:0] pipe_rd_pending_fifo_tag;
wire pipe_rd_pending_fifo_valid;
wire pipe_rd_pending_fifo_full;
wire fifo_tx_wr_valid;
wire [57:0] fifo_tx_wr_addr;
wire [USER_TAG+1:0] fifo_tx_wr_tag;
wire [511:0] fifo_tx_data;
wire fifo_tx_wr_ready;
wire [USER_TAG+1:0] fifo_rx_wr_tag;
wire fifo_rx_wr_valid;
wire usr_tx_wr_ready;
wire [USER_TAG-1:0] usr_rx_wr_tag;
wire usr_rx_wr_valid;
wire fifo_done;
reg wr_if_pipelined = 0;
reg in_memory_pipeline = 0;
reg [57:0] fifo_base_addr;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Pipelining Control Flags ////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (~rst_n | reset_interface) begin
wr_if_pipelined <= 0;
in_memory_pipeline <= 0;
fifo_base_addr <= 0;
end
else begin
if(set_if_pipelined) begin
wr_if_pipelined <= 1'b1;
end
fifo_base_addr <= mem_pipeline_addr;
if(fifo_done) begin
in_memory_pipeline <= 1'b0;
end
else if(set_if_mem_pipelined) begin
in_memory_pipeline <= 1'b1;
end
end
end
assign user_tx_wr_if_empty = (in_memory_pipeline)? fifo_done : tx_wr_fifo_empty & ~fifo_tx_wr_valid;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Writer Requests FIFO /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
quick_fifo #(.FIFO_WIDTH(512 + 58 + USER_TAG),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD((2**9) - 8)
) tx_wr_fifo(
.clk (clk),
.reset_n (rst_n & ~reset_interface),
.din ({um_tx_wr_tag, um_tx_wr_addr, um_tx_data}),
.we (um_tx_wr_valid),
.re (tx_wr_fifo_re),
.dout (tx_wr_fifo_dout),
.empty (tx_wr_fifo_empty),
.valid (tx_wr_fifo_valid),
.full (tx_wr_fifo_full),
.count (),
.almostfull ()
);
assign um_tx_wr_ready = ~tx_wr_fifo_full;
assign tx_wr_fifo_re = (wr_if_pipelined)? usr_pipe_rx_rd_ready & pipe_rd_pending_fifo_valid : usr_tx_wr_ready;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Accesses To Main Memory /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Pass through in-memory FIFO
sw_fifo_writer #(.USER_TAG(USER_TAG) )
sw_fifo_writer(
.clk (clk),
.rst_n (rst_n & ~reset_interface),
//-------------------------------------------------//
.fifo_base_addr (fifo_base_addr),
.setup_fifo (in_memory_pipeline & ~fifo_done),
.writes_finished (writes_finished & tx_wr_fifo_empty),
.fifo_done (fifo_done),
//--------------------- FIFO to QPI ----------------//
// TX RD
.fifo_tx_rd_addr (wif_tx_rd_addr),
.fifo_tx_rd_tag (wif_tx_rd_tag),
.fifo_tx_rd_valid (wif_tx_rd_valid),
.fifo_tx_rd_ready (wif_tx_rd_ready),
// TX WR
.fifo_tx_wr_addr (fifo_tx_wr_addr),
.fifo_tx_wr_tag (fifo_tx_wr_tag),
.fifo_tx_wr_valid (fifo_tx_wr_valid),
.fifo_tx_data (fifo_tx_data),
.fifo_tx_wr_ready (fifo_tx_wr_ready),
// RX RD
.fifo_rx_rd_tag (wif_rx_rd_tag),
.fifo_rx_data (wif_rx_data),
.fifo_rx_rd_valid (wif_rx_rd_valid),
// RX WR
.fifo_rx_wr_valid (fifo_rx_wr_valid),
.fifo_rx_wr_tag (fifo_rx_wr_tag),
///////////////////////// User Logic Interface ////////////////////
.usr_tx_wr_tag (tx_wr_fifo_dout[512+57+USER_TAG:570]),
.usr_tx_wr_valid (tx_wr_fifo_valid & ~wr_if_pipelined),
.usr_tx_wr_addr (tx_wr_fifo_dout[569:512]),
.usr_tx_data (tx_wr_fifo_dout[511:0]),
.usr_tx_wr_ready (usr_tx_wr_ready),
.usr_rx_wr_tag (usr_rx_wr_tag),
.usr_rx_wr_valid (usr_rx_wr_valid)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Requests Ordering Module ////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
order_module_backpressure_wr #(
.TAG_WIDTH(7),
.OUT_TAG_WIDTH(`IF_TAG),
.USER_TAG_WIDTH(USER_TAG+2))
omodule(
.clk (clk),
.rst_n (rst_n & ~reset_interface),
//-------------------------------------------------//
// input requests
.usr_tx_wr_addr (fifo_tx_wr_addr),
.usr_tx_wr_tag (fifo_tx_wr_tag),
.usr_tx_wr_valid (fifo_tx_wr_valid),
.usr_tx_data (fifo_tx_data),
.usr_tx_wr_ready (fifo_tx_wr_ready),
// TX RD
.ord_tx_wr_addr (usr_arb_tx_wr_addr),
.ord_tx_wr_tag (usr_arb_tx_wr_tag),
.ord_tx_wr_valid (usr_arb_tx_wr_valid),
.ord_tx_data (usr_arb_tx_data),
.ord_tx_wr_ready (usr_arb_tx_wr_ready),
// RX RD
.ord_rx_wr_tag (usr_arb_rx_wr_tag[7:0]),
.ord_rx_wr_valid (usr_arb_rx_wr_valid),
//
.usr_rx_wr_tag (fifo_rx_wr_tag),
.usr_rx_wr_valid (fifo_rx_wr_valid),
.usr_rx_wr_ready (1'b1)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Direct AFU-AFU Pipeline /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//-------------------------------------------//
// Pipe RX RD
// data, tag
always @(posedge clk) begin
if(usr_pipe_rx_rd_ready) begin
usr_pipe_rx_rd_tag <= pipe_rd_pending_fifo_tag;
usr_pipe_rx_data <= tx_wr_fifo_dout[511:0];
end
end
// valid
always @(posedge clk) begin
if (~rst_n) begin
usr_pipe_rx_rd_valid <= 0;
end
else if(usr_pipe_rx_rd_ready) begin
usr_pipe_rx_rd_valid <= pipe_rd_pending_fifo_valid & tx_wr_fifo_valid;
end
end
//--------------------------------------------//
// pipe_rd_pending_fifo
quick_fifo #(.FIFO_WIDTH(`IF_TAG),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD((2**9) - 8)
) pipe_rd_pending_fifo(
.clk (clk),
.reset_n (rst_n),
.din (usr_pipe_tx_rd_tag),
.we (usr_pipe_tx_rd_valid & wr_if_pipelined),
.re (tx_wr_fifo_valid & usr_pipe_rx_rd_ready),
.dout (pipe_rd_pending_fifo_tag),
.empty (),
.valid (pipe_rd_pending_fifo_valid),
.full (pipe_rd_pending_fifo_full),
.count (),
.almostfull ()
);
assign usr_pipe_tx_rd_ready = ~pipe_rd_pending_fifo_full;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Write Request Responses /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// tag
always @(posedge clk) begin
if (wr_if_pipelined) begin
um_rx_wr_tag <= tx_wr_fifo_dout[512+57+USER_TAG:570];
end
else begin
um_rx_wr_tag <= fifo_rx_wr_tag;//[USER_TAG-1:0];
end
end
// valid
always @(posedge clk) begin
if (~rst_n) begin
// reset
um_rx_wr_valid <= 0;
end
else if (wr_if_pipelined) begin
um_rx_wr_valid <= usr_pipe_rx_rd_ready & pipe_rd_pending_fifo_valid & tx_wr_fifo_valid;
end
else begin
um_rx_wr_valid <= usr_rx_wr_valid;
end
end
endmodule
|
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* if "ack" is 1, then current input has been used. */
module f_permutation(clk, reset, in, in_ready, ack, out, out_ready);
input clk, reset;
input [575:0] in;
input in_ready;
output ack;
output reg [1599:0] out;
output reg out_ready;
reg [10:0] i; /* select round constant */
wire [1599:0] round_in, round_out;
wire [63:0] rc1, rc2;
wire update;
wire accept;
reg calc; /* == 1: calculating rounds */
assign accept = in_ready & (~ calc); // in_ready & (i == 0)
always @ (posedge clk)
if (reset) i <= 0;
else i <= {i[9:0], accept};
always @ (posedge clk)
if (reset) calc <= 0;
else calc <= (calc & (~ i[10])) | accept;
assign update = calc | accept;
assign ack = accept;
always @ (posedge clk)
if (reset)
out_ready <= 0;
else if (accept)
out_ready <= 0;
else if (i[10]) // only change at the last round
out_ready <= 1;
assign round_in = accept ? {in ^ out[1599:1599-575], out[1599-576:0]} : out;
rconst2in1
rconst_ ({i, accept}, rc1, rc2);
round2in1
round_ (round_in, rc1, rc2, round_out);
always @ (posedge clk)
if (reset)
out <= 0;
else if (update)
out <= round_out;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 5-input Dynamically Reconfigurable Look-Up-Table with Carry and Clock Enable
// /___/ /\ Filename : CFGLUT5.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision
// 12/27/05 - Initial version.
// 12/13/11 - 524859 - Added `celldefine and `endcelldefine
// 05/13/13 - add IS_CLK_INVERTED
// End Revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`celldefine
module CFGLUT5 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output CDO,
output O5,
output O6,
input CDI,
input CE,
input CLK,
input I0,
input I1,
input I2,
input I3,
input I4
);
`ifdef XIL_TIMING
wire CDI_dly;
wire CE_dly;
wire CLK_dly;
`endif
reg [31:0] data = INIT;
reg first_time = 1'b1;
initial
begin
assign data = INIT;
first_time <= #100000 1'b0;
`ifdef XIL_TIMING
while ((((CLK_dly !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) ||
((CLK_dly !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) &&
(first_time == 1'b1)) #1000;
`else
while ((((CLK !== 1'b0) && (IS_CLK_INVERTED == 1'b0)) ||
((CLK !== 1'b1) && (IS_CLK_INVERTED == 1'b1))) &&
(first_time == 1'b1)) #1000;
`endif
deassign data;
end
`ifdef XIL_TIMING
generate
if (IS_CLK_INVERTED == 1'b0) begin : generate_block1
always @(posedge CLK_dly) begin
if (CE_dly == 1'b1) begin
data[31:0] <= {data[30:0], CDI_dly};
end
end
end else begin : generate_block1
always @(negedge CLK_dly) begin
if (CE_dly == 1'b1) begin
data[31:0] <= {data[30:0], CDI_dly};
end
end
end
endgenerate
`else
generate
if (IS_CLK_INVERTED == 1'b0) begin : generate_block1
always @(posedge CLK) begin
if (CE == 1'b1) begin
data[31:0] <= {data[30:0], CDI};
end
end
end else begin : generate_block1
always @(negedge CLK) begin
if (CE == 1'b1) begin
data[31:0] <= {data[30:0], CDI};
end
end
end
endgenerate
`endif
assign O6 = data[{I4,I3,I2,I1,I0}];
assign O5 = data[{1'b0,I3,I2,I1,I0}];
assign CDO = data[31];
`ifdef XIL_TIMING
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_ce_clk_en_p;
wire sh_ce_clk_en_n;
always @(notifier)
data[0] = 1'bx;
assign sh_clk_en_p = ~IS_CLK_INVERTED;
assign sh_clk_en_n = IS_CLK_INVERTED;
assign sh_ce_clk_en_p = CE && ~IS_CLK_INVERTED;
assign sh_ce_clk_en_n = CE && IS_CLK_INVERTED;
`endif
specify
(CLK => CDO) = (100:100:100, 100:100:100);
(CLK => O5) = (100:100:100, 100:100:100);
(CLK => O6) = (100:100:100, 100:100:100);
(I0 => CDO) = (0:0:0, 0:0:0);
(I0 => O5) = (0:0:0, 0:0:0);
(I0 => O6) = (0:0:0, 0:0:0);
(I1 => CDO) = (0:0:0, 0:0:0);
(I1 => O5) = (0:0:0, 0:0:0);
(I1 => O6) = (0:0:0, 0:0:0);
(I2 => CDO) = (0:0:0, 0:0:0);
(I2 => O5) = (0:0:0, 0:0:0);
(I2 => O6) = (0:0:0, 0:0:0);
(I3 => CDO) = (0:0:0, 0:0:0);
(I3 => O5) = (0:0:0, 0:0:0);
(I3 => O6) = (0:0:0, 0:0:0);
(I4 => CDO) = (0:0:0, 0:0:0);
(I4 => O5) = (0:0:0, 0:0:0);
(I4 => O6) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, negedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,CDI_dly);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly);
$setuphold (negedge CLK, posedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,CDI_dly);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly);
$setuphold (posedge CLK, negedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,CDI_dly);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly);
$setuphold (posedge CLK, posedge CDI, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,CDI_dly);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/*
* Copyright (c) 2015, Arch Labolatory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module ao486_rst_controller
(
input wire clk_sys,
input wire rst,
output reg ao486_rst,
input wire [1:0] address,
input wire write,
input wire [31:0] writedata
);
always @(posedge clk_sys) begin
if(rst) begin
ao486_rst <= 1;
end else begin
if(write && writedata[0] == 1'b0 && address == 4'b0000)
ao486_rst <= 0;
else if(write && writedata[0] == 1'b1 && address == 4'b0000)
ao486_rst <= 1;
end
end
endmodule
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : clk_gen.v
//Project Name : azpr_soc
//Description : the digital top of the chip.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/chip.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-11-23 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.23 - lichangbeiju - Change the coding style.
//2016.11.22 - lichangbeiju - Add io port.
//****************************************************************************************************
`include "sys_include.h"
module clk_gen (
input wire clk_ref,
input wire reset_sw,
output wire clk,
output wire clk_n,
output wire chip_reset
);
wire locked;
wire dcm_reset;
assign locked = 1'b1;
assign dcm_reset = (reset_sw == `RESET_ENABLE) ? `ENABLE : `DISABLE;
assign chip_reset = ((reset_sw == `RESET_ENABLE) || (locked == `DISABLE)) ?
`RESET_ENABLE : `RESET_DISABLE;
// /********** Xilinx DCM (Digitl Clock Manager) **********/
// x_s3e_dcm x_s3e_dcm (
// .CLKIN_IN (clk_ref),
// .RST_IN (dcm_reset),
// .CLK0_OUT (clk),
// .CLK180_OUT (clk_n),
// .LOCKED_OUT (locked)
//);
assign clk = clk_ref;
assign clk_n = ~clk_ref;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVP_1_V
`define SKY130_FD_SC_HDLL__EINVP_1_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvp_1 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvp_1 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVP_1_V
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
`include "hi_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/10/2016 04:46:19 PM
// Design Name:
// Module Name: exp_operation
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_Operation
#(parameter EW = 8) //Exponent Width
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,
input wire load_b_i,
input wire [EW-1:0] Data_A_i,
input wire [EW-1:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW-1:0] Data_Result_o,
output wire Overflow_flag_o,
output wire Underflow_flag_o
);
//wire [EW-1:0] Data_B;
wire [EW:0] Data_S;
/////////////////////////////////////////7
//genvar j;
//for (j=0; j<EW; j=j+1)begin
// assign Data_B[j] = PreData_B_i[j] ^ Add_Subt_i;
//end
/////////////////////////////////////////
add_sub_carry_out #(.W(EW)) exp_add_subt(
.op_mode (Add_Subt_i),
.Data_A (Data_A_i),
.Data_B (Data_B_i),
.Data_S (Data_S)
);
//assign Overflow_flag_o = 1'b0;
//assign Underflow_flag_o = 1'b0;
Comparators #(.W_Exp(EW+1)) array_comparators(
.exp(Data_S),
.overflow(Overflow_flag),
.underflow(Underflow_flag)
);
RegisterAdd #(.W(EW)) exp_result(
.clk (clk),
.rst (rst),
.load (load_a_i),
.D (Data_S[EW-1:0]),
.Q (Data_Result_o)
);
RegisterAdd #(.W(1)) Overflow (
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(Overflow_flag),
.Q(Overflow_flag_o)
);
RegisterAdd #(.W(1)) Underflow (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Underflow_flag),
.Q(Underflow_flag_o)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/10/2016 04:46:19 PM
// Design Name:
// Module Name: exp_operation
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_Operation
#(parameter EW = 8) //Exponent Width
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,
input wire load_b_i,
input wire [EW-1:0] Data_A_i,
input wire [EW-1:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW-1:0] Data_Result_o,
output wire Overflow_flag_o,
output wire Underflow_flag_o
);
//wire [EW-1:0] Data_B;
wire [EW:0] Data_S;
/////////////////////////////////////////7
//genvar j;
//for (j=0; j<EW; j=j+1)begin
// assign Data_B[j] = PreData_B_i[j] ^ Add_Subt_i;
//end
/////////////////////////////////////////
add_sub_carry_out #(.W(EW)) exp_add_subt(
.op_mode (Add_Subt_i),
.Data_A (Data_A_i),
.Data_B (Data_B_i),
.Data_S (Data_S)
);
//assign Overflow_flag_o = 1'b0;
//assign Underflow_flag_o = 1'b0;
Comparators #(.W_Exp(EW+1)) array_comparators(
.exp(Data_S),
.overflow(Overflow_flag),
.underflow(Underflow_flag)
);
RegisterAdd #(.W(EW)) exp_result(
.clk (clk),
.rst (rst),
.load (load_a_i),
.D (Data_S[EW-1:0]),
.Q (Data_Result_o)
);
RegisterAdd #(.W(1)) Overflow (
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(Overflow_flag),
.Q(Overflow_flag_o)
);
RegisterAdd #(.W(1)) Underflow (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Underflow_flag),
.Q(Underflow_flag_o)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/10/2016 04:46:19 PM
// Design Name:
// Module Name: exp_operation
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_Operation
#(parameter EW = 8) //Exponent Width
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,
input wire load_b_i,
input wire [EW-1:0] Data_A_i,
input wire [EW-1:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW-1:0] Data_Result_o,
output wire Overflow_flag_o,
output wire Underflow_flag_o
);
//wire [EW-1:0] Data_B;
wire [EW:0] Data_S;
/////////////////////////////////////////7
//genvar j;
//for (j=0; j<EW; j=j+1)begin
// assign Data_B[j] = PreData_B_i[j] ^ Add_Subt_i;
//end
/////////////////////////////////////////
add_sub_carry_out #(.W(EW)) exp_add_subt(
.op_mode (Add_Subt_i),
.Data_A (Data_A_i),
.Data_B (Data_B_i),
.Data_S (Data_S)
);
//assign Overflow_flag_o = 1'b0;
//assign Underflow_flag_o = 1'b0;
Comparators #(.W_Exp(EW+1)) array_comparators(
.exp(Data_S),
.overflow(Overflow_flag),
.underflow(Underflow_flag)
);
RegisterAdd #(.W(EW)) exp_result(
.clk (clk),
.rst (rst),
.load (load_a_i),
.D (Data_S[EW-1:0]),
.Q (Data_Result_o)
);
RegisterAdd #(.W(1)) Overflow (
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(Overflow_flag),
.Q(Overflow_flag_o)
);
RegisterAdd #(.W(1)) Underflow (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Underflow_flag),
.Q(Underflow_flag_o)
);
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
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