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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDLCLKP_4_V
`define SKY130_FD_SC_HDLL__SDLCLKP_4_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdlclkp_4 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdlclkp_4 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDLCLKP_4_V
|
//
// Avalon MM Slave for parallel input/output camera registers
//
module avalon_camera (
// Avalon clock interface signals
input clk,
input reset_n,
// Signals for Avalon-MM slave port
input [4:0] avs_s1_address,
input avs_s1_read,
output reg [31:0] avs_s1_readdata,
input avs_s1_write,
input [31:0] avs_s1_writedata,
// Control signals to export to the image_capture
output avs_export_start_capture,
output [23:0] avs_export_capture_imgsize,
output [31:0] avs_export_buff,
input avs_export_image_captured,
input avs_export_capture_standby,
// Registers to export to the camera_config
output [15:0] avs_export_width,
output [15:0] avs_export_height,
output [15:0] avs_export_start_row,
output [15:0] avs_export_start_column,
output [15:0] avs_export_row_size,
output [15:0] avs_export_column_size,
output [15:0] avs_export_row_mode,
output [15:0] avs_export_column_mode,
output [15:0] avs_export_exposure,
//soft reset
output avs_export_cam_soft_reset_n
);
// Addresses of the registers to control image_capture
`define ADDR_START_CAPTURE 5'h00
`define ADDR_CAPTURE_IMGSIZE 5'h01
`define ADDR_BUFF 5'h02
`define ADDR_IMGCAPTURED 5'h03
`define ADDR_CAPTURE_STANDBY 5'h04
// Addresses of the registers to control camera_config
`define ADDR_WIDTH 5'h09
`define ADDR_HEIGHT 5'h0a
`define ADDR_START_ROW 5'h0b
`define ADDR_START_COLUMN 5'h0c
`define ADDR_ROW_SIZE 5'h0d
`define ADDR_COLUMN_SIZE 5'h0e
`define ADDR_ROW_MODE 5'h0f
`define ADDR_COLUMN_MODE 5'h10
`define ADDR_EXPOSURE 5'h11
// Address of the soft reset
`define SOFT_RESET_N 5'h1F //last address
// Camera configuration registers default values.
parameter WIDTH = 16'd320;
parameter HEIGHT = 16'd240;
parameter START_ROW = 16'h0036;
parameter START_COLUMN = 16'h0010;
parameter ROW_SIZE = 16'h059f;
parameter COLUMN_SIZE = 16'h077f;
parameter ROW_MODE = 16'h0002;
parameter COLUMN_MODE = 16'h0002;
parameter EXPOSURE = 16'h07c0;
// image_capture registers
reg start_capture;
reg [23:0] capture_imgsize;
reg [31:0] buff;
reg imgcaptured;
wire standby;
// camera_config registers
reg [15:0] data_width;
reg [15:0] data_height;
reg [15:0] data_start_row;
reg [15:0] data_start_column;
reg [15:0] data_row_size;
reg [15:0] data_column_size;
reg [15:0] data_row_mode;
reg [15:0] data_column_mode;
reg [15:0] data_exposure;
//soft_reset reg
reg cam_soft_reset_n;
// Read/Write registers
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
start_capture <= 1'b0;
capture_imgsize <= 24'd0;
buff[31:0] <= 32'd0;
data_width[15:0] <= WIDTH[15:0];
data_height[15:0] <= HEIGHT[15:0];
data_start_row[15:0] <= START_ROW[15:0];
data_start_column[15:0] <= START_COLUMN[15:0];
data_row_size[15:0] <= ROW_SIZE[15:0];
data_column_size[15:0] <= COLUMN_SIZE[15:0];
data_row_mode[15:0] <= ROW_MODE[15:0];
data_column_mode[15:0] <= COLUMN_MODE[15:0];
data_exposure[15:0] <= EXPOSURE[15:0];
cam_soft_reset_n <= 1;
end
else begin
if (avs_s1_read) begin
case (avs_s1_address)
// image_capture
`ADDR_START_CAPTURE:
avs_s1_readdata[31:0] <= {31'b0, start_capture};
`ADDR_CAPTURE_IMGSIZE:
avs_s1_readdata[31:0] <= {8'b0, capture_imgsize};
`ADDR_BUFF:
avs_s1_readdata[31:0] <= buff;
`ADDR_IMGCAPTURED:
avs_s1_readdata[31:0] <= {31'b0, imgcaptured};
`ADDR_CAPTURE_STANDBY:
avs_s1_readdata[31:0] <= {31'b0, standby};
// camera_config
`ADDR_WIDTH:
avs_s1_readdata[15:0] <= data_width[15:0];
`ADDR_HEIGHT:
avs_s1_readdata[15:0] <= data_height[15:0];
`ADDR_START_ROW:
avs_s1_readdata[15:0] <= data_start_row[15:0];
`ADDR_START_COLUMN:
avs_s1_readdata[15:0] <= data_start_column[15:0];
`ADDR_ROW_SIZE:
avs_s1_readdata[15:0] <= data_row_size[15:0];
`ADDR_COLUMN_SIZE:
avs_s1_readdata[15:0] <= data_column_size[15:0];
`ADDR_ROW_MODE:
avs_s1_readdata[15:0] <= data_row_mode[15:0];
`ADDR_COLUMN_MODE:
avs_s1_readdata[15:0] <= data_column_mode[15:0];
`ADDR_EXPOSURE:
avs_s1_readdata[15:0] <= data_exposure[15:0];
// soft reset
`SOFT_RESET_N:
avs_s1_readdata[31:0] <= {31'b0, cam_soft_reset_n};
default:
avs_s1_readdata[31:0] <= {32'b0};
endcase
end
// Routine when avs_s1_read is FALSE.
else begin
if (avs_s1_write) begin
case (avs_s1_address)
// image_capture
`ADDR_START_CAPTURE:
start_capture <= avs_s1_writedata[0];
`ADDR_CAPTURE_IMGSIZE:
capture_imgsize <= avs_s1_writedata[23:0];
`ADDR_BUFF:
buff <= avs_s1_writedata[31:0];
//`ADDR_CAPTURE_STANDBY://not writable
// camera_config
`ADDR_WIDTH:
data_width[15:0] <= avs_s1_writedata[15:0];
`ADDR_HEIGHT:
data_height[15:0] <= avs_s1_writedata[15:0];
`ADDR_START_ROW:
data_start_row[15:0] <= avs_s1_writedata[15:0];
`ADDR_START_COLUMN:
data_start_column[15:0] <= avs_s1_writedata[15:0];
`ADDR_ROW_SIZE:
data_row_size[15:0] <= avs_s1_writedata[15:0];
`ADDR_COLUMN_SIZE:
data_column_size[15:0] <= avs_s1_writedata[15:0];
`ADDR_ROW_MODE:
data_row_mode[15:0] <= avs_s1_writedata[15:0];
`ADDR_COLUMN_MODE:
data_column_mode[15:0] <= avs_s1_writedata[15:0];
`ADDR_EXPOSURE:
data_exposure[15:0] <= avs_s1_writedata[15:0];
// soft reset
`SOFT_RESET_N:
cam_soft_reset_n <= avs_s1_writedata[0];
endcase
end
end
end
end
// imgcaptured registers
// This signals come from the capture_image component and may be clocked
// by a different clock. That is why asynchronous set is done here
// to set this signal. The processor uses this signals to know that
// one line has been captured and can read the buffer. The processor is
// in charge of erasing these signals through the avalon bus.
// The standby signal can also be used to know when a capture finished.
always @(posedge clk or negedge reset_n or posedge avs_export_image_captured)
begin
if (avs_export_image_captured)
imgcaptured <= 1'b1;
else if (!reset_n)
imgcaptured <= 1'b0;
else begin
if (avs_s1_write == 1) begin
case (avs_s1_address)
`ADDR_IMGCAPTURED: imgcaptured <= avs_s1_writedata[0];
endcase
end
end
end
// Control signals to export to the image capture
assign avs_export_start_capture = start_capture;
assign avs_export_capture_imgsize = capture_imgsize;
assign avs_export_buff = buff;
assign standby = avs_export_capture_standby;
// Registers to export to the camera_config
assign avs_export_start_row[15:0] = data_start_row[15:0];
assign avs_export_start_column[15:0] = data_start_column[15:0];
assign avs_export_row_size[15:0] = data_row_size[15:0];
assign avs_export_column_size[15:0] = data_column_size[15:0];
assign avs_export_row_mode[15:0] = data_row_mode[15:0];
assign avs_export_column_mode[15:0] = data_column_mode[15:0];
assign avs_export_exposure[15:0] = data_exposure[15:0];
// Registers to export to the camera_config an
assign avs_export_width[15:0] = data_width[15:0];
assign avs_export_height[15:0] = data_height[15:0];
//soft reset
assign avs_export_cam_soft_reset_n = cam_soft_reset_n;
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2009 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
// Major Functions: DE0 TOP
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// --------------------------------------------------------------------
module Alice4
(
//////////////////////// Clock Input ////////////////////////
input CLOCK_50, // 50 MHz
input CLOCK_50_2, // 50 MHz
//////////////////////// Push Button ////////////////////////
input [2:0] BUTTON, // Pushbutton[2:0]
//////////////////////// DPDT Switch ////////////////////////
// input [9:0] SW, // Toggle Switch[9:0]
//////////////////////// 7-SEG Dispaly ////////////////////////
output [6:0] HEX0_D, // Seven Segment Digit 0
output HEX0_DP, // Seven Segment Digit DP 0
output [6:0] HEX1_D, // Seven Segment Digit 1
output HEX1_DP, // Seven Segment Digit DP 1
output [6:0] HEX2_D, // Seven Segment Digit 2
output HEX2_DP, // Seven Segment Digit DP 2
output [6:0] HEX3_D, // Seven Segment Digit 3
output HEX3_DP, // Seven Segment Digit DP 3
//////////////////////////// LED ////////////////////////////
output [9:0] LEDG, // LED Green[9:0]
//////////////////////////// UART ////////////////////////////
// output UART_TXD, // UART Transmitter
// input UART_RXD, // UART Receiver
// output UART_CTS, // UART Clear To Send
// input UART_RTS, // UART Request To Send
/////////////////////// SDRAM Interface ////////////////////////
inout [15:0] DRAM_DQ, // SDRAM Data bus 16 Bits
output [12:0] DRAM_ADDR, // SDRAM Address bus 13 Bits
output DRAM_LDQM, // SDRAM Low-byte Data Mask
output DRAM_UDQM, // SDRAM High-byte Data Mask
output DRAM_WE_N, // SDRAM Write Enable
output DRAM_CAS_N, // SDRAM Column Address Strobe
output DRAM_RAS_N, // SDRAM Row Address Strobe
output DRAM_CS_N, // SDRAM Chip Select
output DRAM_BA_0, // SDRAM Bank Address 0
output DRAM_BA_1, // SDRAM Bank Address 1
output DRAM_CLK, // SDRAM Clock
output DRAM_CKE, // SDRAM Clock Enable
//////////////////////// Flash Interface ////////////////////////
// inout [14:0] FL_DQ, // FLASH Data bus 15 Bits
// inout FL_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
// output [21:0] FL_ADDR, // FLASH Address bus 22 Bits
// output FL_WE_N, // FLASH Write Enable
// output FL_RST_N, // FLASH Reset
// output FL_OE_N, // FLASH Output Enable
// output FL_CE_N, // FLASH Chip Enable
// output FL_WP_N, // FLASH Hardware Write Protect
// output FL_BYTE_N, // FLASH Selects 8/16-bit mode
// input FL_RY, // FLASH Ready/Busy
//////////////////// LCD Module 16X2 ////////////////////////////
// inout [7:0] LCD_DATA, // LCD Data bus 8 bits
// output LCD_BLON, // LCD Back Light ON/OFF
// output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
// output LCD_EN, // LCD Enable
// output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
//////////////////// SD Card Interface ////////////////////////
// inout SD_DAT0, // SD Card Data 0
// inout SD_DAT3, // SD Card Data 3
// inout SD_CMD, // SD Card Command Signal
// output SD_CLK, // SD Card Clock
// input SD_WP_N, // SD Card Write Protect
//////////////////////// PS2 ////////////////////////////////
// inout PS2_KBDAT, // PS2 Keyboard Data
// inout PS2_KBCLK, // PS2 Keyboard Clock
// inout PS2_MSDAT, // PS2 Mouse Data
// inout PS2_MSCLK, // PS2 Mouse Clock
//////////////////////// VGA ////////////////////////////
output VGA_HS, // VGA H_SYNC
output VGA_VS, // VGA V_SYNC
output [3:0] VGA_R, // VGA Red[3:0]
output [3:0] VGA_G, // VGA Green[3:0]
output [3:0] VGA_B, // VGA Blue[3:0]
//////////////////////// GPIO ////////////////////////////////
// input [1:0] GPIO0_CLKIN, // GPIO Connection 0 Clock In Bus
// output [1:0] GPIO0_CLKOUT, // GPIO Connection 0 Clock Out Bus
// inout [31:0] GPIO0_D, // GPIO Connection 0 Data Bus
// input [1:0] GPIO1_CLKIN, // GPIO Connection 1 Clock In Bus
// output [1:0] GPIO1_CLKOUT, // GPIO Connection 1 Clock Out Bus
inout [31:0] GPIO1_D // GPIO Connection 1 Data Bus
);
// Generic useful debug counter.
reg [30:0] counter;
// What's displayed on the 7-segment display.
reg [15:0] debug_number;
reg [15:0] debug_number_nxt;
wire [15:0] debug_number_sdram_test;
// Button for resetting system, active low.
wire reset_n = BUTTON[2];
// The pixel clock of the video output, from the PLL.
wire vga_pixel_clock;
// Host-side VGA parameters.
wire [3:0] m_vga_r;
wire [3:0] m_vga_g;
wire [3:0] m_vga_b;
wire m_vga_request;
wire m_vga_top_of_screen;
reg m_vga_top_of_screen_latched;
// VGA_side VGA parameters.
wire [3:0] s_vga_r;
wire [3:0] s_vga_g;
wire [3:0] s_vga_b;
// Hook up to pins to hardware.
assign VGA_R = s_vga_r;
assign VGA_G = s_vga_g;
assign VGA_B = s_vga_b;
// Whether the SDRAM PLL has locked.
wire sdram_clk_locked;
// Debugging LEDs.
assign LEDG[0] = sdram_clk_locked;
assign LEDG[9:1] = counter[30:22];
// Clock that we're actually running our logic on.
wire our_clock = DRAM_CLK;
reg vga_fifo_clear;
reg vga_fifo_clear_nxt;
wire [11:0] vga_fifo_input;
wire vga_fifo_wrclk;
wire [11:0] vga_fifo_output;
wire vga_fifo_rdempty;
wire [7:0] vga_fifo_wrusedw;
wire vga_fifo_almost_full = vga_fifo_wrusedw[7];
reg vga_fifo_wrreq;
reg vga_fifo_wrreq_nxt;
// State machine states.
localparam STATE_START = 0;
localparam STATE_RESET = 1;
localparam STATE_GOING = 2;
localparam STATE_PAUSED = 3;
localparam STATE_STOPPED = 4;
reg [9:0] x; // [0,640)
reg [9:0] x_nxt;
reg [9:0] y; // [0,480)
reg [9:0] y_nxt;
reg [2:0] state;
reg [2:0] state_nxt;
reg [15:0] pixel_count;
reg [15:0] pixel_count_nxt;
// Convert the debug_number to four hex digits.
SEG7_LUT_4 seg7_lut_4(
.oSEG0(HEX0_D),
.oSEG0_DP(HEX0_DP),
.oSEG1(HEX1_D),
.oSEG1_DP(HEX1_DP),
.oSEG2(HEX2_D),
.oSEG2_DP(HEX2_DP),
.oSEG3(HEX3_D),
.oSEG3_DP(HEX3_DP),
.iDIG(debug_number_sdram_test)
);
// Generate the VGA pixel clock.
Vga_clock vga_clock(
.inclk0(CLOCK_50_2),
.c0(vga_pixel_clock)
);
// Generate all signals for the VGA.
/*
Vga_control vga_control(
// Host Side
.oCurrent_X(),
.oCurrent_Y(),
.oAddress(),
.iRed(m_vga_r),
.iGreen(m_vga_g),
.iBlue(m_vga_b),
.oRequest(m_vga_request),
.oTopOfScreen(m_vga_top_of_screen),
// VGA Side
.oVGA_R(s_vga_r),
.oVGA_G(s_vga_g),
.oVGA_B(s_vga_b),
.oVGA_HS(VGA_HS),
.oVGA_VS(VGA_VS),
.oVGA_BLANK(),
.oVGA_CLOCK(),
// Control Signal
.iCLK(vga_pixel_clock),
.iRST_N(reset_n)
);
*/
// Generate all signals for the LCD.
LCD_control lcd_control(
// Host Side
.iRed(m_lcd_r),
.iGreen(m_lcd_g),
.iBlue(m_lcd_b),
.oCurrent_X(lcd_x),
.oCurrent_Y(lcd_y),
.oAddress(),
.oRequest(),
.oTopOfScreen(),
// LCD Side
.oLCD_R(s_lcd_r),
.oLCD_G(s_lcd_g),
.oLCD_B(s_lcd_b),
.oLCD_HS(lcd_hs),
.oLCD_VS(lcd_vs),
.oLCD_DE(lcd_de),
// Control Signal
.iCLK(vga_pixel_clock),
.iRST_N(reset_n)
);
// FIFO to pass data from RAM to VGA.
VGA_FIFO vga_fifo(
// Inputs.
.aclr(vga_fifo_clear),
.data(vga_fifo_input),
.rdclk(vga_pixel_clock),
.rdreq(m_vga_request),
.wrclk(vga_fifo_wrclk),
.wrreq(vga_fifo_wrreq),
// Outputs.
.q(vga_fifo_output),
.rdempty(vga_fifo_rdempty),
.wrfull(),
.wrusedw(vga_fifo_wrusedw)
);
// PLL for the SDRAM clock.
SDRAM_clock sdram_clock(
.areset(!reset_n),
.inclk0(CLOCK_50),
.c0(DRAM_CLK),
.locked(sdram_clk_locked)
);
// Test of SDRAM.
// Convert from 13 to 12 bits for address.
wire [11:0] dram_addr;
assign DRAM_ADDR = { 1'b0, dram_addr };
SDRAM_test sdram_test(
.reset_n(reset_n),
.dram_dq(DRAM_DQ),
.dram_addr(dram_addr),
.dram_ldqm(DRAM_LDQM),
.dram_udqm(DRAM_UDQM),
.dram_we_n(DRAM_WE_N),
.dram_cas_n(DRAM_CAS_N),
.dram_ras_n(DRAM_RAS_N),
.dram_cs_n(DRAM_CS_N),
.dram_ba_0(DRAM_BA_0),
.dram_ba_1(DRAM_BA_1),
.dram_clk(DRAM_CLK),
.dram_cke(DRAM_CKE),
.dram_clk_locked(sdram_clk_locked),
.debug_number(debug_number_sdram_test)
);
`ifdef NOTDEF
always @(posedge DRAM_CLK or negedge reset_n) begin
if (!reset_n) begin
counter <= 0;
end
else
begin
counter <= counter + 1'b1;
/*
if (counter == 50_000_000) begin
counter <= 0;
end
*/
end
end
`endif
assign vga_fifo_input = (x == 0 || x == 639 || y == 0 || y == 479) ? 12'hF00 :
(x[4] ^ y[4]) ? 12'h000 : 12'hFFF;
assign vga_fifo_wrclk = our_clock;
// Use magenta if the FIFO is empty.
assign m_vga_r = vga_fifo_rdempty ? 4'b1111 : vga_fifo_output[11:8];
assign m_vga_g = vga_fifo_rdempty ? 4'b0000 : vga_fifo_output[7:4];
assign m_vga_b = vga_fifo_rdempty ? 4'b1111 : vga_fifo_output[3:0];
// Initialize our variables.
initial begin
counter <= 0;
debug_number <= 16'h0000;
end
// Compute the next values of the input to the FIFO.
always @(*) begin
state_nxt = state;
x_nxt = x;
y_nxt = y;
vga_fifo_clear_nxt = vga_fifo_clear;
vga_fifo_wrreq_nxt = 0;
pixel_count_nxt = pixel_count;
debug_number_nxt = debug_number;
case (state)
STATE_START: begin
state_nxt = STATE_RESET;
vga_fifo_clear_nxt = 1;
// debug_number_nxt = debug_number + 1;
end
STATE_RESET: begin
state_nxt = STATE_GOING;
vga_fifo_clear_nxt = 0;
x_nxt = 1'b0;
y_nxt = 1'b0;
pixel_count_nxt = 1;
end
STATE_GOING: begin
if (vga_fifo_almost_full) begin
state_nxt = STATE_PAUSED;
end else begin
if (x == 639) begin
x_nxt = 1'b0;
if (y == 479) begin
state_nxt = STATE_STOPPED;
// debug_number_nxt = pixel_count;
end else begin
y_nxt = y + 1'b1;
vga_fifo_wrreq_nxt = 1'b1;
pixel_count_nxt = pixel_count + 1'b1;
end
end else begin
x_nxt = x + 1'b1;
vga_fifo_wrreq_nxt = 1'b1;
pixel_count_nxt = pixel_count + 1'b1;
end
end
end
STATE_PAUSED: begin
if (!vga_fifo_almost_full) begin
state_nxt = STATE_GOING;
end
end
STATE_STOPPED: begin
// Nothing.
end
endcase
end
// Clock next values into the current ones.
always @(posedge our_clock) begin
m_vga_top_of_screen_latched <= m_vga_top_of_screen;
if (m_vga_top_of_screen_latched) begin
state <= STATE_START;
x <= 0;
y <= 0;
vga_fifo_clear <= 0;
vga_fifo_wrreq <= 0;
end else begin
state <= state_nxt;
x <= x_nxt;
y <= y_nxt;
vga_fifo_clear <= vga_fifo_clear_nxt;
vga_fifo_wrreq <= vga_fifo_wrreq_nxt;
end
pixel_count <= pixel_count_nxt;
debug_number <= debug_number_nxt;
end
// ****************** Nothing used below here.
`ifdef NOTDEF
reg signed [19:0] w0_row;
reg signed [19:0] w1_row;
reg signed [19:0] w2_row;
wire signed [19:0] w0;
wire signed [19:0] w1;
wire signed [19:0] w2;
assign w0 = 128_400 + m_vga_x*(-140) + m_vga_y*(-220);
assign w1 = -6000 + m_vga_x*(280) + m_vga_y*(-220);
assign w2 = -30000 + m_vga_x*(-140) + m_vga_y*(440);
wire insideTriangle = 1; // w0 >= 0 && w1 >= 0 && w2 >= 0;
//assign m_vga_r = insideTriangle ? (w0/6160) : 4'b0000;
//assign m_vga_g = insideTriangle ? (w1/6160) : 4'b0000;
//assign m_vga_b = insideTriangle ? (w2/6160) : 4'b0000;
`endif
`ifdef NOTDEF
always @(m_vga_x or m_vga_y)
begin
if (m_vga_x == 0 && m_vga_y == 0)
begin
w0_row <= 128_400;
w1_row <= -6_000;
w2_row <= -30_000;
w0 <= w0_row;
w1 <= w1_row;
w2 <= w2_row;
end
else if (m_vga_x == 0)
begin
w0_row <= w0_row - 220;
w1_row <= w1_row - 220;
w2_row <= w2_row + 440;
w0 <= w0_row;
w1 <= w1_row;
w2 <= w2_row;
end
else
begin
w0 <= w0 - 140;
w1 <= w1 + 280;
w2 <= w2 - 140;
end
end
`endif
// LCD test code.
reg [7:0] horiz_prescale;
reg [2:0] color_counter;
wire [7:0] red = color_counter[0] ? 8'hFF : 8'h00;
wire [7:0] green = color_counter[1] ? 8'hFF : 8'h00;
wire [7:0] blue = color_counter[2] ? 8'hFF : 8'h00;
wire [9:0] lcd_x;
wire [9:0] lcd_y;
wire lcd_checkerboard = lcd_x[4] ^ lcd_y[4];
wire [7:0] m_lcd_r = lcd_checkerboard ? red : 8'h00;
wire [7:0] m_lcd_g = lcd_checkerboard ? green : 8'h00;
wire [7:0] m_lcd_b = lcd_checkerboard ? blue : 8'h00;
wire [7:0] s_lcd_r;
wire [7:0] s_lcd_g;
wire [7:0] s_lcd_b;
wire lcd_hs;
wire lcd_vs;
wire lcd_de;
wire lcd_display_on = 1'b1;
assign { GPIO1_D[16:15], GPIO1_D[13:10] } = s_lcd_r[7:2];
assign { GPIO1_D[23:19], GPIO1_D[17] } = s_lcd_g[7:2];
assign { GPIO1_D[31], GPIO1_D[29:26], GPIO1_D[24] } = s_lcd_b[7:2];
assign GPIO1_D[2] = vga_pixel_clock;
assign GPIO1_D[4] = lcd_hs;
assign GPIO1_D[5] = lcd_vs;
assign GPIO1_D[7] = lcd_de;
assign GPIO1_D[8] = lcd_display_on;
always @(posedge vga_pixel_clock) begin
if (!lcd_de) begin
horiz_prescale <= 8'd0;
color_counter <= 3'd1;
end else begin
if (horiz_prescale == 8'd115) begin
horiz_prescale <= 8'd0;
color_counter <= color_counter + 3'd1;
end else begin
horiz_prescale <= horiz_prescale + 8'd1;
end
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : axi_basic_tx.v
// Version : 2.3
//----------------------------------------------------------------------------//
// File: axi_basic_tx.v //
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [STRB_WIDTH-1:0] s_axis_tx_tstrb, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tstrb( s_axis_tx_tstrb ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tecrc_gen( trn_tecrc_gen ),
.trn_lnk_up( trn_lnk_up ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av( trn_tbuf_av ),
.trn_tdst_rdy( trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule
|
// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_7"),
.ENUM_MEM_IF_TCWL ("TCWL_7"),
.ENUM_MEM_IF_TFAW ("TFAW_15"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (120),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
module jt12_pcm(
input rst,
input clk,
input clk_en /* synthesis direct_enable */,
input zero,
input signed [8:0] pcm,
input pcm_wr,
output reg signed [8:0] pcm_resampled
);
// reg [2:0] ratesel;
// reg [3:0] cnt8;
// reg wrcnt, wrclr;
reg last_zero;
wire zero_edge = !last_zero && zero;
/*
always @(posedge clk)
if(rst) begin
cnt8 <= 4'd0;
wrclr <= 1'd0;
ratesel <= 3'd1;
wrcnt <= 1'b0;
end else if(clk_en) begin
if( pcm_wr ) begin
if( wrcnt ) begin
// case( cnt8[3:2] )
// 2'd3: ratesel <= 3'b111; // x8
// 2'd2: ratesel <= 3'b011; // x4
// 2'd1: ratesel <= 3'b001; // x2
// 2'd0: ratesel <= 3'b000; // x1
// endcase
cnt8 <= 4'd0;
wrcnt <= 1'b0;
end
else wrcnt <= 1'b1;
end else
if( cnt8!=4'hf && zero ) cnt8 <= cnt8 + 4'd1;
end
*/
// up-rate PCM samples
reg rate1, rate2; //, rate4, rate8;
reg cen1, cen2; //, cen4, cen8;
always @(posedge clk, posedge rst)
if(rst)
rate2 <= 1'b0;
else begin
last_zero <= zero;
rate1 <= zero_edge;
if(zero_edge) begin
rate2 <= ~rate2;
// if(rate2) begin
// rate4 <= ~rate4;
// if(rate4) rate8<=~rate8;
// end
end
end
always @(posedge clk) begin
cen1 <= rate1;
cen2 <= rate1 && rate2;
// cen4 <= rate1 && rate2 && rate4;
// cen8 <= rate1 && rate2 && rate4 && rate8;
end
wire signed [8:0] pcm3; //,pcm2, pcm1;
//always @(posedge clk) if( clk_en )
// pcm_resampled <= ratesel[0] ? pcm3 : pcm;
always @(*)
pcm_resampled = pcm3;
// rate x2
//wire signed [8:0] pcm_in2 = ratesel[1] ? pcm2 : pcm;
jt12_interpol #(.calcw(10),.inw(9),.rate(2),.m(1),.n(2))
u_uprate_3(
.clk ( clk ),
.rst ( rst ),
.cen_in ( cen2 ),
.cen_out( cen1 ),
// .snd_in ( pcm_in2 ),
.snd_in ( pcm ),
.snd_out( pcm3 )
);
/*
// rate x2
wire signed [8:0] pcm_in1 = ratesel[2] ? pcm1 : pcm;
jt12_interpol #(.calcw(10),.inw(9),.rate(2),.m(1),.n(2))
u_uprate_2(
.clk ( clk ),
.rst ( rst ),
.cen_in ( cen4 ),
.cen_out( cen2 ),
.snd_in ( pcm_in1 ),
.snd_out( pcm2 )
);
// rate x2
jt12_interpol #(.calcw(10),.inw(9),.rate(2),.m(1),.n(2))
u_uprate_1(
.clk ( clk ),
.rst ( rst ),
.cen_in ( cen8 ),
.cen_out( cen4 ),
.snd_in ( pcm ),
.snd_out( pcm1 )
);
*/
endmodule // jt12_pcm |
`include "elink_constants.vh"
module erx_clocks (/*AUTOARG*/
// Outputs
rx_lclk, rx_lclk_div4, rx_active, erx_nreset, erx_io_nreset,
// Inputs
sys_nreset, soft_reset, tx_active, sys_clk, rx_clkin
);
//Frequency Settings (Mhz)
parameter FREQ_RXCLK = 300;
parameter FREQ_IDELAY = 200;
parameter RXCLK_PHASE = 0; // 270;
parameter PLL_VCO_MULT = 4; // RX
parameter TARGET = `CFG_TARGET; // "XILINX", "ALTERA" etc
//Override reset counter size for simulation
`ifdef TARGET_SIM
parameter RCW = 4; // reset counter width
`else
parameter RCW = 8; // reset counter width
`endif
//Don't touch these! (derived parameters)
localparam real RXCLK_PERIOD = 1000.000000 / FREQ_RXCLK; //? Why is the period needed here?
localparam integer IREF_DIVIDE = PLL_VCO_MULT * FREQ_RXCLK / FREQ_IDELAY;
localparam integer RXCLK_DIVIDE = PLL_VCO_MULT; //1:1
//Input clock, reset, config interface
input sys_nreset; // active low system reset (hw)
input soft_reset; // rx enable signal (sw)
input tx_active; // tx active input
//Main input clocks
input sys_clk; // always on input clk cclk/TX MMCM
input rx_clkin; // input clk for RX only PLL
//RX Clocks
output rx_lclk; // rx high speed clock for DDR IO
output rx_lclk_div4; // rx slow clock for logic
//Reset
output rx_active; // rx active
output erx_nreset; // reset for rx core logic
output erx_io_nreset; // io reset (synced to high speed clock)
//############
//# WIRES
//############
//Idelay controller
wire idelay_reset;
wire idelay_ready; //ignore this?
wire idelay_ref_clk;
//pll outputs
wire rx_lclk_pll;
wire rx_lclk_div4_pll;
wire idelay_ref_clk_pll;
//PLL
wire rx_lclk_fb;
wire rx_nreset_in;
//###########################
// RESET STATE MACHINE
//###########################
reg [RCW:0] reset_counter = 'b0; //works b/c of free running counter!
reg heartbeat;
wire pll_locked_sync;
reg [2:0] reset_state;
wire pll_reset;
reg rx_nreset;
wire pll_locked;
//Reset
assign rx_nreset_in = sys_nreset & tx_active;
//wrap around counter that generates a 1 cycle heartbeat
always @ (posedge sys_clk)
begin
reset_counter[RCW-1:0] <= reset_counter[RCW-1:0]+1'b1;
heartbeat <= ~(|reset_counter[RCW-1:0]);
end
`define RX_RESET_ALL 3'b000
`define RX_START_PLL 3'b001
`define RX_ACTIVE 3'b010
//Reset sequence state machine
always @ (posedge sys_clk or negedge rx_nreset_in)
if(!rx_nreset_in)
reset_state[2:0] <= `RX_RESET_ALL;
else if(heartbeat)
case(reset_state[2:0])
`RX_RESET_ALL :
if(~soft_reset)
reset_state[2:0] <= `RX_START_PLL;
`RX_START_PLL :
if(pll_locked_sync & idelay_ready)
reset_state[2:0] <= `RX_ACTIVE;
`RX_ACTIVE:
if(soft_reset)
reset_state[2:0] <= `RX_RESET_ALL; //stay there until next reset
endcase // case (reset_state[2:0])
assign pll_reset = (reset_state[2:0]==`RX_RESET_ALL);
assign idelay_reset = (reset_state[2:0]==`RX_RESET_ALL);
//Reset for RX (pipeline to improve timing)
always @ (posedge sys_clk)
rx_nreset <= ~(reset_state[2:0] != `RX_ACTIVE);
//active indicator
assign rx_active = (reset_state[2:0] == `RX_ACTIVE);
//#############################
//#RESET SYNCING
//#############################
oh_rsync rsync_io (// Outputs
.nrst_out (erx_io_nreset),
// Inputs
.clk (rx_lclk),
.nrst_in (rx_nreset)
);
oh_rsync rsync_core (// Outputs
.nrst_out (erx_nreset),
// Inputs
.clk (rx_lclk_div4),
.nrst_in (rx_nreset)
);
generate
if(TARGET=="XILINX")
begin
//###########################
// PLL RX
//###########################
PLLE2_ADV
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(PLL_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(RXCLK_PERIOD),
.CLKOUT0_DIVIDE(128),
.CLKOUT1_DIVIDE(128),
.CLKOUT2_DIVIDE(128),
.CLKOUT3_DIVIDE(IREF_DIVIDE), // idelay ref clk
.CLKOUT4_DIVIDE(RXCLK_DIVIDE), // rx_lclk
.CLKOUT5_DIVIDE(RXCLK_DIVIDE*4), // rx_lclk_div4
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),//RXCLK_PHASE
.CLKOUT5_PHASE(0.0),//RXCLK_PHASE/4
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) pll_rx
(
.CLKOUT0(),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(idelay_ref_clk_pll),
.CLKOUT4(rx_lclk_pll),
.CLKOUT5(rx_lclk_div4_pll),
.PWRDWN(1'b0),
.RST(pll_reset),
.CLKFBIN(rx_lclk_fb),
.CLKFBOUT(rx_lclk_fb),
.CLKIN1(rx_clkin),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(7'b0),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'b0),
.DWE(1'b0),
.DRDY(),//??
.DO(), //??
.LOCKED(pll_locked)
);
//Clock network
BUFG i_lclk_bufg (.I(rx_lclk_pll), .O(rx_lclk)); //300Mhz
BUFG i_lclk_div4_bufg (.I(rx_lclk_div4_pll), .O(rx_lclk_div4)); //(300Mhz/4)
BUFG i_idelay_bufg (.I(idelay_ref_clk_pll),.O(idelay_ref_clk));//idelay ctrl clock
//two clock synchronizer for lock signal
oh_dsync dsync (.dout (pll_locked_sync),
.clk (sys_clk),
.nreset (1'b1),
.din (pll_locked)
);
//###########################
// Idelay controller
//###########################
`define IDELAYCTRL_WONT_SYNTHESIZE
`ifdef IDELAYCTRL_WONT_SYNTHESIZE
assign idelay_ready = 'b1;
`else
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYCTRL
#(
.SIM_DEVICE("ULTRASCALE_PLUS_ES2")
) idelayctrl_inst
(
.RDY(idelay_ready), // check ready flag in reset sequence?
.REFCLK(idelay_ref_clk),//200MHz clk (78ps tap delay)
.RST(idelay_reset)
);
`endif
end // if (TARGET=="XILINX")
endgenerate
endmodule // eclocks
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_if0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe (probe_input),
.source ()
// synopsys translate_off
,
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
iss_probe_inst.enable_metastability = "NO",
iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH,
iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0,
iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
|
//============================================================
//
// Hsiang-Yi Chung
// March 2016
//
// This Module is for transfering the data to a processor
//
//============================================================
module SerialInterface(
input clk,
input next_out,
input reset_n,
input [11:0] fft_out1,
input [11:0] fft_out2,
output reg next_data,
output reg data
);
localparam s0 = 3'b000;
localparam s1 = 3'b001;
localparam s2 = 3'b010;
localparam s3 = 3'b011;
localparam s4 = 3'b100;
localparam s5 = 3'b101;
localparam s6 = 3'b110;
localparam s7 = 3'b111;
reg [2:0] state, nextState;
reg [10:0] addr_counter;
reg [3:0] bit_counter;
reg [11:0] temp;
reg reset_addr_counter, incre_addr_counter1, incre_addr_counter2,
we_a, we_b, reset_bit_counter, incre_bit_counter, update_output;
wire [11:0] q_a, q_b;
wire [10:0] addr_a, addr_b;
Serial_Ram ram_inst (.data_a(fft_out1), .data_b(fft_out2),
.addr_a(addr_a), .addr_b(addr_b),
.we_a(we_a), .we_b(we_b),
.q_a(q_a), .q_b(q_b), .clk(clk));
initial begin
addr_counter = 0;
we_a = 0;
we_b = 0;
next_data = 0;
data = 0;
bit_counter = 0;
update_output = 0;
end
assign addr_a = addr_counter;
assign addr_b = addr_counter+1;
always @ (posedge clk) begin
if(!reset_n) begin
state <= s0;
end
else begin
state <= nextState;
end
end
always @ (posedge clk) begin
//address counter
if(reset_addr_counter)
addr_counter <= 0;
else if(incre_addr_counter1)
addr_counter <= addr_counter + 1;
else if(incre_addr_counter2)
addr_counter <= addr_counter + 2;
//bit counter
if(reset_bit_counter)
bit_counter <= 0;
else if(incre_bit_counter)
bit_counter <= bit_counter + 1;
if(update_output) begin
data <= q_a[11-bit_counter];
end
end
always @ * begin
reset_addr_counter = 0; incre_addr_counter1 = 0; incre_addr_counter2 = 0;
next_data = 0; we_a = 0; we_b = 0;
reset_bit_counter = 0; incre_bit_counter = 0; update_output = 0;
case(state)
//Wait until the FFT starts to output
s0: begin
if(next_out)
nextState = s1;
else
nextState = s0;
end
s1: begin
nextState = s2;
we_a = 1;
we_b = 1;
end
//load fft magnitude into buffer
s2: begin
nextState = s3;
we_a = 1;
we_b = 1;
end
//check if received 2048 samples & increament counter if needed
s3: begin
we_a = 1;
we_b = 1;
if(addr_counter == 2046) begin
reset_addr_counter = 1;
nextState = s4;
end else begin
incre_addr_counter2 = 1;
nextState = s2;
end
end
//asserts the beginning of the output data stream
s4: begin
next_data = 1;
nextState = s5;
we_a = 0;
we_b = 0;
end
s5: begin
update_output = 1;
next_data = 1;
nextState = s6;
we_a = 0;
we_b = 0;
end
s6: begin
we_a = 0;
we_b = 0;
next_data = 1;
if(bit_counter == 11 && addr_counter == 2047) begin
reset_addr_counter = 1;
reset_bit_counter = 1;
nextState = s0;
end else if(bit_counter == 11) begin
reset_bit_counter = 1;
incre_addr_counter1 = 1;
nextState = s5;
end else begin
incre_bit_counter = 1;
nextState = s5;
end
end
endcase
end
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 06:23:47 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_rst_ps7_0_50M_0_stub.v
// Design : design_1_rst_ps7_0_50M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Clock generation for DDR2 MCB
*/
module ddr2_clock
(
// 250 MHz clock and reset
input wire clk_250mhz,
input wire rst_250mhz,
// Output clocks to MCB
output wire mcb_clk_0,
output wire mcb_clk_180,
output wire mcb_drp_clk,
output wire mcb_clk_locked
);
wire clkfb;
wire mcb_clk_0_int;
wire mcb_clk_180_int;
wire mcb_drp_clk_int;
// input is 250 MHz
// output0/1 are 250 MHz * 5 / 2 = 625 MHz (MCB 2x clock)
// output2 is 625 MHz / 10 = 62.5 MHz (MCB DRP clock)
PLL_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (4.000),
.CLKIN2_PERIOD (4.000),
.CLKOUT0_DIVIDE (1),
.CLKOUT1_DIVIDE (1),
.CLKOUT2_DIVIDE (10),
.CLKOUT3_DIVIDE (1),
.CLKOUT4_DIVIDE (1),
.CLKOUT5_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_PHASE (180.000),
.CLKOUT2_PHASE (0.000),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_PHASE (0.000),
.CLKOUT5_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT5_DUTY_CYCLE (0.500),
.SIM_DEVICE ("SPARTAN6"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (2),
.CLKFBOUT_MULT (5),
.CLKFBOUT_PHASE (0.0),
.REF_JITTER (0.025000)
)
mcb_pll
(
.CLKFBIN (clkfb),
.CLKINSEL (1'b1),
.CLKIN1 (clk_250mhz),
.CLKIN2 (1'b0),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.REL (1'b0),
.RST (rst_250mhz),
.CLKFBDCM (),
.CLKFBOUT (clkfb),
.CLKOUTDCM0 (),
.CLKOUTDCM1 (),
.CLKOUTDCM2 (),
.CLKOUTDCM3 (),
.CLKOUTDCM4 (),
.CLKOUTDCM5 (),
.CLKOUT0 (mcb_clk_0),
.CLKOUT1 (mcb_clk_180),
.CLKOUT2 (mcb_drp_clk_int),
.CLKOUT3 (),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (mcb_clk_locked)
);
BUFGCE
mcb_drp_clk_bufg_inst
(
.I(mcb_drp_clk_int),
.O(mcb_drp_clk),
.CE(mcb_clk_locked)
);
endmodule
|
`include "constants.v"
`ifndef _clkdiv
`define _clkdiv
module clkdiv(input in, output out);
parameter CLK_DIVIDER_WIDTH = `CLK_DIVIDER_WIDTH;
parameter CLK_DIVIDER_VALUE = `CLK_DIVIDER_VALUE;
reg [CLK_DIVIDER_WIDTH-1:0] _icounter;
reg _internal_clk;
assign out = _internal_clk;
initial begin
_icounter = {(CLK_DIVIDER_WIDTH){1'b0}};
_internal_clk = 0;
end
always @(posedge in) begin
_internal_clk = (_icounter == {CLK_DIVIDER_VALUE} ) ? ~_internal_clk : _internal_clk;
_icounter = (_icounter == {CLK_DIVIDER_VALUE} ) ? 0 : _icounter + 1;
end
endmodule
module COUNTER( input [7:0] DATA, input NCCLR, input NCCKEN, input CCK,
input NCLOAD, input RCK, output [7:0] QDATA);
parameter CLK_DIVIDER_WIDTH = 8;
reg [CLK_DIVIDER_WIDTH-1:0] _icounter;
assign QDATA = _icounter;
initial begin
_icounter = {(CLK_DIVIDER_WIDTH){1'b0}};
end
always @(posedge CCK, negedge NCCKEN, negedge NCCLR) begin
if (~NCCKEN) begin
if (~NCCLR) begin
_icounter = 8'h0;
end
else if (~NCLOAD) begin
_icounter = DATA;
end
else begin
if (CCK == 1) begin
_icounter = _icounter + 1;
end
end
end
end
endmodule
`endif |
`include "bsg_defines.v"
// MBT 11/26/2014, bsg_fsb_node_trace_replay
// Shaolin 01/06/2018, generalized from the bsg_trace_replay
// trace format (see enum below)
//
// Debug Display Levels:
// 0 = suppress all non-errors. only shows mismatch and unknown op
// (default) 1 = adds finish and done
// 2 = all messages. adds send, recv, cycle dec, and cycle init
module bsg_trace_replay
#( parameter payload_width_p =80
, parameter rom_addr_width_p=6
, parameter counter_width_p=`BSG_MIN(payload_width_p,16)
, parameter debug_p = 1
, parameter finish_on_error_p = 1
//The operation code is always 4 bits.
, parameter opcode_width_lp = 4
)
( input clk_i
, input reset_i
, input en_i
// input channel
, input v_i
, input [payload_width_p-1:0] data_i
, output logic ready_o
// output channel
, output logic v_o
, output logic [payload_width_p-1:0] data_o
, input yumi_i
// connection to rom
// note: asynchronous reads
, output [rom_addr_width_p-1:0] rom_addr_o
, input [payload_width_p+4-1:0] rom_data_i
// true outputs
, output logic done_o
, output logic error_o
);
// 0: wait one cycle
// 1: send data
// 2: receive data (and check its value)
// 3: assert done_o; test complete.
// 4: end test; call $finish
// 5: decrement cycle counter; wait for cycle_counter == 0
// 6: initialized cycle counter with 16 bits
// in theory, we could add branching, etc.
// before we know it, we have a processor =)
typedef enum logic [opcode_width_lp-1:0] {
eNop=4'd0,
eSend=4'd1,
eReceive=4'd2,
eDone=4'd3,
eFinish=4'd4,
eCycleDec=4'd5,
eCycleInit=4'd6
} eOp;
logic [counter_width_p-1:0] cycle_ctr_r, cycle_ctr_n;
logic [rom_addr_width_p-1:0] addr_r, addr_n;
logic done_r, done_n;
logic error_r, error_n;
assign rom_addr_o = addr_r;
assign data_o = rom_data_i[0+:payload_width_p];
assign done_o = done_r;
assign error_o = error_r;
always_ff @(posedge clk_i) begin
if (reset_i) begin
addr_r <= 0;
done_r <= 0;
error_r <= 0;
cycle_ctr_r <= 16'b1;
end else begin
addr_r <= addr_n;
done_r <= done_n;
error_r <= error_n;
cycle_ctr_r <= cycle_ctr_n;
end
end // always_ff @
logic [3:0] op;
assign op = rom_data_i[payload_width_p+:4];
logic instr_completed;
assign addr_n = instr_completed ? (addr_r+1'b1) : addr_r;
// handle outputs
always_comb begin
// defaults; not sending and not receiving unless done
v_o = 1'b0;
ready_o = done_r;
done_n = done_r;
if (!done_r & en_i & ~reset_i) begin
case (op)
eSend: v_o = 1'b1;
eReceive: ready_o = 1'b1;
eDone: done_n = 1'b1;
default:
begin
end
endcase
end
end // always_comb
// next instruction logic
always_comb begin
instr_completed = 1'b0;
error_n = error_r;
cycle_ctr_n = cycle_ctr_r;
if (!done_r & en_i & ~reset_i) begin
case (op)
eNop: instr_completed = 1'b1;
eSend: if (yumi_i) instr_completed = 1'b1;
eReceive: begin
if (v_i)
begin
instr_completed = 1'b1;
if (error_r == 0)
error_n = data_i != data_o;
end
end
eDone: instr_completed = 1'b1;
eFinish: instr_completed = 1'b1;
eCycleDec:
begin
cycle_ctr_n = cycle_ctr_r - 1'b1;
instr_completed = ~(|cycle_ctr_r);
end
eCycleInit:
begin
cycle_ctr_n = rom_data_i[counter_width_p-1:0];
instr_completed = 1'b1;
end
default:
begin
error_n = 1'b1;
instr_completed = 1'b1;
end
endcase // case (op)
end
end
// non-synthesizeable components
always @(negedge clk_i) begin
if (instr_completed & ~reset_i & ~done_r) begin
case(op)
eNop: begin end
eSend: begin
if (debug_p >= 2) begin
$display("### bsg_trace_replay SEND %d'b%b (%m)", payload_width_p,data_o);
end
end
eReceive: begin
if (data_i !== data_o) begin
$display("############################################################################");
$display("### bsg_trace_replay RECEIVE unmatched (%m) ");
$display("### ");
$display("### FAIL (trace mismatch) = %h", data_i);
$display("### expected = %h\n", data_o);
$display("############################################################################");
if (finish_on_error_p == 1) begin
$finish();
end
end else begin
if (debug_p >= 2) begin
$display("### bsg_trace_replay RECEIVE matched %h (%m)", data_o);
end
end // else: !if(data_i != data_o)
end
eDone: begin
if (debug_p >= 1) begin
$display("############################################################################");
$display("###### bsg_trace_replay DONE done_o=1 (trace finished addr=%x) (%m)",rom_addr_o);
$display("############################################################################");
end
end
eFinish: begin
if (debug_p >= 1) begin
$display("############################################################################");
$display("###### bsg_trace_replay FINISH (trace finished; CALLING $finish) (%m)");
$display("############################################################################");
end
$finish;
end
eCycleDec: begin
if (debug_p >= 2) begin
$display("### bsg_trace_replay CYCLE DEC cycle_ctr_r = %x (%m)",cycle_ctr_r);
end
end
eCycleInit: begin
if (debug_p >= 2) begin
$display("### bsg_trace_replay CYCLE INIT = %x (%m)",cycle_ctr_n);
end
end
default: begin
$error("### bsg_trace_replay UNKNOWN op %x (%m)\n", op);
if (finish_on_error_p == 1) begin
$finish();
end
end
endcase // case (op)
end // if (instr_completed & ~reset_i & ~done_r)
end // always @ (negedge clk_i)
endmodule
|
// lights_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.0 595
`timescale 1 ps / 1 ps
module lights_mm_interconnect_0 (
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire nios2_qsys_0_reset_n_reset_bridge_in_reset_reset, // nios2_qsys_0_reset_n_reset_bridge_in_reset.reset
input wire [13:0] nios2_qsys_0_data_master_address, // nios2_qsys_0_data_master.address
output wire nios2_qsys_0_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_qsys_0_data_master_byteenable, // .byteenable
input wire nios2_qsys_0_data_master_read, // .read
output wire [31:0] nios2_qsys_0_data_master_readdata, // .readdata
input wire nios2_qsys_0_data_master_write, // .write
input wire [31:0] nios2_qsys_0_data_master_writedata, // .writedata
input wire nios2_qsys_0_data_master_debugaccess, // .debugaccess
input wire [12:0] nios2_qsys_0_instruction_master_address, // nios2_qsys_0_instruction_master.address
output wire nios2_qsys_0_instruction_master_waitrequest, // .waitrequest
input wire nios2_qsys_0_instruction_master_read, // .read
output wire [31:0] nios2_qsys_0_instruction_master_readdata, // .readdata
output wire [0:0] jtag_uart_0_avalon_jtag_slave_address, // jtag_uart_0_avalon_jtag_slave.address
output wire jtag_uart_0_avalon_jtag_slave_write, // .write
output wire jtag_uart_0_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_0_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_0_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_0_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_0_avalon_jtag_slave_chipselect, // .chipselect
output wire [1:0] LEDs_s1_address, // LEDs_s1.address
output wire LEDs_s1_write, // .write
input wire [31:0] LEDs_s1_readdata, // .readdata
output wire [31:0] LEDs_s1_writedata, // .writedata
output wire LEDs_s1_chipselect, // .chipselect
output wire [8:0] nios2_qsys_0_jtag_debug_module_address, // nios2_qsys_0_jtag_debug_module.address
output wire nios2_qsys_0_jtag_debug_module_write, // .write
output wire nios2_qsys_0_jtag_debug_module_read, // .read
input wire [31:0] nios2_qsys_0_jtag_debug_module_readdata, // .readdata
output wire [31:0] nios2_qsys_0_jtag_debug_module_writedata, // .writedata
output wire [3:0] nios2_qsys_0_jtag_debug_module_byteenable, // .byteenable
input wire nios2_qsys_0_jtag_debug_module_waitrequest, // .waitrequest
output wire nios2_qsys_0_jtag_debug_module_debugaccess, // .debugaccess
output wire [9:0] onchip_memory2_0_s1_address, // onchip_memory2_0_s1.address
output wire onchip_memory2_0_s1_write, // .write
input wire [31:0] onchip_memory2_0_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_0_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_0_s1_byteenable, // .byteenable
output wire onchip_memory2_0_s1_chipselect, // .chipselect
output wire onchip_memory2_0_s1_clken, // .clken
output wire [1:0] switches_s1_address, // switches_s1.address
input wire [31:0] switches_s1_readdata // .readdata
);
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_0_data_master_agent:av_waitrequest -> nios2_qsys_0_data_master_translator:uav_waitrequest
wire [31:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_0_data_master_agent:av_readdata -> nios2_qsys_0_data_master_translator:uav_readdata
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_0_data_master_translator:uav_debugaccess -> nios2_qsys_0_data_master_agent:av_debugaccess
wire [13:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_address; // nios2_qsys_0_data_master_translator:uav_address -> nios2_qsys_0_data_master_agent:av_address
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_read; // nios2_qsys_0_data_master_translator:uav_read -> nios2_qsys_0_data_master_agent:av_read
wire [3:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_0_data_master_translator:uav_byteenable -> nios2_qsys_0_data_master_agent:av_byteenable
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_0_data_master_agent:av_readdatavalid -> nios2_qsys_0_data_master_translator:uav_readdatavalid
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock; // nios2_qsys_0_data_master_translator:uav_lock -> nios2_qsys_0_data_master_agent:av_lock
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_write; // nios2_qsys_0_data_master_translator:uav_write -> nios2_qsys_0_data_master_agent:av_write
wire [31:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_0_data_master_translator:uav_writedata -> nios2_qsys_0_data_master_agent:av_writedata
wire [2:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_0_data_master_translator:uav_burstcount -> nios2_qsys_0_data_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> nios2_qsys_0_data_master_agent:rp_valid
wire [89:0] rsp_mux_src_data; // rsp_mux:src_data -> nios2_qsys_0_data_master_agent:rp_data
wire rsp_mux_src_ready; // nios2_qsys_0_data_master_agent:rp_ready -> rsp_mux:src_ready
wire [4:0] rsp_mux_src_channel; // rsp_mux:src_channel -> nios2_qsys_0_data_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> nios2_qsys_0_data_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> nios2_qsys_0_data_master_agent:rp_endofpacket
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_0_instruction_master_agent:av_waitrequest -> nios2_qsys_0_instruction_master_translator:uav_waitrequest
wire [31:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_0_instruction_master_agent:av_readdata -> nios2_qsys_0_instruction_master_translator:uav_readdata
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_0_instruction_master_translator:uav_debugaccess -> nios2_qsys_0_instruction_master_agent:av_debugaccess
wire [13:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_qsys_0_instruction_master_translator:uav_address -> nios2_qsys_0_instruction_master_agent:av_address
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_qsys_0_instruction_master_translator:uav_read -> nios2_qsys_0_instruction_master_agent:av_read
wire [3:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_0_instruction_master_translator:uav_byteenable -> nios2_qsys_0_instruction_master_agent:av_byteenable
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_0_instruction_master_agent:av_readdatavalid -> nios2_qsys_0_instruction_master_translator:uav_readdatavalid
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_qsys_0_instruction_master_translator:uav_lock -> nios2_qsys_0_instruction_master_agent:av_lock
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_qsys_0_instruction_master_translator:uav_write -> nios2_qsys_0_instruction_master_agent:av_write
wire [31:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_0_instruction_master_translator:uav_writedata -> nios2_qsys_0_instruction_master_agent:av_writedata
wire [2:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_0_instruction_master_translator:uav_burstcount -> nios2_qsys_0_instruction_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_qsys_0_instruction_master_agent:rp_valid
wire [89:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_qsys_0_instruction_master_agent:rp_data
wire rsp_mux_001_src_ready; // nios2_qsys_0_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [4:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_qsys_0_instruction_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_qsys_0_instruction_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_qsys_0_instruction_master_agent:rp_endofpacket
wire [31:0] jtag_uart_0_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_agent:m0_waitrequest
wire jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_0_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
wire [13:0] jtag_uart_0_avalon_jtag_slave_agent_m0_address; // jtag_uart_0_avalon_jtag_slave_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
wire [3:0] jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_0_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_0_avalon_jtag_slave_agent_m0_read; // jtag_uart_0_avalon_jtag_slave_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
wire jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_0_avalon_jtag_slave_agent_m0_lock; // jtag_uart_0_avalon_jtag_slave_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
wire [31:0] jtag_uart_0_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_0_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
wire jtag_uart_0_avalon_jtag_slave_agent_m0_write; // jtag_uart_0_avalon_jtag_slave_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
wire [2:0] jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_0_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire [90:0] jtag_uart_0_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_valid
wire [90:0] jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_0_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> jtag_uart_0_avalon_jtag_slave_agent:cp_valid
wire [89:0] cmd_mux_src_data; // cmd_mux:src_data -> jtag_uart_0_avalon_jtag_slave_agent:cp_data
wire cmd_mux_src_ready; // jtag_uart_0_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
wire [4:0] cmd_mux_src_channel; // cmd_mux:src_channel -> jtag_uart_0_avalon_jtag_slave_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent:cp_endofpacket
wire [31:0] nios2_qsys_0_jtag_debug_module_agent_m0_readdata; // nios2_qsys_0_jtag_debug_module_translator:uav_readdata -> nios2_qsys_0_jtag_debug_module_agent:m0_readdata
wire nios2_qsys_0_jtag_debug_module_agent_m0_waitrequest; // nios2_qsys_0_jtag_debug_module_translator:uav_waitrequest -> nios2_qsys_0_jtag_debug_module_agent:m0_waitrequest
wire nios2_qsys_0_jtag_debug_module_agent_m0_debugaccess; // nios2_qsys_0_jtag_debug_module_agent:m0_debugaccess -> nios2_qsys_0_jtag_debug_module_translator:uav_debugaccess
wire [13:0] nios2_qsys_0_jtag_debug_module_agent_m0_address; // nios2_qsys_0_jtag_debug_module_agent:m0_address -> nios2_qsys_0_jtag_debug_module_translator:uav_address
wire [3:0] nios2_qsys_0_jtag_debug_module_agent_m0_byteenable; // nios2_qsys_0_jtag_debug_module_agent:m0_byteenable -> nios2_qsys_0_jtag_debug_module_translator:uav_byteenable
wire nios2_qsys_0_jtag_debug_module_agent_m0_read; // nios2_qsys_0_jtag_debug_module_agent:m0_read -> nios2_qsys_0_jtag_debug_module_translator:uav_read
wire nios2_qsys_0_jtag_debug_module_agent_m0_readdatavalid; // nios2_qsys_0_jtag_debug_module_translator:uav_readdatavalid -> nios2_qsys_0_jtag_debug_module_agent:m0_readdatavalid
wire nios2_qsys_0_jtag_debug_module_agent_m0_lock; // nios2_qsys_0_jtag_debug_module_agent:m0_lock -> nios2_qsys_0_jtag_debug_module_translator:uav_lock
wire [31:0] nios2_qsys_0_jtag_debug_module_agent_m0_writedata; // nios2_qsys_0_jtag_debug_module_agent:m0_writedata -> nios2_qsys_0_jtag_debug_module_translator:uav_writedata
wire nios2_qsys_0_jtag_debug_module_agent_m0_write; // nios2_qsys_0_jtag_debug_module_agent:m0_write -> nios2_qsys_0_jtag_debug_module_translator:uav_write
wire [2:0] nios2_qsys_0_jtag_debug_module_agent_m0_burstcount; // nios2_qsys_0_jtag_debug_module_agent:m0_burstcount -> nios2_qsys_0_jtag_debug_module_translator:uav_burstcount
wire nios2_qsys_0_jtag_debug_module_agent_rf_source_valid; // nios2_qsys_0_jtag_debug_module_agent:rf_source_valid -> nios2_qsys_0_jtag_debug_module_agent_rsp_fifo:in_valid
wire [90:0] nios2_qsys_0_jtag_debug_module_agent_rf_source_data; // nios2_qsys_0_jtag_debug_module_agent:rf_source_data -> nios2_qsys_0_jtag_debug_module_agent_rsp_fifo:in_data
wire nios2_qsys_0_jtag_debug_module_agent_rf_source_ready; // nios2_qsys_0_jtag_debug_module_agent_rsp_fifo:in_ready -> nios2_qsys_0_jtag_debug_module_agent:rf_source_ready
wire nios2_qsys_0_jtag_debug_module_agent_rf_source_startofpacket; // nios2_qsys_0_jtag_debug_module_agent:rf_source_startofpacket -> nios2_qsys_0_jtag_debug_module_agent_rsp_fifo:in_startofpacket
wire nios2_qsys_0_jtag_debug_module_agent_rf_source_endofpacket; // nios2_qsys_0_jtag_debug_module_agent:rf_source_endofpacket -> nios2_qsys_0_jtag_debug_module_agent_rsp_fifo:in_endofpacket
wire nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_valid; // nios2_qsys_0_jtag_debug_module_agent_rsp_fifo:out_valid -> nios2_qsys_0_jtag_debug_module_agent:rf_sink_valid
wire [90:0] nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_data; // nios2_qsys_0_jtag_debug_module_agent_rsp_fifo:out_data -> nios2_qsys_0_jtag_debug_module_agent:rf_sink_data
wire nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_ready; // nios2_qsys_0_jtag_debug_module_agent:rf_sink_ready -> nios2_qsys_0_jtag_debug_module_agent_rsp_fifo:out_ready
wire nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_startofpacket; // nios2_qsys_0_jtag_debug_module_agent_rsp_fifo:out_startofpacket -> nios2_qsys_0_jtag_debug_module_agent:rf_sink_startofpacket
wire nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_endofpacket; // nios2_qsys_0_jtag_debug_module_agent_rsp_fifo:out_endofpacket -> nios2_qsys_0_jtag_debug_module_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> nios2_qsys_0_jtag_debug_module_agent:cp_valid
wire [89:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> nios2_qsys_0_jtag_debug_module_agent:cp_data
wire cmd_mux_001_src_ready; // nios2_qsys_0_jtag_debug_module_agent:cp_ready -> cmd_mux_001:src_ready
wire [4:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> nios2_qsys_0_jtag_debug_module_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> nios2_qsys_0_jtag_debug_module_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> nios2_qsys_0_jtag_debug_module_agent:cp_endofpacket
wire [31:0] onchip_memory2_0_s1_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
wire onchip_memory2_0_s1_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
wire onchip_memory2_0_s1_agent_m0_debugaccess; // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [13:0] onchip_memory2_0_s1_agent_m0_address; // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire [3:0] onchip_memory2_0_s1_agent_m0_byteenable; // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_agent_m0_read; // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire onchip_memory2_0_s1_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
wire onchip_memory2_0_s1_agent_m0_lock; // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire [31:0] onchip_memory2_0_s1_agent_m0_writedata; // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire onchip_memory2_0_s1_agent_m0_write; // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire [2:0] onchip_memory2_0_s1_agent_m0_burstcount; // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire onchip_memory2_0_s1_agent_rf_source_valid; // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
wire [90:0] onchip_memory2_0_s1_agent_rf_source_data; // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_agent_rf_source_ready; // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
wire onchip_memory2_0_s1_agent_rf_source_startofpacket; // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_0_s1_agent_rf_source_endofpacket; // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
wire [90:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
wire onchip_memory2_0_s1_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> onchip_memory2_0_s1_agent:cp_valid
wire [89:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> onchip_memory2_0_s1_agent:cp_data
wire cmd_mux_002_src_ready; // onchip_memory2_0_s1_agent:cp_ready -> cmd_mux_002:src_ready
wire [4:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> onchip_memory2_0_s1_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
wire [31:0] switches_s1_agent_m0_readdata; // switches_s1_translator:uav_readdata -> switches_s1_agent:m0_readdata
wire switches_s1_agent_m0_waitrequest; // switches_s1_translator:uav_waitrequest -> switches_s1_agent:m0_waitrequest
wire switches_s1_agent_m0_debugaccess; // switches_s1_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess
wire [13:0] switches_s1_agent_m0_address; // switches_s1_agent:m0_address -> switches_s1_translator:uav_address
wire [3:0] switches_s1_agent_m0_byteenable; // switches_s1_agent:m0_byteenable -> switches_s1_translator:uav_byteenable
wire switches_s1_agent_m0_read; // switches_s1_agent:m0_read -> switches_s1_translator:uav_read
wire switches_s1_agent_m0_readdatavalid; // switches_s1_translator:uav_readdatavalid -> switches_s1_agent:m0_readdatavalid
wire switches_s1_agent_m0_lock; // switches_s1_agent:m0_lock -> switches_s1_translator:uav_lock
wire [31:0] switches_s1_agent_m0_writedata; // switches_s1_agent:m0_writedata -> switches_s1_translator:uav_writedata
wire switches_s1_agent_m0_write; // switches_s1_agent:m0_write -> switches_s1_translator:uav_write
wire [2:0] switches_s1_agent_m0_burstcount; // switches_s1_agent:m0_burstcount -> switches_s1_translator:uav_burstcount
wire switches_s1_agent_rf_source_valid; // switches_s1_agent:rf_source_valid -> switches_s1_agent_rsp_fifo:in_valid
wire [90:0] switches_s1_agent_rf_source_data; // switches_s1_agent:rf_source_data -> switches_s1_agent_rsp_fifo:in_data
wire switches_s1_agent_rf_source_ready; // switches_s1_agent_rsp_fifo:in_ready -> switches_s1_agent:rf_source_ready
wire switches_s1_agent_rf_source_startofpacket; // switches_s1_agent:rf_source_startofpacket -> switches_s1_agent_rsp_fifo:in_startofpacket
wire switches_s1_agent_rf_source_endofpacket; // switches_s1_agent:rf_source_endofpacket -> switches_s1_agent_rsp_fifo:in_endofpacket
wire switches_s1_agent_rsp_fifo_out_valid; // switches_s1_agent_rsp_fifo:out_valid -> switches_s1_agent:rf_sink_valid
wire [90:0] switches_s1_agent_rsp_fifo_out_data; // switches_s1_agent_rsp_fifo:out_data -> switches_s1_agent:rf_sink_data
wire switches_s1_agent_rsp_fifo_out_ready; // switches_s1_agent:rf_sink_ready -> switches_s1_agent_rsp_fifo:out_ready
wire switches_s1_agent_rsp_fifo_out_startofpacket; // switches_s1_agent_rsp_fifo:out_startofpacket -> switches_s1_agent:rf_sink_startofpacket
wire switches_s1_agent_rsp_fifo_out_endofpacket; // switches_s1_agent_rsp_fifo:out_endofpacket -> switches_s1_agent:rf_sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> switches_s1_agent:cp_valid
wire [89:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> switches_s1_agent:cp_data
wire cmd_mux_003_src_ready; // switches_s1_agent:cp_ready -> cmd_mux_003:src_ready
wire [4:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> switches_s1_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> switches_s1_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> switches_s1_agent:cp_endofpacket
wire [31:0] leds_s1_agent_m0_readdata; // LEDs_s1_translator:uav_readdata -> LEDs_s1_agent:m0_readdata
wire leds_s1_agent_m0_waitrequest; // LEDs_s1_translator:uav_waitrequest -> LEDs_s1_agent:m0_waitrequest
wire leds_s1_agent_m0_debugaccess; // LEDs_s1_agent:m0_debugaccess -> LEDs_s1_translator:uav_debugaccess
wire [13:0] leds_s1_agent_m0_address; // LEDs_s1_agent:m0_address -> LEDs_s1_translator:uav_address
wire [3:0] leds_s1_agent_m0_byteenable; // LEDs_s1_agent:m0_byteenable -> LEDs_s1_translator:uav_byteenable
wire leds_s1_agent_m0_read; // LEDs_s1_agent:m0_read -> LEDs_s1_translator:uav_read
wire leds_s1_agent_m0_readdatavalid; // LEDs_s1_translator:uav_readdatavalid -> LEDs_s1_agent:m0_readdatavalid
wire leds_s1_agent_m0_lock; // LEDs_s1_agent:m0_lock -> LEDs_s1_translator:uav_lock
wire [31:0] leds_s1_agent_m0_writedata; // LEDs_s1_agent:m0_writedata -> LEDs_s1_translator:uav_writedata
wire leds_s1_agent_m0_write; // LEDs_s1_agent:m0_write -> LEDs_s1_translator:uav_write
wire [2:0] leds_s1_agent_m0_burstcount; // LEDs_s1_agent:m0_burstcount -> LEDs_s1_translator:uav_burstcount
wire leds_s1_agent_rf_source_valid; // LEDs_s1_agent:rf_source_valid -> LEDs_s1_agent_rsp_fifo:in_valid
wire [90:0] leds_s1_agent_rf_source_data; // LEDs_s1_agent:rf_source_data -> LEDs_s1_agent_rsp_fifo:in_data
wire leds_s1_agent_rf_source_ready; // LEDs_s1_agent_rsp_fifo:in_ready -> LEDs_s1_agent:rf_source_ready
wire leds_s1_agent_rf_source_startofpacket; // LEDs_s1_agent:rf_source_startofpacket -> LEDs_s1_agent_rsp_fifo:in_startofpacket
wire leds_s1_agent_rf_source_endofpacket; // LEDs_s1_agent:rf_source_endofpacket -> LEDs_s1_agent_rsp_fifo:in_endofpacket
wire leds_s1_agent_rsp_fifo_out_valid; // LEDs_s1_agent_rsp_fifo:out_valid -> LEDs_s1_agent:rf_sink_valid
wire [90:0] leds_s1_agent_rsp_fifo_out_data; // LEDs_s1_agent_rsp_fifo:out_data -> LEDs_s1_agent:rf_sink_data
wire leds_s1_agent_rsp_fifo_out_ready; // LEDs_s1_agent:rf_sink_ready -> LEDs_s1_agent_rsp_fifo:out_ready
wire leds_s1_agent_rsp_fifo_out_startofpacket; // LEDs_s1_agent_rsp_fifo:out_startofpacket -> LEDs_s1_agent:rf_sink_startofpacket
wire leds_s1_agent_rsp_fifo_out_endofpacket; // LEDs_s1_agent_rsp_fifo:out_endofpacket -> LEDs_s1_agent:rf_sink_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> LEDs_s1_agent:cp_valid
wire [89:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> LEDs_s1_agent:cp_data
wire cmd_mux_004_src_ready; // LEDs_s1_agent:cp_ready -> cmd_mux_004:src_ready
wire [4:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> LEDs_s1_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> LEDs_s1_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> LEDs_s1_agent:cp_endofpacket
wire nios2_qsys_0_data_master_agent_cp_valid; // nios2_qsys_0_data_master_agent:cp_valid -> router:sink_valid
wire [89:0] nios2_qsys_0_data_master_agent_cp_data; // nios2_qsys_0_data_master_agent:cp_data -> router:sink_data
wire nios2_qsys_0_data_master_agent_cp_ready; // router:sink_ready -> nios2_qsys_0_data_master_agent:cp_ready
wire nios2_qsys_0_data_master_agent_cp_startofpacket; // nios2_qsys_0_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire nios2_qsys_0_data_master_agent_cp_endofpacket; // nios2_qsys_0_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [89:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [4:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire nios2_qsys_0_instruction_master_agent_cp_valid; // nios2_qsys_0_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [89:0] nios2_qsys_0_instruction_master_agent_cp_data; // nios2_qsys_0_instruction_master_agent:cp_data -> router_001:sink_data
wire nios2_qsys_0_instruction_master_agent_cp_ready; // router_001:sink_ready -> nios2_qsys_0_instruction_master_agent:cp_ready
wire nios2_qsys_0_instruction_master_agent_cp_startofpacket; // nios2_qsys_0_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire nios2_qsys_0_instruction_master_agent_cp_endofpacket; // nios2_qsys_0_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [89:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [4:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rp_valid; // jtag_uart_0_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
wire [89:0] jtag_uart_0_avalon_jtag_slave_agent_rp_data; // jtag_uart_0_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rp_ready; // router_002:sink_ready -> jtag_uart_0_avalon_jtag_slave_agent:rp_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [89:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [4:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire nios2_qsys_0_jtag_debug_module_agent_rp_valid; // nios2_qsys_0_jtag_debug_module_agent:rp_valid -> router_003:sink_valid
wire [89:0] nios2_qsys_0_jtag_debug_module_agent_rp_data; // nios2_qsys_0_jtag_debug_module_agent:rp_data -> router_003:sink_data
wire nios2_qsys_0_jtag_debug_module_agent_rp_ready; // router_003:sink_ready -> nios2_qsys_0_jtag_debug_module_agent:rp_ready
wire nios2_qsys_0_jtag_debug_module_agent_rp_startofpacket; // nios2_qsys_0_jtag_debug_module_agent:rp_startofpacket -> router_003:sink_startofpacket
wire nios2_qsys_0_jtag_debug_module_agent_rp_endofpacket; // nios2_qsys_0_jtag_debug_module_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [89:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [4:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire onchip_memory2_0_s1_agent_rp_valid; // onchip_memory2_0_s1_agent:rp_valid -> router_004:sink_valid
wire [89:0] onchip_memory2_0_s1_agent_rp_data; // onchip_memory2_0_s1_agent:rp_data -> router_004:sink_data
wire onchip_memory2_0_s1_agent_rp_ready; // router_004:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
wire onchip_memory2_0_s1_agent_rp_startofpacket; // onchip_memory2_0_s1_agent:rp_startofpacket -> router_004:sink_startofpacket
wire onchip_memory2_0_s1_agent_rp_endofpacket; // onchip_memory2_0_s1_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire [89:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire [4:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire switches_s1_agent_rp_valid; // switches_s1_agent:rp_valid -> router_005:sink_valid
wire [89:0] switches_s1_agent_rp_data; // switches_s1_agent:rp_data -> router_005:sink_data
wire switches_s1_agent_rp_ready; // router_005:sink_ready -> switches_s1_agent:rp_ready
wire switches_s1_agent_rp_startofpacket; // switches_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
wire switches_s1_agent_rp_endofpacket; // switches_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire [89:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire [4:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire leds_s1_agent_rp_valid; // LEDs_s1_agent:rp_valid -> router_006:sink_valid
wire [89:0] leds_s1_agent_rp_data; // LEDs_s1_agent:rp_data -> router_006:sink_data
wire leds_s1_agent_rp_ready; // router_006:sink_ready -> LEDs_s1_agent:rp_ready
wire leds_s1_agent_rp_startofpacket; // LEDs_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire leds_s1_agent_rp_endofpacket; // LEDs_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire [89:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire [4:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [89:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [4:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [89:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [4:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [89:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [4:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [89:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [4:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire [89:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire [4:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_001:sink1_valid
wire [89:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_001:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src0_ready
wire [4:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_002:sink1_valid
wire [89:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_002:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src1_ready
wire [4:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_002:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [89:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [4:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [89:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [4:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink0_valid
wire [89:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_001:src1_ready
wire [4:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [89:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [4:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink1_valid
wire [89:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_002:src1_ready
wire [4:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [89:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [4:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire [89:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire [4:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_error
wire nios2_qsys_0_jtag_debug_module_agent_rdata_fifo_src_valid; // nios2_qsys_0_jtag_debug_module_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] nios2_qsys_0_jtag_debug_module_agent_rdata_fifo_src_data; // nios2_qsys_0_jtag_debug_module_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire nios2_qsys_0_jtag_debug_module_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> nios2_qsys_0_jtag_debug_module_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> nios2_qsys_0_jtag_debug_module_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> nios2_qsys_0_jtag_debug_module_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // nios2_qsys_0_jtag_debug_module_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> nios2_qsys_0_jtag_debug_module_agent:rdata_fifo_sink_error
wire onchip_memory2_0_s1_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire onchip_memory2_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> onchip_memory2_0_s1_agent:rdata_fifo_sink_error
wire switches_s1_agent_rdata_fifo_src_valid; // switches_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] switches_s1_agent_rdata_fifo_src_data; // switches_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire switches_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> switches_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> switches_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> switches_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // switches_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> switches_s1_agent:rdata_fifo_sink_error
wire leds_s1_agent_rdata_fifo_src_valid; // LEDs_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
wire [33:0] leds_s1_agent_rdata_fifo_src_data; // LEDs_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
wire leds_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> LEDs_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> LEDs_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> LEDs_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // LEDs_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> LEDs_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) nios2_qsys_0_data_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
.av_read (nios2_qsys_0_data_master_read), // .read
.av_readdata (nios2_qsys_0_data_master_readdata), // .readdata
.av_write (nios2_qsys_0_data_master_write), // .write
.av_writedata (nios2_qsys_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_qsys_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_qsys_0_instruction_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_qsys_0_instruction_master_read), // .read
.av_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_0_avalon_jtag_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_0_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_0_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_0_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_0_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_0_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_0_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_0_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_0_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_0_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_0_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_qsys_0_jtag_debug_module_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_0_jtag_debug_module_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_qsys_0_jtag_debug_module_agent_m0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_jtag_debug_module_agent_m0_read), // .read
.uav_write (nios2_qsys_0_jtag_debug_module_agent_m0_write), // .write
.uav_waitrequest (nios2_qsys_0_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_jtag_debug_module_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_jtag_debug_module_agent_m0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_jtag_debug_module_agent_m0_writedata), // .writedata
.uav_lock (nios2_qsys_0_jtag_debug_module_agent_m0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_jtag_debug_module_address), // avalon_anti_slave_0.address
.av_write (nios2_qsys_0_jtag_debug_module_write), // .write
.av_read (nios2_qsys_0_jtag_debug_module_read), // .read
.av_readdata (nios2_qsys_0_jtag_debug_module_readdata), // .readdata
.av_writedata (nios2_qsys_0_jtag_debug_module_writedata), // .writedata
.av_byteenable (nios2_qsys_0_jtag_debug_module_byteenable), // .byteenable
.av_waitrequest (nios2_qsys_0_jtag_debug_module_waitrequest), // .waitrequest
.av_debugaccess (nios2_qsys_0_jtag_debug_module_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (10),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_write), // .write
.av_readdata (onchip_memory2_0_s1_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) switches_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (switches_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (switches_s1_agent_m0_burstcount), // .burstcount
.uav_read (switches_s1_agent_m0_read), // .read
.uav_write (switches_s1_agent_m0_write), // .write
.uav_waitrequest (switches_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (switches_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (switches_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (switches_s1_agent_m0_readdata), // .readdata
.uav_writedata (switches_s1_agent_m0_writedata), // .writedata
.uav_lock (switches_s1_agent_m0_lock), // .lock
.uav_debugaccess (switches_s1_agent_m0_debugaccess), // .debugaccess
.av_address (switches_s1_address), // avalon_anti_slave_0.address
.av_readdata (switches_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) leds_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (leds_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (leds_s1_agent_m0_burstcount), // .burstcount
.uav_read (leds_s1_agent_m0_read), // .read
.uav_write (leds_s1_agent_m0_write), // .write
.uav_waitrequest (leds_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (leds_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (leds_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (leds_s1_agent_m0_readdata), // .readdata
.uav_writedata (leds_s1_agent_m0_writedata), // .writedata
.uav_lock (leds_s1_agent_m0_lock), // .lock
.uav_debugaccess (leds_s1_agent_m0_debugaccess), // .debugaccess
.av_address (LEDs_s1_address), // avalon_anti_slave_0.address
.av_write (LEDs_s1_write), // .write
.av_readdata (LEDs_s1_readdata), // .readdata
.av_writedata (LEDs_s1_writedata), // .writedata
.av_chipselect (LEDs_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (89),
.PKT_ORI_BURST_SIZE_L (87),
.PKT_RESPONSE_STATUS_H (86),
.PKT_RESPONSE_STATUS_L (85),
.PKT_QOS_H (70),
.PKT_QOS_L (70),
.PKT_DATA_SIDEBAND_H (68),
.PKT_DATA_SIDEBAND_L (68),
.PKT_ADDR_SIDEBAND_H (67),
.PKT_ADDR_SIDEBAND_L (67),
.PKT_BURST_TYPE_H (66),
.PKT_BURST_TYPE_L (65),
.PKT_CACHE_H (84),
.PKT_CACHE_L (81),
.PKT_THREAD_ID_H (77),
.PKT_THREAD_ID_L (77),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.PKT_TRANS_EXCLUSIVE (55),
.PKT_TRANS_LOCK (54),
.PKT_BEGIN_BURST (69),
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (71),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (74),
.ST_DATA_W (90),
.ST_CHANNEL_W (5),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_0_data_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_qsys_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_0_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_0_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_0_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_0_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_0_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (89),
.PKT_ORI_BURST_SIZE_L (87),
.PKT_RESPONSE_STATUS_H (86),
.PKT_RESPONSE_STATUS_L (85),
.PKT_QOS_H (70),
.PKT_QOS_L (70),
.PKT_DATA_SIDEBAND_H (68),
.PKT_DATA_SIDEBAND_L (68),
.PKT_ADDR_SIDEBAND_H (67),
.PKT_ADDR_SIDEBAND_L (67),
.PKT_BURST_TYPE_H (66),
.PKT_BURST_TYPE_L (65),
.PKT_CACHE_H (84),
.PKT_CACHE_L (81),
.PKT_THREAD_ID_H (77),
.PKT_THREAD_ID_L (77),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.PKT_TRANS_EXCLUSIVE (55),
.PKT_TRANS_LOCK (54),
.PKT_BEGIN_BURST (69),
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (71),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (74),
.ST_DATA_W (90),
.ST_CHANNEL_W (5),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_0_instruction_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_0_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_0_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_0_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (89),
.PKT_ORI_BURST_SIZE_L (87),
.PKT_RESPONSE_STATUS_H (86),
.PKT_RESPONSE_STATUS_L (85),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.PKT_TRANS_LOCK (54),
.PKT_BEGIN_BURST (69),
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (71),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (74),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (90),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) jtag_uart_0_avalon_jtag_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_0_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_0_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_0_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_0_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_0_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_0_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_0_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_0_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_0_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_0_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (91),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_0_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (89),
.PKT_ORI_BURST_SIZE_L (87),
.PKT_RESPONSE_STATUS_H (86),
.PKT_RESPONSE_STATUS_L (85),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.PKT_TRANS_LOCK (54),
.PKT_BEGIN_BURST (69),
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (71),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (74),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (90),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) nios2_qsys_0_jtag_debug_module_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_qsys_0_jtag_debug_module_agent_m0_address), // m0.address
.m0_burstcount (nios2_qsys_0_jtag_debug_module_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_qsys_0_jtag_debug_module_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_qsys_0_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_qsys_0_jtag_debug_module_agent_m0_lock), // .lock
.m0_readdata (nios2_qsys_0_jtag_debug_module_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_qsys_0_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_qsys_0_jtag_debug_module_agent_m0_read), // .read
.m0_waitrequest (nios2_qsys_0_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_qsys_0_jtag_debug_module_agent_m0_writedata), // .writedata
.m0_write (nios2_qsys_0_jtag_debug_module_agent_m0_write), // .write
.rp_endofpacket (nios2_qsys_0_jtag_debug_module_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_qsys_0_jtag_debug_module_agent_rp_ready), // .ready
.rp_valid (nios2_qsys_0_jtag_debug_module_agent_rp_valid), // .valid
.rp_data (nios2_qsys_0_jtag_debug_module_agent_rp_data), // .data
.rp_startofpacket (nios2_qsys_0_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_qsys_0_jtag_debug_module_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_qsys_0_jtag_debug_module_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_qsys_0_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_qsys_0_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_qsys_0_jtag_debug_module_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (nios2_qsys_0_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_qsys_0_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_qsys_0_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (91),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_qsys_0_jtag_debug_module_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_qsys_0_jtag_debug_module_agent_rf_source_data), // in.data
.in_valid (nios2_qsys_0_jtag_debug_module_agent_rf_source_valid), // .valid
.in_ready (nios2_qsys_0_jtag_debug_module_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_qsys_0_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_qsys_0_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_qsys_0_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (89),
.PKT_ORI_BURST_SIZE_L (87),
.PKT_RESPONSE_STATUS_H (86),
.PKT_RESPONSE_STATUS_L (85),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.PKT_TRANS_LOCK (54),
.PKT_BEGIN_BURST (69),
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (71),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (74),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (90),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_memory2_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (91),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (89),
.PKT_ORI_BURST_SIZE_L (87),
.PKT_RESPONSE_STATUS_H (86),
.PKT_RESPONSE_STATUS_L (85),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.PKT_TRANS_LOCK (54),
.PKT_BEGIN_BURST (69),
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (71),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (74),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (90),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) switches_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (switches_s1_agent_m0_address), // m0.address
.m0_burstcount (switches_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (switches_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (switches_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (switches_s1_agent_m0_lock), // .lock
.m0_readdata (switches_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (switches_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (switches_s1_agent_m0_read), // .read
.m0_waitrequest (switches_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (switches_s1_agent_m0_writedata), // .writedata
.m0_write (switches_s1_agent_m0_write), // .write
.rp_endofpacket (switches_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (switches_s1_agent_rp_ready), // .ready
.rp_valid (switches_s1_agent_rp_valid), // .valid
.rp_data (switches_s1_agent_rp_data), // .data
.rp_startofpacket (switches_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (switches_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (switches_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (switches_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (switches_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (switches_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (switches_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (switches_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (switches_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (switches_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (switches_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (switches_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (switches_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (switches_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (91),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) switches_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (switches_s1_agent_rf_source_data), // in.data
.in_valid (switches_s1_agent_rf_source_valid), // .valid
.in_ready (switches_s1_agent_rf_source_ready), // .ready
.in_startofpacket (switches_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (switches_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (switches_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (switches_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (switches_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (switches_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (switches_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (89),
.PKT_ORI_BURST_SIZE_L (87),
.PKT_RESPONSE_STATUS_H (86),
.PKT_RESPONSE_STATUS_L (85),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.PKT_TRANS_LOCK (54),
.PKT_BEGIN_BURST (69),
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (71),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (74),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (90),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) leds_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (leds_s1_agent_m0_address), // m0.address
.m0_burstcount (leds_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (leds_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (leds_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (leds_s1_agent_m0_lock), // .lock
.m0_readdata (leds_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (leds_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (leds_s1_agent_m0_read), // .read
.m0_waitrequest (leds_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (leds_s1_agent_m0_writedata), // .writedata
.m0_write (leds_s1_agent_m0_write), // .write
.rp_endofpacket (leds_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (leds_s1_agent_rp_ready), // .ready
.rp_valid (leds_s1_agent_rp_valid), // .valid
.rp_data (leds_s1_agent_rp_data), // .data
.rp_startofpacket (leds_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (leds_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (leds_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (leds_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (leds_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (leds_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (leds_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (leds_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (leds_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (leds_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (leds_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (leds_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (leds_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (leds_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (91),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) leds_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (leds_s1_agent_rf_source_data), // in.data
.in_valid (leds_s1_agent_rf_source_valid), // .valid
.in_ready (leds_s1_agent_rf_source_ready), // .ready
.in_startofpacket (leds_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (leds_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (leds_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (leds_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (leds_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (leds_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (leds_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
lights_mm_interconnect_0_router router (
.sink_ready (nios2_qsys_0_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_0_data_master_agent_cp_valid), // .valid
.sink_data (nios2_qsys_0_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_0_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_data_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_router_001 router_001 (
.sink_ready (nios2_qsys_0_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_0_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_qsys_0_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_router_002 router_002 (
.sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_0_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_router_003 router_003 (
.sink_ready (nios2_qsys_0_jtag_debug_module_agent_rp_ready), // sink.ready
.sink_valid (nios2_qsys_0_jtag_debug_module_agent_rp_valid), // .valid
.sink_data (nios2_qsys_0_jtag_debug_module_agent_rp_data), // .data
.sink_startofpacket (nios2_qsys_0_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_jtag_debug_module_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_router_003 router_004 (
.sink_ready (onchip_memory2_0_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_router_002 router_005 (
.sink_ready (switches_s1_agent_rp_ready), // sink.ready
.sink_valid (switches_s1_agent_rp_valid), // .valid
.sink_data (switches_s1_agent_rp_data), // .data
.sink_startofpacket (switches_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (switches_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_router_002 router_006 (
.sink_ready (leds_s1_agent_rp_ready), // sink.ready
.sink_valid (leds_s1_agent_rp_valid), // .valid
.sink_data (leds_s1_agent_rp_data), // .data
.sink_startofpacket (leds_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (leds_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_cmd_mux_001 cmd_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_cmd_mux cmd_mux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_cmd_demux_001 rsp_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_cmd_demux_001 rsp_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_rsp_demux rsp_demux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src1_valid), // .valid
.sink0_channel (rsp_demux_001_src1_channel), // .channel
.sink0_data (rsp_demux_001_src1_data), // .data
.sink0_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_002_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_002_src1_valid), // .valid
.sink1_channel (rsp_demux_002_src1_channel), // .channel
.sink1_data (rsp_demux_002_src1_data), // .data
.sink1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
lights_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
lights_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (nios2_qsys_0_jtag_debug_module_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (nios2_qsys_0_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (nios2_qsys_0_jtag_debug_module_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
lights_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
lights_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (switches_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (switches_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (switches_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
lights_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_qsys_0_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (leds_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (leds_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (leds_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_hdr_fifo.v
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The tx_hdr_fifo module implements a simple fifo for a packet
// (WR_TX_HDR) header and three metadata signals: WR_TX_HDR_ABLANKS,
// WR_TX_HDR_LEN, WR_TX_HDR_NOPAYLOAD. NOPAYLOAD indicates that the header is not
// followed by a payload. HDR_LEN indicates the length of the header in
// dwords. The ABLANKS signal indicates how many dwords should be inserted between
// the header and payload.
//
// The intended use for this module is between the interface specific tx formatter
// (TXC or TXR) and the alignment pipeline, in parallel with the tx_data_pipeline
// which contains a fifo for payloads.
//
// Author: Dustin Richmond (@darichmond)
// Co-Authors:
//----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_hdr_fifo
#(parameter C_DEPTH_PACKETS = 10,
parameter C_MAX_HDR_WIDTH = 128,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_PIPELINE_INPUT = 1,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: WR_TX_HDR
input WR_TX_HDR_VALID,
input [(C_MAX_HDR_WIDTH)-1:0] WR_TX_HDR,
input [`SIG_LEN_W-1:0] WR_TX_HDR_PAYLOAD_LEN,
input [`SIG_NONPAY_W-1:0] WR_TX_HDR_NONPAY_LEN,
input [`SIG_PACKETLEN_W-1:0] WR_TX_HDR_PACKET_LEN,
input WR_TX_HDR_NOPAYLOAD,
output WR_TX_HDR_READY,
// Interface: RD_TX_HDR
output RD_TX_HDR_VALID,
output [(C_MAX_HDR_WIDTH)-1:0] RD_TX_HDR,
output [`SIG_LEN_W-1:0] RD_TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] RD_TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] RD_TX_HDR_PACKET_LEN,
output RD_TX_HDR_NOPAYLOAD,
input RD_TX_HDR_READY
);
// Size of the header, plus the three metadata signals
localparam C_WIDTH = (C_MAX_HDR_WIDTH) + `SIG_NONPAY_W + `SIG_PACKETLEN_W + 1 + `SIG_LEN_W;
wire RST;
wire wWrTxHdrReady;
wire wWrTxHdrValid;
wire [(C_MAX_HDR_WIDTH)-1:0] wWrTxHdr;
wire [`SIG_NONPAY_W-1:0] wWrTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wWrTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wWrTxHdrPayloadLen;
wire wWrTxHdrNoPayload;
wire wRdTxHdrReady;
wire wRdTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wRdTxHdr;
wire [`SIG_NONPAY_W-1:0] wRdTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wRdTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wRdTxHdrPayloadLen;
wire wRdTxHdrNoPayload;
assign RST = RST_IN;
pipeline
#(
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
input_pipeline_inst
(
// Outputs
.WR_DATA_READY (WR_TX_HDR_READY),
.RD_DATA ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
.RD_DATA_VALID (wWrTxHdrValid),
// Inputs
.WR_DATA ({WR_TX_HDR,WR_TX_HDR_NONPAY_LEN,WR_TX_HDR_PACKET_LEN,WR_TX_HDR_PAYLOAD_LEN,WR_TX_HDR_NOPAYLOAD}),
.WR_DATA_VALID (WR_TX_HDR_VALID),
.RD_DATA_READY (wWrTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
fifo
#(
// Parameters
.C_DELAY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH),
.C_DEPTH (C_DEPTH_PACKETS))
fifo_inst
(
// Outputs
.RD_DATA ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
.WR_READY (wWrTxHdrReady),
.RD_VALID (wRdTxHdrValid),
// Inputs
.WR_DATA ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
.WR_VALID (wWrTxHdrValid),
.RD_READY (wRdTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST (RST));
pipeline
#(
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
output_pipeline_inst
(
// Outputs
.WR_DATA_READY (wRdTxHdrReady),
.RD_DATA ({RD_TX_HDR,RD_TX_HDR_NONPAY_LEN,RD_TX_HDR_PACKET_LEN,RD_TX_HDR_PAYLOAD_LEN,RD_TX_HDR_NOPAYLOAD}),
.RD_DATA_VALID (RD_TX_HDR_VALID),
// Inputs
.WR_DATA ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
.WR_DATA_VALID (wRdTxHdrValid),
.RD_DATA_READY (RD_TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/")
// End:
|
/* Argmin helper is the recursive step of the argmin function.
*
* Copyright (c) 2016, Stephen Longfield, stephenlongfield.com
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`ifndef CENSUS_ARGMIN_HELPER_V_
`define CENSUS_ARGMIN_HELPER_V_
`include "argmin_stage.v"
`include "dff.v"
// Argmin helper is an individual 'layer' of the argmin tree.
// Argmin is made out of a pipelined tree of argmin helpers, each of which looks
// to see if the left or right value is smaller, and then forwards along the
// minimum value, along with the 'address' of the minimum for the section of the
// list it's scanned so far. For instance, for a length-6 list:
//
// Out
// _|_
// 0/ \1
// __|__ |___
// 0/ \1 \0
// X X X
// 0/ \1 0/ \1 0/ \1
// 0 1 2 3 4 5
//
// If element 3 is the minimum, then follow the path from the output back to
// 3 to get the address, 011, or 3. Note that when a layer isn't a multiple of
// two long, a pass-through stage is used.
module argmin_helper#(
parameter WIDTH=1,
parameter ADDR_WIDTH=1,
parameter NUM_INP=2,
parameter NUM_OUTP=1,
parameter STAGE=1
) (
input wire clk,
input wire rst,
input wire [WIDTH*NUM_INP-1:0] inp,
input wire [ADDR_WIDTH*NUM_INP-1:0] inp_addr,
output wire [WIDTH*NUM_OUTP-1:0] outp,
output wire [ADDR_WIDTH*NUM_OUTP-1:0] outp_addr
);
localparam INP_WIDTH = WIDTH*NUM_INP;
localparam INP_A_WIDTH = ADDR_WIDTH*NUM_INP;
// Unpack the input words
wire [WIDTH-1:0] inp_word[NUM_INP];
wire [ADDR_WIDTH-1:0] inp_addr_word[NUM_INP];
genvar i;
generate
for (i = 0; i < NUM_INP; i++) begin
assign inp_word[i] = inp[(INP_WIDTH-WIDTH*i-1):(INP_WIDTH-WIDTH*(i+1))];
assign inp_addr_word[i] = inp_addr[(INP_A_WIDTH-ADDR_WIDTH*i-1):
(INP_A_WIDTH-ADDR_WIDTH*(i+1))];
end
endgenerate
localparam OUTP_WIDTH = WIDTH*NUM_OUTP;
localparam OUTP_A_WIDTH = ADDR_WIDTH*NUM_OUTP;
// Pack the output words
wire [WIDTH-1:0] outp_word[NUM_OUTP];
wire [ADDR_WIDTH-1:0] outp_addr_word[NUM_OUTP];
genvar j;
generate
for (j = 0; j < NUM_OUTP; j++) begin
assign outp[(OUTP_WIDTH-WIDTH*j-1):(OUTP_WIDTH-WIDTH*(j+1))] = outp_word[j];
assign outp_addr[(OUTP_A_WIDTH-ADDR_WIDTH*j-1):
(OUTP_A_WIDTH-ADDR_WIDTH*(j+1))] = outp_addr_word[j];
end
endgenerate
// Create the different argmin stages.
genvar k;
generate
for (k = 0; k < NUM_INP; k += 2) begin : node
if (k+2 > NUM_INP) begin
// This will be satisfied iff NUM_INP is odd, and we are at the end of the
// list. If that's the case, generate pass-through flip-flops instead of
// the argmin stage.
dff#(.WIDTH(WIDTH)) val(clk, rst, inp_word[k], outp_word[k/2]);
dff#(.WIDTH(ADDR_WIDTH)) addr(clk, rst, inp_addr_word[k],
outp_addr_word[k/2]);
end else begin
// Otherwise, generate an argmin_stage that reduces two inputs to a single
// output.
argmin_stage#(.WIDTH(WIDTH), .ADDR_WIDTH(ADDR_WIDTH), .STAGE(STAGE))
as(clk, rst, inp_word[k], inp_addr_word[k], inp_word[k+1],
inp_addr_word[k+1],
outp_word[k/2], outp_addr_word[k/2]);
end
end
endgenerate
endmodule
`endif // CENSUS_ARGMIN_HELPER_V_
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/26 19:35:42
// Design Name:
// Module Name: fulladder_dataflow_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fulladder_dataflow_tb();
reg a, b, cin;
wire cout, s;
reg e_cout,e_s;
integer i;
fulladder_dataflow DUT (.a(a), .b(b), .cin(cin), .cout(cout), .s(s));
function expected_s;
input a,b,cin;
begin
expected_s = a ^ b ^ cin;
end
endfunction
function expected_cout;
input a,b,cin;
begin
expected_cout = ((a ^ b)&cin) | (a & b);
end
endfunction
initial
begin
for(i=0;i<=8;i=i+1)
begin
#50 {cin,b,a} = i;
#10 e_cout = expected_cout(a,b,cin);e_s = expected_s(a,b,cin);
if((cout == e_cout) &&(s == e_s))
$display("Test Passed");
else
$display("Test Failed");
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND2_TB_V
`define SKY130_FD_SC_HS__TAPVGND2_TB_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__tapvgnd2.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VPWR = 1'b0;
#60 VGND = 1'b1;
#80 VPWR = 1'b1;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 VPWR = 1'b1;
#160 VGND = 1'b1;
#180 VPWR = 1'bx;
#200 VGND = 1'bx;
end
sky130_fd_sc_hs__tapvgnd2 dut (.VPWR(VPWR), .VGND(VGND));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND2_TB_V
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_cpu_s1_test_bench (
// inputs:
A_bstatus_reg,
A_ctrl_ld_non_io,
A_en,
A_estatus_reg,
A_status_reg,
A_valid,
A_wr_data_unfiltered,
A_wr_dst_reg,
E_add_br_to_taken_history_unfiltered,
E_valid,
M_bht_ptr_unfiltered,
M_bht_wr_data_unfiltered,
M_bht_wr_en_unfiltered,
M_mem_baddr,
M_target_pcb,
M_valid,
W_dst_regnum,
W_iw,
W_iw_op,
W_iw_opx,
W_pcb,
W_valid,
W_vinst,
W_wr_dst_reg,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdatavalid,
reset_n,
// outputs:
A_wr_data_filtered,
E_add_br_to_taken_history_filtered,
M_bht_ptr_filtered,
M_bht_wr_data_filtered,
M_bht_wr_en_filtered,
test_has_ended
)
;
output [ 31: 0] A_wr_data_filtered;
output E_add_br_to_taken_history_filtered;
output [ 7: 0] M_bht_ptr_filtered;
output [ 1: 0] M_bht_wr_data_filtered;
output M_bht_wr_en_filtered;
output test_has_ended;
input [ 31: 0] A_bstatus_reg;
input A_ctrl_ld_non_io;
input A_en;
input [ 31: 0] A_estatus_reg;
input [ 31: 0] A_status_reg;
input A_valid;
input [ 31: 0] A_wr_data_unfiltered;
input A_wr_dst_reg;
input E_add_br_to_taken_history_unfiltered;
input E_valid;
input [ 7: 0] M_bht_ptr_unfiltered;
input [ 1: 0] M_bht_wr_data_unfiltered;
input M_bht_wr_en_unfiltered;
input [ 27: 0] M_mem_baddr;
input [ 27: 0] M_target_pcb;
input M_valid;
input [ 4: 0] W_dst_regnum;
input [ 31: 0] W_iw;
input [ 5: 0] W_iw_op;
input [ 5: 0] W_iw_opx;
input [ 27: 0] W_pcb;
input W_valid;
input [ 55: 0] W_vinst;
input W_wr_dst_reg;
input clk;
input [ 27: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 27: 0] i_address;
input i_read;
input i_readdatavalid;
input reset_n;
reg [ 27: 0] A_mem_baddr;
reg [ 27: 0] A_target_pcb;
wire [ 31: 0] A_wr_data_filtered;
wire A_wr_data_unfiltered_0_is_x;
wire A_wr_data_unfiltered_10_is_x;
wire A_wr_data_unfiltered_11_is_x;
wire A_wr_data_unfiltered_12_is_x;
wire A_wr_data_unfiltered_13_is_x;
wire A_wr_data_unfiltered_14_is_x;
wire A_wr_data_unfiltered_15_is_x;
wire A_wr_data_unfiltered_16_is_x;
wire A_wr_data_unfiltered_17_is_x;
wire A_wr_data_unfiltered_18_is_x;
wire A_wr_data_unfiltered_19_is_x;
wire A_wr_data_unfiltered_1_is_x;
wire A_wr_data_unfiltered_20_is_x;
wire A_wr_data_unfiltered_21_is_x;
wire A_wr_data_unfiltered_22_is_x;
wire A_wr_data_unfiltered_23_is_x;
wire A_wr_data_unfiltered_24_is_x;
wire A_wr_data_unfiltered_25_is_x;
wire A_wr_data_unfiltered_26_is_x;
wire A_wr_data_unfiltered_27_is_x;
wire A_wr_data_unfiltered_28_is_x;
wire A_wr_data_unfiltered_29_is_x;
wire A_wr_data_unfiltered_2_is_x;
wire A_wr_data_unfiltered_30_is_x;
wire A_wr_data_unfiltered_31_is_x;
wire A_wr_data_unfiltered_3_is_x;
wire A_wr_data_unfiltered_4_is_x;
wire A_wr_data_unfiltered_5_is_x;
wire A_wr_data_unfiltered_6_is_x;
wire A_wr_data_unfiltered_7_is_x;
wire A_wr_data_unfiltered_8_is_x;
wire A_wr_data_unfiltered_9_is_x;
wire E_add_br_to_taken_history_filtered;
wire [ 7: 0] M_bht_ptr_filtered;
wire [ 1: 0] M_bht_wr_data_filtered;
wire M_bht_wr_en_filtered;
wire W_op_add;
wire W_op_addi;
wire W_op_and;
wire W_op_andhi;
wire W_op_andi;
wire W_op_beq;
wire W_op_bge;
wire W_op_bgeu;
wire W_op_blt;
wire W_op_bltu;
wire W_op_bne;
wire W_op_br;
wire W_op_break;
wire W_op_bret;
wire W_op_call;
wire W_op_callr;
wire W_op_cmpeq;
wire W_op_cmpeqi;
wire W_op_cmpge;
wire W_op_cmpgei;
wire W_op_cmpgeu;
wire W_op_cmpgeui;
wire W_op_cmplt;
wire W_op_cmplti;
wire W_op_cmpltu;
wire W_op_cmpltui;
wire W_op_cmpne;
wire W_op_cmpnei;
wire W_op_crst;
wire W_op_custom;
wire W_op_div;
wire W_op_divu;
wire W_op_eret;
wire W_op_flushd;
wire W_op_flushda;
wire W_op_flushi;
wire W_op_flushp;
wire W_op_hbreak;
wire W_op_initd;
wire W_op_initda;
wire W_op_initi;
wire W_op_intr;
wire W_op_jmp;
wire W_op_jmpi;
wire W_op_ldb;
wire W_op_ldbio;
wire W_op_ldbu;
wire W_op_ldbuio;
wire W_op_ldh;
wire W_op_ldhio;
wire W_op_ldhu;
wire W_op_ldhuio;
wire W_op_ldl;
wire W_op_ldw;
wire W_op_ldwio;
wire W_op_mul;
wire W_op_muli;
wire W_op_mulxss;
wire W_op_mulxsu;
wire W_op_mulxuu;
wire W_op_nextpc;
wire W_op_nor;
wire W_op_opx;
wire W_op_or;
wire W_op_orhi;
wire W_op_ori;
wire W_op_rdctl;
wire W_op_rdprs;
wire W_op_ret;
wire W_op_rol;
wire W_op_roli;
wire W_op_ror;
wire W_op_rsv02;
wire W_op_rsv09;
wire W_op_rsv10;
wire W_op_rsv17;
wire W_op_rsv18;
wire W_op_rsv25;
wire W_op_rsv26;
wire W_op_rsv33;
wire W_op_rsv34;
wire W_op_rsv41;
wire W_op_rsv42;
wire W_op_rsv49;
wire W_op_rsv57;
wire W_op_rsv61;
wire W_op_rsv62;
wire W_op_rsv63;
wire W_op_rsvx00;
wire W_op_rsvx10;
wire W_op_rsvx15;
wire W_op_rsvx17;
wire W_op_rsvx21;
wire W_op_rsvx25;
wire W_op_rsvx33;
wire W_op_rsvx34;
wire W_op_rsvx35;
wire W_op_rsvx42;
wire W_op_rsvx43;
wire W_op_rsvx44;
wire W_op_rsvx47;
wire W_op_rsvx50;
wire W_op_rsvx51;
wire W_op_rsvx55;
wire W_op_rsvx56;
wire W_op_rsvx60;
wire W_op_rsvx63;
wire W_op_sll;
wire W_op_slli;
wire W_op_sra;
wire W_op_srai;
wire W_op_srl;
wire W_op_srli;
wire W_op_stb;
wire W_op_stbio;
wire W_op_stc;
wire W_op_sth;
wire W_op_sthio;
wire W_op_stw;
wire W_op_stwio;
wire W_op_sub;
wire W_op_sync;
wire W_op_trap;
wire W_op_wrctl;
wire W_op_wrprs;
wire W_op_xor;
wire W_op_xorhi;
wire W_op_xori;
wire test_has_ended;
assign W_op_call = W_iw_op == 0;
assign W_op_jmpi = W_iw_op == 1;
assign W_op_ldbu = W_iw_op == 3;
assign W_op_addi = W_iw_op == 4;
assign W_op_stb = W_iw_op == 5;
assign W_op_br = W_iw_op == 6;
assign W_op_ldb = W_iw_op == 7;
assign W_op_cmpgei = W_iw_op == 8;
assign W_op_ldhu = W_iw_op == 11;
assign W_op_andi = W_iw_op == 12;
assign W_op_sth = W_iw_op == 13;
assign W_op_bge = W_iw_op == 14;
assign W_op_ldh = W_iw_op == 15;
assign W_op_cmplti = W_iw_op == 16;
assign W_op_initda = W_iw_op == 19;
assign W_op_ori = W_iw_op == 20;
assign W_op_stw = W_iw_op == 21;
assign W_op_blt = W_iw_op == 22;
assign W_op_ldw = W_iw_op == 23;
assign W_op_cmpnei = W_iw_op == 24;
assign W_op_flushda = W_iw_op == 27;
assign W_op_xori = W_iw_op == 28;
assign W_op_stc = W_iw_op == 29;
assign W_op_bne = W_iw_op == 30;
assign W_op_ldl = W_iw_op == 31;
assign W_op_cmpeqi = W_iw_op == 32;
assign W_op_ldbuio = W_iw_op == 35;
assign W_op_muli = W_iw_op == 36;
assign W_op_stbio = W_iw_op == 37;
assign W_op_beq = W_iw_op == 38;
assign W_op_ldbio = W_iw_op == 39;
assign W_op_cmpgeui = W_iw_op == 40;
assign W_op_ldhuio = W_iw_op == 43;
assign W_op_andhi = W_iw_op == 44;
assign W_op_sthio = W_iw_op == 45;
assign W_op_bgeu = W_iw_op == 46;
assign W_op_ldhio = W_iw_op == 47;
assign W_op_cmpltui = W_iw_op == 48;
assign W_op_initd = W_iw_op == 51;
assign W_op_orhi = W_iw_op == 52;
assign W_op_stwio = W_iw_op == 53;
assign W_op_bltu = W_iw_op == 54;
assign W_op_ldwio = W_iw_op == 55;
assign W_op_rdprs = W_iw_op == 56;
assign W_op_flushd = W_iw_op == 59;
assign W_op_xorhi = W_iw_op == 60;
assign W_op_rsv02 = W_iw_op == 2;
assign W_op_rsv09 = W_iw_op == 9;
assign W_op_rsv10 = W_iw_op == 10;
assign W_op_rsv17 = W_iw_op == 17;
assign W_op_rsv18 = W_iw_op == 18;
assign W_op_rsv25 = W_iw_op == 25;
assign W_op_rsv26 = W_iw_op == 26;
assign W_op_rsv33 = W_iw_op == 33;
assign W_op_rsv34 = W_iw_op == 34;
assign W_op_rsv41 = W_iw_op == 41;
assign W_op_rsv42 = W_iw_op == 42;
assign W_op_rsv49 = W_iw_op == 49;
assign W_op_rsv57 = W_iw_op == 57;
assign W_op_rsv61 = W_iw_op == 61;
assign W_op_rsv62 = W_iw_op == 62;
assign W_op_rsv63 = W_iw_op == 63;
assign W_op_eret = W_op_opx & (W_iw_opx == 1);
assign W_op_roli = W_op_opx & (W_iw_opx == 2);
assign W_op_rol = W_op_opx & (W_iw_opx == 3);
assign W_op_flushp = W_op_opx & (W_iw_opx == 4);
assign W_op_ret = W_op_opx & (W_iw_opx == 5);
assign W_op_nor = W_op_opx & (W_iw_opx == 6);
assign W_op_mulxuu = W_op_opx & (W_iw_opx == 7);
assign W_op_cmpge = W_op_opx & (W_iw_opx == 8);
assign W_op_bret = W_op_opx & (W_iw_opx == 9);
assign W_op_ror = W_op_opx & (W_iw_opx == 11);
assign W_op_flushi = W_op_opx & (W_iw_opx == 12);
assign W_op_jmp = W_op_opx & (W_iw_opx == 13);
assign W_op_and = W_op_opx & (W_iw_opx == 14);
assign W_op_cmplt = W_op_opx & (W_iw_opx == 16);
assign W_op_slli = W_op_opx & (W_iw_opx == 18);
assign W_op_sll = W_op_opx & (W_iw_opx == 19);
assign W_op_wrprs = W_op_opx & (W_iw_opx == 20);
assign W_op_or = W_op_opx & (W_iw_opx == 22);
assign W_op_mulxsu = W_op_opx & (W_iw_opx == 23);
assign W_op_cmpne = W_op_opx & (W_iw_opx == 24);
assign W_op_srli = W_op_opx & (W_iw_opx == 26);
assign W_op_srl = W_op_opx & (W_iw_opx == 27);
assign W_op_nextpc = W_op_opx & (W_iw_opx == 28);
assign W_op_callr = W_op_opx & (W_iw_opx == 29);
assign W_op_xor = W_op_opx & (W_iw_opx == 30);
assign W_op_mulxss = W_op_opx & (W_iw_opx == 31);
assign W_op_cmpeq = W_op_opx & (W_iw_opx == 32);
assign W_op_divu = W_op_opx & (W_iw_opx == 36);
assign W_op_div = W_op_opx & (W_iw_opx == 37);
assign W_op_rdctl = W_op_opx & (W_iw_opx == 38);
assign W_op_mul = W_op_opx & (W_iw_opx == 39);
assign W_op_cmpgeu = W_op_opx & (W_iw_opx == 40);
assign W_op_initi = W_op_opx & (W_iw_opx == 41);
assign W_op_trap = W_op_opx & (W_iw_opx == 45);
assign W_op_wrctl = W_op_opx & (W_iw_opx == 46);
assign W_op_cmpltu = W_op_opx & (W_iw_opx == 48);
assign W_op_add = W_op_opx & (W_iw_opx == 49);
assign W_op_break = W_op_opx & (W_iw_opx == 52);
assign W_op_hbreak = W_op_opx & (W_iw_opx == 53);
assign W_op_sync = W_op_opx & (W_iw_opx == 54);
assign W_op_sub = W_op_opx & (W_iw_opx == 57);
assign W_op_srai = W_op_opx & (W_iw_opx == 58);
assign W_op_sra = W_op_opx & (W_iw_opx == 59);
assign W_op_intr = W_op_opx & (W_iw_opx == 61);
assign W_op_crst = W_op_opx & (W_iw_opx == 62);
assign W_op_rsvx00 = W_op_opx & (W_iw_opx == 0);
assign W_op_rsvx10 = W_op_opx & (W_iw_opx == 10);
assign W_op_rsvx15 = W_op_opx & (W_iw_opx == 15);
assign W_op_rsvx17 = W_op_opx & (W_iw_opx == 17);
assign W_op_rsvx21 = W_op_opx & (W_iw_opx == 21);
assign W_op_rsvx25 = W_op_opx & (W_iw_opx == 25);
assign W_op_rsvx33 = W_op_opx & (W_iw_opx == 33);
assign W_op_rsvx34 = W_op_opx & (W_iw_opx == 34);
assign W_op_rsvx35 = W_op_opx & (W_iw_opx == 35);
assign W_op_rsvx42 = W_op_opx & (W_iw_opx == 42);
assign W_op_rsvx43 = W_op_opx & (W_iw_opx == 43);
assign W_op_rsvx44 = W_op_opx & (W_iw_opx == 44);
assign W_op_rsvx47 = W_op_opx & (W_iw_opx == 47);
assign W_op_rsvx50 = W_op_opx & (W_iw_opx == 50);
assign W_op_rsvx51 = W_op_opx & (W_iw_opx == 51);
assign W_op_rsvx55 = W_op_opx & (W_iw_opx == 55);
assign W_op_rsvx56 = W_op_opx & (W_iw_opx == 56);
assign W_op_rsvx60 = W_op_opx & (W_iw_opx == 60);
assign W_op_rsvx63 = W_op_opx & (W_iw_opx == 63);
assign W_op_opx = W_iw_op == 58;
assign W_op_custom = W_iw_op == 50;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_target_pcb <= 0;
else if (A_en)
A_target_pcb <= M_target_pcb;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_mem_baddr <= 0;
else if (A_en)
A_mem_baddr <= M_mem_baddr;
end
//Propagating 'X' data bits
assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered;
//Propagating 'X' data bits
assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered;
//Propagating 'X' data bits
assign M_bht_wr_data_filtered = M_bht_wr_data_unfiltered;
//Propagating 'X' data bits
assign M_bht_ptr_filtered = M_bht_ptr_unfiltered;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign A_wr_data_unfiltered_0_is_x = ^(A_wr_data_unfiltered[0]) === 1'bx;
assign A_wr_data_filtered[0] = (A_wr_data_unfiltered_0_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[0];
assign A_wr_data_unfiltered_1_is_x = ^(A_wr_data_unfiltered[1]) === 1'bx;
assign A_wr_data_filtered[1] = (A_wr_data_unfiltered_1_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[1];
assign A_wr_data_unfiltered_2_is_x = ^(A_wr_data_unfiltered[2]) === 1'bx;
assign A_wr_data_filtered[2] = (A_wr_data_unfiltered_2_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[2];
assign A_wr_data_unfiltered_3_is_x = ^(A_wr_data_unfiltered[3]) === 1'bx;
assign A_wr_data_filtered[3] = (A_wr_data_unfiltered_3_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[3];
assign A_wr_data_unfiltered_4_is_x = ^(A_wr_data_unfiltered[4]) === 1'bx;
assign A_wr_data_filtered[4] = (A_wr_data_unfiltered_4_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[4];
assign A_wr_data_unfiltered_5_is_x = ^(A_wr_data_unfiltered[5]) === 1'bx;
assign A_wr_data_filtered[5] = (A_wr_data_unfiltered_5_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[5];
assign A_wr_data_unfiltered_6_is_x = ^(A_wr_data_unfiltered[6]) === 1'bx;
assign A_wr_data_filtered[6] = (A_wr_data_unfiltered_6_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[6];
assign A_wr_data_unfiltered_7_is_x = ^(A_wr_data_unfiltered[7]) === 1'bx;
assign A_wr_data_filtered[7] = (A_wr_data_unfiltered_7_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[7];
assign A_wr_data_unfiltered_8_is_x = ^(A_wr_data_unfiltered[8]) === 1'bx;
assign A_wr_data_filtered[8] = (A_wr_data_unfiltered_8_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[8];
assign A_wr_data_unfiltered_9_is_x = ^(A_wr_data_unfiltered[9]) === 1'bx;
assign A_wr_data_filtered[9] = (A_wr_data_unfiltered_9_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[9];
assign A_wr_data_unfiltered_10_is_x = ^(A_wr_data_unfiltered[10]) === 1'bx;
assign A_wr_data_filtered[10] = (A_wr_data_unfiltered_10_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[10];
assign A_wr_data_unfiltered_11_is_x = ^(A_wr_data_unfiltered[11]) === 1'bx;
assign A_wr_data_filtered[11] = (A_wr_data_unfiltered_11_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[11];
assign A_wr_data_unfiltered_12_is_x = ^(A_wr_data_unfiltered[12]) === 1'bx;
assign A_wr_data_filtered[12] = (A_wr_data_unfiltered_12_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[12];
assign A_wr_data_unfiltered_13_is_x = ^(A_wr_data_unfiltered[13]) === 1'bx;
assign A_wr_data_filtered[13] = (A_wr_data_unfiltered_13_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[13];
assign A_wr_data_unfiltered_14_is_x = ^(A_wr_data_unfiltered[14]) === 1'bx;
assign A_wr_data_filtered[14] = (A_wr_data_unfiltered_14_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[14];
assign A_wr_data_unfiltered_15_is_x = ^(A_wr_data_unfiltered[15]) === 1'bx;
assign A_wr_data_filtered[15] = (A_wr_data_unfiltered_15_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[15];
assign A_wr_data_unfiltered_16_is_x = ^(A_wr_data_unfiltered[16]) === 1'bx;
assign A_wr_data_filtered[16] = (A_wr_data_unfiltered_16_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[16];
assign A_wr_data_unfiltered_17_is_x = ^(A_wr_data_unfiltered[17]) === 1'bx;
assign A_wr_data_filtered[17] = (A_wr_data_unfiltered_17_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[17];
assign A_wr_data_unfiltered_18_is_x = ^(A_wr_data_unfiltered[18]) === 1'bx;
assign A_wr_data_filtered[18] = (A_wr_data_unfiltered_18_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[18];
assign A_wr_data_unfiltered_19_is_x = ^(A_wr_data_unfiltered[19]) === 1'bx;
assign A_wr_data_filtered[19] = (A_wr_data_unfiltered_19_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[19];
assign A_wr_data_unfiltered_20_is_x = ^(A_wr_data_unfiltered[20]) === 1'bx;
assign A_wr_data_filtered[20] = (A_wr_data_unfiltered_20_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[20];
assign A_wr_data_unfiltered_21_is_x = ^(A_wr_data_unfiltered[21]) === 1'bx;
assign A_wr_data_filtered[21] = (A_wr_data_unfiltered_21_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[21];
assign A_wr_data_unfiltered_22_is_x = ^(A_wr_data_unfiltered[22]) === 1'bx;
assign A_wr_data_filtered[22] = (A_wr_data_unfiltered_22_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[22];
assign A_wr_data_unfiltered_23_is_x = ^(A_wr_data_unfiltered[23]) === 1'bx;
assign A_wr_data_filtered[23] = (A_wr_data_unfiltered_23_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[23];
assign A_wr_data_unfiltered_24_is_x = ^(A_wr_data_unfiltered[24]) === 1'bx;
assign A_wr_data_filtered[24] = (A_wr_data_unfiltered_24_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[24];
assign A_wr_data_unfiltered_25_is_x = ^(A_wr_data_unfiltered[25]) === 1'bx;
assign A_wr_data_filtered[25] = (A_wr_data_unfiltered_25_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[25];
assign A_wr_data_unfiltered_26_is_x = ^(A_wr_data_unfiltered[26]) === 1'bx;
assign A_wr_data_filtered[26] = (A_wr_data_unfiltered_26_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[26];
assign A_wr_data_unfiltered_27_is_x = ^(A_wr_data_unfiltered[27]) === 1'bx;
assign A_wr_data_filtered[27] = (A_wr_data_unfiltered_27_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[27];
assign A_wr_data_unfiltered_28_is_x = ^(A_wr_data_unfiltered[28]) === 1'bx;
assign A_wr_data_filtered[28] = (A_wr_data_unfiltered_28_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[28];
assign A_wr_data_unfiltered_29_is_x = ^(A_wr_data_unfiltered[29]) === 1'bx;
assign A_wr_data_filtered[29] = (A_wr_data_unfiltered_29_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[29];
assign A_wr_data_unfiltered_30_is_x = ^(A_wr_data_unfiltered[30]) === 1'bx;
assign A_wr_data_filtered[30] = (A_wr_data_unfiltered_30_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[30];
assign A_wr_data_unfiltered_31_is_x = ^(A_wr_data_unfiltered[31]) === 1'bx;
assign A_wr_data_filtered[31] = (A_wr_data_unfiltered_31_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(W_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/W_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/W_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_pcb) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/W_pcb is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_iw) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/W_iw is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_en) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/A_en is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(M_valid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/M_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_valid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/A_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (A_valid & A_en & A_wr_dst_reg)
if (^(A_wr_data_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: soc_system_cpu_s1_test_bench/A_wr_data_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_status_reg) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/A_status_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_estatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/A_estatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_bstatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/A_bstatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_readdatavalid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/i_readdatavalid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s1_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign A_wr_data_filtered = A_wr_data_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXTP_BLACKBOX_V
`define SKY130_FD_SC_LS__DFXTP_BLACKBOX_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfxtp (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXTP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__FA_FUNCTIONAL_PP_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire or2_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FA_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_PS_TB_V
`define SKY130_FD_SC_HDLL__UDP_DFF_PS_TB_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_dff_ps.v"
module top();
// Inputs are registered
reg D;
reg SET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 SET = 1'b0;
#60 D = 1'b1;
#80 SET = 1'b1;
#100 D = 1'b0;
#120 SET = 1'b0;
#140 SET = 1'b1;
#160 D = 1'b1;
#180 SET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__udp_dff$PS dut (.D(D), .SET(SET), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_PS_TB_V
|
/////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2005
//
// Title : Clock switch module for non programmable PLLs
// File : clk_switch.v
// Author : Frank Bruno
// Created : 05-Mar-2005
// RCS File : $Source:$
// Status : $Id:$
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module takes in up to 6 PLL derived clocks plus a master clock (PCI).
// This module allows the glitchless switching amongst the clock frequencies.
// The purpose of this is to allow an FPGA w/o a programmable PLL
// (ex Cyclone2) to provide us with a variety of frequencies for generating
// Pixel clock and CRT clocks.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module clk_gen_ipll_stim;
reg hb_clk;
reg hb_resetn;
reg refclk;
reg [1:0] bpp;
reg vga_mode;
reg [1:0] int_fs;
reg sync_ext;
reg [2:0] pixclksel; // input [2:0] 001= comp-ext, 100 = std-ext
// 011= comp-int, 101 = std-int
reg ext_fs;
reg [7:0] pixreg20; // Input [7:0]
reg [7:0] pixreg21; // Input [7:0]
reg [7:0] pixreg22; // Input [7:0]
reg [7:0] pixreg23; // Input [7:0]
reg [7:0] pixreg24; // Input [7:0]
reg [7:0] pixreg25; // Input [7:0]
reg [7:0] pixreg26; // Input [7:0]
reg [7:0] pixreg27; // Input [7:0]
wire pix_clk;
wire pix_clk_vga;
wire crt_clk;
wire pix_locked;
wire [2:0] counter_param;
wire [3:0] counter_type;
wire [8:0] data_in;
parameter tcp = 26.67;
clk_gen_ipll u_clk_gen_ipll
(
.hb_clk (hb_clk),
.hb_resetn (hb_resetn),
.refclk (refclk),
.bpp (bpp),
.vga_mode (vga_mode),
.int_fs (int_fs),
.sync_ext (sync_ext),
.pixclksel (pixclksel),
.ext_fs (ext_fs),
.pixreg20 (pixreg20),
.pixreg21 (pixreg21),
.pixreg22 (pixreg22),
.pixreg23 (pixreg23),
.pixreg24 (pixreg24),
.pixreg25 (pixreg25),
.pixreg26 (pixreg26),
.pixreg27 (pixreg27),
.pix_clk (pix_clk),
.pix_clk_vga (pix_clk_vga),
.crt_clk (crt_clk),
.pix_locked (pix_locked)
);
always begin
#(tcp/2) begin
hb_clk = 0;
refclk = 0;
end
#(tcp/2) begin
hb_clk = 1;
refclk = 1;
end
end
initial begin
refclk = 1;
hb_clk = 1;
hb_resetn = 0;
bpp = 1;
vga_mode = 0;
int_fs = 0;
sync_ext = 0;
pixclksel = 3; // input [2:0] 001= comp-ext, 100 = std-ext
ext_fs = 0;
pixreg20 = 8'h11;
pixreg21 = 8'h11;
pixreg22 = 8'h11;
pixreg23 = 8'h11;
pixreg24 = 8'h11;
pixreg25 = 8'h11;
pixreg26 = 8'h11;
pixreg27 = 8'h11;
#((tcp * 10) + 2)
hb_resetn = 1;
#(tcp * 1000)
pixreg21 = 8'h11;
pixreg20 = 8'hE7;
#(tcp * 1000) $stop;
end
/*
PIXEL_CLK_25175 EQU 01015h ; 25.19531 MHz, 1.17188 MHz
PIXEL_CLK_28322 EQU 0122Ch ; 28.38540 MHz, 1.04167 MHz
PIXEL_CLK_31500 EQU 00E1Dh ; 31.47320 MHz, 1.33929 MHz
PIXEL_CLK_36000 EQU 00C1Bh ; 35.93750 MHz, 1.56250 MHz
PIXEL_CLK_40000 EQU 00F3Fh ; 40.00000 MHz, 1.25000 MHz
PIXEL_CLK_49500 EQU 0091Eh ; 49.47916 MHz, 2.08333 MHz
PIXEL_CLK_50000 EQU 00C3Fh ; 50.00000 MHz, 1.56250 MHz
PIXEL_CLK_54375 EQU 00A33h ; 54.37500 MHz, 1.87500 MHz
PIXEL_CLK_56250 EQU 00713h ; 56.24999 MHz, 2.67857 MHz
PIXEL_CLK_65000 EQU 00720h ; 64.95535 MHz, 2.67857 MHz
PIXEL_CLK_72000 EQU 01284h ; 71.87500 MHz, 1.04170 MHz
PIXEL_CLK_75000 EQU 0083Fh ; 75.00000 MHz, 2.34375 MHz
PIXEL_CLK_78750 EQU 00A53h ; 78.75000 MHz, 1.87500 MHz
PIXEL_CLK_80000 EQU 00F7Fh ; 80.00000 MHz, 1.25000 MHz
PIXEL_CLK_88125 EQU 00A5Dh ; 88.12500 MHz, 1.87500 MHz
PIXEL_CLK_94200 EQU 01FCDh ; 94.35480 MHz, 1.20968 MHz
PIXEL_CLK_94500 EQU 00C78h ; 94.53125 MHz, 1.56250 MHz
PIXEL_CLK_102778 EQU 01BC9h ; 102.77780 MHz, 1.38890 MHz
PIXEL_CLK_108000 EQU 019C7h ; 108.00000 MHz, 1.50000 MHz
PIXEL_CLK_108500 EQU 00750h ; 108.48212 MHz, 2.67857 MHz
PIXEL_CLK_121500 EQU 019D0h ; 121.50000 MHz, 1.50000 MHz
PIXEL_CLK_135000 EQU 00A87h ; 135.00000 MHz, 1.87500 MHz
PIXEL_CLK_157500 EQU 00A93h ; 157.50000 MHz, 1.87500 MHz
PIXEL_CLK_158400 EQU 016DCh ; 158.52269 MHz, 1.70455 MHz
PIXEL_CLK_162000 EQU 019EBh ; 162.00000 MHz, 1.50000 MHz
PIXEL_CLK_173000 EQU 00992h ; 172.91664 MHz, 2.08333 MHz
PIXEL_CLK_175500 EQU 00BA6h ; 176.56813 MHz, 1.70455 MHz
PIXEL_CLK_189000 EQU 019FDh ; 189.00000 MHz, 1.50000 MHz
PIXEL_CLK_198000 EQU 0099Eh ; 197.91664 MHz, 2.08333 MHz
PIXEL_CLK_202500 EQU 00FD0h ; 202.50000 MHz, 2.50000 MHz
PIXEL_CLK_216000 EQU 015F8h ; 216.07140 MHz, 1.78571 MHz
PIXEL_CLK_229500 EQU 011E7h ; 229.41173 MHz, 2.20588 MHz
*/
endmodule
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Fri Apr 1 16:03:12 2016
//Host : ubuntu-desktop running 64-bit Ubuntu 14.04.4 LTS
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire GND_1;
wire VCC_1;
wire [31:0]axi_dma_0_M_AXI_S2MM_AWADDR;
wire [1:0]axi_dma_0_M_AXI_S2MM_AWBURST;
wire [3:0]axi_dma_0_M_AXI_S2MM_AWCACHE;
wire [7:0]axi_dma_0_M_AXI_S2MM_AWLEN;
wire [2:0]axi_dma_0_M_AXI_S2MM_AWPROT;
wire axi_dma_0_M_AXI_S2MM_AWREADY;
wire [2:0]axi_dma_0_M_AXI_S2MM_AWSIZE;
wire axi_dma_0_M_AXI_S2MM_AWVALID;
wire axi_dma_0_M_AXI_S2MM_BREADY;
wire [1:0]axi_dma_0_M_AXI_S2MM_BRESP;
wire axi_dma_0_M_AXI_S2MM_BVALID;
wire [31:0]axi_dma_0_M_AXI_S2MM_WDATA;
wire axi_dma_0_M_AXI_S2MM_WLAST;
wire axi_dma_0_M_AXI_S2MM_WREADY;
wire [3:0]axi_dma_0_M_AXI_S2MM_WSTRB;
wire axi_dma_0_M_AXI_S2MM_WVALID;
wire axi_dma_0_s2mm_introut;
wire [7:0]axi_gpio_0_gpio_io_o;
wire [0:0]axi_gpio_1_gpio_io_o;
wire [31:0]axi_mem_intercon_M00_AXI_AWADDR;
wire [1:0]axi_mem_intercon_M00_AXI_AWBURST;
wire [3:0]axi_mem_intercon_M00_AXI_AWCACHE;
wire [3:0]axi_mem_intercon_M00_AXI_AWLEN;
wire [1:0]axi_mem_intercon_M00_AXI_AWLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_AWPROT;
wire [3:0]axi_mem_intercon_M00_AXI_AWQOS;
wire axi_mem_intercon_M00_AXI_AWREADY;
wire [2:0]axi_mem_intercon_M00_AXI_AWSIZE;
wire axi_mem_intercon_M00_AXI_AWVALID;
wire axi_mem_intercon_M00_AXI_BREADY;
wire [1:0]axi_mem_intercon_M00_AXI_BRESP;
wire axi_mem_intercon_M00_AXI_BVALID;
wire [63:0]axi_mem_intercon_M00_AXI_WDATA;
wire axi_mem_intercon_M00_AXI_WLAST;
wire axi_mem_intercon_M00_AXI_WREADY;
wire [7:0]axi_mem_intercon_M00_AXI_WSTRB;
wire axi_mem_intercon_M00_AXI_WVALID;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_CLK0;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [9:0]processing_system7_0_axi_periph_M00_AXI_ARADDR;
wire processing_system7_0_axi_periph_M00_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_ARVALID;
wire [9:0]processing_system7_0_axi_periph_M00_AXI_AWADDR;
wire processing_system7_0_axi_periph_M00_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_BRESP;
wire processing_system7_0_axi_periph_M00_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_RRESP;
wire processing_system7_0_axi_periph_M00_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_WDATA;
wire processing_system7_0_axi_periph_M00_AXI_WREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_WVALID;
wire [8:0]processing_system7_0_axi_periph_M01_AXI_ARADDR;
wire processing_system7_0_axi_periph_M01_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_ARVALID;
wire [8:0]processing_system7_0_axi_periph_M01_AXI_AWADDR;
wire processing_system7_0_axi_periph_M01_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_BRESP;
wire processing_system7_0_axi_periph_M01_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_RRESP;
wire processing_system7_0_axi_periph_M01_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_WDATA;
wire processing_system7_0_axi_periph_M01_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M01_AXI_WSTRB;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_WVALID;
wire [8:0]processing_system7_0_axi_periph_M02_AXI_ARADDR;
wire processing_system7_0_axi_periph_M02_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_ARVALID;
wire [8:0]processing_system7_0_axi_periph_M02_AXI_AWADDR;
wire processing_system7_0_axi_periph_M02_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_BRESP;
wire processing_system7_0_axi_periph_M02_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_RRESP;
wire processing_system7_0_axi_periph_M02_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_WDATA;
wire processing_system7_0_axi_periph_M02_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M02_AXI_WSTRB;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_WVALID;
wire [0:0]rst_processing_system7_0_100M_interconnect_aresetn;
wire [0:0]rst_processing_system7_0_100M_peripheral_aresetn;
wire [31:0]sample_generator_0_M_AXIS_TDATA;
wire sample_generator_0_M_AXIS_TLAST;
wire sample_generator_0_M_AXIS_TREADY;
wire sample_generator_0_M_AXIS_TVALID;
wire [3:0]xlconstant_0_dout;
wire [0:0]xlconstant_1_dout;
GND GND
(.G(GND_1));
VCC VCC
(.P(VCC_1));
design_1_axi_dma_0_0 axi_dma_0
(.axi_resetn(rst_processing_system7_0_100M_peripheral_aresetn),
.m_axi_s2mm_aclk(processing_system7_0_FCLK_CLK0),
.m_axi_s2mm_awaddr(axi_dma_0_M_AXI_S2MM_AWADDR),
.m_axi_s2mm_awburst(axi_dma_0_M_AXI_S2MM_AWBURST),
.m_axi_s2mm_awcache(axi_dma_0_M_AXI_S2MM_AWCACHE),
.m_axi_s2mm_awlen(axi_dma_0_M_AXI_S2MM_AWLEN),
.m_axi_s2mm_awprot(axi_dma_0_M_AXI_S2MM_AWPROT),
.m_axi_s2mm_awready(axi_dma_0_M_AXI_S2MM_AWREADY),
.m_axi_s2mm_awsize(axi_dma_0_M_AXI_S2MM_AWSIZE),
.m_axi_s2mm_awvalid(axi_dma_0_M_AXI_S2MM_AWVALID),
.m_axi_s2mm_bready(axi_dma_0_M_AXI_S2MM_BREADY),
.m_axi_s2mm_bresp(axi_dma_0_M_AXI_S2MM_BRESP),
.m_axi_s2mm_bvalid(axi_dma_0_M_AXI_S2MM_BVALID),
.m_axi_s2mm_wdata(axi_dma_0_M_AXI_S2MM_WDATA),
.m_axi_s2mm_wlast(axi_dma_0_M_AXI_S2MM_WLAST),
.m_axi_s2mm_wready(axi_dma_0_M_AXI_S2MM_WREADY),
.m_axi_s2mm_wstrb(axi_dma_0_M_AXI_S2MM_WSTRB),
.m_axi_s2mm_wvalid(axi_dma_0_M_AXI_S2MM_WVALID),
.s2mm_introut(axi_dma_0_s2mm_introut),
.s_axi_lite_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_lite_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.s_axi_lite_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.s_axi_lite_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.s_axi_lite_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.s_axi_lite_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.s_axi_lite_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.s_axi_lite_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.s_axi_lite_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.s_axi_lite_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.s_axi_lite_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.s_axi_lite_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.s_axi_lite_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.s_axi_lite_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.s_axi_lite_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.s_axi_lite_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.s_axi_lite_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID),
.s_axis_s2mm_tdata(sample_generator_0_M_AXIS_TDATA),
.s_axis_s2mm_tkeep(xlconstant_0_dout),
.s_axis_s2mm_tlast(sample_generator_0_M_AXIS_TLAST),
.s_axis_s2mm_tready(sample_generator_0_M_AXIS_TREADY),
.s_axis_s2mm_tvalid(sample_generator_0_M_AXIS_TVALID));
design_1_axi_gpio_0_0 axi_gpio_0
(.gpio_io_i({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.gpio_io_o(axi_gpio_0_gpio_io_o),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_M01_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID));
design_1_axi_gpio_1_0 axi_gpio_1
(.gpio_io_i(GND_1),
.gpio_io_o(axi_gpio_1_gpio_io_o),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_M02_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID));
design_1_axi_mem_intercon_0 axi_mem_intercon
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_awaddr(axi_mem_intercon_M00_AXI_AWADDR),
.M00_AXI_awburst(axi_mem_intercon_M00_AXI_AWBURST),
.M00_AXI_awcache(axi_mem_intercon_M00_AXI_AWCACHE),
.M00_AXI_awlen(axi_mem_intercon_M00_AXI_AWLEN),
.M00_AXI_awlock(axi_mem_intercon_M00_AXI_AWLOCK),
.M00_AXI_awprot(axi_mem_intercon_M00_AXI_AWPROT),
.M00_AXI_awqos(axi_mem_intercon_M00_AXI_AWQOS),
.M00_AXI_awready(axi_mem_intercon_M00_AXI_AWREADY),
.M00_AXI_awsize(axi_mem_intercon_M00_AXI_AWSIZE),
.M00_AXI_awvalid(axi_mem_intercon_M00_AXI_AWVALID),
.M00_AXI_bready(axi_mem_intercon_M00_AXI_BREADY),
.M00_AXI_bresp(axi_mem_intercon_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_mem_intercon_M00_AXI_BVALID),
.M00_AXI_wdata(axi_mem_intercon_M00_AXI_WDATA),
.M00_AXI_wlast(axi_mem_intercon_M00_AXI_WLAST),
.M00_AXI_wready(axi_mem_intercon_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_mem_intercon_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_mem_intercon_M00_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_awaddr(axi_dma_0_M_AXI_S2MM_AWADDR),
.S00_AXI_awburst(axi_dma_0_M_AXI_S2MM_AWBURST),
.S00_AXI_awcache(axi_dma_0_M_AXI_S2MM_AWCACHE),
.S00_AXI_awlen(axi_dma_0_M_AXI_S2MM_AWLEN),
.S00_AXI_awprot(axi_dma_0_M_AXI_S2MM_AWPROT),
.S00_AXI_awready(axi_dma_0_M_AXI_S2MM_AWREADY),
.S00_AXI_awsize(axi_dma_0_M_AXI_S2MM_AWSIZE),
.S00_AXI_awvalid(axi_dma_0_M_AXI_S2MM_AWVALID),
.S00_AXI_bready(axi_dma_0_M_AXI_S2MM_BREADY),
.S00_AXI_bresp(axi_dma_0_M_AXI_S2MM_BRESP),
.S00_AXI_bvalid(axi_dma_0_M_AXI_S2MM_BVALID),
.S00_AXI_wdata(axi_dma_0_M_AXI_S2MM_WDATA),
.S00_AXI_wlast(axi_dma_0_M_AXI_S2MM_WLAST),
.S00_AXI_wready(axi_dma_0_M_AXI_S2MM_WREADY),
.S00_AXI_wstrb(axi_dma_0_M_AXI_S2MM_WSTRB),
.S00_AXI_wvalid(axi_dma_0_M_AXI_S2MM_WVALID));
design_1_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.IRQ_F2P(axi_dma_0_s2mm_introut),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.S_AXI_HP0_ACLK(processing_system7_0_FCLK_CLK0),
.S_AXI_HP0_ARADDR({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.S_AXI_HP0_ARBURST({GND_1,GND_1}),
.S_AXI_HP0_ARCACHE({GND_1,GND_1,GND_1,GND_1}),
.S_AXI_HP0_ARID({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.S_AXI_HP0_ARLEN({GND_1,GND_1,GND_1,GND_1}),
.S_AXI_HP0_ARLOCK({GND_1,GND_1}),
.S_AXI_HP0_ARPROT({GND_1,GND_1,GND_1}),
.S_AXI_HP0_ARQOS({GND_1,GND_1,GND_1,GND_1}),
.S_AXI_HP0_ARSIZE({GND_1,GND_1,GND_1}),
.S_AXI_HP0_ARVALID(GND_1),
.S_AXI_HP0_AWADDR(axi_mem_intercon_M00_AXI_AWADDR),
.S_AXI_HP0_AWBURST(axi_mem_intercon_M00_AXI_AWBURST),
.S_AXI_HP0_AWCACHE(axi_mem_intercon_M00_AXI_AWCACHE),
.S_AXI_HP0_AWID({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.S_AXI_HP0_AWLEN(axi_mem_intercon_M00_AXI_AWLEN),
.S_AXI_HP0_AWLOCK(axi_mem_intercon_M00_AXI_AWLOCK),
.S_AXI_HP0_AWPROT(axi_mem_intercon_M00_AXI_AWPROT),
.S_AXI_HP0_AWQOS(axi_mem_intercon_M00_AXI_AWQOS),
.S_AXI_HP0_AWREADY(axi_mem_intercon_M00_AXI_AWREADY),
.S_AXI_HP0_AWSIZE(axi_mem_intercon_M00_AXI_AWSIZE),
.S_AXI_HP0_AWVALID(axi_mem_intercon_M00_AXI_AWVALID),
.S_AXI_HP0_BREADY(axi_mem_intercon_M00_AXI_BREADY),
.S_AXI_HP0_BRESP(axi_mem_intercon_M00_AXI_BRESP),
.S_AXI_HP0_BVALID(axi_mem_intercon_M00_AXI_BVALID),
.S_AXI_HP0_RDISSUECAP1_EN(GND_1),
.S_AXI_HP0_RREADY(GND_1),
.S_AXI_HP0_WDATA(axi_mem_intercon_M00_AXI_WDATA),
.S_AXI_HP0_WID({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.S_AXI_HP0_WLAST(axi_mem_intercon_M00_AXI_WLAST),
.S_AXI_HP0_WREADY(axi_mem_intercon_M00_AXI_WREADY),
.S_AXI_HP0_WRISSUECAP1_EN(GND_1),
.S_AXI_HP0_WSTRB(axi_mem_intercon_M00_AXI_WSTRB),
.S_AXI_HP0_WVALID(axi_mem_intercon_M00_AXI_WVALID),
.USB0_VBUS_PWRFAULT(GND_1));
design_1_processing_system7_0_axi_periph_0 processing_system7_0_axi_periph
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.M00_AXI_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.M00_AXI_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.M00_AXI_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.M00_AXI_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.M00_AXI_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.M00_AXI_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.M00_AXI_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.M00_AXI_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.M00_AXI_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.M00_AXI_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.M00_AXI_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.M00_AXI_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.M00_AXI_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.M00_AXI_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.M00_AXI_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID),
.M01_ACLK(processing_system7_0_FCLK_CLK0),
.M01_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M01_AXI_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.M01_AXI_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.M01_AXI_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.M01_AXI_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.M01_AXI_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.M01_AXI_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.M01_AXI_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.M01_AXI_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.M01_AXI_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.M01_AXI_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.M01_AXI_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.M01_AXI_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.M01_AXI_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.M01_AXI_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.M01_AXI_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.M01_AXI_wstrb(processing_system7_0_axi_periph_M01_AXI_WSTRB),
.M01_AXI_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID),
.M02_ACLK(processing_system7_0_FCLK_CLK0),
.M02_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M02_AXI_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.M02_AXI_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.M02_AXI_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.M02_AXI_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.M02_AXI_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.M02_AXI_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.M02_AXI_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.M02_AXI_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.M02_AXI_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.M02_AXI_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.M02_AXI_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.M02_AXI_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.M02_AXI_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.M02_AXI_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.M02_AXI_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.M02_AXI_wstrb(processing_system7_0_axi_periph_M02_AXI_WSTRB),
.M02_AXI_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
design_1_rst_processing_system7_0_100M_0 rst_processing_system7_0_100M
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.interconnect_aresetn(rst_processing_system7_0_100M_interconnect_aresetn),
.mb_debug_sys_rst(GND_1),
.peripheral_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
design_1_sample_generator_0_0 sample_generator_0
(.AXI_En(xlconstant_1_dout),
.En(axi_gpio_1_gpio_io_o),
.FrameSize(axi_gpio_0_gpio_io_o),
.m_axis_aclk(processing_system7_0_FCLK_CLK0),
.m_axis_aresetn(rst_processing_system7_0_100M_interconnect_aresetn),
.m_axis_tdata(sample_generator_0_M_AXIS_TDATA),
.m_axis_tlast(sample_generator_0_M_AXIS_TLAST),
.m_axis_tready(sample_generator_0_M_AXIS_TREADY),
.m_axis_tvalid(sample_generator_0_M_AXIS_TVALID),
.s_axis_aclk(processing_system7_0_FCLK_CLK0),
.s_axis_aresetn(rst_processing_system7_0_100M_interconnect_aresetn),
.s_axis_tdata({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.s_axis_tlast(GND_1),
.s_axis_tstrb({GND_1,GND_1,GND_1,GND_1}),
.s_axis_tvalid(GND_1));
design_1_xlconstant_0_0 xlconstant_0
(.dout(xlconstant_0_dout));
design_1_xlconstant_1_0 xlconstant_1
(.dout(xlconstant_1_dout));
endmodule
module design_1_axi_mem_intercon_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_wdata,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awlen,
S00_AXI_awprot,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_wdata,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [31:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [3:0]M00_AXI_awlen;
output [1:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
output [3:0]M00_AXI_awqos;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
output [63:0]M00_AXI_wdata;
output M00_AXI_wlast;
input M00_AXI_wready;
output [7:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [7:0]S00_AXI_awlen;
input [2:0]S00_AXI_awprot;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
input [31:0]S00_AXI_wdata;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire axi_mem_intercon_ACLK_net;
wire [0:0]axi_mem_intercon_ARESETN_net;
wire [31:0]axi_mem_intercon_to_s00_couplers_AWADDR;
wire [1:0]axi_mem_intercon_to_s00_couplers_AWBURST;
wire [3:0]axi_mem_intercon_to_s00_couplers_AWCACHE;
wire [7:0]axi_mem_intercon_to_s00_couplers_AWLEN;
wire [2:0]axi_mem_intercon_to_s00_couplers_AWPROT;
wire axi_mem_intercon_to_s00_couplers_AWREADY;
wire [2:0]axi_mem_intercon_to_s00_couplers_AWSIZE;
wire axi_mem_intercon_to_s00_couplers_AWVALID;
wire axi_mem_intercon_to_s00_couplers_BREADY;
wire [1:0]axi_mem_intercon_to_s00_couplers_BRESP;
wire axi_mem_intercon_to_s00_couplers_BVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_WDATA;
wire axi_mem_intercon_to_s00_couplers_WLAST;
wire axi_mem_intercon_to_s00_couplers_WREADY;
wire [3:0]axi_mem_intercon_to_s00_couplers_WSTRB;
wire axi_mem_intercon_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_axi_mem_intercon_AWADDR;
wire [1:0]s00_couplers_to_axi_mem_intercon_AWBURST;
wire [3:0]s00_couplers_to_axi_mem_intercon_AWCACHE;
wire [3:0]s00_couplers_to_axi_mem_intercon_AWLEN;
wire [1:0]s00_couplers_to_axi_mem_intercon_AWLOCK;
wire [2:0]s00_couplers_to_axi_mem_intercon_AWPROT;
wire [3:0]s00_couplers_to_axi_mem_intercon_AWQOS;
wire s00_couplers_to_axi_mem_intercon_AWREADY;
wire [2:0]s00_couplers_to_axi_mem_intercon_AWSIZE;
wire s00_couplers_to_axi_mem_intercon_AWVALID;
wire s00_couplers_to_axi_mem_intercon_BREADY;
wire [1:0]s00_couplers_to_axi_mem_intercon_BRESP;
wire s00_couplers_to_axi_mem_intercon_BVALID;
wire [63:0]s00_couplers_to_axi_mem_intercon_WDATA;
wire s00_couplers_to_axi_mem_intercon_WLAST;
wire s00_couplers_to_axi_mem_intercon_WREADY;
wire [7:0]s00_couplers_to_axi_mem_intercon_WSTRB;
wire s00_couplers_to_axi_mem_intercon_WVALID;
assign M00_AXI_awaddr[31:0] = s00_couplers_to_axi_mem_intercon_AWADDR;
assign M00_AXI_awburst[1:0] = s00_couplers_to_axi_mem_intercon_AWBURST;
assign M00_AXI_awcache[3:0] = s00_couplers_to_axi_mem_intercon_AWCACHE;
assign M00_AXI_awlen[3:0] = s00_couplers_to_axi_mem_intercon_AWLEN;
assign M00_AXI_awlock[1:0] = s00_couplers_to_axi_mem_intercon_AWLOCK;
assign M00_AXI_awprot[2:0] = s00_couplers_to_axi_mem_intercon_AWPROT;
assign M00_AXI_awqos[3:0] = s00_couplers_to_axi_mem_intercon_AWQOS;
assign M00_AXI_awsize[2:0] = s00_couplers_to_axi_mem_intercon_AWSIZE;
assign M00_AXI_awvalid = s00_couplers_to_axi_mem_intercon_AWVALID;
assign M00_AXI_bready = s00_couplers_to_axi_mem_intercon_BREADY;
assign M00_AXI_wdata[63:0] = s00_couplers_to_axi_mem_intercon_WDATA;
assign M00_AXI_wlast = s00_couplers_to_axi_mem_intercon_WLAST;
assign M00_AXI_wstrb[7:0] = s00_couplers_to_axi_mem_intercon_WSTRB;
assign M00_AXI_wvalid = s00_couplers_to_axi_mem_intercon_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_awready = axi_mem_intercon_to_s00_couplers_AWREADY;
assign S00_AXI_bresp[1:0] = axi_mem_intercon_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_mem_intercon_to_s00_couplers_BVALID;
assign S00_AXI_wready = axi_mem_intercon_to_s00_couplers_WREADY;
assign axi_mem_intercon_ACLK_net = M00_ACLK;
assign axi_mem_intercon_ARESETN_net = M00_ARESETN[0];
assign axi_mem_intercon_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_mem_intercon_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_mem_intercon_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_mem_intercon_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];
assign axi_mem_intercon_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_mem_intercon_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_mem_intercon_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_mem_intercon_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_mem_intercon_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_mem_intercon_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_mem_intercon_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_mem_intercon_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign s00_couplers_to_axi_mem_intercon_AWREADY = M00_AXI_awready;
assign s00_couplers_to_axi_mem_intercon_BRESP = M00_AXI_bresp[1:0];
assign s00_couplers_to_axi_mem_intercon_BVALID = M00_AXI_bvalid;
assign s00_couplers_to_axi_mem_intercon_WREADY = M00_AXI_wready;
s00_couplers_imp_7HNO1D s00_couplers
(.M_ACLK(axi_mem_intercon_ACLK_net),
.M_ARESETN(axi_mem_intercon_ARESETN_net),
.M_AXI_awaddr(s00_couplers_to_axi_mem_intercon_AWADDR),
.M_AXI_awburst(s00_couplers_to_axi_mem_intercon_AWBURST),
.M_AXI_awcache(s00_couplers_to_axi_mem_intercon_AWCACHE),
.M_AXI_awlen(s00_couplers_to_axi_mem_intercon_AWLEN),
.M_AXI_awlock(s00_couplers_to_axi_mem_intercon_AWLOCK),
.M_AXI_awprot(s00_couplers_to_axi_mem_intercon_AWPROT),
.M_AXI_awqos(s00_couplers_to_axi_mem_intercon_AWQOS),
.M_AXI_awready(s00_couplers_to_axi_mem_intercon_AWREADY),
.M_AXI_awsize(s00_couplers_to_axi_mem_intercon_AWSIZE),
.M_AXI_awvalid(s00_couplers_to_axi_mem_intercon_AWVALID),
.M_AXI_bready(s00_couplers_to_axi_mem_intercon_BREADY),
.M_AXI_bresp(s00_couplers_to_axi_mem_intercon_BRESP),
.M_AXI_bvalid(s00_couplers_to_axi_mem_intercon_BVALID),
.M_AXI_wdata(s00_couplers_to_axi_mem_intercon_WDATA),
.M_AXI_wlast(s00_couplers_to_axi_mem_intercon_WLAST),
.M_AXI_wready(s00_couplers_to_axi_mem_intercon_WREADY),
.M_AXI_wstrb(s00_couplers_to_axi_mem_intercon_WSTRB),
.M_AXI_wvalid(s00_couplers_to_axi_mem_intercon_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_awaddr(axi_mem_intercon_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_mem_intercon_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_mem_intercon_to_s00_couplers_AWCACHE),
.S_AXI_awlen(axi_mem_intercon_to_s00_couplers_AWLEN),
.S_AXI_awprot(axi_mem_intercon_to_s00_couplers_AWPROT),
.S_AXI_awready(axi_mem_intercon_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_mem_intercon_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_mem_intercon_to_s00_couplers_AWVALID),
.S_AXI_bready(axi_mem_intercon_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_mem_intercon_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_mem_intercon_to_s00_couplers_BVALID),
.S_AXI_wdata(axi_mem_intercon_to_s00_couplers_WDATA),
.S_AXI_wlast(axi_mem_intercon_to_s00_couplers_WLAST),
.S_AXI_wready(axi_mem_intercon_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_mem_intercon_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_mem_intercon_to_s00_couplers_WVALID));
endmodule
module design_1_processing_system7_0_axi_periph_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arready,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awready,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wready,
M01_AXI_wstrb,
M01_AXI_wvalid,
M02_ACLK,
M02_ARESETN,
M02_AXI_araddr,
M02_AXI_arready,
M02_AXI_arvalid,
M02_AXI_awaddr,
M02_AXI_awready,
M02_AXI_awvalid,
M02_AXI_bready,
M02_AXI_bresp,
M02_AXI_bvalid,
M02_AXI_rdata,
M02_AXI_rready,
M02_AXI_rresp,
M02_AXI_rvalid,
M02_AXI_wdata,
M02_AXI_wready,
M02_AXI_wstrb,
M02_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [9:0]M00_AXI_araddr;
input [0:0]M00_AXI_arready;
output [0:0]M00_AXI_arvalid;
output [9:0]M00_AXI_awaddr;
input [0:0]M00_AXI_awready;
output [0:0]M00_AXI_awvalid;
output [0:0]M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input [0:0]M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output [0:0]M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input [0:0]M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input [0:0]M00_AXI_wready;
output [0:0]M00_AXI_wvalid;
input M01_ACLK;
input [0:0]M01_ARESETN;
output [8:0]M01_AXI_araddr;
input [0:0]M01_AXI_arready;
output [0:0]M01_AXI_arvalid;
output [8:0]M01_AXI_awaddr;
input [0:0]M01_AXI_awready;
output [0:0]M01_AXI_awvalid;
output [0:0]M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input [0:0]M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
output [0:0]M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input [0:0]M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
input [0:0]M01_AXI_wready;
output [3:0]M01_AXI_wstrb;
output [0:0]M01_AXI_wvalid;
input M02_ACLK;
input [0:0]M02_ARESETN;
output [8:0]M02_AXI_araddr;
input [0:0]M02_AXI_arready;
output [0:0]M02_AXI_arvalid;
output [8:0]M02_AXI_awaddr;
input [0:0]M02_AXI_awready;
output [0:0]M02_AXI_awvalid;
output [0:0]M02_AXI_bready;
input [1:0]M02_AXI_bresp;
input [0:0]M02_AXI_bvalid;
input [31:0]M02_AXI_rdata;
output [0:0]M02_AXI_rready;
input [1:0]M02_AXI_rresp;
input [0:0]M02_AXI_rvalid;
output [31:0]M02_AXI_wdata;
input [0:0]M02_AXI_wready;
output [3:0]M02_AXI_wstrb;
output [0:0]M02_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire M00_ACLK_1;
wire [0:0]M00_ARESETN_1;
wire M01_ACLK_1;
wire [0:0]M01_ARESETN_1;
wire M02_ACLK_1;
wire [0:0]M02_ARESETN_1;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire [9:0]m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [9:0]m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_BRESP;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_RDATA;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_RRESP;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_WDATA;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [8:0]m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [8:0]m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_BRESP;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_RDATA;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_RRESP;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_WDATA;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m01_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [8:0]m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [8:0]m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_BRESP;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_RDATA;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_RRESP;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_WDATA;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m02_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_WVALID;
wire processing_system7_0_axi_periph_ACLK_net;
wire [0:0]processing_system7_0_axi_periph_ARESETN_net;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_ARADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_ARID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_ARVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_AWADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_AWID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_AWVALID;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_BID;
wire processing_system7_0_axi_periph_to_s00_couplers_BREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_BRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_BVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_RDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_RID;
wire processing_system7_0_axi_periph_to_s00_couplers_RLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_RREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_RRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_RVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_WDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_WID;
wire processing_system7_0_axi_periph_to_s00_couplers_WLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_WREADY;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_WSTRB;
wire processing_system7_0_axi_periph_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [31:0]s00_couplers_to_xbar_RDATA;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s00_couplers_to_xbar_WDATA;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [3:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [0:0]xbar_to_m00_couplers_ARREADY;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [0:0]xbar_to_m00_couplers_AWREADY;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire [0:0]xbar_to_m00_couplers_BVALID;
wire [31:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire [0:0]xbar_to_m00_couplers_RVALID;
wire [31:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WREADY;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire [0:0]xbar_to_m01_couplers_ARREADY;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire [0:0]xbar_to_m01_couplers_AWREADY;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire [0:0]xbar_to_m01_couplers_BVALID;
wire [31:0]xbar_to_m01_couplers_RDATA;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire [0:0]xbar_to_m01_couplers_RVALID;
wire [63:32]xbar_to_m01_couplers_WDATA;
wire [0:0]xbar_to_m01_couplers_WREADY;
wire [7:4]xbar_to_m01_couplers_WSTRB;
wire [1:1]xbar_to_m01_couplers_WVALID;
wire [95:64]xbar_to_m02_couplers_ARADDR;
wire [0:0]xbar_to_m02_couplers_ARREADY;
wire [2:2]xbar_to_m02_couplers_ARVALID;
wire [95:64]xbar_to_m02_couplers_AWADDR;
wire [0:0]xbar_to_m02_couplers_AWREADY;
wire [2:2]xbar_to_m02_couplers_AWVALID;
wire [2:2]xbar_to_m02_couplers_BREADY;
wire [1:0]xbar_to_m02_couplers_BRESP;
wire [0:0]xbar_to_m02_couplers_BVALID;
wire [31:0]xbar_to_m02_couplers_RDATA;
wire [2:2]xbar_to_m02_couplers_RREADY;
wire [1:0]xbar_to_m02_couplers_RRESP;
wire [0:0]xbar_to_m02_couplers_RVALID;
wire [95:64]xbar_to_m02_couplers_WDATA;
wire [0:0]xbar_to_m02_couplers_WREADY;
wire [11:8]xbar_to_m02_couplers_WSTRB;
wire [2:2]xbar_to_m02_couplers_WVALID;
wire [11:0]NLW_xbar_m_axi_wstrb_UNCONNECTED;
assign M00_ACLK_1 = M00_ACLK;
assign M00_ARESETN_1 = M00_ARESETN[0];
assign M00_AXI_araddr[9:0] = m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M00_AXI_arvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M00_AXI_awaddr[9:0] = m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M00_AXI_awvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M00_AXI_bready[0] = m00_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M00_AXI_rready[0] = m00_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M00_AXI_wdata[31:0] = m00_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M00_AXI_wvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M01_ACLK_1 = M01_ACLK;
assign M01_ARESETN_1 = M01_ARESETN[0];
assign M01_AXI_araddr[8:0] = m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M01_AXI_arvalid[0] = m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M01_AXI_awaddr[8:0] = m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M01_AXI_awvalid[0] = m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M01_AXI_bready[0] = m01_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M01_AXI_rready[0] = m01_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M01_AXI_wstrb[3:0] = m01_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M01_AXI_wvalid[0] = m01_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M02_ACLK_1 = M02_ACLK;
assign M02_ARESETN_1 = M02_ARESETN[0];
assign M02_AXI_araddr[8:0] = m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M02_AXI_arvalid[0] = m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M02_AXI_awaddr[8:0] = m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M02_AXI_awvalid[0] = m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M02_AXI_bready[0] = m02_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M02_AXI_rready[0] = m02_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M02_AXI_wdata[31:0] = m02_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M02_AXI_wstrb[3:0] = m02_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M02_AXI_wvalid[0] = m02_couplers_to_processing_system7_0_axi_periph_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
assign S00_AXI_awready = processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = processing_system7_0_axi_periph_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = processing_system7_0_axi_periph_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_RID;
assign S00_AXI_rlast = processing_system7_0_axi_periph_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = processing_system7_0_axi_periph_to_s00_couplers_RVALID;
assign S00_AXI_wready = processing_system7_0_axi_periph_to_s00_couplers_WREADY;
assign m00_couplers_to_processing_system7_0_axi_periph_ARREADY = M00_AXI_arready[0];
assign m00_couplers_to_processing_system7_0_axi_periph_AWREADY = M00_AXI_awready[0];
assign m00_couplers_to_processing_system7_0_axi_periph_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_BVALID = M00_AXI_bvalid[0];
assign m00_couplers_to_processing_system7_0_axi_periph_RDATA = M00_AXI_rdata[31:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RVALID = M00_AXI_rvalid[0];
assign m00_couplers_to_processing_system7_0_axi_periph_WREADY = M00_AXI_wready[0];
assign m01_couplers_to_processing_system7_0_axi_periph_ARREADY = M01_AXI_arready[0];
assign m01_couplers_to_processing_system7_0_axi_periph_AWREADY = M01_AXI_awready[0];
assign m01_couplers_to_processing_system7_0_axi_periph_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_BVALID = M01_AXI_bvalid[0];
assign m01_couplers_to_processing_system7_0_axi_periph_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RVALID = M01_AXI_rvalid[0];
assign m01_couplers_to_processing_system7_0_axi_periph_WREADY = M01_AXI_wready[0];
assign m02_couplers_to_processing_system7_0_axi_periph_ARREADY = M02_AXI_arready[0];
assign m02_couplers_to_processing_system7_0_axi_periph_AWREADY = M02_AXI_awready[0];
assign m02_couplers_to_processing_system7_0_axi_periph_BRESP = M02_AXI_bresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_BVALID = M02_AXI_bvalid[0];
assign m02_couplers_to_processing_system7_0_axi_periph_RDATA = M02_AXI_rdata[31:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RRESP = M02_AXI_rresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RVALID = M02_AXI_rvalid[0];
assign m02_couplers_to_processing_system7_0_axi_periph_WREADY = M02_AXI_wready[0];
assign processing_system7_0_axi_periph_ACLK_net = ACLK;
assign processing_system7_0_axi_periph_ARESETN_net = ARESETN[0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
assign processing_system7_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
assign processing_system7_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast;
assign processing_system7_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
m00_couplers_imp_OBU1DD m00_couplers
(.M_ACLK(M00_ACLK_1),
.M_ARESETN(M00_ARESETN_1),
.M_AXI_araddr(m00_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m00_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m00_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m00_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m00_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m00_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m00_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m00_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m00_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m00_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m00_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m00_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m00_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m00_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m00_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wvalid(m00_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR[9:0]),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR[9:0]),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_1FBREZ4 m01_couplers
(.M_ACLK(M01_ACLK_1),
.M_ARESETN(M01_ARESETN_1),
.M_AXI_araddr(m01_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m01_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m01_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m01_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m01_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m01_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m01_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m01_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m01_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m01_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m01_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m01_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m01_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m01_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m01_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m01_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m01_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR[40:32]),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR[40:32]),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
m02_couplers_imp_MVV5YQ m02_couplers
(.M_ACLK(M02_ACLK_1),
.M_ARESETN(M02_ARESETN_1),
.M_AXI_araddr(m02_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m02_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m02_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m02_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m02_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m02_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m02_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m02_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m02_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m02_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m02_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m02_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m02_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m02_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m02_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m02_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m02_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m02_couplers_ARADDR[72:64]),
.S_AXI_arready(xbar_to_m02_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m02_couplers_AWADDR[72:64]),
.S_AXI_awready(xbar_to_m02_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),
.S_AXI_bready(xbar_to_m02_couplers_BREADY),
.S_AXI_bresp(xbar_to_m02_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m02_couplers_BVALID),
.S_AXI_rdata(xbar_to_m02_couplers_RDATA),
.S_AXI_rready(xbar_to_m02_couplers_RREADY),
.S_AXI_rresp(xbar_to_m02_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m02_couplers_RVALID),
.S_AXI_wdata(xbar_to_m02_couplers_WDATA),
.S_AXI_wready(xbar_to_m02_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m02_couplers_WVALID));
s00_couplers_imp_1CFO1MB s00_couplers
(.M_ACLK(processing_system7_0_axi_periph_ACLK_net),
.M_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(processing_system7_0_axi_periph_to_s00_couplers_ARADDR),
.S_AXI_arburst(processing_system7_0_axi_periph_to_s00_couplers_ARBURST),
.S_AXI_arcache(processing_system7_0_axi_periph_to_s00_couplers_ARCACHE),
.S_AXI_arid(processing_system7_0_axi_periph_to_s00_couplers_ARID),
.S_AXI_arlen(processing_system7_0_axi_periph_to_s00_couplers_ARLEN),
.S_AXI_arlock(processing_system7_0_axi_periph_to_s00_couplers_ARLOCK),
.S_AXI_arprot(processing_system7_0_axi_periph_to_s00_couplers_ARPROT),
.S_AXI_arqos(processing_system7_0_axi_periph_to_s00_couplers_ARQOS),
.S_AXI_arready(processing_system7_0_axi_periph_to_s00_couplers_ARREADY),
.S_AXI_arsize(processing_system7_0_axi_periph_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(processing_system7_0_axi_periph_to_s00_couplers_ARVALID),
.S_AXI_awaddr(processing_system7_0_axi_periph_to_s00_couplers_AWADDR),
.S_AXI_awburst(processing_system7_0_axi_periph_to_s00_couplers_AWBURST),
.S_AXI_awcache(processing_system7_0_axi_periph_to_s00_couplers_AWCACHE),
.S_AXI_awid(processing_system7_0_axi_periph_to_s00_couplers_AWID),
.S_AXI_awlen(processing_system7_0_axi_periph_to_s00_couplers_AWLEN),
.S_AXI_awlock(processing_system7_0_axi_periph_to_s00_couplers_AWLOCK),
.S_AXI_awprot(processing_system7_0_axi_periph_to_s00_couplers_AWPROT),
.S_AXI_awqos(processing_system7_0_axi_periph_to_s00_couplers_AWQOS),
.S_AXI_awready(processing_system7_0_axi_periph_to_s00_couplers_AWREADY),
.S_AXI_awsize(processing_system7_0_axi_periph_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(processing_system7_0_axi_periph_to_s00_couplers_AWVALID),
.S_AXI_bid(processing_system7_0_axi_periph_to_s00_couplers_BID),
.S_AXI_bready(processing_system7_0_axi_periph_to_s00_couplers_BREADY),
.S_AXI_bresp(processing_system7_0_axi_periph_to_s00_couplers_BRESP),
.S_AXI_bvalid(processing_system7_0_axi_periph_to_s00_couplers_BVALID),
.S_AXI_rdata(processing_system7_0_axi_periph_to_s00_couplers_RDATA),
.S_AXI_rid(processing_system7_0_axi_periph_to_s00_couplers_RID),
.S_AXI_rlast(processing_system7_0_axi_periph_to_s00_couplers_RLAST),
.S_AXI_rready(processing_system7_0_axi_periph_to_s00_couplers_RREADY),
.S_AXI_rresp(processing_system7_0_axi_periph_to_s00_couplers_RRESP),
.S_AXI_rvalid(processing_system7_0_axi_periph_to_s00_couplers_RVALID),
.S_AXI_wdata(processing_system7_0_axi_periph_to_s00_couplers_WDATA),
.S_AXI_wid(processing_system7_0_axi_periph_to_s00_couplers_WID),
.S_AXI_wlast(processing_system7_0_axi_periph_to_s00_couplers_WLAST),
.S_AXI_wready(processing_system7_0_axi_periph_to_s00_couplers_WREADY),
.S_AXI_wstrb(processing_system7_0_axi_periph_to_s00_couplers_WSTRB),
.S_AXI_wvalid(processing_system7_0_axi_periph_to_s00_couplers_WVALID));
design_1_xbar_0 xbar
(.aclk(processing_system7_0_axi_periph_ACLK_net),
.aresetn(processing_system7_0_axi_periph_ARESETN_net),
.m_axi_araddr({xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arready({xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arvalid({xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awready({xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awvalid({xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rready({xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wready({xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,NLW_xbar_m_axi_wstrb_UNCONNECTED[3:0]}),
.m_axi_wvalid({xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr(s00_couplers_to_xbar_ARADDR),
.s_axi_arprot(s00_couplers_to_xbar_ARPROT),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
.s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
.s_axi_awprot(s00_couplers_to_xbar_AWPROT),
.s_axi_awready(s00_couplers_to_xbar_AWREADY),
.s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
.s_axi_bready(s00_couplers_to_xbar_BREADY),
.s_axi_bresp(s00_couplers_to_xbar_BRESP),
.s_axi_bvalid(s00_couplers_to_xbar_BVALID),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rready(s00_couplers_to_xbar_RREADY),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata(s00_couplers_to_xbar_WDATA),
.s_axi_wready(s00_couplers_to_xbar_WREADY),
.s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
.s_axi_wvalid(s00_couplers_to_xbar_WVALID));
endmodule
module m00_couplers_imp_OBU1DD
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [9:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [9:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [9:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [9:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [0:0]S_AXI_wvalid;
wire [9:0]m00_couplers_to_m00_couplers_ARADDR;
wire [0:0]m00_couplers_to_m00_couplers_ARREADY;
wire [0:0]m00_couplers_to_m00_couplers_ARVALID;
wire [9:0]m00_couplers_to_m00_couplers_AWADDR;
wire [0:0]m00_couplers_to_m00_couplers_AWREADY;
wire [0:0]m00_couplers_to_m00_couplers_AWVALID;
wire [0:0]m00_couplers_to_m00_couplers_BREADY;
wire [1:0]m00_couplers_to_m00_couplers_BRESP;
wire [0:0]m00_couplers_to_m00_couplers_BVALID;
wire [31:0]m00_couplers_to_m00_couplers_RDATA;
wire [0:0]m00_couplers_to_m00_couplers_RREADY;
wire [1:0]m00_couplers_to_m00_couplers_RRESP;
wire [0:0]m00_couplers_to_m00_couplers_RVALID;
wire [31:0]m00_couplers_to_m00_couplers_WDATA;
wire [0:0]m00_couplers_to_m00_couplers_WREADY;
wire [0:0]m00_couplers_to_m00_couplers_WVALID;
assign M_AXI_araddr[9:0] = m00_couplers_to_m00_couplers_ARADDR;
assign M_AXI_arvalid[0] = m00_couplers_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[9:0] = m00_couplers_to_m00_couplers_AWADDR;
assign M_AXI_awvalid[0] = m00_couplers_to_m00_couplers_AWVALID;
assign M_AXI_bready[0] = m00_couplers_to_m00_couplers_BREADY;
assign M_AXI_rready[0] = m00_couplers_to_m00_couplers_RREADY;
assign M_AXI_wdata[31:0] = m00_couplers_to_m00_couplers_WDATA;
assign M_AXI_wvalid[0] = m00_couplers_to_m00_couplers_WVALID;
assign S_AXI_arready[0] = m00_couplers_to_m00_couplers_ARREADY;
assign S_AXI_awready[0] = m00_couplers_to_m00_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m00_couplers_to_m00_couplers_BRESP;
assign S_AXI_bvalid[0] = m00_couplers_to_m00_couplers_BVALID;
assign S_AXI_rdata[31:0] = m00_couplers_to_m00_couplers_RDATA;
assign S_AXI_rresp[1:0] = m00_couplers_to_m00_couplers_RRESP;
assign S_AXI_rvalid[0] = m00_couplers_to_m00_couplers_RVALID;
assign S_AXI_wready[0] = m00_couplers_to_m00_couplers_WREADY;
assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr[9:0];
assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready[0];
assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid[0];
assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr[9:0];
assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready[0];
assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid[0];
assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready[0];
assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid[0];
assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata[31:0];
assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready[0];
assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid[0];
assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata[31:0];
assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready[0];
assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module m01_couplers_imp_1FBREZ4
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [8:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [8:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [3:0]M_AXI_wstrb;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [8:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [8:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [3:0]S_AXI_wstrb;
input [0:0]S_AXI_wvalid;
wire [8:0]m01_couplers_to_m01_couplers_ARADDR;
wire [0:0]m01_couplers_to_m01_couplers_ARREADY;
wire [0:0]m01_couplers_to_m01_couplers_ARVALID;
wire [8:0]m01_couplers_to_m01_couplers_AWADDR;
wire [0:0]m01_couplers_to_m01_couplers_AWREADY;
wire [0:0]m01_couplers_to_m01_couplers_AWVALID;
wire [0:0]m01_couplers_to_m01_couplers_BREADY;
wire [1:0]m01_couplers_to_m01_couplers_BRESP;
wire [0:0]m01_couplers_to_m01_couplers_BVALID;
wire [31:0]m01_couplers_to_m01_couplers_RDATA;
wire [0:0]m01_couplers_to_m01_couplers_RREADY;
wire [1:0]m01_couplers_to_m01_couplers_RRESP;
wire [0:0]m01_couplers_to_m01_couplers_RVALID;
wire [31:0]m01_couplers_to_m01_couplers_WDATA;
wire [0:0]m01_couplers_to_m01_couplers_WREADY;
wire [3:0]m01_couplers_to_m01_couplers_WSTRB;
wire [0:0]m01_couplers_to_m01_couplers_WVALID;
assign M_AXI_araddr[8:0] = m01_couplers_to_m01_couplers_ARADDR;
assign M_AXI_arvalid[0] = m01_couplers_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[8:0] = m01_couplers_to_m01_couplers_AWADDR;
assign M_AXI_awvalid[0] = m01_couplers_to_m01_couplers_AWVALID;
assign M_AXI_bready[0] = m01_couplers_to_m01_couplers_BREADY;
assign M_AXI_rready[0] = m01_couplers_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = m01_couplers_to_m01_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m01_couplers_to_m01_couplers_WSTRB;
assign M_AXI_wvalid[0] = m01_couplers_to_m01_couplers_WVALID;
assign S_AXI_arready[0] = m01_couplers_to_m01_couplers_ARREADY;
assign S_AXI_awready[0] = m01_couplers_to_m01_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_m01_couplers_BRESP;
assign S_AXI_bvalid[0] = m01_couplers_to_m01_couplers_BVALID;
assign S_AXI_rdata[31:0] = m01_couplers_to_m01_couplers_RDATA;
assign S_AXI_rresp[1:0] = m01_couplers_to_m01_couplers_RRESP;
assign S_AXI_rvalid[0] = m01_couplers_to_m01_couplers_RVALID;
assign S_AXI_wready[0] = m01_couplers_to_m01_couplers_WREADY;
assign m01_couplers_to_m01_couplers_ARADDR = S_AXI_araddr[8:0];
assign m01_couplers_to_m01_couplers_ARREADY = M_AXI_arready[0];
assign m01_couplers_to_m01_couplers_ARVALID = S_AXI_arvalid[0];
assign m01_couplers_to_m01_couplers_AWADDR = S_AXI_awaddr[8:0];
assign m01_couplers_to_m01_couplers_AWREADY = M_AXI_awready[0];
assign m01_couplers_to_m01_couplers_AWVALID = S_AXI_awvalid[0];
assign m01_couplers_to_m01_couplers_BREADY = S_AXI_bready[0];
assign m01_couplers_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign m01_couplers_to_m01_couplers_BVALID = M_AXI_bvalid[0];
assign m01_couplers_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign m01_couplers_to_m01_couplers_RREADY = S_AXI_rready[0];
assign m01_couplers_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign m01_couplers_to_m01_couplers_RVALID = M_AXI_rvalid[0];
assign m01_couplers_to_m01_couplers_WDATA = S_AXI_wdata[31:0];
assign m01_couplers_to_m01_couplers_WREADY = M_AXI_wready[0];
assign m01_couplers_to_m01_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module m02_couplers_imp_MVV5YQ
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [8:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [8:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [3:0]M_AXI_wstrb;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [8:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [8:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [3:0]S_AXI_wstrb;
input [0:0]S_AXI_wvalid;
wire [8:0]m02_couplers_to_m02_couplers_ARADDR;
wire [0:0]m02_couplers_to_m02_couplers_ARREADY;
wire [0:0]m02_couplers_to_m02_couplers_ARVALID;
wire [8:0]m02_couplers_to_m02_couplers_AWADDR;
wire [0:0]m02_couplers_to_m02_couplers_AWREADY;
wire [0:0]m02_couplers_to_m02_couplers_AWVALID;
wire [0:0]m02_couplers_to_m02_couplers_BREADY;
wire [1:0]m02_couplers_to_m02_couplers_BRESP;
wire [0:0]m02_couplers_to_m02_couplers_BVALID;
wire [31:0]m02_couplers_to_m02_couplers_RDATA;
wire [0:0]m02_couplers_to_m02_couplers_RREADY;
wire [1:0]m02_couplers_to_m02_couplers_RRESP;
wire [0:0]m02_couplers_to_m02_couplers_RVALID;
wire [31:0]m02_couplers_to_m02_couplers_WDATA;
wire [0:0]m02_couplers_to_m02_couplers_WREADY;
wire [3:0]m02_couplers_to_m02_couplers_WSTRB;
wire [0:0]m02_couplers_to_m02_couplers_WVALID;
assign M_AXI_araddr[8:0] = m02_couplers_to_m02_couplers_ARADDR;
assign M_AXI_arvalid[0] = m02_couplers_to_m02_couplers_ARVALID;
assign M_AXI_awaddr[8:0] = m02_couplers_to_m02_couplers_AWADDR;
assign M_AXI_awvalid[0] = m02_couplers_to_m02_couplers_AWVALID;
assign M_AXI_bready[0] = m02_couplers_to_m02_couplers_BREADY;
assign M_AXI_rready[0] = m02_couplers_to_m02_couplers_RREADY;
assign M_AXI_wdata[31:0] = m02_couplers_to_m02_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m02_couplers_to_m02_couplers_WSTRB;
assign M_AXI_wvalid[0] = m02_couplers_to_m02_couplers_WVALID;
assign S_AXI_arready[0] = m02_couplers_to_m02_couplers_ARREADY;
assign S_AXI_awready[0] = m02_couplers_to_m02_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m02_couplers_to_m02_couplers_BRESP;
assign S_AXI_bvalid[0] = m02_couplers_to_m02_couplers_BVALID;
assign S_AXI_rdata[31:0] = m02_couplers_to_m02_couplers_RDATA;
assign S_AXI_rresp[1:0] = m02_couplers_to_m02_couplers_RRESP;
assign S_AXI_rvalid[0] = m02_couplers_to_m02_couplers_RVALID;
assign S_AXI_wready[0] = m02_couplers_to_m02_couplers_WREADY;
assign m02_couplers_to_m02_couplers_ARADDR = S_AXI_araddr[8:0];
assign m02_couplers_to_m02_couplers_ARREADY = M_AXI_arready[0];
assign m02_couplers_to_m02_couplers_ARVALID = S_AXI_arvalid[0];
assign m02_couplers_to_m02_couplers_AWADDR = S_AXI_awaddr[8:0];
assign m02_couplers_to_m02_couplers_AWREADY = M_AXI_awready[0];
assign m02_couplers_to_m02_couplers_AWVALID = S_AXI_awvalid[0];
assign m02_couplers_to_m02_couplers_BREADY = S_AXI_bready[0];
assign m02_couplers_to_m02_couplers_BRESP = M_AXI_bresp[1:0];
assign m02_couplers_to_m02_couplers_BVALID = M_AXI_bvalid[0];
assign m02_couplers_to_m02_couplers_RDATA = M_AXI_rdata[31:0];
assign m02_couplers_to_m02_couplers_RREADY = S_AXI_rready[0];
assign m02_couplers_to_m02_couplers_RRESP = M_AXI_rresp[1:0];
assign m02_couplers_to_m02_couplers_RVALID = M_AXI_rvalid[0];
assign m02_couplers_to_m02_couplers_WDATA = S_AXI_wdata[31:0];
assign m02_couplers_to_m02_couplers_WREADY = M_AXI_wready[0];
assign m02_couplers_to_m02_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m02_couplers_to_m02_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module s00_couplers_imp_1CFO1MB
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
design_1_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
module s00_couplers_imp_7HNO1D
(M_ACLK,
M_ARESETN,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awprot,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [3:0]M_AXI_awlen;
output [1:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
output [63:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [2:0]S_AXI_awprot;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire GND_1;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_auto_us_AWADDR;
wire [1:0]auto_pc_to_auto_us_AWBURST;
wire [3:0]auto_pc_to_auto_us_AWCACHE;
wire [3:0]auto_pc_to_auto_us_AWLEN;
wire [1:0]auto_pc_to_auto_us_AWLOCK;
wire [2:0]auto_pc_to_auto_us_AWPROT;
wire [3:0]auto_pc_to_auto_us_AWQOS;
wire auto_pc_to_auto_us_AWREADY;
wire [2:0]auto_pc_to_auto_us_AWSIZE;
wire auto_pc_to_auto_us_AWVALID;
wire auto_pc_to_auto_us_BREADY;
wire [1:0]auto_pc_to_auto_us_BRESP;
wire auto_pc_to_auto_us_BVALID;
wire [31:0]auto_pc_to_auto_us_WDATA;
wire auto_pc_to_auto_us_WLAST;
wire auto_pc_to_auto_us_WREADY;
wire [3:0]auto_pc_to_auto_us_WSTRB;
wire auto_pc_to_auto_us_WVALID;
wire [31:0]auto_us_to_s00_couplers_AWADDR;
wire [1:0]auto_us_to_s00_couplers_AWBURST;
wire [3:0]auto_us_to_s00_couplers_AWCACHE;
wire [3:0]auto_us_to_s00_couplers_AWLEN;
wire [1:0]auto_us_to_s00_couplers_AWLOCK;
wire [2:0]auto_us_to_s00_couplers_AWPROT;
wire [3:0]auto_us_to_s00_couplers_AWQOS;
wire auto_us_to_s00_couplers_AWREADY;
wire [2:0]auto_us_to_s00_couplers_AWSIZE;
wire auto_us_to_s00_couplers_AWVALID;
wire auto_us_to_s00_couplers_BREADY;
wire [1:0]auto_us_to_s00_couplers_BRESP;
wire auto_us_to_s00_couplers_BVALID;
wire [63:0]auto_us_to_s00_couplers_WDATA;
wire auto_us_to_s00_couplers_WLAST;
wire auto_us_to_s00_couplers_WREADY;
wire [7:0]auto_us_to_s00_couplers_WSTRB;
wire auto_us_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [7:0]s00_couplers_to_auto_pc_AWLEN;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_awaddr[31:0] = auto_us_to_s00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_us_to_s00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_us_to_s00_couplers_AWCACHE;
assign M_AXI_awlen[3:0] = auto_us_to_s00_couplers_AWLEN;
assign M_AXI_awlock[1:0] = auto_us_to_s00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_us_to_s00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_us_to_s00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_us_to_s00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_us_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_us_to_s00_couplers_BREADY;
assign M_AXI_wdata[63:0] = auto_us_to_s00_couplers_WDATA;
assign M_AXI_wlast = auto_us_to_s00_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_us_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_us_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_us_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_us_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_us_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_us_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
GND GND
(.G(GND_1));
design_1_auto_pc_1 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_awaddr(auto_pc_to_auto_us_AWADDR),
.m_axi_awburst(auto_pc_to_auto_us_AWBURST),
.m_axi_awcache(auto_pc_to_auto_us_AWCACHE),
.m_axi_awlen(auto_pc_to_auto_us_AWLEN),
.m_axi_awlock(auto_pc_to_auto_us_AWLOCK),
.m_axi_awprot(auto_pc_to_auto_us_AWPROT),
.m_axi_awqos(auto_pc_to_auto_us_AWQOS),
.m_axi_awready(auto_pc_to_auto_us_AWREADY),
.m_axi_awsize(auto_pc_to_auto_us_AWSIZE),
.m_axi_awvalid(auto_pc_to_auto_us_AWVALID),
.m_axi_bready(auto_pc_to_auto_us_BREADY),
.m_axi_bresp(auto_pc_to_auto_us_BRESP),
.m_axi_bvalid(auto_pc_to_auto_us_BVALID),
.m_axi_wdata(auto_pc_to_auto_us_WDATA),
.m_axi_wlast(auto_pc_to_auto_us_WLAST),
.m_axi_wready(auto_pc_to_auto_us_WREADY),
.m_axi_wstrb(auto_pc_to_auto_us_WSTRB),
.m_axi_wvalid(auto_pc_to_auto_us_WVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(GND_1),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos({GND_1,GND_1,GND_1,GND_1}),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awregion({GND_1,GND_1,GND_1,GND_1}),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
design_1_auto_us_0 auto_us
(.m_axi_awaddr(auto_us_to_s00_couplers_AWADDR),
.m_axi_awburst(auto_us_to_s00_couplers_AWBURST),
.m_axi_awcache(auto_us_to_s00_couplers_AWCACHE),
.m_axi_awlen(auto_us_to_s00_couplers_AWLEN),
.m_axi_awlock(auto_us_to_s00_couplers_AWLOCK),
.m_axi_awprot(auto_us_to_s00_couplers_AWPROT),
.m_axi_awqos(auto_us_to_s00_couplers_AWQOS),
.m_axi_awready(auto_us_to_s00_couplers_AWREADY),
.m_axi_awsize(auto_us_to_s00_couplers_AWSIZE),
.m_axi_awvalid(auto_us_to_s00_couplers_AWVALID),
.m_axi_bready(auto_us_to_s00_couplers_BREADY),
.m_axi_bresp(auto_us_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_us_to_s00_couplers_BVALID),
.m_axi_wdata(auto_us_to_s00_couplers_WDATA),
.m_axi_wlast(auto_us_to_s00_couplers_WLAST),
.m_axi_wready(auto_us_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_us_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_us_to_s00_couplers_WVALID),
.s_axi_aclk(S_ACLK_1),
.s_axi_aresetn(S_ARESETN_1),
.s_axi_awaddr(auto_pc_to_auto_us_AWADDR),
.s_axi_awburst(auto_pc_to_auto_us_AWBURST),
.s_axi_awcache(auto_pc_to_auto_us_AWCACHE),
.s_axi_awlen(auto_pc_to_auto_us_AWLEN),
.s_axi_awlock(auto_pc_to_auto_us_AWLOCK),
.s_axi_awprot(auto_pc_to_auto_us_AWPROT),
.s_axi_awqos(auto_pc_to_auto_us_AWQOS),
.s_axi_awready(auto_pc_to_auto_us_AWREADY),
.s_axi_awsize(auto_pc_to_auto_us_AWSIZE),
.s_axi_awvalid(auto_pc_to_auto_us_AWVALID),
.s_axi_bready(auto_pc_to_auto_us_BREADY),
.s_axi_bresp(auto_pc_to_auto_us_BRESP),
.s_axi_bvalid(auto_pc_to_auto_us_BVALID),
.s_axi_wdata(auto_pc_to_auto_us_WDATA),
.s_axi_wlast(auto_pc_to_auto_us_WLAST),
.s_axi_wready(auto_pc_to_auto_us_WREADY),
.s_axi_wstrb(auto_pc_to_auto_us_WSTRB),
.s_axi_wvalid(auto_pc_to_auto_us_WVALID));
endmodule
|
//Define 32 bit 2s complement
module complement2s(X , x);
// I/O port declaration
output [31:0] X;
input [31:0] x;
reg [31:0]reg1 = 32'd1;
reg reg0 = 1'd0;
//internal nets
wire [31:0]x_not ;
wire shit,shit1;
//internal gate circuitry
not (x_not[0],x[0]);
not (x_not[1],x[1]);
not (x_not[2],x[2]);
not (x_not[3],x[3]);
not (x_not[4],x[4]);
not (x_not[5],x[5]);
not (x_not[6],x[6]);
not (x_not[7],x[7]);
not (x_not[8],x[8]);
not (x_not[9],x[9]);
not (x_not[10],x[10]);
not (x_not[11],x[11]);
not (x_not[12],x[12]);
not (x_not[13],x[13]);
not (x_not[14],x[14]);
not (x_not[15],x[15]);
not (x_not[16],x[16]);
not (x_not[17],x[17]);
not (x_not[18],x[18]);
not (x_not[19],x[19]);
not (x_not[20],x[20]);
not (x_not[21],x[21]);
not (x_not[22],x[22]);
not (x_not[23],x[23]);
not (x_not[24],x[24]);
not (x_not[25],x[25]);
not (x_not[26],x[26]);
not (x_not[27],x[27]);
not (x_not[28],x[28]);
not (x_not[29],x[29]);
not (x_not[30],x[30]);
not (x_not[31],x[31]);
UAdder add( X ,shit1, shit , x_not ,reg1 ,reg0 );
endmodule
|
module simd_alu
(
alu_source1_data,
alu_source2_data,
alu_source3_data, //TODO
alu_source_vcc_value,
alu_source_exec_value,
alu_control,
alu_start,
alu_vgpr_dest_data,
alu_sgpr_dest_data,
alu_dest_vcc_value,
alu_done,
clk,
rst
);
//TODO check overflow for signed and unsigned
input clk;
input rst;
input [31:0] alu_source1_data;
input [31:0] alu_source2_data;
input [31:0] alu_source3_data;
input alu_source_vcc_value;
input alu_source_exec_value;
input [31:0] alu_control;
input alu_start;
output [31:0] alu_vgpr_dest_data;
output alu_sgpr_dest_data;
output alu_dest_vcc_value;
output alu_done;
reg [31:0] alu_vgpr_dest_data;
reg alu_dest_vcc_value;
reg alu_done;
// Signals used by the multiplier
reg [31:0] mul_inp0_s;
reg [31:0] mul_inp1_s;
wire [63:0] mul_out_s; // Combi output from multiplier
reg [1:0] mul_cycles_s; // The current mult takes 4 cycles.
wire mul_busy_s; // High 1 cycle after new mult, till done
wire mul_done_s; // Pulse at end of computation
reg mul_op_s; // Indicates multipler operation underway
wire [31:0] twos_complement_inp0_s;
wire [31:0] twos_complement_inp1_s;
wire [31:0] twos_complement_inp2_s; //VIN
//TODO check logic
reg [31:0] abs_signed_source1_data;
reg [31:0] abs_signed_source2_data;
reg [31:0] abs_signed_source3_data;
reg [31:0] abs_unsigned_source1_data;
reg [31:0] abs_unsigned_source2_data;
reg [31:0] abs_unsigned_source3_data;
reg [31:0] final_signed_source1_data;
reg [31:0] final_signed_source2_data;
reg [31:0] final_signed_source3_data;
reg [31:0] final_unsigned_source1_data;
reg [31:0] final_unsigned_source2_data;
reg [31:0] final_unsigned_source3_data;
assign twos_complement_inp0_s = ~alu_source1_data + 32'd1;
assign twos_complement_inp1_s = ~alu_source2_data + 32'd1;
assign twos_complement_inp2_s = ~alu_source3_data + 32'd1;
assign alu_sgpr_dest_data = alu_dest_vcc_value;
always @* begin
casex(alu_control[31:24])
{`ALU_VOP3A_FORMAT} :
begin
abs_signed_source1_data <= alu_control[`ALU_VOP3A_ABS1_POS]
? (alu_source1_data[31] ? twos_complement_inp0_s : alu_source1_data)
: alu_source1_data;
abs_signed_source2_data <= alu_control[`ALU_VOP3A_ABS2_POS]
? (alu_source2_data[31] ? twos_complement_inp1_s : alu_source2_data)
: alu_source2_data;
abs_signed_source3_data <= alu_control[`ALU_VOP3A_ABS3_POS]
? (alu_source3_data[31] ? twos_complement_inp2_s : alu_source3_data)
: alu_source3_data;
end
default : //VOP1, VOP2 and VOPC
begin
abs_signed_source1_data <= alu_source1_data;
abs_signed_source2_data <= alu_source2_data;
abs_signed_source3_data <= alu_source3_data;
end
endcase
end // always @ (...
always @* begin
casex(alu_control[31:24])
{`ALU_VOP3A_FORMAT} :
begin
final_signed_source1_data <= alu_control[`ALU_VOP3A_NEG1_POS] ? (~abs_signed_source1_data + 32'd1) : abs_signed_source1_data;
final_signed_source2_data <= alu_control[`ALU_VOP3A_NEG2_POS] ? (~abs_signed_source2_data + 32'd1) : abs_signed_source2_data;
final_signed_source3_data <= alu_control[`ALU_VOP3A_NEG3_POS] ? (~abs_signed_source3_data + 32'd1) : abs_signed_source3_data;
final_unsigned_source1_data <= alu_control[`ALU_VOP3A_NEG1_POS] ? twos_complement_inp0_s : alu_source1_data;
final_unsigned_source2_data <= alu_control[`ALU_VOP3A_NEG2_POS] ? twos_complement_inp1_s : alu_source2_data;
final_unsigned_source3_data <= alu_control[`ALU_VOP3A_NEG3_POS] ? twos_complement_inp2_s : alu_source3_data;
end
{`ALU_VOP3B_FORMAT} :
begin
final_signed_source1_data <= alu_control[`ALU_VOP3B_NEG1_POS] ? (~abs_signed_source1_data + 32'd1) : abs_signed_source1_data;
final_signed_source2_data <= alu_control[`ALU_VOP3B_NEG2_POS] ? (~abs_signed_source2_data + 32'd1) : abs_signed_source2_data;
final_signed_source3_data <= alu_control[`ALU_VOP3B_NEG3_POS] ? (~abs_signed_source3_data + 32'd1) : abs_signed_source3_data;
final_unsigned_source1_data <= alu_control[`ALU_VOP3B_NEG1_POS] ? twos_complement_inp0_s : alu_source1_data;
final_unsigned_source2_data <= alu_control[`ALU_VOP3B_NEG2_POS] ? twos_complement_inp1_s : alu_source2_data;
final_unsigned_source3_data <= alu_control[`ALU_VOP3B_NEG3_POS] ? twos_complement_inp2_s : alu_source3_data;
end
default : //VOP1, VOP2 and VOPC
begin
final_signed_source1_data <= abs_signed_source1_data;
final_signed_source2_data <= abs_signed_source2_data;
final_signed_source3_data <= abs_signed_source3_data;
final_unsigned_source1_data <= alu_source1_data;
final_unsigned_source2_data <= alu_source2_data;
final_unsigned_source3_data <= alu_source3_data;
end
endcase
end // always @ (...
always @* begin
casex({alu_source_exec_value, alu_control[31:24], alu_control[11:0]})
{1'b0, 8'h??, 12'h???} : //EXEC disabled
begin
alu_done <= 1'b0;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP1_FORMAT, 12'h001} : //VOP1: V_MOV_B32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= alu_source1_data;
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h025} : //VOP2: V_ADD_I32
begin
alu_done <= 1'b1;
{alu_dest_vcc_value, alu_vgpr_dest_data} <= final_signed_source1_data + final_signed_source2_data;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h026} : //VOP2: V_SUB_I32
begin
alu_done <= 1'b1;
{alu_dest_vcc_value, alu_vgpr_dest_data} <= final_signed_source1_data - final_signed_source2_data;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h01B} : //VOP2: V_AND_B32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= alu_source1_data & alu_source2_data;
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h11B} : //VOP3A: V_AND_B32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= alu_source1_data & alu_source2_data;
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h01C} : //VOP2: V_OR_B32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= alu_source1_data | alu_source2_data;
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h01A} : //VOP2: V_LSHLREV_B32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= alu_source2_data << alu_source1_data[4:0];
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h016} : //VOP2: V_LSHRREV_B32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= alu_source2_data >> alu_source1_data[4:0];
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h018} : //VOP2: V_ASHRREV_I32 - VIN
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= final_signed_source2_data >> final_signed_source1_data[4:0];
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h014} : //VOP2: V_MAX_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= (final_unsigned_source1_data >= final_unsigned_source2_data) ? final_unsigned_source1_data : final_unsigned_source2_data;
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h012} : //VOP2: V_MAX_I32 - VIN
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= (final_signed_source1_data >= final_signed_source2_data) ? final_signed_source1_data : final_signed_source2_data;
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h114} : //VOP3A: V_MAX_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= (final_unsigned_source1_data >= final_unsigned_source2_data) ? final_unsigned_source1_data : final_unsigned_source2_data;
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h013} : //VOP2: V_MIN_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= (final_unsigned_source1_data <= final_unsigned_source2_data) ? final_unsigned_source1_data : final_unsigned_source2_data;
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h113} : //VOP3A: V_MIN_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= (final_unsigned_source1_data <= final_unsigned_source2_data) ? final_unsigned_source1_data : final_unsigned_source2_data;
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h000} : //VOP2: V_CNDMASK_B32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= alu_source_vcc_value ? alu_source2_data : alu_source1_data;
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOPC_FORMAT, 12'h080} : //VOPC: V_CMP_F_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= 1'b0;
end
{1'b1, `ALU_VOPC_FORMAT, 12'h081} : //VOPC: V_CMP_LT_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= (final_signed_source1_data < final_signed_source2_data);
end
{1'b1, `ALU_VOPC_FORMAT, 12'h082} : //VOPC: V_CMP_EQ_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= (final_signed_source1_data == final_signed_source2_data);
end
{1'b1, `ALU_VOPC_FORMAT, 12'h083} : //VOPC: V_CMP_LE_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= (final_signed_source1_data <= final_signed_source2_data);
end
{1'b1, `ALU_VOPC_FORMAT, 12'h084} : //VOPC: V_CMP_GT_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= (final_signed_source1_data > final_signed_source2_data);
end
{1'b1, `ALU_VOPC_FORMAT, 12'h085} : //VOPC: V_CMP_LG_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= (final_signed_source1_data != final_signed_source2_data);
end
{1'b1, `ALU_VOPC_FORMAT, 12'h086} : //VOPC: V_CMP_GE_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= (final_signed_source1_data >= final_signed_source2_data);
end
{1'b1, `ALU_VOPC_FORMAT, 12'h087} : //VOPC: V_CMP_TRU_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= 1'b1;
end
{1'b1, `ALU_VOPC_FORMAT, 12'h0C0} : //VOPC: V_CMP_F_U_32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= 1'b0;
end
{1'b1, `ALU_VOPC_FORMAT, 12'h0C1} : //VOPC: V_CMP_LT_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= ({1'b0, final_unsigned_source1_data} < {1'b0, final_unsigned_source2_data});
end
{1'b1, `ALU_VOPC_FORMAT, 12'h0C2} : //VOPC: V_CMP_EQ_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= ({1'b0, final_unsigned_source1_data} == {1'b0, final_unsigned_source2_data});
end
{1'b1, `ALU_VOPC_FORMAT, 12'h0C3} : //VOPC: V_CMP_LE_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= ({1'b0, final_unsigned_source1_data} <= {1'b0, final_unsigned_source2_data});
end
{1'b1, `ALU_VOPC_FORMAT, 12'h0C4} : //VOPC: V_CMP_GT_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= ({1'b0, final_unsigned_source1_data} > {1'b0, final_unsigned_source2_data});
end
{1'b1, `ALU_VOPC_FORMAT, 12'h0C5} : //VOPC: V_CMP_LG_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= ({1'b0, final_unsigned_source1_data} != {1'b0, final_unsigned_source2_data});
end
{1'b1, `ALU_VOPC_FORMAT, 12'h0C6} : //VOPC: V_CMP_GE_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= ({1'b0, final_unsigned_source1_data} >= {1'b0, final_unsigned_source2_data});
end
{1'b1, `ALU_VOPC_FORMAT, 12'h0C7} : //VOPC: V_CMP_TRU_U_32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= 1'b1;
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h080} : //VOP3a: V_CMP_F_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= 1'b0;
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h081} : //VOP3a: V_CMP_LT_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= (final_signed_source1_data < final_signed_source2_data);
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h082} : //VOP3a: V_CMP_EQ_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= (final_signed_source1_data == final_signed_source2_data);
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h083} : //VOP3a: V_CMP_LE_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= (final_signed_source1_data <= final_signed_source2_data);
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h084} : //VOP3a: V_CMP_GT_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= (final_signed_source1_data > final_signed_source2_data);
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h085} : //VOP3a: V_CMP_LG_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= (final_signed_source1_data != final_signed_source2_data);
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h086} : //VOP3a: V_CMP_GE_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= (final_signed_source1_data >= final_signed_source2_data);
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h087} : //VOP3a: V_CMP_TRU_I32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= 1'b1;
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h0C0} : //VOP3a: V_CMP_F_U_32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= 1'b0;
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h0C1} : //VOP3a: V_CMP_LT_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= ({1'b0, final_unsigned_source1_data} < {1'b0, final_unsigned_source2_data});
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h0C2} : //VOP3a: V_CMP_EQ_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= ({1'b0, final_unsigned_source1_data} == {1'b0, final_unsigned_source2_data});
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h0C3} : //VOP3a: V_CMP_LE_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= ({1'b0, final_unsigned_source1_data} <= {1'b0, final_unsigned_source2_data});
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h0C4} : //VOP3a: V_CMP_GT_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= ({1'b0, final_unsigned_source1_data} > {1'b0, final_unsigned_source2_data});
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h0C5} : //VOP3a: V_CMP_LG_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= ({1'b0, final_unsigned_source1_data} != {1'b0, final_unsigned_source2_data});
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h0C6} : //VOP3a: V_CMP_GE_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= ({1'b0, final_unsigned_source1_data} >= {1'b0, final_unsigned_source2_data});
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h0C7} : //VOP3a: V_CMP_TRU_U_32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= 1'b1;
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h16A} : //VOP3a: V_MUL_HI_U32 => /* D.u = (S0.u * S1.u)>>32 */ VCC not used
begin
alu_done <= mul_done_s;
alu_vgpr_dest_data <= mul_out_s[63:32];
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h009} : //VOP2: V_MUL_I32_I24 => /* D.i = S0.i[23:0] * S1.i[23:0]. */ VCC not used
begin
alu_done <= mul_done_s;
alu_vgpr_dest_data <= mul_out_s[31:0];
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h109} : //VOP3a: V_MUL_I32_I24 => /* D.i = S0.i[23:0] * S1.i[23:0]. */ VCC not used
begin
alu_done <= mul_done_s;
alu_vgpr_dest_data <= mul_out_s[31:0];
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h16B} : //VOP3a: V_MUL_LO_I32 => /* D.i = S0.i * S1.i. */ VCC not used
begin
// TODO-RAGHU-20130205 : When slicing, sign bit is missed.
// FIXME
alu_done <= mul_done_s;
alu_vgpr_dest_data <= mul_out_s[31:0];
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h169} : //VOP3a: V_MUL_LO_U32 => /* D.u = S0.u * S1.u. */ VCC not used
begin
alu_done <= mul_done_s;
alu_vgpr_dest_data <= mul_out_s[31:0];
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h148} : //VOP3A: V_BFE_U32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= (final_unsigned_source1_data >> final_unsigned_source2_data[4:0]) & ((1<<final_unsigned_source3_data[4:0])-1);
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h149} : //VOP3A: V_BFE_I32 - VIN //needs correct implmentation
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= (final_signed_source1_data >>> final_signed_source2_data[4:0]) & ((1 <<< final_signed_source3_data[4:0])-1);
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h14A} : //VOP3A: V_BFI_B32
begin
alu_done <= 1'b1;
alu_vgpr_dest_data <= (alu_source1_data & alu_source2_data) | (~alu_source1_data & alu_source3_data);
alu_dest_vcc_value <= alu_source_vcc_value;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h028} : //VOP2: V_ADDC_U32 - VIN
begin
alu_done <= 1'b1;
{alu_dest_vcc_value, alu_vgpr_dest_data} <= final_unsigned_source1_data + final_unsigned_source2_data + alu_source_vcc_value;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h027} : //VOP2: V_SUBREV_I32 - VIN
begin
alu_done <= 1'b1;
{alu_dest_vcc_value, alu_vgpr_dest_data} <= final_signed_source2_data - final_signed_source1_data;
end
default :
begin
alu_done <= 1'b0;
alu_vgpr_dest_data <= {32{1'bx}};
alu_dest_vcc_value <= 1'bx;
end
endcase
end // always @ (...
// Multiplier inputs
always @* begin
casex({alu_source_exec_value, alu_control[31:24], alu_control[11:0]})
{1'b1, `ALU_VOP3A_FORMAT, 12'h16A} : // V_MUL_HI_U32 => /* D.u = (S0.u * S1.u)>>32 */ VCC not used
begin
mul_op_s <= 1'b1;
mul_inp0_s <= final_unsigned_source1_data;
mul_inp1_s <= final_unsigned_source2_data;
end
{1'b1, `ALU_VOP2_FORMAT, 12'h009} : // V_MUL_I32_I24 => /* D.i = S0.i[23:0] * S1.i[23:0]. */ VCC not used
begin
mul_op_s <= 1'b1;
// ISSUE-Ragh-20130205 : Assuming i24 => 31st bit is sign, [23:0] has data.
if (alu_source1_data[31])
begin
mul_inp0_s[23:0] <= twos_complement_inp0_s[23:0];
mul_inp0_s[31:24] <= 'd0;
end
else
begin
mul_inp0_s[23:0] <= alu_source1_data[23:0];
mul_inp0_s[31:24] <= 'd0;
end
if (alu_source2_data[31])
begin
mul_inp1_s[23:0] <= twos_complement_inp1_s[23:0];
mul_inp1_s[31:24] <= 'd0;
end
else
begin
mul_inp1_s[23:0] <= alu_source2_data[23:0];
mul_inp1_s[31:24] <= 'd0;
end
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h109} : // V_MUL_I32_I24 => /* D.i = S0.i[23:0] * S1.i[23:0]. */ VCC not used
begin
mul_op_s <= 1'b1;
// ISSUE-Ragh-20130205 : Assuming i24 => 31st bit is sign, [23:0] has data.
if (alu_source1_data[31])
begin
mul_inp0_s[23:0] <= twos_complement_inp0_s[23:0];
mul_inp0_s[31:24] <= 'd0;
end
else
begin
mul_inp0_s[23:0] <= alu_source1_data[23:0];
mul_inp0_s[31:24] <= 'd0;
end
if (alu_source2_data[31])
begin
mul_inp1_s[23:0] <= twos_complement_inp1_s[23:0];
mul_inp1_s[31:24] <= 'd0;
end
else
begin
mul_inp1_s[23:0] <= alu_source1_data[23:0];
mul_inp1_s[31:24] <= 'd0;
end
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h16B} : // V_MUL_LO_I32 => /* D.i = S0.i * S1.i. */ VCC not used
begin
mul_op_s <= 1'b1;
if (alu_source1_data[31])
mul_inp0_s <= twos_complement_inp0_s;
else
mul_inp0_s <= alu_source1_data;
if (alu_source2_data[31])
mul_inp1_s <= twos_complement_inp1_s;
else
mul_inp1_s <= alu_source2_data;
end
{1'b1, `ALU_VOP3A_FORMAT, 12'h169} : // V_MUL_LO_U32 => /* D.u = S0.u * S1.u. */ VCC not used
begin
mul_op_s <= 1'b1;
mul_inp0_s <= alu_source1_data;
mul_inp1_s <= alu_source2_data;
end
default :
begin
mul_op_s <= 1'b0;
mul_inp0_s <= 'd0;
mul_inp1_s <= 'd0;
end
endcase
end // always @ (...
// Booth multiplier from openrisc
// amultp2_32x32 amultp2_32x32
// (
// .X(mul_inp0_s),
// .Y(mul_inp1_s),
// .RST(rst),
// .CLK(clk),
// .P(mul_out_s)
// );
assign mul_out_s = mul_inp0_s * mul_inp1_s;
assign mul_busy_s = |mul_cycles_s;
assign mul_done_s = (mul_cycles_s == 2'd2);
always @(posedge clk or posedge rst)
if (rst)
begin
mul_cycles_s <= 'd0;
end
else
begin
if (~mul_op_s)
begin
mul_cycles_s <= 'd0;
end
else
begin
if (mul_cycles_s == 2'd2)
mul_cycles_s <= 'd0;
else
mul_cycles_s <= mul_cycles_s + 'd1;
end
end
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Verilog implementation of MBUS
*
* This block is the new bus controller, maintaining the same interface
* as the previous I2C controller. However, the current implementation of
* MBUS makes certain assumptions about the transmissions:
*
* 1. The transmission each round is always 32-bits, i.e. TX_DATA is 32-bit
* wide. This could be changed in the definitions file include/mbus_def.v
*
* 2. Transmissions only use short (8-bit) addresses.
*
* In addition, MBUS adds new features:
*
* 1. The additional TX_PRIORITY input. This input sets the transmission
* priority. If the TX_PRIORITY input has been asserted, it gives additional
* flexibility for the lower layer to win bus arbitration.
*
* 2. TX_PEND, RX_PEND. These inputs indicate more data coming after first
* transmission, i.e. if TX_REQ and TX_PEND are asserted at the same time,
* when the MBUS controller latches the inputs the BUS controller knows more
* data to the same destination will follow. If the next TX_REQ does not assert
* in time, the bus controller experiences a TX_FAIL (tx buffer underflow).
* Similarly for RX_PEND, if RX_REQ is asserted the layer controller must also
* monitorthe RX_PEND signal, which indicates more data for the same message
* follows.
*
* 3. The broadcast message. Every layer in MBUS will receive and acknowledge
* broadcast messages. The destination address of broadcast message is 0x00.
*
* To create a simple node that wires up to an old layer controller that
* generates data in 32-bit segments:
*
* 1. connect all interfaces,
* 2. connect TX_PEND to 0, every transmit is 32-bits wide
* 3. float RX_PEND, old layer controller doesn't support this
* 4. connect PRIORITU to 0, every transmission is a regular transmission
* 5. set corresponding address and address mask by parameter, the address
* mask indicates which bits are comparing to:
* i.e. ADDRESS_MASK = 8'hff, all 8-bits of address must match.
* i.e. ADDRESS_MASK = 8'hf0, compare only upper 4-bit of address (from MSB)
*
*
* Last modified date: 09/05 '13
* Last modified by: Yoonmyung Lee <[email protected]>
*
* Update log:
* 9/5 '13
* Change port names:
* RELEASE_RST_FROM_SLEEP_CTRL -> MBC_RESET
* POWER_ON_TO_LAYER_CTRL -> LRC_SLEEP
* RELEASE_CLK_TO_LAYER_CTRL -> LRC_CLKENB
* RELEASE_ISO_TO_LAYER_CTRL -> LRC_ISOLATE
* RELEASE_RST_TO_LAYER_CTRL -> LRC_RESET
* 5/9 '13
* Change tx_broadcast_latched from TX_ADDR to ADDR
* 5/6 '13
* Rename PRIORITY -> TX_PRIORITY
* 5/1 '13
* Add CLR_BUSY Port
* 4/28 '13
* fixed streaming broadcast RX_REQ asserts in between
* 4/24 '13
* change RX_REQ, RX_FAIL and RX_PEND by asynchronize reset from RX_ACK
* 4/16 '13
* fixed reset state for control node, since control node has different sleep
* controller, it resets bus controller before clk chain ticks. Thus, it
* should go to BUS_ILDE state for control node
* 4/15 '13
* remove BUS_PWR_OVERRIDE port
* 4/14 '13
* Add power related signals, these signals are only for simulation, in real
* setting, the isolation block will assert these signals to layer controller
* Add a BUS_PWR_OVERRIDE port, this signal indicates ctrl_wrapper to switch
* the mux
* 4/09 '13
* changed to 32-bit long and short address scheme,
* add external int,
* 3/16 '13
* Add power gated signals, move reset state to RX_ADDR
* 3/6 '13
* switch clock mux to posedge edge trigger, clock holds at high if a node request
* interrupt, bypass clock once interrupt occurred
* */
`include "include/mbus_def.v"
module mbus_node(
input CLKIN,
input RESETn,
input DIN,
output reg CLKOUT,
output reg DOUT,
input [`ADDR_WIDTH-1:0] TX_ADDR,
input [`DATA_WIDTH-1:0] TX_DATA,
input TX_PEND,
input TX_REQ,
output reg TX_ACK,
input TX_PRIORITY,
output reg [`ADDR_WIDTH-1:0] RX_ADDR,
output reg [`DATA_WIDTH-1:0] RX_DATA,
output reg RX_PEND,
output reg RX_REQ,
input RX_ACK,
output RX_BROADCAST,
input rx_snoop,
output reg RX_FAIL,
output reg TX_FAIL,
output reg TX_SUCC,
input TX_RESP_ACK,
`ifdef POWER_GATING
// power gated signals from sleep controller
input MBC_RESET,
// power gated signals to layer controller
output reg LRC_SLEEP,
output reg LRC_CLKENB,
output reg LRC_RESET,
output reg LRC_ISOLATE,
// power gated signal to sleep controller
output reg SLEEP_REQUEST_TO_SLEEP_CTRL,
// External interrupt
input EXTERNAL_INT,
output reg CLR_EXT_INT,
output reg CLR_BUSY,
`endif
// interface with local register files (RF)
input [`DYNA_WIDTH-1:0] ASSIGNED_ADDR_IN,
output [`DYNA_WIDTH-1:0] ASSIGNED_ADDR_OUT,
input ASSIGNED_ADDR_VALID,
output reg ASSIGNED_ADDR_WRITE,
output reg ASSIGNED_ADDR_INVALIDn,
output [3:0] debug
);
`include "include/mbus_func.v"
parameter ADDRESS = 20'habcde;
wire [`PRFIX_WIDTH-1:0] ADDRESS_MASK = {(`PRFIX_WIDTH){~rx_snoop}};
wire [`DYNA_WIDTH-1:0] ADDRESS_MASK_SHORT = {`DYNA_WIDTH{~rx_snoop}};
// Node mode
parameter MODE_TX_NON_PRIO = 2'd0;
parameter MODE_TX = 2'd1;
parameter MODE_RX = 2'd2;
parameter MODE_FWD = 2'd3;
// BUS state
parameter BUS_IDLE = 0;
parameter BUS_ARBITRATE = 1;
parameter BUS_PRIO = 2;
parameter BUS_ADDR = 3;
parameter BUS_DATA_RX_ADDI = 4;
parameter BUS_DATA = 5;
parameter BUS_DATA_RX_CHECK = 6;
parameter BUS_REQ_INTERRUPT = 7;
parameter BUS_CONTROL0 = 8;
parameter BUS_CONTROL1 = 9;
parameter BUS_BACK_TO_IDLE = 10;
parameter NUM_OF_BUS_STATE = 11;
// Address enumeration response type
parameter ADDR_ENUM_RESPOND_T1 = 2'b00;
parameter ADDR_ENUM_RESPOND_T2 = 2'b10;
parameter ADDR_ENUM_RESPOND_NONE = 2'b11;
// TX broadcast data length
parameter LENGTH_1BYTE = 2'b00;
parameter LENGTH_2BYTE = 2'b01;
parameter LENGTH_3BYTE = 2'b10;
parameter LENGTH_4BYTE = 2'b11;
parameter RX_ABOVE_TX = 1'b1;
parameter RX_BELOW_TX = 1'b0;
// override this parameter to "1'b1" if the node is master
parameter MASTER_NODE = 1'b0;
// override this parameter to "1'b1" if the layer is CPU
parameter CPU_LAYER = 1'b0;//TODO: Set this to 1'b1 in order to listen to broadcast messages
wire [1:0] CONTROL_BITS = `CONTROL_SEQ; // EOM?, ~ACK?
// general registers
reg [1:0] mode, next_mode, mode_neg, mode_temp;
reg [log2(NUM_OF_BUS_STATE-1)-1:0] bus_state, next_bus_state, bus_state_neg;
reg [log2(`DATA_WIDTH-1)-1:0] bit_position, next_bit_position;
reg req_interrupt, next_req_interrupt;
reg out_reg_pos, next_out_reg_pos, out_reg_neg;
reg next_clr_busy;
assign debug = bus_state;
// tx registers
reg [`ADDR_WIDTH-1:0] ADDR, next_addr;
reg [`DATA_WIDTH-1:0] DATA, next_data;
reg tx_pend, next_tx_pend;
reg tx_underflow, next_tx_underflow;
reg ctrl_bit_buf, next_ctrl_bit_buf;
// rx registers
reg [`ADDR_WIDTH-1:0] next_rx_addr;
reg [`DATA_WIDTH-1:0] next_rx_data;
reg [`DATA_WIDTH+1:0] rx_data_buf, next_rx_data_buf;
reg next_rx_fail;
// address enumation registers
reg [1:0] enum_addr_resp, next_enum_addr_resp;
reg next_assigned_addr_write;
reg next_assigned_addr_invalidn;
// interrupt register
reg BUS_INT_RSTn;
wire BUS_INT;
// interface registers
reg next_tx_ack;
reg next_tx_fail;
reg next_tx_success;
reg next_rx_req;
reg next_rx_pend;
wire addr_bit_extract = ((ADDR & (1'b1<<bit_position))==0)? 1'b0 : 1'b1;
wire data_bit_extract = ((DATA & (1'b1<<bit_position))==0)? 1'b0 : 1'b1;
reg [1:0] addr_match_temp;
wire address_match = (addr_match_temp[1] | addr_match_temp[0]);
// Broadcast processing
reg [`BROADCAST_CMD_WIDTH -1:0] rx_broadcast_command;
wire rx_long_addr_en = (RX_ADDR[`ADDR_WIDTH-1:`ADDR_WIDTH-4]==4'hf)? 1'b1 : 1'b0;
wire tx_long_addr_en = (TX_ADDR[`ADDR_WIDTH-1:`ADDR_WIDTH-4]==4'hf)? 1'b1 : 1'b0;
wire tx_long_addr_en_latched = (ADDR[`ADDR_WIDTH-1:`ADDR_WIDTH-4]==4'hf)? 1'b1 : 1'b0;
reg tx_broadcast_latched;
reg [1:0] tx_dat_length, rx_dat_length;
reg rx_position, rx_dat_length_valid;
reg wakeup_req;
wire [`DATA_WIDTH-1:0] broadcast_addr = `BROADCAST_ADDR;
wire [`DATA_WIDTH-1:0] rx_data_buf_proc = (rx_dat_length_valid)? (rx_position==RX_BELOW_TX)? rx_data_buf[`DATA_WIDTH-1:0] : rx_data_buf[`DATA_WIDTH+1:2] : {`DATA_WIDTH{1'b0}};
// Power gating related signals
`ifdef POWER_GATING
wire RESETn_local = (RESETn & (~MBC_RESET));
`else
wire RESETn_local = RESETn;
`endif
`ifdef POWER_GATING
reg [1:0] powerup_seq_fsm;
reg shutdown, next_shutdown;
reg ext_int;
`endif
wire [15:0] layer_slot = (1'b1<<ASSIGNED_ADDR_IN);
// Assignments
assign RX_BROADCAST = addr_match_temp[0];
assign ASSIGNED_ADDR_OUT = DATA[`DYNA_WIDTH-1:0];
// Node priority
// Used only when the BUS_STATE == BUS_PRIO, determine the node should be RX or TX
always @ *
begin
mode_temp = MODE_RX;
if (mode==MODE_TX_NON_PRIO)
begin
// Other node request priority,
if (DIN & (~TX_PRIORITY))
mode_temp = MODE_RX;
else
mode_temp = MODE_TX;
end
else
begin
// the node won first trial doesn't request priority
if (TX_REQ & TX_PRIORITY & (~DIN))
mode_temp = MODE_TX;
else
mode_temp = MODE_RX;
end
end
// End of node priority
// TX Broadcast
// For some boradcast message, TX node should take apporiate action, ex: all node sleep
// determined by ADDR flops, not TX_ADDR
always @ *
begin
tx_broadcast_latched = 0;
if (tx_long_addr_en_latched)
begin
if (ADDR[`DATA_WIDTH-1:`FUNC_WIDTH]==broadcast_addr[`DATA_WIDTH-1:`FUNC_WIDTH])
tx_broadcast_latched = 1;
end
else
begin
if (ADDR[`SHORT_ADDR_WIDTH-1:`FUNC_WIDTH]==broadcast_addr[`SHORT_ADDR_WIDTH-1:`FUNC_WIDTH])
tx_broadcast_latched = 1;
end
end
// End of TX broadcast
// Wake up control
// What type of message should wake up the layer controller (LC)
always @ *
begin
wakeup_req = 0;
// normal messages
if (~RX_BROADCAST)
wakeup_req = address_match;
else
begin
// master node should wake up for every broadcast message
if (MASTER_NODE==1'b1)
wakeup_req = address_match;
// which channels should wake up
case (RX_ADDR[`FUNC_WIDTH-1:0])
`CHANNEL_POWER:
begin
case (rx_data_buf[`BROADCAST_CMD_WIDTH-1:0])
`CMD_CHANNEL_POWER_ALL_WAKE: begin wakeup_req = 1; end
endcase
end
default: begin end
endcase
end
end
// End of Wake up control
// Address compare
// This block determine the incoming message has match the address or not
always @ *
begin
addr_match_temp = 2'b00;
if (rx_long_addr_en)
begin
if (RX_ADDR[`DATA_WIDTH-1:`FUNC_WIDTH]==broadcast_addr[`DATA_WIDTH-1:`FUNC_WIDTH])
addr_match_temp[0] = 1;
if (((RX_ADDR[`DATA_WIDTH-`RSVD_WIDTH-1:`FUNC_WIDTH] ^ ADDRESS) & ADDRESS_MASK)==0)
addr_match_temp[1] = 1;
end
// short address assigned
else
begin
if (RX_ADDR[`SHORT_ADDR_WIDTH-1:`FUNC_WIDTH]==broadcast_addr[`SHORT_ADDR_WIDTH-1:`FUNC_WIDTH])
addr_match_temp[0] = 1;
if (ASSIGNED_ADDR_VALID)
begin
if (((RX_ADDR[`SHORT_ADDR_WIDTH-1:`FUNC_WIDTH] ^ ASSIGNED_ADDR_IN) & ADDRESS_MASK_SHORT)==0)
addr_match_temp[1] = 1;
end
end
end
// End of address compare
// TX broadcast command length
// This only take care the broadcast command issued from layer controller
// CANNOT use this in self generate enumerate response
always @ *
begin
tx_dat_length = LENGTH_4BYTE;
if (tx_broadcast_latched)
begin
case (ADDR[`FUNC_WIDTH-1:0])
`CHANNEL_ENUM:
begin
case (DATA[`DATA_WIDTH-1:`DATA_WIDTH-`BROADCAST_CMD_WIDTH])
`CMD_CHANNEL_ENUM_QUERRY: begin tx_dat_length = LENGTH_1BYTE; end
`CMD_CHANNEL_ENUM_RESPONSE: begin tx_dat_length = LENGTH_4BYTE; end
`CMD_CHANNEL_ENUM_ENUMERATE: begin tx_dat_length = LENGTH_1BYTE; end
`CMD_CHANNEL_ENUM_INVALIDATE: begin tx_dat_length = LENGTH_1BYTE; end
endcase
end
`CHANNEL_POWER:
begin
case (DATA[`DATA_WIDTH-1:`DATA_WIDTH-`BROADCAST_CMD_WIDTH])
`CMD_CHANNEL_POWER_ALL_SLEEP: begin tx_dat_length = LENGTH_1BYTE; end
`CMD_CHANNEL_POWER_ALL_WAKE: begin tx_dat_length = LENGTH_1BYTE; end
`CMD_CHANNEL_POWER_SEL_SLEEP: begin tx_dat_length = LENGTH_3BYTE; end
`CMD_CHANNEL_POWER_SEL_SLEEP_FULL: begin tx_dat_length = LENGTH_4BYTE; end
`CMD_CHANNEL_POWER_SEL_WAKE: begin tx_dat_length = LENGTH_3BYTE; end
endcase
end
endcase
end
end
// This block used to determine the received data length.
// only broadcast can be any byte aligned
// otherwise, regular message has to be word aligned
always @ *
begin
rx_dat_length = LENGTH_4BYTE;
rx_dat_length_valid = 0;
rx_position = RX_ABOVE_TX;
case (bit_position)
1: begin rx_dat_length = LENGTH_4BYTE; rx_dat_length_valid = 1; rx_position = RX_BELOW_TX; end
(`DATA_WIDTH-1'b1): begin rx_dat_length = LENGTH_4BYTE; rx_dat_length_valid = 1; rx_position = RX_ABOVE_TX; end
9: begin rx_dat_length = LENGTH_3BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_BELOW_TX; end
7: begin rx_dat_length = LENGTH_3BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_ABOVE_TX; end
17: begin rx_dat_length = LENGTH_2BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_BELOW_TX; end
15: begin rx_dat_length = LENGTH_2BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_ABOVE_TX; end
25: begin rx_dat_length = LENGTH_1BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_BELOW_TX; end
23: begin rx_dat_length = LENGTH_1BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_ABOVE_TX; end
endcase
end
always @ *
begin
rx_broadcast_command = rx_data_buf_proc[`DATA_WIDTH-1:`DATA_WIDTH-`BROADCAST_CMD_WIDTH];
case (rx_dat_length)
LENGTH_4BYTE: begin rx_broadcast_command = rx_data_buf_proc[`DATA_WIDTH-1:`DATA_WIDTH-`BROADCAST_CMD_WIDTH]; end
LENGTH_3BYTE: begin rx_broadcast_command = rx_data_buf_proc[`DATA_WIDTH-9:`DATA_WIDTH-`BROADCAST_CMD_WIDTH-8]; end
LENGTH_2BYTE: begin rx_broadcast_command = rx_data_buf_proc[`DATA_WIDTH-17:`DATA_WIDTH-`BROADCAST_CMD_WIDTH-16]; end
LENGTH_1BYTE: begin rx_broadcast_command = rx_data_buf_proc[`DATA_WIDTH-25:`DATA_WIDTH-`BROADCAST_CMD_WIDTH-24]; end
endcase
end
always @ (posedge CLKIN or negedge RESETn_local)
begin
if (~RESETn_local)
begin
`ifdef POWER_GATING
if (MASTER_NODE==1'b1)
bus_state <= BUS_IDLE;
else
bus_state <= BUS_PRIO;
`else
bus_state <= BUS_IDLE;
`endif
BUS_INT_RSTn <= 1;
end
else
begin
if (BUS_INT)
begin
bus_state <= BUS_CONTROL0;
BUS_INT_RSTn <= 0;
end
else
begin
bus_state <= next_bus_state;
BUS_INT_RSTn <= 1;
end
end
end
wire TX_RESP_RSTn = RESETn_local & (~TX_RESP_ACK);
always @ (posedge CLKIN or negedge TX_RESP_RSTn)
begin
if (~TX_RESP_RSTn)
begin
TX_FAIL <= 0;
TX_SUCC <= 0;
end
else
begin
TX_FAIL <= next_tx_fail;
TX_SUCC <= next_tx_success;
end
end
wire RX_ACK_RSTn = RESETn_local & (~RX_ACK);
always @ (posedge CLKIN or negedge RX_ACK_RSTn)
begin
if (~RX_ACK_RSTn)
begin
RX_REQ <= 0;
RX_PEND <= 0;
RX_FAIL <= 0;
end
else if (~BUS_INT)
begin
RX_REQ <= next_rx_req;
RX_PEND <= next_rx_pend;
RX_FAIL <= next_rx_fail;
end
end
always @ (posedge CLKIN or negedge RESETn_local)
begin
if (~RESETn_local)
begin
// general registers
mode <= MODE_RX;
bit_position <= `ADDR_WIDTH - 1'b1;
req_interrupt <= 0;
out_reg_pos <= 0;
CLR_BUSY <= 0;
// Transmitter registers
ADDR <= 0;
DATA <= 0;
tx_pend <= 0;
tx_underflow <= 0;
ctrl_bit_buf <= 0;
// Receiver register
RX_ADDR <= 0;
RX_DATA <= 0;
rx_data_buf <= 0;
// Interface registers
TX_ACK <= 0;
`ifdef POWER_GATING
// power gated related signal
shutdown <= 0;
`endif
// address enumeration
enum_addr_resp <= ADDR_ENUM_RESPOND_NONE;
// address enumeration interface
ASSIGNED_ADDR_WRITE <= 0;
ASSIGNED_ADDR_INVALIDn <= 1;
end
else
begin
// general registers
mode <= next_mode;
if (~BUS_INT)
begin
bit_position <= next_bit_position;
rx_data_buf <= next_rx_data_buf;
// Receiver register
RX_ADDR <= next_rx_addr;
RX_DATA <= next_rx_data;
end
req_interrupt <= next_req_interrupt;
out_reg_pos <= next_out_reg_pos;
CLR_BUSY <= next_clr_busy;
// Transmitter registers
ADDR <= next_addr;
DATA <= next_data;
tx_pend <= next_tx_pend;
tx_underflow <= next_tx_underflow;
ctrl_bit_buf <= next_ctrl_bit_buf;
// Interface registers
TX_ACK <= next_tx_ack;
`ifdef POWER_GATING
// power gated related signal
shutdown <= next_shutdown;
`endif
// address enumeration
enum_addr_resp <= next_enum_addr_resp;
// address enumeration interface
ASSIGNED_ADDR_WRITE <= next_assigned_addr_write;
ASSIGNED_ADDR_INVALIDn <= next_assigned_addr_invalidn;
end
end
always @ *
begin
// general registers
next_mode = mode;
next_bus_state = bus_state;
next_bit_position = bit_position;
next_req_interrupt = req_interrupt;
next_out_reg_pos = out_reg_pos;
next_clr_busy = CLR_BUSY;
// Transmitter registers
next_addr = ADDR;
next_data = DATA;
next_tx_pend = tx_pend;
next_tx_underflow = tx_underflow;
next_ctrl_bit_buf = ctrl_bit_buf;
// Receiver register
next_rx_addr = RX_ADDR;
next_rx_data = RX_DATA;
next_rx_fail = RX_FAIL;
next_rx_data_buf = rx_data_buf;
// Interface registers
next_rx_req = RX_REQ;
next_rx_pend = RX_PEND;
next_tx_fail = TX_FAIL;
next_tx_success = TX_SUCC;
next_tx_ack = TX_ACK;
// Address enumeration
next_enum_addr_resp = enum_addr_resp;
// Address enumeratio interface
next_assigned_addr_write = 0;
next_assigned_addr_invalidn = 1;
// Asynchronous interface
if (TX_ACK & (~TX_REQ))
next_tx_ack = 0;
`ifdef POWER_GATING
// power gating signals
next_shutdown = shutdown;
`endif
case (bus_state)
BUS_IDLE:
begin
if (DIN^DOUT)
next_mode = MODE_TX_NON_PRIO;
else
next_mode = MODE_RX;
// general registers
next_bus_state = BUS_ARBITRATE;
next_bit_position = `ADDR_WIDTH - 1'b1;
end
BUS_ARBITRATE:
begin
next_bus_state = BUS_PRIO;
end
BUS_PRIO:
begin
next_clr_busy = 0;
next_mode = mode_temp;
next_bus_state = BUS_ADDR;
// no matter this node wins the arbitration or not, must clear
// type T1
if (enum_addr_resp== ADDR_ENUM_RESPOND_T1)
next_enum_addr_resp = ADDR_ENUM_RESPOND_NONE;
if (mode_temp==MODE_TX)
begin
case (enum_addr_resp)
// respond to enumeration
ADDR_ENUM_RESPOND_T1:
begin
next_bit_position = `SHORT_ADDR_WIDTH - 1'b1;
next_assigned_addr_write = 1;
end
// respond to query
ADDR_ENUM_RESPOND_T2:
begin
next_bit_position = `SHORT_ADDR_WIDTH - 1'b1;
next_enum_addr_resp = ADDR_ENUM_RESPOND_NONE;
end
// TX initiated from layer controller
default:
begin
next_addr = TX_ADDR;
next_data = TX_DATA;
next_tx_ack = 1;
next_tx_pend = TX_PEND;
if (tx_long_addr_en)
next_bit_position = `ADDR_WIDTH - 1'b1;
else
next_bit_position = `SHORT_ADDR_WIDTH - 1'b1;
end
endcase
end
else
// RX mode
begin
next_rx_data_buf = 0;
next_rx_addr = 0;
end
end
BUS_ADDR:
begin
case (mode)
MODE_TX:
begin
if (bit_position)
next_bit_position = bit_position - 1'b1;
else
begin
next_bit_position = `DATA_WIDTH - 1'b1;
next_bus_state = BUS_DATA;
end
end
MODE_RX:
begin
// short address
if ((bit_position==`ADDR_WIDTH-3'd5)&&(RX_ADDR[3:0]!=4'hf))
next_bit_position = `SHORT_ADDR_WIDTH - 3'd6;
else
begin
if (bit_position)
next_bit_position = bit_position - 1'b1;
else
begin
next_bit_position = `DATA_WIDTH - 1'b1;
next_bus_state = BUS_DATA_RX_ADDI;
end
end
next_rx_addr = {RX_ADDR[`ADDR_WIDTH-2:0], DIN};
end
endcase
end
BUS_DATA_RX_ADDI:
begin
next_rx_data_buf = {rx_data_buf[`DATA_WIDTH:0], DIN};
next_bit_position = bit_position - 1'b1;
`ifdef POWER_GATING
next_shutdown = 0;
`endif
if (bit_position==(`DATA_WIDTH-2'b10))
begin
next_bus_state = BUS_DATA;
next_bit_position = `DATA_WIDTH - 1'b1;
end
if (address_match==0)
next_mode = MODE_FWD;
end
BUS_DATA:
begin
case (mode)
MODE_TX:
begin
// support variable tx length for broadcast messages
if (((tx_dat_length==LENGTH_4BYTE)&&(bit_position>0))||((tx_dat_length==LENGTH_3BYTE)&&(bit_position>8))||((tx_dat_length==LENGTH_2BYTE)&&(bit_position>16))||((tx_dat_length==LENGTH_1BYTE)&&(bit_position>24)))
//if (bit_position)
next_bit_position = bit_position - 1'b1;
else
begin
next_bit_position = `DATA_WIDTH - 1'b1;
case ({tx_pend, TX_REQ})
// continue next word
2'b11:
begin
next_tx_pend = TX_PEND;
next_data = TX_DATA;
next_tx_ack = 1;
end
// underflow
2'b10:
begin
next_bus_state = BUS_REQ_INTERRUPT;
next_tx_underflow = 1;
next_req_interrupt = 1;
next_tx_fail = 1;
end
default:
begin
next_bus_state = BUS_REQ_INTERRUPT;
next_req_interrupt = 1;
end
endcase
end
end
MODE_RX:
begin
next_rx_data_buf = {rx_data_buf[`DATA_WIDTH:0], DIN};
if (bit_position)
next_bit_position = bit_position - 1'b1;
else
begin
if (RX_REQ)
begin
// RX overflow
next_bus_state = BUS_REQ_INTERRUPT;
next_req_interrupt = 1;
next_rx_fail = 1;
end
else
begin
next_bus_state = BUS_DATA_RX_CHECK;
next_bit_position = `DATA_WIDTH - 1'b1;
end
end
end
endcase
end
BUS_DATA_RX_CHECK:
begin
next_bit_position = bit_position - 1'b1;
next_rx_data_buf = {rx_data_buf[`DATA_WIDTH:0], DIN};
if (RX_BROADCAST)
begin
if (CPU_LAYER==1'b1)
next_rx_req = 1;
else
next_rx_req = 0;
end
else
next_rx_req = 1;
next_rx_pend = 1;
next_rx_data = rx_data_buf[`DATA_WIDTH+1:2];
next_bus_state = BUS_DATA;
end
BUS_REQ_INTERRUPT:
begin
end
BUS_CONTROL0:
begin
next_bus_state = BUS_CONTROL1;
next_ctrl_bit_buf = DIN;
case (mode)
MODE_TX:
begin
if (req_interrupt)
begin
// Prevent wire floating
next_out_reg_pos = ~CONTROL_BITS[0];
if (tx_broadcast_latched)
begin
case (ADDR[`FUNC_WIDTH-1:0])
`CHANNEL_POWER:
begin
case (DATA[`DATA_WIDTH-1:`DATA_WIDTH-`BROADCAST_CMD_WIDTH ])
`CMD_CHANNEL_POWER_ALL_SLEEP:
begin
next_shutdown = 1;
end
`CMD_CHANNEL_POWER_SEL_SLEEP:
begin
if ((DATA[27:12]&layer_slot)>0)
next_shutdown = 1;
end
`CMD_CHANNEL_POWER_SEL_SLEEP_FULL:
begin
if (((DATA[`PRFIX_WIDTH+3:4] ^ ADDRESS) & ADDRESS_MASK)==0)
next_shutdown = 1;
end
endcase
end
endcase
end
end
else
begin
next_tx_fail = 1;
end
end
MODE_RX:
begin
if (req_interrupt)
next_out_reg_pos = ~CONTROL_BITS[0];
else
begin
// End of Message
// correct ending state
// rx above tx = 31
// rx below tx = 1
if ((DIN==CONTROL_BITS[1])&&(rx_dat_length_valid))
begin
// rx overflow
if (RX_REQ)
begin
next_out_reg_pos = ~CONTROL_BITS[0];
next_rx_fail = 1;
end
else
// assert rx_req if not a broadcast
begin
next_rx_data = rx_data_buf_proc;
next_out_reg_pos = CONTROL_BITS[0];
if (~RX_BROADCAST)
next_rx_req = 1;
next_rx_pend = 0;
end
// broadcast message
if (RX_BROADCAST)
begin
// assert broadcast rx_req only in CPU layer
if ((CPU_LAYER==1'b1)&&(~RX_REQ))
next_rx_req = 1;
// broadcast channel
case (RX_ADDR[`FUNC_WIDTH-1:0])
`CHANNEL_ENUM:
begin
case (rx_broadcast_command)
// any node should report its full prefix and short prefix (dynamic allocated address)
// Pad "0" if the dynamic address is invalid
`CMD_CHANNEL_ENUM_QUERRY:
begin
// this node doesn't have a valid short address, active low
next_enum_addr_resp = ADDR_ENUM_RESPOND_T2;
next_addr = broadcast_addr[`SHORT_ADDR_WIDTH-1:0];
next_data = ((`CMD_CHANNEL_ENUM_RESPONSE<<(`DATA_WIDTH-`BROADCAST_CMD_WIDTH)) | (ADDRESS<<`DYNA_WIDTH) | ASSIGNED_ADDR_IN);
end
// request arbitration, set short prefix if successed
`CMD_CHANNEL_ENUM_ENUMERATE:
begin
if (~ASSIGNED_ADDR_VALID)
begin
next_enum_addr_resp = ADDR_ENUM_RESPOND_T1;
next_addr = broadcast_addr[`SHORT_ADDR_WIDTH-1:0];
next_data = ((`CMD_CHANNEL_ENUM_RESPONSE<<(`DATA_WIDTH-`BROADCAST_CMD_WIDTH)) | (ADDRESS<<`DYNA_WIDTH) | rx_data_buf_proc[`DYNA_WIDTH-1:0]);
end
end
`CMD_CHANNEL_ENUM_INVALIDATE:
begin
case (rx_data_buf_proc[`DYNA_WIDTH-1:0])
{`DYNA_WIDTH{1'b1}}: begin next_assigned_addr_invalidn = 0; end
ASSIGNED_ADDR_IN: begin next_assigned_addr_invalidn = 0; end
default: begin end
endcase
end
endcase
end
`CHANNEL_POWER:
begin
// PWR Command
case (rx_broadcast_command)
`CMD_CHANNEL_POWER_ALL_SLEEP:
begin
next_shutdown = 1;
end
`CMD_CHANNEL_POWER_SEL_SLEEP:
begin
if ((rx_data_buf_proc[19:4]&layer_slot)>0)
next_shutdown = 1;
end
`CMD_CHANNEL_POWER_SEL_SLEEP_FULL:
begin
if (((rx_data_buf_proc[`PRFIX_WIDTH+3:4] ^ ADDRESS) & ADDRESS_MASK)==0)
next_shutdown = 1;
end
endcase
end
// shoud only be active at master
`CHANNEL_CTRL:
begin
if (MASTER_NODE==1'b1)
next_rx_req = 1;
end
endcase
end // endif rx_broadcast
end // endif valid reception
else
// invalid data length or invalid EOM
begin
next_out_reg_pos = ~CONTROL_BITS[0];
`ifdef POWER_GATING
if (~ext_int)
next_rx_fail = 1;
`else
next_rx_fail = 1;
`endif
end
end
end
endcase
end
BUS_CONTROL1:
begin
next_bus_state = BUS_BACK_TO_IDLE;
if (req_interrupt)
begin
if ((mode==MODE_TX)&&(~tx_underflow))
begin
// ACK received
if ({ctrl_bit_buf, DIN}==CONTROL_BITS)
next_tx_success = 1;
else
next_tx_fail = 1;
end
end
end
BUS_BACK_TO_IDLE:
begin
next_clr_busy = 1;
next_bus_state = BUS_IDLE;
next_req_interrupt = 0;
next_mode = MODE_RX;
next_tx_underflow = 0;
end
endcase
end
`ifdef POWER_GATING
always @ (negedge CLKIN or negedge RESETn_local)
begin
if (~RESETn_local)
begin
powerup_seq_fsm <= 0;
LRC_SLEEP <= `IO_HOLD;
LRC_CLKENB <= `IO_HOLD;
LRC_ISOLATE <= `IO_HOLD;
LRC_RESET <= `IO_HOLD;
SLEEP_REQUEST_TO_SLEEP_CTRL <= 0;
ext_int <= 0;
CLR_EXT_INT <= 0;
end
else
begin
if (CLR_EXT_INT & (~EXTERNAL_INT))
CLR_EXT_INT <= 0;
// master node should wake up layer controller "early"
if (((bus_state==BUS_ADDR)&&(MASTER_NODE==1'b0))||((bus_state==BUS_IDLE)&&(MASTER_NODE==1'b1)))
begin
if (EXTERNAL_INT)
begin
ext_int <= 1;
powerup_seq_fsm <= 1;
LRC_SLEEP <= `IO_RELEASE;
end
else
powerup_seq_fsm <= 0;
end
if (bus_state==BUS_CONTROL1)
ext_int <= 0;
if (ext_int)
begin
case (powerup_seq_fsm)
1: begin LRC_CLKENB <= `IO_RELEASE; CLR_EXT_INT <= 1; powerup_seq_fsm <= powerup_seq_fsm + 1'b1; end
2: begin LRC_ISOLATE <= `IO_RELEASE; powerup_seq_fsm <= powerup_seq_fsm + 1'b1; end
3: begin LRC_RESET <= `IO_RELEASE; powerup_seq_fsm <= powerup_seq_fsm + 1'b1; end
0: begin end
endcase
end
else
begin
case (bus_state)
BUS_DATA:
begin
case (powerup_seq_fsm)
0:
begin
// only check the wakeup_req after received broadcast command
// FSM stays at BUS_ADDR_ADDI for 2 cycles before entering BUS_DATA
// the complete command should received after `DATA_WIDTH (32) - `BROADCAST_CMD_WIDTH(4) + 2(2 BUS_ADDR_ADDI) - 1
if ((wakeup_req)&&(bit_position==`DATA_WIDTH-`BROADCAST_CMD_WIDTH+1))
begin
LRC_SLEEP <= `IO_RELEASE;
powerup_seq_fsm <= powerup_seq_fsm + 1'b1;
end
end
1:
begin
LRC_CLKENB <= `IO_RELEASE;
powerup_seq_fsm <= powerup_seq_fsm + 1'b1;
end
2:
begin
LRC_ISOLATE <= `IO_RELEASE;
powerup_seq_fsm <= powerup_seq_fsm + 1'b1;
end
3:
begin
LRC_RESET <= `IO_RELEASE;
end
endcase
end
BUS_CONTROL1:
begin
if (shutdown)
begin
SLEEP_REQUEST_TO_SLEEP_CTRL <= 1;
LRC_ISOLATE <= `IO_HOLD;
end
end
BUS_BACK_TO_IDLE:
begin
end
endcase
end
end
end
`endif
always @ (negedge CLKIN or negedge RESETn_local)
begin
if (~RESETn_local)
begin
out_reg_neg <= 1;
`ifdef POWER_GATING
if (MASTER_NODE==1'b1)
bus_state_neg <= BUS_IDLE;
else
bus_state_neg <= BUS_PRIO;
`else
bus_state_neg <= BUS_IDLE;
`endif
mode_neg <= MODE_RX;
end
else
begin
if (req_interrupt & BUS_INT)
bus_state_neg <= BUS_CONTROL0;
else
bus_state_neg <= bus_state;
mode_neg <= mode;
case (bus_state)
BUS_ADDR:
begin
if (mode==MODE_TX)
out_reg_neg <= addr_bit_extract;
end
BUS_DATA:
begin
if (mode==MODE_TX)
out_reg_neg <= data_bit_extract;
end
BUS_CONTROL0:
begin
if (req_interrupt)
begin
if (mode==MODE_TX)
begin
if (tx_underflow)
out_reg_neg <= ~CONTROL_BITS[1];
else
out_reg_neg <= CONTROL_BITS[1];
end
else
out_reg_neg <= ~CONTROL_BITS[1];
end
end
BUS_CONTROL1:
begin
out_reg_neg <= out_reg_pos;
end
endcase
end
end
always @ *
begin
DOUT = DIN;
case (bus_state_neg)
BUS_IDLE:
begin
DOUT = ((~TX_REQ) & DIN & enum_addr_resp[0]);
end
BUS_ARBITRATE:
begin
if (mode_neg==MODE_TX_NON_PRIO)
DOUT = 0;
end
BUS_PRIO:
begin
if (mode_neg==MODE_TX_NON_PRIO)
begin
if (TX_PRIORITY)
DOUT = 1;
else
DOUT = 0;
end
else if ((mode_neg==MODE_RX)&&(TX_PRIORITY & TX_REQ))
DOUT = 1;
end
BUS_ADDR:
begin
// Drive value only if interrupt is low
if (~BUS_INT &(mode_neg==MODE_TX))
DOUT = out_reg_neg;
end
BUS_DATA:
begin
// Drive value only if interrupt is low
if (~BUS_INT &(mode_neg==MODE_TX))
DOUT = out_reg_neg;
end
BUS_CONTROL0:
begin
if (req_interrupt)
DOUT = out_reg_neg;
end
BUS_CONTROL1:
begin
if (mode_neg==MODE_RX)
DOUT = out_reg_neg;
else if (req_interrupt)
DOUT = out_reg_neg;
end
BUS_BACK_TO_IDLE:
begin
DOUT = ((~TX_REQ) & DIN & enum_addr_resp[0]);
end
endcase
end
always @ *
begin
// forward clock once interrupt occurred
CLKOUT = CLKIN;
if ((bus_state==BUS_REQ_INTERRUPT)&&(~BUS_INT))
CLKOUT = 1;
end
mbus_swapper swapper0(
// inputs
.CLK(CLKIN),
.RESETn(RESETn_local),
.DATA(DIN),
.INT_FLAG_RESETn(BUS_INT_RSTn),
//Outputs
.LAST_CLK(),
.INT_FLAG(BUS_INT));
endmodule
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [15:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // ROMSEL from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
output r213f_enable,
output r2100_hit,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable,
output branch3_enable,
output gsu_enable
);
parameter [2:0]
//FEAT_DSPX = 0,
//FEAT_ST0010 = 1,
//FEAT_SRTC = 2,
FEAT_MSU1 = 3,
FEAT_213F = 4,
FEAT_2100 = 6
;
wire [23:0] SRAM_SNES_ADDR;
assign IS_ROM = ~SNES_ROMSEL;
assign IS_SAVERAM = SAVERAM_MASK[0]
& ( // 60-7D/E0-FF:0000-FFFF
( &SNES_ADDR[22:21]
& ~SNES_ROMSEL
)
// 00-3F/80-BF:6000-7FFF
| ( ~SNES_ADDR[22]
& ~SNES_ADDR[15]
& &SNES_ADDR[14:13]
)
);
assign IS_WRITABLE = IS_SAVERAM;
// GSU has a weird hybrid of Lo and Hi ROM formats.
// TODO: add programmable address map
assign SRAM_SNES_ADDR = (IS_SAVERAM
// 60-7D/E0-FF:0000-FFFF or 00-3F/80-BF:6000-7FFF (first 8K mirror)
? (24'hE00000 + ((SNES_ADDR[22] ? SNES_ADDR[16:0] : SNES_ADDR[12:0]) & SAVERAM_MASK))
// 40-5F/C0-DF:0000-FFFF or 00-3F/80-BF:8000-FFFF
: ((SNES_ADDR[22] ? {2'b00, SNES_ADDR[21:0]} : {2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}) & ROM_MASK)
);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_HIT = IS_ROM | IS_WRITABLE;
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign r2100_hit = (SNES_PA == 8'h00);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A6C);
assign branch1_enable = (SNES_ADDR == 24'h002A1F);
assign branch2_enable = (SNES_ADDR == 24'h002A59);
assign branch3_enable = (SNES_ADDR == 24'h002A5E);
// 00-3F/80-BF:3000-32FF gsu registers. TODO: some emulators go to $34FF???
assign gsu_enable = (!SNES_ADDR[22] && ({SNES_ADDR[15:10],2'h0} == 8'h30)) && (SNES_ADDR[9:8] != 2'h3);
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: linetest.v
// {{{
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: To test that the txuart and rxuart modules work properly, by
// buffering one line's worth of input, and then piping that line
// to the transmitter while (possibly) receiving a new line.
//
// With some modifications (discussed below), this RTL should be able to
// run as a top-level testing file, requiring only the transmit and receive
// UART pins and the clock to work.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2015-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License: GPL, v3, as defined and found on www.gnu.org,
// {{{
// http://www.gnu.org/licenses/gpl.html
//
////////////////////////////////////////////////////////////////////////////////
//
//
// One issue with the design is how to set the values of the setup register.
// (*This is a comment, not a verilator attribute ... ) Verilator needs to
// know/set those values in order to work. However, this design can also be
// used as a stand-alone top level configuration file. In this latter case,
// the setup register needs to be set internal to the file. Here, we use
// OPT_STANDALONE to distinguish between the two. If set, the file runs under
// (* Another comment still ...) Verilator and we need to get i_setup from the
// external environment. If not, it must be set internally.
// }}}
`ifndef VERILATOR
`define OPT_STANDALONE
`endif
// {{{
//
// Two versions of the UART can be found in the rtl directory: a full featured
// UART, and a LITE UART that only handles 8N1 -- no break sending, break
// detection, parity error detection, etc. If we set USE_LITE_UART here, those
// simplified UART modules will be used.
// }}}
// `define USE_LITE_UART
//
`default_nettype none
//
module linetest(
// {{{
input wire i_clk,
`ifndef OPT_STANDALONE
input wire [30:0] i_setup,
`endif
input i_uart_rx,
output wire o_uart_tx
// }}}
);
// Signal declarations
// {{{
reg [7:0] buffer [0:255];
reg [7:0] head, tail;
reg pwr_reset;
wire rx_stb, rx_break, rx_perr, rx_ferr;
/* verilator lint_off UNUSED */
wire rx_ignored;
/* verilator lint_on UNUSED */
wire [7:0] rx_data;
wire [7:0] nxt_head;
wire [7:0] nused;
reg [7:0] lineend;
reg run_tx;
wire tx_break, tx_busy;
reg [7:0] tx_data;
reg tx_stb;
wire cts_n;
// }}}
// i_setup
// {{{
// If i_setup isnt set up as an input parameter, it needs to be set.
// We do so here, to a setting appropriate to create a 115200 Baud
// comms system from a 100MHz clock. This also sets us to an 8-bit
// data word, 1-stop bit, and no parity.
`ifdef OPT_STANDALONE
wire [30:0] i_setup;
assign i_setup = 31'd868; // 115200 Baud, if clk @ 100MHz
`endif
// }}}
// pwr_reset
// {{{
// Create a reset line that will always be true on a power on reset
initial pwr_reset = 1'b1;
always @(posedge i_clk)
pwr_reset <= 1'b0;
// }}}
// The UART Receiver
// {{{
// This is where everything begins, by reading data from the UART.
//
// Data (rx_data) is present when rx_stb is true. Any parity or
// frame errors will also be valid at that time. Finally, we'll ignore
// errors, and even the clocked uart input distributed from here.
`ifdef USE_LITE_UART
rxuartlite #(24'd868)
receiver(i_clk, i_uart_rx, rx_stb, rx_data);
`else
rxuart receiver(i_clk, pwr_reset, i_setup, i_uart_rx, rx_stb, rx_data,
rx_break, rx_perr, rx_ferr, rx_ignored);
`endif
// }}}
// nxt_head, and write to the buffer
// {{{
// The next step in this process is to dump everything we read into a
// FIFO. First step: writing into the FIFO. Always write into FIFO
// memory. (The next step will step the memory address if rx_stb was
// true ...)
assign nxt_head = head + 8'h01;
always @(posedge i_clk)
buffer[head] <= rx_data;
// }}}
// head
// {{{
// Select where in our FIFO memory to write. On reset, we clear the
// memory. In all other cases/respects, we step the memory forward.
//
// However ... we won't step it forward IF ...
// rx_break - we are in a BREAK condition on the line
// (i.e. ... it's disconnected)
// rx_perr - We've seen a parity error
// rx_ferr - Same thing for a frame error
// nxt_head != tail - If the FIFO is already full, we'll just drop
// this new value, rather than dumping random garbage
// from the FIFO until we go round again ... i.e., we
// don't write on potential overflow.
//
// Adjusting this address will make certain that the next write to the
// FIFO goes to the next address--since we've already written the FIFO
// memory at this address.
initial head= 8'h00;
always @(posedge i_clk)
if (pwr_reset)
head <= 8'h00;
else if ((rx_stb)&&(!rx_break)&&(!rx_perr)&&(!rx_ferr)&&(nxt_head != tail))
head <= nxt_head;
// }}}
// How much of the FIFO is in use? head - tail. What if they wrap
// around? Still: head-tail, but this time truncated to the number of
// bits of interest. It can never be negative ... so ... we're good,
// this just measures that number.
assign nused = head-tail;
// run_tx, lineend
// {{{
// Here's the guts of the algorithm--setting run_tx. Once set, the
// buffer will flush. Here, we set it on one of two conditions: 1)
// a newline is received, or 2) the line is now longer than 80
// characters.
//
// Once the line has ben transmitted (separate from emptying the buffer)
// we stop transmitting.
initial run_tx = 0;
initial lineend = 0;
always @(posedge i_clk)
if (pwr_reset)
begin
run_tx <= 1'b0;
lineend <= 8'h00;
end else if(((rx_data == 8'h0a)||(rx_data == 8'hd))&&(rx_stb))
begin
// Start transmitting once we get to either a newline
// or a carriage return character
lineend <= head+8'h1;
run_tx <= 1'b1;
end else if ((!run_tx)&&(nused>8'd80))
begin
// Start transmitting once we get to 80 chars
lineend <= head;
run_tx <= 1'b1;
end else if (tail == lineend)
// Line buffer has been emptied
run_tx <= 1'b0;
// }}}
// UART transmitter
// {{{
// Now ... let's deal with the transmitter
assign tx_break = 1'b0;
// When do we wish to transmit?
//
// Any time run_tx is true--but we'll give it an extra clock.
initial tx_stb = 1'b0;
always @(posedge i_clk)
tx_stb <= run_tx;
// We'll transmit the data from our FIFO from ... wherever our tail
// is pointed.
always @(posedge i_clk)
tx_data <= buffer[tail];
// We increment the pointer to where we read from any time 1) we are
// requesting to transmit a character, and 2) the transmitter was not
// busy and thus accepted our request. At that time, increment the
// pointer, and we'll be ready for another round.
initial tail = 8'h00;
always @(posedge i_clk)
if(pwr_reset)
tail <= 8'h00;
else if ((tx_stb)&&(!tx_busy))
tail <= tail + 8'h01;
// Bypass any hardwaare flow control
assign cts_n = 1'b0;
`ifdef USE_LITE_UART
txuartlite #(24'd868)
transmitter(i_clk, tx_stb, tx_data, o_uart_tx, tx_busy);
`else
txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
tx_stb, tx_data, cts_n, o_uart_tx, tx_busy);
`endif
// }}}
endmodule
|
/*
* This file is part of the DSLogic-hdl project.
*
* Copyright (C) 2014 DreamSourceLab <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
`timescale 1ns/100ps
`define D #1
module trigger(
// -- clock & reset
input core_clk,
input core_rst,
// -- trigger configuration
input full_speed,
input trig_en,
input [3:0] trig_stages,
input [1:0] trig_mu,
input trig_mask_wr,
input trig_value_wr,
input trig_edge_wr,
input trig_count_wr,
input trig_logic_wr,
input [15:0] trig_mask,
input [15:0] trig_value,
input [15:0] trig_edge,
input [15:0] trig_count,
input [1:0] trig_logic,
input sample_en,
// -- sample data in
input sample_valid,
input [15:0] sample_data,
// -- control
input capture_done,
// -- trigger output
output [3:0] trig_dly,
output reg trig_hit = 1'b0
);
// --
// internal singals definition
// --
wire trig_hit_nxt;
// --
// trigger flag setting
// --
// --
// trigger hit
// --
wire trig_shift;
reg sample_en_1T;
reg sample_valid_1T = 1'b0;
reg sample_valid_2T = 1'b0;
reg edge_window = 1'b0;
wire edge_window_nxt;
reg [15:0] cur_trig_value0 = 16'b0;
reg [15:0] cur_trig_value1 = 16'b0;
reg [15:0] cur_trig_value2 = 16'b0;
reg [15:0] cur_trig_value3 = 16'b0;
reg [15:0] cur_trig_mask0 = 16'b0;
reg [15:0] cur_trig_mask1 = 16'b0;
reg [15:0] cur_trig_mask2 = 16'b0;
reg [15:0] cur_trig_mask3 = 16'b0;
reg [15:0] cur_trig_edge0 = 16'b0;
reg [15:0] cur_trig_edge1 = 16'b0;
reg [15:0] cur_trig_edge2 = 16'b0;
reg [15:0] cur_trig_edge3 = 16'b0;
reg [15:0] cur_trig_count0 = 16'b0;
reg [15:0] cur_trig_count1 = 16'b0;
reg [15:0] cur_trig_count2 = 16'b0;
reg [15:0] cur_trig_count3 = 16'b0;
reg cur_trig_and0 = 1'b1;
reg cur_trig_and1 = 1'b1;
reg cur_trig_and2 = 1'b1;
reg cur_trig_and3 = 1'b1;
reg cur_trig_inv0 = 1'b0;
reg cur_trig_inv1 = 1'b0;
reg cur_trig_inv2 = 1'b0;
reg cur_trig_inv3 = 1'b0;
wire [15:0] cur_trig_value0_nxt;
wire [15:0] cur_trig_value1_nxt;
wire [15:0] cur_trig_value2_nxt;
wire [15:0] cur_trig_value3_nxt;
wire [15:0] cur_trig_mask0_nxt;
wire [15:0] cur_trig_mask1_nxt;
wire [15:0] cur_trig_mask2_nxt;
wire [15:0] cur_trig_mask3_nxt;
wire [15:0] cur_trig_edge0_nxt;
wire [15:0] cur_trig_edge1_nxt;
wire [15:0] cur_trig_edge2_nxt;
wire [15:0] cur_trig_edge3_nxt;
wire [15:0] cur_trig_count0_nxt;
wire [15:0] cur_trig_count1_nxt;
wire [15:0] cur_trig_count2_nxt;
wire [15:0] cur_trig_count3_nxt;
wire cur_trig_and0_nxt;
wire cur_trig_and1_nxt;
wire cur_trig_and2_nxt;
wire cur_trig_and3_nxt;
wire cur_trig_inv0_nxt;
wire cur_trig_inv1_nxt;
wire cur_trig_inv2_nxt;
wire cur_trig_inv3_nxt;
reg cur_trig_count0_eq0 = 1'b0;
reg cur_trig_count1_eq0 = 1'b0;
reg cur_trig_count2_eq0 = 1'b0;
reg cur_trig_count3_eq0 = 1'b0;
wire cur_trig_count0_eq0_nxt;
wire cur_trig_count1_eq0_nxt;
wire cur_trig_count2_eq0_nxt;
wire cur_trig_count3_eq0_nxt;
reg mu0_match = 1'b0;
reg mu1_match = 1'b0;
reg mu2_match = 1'b0;
reg mu3_match = 1'b0;
wire mu0_match_nxt;
wire mu1_match_nxt;
wire mu2_match_nxt;
wire mu3_match_nxt;
wire mu0_match_count;
wire mu1_match_count;
wire mu2_match_count;
wire mu3_match_count;
reg mu_all_match = 1'b0;
wire mu_all_match_nxt;
reg [3:0] match_stages = 4'b0;
wire [3:0] match_stages_nxt;
reg match_stages_valid = 1'b0;
wire match_stages_valid_nxt;
reg [3:0] data_delay = 4'b0;
wire [3:0] data_delay_nxt;
wire [15:0] data_shift;
reg [15:0] cur_cmp_data = 16'b0;
wire [15:0] cur_cmp_data_nxt;
reg cur_cmp_valid = 1'b0;
reg [15:0] pre_cmp_data = 16'b0;
wire [15:0] pre_cmp_data_nxt;
wire [15:0] cur_edge;
wire [15:0] mu0mk_out;
wire [15:0] mu1mk_out;
wire [15:0] mu2mk_out;
wire [15:0] mu3mk_out;
wire [15:0] mu0_out;
wire [15:0] mu1_out;
wire [15:0] mu2_out;
wire [15:0] mu3_out;
wire [15:0] mu0eg_out;
wire [15:0] mu1eg_out;
wire [15:0] mu2eg_out;
wire [15:0] mu3eg_out;
wire [15:0] mu0ct_out;
wire [15:0] mu1ct_out;
wire [15:0] mu2ct_out;
wire [15:0] mu3ct_out;
wire [1:0] mu0lg_out;
wire [1:0] mu1lg_out;
wire [1:0] mu2lg_out;
wire [1:0] mu3lg_out;
wire mu0mk_shift = (trig_mask_wr & trig_mu == 2'b00) | trig_shift;
wire mu1mk_shift = (trig_mask_wr & trig_mu == 2'b01) | trig_shift;
wire mu2mk_shift = (trig_mask_wr & trig_mu == 2'b10) | trig_shift;
wire mu3mk_shift = (trig_mask_wr & trig_mu == 2'b11) | trig_shift;
wire [15:0] mu0mk_in = trig_shift ? mu0mk_out : trig_mask;
wire [15:0] mu1mk_in = trig_shift ? mu1mk_out : trig_mask;
wire [15:0] mu2mk_in = trig_shift ? mu2mk_out : trig_mask;
wire [15:0] mu3mk_in = trig_shift ? mu3mk_out : trig_mask;
wire mu0_shift = (trig_value_wr & trig_mu == 2'b00) | trig_shift;
wire mu1_shift = (trig_value_wr & trig_mu == 2'b01) | trig_shift;
wire mu2_shift = (trig_value_wr & trig_mu == 2'b10) | trig_shift;
wire mu3_shift = (trig_value_wr & trig_mu == 2'b11) | trig_shift;
wire [15:0] mu0_in = trig_shift ? mu0_out : trig_value;
wire [15:0] mu1_in = trig_shift ? mu1_out : trig_value;
wire [15:0] mu2_in = trig_shift ? mu2_out : trig_value;
wire [15:0] mu3_in = trig_shift ? mu3_out : trig_value;
wire mu0eg_shift = (trig_edge_wr & trig_mu == 2'b00) | trig_shift;
wire mu1eg_shift = (trig_edge_wr & trig_mu == 2'b01) | trig_shift;
wire mu2eg_shift = (trig_edge_wr & trig_mu == 2'b10) | trig_shift;
wire mu3eg_shift = (trig_edge_wr & trig_mu == 2'b11) | trig_shift;
wire [15:0] mu0eg_in = trig_shift ? mu0eg_out : trig_edge;
wire [15:0] mu1eg_in = trig_shift ? mu1eg_out : trig_edge;
wire [15:0] mu2eg_in = trig_shift ? mu2eg_out : trig_edge;
wire [15:0] mu3eg_in = trig_shift ? mu3eg_out : trig_edge;
wire mu0ct_shift = (trig_count_wr & trig_mu == 2'b00) | trig_shift;
wire mu1ct_shift = (trig_count_wr & trig_mu == 2'b01) | trig_shift;
wire mu2ct_shift = (trig_count_wr & trig_mu == 2'b10) | trig_shift;
wire mu3ct_shift = (trig_count_wr & trig_mu == 2'b11) | trig_shift;
wire [15:0] mu0ct_in = trig_shift ? mu0ct_out : trig_count;
wire [15:0] mu1ct_in = trig_shift ? mu1ct_out : trig_count;
wire [15:0] mu2ct_in = trig_shift ? mu2ct_out : trig_count;
wire [15:0] mu3ct_in = trig_shift ? mu3ct_out : trig_count;
wire mu0lg_shift = (trig_logic_wr & trig_mu == 2'b00) | trig_shift;
wire mu1lg_shift = (trig_logic_wr & trig_mu == 2'b01) | trig_shift;
wire mu2lg_shift = (trig_logic_wr & trig_mu == 2'b10) | trig_shift;
wire mu3lg_shift = (trig_logic_wr & trig_mu == 2'b11) | trig_shift;
wire [1:0] mu0lg_in = trig_shift ? mu0lg_out : trig_logic;
wire [1:0] mu1lg_in = trig_shift ? mu1lg_out : trig_logic;
wire [1:0] mu2lg_in = trig_shift ? mu2lg_out : trig_logic;
wire [1:0] mu3lg_in = trig_shift ? mu3lg_out : trig_logic;
assign trig_shift = (sample_en & ~sample_en_1T) | (sample_en & mu_all_match & ~trig_hit);
always @(posedge core_clk)
begin
sample_en_1T <= `D sample_en;
end
assign cur_trig_value0_nxt = (trig_shift) ? mu0_out : cur_trig_value0;
assign cur_trig_value1_nxt = (trig_shift) ? mu1_out : cur_trig_value1;
assign cur_trig_value2_nxt = (trig_shift) ? mu2_out : cur_trig_value2;
assign cur_trig_value3_nxt = (trig_shift) ? mu3_out : cur_trig_value3;
assign cur_trig_mask0_nxt = (trig_shift) ? mu0mk_out : cur_trig_mask0;
assign cur_trig_mask1_nxt = (trig_shift) ? mu1mk_out : cur_trig_mask1;
assign cur_trig_mask2_nxt = (trig_shift) ? mu2mk_out : cur_trig_mask2;
assign cur_trig_mask3_nxt = (trig_shift) ? mu3mk_out : cur_trig_mask3;
assign cur_trig_edge0_nxt = (trig_shift) ? mu0eg_out : cur_trig_edge0;
assign cur_trig_edge1_nxt = (trig_shift) ? mu1eg_out : cur_trig_edge1;
assign cur_trig_edge2_nxt = (trig_shift) ? mu2eg_out : cur_trig_edge2;
assign cur_trig_edge3_nxt = (trig_shift) ? mu3eg_out : cur_trig_edge3;
assign cur_trig_count0_nxt = (trig_shift) ? mu0ct_out :
(mu0_match & cur_trig_count0 != 'b0) ? cur_trig_count0 - 1'b1 : cur_trig_count0;
assign cur_trig_count1_nxt = (trig_shift) ? mu1ct_out :
(mu1_match & cur_trig_count1 != 'b0) ? cur_trig_count1 - 1'b1 : cur_trig_count1;
assign cur_trig_count2_nxt = (trig_shift) ? mu2ct_out :
(mu2_match & cur_trig_count2 != 'b0) ? cur_trig_count2 - 1'b1 : cur_trig_count2;
assign cur_trig_count3_nxt = (trig_shift) ? mu3ct_out :
(mu3_match & cur_trig_count3 != 'b0) ? cur_trig_count3 - 1'b1 : cur_trig_count3;
assign cur_trig_count0_eq0_nxt = (cur_trig_count0_nxt == 'b0);
assign cur_trig_count1_eq0_nxt = (cur_trig_count1_nxt == 'b0);
assign cur_trig_count2_eq0_nxt = (cur_trig_count2_nxt == 'b0);
assign cur_trig_count3_eq0_nxt = (cur_trig_count3_nxt == 'b0);
assign cur_trig_and0_nxt = (trig_shift) ? mu0lg_out[1] : cur_trig_and0;
assign cur_trig_and1_nxt = (trig_shift) ? mu1lg_out[1] : cur_trig_and1;
assign cur_trig_and2_nxt = (trig_shift) ? mu2lg_out[1] : cur_trig_and2;
assign cur_trig_and3_nxt = (trig_shift) ? mu3lg_out[1] : cur_trig_and3;
assign cur_trig_inv0_nxt = (trig_shift) ? mu0lg_out[0] : cur_trig_inv0;
assign cur_trig_inv1_nxt = (trig_shift) ? mu1lg_out[0] : cur_trig_inv1;
assign cur_trig_inv2_nxt = (trig_shift) ? mu2lg_out[0] : cur_trig_inv2;
assign cur_trig_inv3_nxt = (trig_shift) ? mu3lg_out[0] : cur_trig_inv3;
always @(posedge core_clk)
begin
if (trig_en) begin
cur_trig_value0 <= `D cur_trig_value0_nxt;
cur_trig_value1 <= `D cur_trig_value1_nxt;
cur_trig_value2 <= `D cur_trig_value2_nxt;
cur_trig_value3 <= `D cur_trig_value3_nxt;
cur_trig_mask0 <= `D cur_trig_mask0_nxt;
cur_trig_mask1 <= `D cur_trig_mask1_nxt;
cur_trig_mask2 <= `D cur_trig_mask2_nxt;
cur_trig_mask3 <= `D cur_trig_mask3_nxt;
cur_trig_edge0 <= `D cur_trig_edge0_nxt;
cur_trig_edge1 <= `D cur_trig_edge1_nxt;
cur_trig_edge2 <= `D cur_trig_edge2_nxt;
cur_trig_edge3 <= `D cur_trig_edge3_nxt;
cur_trig_count0 <= `D cur_trig_count0_nxt;
cur_trig_count1 <= `D cur_trig_count1_nxt;
cur_trig_count2 <= `D cur_trig_count2_nxt;
cur_trig_count3 <= `D cur_trig_count3_nxt;
cur_trig_count0_eq0 <= `D cur_trig_count0_eq0_nxt;
cur_trig_count1_eq0 <= `D cur_trig_count1_eq0_nxt;
cur_trig_count2_eq0 <= `D cur_trig_count2_eq0_nxt;
cur_trig_count3_eq0 <= `D cur_trig_count3_eq0_nxt;
cur_trig_and0 <= `D cur_trig_and0_nxt;
cur_trig_and1 <= `D cur_trig_and1_nxt;
cur_trig_and2 <= `D cur_trig_and2_nxt;
cur_trig_and3 <= `D cur_trig_and3_nxt;
cur_trig_inv0 <= `D cur_trig_inv0_nxt;
cur_trig_inv1 <= `D cur_trig_inv1_nxt;
cur_trig_inv2 <= `D cur_trig_inv2_nxt;
cur_trig_inv3 <= `D cur_trig_inv3_nxt;
end
end
assign cur_edge = {16{edge_window}} & (cur_cmp_data ^ pre_cmp_data);
//assign mu0_match_nxt = cur_trig_inv0 ^ (~|(((cur_cmp_data ^ cur_trig_value0) | (cur_trig_edge0 & ~cur_edge)) & ~cur_trig_mask0) & cur_cmp_valid);
//assign mu1_match_nxt = cur_trig_inv1 ^ (~|(((cur_cmp_data ^ cur_trig_value1) | (cur_trig_edge1 & ~cur_edge)) & ~cur_trig_mask1) & cur_cmp_valid);
//assign mu2_match_nxt = cur_trig_inv2 ^ (~|(((cur_cmp_data ^ cur_trig_value2) | (cur_trig_edge2 & ~cur_edge)) & ~cur_trig_mask2) & cur_cmp_valid);
//assign mu3_match_nxt = cur_trig_inv3 ^ (~|(((cur_cmp_data ^ cur_trig_value3) | (cur_trig_edge3 & ~cur_edge)) & ~cur_trig_mask3) & cur_cmp_valid);
assign mu0_match_nxt = cur_trig_inv0 ^ (~|(((cur_cmp_data ^ cur_trig_value0) & ~cur_trig_mask0) | (cur_trig_edge0 & ~cur_edge)) & cur_cmp_valid);
assign mu1_match_nxt = cur_trig_inv1 ^ (~|(((cur_cmp_data ^ cur_trig_value1) & ~cur_trig_mask1) | (cur_trig_edge1 & ~cur_edge)) & cur_cmp_valid);
assign mu2_match_nxt = cur_trig_inv2 ^ (~|(((cur_cmp_data ^ cur_trig_value2) & ~cur_trig_mask2) | (cur_trig_edge2 & ~cur_edge)) & cur_cmp_valid);
assign mu3_match_nxt = cur_trig_inv3 ^ (~|(((cur_cmp_data ^ cur_trig_value3) & ~cur_trig_mask3) | (cur_trig_edge3 & ~cur_edge)) & cur_cmp_valid);
//assign mu0_match_nxt = cur_trig_inv0 ^ (~|(((cur_cmp_data ^ cur_trig_value0)) & ~cur_trig_mask0) & cur_cmp_valid);
//assign mu1_match_nxt = cur_trig_inv1 ^ (~|(((cur_cmp_data ^ cur_trig_value1)) & ~cur_trig_mask1) & cur_cmp_valid);
//assign mu2_match_nxt = cur_trig_inv2 ^ (~|(((cur_cmp_data ^ cur_trig_value2)) & ~cur_trig_mask2) & cur_cmp_valid);
//assign mu3_match_nxt = cur_trig_inv3 ^ (~|(((cur_cmp_data ^ cur_trig_value3)) & ~cur_trig_mask3) & cur_cmp_valid);
always @(posedge core_clk)
begin
mu0_match <= `D mu0_match_nxt;
mu1_match <= `D mu1_match_nxt;
mu2_match <= `D mu2_match_nxt;
mu3_match <= `D mu3_match_nxt;
end
assign mu0_match_count = mu0_match_nxt & (cur_trig_count0 == 'b0);
assign mu1_match_count = mu1_match_nxt & (cur_trig_count1 == 'b0);
assign mu2_match_count = mu2_match_nxt & (cur_trig_count2 == 'b0);
assign mu3_match_count = mu3_match_nxt & (cur_trig_count3 == 'b0);
//assign mu_all_match_nxt = cur_trig_and0 ? (mu0_match_count & mu1_match_count & mu2_match_count & mu3_match_count) :
// (mu0_match_count | mu1_match_count | mu2_match_count | mu3_match_count);
assign mu_all_match_nxt = cur_trig_and0 ? (mu0_match_count & mu1_match_count) :
(mu0_match_count | mu1_match_count);
//assign mu_all_match_nxt = cur_trig_and0 ? (mu0_match_nxt & mu1_match_nxt & mu2_match_nxt & mu3_match_nxt) :
// (mu0_match_nxt | mu1_match_nxt | mu2_match_nxt | mu3_match_nxt);
always @(posedge core_clk)
begin
mu_all_match <= `D mu_all_match_nxt;
end
assign data_delay_nxt = (sample_en & ~sample_en_1T) ? 4'b0 :
(full_speed & mu_all_match_nxt) ? data_delay + 1'b1 : data_delay;
always @(posedge core_clk)
begin
data_delay <= `D data_delay_nxt;
end
assign match_stages_valid_nxt = (~sample_en & sample_en_1T) ? 1'b0 :
mu_all_match & sample_en ? 1'b1 : match_stages_valid;
assign match_stages_nxt = (sample_en & ~sample_en_1T) ? 4'b0 :
(mu_all_match & match_stages_valid) ? match_stages + 1'b1 : match_stages;
always @(posedge core_clk)
begin
match_stages_valid <= `D match_stages_valid_nxt;
match_stages <= `D match_stages_nxt;
end
assign trig_hit_nxt = (~sample_en & sample_en_1T) ? 1'b0 :
(sample_en & ~sample_en_1T & ~trig_en) ? 1'b1 :
(sample_en & match_stages_valid & (match_stages == trig_stages)) ? 1'b1 : trig_hit;
always @(posedge core_clk)
begin
trig_hit <= `D trig_hit_nxt;
end
// --
// trigger delay clock count
// --
assign trig_dly = full_speed ? trig_stages : 4'b0;
// --
// data shift
// --
assign cur_cmp_data_nxt = sample_valid_1T ? data_shift : cur_cmp_data;
assign pre_cmp_data_nxt = (sample_valid_2T & ~(full_speed & mu_all_match))? cur_cmp_data : pre_cmp_data;
assign edge_window_nxt = (sample_en & ~sample_en_1T) ? 1'b0 :
sample_valid_2T ? 1'b1 : edge_window;
always @(posedge core_clk)
begin
sample_valid_1T <= `D sample_valid;
sample_valid_2T <= `D sample_valid_1T;
edge_window <= `D edge_window_nxt;
cur_cmp_valid <= `D sample_valid_1T;
cur_cmp_data <= `D cur_cmp_data_nxt;
pre_cmp_data <= `D pre_cmp_data_nxt;
end
SRL16E data00(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[0]), .Q(data_shift[0]));
SRL16E data01(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[1]), .Q(data_shift[1]));
SRL16E data02(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[2]), .Q(data_shift[2]));
SRL16E data03(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[3]), .Q(data_shift[3]));
SRL16E data04(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[4]), .Q(data_shift[4]));
SRL16E data05(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[5]), .Q(data_shift[5]));
SRL16E data06(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[6]), .Q(data_shift[6]));
SRL16E data07(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[7]), .Q(data_shift[7]));
SRL16E data08(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[8]), .Q(data_shift[8]));
SRL16E data09(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[9]), .Q(data_shift[9]));
SRL16E data10(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[10]), .Q(data_shift[10]));
SRL16E data11(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[11]), .Q(data_shift[11]));
SRL16E data12(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[12]), .Q(data_shift[12]));
SRL16E data13(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[13]), .Q(data_shift[13]));
SRL16E data14(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[14]), .Q(data_shift[14]));
SRL16E data15(.A0(data_delay[0]), .A1(data_delay[1]), .A2(data_delay[2]), .A3(data_delay[3]), .CLK(core_clk), .CE(sample_valid), .D(sample_data[15]), .Q(data_shift[15]));
// --
// Match Units 16stages*4sets
// --
// -- Match Unit 0
SRL16E mu0mk00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[0]), .Q(mu0mk_out[0]));
SRL16E mu0mk01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[1]), .Q(mu0mk_out[1]));
SRL16E mu0mk02(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[2]), .Q(mu0mk_out[2]));
SRL16E mu0mk03(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[3]), .Q(mu0mk_out[3]));
SRL16E mu0mk04(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[4]), .Q(mu0mk_out[4]));
SRL16E mu0mk05(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[5]), .Q(mu0mk_out[5]));
SRL16E mu0mk06(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[6]), .Q(mu0mk_out[6]));
SRL16E mu0mk07(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[7]), .Q(mu0mk_out[7]));
SRL16E mu0mk08(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[8]), .Q(mu0mk_out[8]));
SRL16E mu0mk09(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[9]), .Q(mu0mk_out[9]));
SRL16E mu0mk10(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[10]), .Q(mu0mk_out[10]));
SRL16E mu0mk11(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[11]), .Q(mu0mk_out[11]));
SRL16E mu0mk12(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[12]), .Q(mu0mk_out[12]));
SRL16E mu0mk13(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[13]), .Q(mu0mk_out[13]));
SRL16E mu0mk14(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[14]), .Q(mu0mk_out[14]));
SRL16E mu0mk15(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0mk_shift), .D(mu0mk_in[15]), .Q(mu0mk_out[15]));
SRL16E mu0eg00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[0]), .Q(mu0eg_out[0]));
SRL16E mu0eg01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[1]), .Q(mu0eg_out[1]));
SRL16E mu0eg02(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[2]), .Q(mu0eg_out[2]));
SRL16E mu0eg03(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[3]), .Q(mu0eg_out[3]));
SRL16E mu0eg04(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[4]), .Q(mu0eg_out[4]));
SRL16E mu0eg05(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[5]), .Q(mu0eg_out[5]));
SRL16E mu0eg06(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[6]), .Q(mu0eg_out[6]));
SRL16E mu0eg07(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[7]), .Q(mu0eg_out[7]));
SRL16E mu0eg08(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[8]), .Q(mu0eg_out[8]));
SRL16E mu0eg09(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[9]), .Q(mu0eg_out[9]));
SRL16E mu0eg10(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[10]), .Q(mu0eg_out[10]));
SRL16E mu0eg11(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[11]), .Q(mu0eg_out[11]));
SRL16E mu0eg12(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[12]), .Q(mu0eg_out[12]));
SRL16E mu0eg13(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[13]), .Q(mu0eg_out[13]));
SRL16E mu0eg14(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[14]), .Q(mu0eg_out[14]));
SRL16E mu0eg15(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0eg_shift), .D(mu0eg_in[15]), .Q(mu0eg_out[15]));
SRL16E mu0ct00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[0]), .Q(mu0ct_out[0]));
SRL16E mu0ct01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[1]), .Q(mu0ct_out[1]));
SRL16E mu0ct02(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[2]), .Q(mu0ct_out[2]));
SRL16E mu0ct03(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[3]), .Q(mu0ct_out[3]));
SRL16E mu0ct04(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[4]), .Q(mu0ct_out[4]));
SRL16E mu0ct05(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[5]), .Q(mu0ct_out[5]));
SRL16E mu0ct06(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[6]), .Q(mu0ct_out[6]));
SRL16E mu0ct07(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[7]), .Q(mu0ct_out[7]));
SRL16E mu0ct08(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[8]), .Q(mu0ct_out[8]));
SRL16E mu0ct09(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[9]), .Q(mu0ct_out[9]));
SRL16E mu0ct10(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[10]), .Q(mu0ct_out[10]));
SRL16E mu0ct11(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[11]), .Q(mu0ct_out[11]));
SRL16E mu0ct12(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[12]), .Q(mu0ct_out[12]));
SRL16E mu0ct13(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[13]), .Q(mu0ct_out[13]));
SRL16E mu0ct14(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[14]), .Q(mu0ct_out[14]));
SRL16E mu0ct15(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0ct_shift), .D(mu0ct_in[15]), .Q(mu0ct_out[15]));
SRL16E mu000(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[0]), .Q(mu0_out[0]));
SRL16E mu001(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[1]), .Q(mu0_out[1]));
SRL16E mu002(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[2]), .Q(mu0_out[2]));
SRL16E mu003(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[3]), .Q(mu0_out[3]));
SRL16E mu004(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[4]), .Q(mu0_out[4]));
SRL16E mu005(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[5]), .Q(mu0_out[5]));
SRL16E mu006(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[6]), .Q(mu0_out[6]));
SRL16E mu007(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[7]), .Q(mu0_out[7]));
SRL16E mu008(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[8]), .Q(mu0_out[8]));
SRL16E mu009(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[9]), .Q(mu0_out[9]));
SRL16E mu010(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[10]), .Q(mu0_out[10]));
SRL16E mu011(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[11]), .Q(mu0_out[11]));
SRL16E mu012(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[12]), .Q(mu0_out[12]));
SRL16E mu013(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[13]), .Q(mu0_out[13]));
SRL16E mu014(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[14]), .Q(mu0_out[14]));
SRL16E mu015(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0_shift), .D(mu0_in[15]), .Q(mu0_out[15]));
SRL16E mu0lg00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0lg_shift), .D(mu0lg_in[0]), .Q(mu0lg_out[0]));
SRL16E mu0lg01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu0lg_shift), .D(mu0lg_in[1]), .Q(mu0lg_out[1]));
// -- Match Unit 1
SRL16E mu1mk00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[0]), .Q(mu1mk_out[0]));
SRL16E mu1mk01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[1]), .Q(mu1mk_out[1]));
SRL16E mu1mk02(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[2]), .Q(mu1mk_out[2]));
SRL16E mu1mk03(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[3]), .Q(mu1mk_out[3]));
SRL16E mu1mk04(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[4]), .Q(mu1mk_out[4]));
SRL16E mu1mk05(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[5]), .Q(mu1mk_out[5]));
SRL16E mu1mk06(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[6]), .Q(mu1mk_out[6]));
SRL16E mu1mk07(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[7]), .Q(mu1mk_out[7]));
SRL16E mu1mk08(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[8]), .Q(mu1mk_out[8]));
SRL16E mu1mk09(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[9]), .Q(mu1mk_out[9]));
SRL16E mu1mk10(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[10]), .Q(mu1mk_out[10]));
SRL16E mu1mk11(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[11]), .Q(mu1mk_out[11]));
SRL16E mu1mk12(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[12]), .Q(mu1mk_out[12]));
SRL16E mu1mk13(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[13]), .Q(mu1mk_out[13]));
SRL16E mu1mk14(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[14]), .Q(mu1mk_out[14]));
SRL16E mu1mk15(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1mk_shift), .D(mu1mk_in[15]), .Q(mu1mk_out[15]));
SRL16E mu1eg00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[0]), .Q(mu1eg_out[0]));
SRL16E mu1eg01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[1]), .Q(mu1eg_out[1]));
SRL16E mu1eg02(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[2]), .Q(mu1eg_out[2]));
SRL16E mu1eg03(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[3]), .Q(mu1eg_out[3]));
SRL16E mu1eg04(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[4]), .Q(mu1eg_out[4]));
SRL16E mu1eg05(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[5]), .Q(mu1eg_out[5]));
SRL16E mu1eg06(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[6]), .Q(mu1eg_out[6]));
SRL16E mu1eg07(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[7]), .Q(mu1eg_out[7]));
SRL16E mu1eg08(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[8]), .Q(mu1eg_out[8]));
SRL16E mu1eg09(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[9]), .Q(mu1eg_out[9]));
SRL16E mu1eg10(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[10]), .Q(mu1eg_out[10]));
SRL16E mu1eg11(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[11]), .Q(mu1eg_out[11]));
SRL16E mu1eg12(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[12]), .Q(mu1eg_out[12]));
SRL16E mu1eg13(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[13]), .Q(mu1eg_out[13]));
SRL16E mu1eg14(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[14]), .Q(mu1eg_out[14]));
SRL16E mu1eg15(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1eg_shift), .D(mu1eg_in[15]), .Q(mu1eg_out[15]));
SRL16E mu1ct00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[0]), .Q(mu1ct_out[0]));
SRL16E mu1ct01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[1]), .Q(mu1ct_out[1]));
SRL16E mu1ct02(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[2]), .Q(mu1ct_out[2]));
SRL16E mu1ct03(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[3]), .Q(mu1ct_out[3]));
SRL16E mu1ct04(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[4]), .Q(mu1ct_out[4]));
SRL16E mu1ct05(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[5]), .Q(mu1ct_out[5]));
SRL16E mu1ct06(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[6]), .Q(mu1ct_out[6]));
SRL16E mu1ct07(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[7]), .Q(mu1ct_out[7]));
SRL16E mu1ct08(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[8]), .Q(mu1ct_out[8]));
SRL16E mu1ct09(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[9]), .Q(mu1ct_out[9]));
SRL16E mu1ct10(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[10]), .Q(mu1ct_out[10]));
SRL16E mu1ct11(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[11]), .Q(mu1ct_out[11]));
SRL16E mu1ct12(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[12]), .Q(mu1ct_out[12]));
SRL16E mu1ct13(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[13]), .Q(mu1ct_out[13]));
SRL16E mu1ct14(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[14]), .Q(mu1ct_out[14]));
SRL16E mu1ct15(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1ct_shift), .D(mu1ct_in[15]), .Q(mu1ct_out[15]));
SRL16E mu100(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[0]), .Q(mu1_out[0]));
SRL16E mu101(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[1]), .Q(mu1_out[1]));
SRL16E mu102(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[2]), .Q(mu1_out[2]));
SRL16E mu103(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[3]), .Q(mu1_out[3]));
SRL16E mu104(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[4]), .Q(mu1_out[4]));
SRL16E mu105(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[5]), .Q(mu1_out[5]));
SRL16E mu106(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[6]), .Q(mu1_out[6]));
SRL16E mu107(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[7]), .Q(mu1_out[7]));
SRL16E mu108(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[8]), .Q(mu1_out[8]));
SRL16E mu109(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[9]), .Q(mu1_out[9]));
SRL16E mu110(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[10]), .Q(mu1_out[10]));
SRL16E mu111(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[11]), .Q(mu1_out[11]));
SRL16E mu112(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[12]), .Q(mu1_out[12]));
SRL16E mu113(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[13]), .Q(mu1_out[13]));
SRL16E mu114(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[14]), .Q(mu1_out[14]));
SRL16E mu115(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1_shift), .D(mu1_in[15]), .Q(mu1_out[15]));
SRL16E mu1lg00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1lg_shift), .D(mu1lg_in[0]), .Q(mu1lg_out[0]));
SRL16E mu1lg01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu1lg_shift), .D(mu1lg_in[1]), .Q(mu1lg_out[1]));
// -- Match Unit 2
SRL16E mu2mk00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[0]), .Q(mu2mk_out[0]));
SRL16E mu2mk01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[1]), .Q(mu2mk_out[1]));
SRL16E mu2mk02(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[2]), .Q(mu2mk_out[2]));
SRL16E mu2mk03(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[3]), .Q(mu2mk_out[3]));
SRL16E mu2mk04(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[4]), .Q(mu2mk_out[4]));
SRL16E mu2mk05(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[5]), .Q(mu2mk_out[5]));
SRL16E mu2mk06(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[6]), .Q(mu2mk_out[6]));
SRL16E mu2mk07(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[7]), .Q(mu2mk_out[7]));
SRL16E mu2mk08(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[8]), .Q(mu2mk_out[8]));
SRL16E mu2mk09(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[9]), .Q(mu2mk_out[9]));
SRL16E mu2mk10(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[10]), .Q(mu2mk_out[10]));
SRL16E mu2mk11(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[11]), .Q(mu2mk_out[11]));
SRL16E mu2mk12(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[12]), .Q(mu2mk_out[12]));
SRL16E mu2mk13(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[13]), .Q(mu2mk_out[13]));
SRL16E mu2mk14(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[14]), .Q(mu2mk_out[14]));
SRL16E mu2mk15(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2mk_shift), .D(mu2mk_in[15]), .Q(mu2mk_out[15]));
SRL16E mu2eg00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[0]), .Q(mu2eg_out[0]));
SRL16E mu2eg01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[1]), .Q(mu2eg_out[1]));
SRL16E mu2eg02(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[2]), .Q(mu2eg_out[2]));
SRL16E mu2eg03(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[3]), .Q(mu2eg_out[3]));
SRL16E mu2eg04(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[4]), .Q(mu2eg_out[4]));
SRL16E mu2eg05(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[5]), .Q(mu2eg_out[5]));
SRL16E mu2eg06(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[6]), .Q(mu2eg_out[6]));
SRL16E mu2eg07(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[7]), .Q(mu2eg_out[7]));
SRL16E mu2eg08(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[8]), .Q(mu2eg_out[8]));
SRL16E mu2eg09(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[9]), .Q(mu2eg_out[9]));
SRL16E mu2eg10(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[10]), .Q(mu2eg_out[10]));
SRL16E mu2eg11(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[11]), .Q(mu2eg_out[11]));
SRL16E mu2eg12(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[12]), .Q(mu2eg_out[12]));
SRL16E mu2eg13(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[13]), .Q(mu2eg_out[13]));
SRL16E mu2eg14(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[14]), .Q(mu2eg_out[14]));
SRL16E mu2eg15(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2eg_shift), .D(mu2eg_in[15]), .Q(mu2eg_out[15]));
SRL16E mu2ct00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[0]), .Q(mu2ct_out[0]));
SRL16E mu2ct01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[1]), .Q(mu2ct_out[1]));
SRL16E mu2ct02(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[2]), .Q(mu2ct_out[2]));
SRL16E mu2ct03(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[3]), .Q(mu2ct_out[3]));
SRL16E mu2ct04(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[4]), .Q(mu2ct_out[4]));
SRL16E mu2ct05(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[5]), .Q(mu2ct_out[5]));
SRL16E mu2ct06(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[6]), .Q(mu2ct_out[6]));
SRL16E mu2ct07(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[7]), .Q(mu2ct_out[7]));
SRL16E mu2ct08(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[8]), .Q(mu2ct_out[8]));
SRL16E mu2ct09(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[9]), .Q(mu2ct_out[9]));
SRL16E mu2ct10(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[10]), .Q(mu2ct_out[10]));
SRL16E mu2ct11(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[11]), .Q(mu2ct_out[11]));
SRL16E mu2ct12(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[12]), .Q(mu2ct_out[12]));
SRL16E mu2ct13(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[13]), .Q(mu2ct_out[13]));
SRL16E mu2ct14(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[14]), .Q(mu2ct_out[14]));
SRL16E mu2ct15(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2ct_shift), .D(mu2ct_in[15]), .Q(mu2ct_out[15]));
SRL16E mu200(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[0]), .Q(mu2_out[0]));
SRL16E mu201(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[1]), .Q(mu2_out[1]));
SRL16E mu202(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[2]), .Q(mu2_out[2]));
SRL16E mu203(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[3]), .Q(mu2_out[3]));
SRL16E mu204(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[4]), .Q(mu2_out[4]));
SRL16E mu205(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[5]), .Q(mu2_out[5]));
SRL16E mu206(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[6]), .Q(mu2_out[6]));
SRL16E mu207(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[7]), .Q(mu2_out[7]));
SRL16E mu208(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[8]), .Q(mu2_out[8]));
SRL16E mu209(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[9]), .Q(mu2_out[9]));
SRL16E mu210(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[10]), .Q(mu2_out[10]));
SRL16E mu211(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[11]), .Q(mu2_out[11]));
SRL16E mu212(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[12]), .Q(mu2_out[12]));
SRL16E mu213(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[13]), .Q(mu2_out[13]));
SRL16E mu214(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[14]), .Q(mu2_out[14]));
SRL16E mu215(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2_shift), .D(mu2_in[15]), .Q(mu2_out[15]));
SRL16E mu2lg00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2lg_shift), .D(mu2lg_in[0]), .Q(mu2lg_out[0]));
SRL16E mu2lg01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu2lg_shift), .D(mu2lg_in[1]), .Q(mu2lg_out[1]));
// -- Match Unit 3
SRL16E mu3mk00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[0]), .Q(mu3mk_out[0]));
SRL16E mu3mk01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[1]), .Q(mu3mk_out[1]));
SRL16E mu3mk02(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[2]), .Q(mu3mk_out[2]));
SRL16E mu3mk03(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[3]), .Q(mu3mk_out[3]));
SRL16E mu3mk04(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[4]), .Q(mu3mk_out[4]));
SRL16E mu3mk05(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[5]), .Q(mu3mk_out[5]));
SRL16E mu3mk06(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[6]), .Q(mu3mk_out[6]));
SRL16E mu3mk07(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[7]), .Q(mu3mk_out[7]));
SRL16E mu3mk08(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[8]), .Q(mu3mk_out[8]));
SRL16E mu3mk09(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[9]), .Q(mu3mk_out[9]));
SRL16E mu3mk10(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[10]), .Q(mu3mk_out[10]));
SRL16E mu3mk11(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[11]), .Q(mu3mk_out[11]));
SRL16E mu3mk12(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[12]), .Q(mu3mk_out[12]));
SRL16E mu3mk13(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[13]), .Q(mu3mk_out[13]));
SRL16E mu3mk14(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[14]), .Q(mu3mk_out[14]));
SRL16E mu3mk15(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3mk_shift), .D(mu3mk_in[15]), .Q(mu3mk_out[15]));
SRL16E mu3eg00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[0]), .Q(mu3eg_out[0]));
SRL16E mu3eg01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[1]), .Q(mu3eg_out[1]));
SRL16E mu3eg02(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[2]), .Q(mu3eg_out[2]));
SRL16E mu3eg03(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[3]), .Q(mu3eg_out[3]));
SRL16E mu3eg04(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[4]), .Q(mu3eg_out[4]));
SRL16E mu3eg05(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[5]), .Q(mu3eg_out[5]));
SRL16E mu3eg06(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[6]), .Q(mu3eg_out[6]));
SRL16E mu3eg07(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[7]), .Q(mu3eg_out[7]));
SRL16E mu3eg08(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[8]), .Q(mu3eg_out[8]));
SRL16E mu3eg09(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[9]), .Q(mu3eg_out[9]));
SRL16E mu3eg10(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[10]), .Q(mu3eg_out[10]));
SRL16E mu3eg11(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[11]), .Q(mu3eg_out[11]));
SRL16E mu3eg12(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[12]), .Q(mu3eg_out[12]));
SRL16E mu3eg13(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[13]), .Q(mu3eg_out[13]));
SRL16E mu3eg14(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[14]), .Q(mu3eg_out[14]));
SRL16E mu3eg15(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3eg_shift), .D(mu3eg_in[15]), .Q(mu3eg_out[15]));
SRL16E mu3ct00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[0]), .Q(mu3ct_out[0]));
SRL16E mu3ct01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[1]), .Q(mu3ct_out[1]));
SRL16E mu3ct02(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[2]), .Q(mu3ct_out[2]));
SRL16E mu3ct03(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[3]), .Q(mu3ct_out[3]));
SRL16E mu3ct04(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[4]), .Q(mu3ct_out[4]));
SRL16E mu3ct05(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[5]), .Q(mu3ct_out[5]));
SRL16E mu3ct06(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[6]), .Q(mu3ct_out[6]));
SRL16E mu3ct07(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[7]), .Q(mu3ct_out[7]));
SRL16E mu3ct08(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[8]), .Q(mu3ct_out[8]));
SRL16E mu3ct09(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[9]), .Q(mu3ct_out[9]));
SRL16E mu3ct10(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[10]), .Q(mu3ct_out[10]));
SRL16E mu3ct11(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[11]), .Q(mu3ct_out[11]));
SRL16E mu3ct12(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[12]), .Q(mu3ct_out[12]));
SRL16E mu3ct13(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[13]), .Q(mu3ct_out[13]));
SRL16E mu3ct14(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[14]), .Q(mu3ct_out[14]));
SRL16E mu3ct15(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3ct_shift), .D(mu3ct_in[15]), .Q(mu3ct_out[15]));
SRL16E mu300(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[0]), .Q(mu3_out[0]));
SRL16E mu301(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[1]), .Q(mu3_out[1]));
SRL16E mu302(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[2]), .Q(mu3_out[2]));
SRL16E mu303(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[3]), .Q(mu3_out[3]));
SRL16E mu304(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[4]), .Q(mu3_out[4]));
SRL16E mu305(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[5]), .Q(mu3_out[5]));
SRL16E mu306(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[6]), .Q(mu3_out[6]));
SRL16E mu307(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[7]), .Q(mu3_out[7]));
SRL16E mu308(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[8]), .Q(mu3_out[8]));
SRL16E mu309(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[9]), .Q(mu3_out[9]));
SRL16E mu310(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[10]), .Q(mu3_out[10]));
SRL16E mu311(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[11]), .Q(mu3_out[11]));
SRL16E mu312(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[12]), .Q(mu3_out[12]));
SRL16E mu313(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[13]), .Q(mu3_out[13]));
SRL16E mu314(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[14]), .Q(mu3_out[14]));
SRL16E mu315(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3_shift), .D(mu3_in[15]), .Q(mu3_out[15]));
SRL16E mu3lg00(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3lg_shift), .D(mu3lg_in[0]), .Q(mu3lg_out[0]));
SRL16E mu3lg01(.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(core_clk), .CE(mu3lg_shift), .D(mu3lg_in[1]), .Q(mu3lg_out[1]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EDFXBP_TB_V
`define SKY130_FD_SC_LP__EDFXBP_TB_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__edfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 DE = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 DE = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 DE = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 DE = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__edfxbp dut (.D(D), .DE(DE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EDFXBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22A_4_V
`define SKY130_FD_SC_HD__O22A_4_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o22a_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o22a_4 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22A_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:09:03 05/21/2016
// Design Name:
// Module Name: Test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Test(
input Clk_100M,
input Reset,
input Rx,
output Tx,
output reg [15:0]LEDs
);
reg [7:0] userData[0:99];
wire Rx_Ready;
reg Rx_Ack;
wire [7:0] Rx_Data;
reg [7:0] Tx_Data;
reg Tx_Send;
wire Tx_Busy;
reg Tx_Reset;
reg [7:0] Tx_DataIndex;
reg Tx_DataIndexLocked;
reg [7:0] sizeOfDataInByte;
reg [7:0] charCount;
reg receivingData;
reg prevBusyState;
initial prevBusyState = 1'b0;
initial sizeOfDataInByte = 1'b0;
reg doneReceiving;
//initial doneReceiving = 1'b1;
// RECEIVE
always @(posedge Clk_100M) begin
if (Reset) begin
Rx_Ack <= 0;
charCount <= 0;
doneReceiving <= 0;
end
else begin
if (prevBusyState & Rx_Ready) begin
// very first byte expected to be # characters in data.
if (sizeOfDataInByte == 0) begin
sizeOfDataInByte <= Rx_Data; // get number of charcters in data.
receivingData <= 1'b1; // next up start receiving data.
end
// actual data starts from byte 2.
else if (receivingData) begin
//userData[99 - charCount] <= Rx_Data; // actual data.
userData[charCount] <= Rx_Data; // actual data.
charCount <= charCount + 1'b1;
// if done receiving data, receive key.
if (charCount == sizeOfDataInByte - 1) begin
receivingData <= 1'b0; // to indicate finish receiving data.
doneReceiving <= 1;
end
end
Rx_Ack <= 1'b1;
end else if(~Rx_Ready) begin
Rx_Ack <= 1'b0;
end
prevBusyState <= !Rx_Ready;
end
end
// SEND.
always @(posedge Clk_100M) begin
if (Reset) begin
Tx_Data <= 1'b0;
Tx_Send <= 1'b0;
Tx_Reset <= 1'b0;
Tx_DataIndex <= 1'b0;
Tx_DataIndexLocked <= 1'b1; // used to lock Tx_DataIndex to prevent uncontrolled increments.
end
else if (doneReceiving) begin
//***********************************************************************************************
if (Tx_Busy == 0 && Tx_DataIndex < sizeOfDataInByte) begin
Tx_Data <= userData[Tx_DataIndex];
Tx_Send <= 1'b1;
Tx_DataIndexLocked <= 1'b0;
end
else begin
if (~Tx_DataIndexLocked) begin
Tx_DataIndex <= Tx_DataIndex + 1'b1;
Tx_DataIndexLocked <= 1'b1;
end
Tx_Send <= 1'b0;
end
//***********************************************************************************************
end
end
UART_Sender #(14, 14'd9999) sender(
Clk_100M,
//Tx_Reset,
Reset,
Tx_Data,
Tx_Send,
Tx_Busy,
Tx
);
UART_Receiver #(14, 14'd9999) receiver(
Clk_100M,
Reset,
Rx_Data,
Rx_Ready,
Rx_Ack,
Rx
);
always @(*) begin
// displays characters on the LEDs. Characters are shifted using btn P17 and M17
// going from left to right and right to left respectively.
//LEDs[15:8] <= Tx_DataIndex; // check
//LEDs[15:8] <= result[currentCharIndex];
//LEDs[15:8] <= encrypt_Data;
//LEDs[15:8] <= byteOfUserData;
//LEDs[15:8] <= keys[currentCharIndex%3]; // check
//LEDs[15:8] <= index; // check
//LEDs[15:8] <= sizeOfKeyInByte; // check
//LEDs[7:0] <= userData[99-currentCharIndex];
LEDs[15:8] <= Tx_DataIndex;
LEDs[7:0] <= userData[2]; // check
//LEDs[15:0] <= 16'b1111111111111111;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3B_BEHAVIORAL_PP_V |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sp_zones_actual (
phzvl_0_0_V_read,
phzvl_0_1_V_read,
phzvl_0_2_V_read,
phzvl_0_3_V_read,
phzvl_0_4_V_read,
phzvl_0_5_V_read,
phzvl_1_0_V_read,
phzvl_1_1_V_read,
phzvl_1_2_V_read,
phzvl_1_3_V_read,
phzvl_1_4_V_read,
phzvl_1_5_V_read,
phzvl_2_0_V_read,
phzvl_2_1_V_read,
phzvl_2_2_V_read,
phzvl_2_3_V_read,
phzvl_2_4_V_read,
phzvl_2_5_V_read,
phzvl_2_6_V_read,
phzvl_2_7_V_read,
phzvl_2_8_V_read,
phzvl_3_0_V_read,
phzvl_3_1_V_read,
phzvl_3_2_V_read,
phzvl_3_3_V_read,
phzvl_3_4_V_read,
phzvl_3_5_V_read,
phzvl_3_6_V_read,
phzvl_3_7_V_read,
phzvl_3_8_V_read,
phzvl_4_0_V_read,
phzvl_4_1_V_read,
phzvl_4_2_V_read,
phzvl_4_3_V_read,
phzvl_4_4_V_read,
phzvl_4_5_V_read,
phzvl_4_6_V_read,
phzvl_4_7_V_read,
phzvl_4_8_V_read,
ph_hit_0_0_V_read,
ph_hit_0_1_V_read,
ph_hit_0_2_V_read,
ph_hit_0_3_V_read,
ph_hit_0_4_V_read,
ph_hit_0_5_V_read,
ph_hit_0_6_V_read,
ph_hit_0_7_V_read,
ph_hit_0_8_V_read,
ph_hit_1_0_V_read,
ph_hit_1_1_V_read,
ph_hit_1_2_V_read,
ph_hit_1_3_V_read,
ph_hit_1_4_V_read,
ph_hit_1_5_V_read,
ph_hit_1_6_V_read,
ph_hit_1_7_V_read,
ph_hit_1_8_V_read,
ph_hit_2_0_V_read,
ph_hit_2_1_V_read,
ph_hit_2_2_V_read,
ph_hit_2_3_V_read,
ph_hit_2_4_V_read,
ph_hit_2_5_V_read,
ph_hit_2_6_V_read,
ph_hit_2_7_V_read,
ph_hit_2_8_V_read,
ph_hit_3_0_V_read,
ph_hit_3_1_V_read,
ph_hit_3_2_V_read,
ph_hit_3_3_V_read,
ph_hit_3_4_V_read,
ph_hit_3_5_V_read,
ph_hit_3_6_V_read,
ph_hit_3_7_V_read,
ph_hit_3_8_V_read,
ph_hit_4_0_V_read,
ph_hit_4_1_V_read,
ph_hit_4_2_V_read,
ph_hit_4_3_V_read,
ph_hit_4_4_V_read,
ph_hit_4_5_V_read,
ph_hit_4_6_V_read,
ph_hit_4_7_V_read,
ph_hit_4_8_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3,
ap_return_4,
ap_return_5,
ap_return_6,
ap_return_7,
ap_return_8,
ap_return_9,
ap_return_10,
ap_return_11,
ap_return_12,
ap_return_13,
ap_return_14
);
parameter ap_const_lv96_0 = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv122_0 = 122'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv32_14 = 32'b10100;
parameter ap_const_lv32_2B = 32'b101011;
parameter ap_const_lv32_27 = 32'b100111;
parameter ap_const_lv32_3E = 32'b111110;
parameter ap_const_lv32_3A = 32'b111010;
parameter ap_const_lv32_51 = 32'b1010001;
parameter ap_const_lv32_4D = 32'b1001101;
parameter ap_const_lv32_64 = 32'b1100100;
parameter ap_const_lv32_5F = 32'b1011111;
parameter ap_const_lv32_76 = 32'b1110110;
parameter ap_const_lv76_0 = 76'b0000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv32_24 = 32'b100100;
parameter ap_const_lv32_4F = 32'b1001111;
parameter ap_const_lv32_50 = 32'b1010000;
parameter ap_const_lv32_53 = 32'b1010011;
parameter ap_const_lv32_4C = 32'b1001100;
parameter ap_const_lv32_77 = 32'b1110111;
parameter ap_const_lv32_78 = 32'b1111000;
parameter ap_const_lv32_52 = 32'b1010010;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_15 = 32'b10101;
parameter ap_const_lv32_2C = 32'b101100;
parameter ap_const_lv32_60 = 32'b1100000;
parameter ap_const_lv97_0 = 97'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv32_63 = 32'b1100011;
parameter ap_const_lv32_13 = 32'b10011;
parameter ap_const_lv32_17 = 32'b10111;
parameter ap_const_lv19_0 = 19'b0000000000000000000;
parameter ap_const_lv32_12 = 32'b10010;
parameter ap_const_lv18_0 = 18'b000000000000000000;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv32_2 = 32'b10;
input [2:0] phzvl_0_0_V_read;
input [2:0] phzvl_0_1_V_read;
input [2:0] phzvl_0_2_V_read;
input [2:0] phzvl_0_3_V_read;
input [2:0] phzvl_0_4_V_read;
input [2:0] phzvl_0_5_V_read;
input [2:0] phzvl_1_0_V_read;
input [2:0] phzvl_1_1_V_read;
input [2:0] phzvl_1_2_V_read;
input [2:0] phzvl_1_3_V_read;
input [2:0] phzvl_1_4_V_read;
input [2:0] phzvl_1_5_V_read;
input [2:0] phzvl_2_0_V_read;
input [2:0] phzvl_2_1_V_read;
input [2:0] phzvl_2_2_V_read;
input [2:0] phzvl_2_3_V_read;
input [2:0] phzvl_2_4_V_read;
input [2:0] phzvl_2_5_V_read;
input [2:0] phzvl_2_6_V_read;
input [2:0] phzvl_2_7_V_read;
input [2:0] phzvl_2_8_V_read;
input [2:0] phzvl_3_0_V_read;
input [2:0] phzvl_3_1_V_read;
input [2:0] phzvl_3_2_V_read;
input [2:0] phzvl_3_3_V_read;
input [2:0] phzvl_3_4_V_read;
input [2:0] phzvl_3_5_V_read;
input [2:0] phzvl_3_6_V_read;
input [2:0] phzvl_3_7_V_read;
input [2:0] phzvl_3_8_V_read;
input [2:0] phzvl_4_0_V_read;
input [2:0] phzvl_4_1_V_read;
input [2:0] phzvl_4_2_V_read;
input [2:0] phzvl_4_3_V_read;
input [2:0] phzvl_4_4_V_read;
input [2:0] phzvl_4_5_V_read;
input [2:0] phzvl_4_6_V_read;
input [2:0] phzvl_4_7_V_read;
input [2:0] phzvl_4_8_V_read;
input [43:0] ph_hit_0_0_V_read;
input [43:0] ph_hit_0_1_V_read;
input [43:0] ph_hit_0_2_V_read;
input [43:0] ph_hit_0_3_V_read;
input [43:0] ph_hit_0_4_V_read;
input [43:0] ph_hit_0_5_V_read;
input [43:0] ph_hit_0_6_V_read;
input [43:0] ph_hit_0_7_V_read;
input [43:0] ph_hit_0_8_V_read;
input [43:0] ph_hit_1_0_V_read;
input [43:0] ph_hit_1_1_V_read;
input [43:0] ph_hit_1_2_V_read;
input [43:0] ph_hit_1_3_V_read;
input [43:0] ph_hit_1_4_V_read;
input [43:0] ph_hit_1_5_V_read;
input [43:0] ph_hit_1_6_V_read;
input [43:0] ph_hit_1_7_V_read;
input [43:0] ph_hit_1_8_V_read;
input [43:0] ph_hit_2_0_V_read;
input [43:0] ph_hit_2_1_V_read;
input [43:0] ph_hit_2_2_V_read;
input [43:0] ph_hit_2_3_V_read;
input [43:0] ph_hit_2_4_V_read;
input [43:0] ph_hit_2_5_V_read;
input [43:0] ph_hit_2_6_V_read;
input [43:0] ph_hit_2_7_V_read;
input [43:0] ph_hit_2_8_V_read;
input [43:0] ph_hit_3_0_V_read;
input [43:0] ph_hit_3_1_V_read;
input [43:0] ph_hit_3_2_V_read;
input [43:0] ph_hit_3_3_V_read;
input [43:0] ph_hit_3_4_V_read;
input [43:0] ph_hit_3_5_V_read;
input [43:0] ph_hit_3_6_V_read;
input [43:0] ph_hit_3_7_V_read;
input [43:0] ph_hit_3_8_V_read;
input [43:0] ph_hit_4_0_V_read;
input [43:0] ph_hit_4_1_V_read;
input [43:0] ph_hit_4_2_V_read;
input [43:0] ph_hit_4_3_V_read;
input [43:0] ph_hit_4_4_V_read;
input [43:0] ph_hit_4_5_V_read;
input [43:0] ph_hit_4_6_V_read;
input [43:0] ph_hit_4_7_V_read;
input [43:0] ph_hit_4_8_V_read;
output [121:0] ap_return_0;
output [121:0] ap_return_1;
output [121:0] ap_return_2;
output [121:0] ap_return_3;
output [121:0] ap_return_4;
output [121:0] ap_return_5;
output [121:0] ap_return_6;
output [121:0] ap_return_7;
output [121:0] ap_return_8;
output [121:0] ap_return_9;
output [121:0] ap_return_10;
output [121:0] ap_return_11;
output [121:0] ap_return_12;
output [121:0] ap_return_13;
output [121:0] ap_return_14;
wire [23:0] tmp_1_fu_796_p1;
wire [0:0] tmp_fu_792_p1;
wire [121:0] p_Result_s_fu_800_p4;
wire [121:0] p_Val2_s_fu_810_p3;
wire [23:0] p_Result_s_56_fu_822_p4;
wire [23:0] tmp_3_fu_832_p1;
wire [23:0] r_V_trunc_fu_836_p2;
wire [0:0] tmp_2_fu_818_p1;
wire [121:0] p_Result_1_fu_842_p5;
wire [121:0] p_Val2_1_fu_854_p3;
wire [23:0] p_Result_4_fu_866_p4;
wire [23:0] tmp_7_fu_876_p1;
wire [23:0] r_V_64_trunc_fu_880_p2;
wire [0:0] tmp_4_fu_862_p1;
wire [121:0] p_Result_2_fu_886_p5;
wire [121:0] p_Val2_2_fu_898_p3;
wire [23:0] p_Result_7_fu_910_p4;
wire [23:0] tmp_15_fu_920_p1;
wire [23:0] r_V_65_trunc_fu_924_p2;
wire [0:0] tmp_12_fu_906_p1;
wire [121:0] p_Result_3_fu_930_p5;
wire [121:0] p_Val2_3_fu_942_p3;
wire [23:0] p_Result_5_fu_954_p4;
wire [23:0] tmp_21_fu_964_p1;
wire [23:0] r_V_66_trunc_fu_968_p2;
wire [0:0] tmp_18_fu_950_p1;
wire [121:0] p_Result_6_fu_974_p5;
wire [121:0] p_Val2_4_fu_986_p3;
wire [23:0] p_Result_8_fu_998_p4;
wire [23:0] tmp_27_fu_1008_p1;
wire [23:0] r_V_67_trunc_fu_1012_p2;
wire [0:0] tmp_24_fu_994_p1;
wire [121:0] p_Result_9_fu_1018_p5;
wire [44:0] rhs_V_140_trunc_fu_1042_p1;
wire [0:0] tmp_28_fu_1038_p1;
wire [121:0] p_Result_10_fu_1046_p4;
wire [121:0] p_Val2_5_fu_1056_p3;
wire [43:0] tmp_5_fu_1068_p4;
wire [0:0] tmp_30_fu_1084_p3;
wire [43:0] tmp_6_fu_1078_p2;
wire [44:0] r_V_68_trunc_fu_1092_p3;
wire [0:0] tmp_29_fu_1064_p1;
wire [121:0] p_Result_11_fu_1100_p5;
wire [121:0] p_Val2_6_fu_1112_p3;
wire [43:0] tmp_8_fu_1124_p4;
wire [0:0] tmp_32_fu_1140_p3;
wire [43:0] tmp_9_fu_1134_p2;
wire [44:0] r_V_69_trunc_fu_1148_p3;
wire [0:0] tmp_31_fu_1120_p1;
wire [121:0] p_Result_12_fu_1156_p5;
wire [44:0] rhs_V_141_trunc_fu_1180_p1;
wire [0:0] tmp_33_fu_1176_p1;
wire [121:0] p_Result_13_fu_1184_p4;
wire [121:0] p_Val2_7_fu_1194_p3;
wire [43:0] tmp_s_fu_1206_p4;
wire [0:0] tmp_35_fu_1222_p3;
wire [43:0] tmp_10_fu_1216_p2;
wire [44:0] r_V_70_trunc_fu_1230_p3;
wire [0:0] tmp_34_fu_1202_p1;
wire [121:0] p_Result_14_fu_1238_p5;
wire [121:0] p_Val2_8_fu_1250_p3;
wire [43:0] tmp_11_fu_1262_p4;
wire [0:0] tmp_37_fu_1278_p3;
wire [43:0] tmp_13_fu_1272_p2;
wire [44:0] r_V_71_trunc_fu_1286_p3;
wire [0:0] tmp_36_fu_1258_p1;
wire [121:0] p_Result_15_fu_1294_p5;
wire [44:0] rhs_V_142_trunc_fu_1318_p1;
wire [0:0] tmp_38_fu_1314_p1;
wire [121:0] p_Result_16_fu_1322_p4;
wire [121:0] p_Val2_9_fu_1332_p3;
wire [43:0] tmp_14_fu_1344_p4;
wire [0:0] tmp_40_fu_1360_p3;
wire [43:0] tmp_16_fu_1354_p2;
wire [44:0] r_V_72_trunc_fu_1368_p3;
wire [0:0] tmp_39_fu_1340_p1;
wire [121:0] p_Result_17_fu_1376_p5;
wire [121:0] p_Val2_10_fu_1388_p3;
wire [43:0] tmp_17_fu_1400_p4;
wire [0:0] tmp_42_fu_1416_p3;
wire [43:0] tmp_19_fu_1410_p2;
wire [44:0] r_V_73_trunc_fu_1424_p3;
wire [0:0] tmp_41_fu_1396_p1;
wire [121:0] p_Result_18_fu_1432_p5;
wire [0:0] tmp_43_fu_1452_p3;
wire [121:0] p_Val2_11_fu_1460_p3;
wire [23:0] p_Result_19_fu_1476_p4;
wire [23:0] r_V_74_trunc_fu_1486_p2;
wire [0:0] tmp_44_fu_1468_p3;
wire [121:0] p_Result_20_fu_1492_p5;
wire [121:0] p_Val2_12_fu_1504_p3;
wire [23:0] p_Result_21_fu_1520_p4;
wire [23:0] r_V_75_trunc_fu_1530_p2;
wire [0:0] tmp_45_fu_1512_p3;
wire [121:0] p_Result_22_fu_1536_p5;
wire [121:0] p_Val2_13_fu_1548_p3;
wire [23:0] p_Result_23_fu_1564_p4;
wire [23:0] r_V_76_trunc_fu_1574_p2;
wire [0:0] tmp_46_fu_1556_p3;
wire [121:0] p_Result_24_fu_1580_p5;
wire [121:0] p_Val2_14_fu_1592_p3;
wire [23:0] p_Result_25_fu_1608_p4;
wire [23:0] r_V_77_trunc_fu_1618_p2;
wire [0:0] tmp_47_fu_1600_p3;
wire [121:0] p_Result_26_fu_1624_p5;
wire [121:0] p_Val2_15_fu_1636_p3;
wire [23:0] p_Result_27_fu_1652_p4;
wire [23:0] r_V_78_trunc_fu_1662_p2;
wire [0:0] tmp_49_fu_1644_p3;
wire [121:0] p_Result_28_fu_1668_p5;
wire [0:0] tmp_51_fu_1688_p3;
wire [121:0] p_Val2_16_fu_1696_p3;
wire [43:0] tmp_20_fu_1712_p4;
wire [0:0] tmp_55_fu_1728_p3;
wire [43:0] tmp_22_fu_1722_p2;
wire [44:0] r_V_79_trunc_fu_1736_p3;
wire [0:0] tmp_53_fu_1704_p3;
wire [121:0] p_Result_29_fu_1744_p5;
wire [121:0] p_Val2_17_fu_1756_p3;
wire [43:0] tmp_23_fu_1772_p4;
wire [0:0] tmp_59_fu_1788_p3;
wire [43:0] tmp_25_fu_1782_p2;
wire [44:0] r_V_80_trunc_fu_1796_p3;
wire [0:0] tmp_57_fu_1764_p3;
wire [121:0] p_Result_30_fu_1804_p5;
wire [23:0] tmp_63_fu_1828_p1;
wire [0:0] tmp_61_fu_1824_p1;
wire [121:0] p_Result_31_fu_1832_p4;
wire [121:0] p_Val2_18_fu_1842_p3;
wire [23:0] p_Result_32_fu_1854_p4;
wire [23:0] tmp_66_fu_1864_p1;
wire [23:0] r_V_81_trunc_fu_1868_p2;
wire [0:0] tmp_65_fu_1850_p1;
wire [121:0] p_Result_33_fu_1874_p5;
wire [121:0] p_Val2_19_fu_1886_p3;
wire [23:0] p_Result_34_fu_1898_p4;
wire [23:0] tmp_68_fu_1908_p1;
wire [23:0] r_V_82_trunc_fu_1912_p2;
wire [0:0] tmp_67_fu_1894_p1;
wire [121:0] p_Result_35_fu_1918_p5;
wire [121:0] p_Val2_20_fu_1930_p3;
wire [23:0] p_Result_36_fu_1942_p4;
wire [23:0] tmp_70_fu_1952_p1;
wire [23:0] r_V_83_trunc_fu_1956_p2;
wire [0:0] tmp_69_fu_1938_p1;
wire [121:0] p_Result_37_fu_1962_p5;
wire [121:0] p_Val2_21_fu_1974_p3;
wire [23:0] p_Result_38_fu_1986_p4;
wire [23:0] tmp_72_fu_1996_p1;
wire [23:0] r_V_84_trunc_fu_2000_p2;
wire [0:0] tmp_71_fu_1982_p1;
wire [121:0] p_Result_39_fu_2006_p5;
wire [121:0] p_Val2_22_fu_2018_p3;
wire [23:0] p_Result_40_fu_2030_p4;
wire [23:0] tmp_74_fu_2040_p1;
wire [23:0] r_V_85_trunc_fu_2044_p2;
wire [0:0] tmp_73_fu_2026_p1;
wire [121:0] p_Result_41_fu_2050_p5;
wire [23:0] tmp_76_fu_2074_p1;
wire [0:0] tmp_75_fu_2070_p1;
wire [121:0] p_Result_42_fu_2078_p4;
wire [121:0] p_Val2_23_fu_2088_p3;
wire [23:0] p_Result_43_fu_2100_p4;
wire [23:0] tmp_78_fu_2110_p1;
wire [23:0] r_V_86_trunc_fu_2114_p2;
wire [0:0] tmp_77_fu_2096_p1;
wire [121:0] p_Result_44_fu_2120_p5;
wire [121:0] p_Val2_24_fu_2132_p3;
wire [23:0] p_Result_45_fu_2144_p4;
wire [23:0] tmp_80_fu_2154_p1;
wire [23:0] r_V_87_trunc_fu_2158_p2;
wire [0:0] tmp_79_fu_2140_p1;
wire [121:0] p_Result_46_fu_2164_p5;
wire [121:0] p_Val2_25_fu_2176_p3;
wire [23:0] p_Result_47_fu_2188_p4;
wire [23:0] tmp_82_fu_2198_p1;
wire [23:0] r_V_88_trunc_fu_2202_p2;
wire [0:0] tmp_81_fu_2184_p1;
wire [121:0] p_Result_48_fu_2208_p5;
wire [121:0] p_Val2_26_fu_2220_p3;
wire [23:0] p_Result_49_fu_2232_p4;
wire [23:0] tmp_84_fu_2242_p1;
wire [23:0] r_V_89_trunc_fu_2246_p2;
wire [0:0] tmp_83_fu_2228_p1;
wire [121:0] p_Result_50_fu_2252_p5;
wire [121:0] p_Val2_27_fu_2264_p3;
wire [23:0] p_Result_51_fu_2276_p4;
wire [23:0] tmp_86_fu_2286_p1;
wire [23:0] r_V_90_trunc_fu_2290_p2;
wire [0:0] tmp_85_fu_2272_p1;
wire [121:0] p_Result_52_fu_2296_p5;
wire [23:0] tmp_88_fu_2320_p1;
wire [0:0] tmp_87_fu_2316_p1;
wire [121:0] p_Result_53_fu_2324_p4;
wire [121:0] p_Val2_28_fu_2334_p3;
wire [23:0] p_Result_54_fu_2346_p4;
wire [23:0] tmp_90_fu_2356_p1;
wire [23:0] r_V_91_trunc_fu_2360_p2;
wire [0:0] tmp_89_fu_2342_p1;
wire [121:0] p_Result_55_fu_2366_p5;
wire [121:0] p_Val2_29_fu_2378_p3;
wire [23:0] p_Result_56_fu_2390_p4;
wire [23:0] tmp_92_fu_2400_p1;
wire [23:0] r_V_92_trunc_fu_2404_p2;
wire [0:0] tmp_91_fu_2386_p1;
wire [121:0] p_Result_57_fu_2410_p5;
wire [121:0] p_Val2_30_fu_2422_p3;
wire [23:0] p_Result_58_fu_2434_p4;
wire [23:0] tmp_94_fu_2444_p1;
wire [23:0] r_V_93_trunc_fu_2448_p2;
wire [0:0] tmp_93_fu_2430_p1;
wire [121:0] p_Result_59_fu_2454_p5;
wire [121:0] p_Val2_31_fu_2466_p3;
wire [23:0] p_Result_60_fu_2478_p4;
wire [23:0] tmp_96_fu_2488_p1;
wire [23:0] r_V_94_trunc_fu_2492_p2;
wire [0:0] tmp_95_fu_2474_p1;
wire [121:0] p_Result_61_fu_2498_p5;
wire [121:0] p_Val2_32_fu_2510_p3;
wire [23:0] p_Result_62_fu_2522_p4;
wire [23:0] tmp_98_fu_2532_p1;
wire [23:0] r_V_95_trunc_fu_2536_p2;
wire [0:0] tmp_97_fu_2518_p1;
wire [121:0] p_Result_63_fu_2542_p5;
wire [23:0] tmp_100_fu_2566_p1;
wire [0:0] tmp_99_fu_2562_p1;
wire [121:0] p_Result_64_fu_2570_p4;
wire [121:0] p_Val2_33_fu_2580_p3;
wire [23:0] p_Result_65_fu_2592_p4;
wire [23:0] tmp_102_fu_2602_p1;
wire [23:0] r_V_96_trunc_fu_2606_p2;
wire [0:0] tmp_101_fu_2588_p1;
wire [121:0] p_Result_66_fu_2612_p5;
wire [121:0] p_Val2_34_fu_2624_p3;
wire [23:0] p_Result_67_fu_2636_p4;
wire [23:0] tmp_104_fu_2646_p1;
wire [23:0] r_V_97_trunc_fu_2650_p2;
wire [0:0] tmp_103_fu_2632_p1;
wire [121:0] p_Result_68_fu_2656_p5;
wire [121:0] p_Val2_35_fu_2668_p3;
wire [23:0] p_Result_69_fu_2680_p4;
wire [23:0] tmp_106_fu_2690_p1;
wire [23:0] r_V_98_trunc_fu_2694_p2;
wire [0:0] tmp_105_fu_2676_p1;
wire [121:0] p_Result_70_fu_2700_p5;
wire [121:0] p_Val2_36_fu_2712_p3;
wire [23:0] p_Result_71_fu_2724_p4;
wire [23:0] tmp_108_fu_2734_p1;
wire [23:0] r_V_99_trunc_fu_2738_p2;
wire [0:0] tmp_107_fu_2720_p1;
wire [121:0] p_Result_72_fu_2744_p5;
wire [121:0] p_Val2_37_fu_2756_p3;
wire [23:0] p_Result_73_fu_2768_p4;
wire [23:0] tmp_110_fu_2778_p1;
wire [23:0] r_V_100_trunc_fu_2782_p2;
wire [0:0] tmp_109_fu_2764_p1;
wire [121:0] p_Result_74_fu_2788_p5;
wire [0:0] tmp_111_fu_2808_p3;
wire [121:0] p_Val2_38_fu_2816_p3;
wire [23:0] p_Result_75_fu_2832_p4;
wire [23:0] r_V_101_trunc_fu_2842_p2;
wire [0:0] tmp_112_fu_2824_p3;
wire [121:0] p_Result_76_fu_2848_p5;
wire [121:0] p_Val2_39_fu_2860_p3;
wire [23:0] p_Result_77_fu_2876_p4;
wire [23:0] r_V_102_trunc_fu_2886_p2;
wire [0:0] tmp_113_fu_2868_p3;
wire [121:0] p_Result_78_fu_2892_p5;
wire [121:0] p_Val2_40_fu_2904_p3;
wire [23:0] p_Result_79_fu_2920_p4;
wire [23:0] r_V_103_trunc_fu_2930_p2;
wire [0:0] tmp_114_fu_2912_p3;
wire [121:0] p_Result_80_fu_2936_p5;
wire [121:0] p_Val2_41_fu_2948_p3;
wire [23:0] p_Result_81_fu_2964_p4;
wire [23:0] r_V_104_trunc_fu_2974_p2;
wire [0:0] tmp_115_fu_2956_p3;
wire [121:0] p_Result_82_fu_2980_p5;
wire [121:0] p_Val2_42_fu_2992_p3;
wire [23:0] p_Result_83_fu_3008_p4;
wire [23:0] r_V_105_trunc_fu_3018_p2;
wire [0:0] tmp_116_fu_3000_p3;
wire [121:0] p_Result_84_fu_3024_p5;
wire [0:0] tmp_117_fu_3044_p3;
wire [121:0] p_Result_85_fu_3052_p4;
wire [121:0] p_Val2_43_fu_3062_p3;
wire [23:0] p_Result_86_fu_3078_p4;
wire [23:0] r_V_106_trunc_fu_3088_p2;
wire [0:0] tmp_118_fu_3070_p3;
wire [121:0] p_Result_87_fu_3094_p5;
wire [121:0] p_Val2_44_fu_3106_p3;
wire [23:0] p_Result_88_fu_3122_p4;
wire [23:0] r_V_107_trunc_fu_3132_p2;
wire [0:0] tmp_119_fu_3114_p3;
wire [121:0] p_Result_89_fu_3138_p5;
wire [121:0] p_Val2_45_fu_3150_p3;
wire [23:0] p_Result_90_fu_3166_p4;
wire [23:0] r_V_108_trunc_fu_3176_p2;
wire [0:0] tmp_120_fu_3158_p3;
wire [121:0] p_Result_91_fu_3182_p5;
wire [121:0] p_Val2_46_fu_3194_p3;
wire [23:0] p_Result_92_fu_3210_p4;
wire [23:0] r_V_109_trunc_fu_3220_p2;
wire [0:0] tmp_121_fu_3202_p3;
wire [121:0] p_Result_93_fu_3226_p5;
wire [121:0] p_Val2_47_fu_3238_p3;
wire [23:0] p_Result_94_fu_3254_p4;
wire [23:0] r_V_110_trunc_fu_3264_p2;
wire [0:0] tmp_122_fu_3246_p3;
wire [121:0] p_Result_95_fu_3270_p5;
wire [4:0] tmp_26_fu_3290_p4;
wire [23:0] tmp_123_fu_3308_p1;
wire [23:0] p_Result_96_fu_3300_p3;
wire [23:0] tmp_48_fu_3312_p2;
wire [4:0] tmp_50_fu_3322_p4;
wire [23:0] tmp_125_fu_3340_p1;
wire [23:0] p_Result_97_fu_3332_p3;
wire [23:0] tmp_52_fu_3344_p2;
wire [4:0] tmp_54_fu_3354_p4;
wire [23:0] tmp_127_fu_3372_p1;
wire [23:0] p_Result_98_fu_3364_p3;
wire [23:0] tmp_56_fu_3376_p2;
wire [5:0] tmp_58_fu_3386_p4;
wire [23:0] tmp_129_fu_3404_p1;
wire [23:0] p_Result_99_fu_3396_p3;
wire [23:0] tmp_60_fu_3408_p2;
wire [4:0] tmp_62_fu_3418_p4;
wire [23:0] p_Result_100_fu_3428_p3;
wire [23:0] tmp_131_fu_3436_p1;
wire [23:0] r_V_115_trunc_fu_3440_p2;
wire [18:0] tmp_132_fu_3446_p1;
wire [17:0] tmp_130_fu_3414_p1;
wire [18:0] tmp_128_fu_3382_p1;
wire [18:0] tmp_126_fu_3350_p1;
wire [18:0] tmp_124_fu_3318_p1;
wire [0:0] tmp_133_fu_3468_p3;
wire [121:0] p_Val2_48_fu_3476_p3;
wire [23:0] p_Result_102_fu_3492_p4;
wire [23:0] r_V_116_trunc_fu_3502_p2;
wire [0:0] tmp_134_fu_3484_p3;
wire [121:0] p_Result_103_fu_3508_p5;
wire [121:0] p_Val2_49_fu_3520_p3;
wire [23:0] p_Result_104_fu_3536_p4;
wire [23:0] r_V_117_trunc_fu_3546_p2;
wire [0:0] tmp_135_fu_3528_p3;
wire [121:0] p_Result_105_fu_3552_p5;
wire [121:0] p_Val2_50_fu_3564_p3;
wire [23:0] p_Result_106_fu_3580_p4;
wire [23:0] r_V_118_trunc_fu_3590_p2;
wire [0:0] tmp_136_fu_3572_p3;
wire [121:0] p_Result_107_fu_3596_p5;
wire [121:0] p_Val2_51_fu_3608_p3;
wire [23:0] p_Result_108_fu_3624_p4;
wire [23:0] r_V_119_trunc_fu_3634_p2;
wire [0:0] tmp_137_fu_3616_p3;
wire [121:0] p_Result_109_fu_3640_p5;
wire [121:0] p_Val2_52_fu_3652_p3;
wire [23:0] p_Result_110_fu_3668_p4;
wire [23:0] r_V_120_trunc_fu_3678_p2;
wire [0:0] tmp_138_fu_3660_p3;
wire [121:0] p_Result_111_fu_3684_p5;
wire [0:0] tmp_139_fu_3704_p3;
wire [121:0] p_Val2_53_fu_3712_p3;
wire [23:0] p_Result_112_fu_3728_p4;
wire [23:0] r_V_121_trunc_fu_3738_p2;
wire [0:0] tmp_140_fu_3720_p3;
wire [121:0] p_Result_113_fu_3744_p5;
wire [121:0] p_Val2_54_fu_3756_p3;
wire [23:0] p_Result_114_fu_3772_p4;
wire [23:0] r_V_122_trunc_fu_3782_p2;
wire [0:0] tmp_141_fu_3764_p3;
wire [121:0] p_Result_115_fu_3788_p5;
wire [121:0] p_Val2_55_fu_3800_p3;
wire [23:0] p_Result_116_fu_3816_p4;
wire [23:0] r_V_123_trunc_fu_3826_p2;
wire [0:0] tmp_142_fu_3808_p3;
wire [121:0] p_Result_117_fu_3832_p5;
wire [121:0] p_Val2_56_fu_3844_p3;
wire [23:0] p_Result_118_fu_3860_p4;
wire [23:0] r_V_124_trunc_fu_3870_p2;
wire [0:0] tmp_143_fu_3852_p3;
wire [121:0] p_Result_119_fu_3876_p5;
wire [121:0] p_Val2_57_fu_3888_p3;
wire [23:0] p_Result_120_fu_3904_p4;
wire [23:0] r_V_125_trunc_fu_3914_p2;
wire [0:0] tmp_144_fu_3896_p3;
wire [121:0] p_Result_121_fu_3920_p5;
wire [121:0] ph_zone_0_1_V_write_assign_fu_1030_p3;
wire [121:0] ph_zone_0_2_V_write_assign_fu_1168_p3;
wire [121:0] ph_zone_0_3_V_write_assign_fu_1306_p3;
wire [121:0] ph_zone_0_4_V_write_assign_fu_1444_p3;
wire [121:0] ph_zone_1_1_V_write_assign_fu_1680_p3;
wire [121:0] ph_zone_1_2_V_write_assign_fu_1816_p3;
wire [121:0] ph_zone_1_3_V_write_assign_fu_2062_p3;
wire [121:0] ph_zone_1_4_V_write_assign_fu_2308_p3;
wire [121:0] ph_zone_2_1_V_write_assign_fu_2554_p3;
wire [121:0] ph_zone_2_2_V_write_assign_fu_2800_p3;
wire [121:0] ph_zone_2_3_V_write_assign_fu_3036_p3;
wire [121:0] ph_zone_2_4_V_write_assign_fu_3282_p3;
wire [121:0] p_Result_101_fu_3450_p8;
wire [121:0] ph_zone_3_2_V_write_assign_fu_3696_p3;
wire [121:0] ph_zone_3_3_V_write_assign_fu_3932_p3;
assign ap_return_0 = ph_zone_0_1_V_write_assign_fu_1030_p3;
assign ap_return_1 = ph_zone_0_2_V_write_assign_fu_1168_p3;
assign ap_return_10 = ph_zone_2_3_V_write_assign_fu_3036_p3;
assign ap_return_11 = ph_zone_2_4_V_write_assign_fu_3282_p3;
assign ap_return_12 = p_Result_101_fu_3450_p8;
assign ap_return_13 = ph_zone_3_2_V_write_assign_fu_3696_p3;
assign ap_return_14 = ph_zone_3_3_V_write_assign_fu_3932_p3;
assign ap_return_2 = ph_zone_0_3_V_write_assign_fu_1306_p3;
assign ap_return_3 = ph_zone_0_4_V_write_assign_fu_1444_p3;
assign ap_return_4 = ph_zone_1_1_V_write_assign_fu_1680_p3;
assign ap_return_5 = ph_zone_1_2_V_write_assign_fu_1816_p3;
assign ap_return_6 = ph_zone_1_3_V_write_assign_fu_2062_p3;
assign ap_return_7 = ph_zone_1_4_V_write_assign_fu_2308_p3;
assign ap_return_8 = ph_zone_2_1_V_write_assign_fu_2554_p3;
assign ap_return_9 = ph_zone_2_2_V_write_assign_fu_2800_p3;
assign p_Result_100_fu_3428_p3 = {{ap_const_lv19_0}, {tmp_62_fu_3418_p4}};
assign p_Result_101_fu_3450_p8 = {{{{{{{r_V_115_trunc_fu_3440_p2}, {tmp_132_fu_3446_p1}}, {tmp_130_fu_3414_p1}}, {tmp_128_fu_3382_p1}}, {tmp_126_fu_3350_p1}}, {tmp_124_fu_3318_p1}}, {ap_const_lv4_0}};
assign p_Result_102_fu_3492_p4 = {{p_Val2_48_fu_3476_p3[ap_const_lv32_2C : ap_const_lv32_15]}};
assign p_Result_103_fu_3508_p5 = {{p_Val2_48_fu_3476_p3[32'd121 : 32'd45]}, {r_V_116_trunc_fu_3502_p2}, {p_Val2_48_fu_3476_p3[32'd20 : 32'd0]}};
assign p_Result_104_fu_3536_p4 = {{p_Val2_49_fu_3520_p3[ap_const_lv32_3E : ap_const_lv32_27]}};
assign p_Result_105_fu_3552_p5 = {{p_Val2_49_fu_3520_p3[32'd121 : 32'd63]}, {r_V_117_trunc_fu_3546_p2}, {p_Val2_49_fu_3520_p3[32'd38 : 32'd0]}};
assign p_Result_106_fu_3580_p4 = {{p_Val2_50_fu_3564_p3[ap_const_lv32_51 : ap_const_lv32_3A]}};
assign p_Result_107_fu_3596_p5 = {{p_Val2_50_fu_3564_p3[32'd121 : 32'd82]}, {r_V_118_trunc_fu_3590_p2}, {p_Val2_50_fu_3564_p3[32'd57 : 32'd0]}};
assign p_Result_108_fu_3624_p4 = {{p_Val2_51_fu_3608_p3[ap_const_lv32_64 : ap_const_lv32_4D]}};
assign p_Result_109_fu_3640_p5 = {{p_Val2_51_fu_3608_p3[32'd121 : 32'd101]}, {r_V_119_trunc_fu_3634_p2}, {p_Val2_51_fu_3608_p3[32'd76 : 32'd0]}};
assign p_Result_10_fu_1046_p4 = {{{{ap_const_lv76_0}, {rhs_V_140_trunc_fu_1042_p1}}}, {1'b0}};
assign p_Result_110_fu_3668_p4 = {{p_Val2_52_fu_3652_p3[ap_const_lv32_76 : ap_const_lv32_5F]}};
assign p_Result_111_fu_3684_p5 = {{p_Val2_52_fu_3652_p3[32'd121 : 32'd119]}, {r_V_120_trunc_fu_3678_p2}, {p_Val2_52_fu_3652_p3[32'd94 : 32'd0]}};
assign p_Result_112_fu_3728_p4 = {{p_Val2_53_fu_3712_p3[ap_const_lv32_2C : ap_const_lv32_15]}};
assign p_Result_113_fu_3744_p5 = {{p_Val2_53_fu_3712_p3[32'd121 : 32'd45]}, {r_V_121_trunc_fu_3738_p2}, {p_Val2_53_fu_3712_p3[32'd20 : 32'd0]}};
assign p_Result_114_fu_3772_p4 = {{p_Val2_54_fu_3756_p3[ap_const_lv32_3E : ap_const_lv32_27]}};
assign p_Result_115_fu_3788_p5 = {{p_Val2_54_fu_3756_p3[32'd121 : 32'd63]}, {r_V_122_trunc_fu_3782_p2}, {p_Val2_54_fu_3756_p3[32'd38 : 32'd0]}};
assign p_Result_116_fu_3816_p4 = {{p_Val2_55_fu_3800_p3[ap_const_lv32_51 : ap_const_lv32_3A]}};
assign p_Result_117_fu_3832_p5 = {{p_Val2_55_fu_3800_p3[32'd121 : 32'd82]}, {r_V_123_trunc_fu_3826_p2}, {p_Val2_55_fu_3800_p3[32'd57 : 32'd0]}};
assign p_Result_118_fu_3860_p4 = {{p_Val2_56_fu_3844_p3[ap_const_lv32_64 : ap_const_lv32_4D]}};
assign p_Result_119_fu_3876_p5 = {{p_Val2_56_fu_3844_p3[32'd121 : 32'd101]}, {r_V_124_trunc_fu_3870_p2}, {p_Val2_56_fu_3844_p3[32'd76 : 32'd0]}};
assign p_Result_11_fu_1100_p5 = {{p_Val2_5_fu_1056_p3[32'd121 : 32'd84]}, {r_V_68_trunc_fu_1092_p3}, {p_Val2_5_fu_1056_p3[32'd38 : 32'd0]}};
assign p_Result_120_fu_3904_p4 = {{p_Val2_57_fu_3888_p3[ap_const_lv32_76 : ap_const_lv32_5F]}};
assign p_Result_121_fu_3920_p5 = {{p_Val2_57_fu_3888_p3[32'd121 : 32'd119]}, {r_V_125_trunc_fu_3914_p2}, {p_Val2_57_fu_3888_p3[32'd94 : 32'd0]}};
assign p_Result_12_fu_1156_p5 = {{p_Val2_6_fu_1112_p3[32'd121 : 32'd121]}, {r_V_69_trunc_fu_1148_p3}, {p_Val2_6_fu_1112_p3[32'd75 : 32'd0]}};
assign p_Result_13_fu_1184_p4 = {{{{ap_const_lv76_0}, {rhs_V_141_trunc_fu_1180_p1}}}, {1'b0}};
assign p_Result_14_fu_1238_p5 = {{p_Val2_7_fu_1194_p3[32'd121 : 32'd84]}, {r_V_70_trunc_fu_1230_p3}, {p_Val2_7_fu_1194_p3[32'd38 : 32'd0]}};
assign p_Result_15_fu_1294_p5 = {{p_Val2_8_fu_1250_p3[32'd121 : 32'd121]}, {r_V_71_trunc_fu_1286_p3}, {p_Val2_8_fu_1250_p3[32'd75 : 32'd0]}};
assign p_Result_16_fu_1322_p4 = {{{{ap_const_lv76_0}, {rhs_V_142_trunc_fu_1318_p1}}}, {1'b0}};
assign p_Result_17_fu_1376_p5 = {{p_Val2_9_fu_1332_p3[32'd121 : 32'd84]}, {r_V_72_trunc_fu_1368_p3}, {p_Val2_9_fu_1332_p3[32'd38 : 32'd0]}};
assign p_Result_18_fu_1432_p5 = {{p_Val2_10_fu_1388_p3[32'd121 : 32'd121]}, {r_V_73_trunc_fu_1424_p3}, {p_Val2_10_fu_1388_p3[32'd75 : 32'd0]}};
assign p_Result_19_fu_1476_p4 = {{p_Val2_11_fu_1460_p3[ap_const_lv32_2B : ap_const_lv32_14]}};
assign p_Result_1_fu_842_p5 = {{p_Val2_s_fu_810_p3[32'd121 : 32'd44]}, {r_V_trunc_fu_836_p2}, {p_Val2_s_fu_810_p3[32'd19 : 32'd0]}};
assign p_Result_20_fu_1492_p5 = {{p_Val2_11_fu_1460_p3[32'd121 : 32'd44]}, {r_V_74_trunc_fu_1486_p2}, {p_Val2_11_fu_1460_p3[32'd19 : 32'd0]}};
assign p_Result_21_fu_1520_p4 = {{p_Val2_12_fu_1504_p3[ap_const_lv32_3E : ap_const_lv32_27]}};
assign p_Result_22_fu_1536_p5 = {{p_Val2_12_fu_1504_p3[32'd121 : 32'd63]}, {r_V_75_trunc_fu_1530_p2}, {p_Val2_12_fu_1504_p3[32'd38 : 32'd0]}};
assign p_Result_23_fu_1564_p4 = {{p_Val2_13_fu_1548_p3[ap_const_lv32_51 : ap_const_lv32_3A]}};
assign p_Result_24_fu_1580_p5 = {{p_Val2_13_fu_1548_p3[32'd121 : 32'd82]}, {r_V_76_trunc_fu_1574_p2}, {p_Val2_13_fu_1548_p3[32'd57 : 32'd0]}};
assign p_Result_25_fu_1608_p4 = {{p_Val2_14_fu_1592_p3[ap_const_lv32_64 : ap_const_lv32_4D]}};
assign p_Result_26_fu_1624_p5 = {{p_Val2_14_fu_1592_p3[32'd121 : 32'd101]}, {r_V_77_trunc_fu_1618_p2}, {p_Val2_14_fu_1592_p3[32'd76 : 32'd0]}};
assign p_Result_27_fu_1652_p4 = {{p_Val2_15_fu_1636_p3[ap_const_lv32_76 : ap_const_lv32_5F]}};
assign p_Result_28_fu_1668_p5 = {{p_Val2_15_fu_1636_p3[32'd121 : 32'd119]}, {r_V_78_trunc_fu_1662_p2}, {p_Val2_15_fu_1636_p3[32'd94 : 32'd0]}};
assign p_Result_29_fu_1744_p5 = {{p_Val2_16_fu_1696_p3[32'd121 : 32'd84]}, {r_V_79_trunc_fu_1736_p3}, {p_Val2_16_fu_1696_p3[32'd38 : 32'd0]}};
assign p_Result_2_fu_886_p5 = {{p_Val2_1_fu_854_p3[32'd121 : 32'd63]}, {r_V_64_trunc_fu_880_p2}, {p_Val2_1_fu_854_p3[32'd38 : 32'd0]}};
assign p_Result_30_fu_1804_p5 = {{p_Val2_17_fu_1756_p3[32'd121 : 32'd121]}, {r_V_80_trunc_fu_1796_p3}, {p_Val2_17_fu_1756_p3[32'd75 : 32'd0]}};
assign p_Result_31_fu_1832_p4 = {{{{ap_const_lv96_0}, {tmp_63_fu_1828_p1}}}, {ap_const_lv2_0}};
assign p_Result_32_fu_1854_p4 = {{p_Val2_18_fu_1842_p3[ap_const_lv32_2C : ap_const_lv32_15]}};
assign p_Result_33_fu_1874_p5 = {{p_Val2_18_fu_1842_p3[32'd121 : 32'd45]}, {r_V_81_trunc_fu_1868_p2}, {p_Val2_18_fu_1842_p3[32'd20 : 32'd0]}};
assign p_Result_34_fu_1898_p4 = {{p_Val2_19_fu_1886_p3[ap_const_lv32_3E : ap_const_lv32_27]}};
assign p_Result_35_fu_1918_p5 = {{p_Val2_19_fu_1886_p3[32'd121 : 32'd63]}, {r_V_82_trunc_fu_1912_p2}, {p_Val2_19_fu_1886_p3[32'd38 : 32'd0]}};
assign p_Result_36_fu_1942_p4 = {{p_Val2_20_fu_1930_p3[ap_const_lv32_51 : ap_const_lv32_3A]}};
assign p_Result_37_fu_1962_p5 = {{p_Val2_20_fu_1930_p3[32'd121 : 32'd82]}, {r_V_83_trunc_fu_1956_p2}, {p_Val2_20_fu_1930_p3[32'd57 : 32'd0]}};
assign p_Result_38_fu_1986_p4 = {{p_Val2_21_fu_1974_p3[ap_const_lv32_64 : ap_const_lv32_4D]}};
assign p_Result_39_fu_2006_p5 = {{p_Val2_21_fu_1974_p3[32'd121 : 32'd101]}, {r_V_84_trunc_fu_2000_p2}, {p_Val2_21_fu_1974_p3[32'd76 : 32'd0]}};
assign p_Result_3_fu_930_p5 = {{p_Val2_2_fu_898_p3[32'd121 : 32'd82]}, {r_V_65_trunc_fu_924_p2}, {p_Val2_2_fu_898_p3[32'd57 : 32'd0]}};
assign p_Result_40_fu_2030_p4 = {{p_Val2_22_fu_2018_p3[ap_const_lv32_76 : ap_const_lv32_5F]}};
assign p_Result_41_fu_2050_p5 = {{p_Val2_22_fu_2018_p3[32'd121 : 32'd119]}, {r_V_85_trunc_fu_2044_p2}, {p_Val2_22_fu_2018_p3[32'd94 : 32'd0]}};
assign p_Result_42_fu_2078_p4 = {{{{ap_const_lv96_0}, {tmp_76_fu_2074_p1}}}, {ap_const_lv2_0}};
assign p_Result_43_fu_2100_p4 = {{p_Val2_23_fu_2088_p3[ap_const_lv32_2C : ap_const_lv32_15]}};
assign p_Result_44_fu_2120_p5 = {{p_Val2_23_fu_2088_p3[32'd121 : 32'd45]}, {r_V_86_trunc_fu_2114_p2}, {p_Val2_23_fu_2088_p3[32'd20 : 32'd0]}};
assign p_Result_45_fu_2144_p4 = {{p_Val2_24_fu_2132_p3[ap_const_lv32_3E : ap_const_lv32_27]}};
assign p_Result_46_fu_2164_p5 = {{p_Val2_24_fu_2132_p3[32'd121 : 32'd63]}, {r_V_87_trunc_fu_2158_p2}, {p_Val2_24_fu_2132_p3[32'd38 : 32'd0]}};
assign p_Result_47_fu_2188_p4 = {{p_Val2_25_fu_2176_p3[ap_const_lv32_51 : ap_const_lv32_3A]}};
assign p_Result_48_fu_2208_p5 = {{p_Val2_25_fu_2176_p3[32'd121 : 32'd82]}, {r_V_88_trunc_fu_2202_p2}, {p_Val2_25_fu_2176_p3[32'd57 : 32'd0]}};
assign p_Result_49_fu_2232_p4 = {{p_Val2_26_fu_2220_p3[ap_const_lv32_64 : ap_const_lv32_4D]}};
assign p_Result_4_fu_866_p4 = {{p_Val2_1_fu_854_p3[ap_const_lv32_3E : ap_const_lv32_27]}};
assign p_Result_50_fu_2252_p5 = {{p_Val2_26_fu_2220_p3[32'd121 : 32'd101]}, {r_V_89_trunc_fu_2246_p2}, {p_Val2_26_fu_2220_p3[32'd76 : 32'd0]}};
assign p_Result_51_fu_2276_p4 = {{p_Val2_27_fu_2264_p3[ap_const_lv32_76 : ap_const_lv32_5F]}};
assign p_Result_52_fu_2296_p5 = {{p_Val2_27_fu_2264_p3[32'd121 : 32'd119]}, {r_V_90_trunc_fu_2290_p2}, {p_Val2_27_fu_2264_p3[32'd94 : 32'd0]}};
assign p_Result_53_fu_2324_p4 = {{{{ap_const_lv96_0}, {tmp_88_fu_2320_p1}}}, {ap_const_lv2_0}};
assign p_Result_54_fu_2346_p4 = {{p_Val2_28_fu_2334_p3[ap_const_lv32_2C : ap_const_lv32_15]}};
assign p_Result_55_fu_2366_p5 = {{p_Val2_28_fu_2334_p3[32'd121 : 32'd45]}, {r_V_91_trunc_fu_2360_p2}, {p_Val2_28_fu_2334_p3[32'd20 : 32'd0]}};
assign p_Result_56_fu_2390_p4 = {{p_Val2_29_fu_2378_p3[ap_const_lv32_3E : ap_const_lv32_27]}};
assign p_Result_57_fu_2410_p5 = {{p_Val2_29_fu_2378_p3[32'd121 : 32'd63]}, {r_V_92_trunc_fu_2404_p2}, {p_Val2_29_fu_2378_p3[32'd38 : 32'd0]}};
assign p_Result_58_fu_2434_p4 = {{p_Val2_30_fu_2422_p3[ap_const_lv32_51 : ap_const_lv32_3A]}};
assign p_Result_59_fu_2454_p5 = {{p_Val2_30_fu_2422_p3[32'd121 : 32'd82]}, {r_V_93_trunc_fu_2448_p2}, {p_Val2_30_fu_2422_p3[32'd57 : 32'd0]}};
assign p_Result_5_fu_954_p4 = {{p_Val2_3_fu_942_p3[ap_const_lv32_64 : ap_const_lv32_4D]}};
assign p_Result_60_fu_2478_p4 = {{p_Val2_31_fu_2466_p3[ap_const_lv32_64 : ap_const_lv32_4D]}};
assign p_Result_61_fu_2498_p5 = {{p_Val2_31_fu_2466_p3[32'd121 : 32'd101]}, {r_V_94_trunc_fu_2492_p2}, {p_Val2_31_fu_2466_p3[32'd76 : 32'd0]}};
assign p_Result_62_fu_2522_p4 = {{p_Val2_32_fu_2510_p3[ap_const_lv32_77 : ap_const_lv32_60]}};
assign p_Result_63_fu_2542_p5 = {{p_Val2_32_fu_2510_p3[32'd121 : 32'd120]}, {r_V_95_trunc_fu_2536_p2}, {p_Val2_32_fu_2510_p3[32'd95 : 32'd0]}};
assign p_Result_64_fu_2570_p4 = {{{{ap_const_lv96_0}, {tmp_100_fu_2566_p1}}}, {ap_const_lv2_0}};
assign p_Result_65_fu_2592_p4 = {{p_Val2_33_fu_2580_p3[ap_const_lv32_2C : ap_const_lv32_15]}};
assign p_Result_66_fu_2612_p5 = {{p_Val2_33_fu_2580_p3[32'd121 : 32'd45]}, {r_V_96_trunc_fu_2606_p2}, {p_Val2_33_fu_2580_p3[32'd20 : 32'd0]}};
assign p_Result_67_fu_2636_p4 = {{p_Val2_34_fu_2624_p3[ap_const_lv32_3E : ap_const_lv32_27]}};
assign p_Result_68_fu_2656_p5 = {{p_Val2_34_fu_2624_p3[32'd121 : 32'd63]}, {r_V_97_trunc_fu_2650_p2}, {p_Val2_34_fu_2624_p3[32'd38 : 32'd0]}};
assign p_Result_69_fu_2680_p4 = {{p_Val2_35_fu_2668_p3[ap_const_lv32_51 : ap_const_lv32_3A]}};
assign p_Result_6_fu_974_p5 = {{p_Val2_3_fu_942_p3[32'd121 : 32'd101]}, {r_V_66_trunc_fu_968_p2}, {p_Val2_3_fu_942_p3[32'd76 : 32'd0]}};
assign p_Result_70_fu_2700_p5 = {{p_Val2_35_fu_2668_p3[32'd121 : 32'd82]}, {r_V_98_trunc_fu_2694_p2}, {p_Val2_35_fu_2668_p3[32'd57 : 32'd0]}};
assign p_Result_71_fu_2724_p4 = {{p_Val2_36_fu_2712_p3[ap_const_lv32_64 : ap_const_lv32_4D]}};
assign p_Result_72_fu_2744_p5 = {{p_Val2_36_fu_2712_p3[32'd121 : 32'd101]}, {r_V_99_trunc_fu_2738_p2}, {p_Val2_36_fu_2712_p3[32'd76 : 32'd0]}};
assign p_Result_73_fu_2768_p4 = {{p_Val2_37_fu_2756_p3[ap_const_lv32_76 : ap_const_lv32_5F]}};
assign p_Result_74_fu_2788_p5 = {{p_Val2_37_fu_2756_p3[32'd121 : 32'd119]}, {r_V_100_trunc_fu_2782_p2}, {p_Val2_37_fu_2756_p3[32'd94 : 32'd0]}};
assign p_Result_75_fu_2832_p4 = {{p_Val2_38_fu_2816_p3[ap_const_lv32_2C : ap_const_lv32_15]}};
assign p_Result_76_fu_2848_p5 = {{p_Val2_38_fu_2816_p3[32'd121 : 32'd45]}, {r_V_101_trunc_fu_2842_p2}, {p_Val2_38_fu_2816_p3[32'd20 : 32'd0]}};
assign p_Result_77_fu_2876_p4 = {{p_Val2_39_fu_2860_p3[ap_const_lv32_3E : ap_const_lv32_27]}};
assign p_Result_78_fu_2892_p5 = {{p_Val2_39_fu_2860_p3[32'd121 : 32'd63]}, {r_V_102_trunc_fu_2886_p2}, {p_Val2_39_fu_2860_p3[32'd38 : 32'd0]}};
assign p_Result_79_fu_2920_p4 = {{p_Val2_40_fu_2904_p3[ap_const_lv32_51 : ap_const_lv32_3A]}};
assign p_Result_7_fu_910_p4 = {{p_Val2_2_fu_898_p3[ap_const_lv32_51 : ap_const_lv32_3A]}};
assign p_Result_80_fu_2936_p5 = {{p_Val2_40_fu_2904_p3[32'd121 : 32'd82]}, {r_V_103_trunc_fu_2930_p2}, {p_Val2_40_fu_2904_p3[32'd57 : 32'd0]}};
assign p_Result_81_fu_2964_p4 = {{p_Val2_41_fu_2948_p3[ap_const_lv32_64 : ap_const_lv32_4D]}};
assign p_Result_82_fu_2980_p5 = {{p_Val2_41_fu_2948_p3[32'd121 : 32'd101]}, {r_V_104_trunc_fu_2974_p2}, {p_Val2_41_fu_2948_p3[32'd76 : 32'd0]}};
assign p_Result_83_fu_3008_p4 = {{p_Val2_42_fu_2992_p3[ap_const_lv32_76 : ap_const_lv32_5F]}};
assign p_Result_84_fu_3024_p5 = {{p_Val2_42_fu_2992_p3[32'd121 : 32'd119]}, {r_V_105_trunc_fu_3018_p2}, {p_Val2_42_fu_2992_p3[32'd94 : 32'd0]}};
assign p_Result_85_fu_3052_p4 = {{{{ap_const_lv97_0}, {tmp_76_fu_2074_p1}}}, {1'b0}};
assign p_Result_86_fu_3078_p4 = {{p_Val2_43_fu_3062_p3[ap_const_lv32_2B : ap_const_lv32_14]}};
assign p_Result_87_fu_3094_p5 = {{p_Val2_43_fu_3062_p3[32'd121 : 32'd44]}, {r_V_106_trunc_fu_3088_p2}, {p_Val2_43_fu_3062_p3[32'd19 : 32'd0]}};
assign p_Result_88_fu_3122_p4 = {{p_Val2_44_fu_3106_p3[ap_const_lv32_3E : ap_const_lv32_27]}};
assign p_Result_89_fu_3138_p5 = {{p_Val2_44_fu_3106_p3[32'd121 : 32'd63]}, {r_V_107_trunc_fu_3132_p2}, {p_Val2_44_fu_3106_p3[32'd38 : 32'd0]}};
assign p_Result_8_fu_998_p4 = {{p_Val2_4_fu_986_p3[ap_const_lv32_76 : ap_const_lv32_5F]}};
assign p_Result_90_fu_3166_p4 = {{p_Val2_45_fu_3150_p3[ap_const_lv32_51 : ap_const_lv32_3A]}};
assign p_Result_91_fu_3182_p5 = {{p_Val2_45_fu_3150_p3[32'd121 : 32'd82]}, {r_V_108_trunc_fu_3176_p2}, {p_Val2_45_fu_3150_p3[32'd57 : 32'd0]}};
assign p_Result_92_fu_3210_p4 = {{p_Val2_46_fu_3194_p3[ap_const_lv32_63 : ap_const_lv32_4C]}};
assign p_Result_93_fu_3226_p5 = {{p_Val2_46_fu_3194_p3[32'd121 : 32'd100]}, {r_V_109_trunc_fu_3220_p2}, {p_Val2_46_fu_3194_p3[32'd75 : 32'd0]}};
assign p_Result_94_fu_3254_p4 = {{p_Val2_47_fu_3238_p3[ap_const_lv32_76 : ap_const_lv32_5F]}};
assign p_Result_95_fu_3270_p5 = {{p_Val2_47_fu_3238_p3[32'd121 : 32'd119]}, {r_V_110_trunc_fu_3264_p2}, {p_Val2_47_fu_3238_p3[32'd94 : 32'd0]}};
assign p_Result_96_fu_3300_p3 = {{ap_const_lv19_0}, {tmp_26_fu_3290_p4}};
assign p_Result_97_fu_3332_p3 = {{ap_const_lv19_0}, {tmp_50_fu_3322_p4}};
assign p_Result_98_fu_3364_p3 = {{ap_const_lv19_0}, {tmp_54_fu_3354_p4}};
assign p_Result_99_fu_3396_p3 = {{ap_const_lv18_0}, {tmp_58_fu_3386_p4}};
assign p_Result_9_fu_1018_p5 = {{p_Val2_4_fu_986_p3[32'd121 : 32'd119]}, {r_V_67_trunc_fu_1012_p2}, {p_Val2_4_fu_986_p3[32'd94 : 32'd0]}};
assign p_Result_s_56_fu_822_p4 = {{p_Val2_s_fu_810_p3[ap_const_lv32_2B : ap_const_lv32_14]}};
assign p_Result_s_fu_800_p4 = {{{{ap_const_lv96_0}, {tmp_1_fu_796_p1}}}, {ap_const_lv2_0}};
assign p_Val2_10_fu_1388_p3 = ((tmp_39_fu_1340_p1[0:0] === 1'b1) ? p_Result_17_fu_1376_p5 : p_Val2_9_fu_1332_p3);
assign p_Val2_11_fu_1460_p3 = ((tmp_43_fu_1452_p3[0:0] === 1'b1) ? p_Result_s_fu_800_p4 : ap_const_lv122_0);
assign p_Val2_12_fu_1504_p3 = ((tmp_44_fu_1468_p3[0:0] === 1'b1) ? p_Result_20_fu_1492_p5 : p_Val2_11_fu_1460_p3);
assign p_Val2_13_fu_1548_p3 = ((tmp_45_fu_1512_p3[0:0] === 1'b1) ? p_Result_22_fu_1536_p5 : p_Val2_12_fu_1504_p3);
assign p_Val2_14_fu_1592_p3 = ((tmp_46_fu_1556_p3[0:0] === 1'b1) ? p_Result_24_fu_1580_p5 : p_Val2_13_fu_1548_p3);
assign p_Val2_15_fu_1636_p3 = ((tmp_47_fu_1600_p3[0:0] === 1'b1) ? p_Result_26_fu_1624_p5 : p_Val2_14_fu_1592_p3);
assign p_Val2_16_fu_1696_p3 = ((tmp_51_fu_1688_p3[0:0] === 1'b1) ? p_Result_10_fu_1046_p4 : ap_const_lv122_0);
assign p_Val2_17_fu_1756_p3 = ((tmp_53_fu_1704_p3[0:0] === 1'b1) ? p_Result_29_fu_1744_p5 : p_Val2_16_fu_1696_p3);
assign p_Val2_18_fu_1842_p3 = ((tmp_61_fu_1824_p1[0:0] === 1'b1) ? p_Result_31_fu_1832_p4 : ap_const_lv122_0);
assign p_Val2_19_fu_1886_p3 = ((tmp_65_fu_1850_p1[0:0] === 1'b1) ? p_Result_33_fu_1874_p5 : p_Val2_18_fu_1842_p3);
assign p_Val2_1_fu_854_p3 = ((tmp_2_fu_818_p1[0:0] === 1'b1) ? p_Result_1_fu_842_p5 : p_Val2_s_fu_810_p3);
assign p_Val2_20_fu_1930_p3 = ((tmp_67_fu_1894_p1[0:0] === 1'b1) ? p_Result_35_fu_1918_p5 : p_Val2_19_fu_1886_p3);
assign p_Val2_21_fu_1974_p3 = ((tmp_69_fu_1938_p1[0:0] === 1'b1) ? p_Result_37_fu_1962_p5 : p_Val2_20_fu_1930_p3);
assign p_Val2_22_fu_2018_p3 = ((tmp_71_fu_1982_p1[0:0] === 1'b1) ? p_Result_39_fu_2006_p5 : p_Val2_21_fu_1974_p3);
assign p_Val2_23_fu_2088_p3 = ((tmp_75_fu_2070_p1[0:0] === 1'b1) ? p_Result_42_fu_2078_p4 : ap_const_lv122_0);
assign p_Val2_24_fu_2132_p3 = ((tmp_77_fu_2096_p1[0:0] === 1'b1) ? p_Result_44_fu_2120_p5 : p_Val2_23_fu_2088_p3);
assign p_Val2_25_fu_2176_p3 = ((tmp_79_fu_2140_p1[0:0] === 1'b1) ? p_Result_46_fu_2164_p5 : p_Val2_24_fu_2132_p3);
assign p_Val2_26_fu_2220_p3 = ((tmp_81_fu_2184_p1[0:0] === 1'b1) ? p_Result_48_fu_2208_p5 : p_Val2_25_fu_2176_p3);
assign p_Val2_27_fu_2264_p3 = ((tmp_83_fu_2228_p1[0:0] === 1'b1) ? p_Result_50_fu_2252_p5 : p_Val2_26_fu_2220_p3);
assign p_Val2_28_fu_2334_p3 = ((tmp_87_fu_2316_p1[0:0] === 1'b1) ? p_Result_53_fu_2324_p4 : ap_const_lv122_0);
assign p_Val2_29_fu_2378_p3 = ((tmp_89_fu_2342_p1[0:0] === 1'b1) ? p_Result_55_fu_2366_p5 : p_Val2_28_fu_2334_p3);
assign p_Val2_2_fu_898_p3 = ((tmp_4_fu_862_p1[0:0] === 1'b1) ? p_Result_2_fu_886_p5 : p_Val2_1_fu_854_p3);
assign p_Val2_30_fu_2422_p3 = ((tmp_91_fu_2386_p1[0:0] === 1'b1) ? p_Result_57_fu_2410_p5 : p_Val2_29_fu_2378_p3);
assign p_Val2_31_fu_2466_p3 = ((tmp_93_fu_2430_p1[0:0] === 1'b1) ? p_Result_59_fu_2454_p5 : p_Val2_30_fu_2422_p3);
assign p_Val2_32_fu_2510_p3 = ((tmp_95_fu_2474_p1[0:0] === 1'b1) ? p_Result_61_fu_2498_p5 : p_Val2_31_fu_2466_p3);
assign p_Val2_33_fu_2580_p3 = ((tmp_99_fu_2562_p1[0:0] === 1'b1) ? p_Result_64_fu_2570_p4 : ap_const_lv122_0);
assign p_Val2_34_fu_2624_p3 = ((tmp_101_fu_2588_p1[0:0] === 1'b1) ? p_Result_66_fu_2612_p5 : p_Val2_33_fu_2580_p3);
assign p_Val2_35_fu_2668_p3 = ((tmp_103_fu_2632_p1[0:0] === 1'b1) ? p_Result_68_fu_2656_p5 : p_Val2_34_fu_2624_p3);
assign p_Val2_36_fu_2712_p3 = ((tmp_105_fu_2676_p1[0:0] === 1'b1) ? p_Result_70_fu_2700_p5 : p_Val2_35_fu_2668_p3);
assign p_Val2_37_fu_2756_p3 = ((tmp_107_fu_2720_p1[0:0] === 1'b1) ? p_Result_72_fu_2744_p5 : p_Val2_36_fu_2712_p3);
assign p_Val2_38_fu_2816_p3 = ((tmp_111_fu_2808_p3[0:0] === 1'b1) ? p_Result_31_fu_1832_p4 : ap_const_lv122_0);
assign p_Val2_39_fu_2860_p3 = ((tmp_112_fu_2824_p3[0:0] === 1'b1) ? p_Result_76_fu_2848_p5 : p_Val2_38_fu_2816_p3);
assign p_Val2_3_fu_942_p3 = ((tmp_12_fu_906_p1[0:0] === 1'b1) ? p_Result_3_fu_930_p5 : p_Val2_2_fu_898_p3);
assign p_Val2_40_fu_2904_p3 = ((tmp_113_fu_2868_p3[0:0] === 1'b1) ? p_Result_78_fu_2892_p5 : p_Val2_39_fu_2860_p3);
assign p_Val2_41_fu_2948_p3 = ((tmp_114_fu_2912_p3[0:0] === 1'b1) ? p_Result_80_fu_2936_p5 : p_Val2_40_fu_2904_p3);
assign p_Val2_42_fu_2992_p3 = ((tmp_115_fu_2956_p3[0:0] === 1'b1) ? p_Result_82_fu_2980_p5 : p_Val2_41_fu_2948_p3);
assign p_Val2_43_fu_3062_p3 = ((tmp_117_fu_3044_p3[0:0] === 1'b1) ? p_Result_85_fu_3052_p4 : ap_const_lv122_0);
assign p_Val2_44_fu_3106_p3 = ((tmp_118_fu_3070_p3[0:0] === 1'b1) ? p_Result_87_fu_3094_p5 : p_Val2_43_fu_3062_p3);
assign p_Val2_45_fu_3150_p3 = ((tmp_119_fu_3114_p3[0:0] === 1'b1) ? p_Result_89_fu_3138_p5 : p_Val2_44_fu_3106_p3);
assign p_Val2_46_fu_3194_p3 = ((tmp_120_fu_3158_p3[0:0] === 1'b1) ? p_Result_91_fu_3182_p5 : p_Val2_45_fu_3150_p3);
assign p_Val2_47_fu_3238_p3 = ((tmp_121_fu_3202_p3[0:0] === 1'b1) ? p_Result_93_fu_3226_p5 : p_Val2_46_fu_3194_p3);
assign p_Val2_48_fu_3476_p3 = ((tmp_133_fu_3468_p3[0:0] === 1'b1) ? p_Result_64_fu_2570_p4 : ap_const_lv122_0);
assign p_Val2_49_fu_3520_p3 = ((tmp_134_fu_3484_p3[0:0] === 1'b1) ? p_Result_103_fu_3508_p5 : p_Val2_48_fu_3476_p3);
assign p_Val2_4_fu_986_p3 = ((tmp_18_fu_950_p1[0:0] === 1'b1) ? p_Result_6_fu_974_p5 : p_Val2_3_fu_942_p3);
assign p_Val2_50_fu_3564_p3 = ((tmp_135_fu_3528_p3[0:0] === 1'b1) ? p_Result_105_fu_3552_p5 : p_Val2_49_fu_3520_p3);
assign p_Val2_51_fu_3608_p3 = ((tmp_136_fu_3572_p3[0:0] === 1'b1) ? p_Result_107_fu_3596_p5 : p_Val2_50_fu_3564_p3);
assign p_Val2_52_fu_3652_p3 = ((tmp_137_fu_3616_p3[0:0] === 1'b1) ? p_Result_109_fu_3640_p5 : p_Val2_51_fu_3608_p3);
assign p_Val2_53_fu_3712_p3 = ((tmp_139_fu_3704_p3[0:0] === 1'b1) ? p_Result_31_fu_1832_p4 : ap_const_lv122_0);
assign p_Val2_54_fu_3756_p3 = ((tmp_140_fu_3720_p3[0:0] === 1'b1) ? p_Result_113_fu_3744_p5 : p_Val2_53_fu_3712_p3);
assign p_Val2_55_fu_3800_p3 = ((tmp_141_fu_3764_p3[0:0] === 1'b1) ? p_Result_115_fu_3788_p5 : p_Val2_54_fu_3756_p3);
assign p_Val2_56_fu_3844_p3 = ((tmp_142_fu_3808_p3[0:0] === 1'b1) ? p_Result_117_fu_3832_p5 : p_Val2_55_fu_3800_p3);
assign p_Val2_57_fu_3888_p3 = ((tmp_143_fu_3852_p3[0:0] === 1'b1) ? p_Result_119_fu_3876_p5 : p_Val2_56_fu_3844_p3);
assign p_Val2_5_fu_1056_p3 = ((tmp_28_fu_1038_p1[0:0] === 1'b1) ? p_Result_10_fu_1046_p4 : ap_const_lv122_0);
assign p_Val2_6_fu_1112_p3 = ((tmp_29_fu_1064_p1[0:0] === 1'b1) ? p_Result_11_fu_1100_p5 : p_Val2_5_fu_1056_p3);
assign p_Val2_7_fu_1194_p3 = ((tmp_33_fu_1176_p1[0:0] === 1'b1) ? p_Result_13_fu_1184_p4 : ap_const_lv122_0);
assign p_Val2_8_fu_1250_p3 = ((tmp_34_fu_1202_p1[0:0] === 1'b1) ? p_Result_14_fu_1238_p5 : p_Val2_7_fu_1194_p3);
assign p_Val2_9_fu_1332_p3 = ((tmp_38_fu_1314_p1[0:0] === 1'b1) ? p_Result_16_fu_1322_p4 : ap_const_lv122_0);
assign p_Val2_s_fu_810_p3 = ((tmp_fu_792_p1[0:0] === 1'b1) ? p_Result_s_fu_800_p4 : ap_const_lv122_0);
assign ph_zone_0_1_V_write_assign_fu_1030_p3 = ((tmp_24_fu_994_p1[0:0] === 1'b1) ? p_Result_9_fu_1018_p5 : p_Val2_4_fu_986_p3);
assign ph_zone_0_2_V_write_assign_fu_1168_p3 = ((tmp_31_fu_1120_p1[0:0] === 1'b1) ? p_Result_12_fu_1156_p5 : p_Val2_6_fu_1112_p3);
assign ph_zone_0_3_V_write_assign_fu_1306_p3 = ((tmp_36_fu_1258_p1[0:0] === 1'b1) ? p_Result_15_fu_1294_p5 : p_Val2_8_fu_1250_p3);
assign ph_zone_0_4_V_write_assign_fu_1444_p3 = ((tmp_41_fu_1396_p1[0:0] === 1'b1) ? p_Result_18_fu_1432_p5 : p_Val2_10_fu_1388_p3);
assign ph_zone_1_1_V_write_assign_fu_1680_p3 = ((tmp_49_fu_1644_p3[0:0] === 1'b1) ? p_Result_28_fu_1668_p5 : p_Val2_15_fu_1636_p3);
assign ph_zone_1_2_V_write_assign_fu_1816_p3 = ((tmp_57_fu_1764_p3[0:0] === 1'b1) ? p_Result_30_fu_1804_p5 : p_Val2_17_fu_1756_p3);
assign ph_zone_1_3_V_write_assign_fu_2062_p3 = ((tmp_73_fu_2026_p1[0:0] === 1'b1) ? p_Result_41_fu_2050_p5 : p_Val2_22_fu_2018_p3);
assign ph_zone_1_4_V_write_assign_fu_2308_p3 = ((tmp_85_fu_2272_p1[0:0] === 1'b1) ? p_Result_52_fu_2296_p5 : p_Val2_27_fu_2264_p3);
assign ph_zone_2_1_V_write_assign_fu_2554_p3 = ((tmp_97_fu_2518_p1[0:0] === 1'b1) ? p_Result_63_fu_2542_p5 : p_Val2_32_fu_2510_p3);
assign ph_zone_2_2_V_write_assign_fu_2800_p3 = ((tmp_109_fu_2764_p1[0:0] === 1'b1) ? p_Result_74_fu_2788_p5 : p_Val2_37_fu_2756_p3);
assign ph_zone_2_3_V_write_assign_fu_3036_p3 = ((tmp_116_fu_3000_p3[0:0] === 1'b1) ? p_Result_84_fu_3024_p5 : p_Val2_42_fu_2992_p3);
assign ph_zone_2_4_V_write_assign_fu_3282_p3 = ((tmp_122_fu_3246_p3[0:0] === 1'b1) ? p_Result_95_fu_3270_p5 : p_Val2_47_fu_3238_p3);
assign ph_zone_3_2_V_write_assign_fu_3696_p3 = ((tmp_138_fu_3660_p3[0:0] === 1'b1) ? p_Result_111_fu_3684_p5 : p_Val2_52_fu_3652_p3);
assign ph_zone_3_3_V_write_assign_fu_3932_p3 = ((tmp_144_fu_3896_p3[0:0] === 1'b1) ? p_Result_121_fu_3920_p5 : p_Val2_57_fu_3888_p3);
assign r_V_100_trunc_fu_2782_p2 = (p_Result_73_fu_2768_p4 | tmp_110_fu_2778_p1);
assign r_V_101_trunc_fu_2842_p2 = (p_Result_75_fu_2832_p4 | tmp_66_fu_1864_p1);
assign r_V_102_trunc_fu_2886_p2 = (p_Result_77_fu_2876_p4 | tmp_68_fu_1908_p1);
assign r_V_103_trunc_fu_2930_p2 = (p_Result_79_fu_2920_p4 | tmp_70_fu_1952_p1);
assign r_V_104_trunc_fu_2974_p2 = (p_Result_81_fu_2964_p4 | tmp_72_fu_1996_p1);
assign r_V_105_trunc_fu_3018_p2 = (p_Result_83_fu_3008_p4 | tmp_74_fu_2040_p1);
assign r_V_106_trunc_fu_3088_p2 = (p_Result_86_fu_3078_p4 | tmp_78_fu_2110_p1);
assign r_V_107_trunc_fu_3132_p2 = (p_Result_88_fu_3122_p4 | tmp_80_fu_2154_p1);
assign r_V_108_trunc_fu_3176_p2 = (p_Result_90_fu_3166_p4 | tmp_82_fu_2198_p1);
assign r_V_109_trunc_fu_3220_p2 = (p_Result_92_fu_3210_p4 | tmp_84_fu_2242_p1);
assign r_V_110_trunc_fu_3264_p2 = (p_Result_94_fu_3254_p4 | tmp_86_fu_2286_p1);
assign r_V_115_trunc_fu_3440_p2 = (p_Result_100_fu_3428_p3 | tmp_131_fu_3436_p1);
assign r_V_116_trunc_fu_3502_p2 = (p_Result_102_fu_3492_p4 | tmp_102_fu_2602_p1);
assign r_V_117_trunc_fu_3546_p2 = (p_Result_104_fu_3536_p4 | tmp_104_fu_2646_p1);
assign r_V_118_trunc_fu_3590_p2 = (p_Result_106_fu_3580_p4 | tmp_106_fu_2690_p1);
assign r_V_119_trunc_fu_3634_p2 = (p_Result_108_fu_3624_p4 | tmp_108_fu_2734_p1);
assign r_V_120_trunc_fu_3678_p2 = (p_Result_110_fu_3668_p4 | tmp_110_fu_2778_p1);
assign r_V_121_trunc_fu_3738_p2 = (p_Result_112_fu_3728_p4 | tmp_66_fu_1864_p1);
assign r_V_122_trunc_fu_3782_p2 = (p_Result_114_fu_3772_p4 | tmp_68_fu_1908_p1);
assign r_V_123_trunc_fu_3826_p2 = (p_Result_116_fu_3816_p4 | tmp_70_fu_1952_p1);
assign r_V_124_trunc_fu_3870_p2 = (p_Result_118_fu_3860_p4 | tmp_72_fu_1996_p1);
assign r_V_125_trunc_fu_3914_p2 = (p_Result_120_fu_3904_p4 | tmp_74_fu_2040_p1);
assign r_V_64_trunc_fu_880_p2 = (p_Result_4_fu_866_p4 | tmp_7_fu_876_p1);
assign r_V_65_trunc_fu_924_p2 = (p_Result_7_fu_910_p4 | tmp_15_fu_920_p1);
assign r_V_66_trunc_fu_968_p2 = (p_Result_5_fu_954_p4 | tmp_21_fu_964_p1);
assign r_V_67_trunc_fu_1012_p2 = (p_Result_8_fu_998_p4 | tmp_27_fu_1008_p1);
assign r_V_68_trunc_fu_1092_p3 = {{tmp_30_fu_1084_p3}, {tmp_6_fu_1078_p2}};
assign r_V_69_trunc_fu_1148_p3 = {{tmp_32_fu_1140_p3}, {tmp_9_fu_1134_p2}};
assign r_V_70_trunc_fu_1230_p3 = {{tmp_35_fu_1222_p3}, {tmp_10_fu_1216_p2}};
assign r_V_71_trunc_fu_1286_p3 = {{tmp_37_fu_1278_p3}, {tmp_13_fu_1272_p2}};
assign r_V_72_trunc_fu_1368_p3 = {{tmp_40_fu_1360_p3}, {tmp_16_fu_1354_p2}};
assign r_V_73_trunc_fu_1424_p3 = {{tmp_42_fu_1416_p3}, {tmp_19_fu_1410_p2}};
assign r_V_74_trunc_fu_1486_p2 = (p_Result_19_fu_1476_p4 | tmp_3_fu_832_p1);
assign r_V_75_trunc_fu_1530_p2 = (p_Result_21_fu_1520_p4 | tmp_7_fu_876_p1);
assign r_V_76_trunc_fu_1574_p2 = (p_Result_23_fu_1564_p4 | tmp_15_fu_920_p1);
assign r_V_77_trunc_fu_1618_p2 = (p_Result_25_fu_1608_p4 | tmp_21_fu_964_p1);
assign r_V_78_trunc_fu_1662_p2 = (p_Result_27_fu_1652_p4 | tmp_27_fu_1008_p1);
assign r_V_79_trunc_fu_1736_p3 = {{tmp_55_fu_1728_p3}, {tmp_22_fu_1722_p2}};
assign r_V_80_trunc_fu_1796_p3 = {{tmp_59_fu_1788_p3}, {tmp_25_fu_1782_p2}};
assign r_V_81_trunc_fu_1868_p2 = (p_Result_32_fu_1854_p4 | tmp_66_fu_1864_p1);
assign r_V_82_trunc_fu_1912_p2 = (p_Result_34_fu_1898_p4 | tmp_68_fu_1908_p1);
assign r_V_83_trunc_fu_1956_p2 = (p_Result_36_fu_1942_p4 | tmp_70_fu_1952_p1);
assign r_V_84_trunc_fu_2000_p2 = (p_Result_38_fu_1986_p4 | tmp_72_fu_1996_p1);
assign r_V_85_trunc_fu_2044_p2 = (p_Result_40_fu_2030_p4 | tmp_74_fu_2040_p1);
assign r_V_86_trunc_fu_2114_p2 = (p_Result_43_fu_2100_p4 | tmp_78_fu_2110_p1);
assign r_V_87_trunc_fu_2158_p2 = (p_Result_45_fu_2144_p4 | tmp_80_fu_2154_p1);
assign r_V_88_trunc_fu_2202_p2 = (p_Result_47_fu_2188_p4 | tmp_82_fu_2198_p1);
assign r_V_89_trunc_fu_2246_p2 = (p_Result_49_fu_2232_p4 | tmp_84_fu_2242_p1);
assign r_V_90_trunc_fu_2290_p2 = (p_Result_51_fu_2276_p4 | tmp_86_fu_2286_p1);
assign r_V_91_trunc_fu_2360_p2 = (p_Result_54_fu_2346_p4 | tmp_90_fu_2356_p1);
assign r_V_92_trunc_fu_2404_p2 = (p_Result_56_fu_2390_p4 | tmp_92_fu_2400_p1);
assign r_V_93_trunc_fu_2448_p2 = (p_Result_58_fu_2434_p4 | tmp_94_fu_2444_p1);
assign r_V_94_trunc_fu_2492_p2 = (p_Result_60_fu_2478_p4 | tmp_96_fu_2488_p1);
assign r_V_95_trunc_fu_2536_p2 = (p_Result_62_fu_2522_p4 | tmp_98_fu_2532_p1);
assign r_V_96_trunc_fu_2606_p2 = (p_Result_65_fu_2592_p4 | tmp_102_fu_2602_p1);
assign r_V_97_trunc_fu_2650_p2 = (p_Result_67_fu_2636_p4 | tmp_104_fu_2646_p1);
assign r_V_98_trunc_fu_2694_p2 = (p_Result_69_fu_2680_p4 | tmp_106_fu_2690_p1);
assign r_V_99_trunc_fu_2738_p2 = (p_Result_71_fu_2724_p4 | tmp_108_fu_2734_p1);
assign r_V_trunc_fu_836_p2 = (p_Result_s_56_fu_822_p4 | tmp_3_fu_832_p1);
assign rhs_V_140_trunc_fu_1042_p1 = ph_hit_2_0_V_read;
assign rhs_V_141_trunc_fu_1180_p1 = ph_hit_3_0_V_read;
assign rhs_V_142_trunc_fu_1318_p1 = ph_hit_4_0_V_read;
assign tmp_100_fu_2566_p1 = ph_hit_2_3_V_read[23:0];
assign tmp_101_fu_2588_p1 = phzvl_2_4_V_read[0:0];
assign tmp_102_fu_2602_p1 = ph_hit_2_4_V_read[23:0];
assign tmp_103_fu_2632_p1 = phzvl_2_5_V_read[0:0];
assign tmp_104_fu_2646_p1 = ph_hit_2_5_V_read[23:0];
assign tmp_105_fu_2676_p1 = phzvl_2_6_V_read[0:0];
assign tmp_106_fu_2690_p1 = ph_hit_2_6_V_read[23:0];
assign tmp_107_fu_2720_p1 = phzvl_2_7_V_read[0:0];
assign tmp_108_fu_2734_p1 = ph_hit_2_7_V_read[23:0];
assign tmp_109_fu_2764_p1 = phzvl_2_8_V_read[0:0];
assign tmp_10_fu_1216_p2 = (tmp_s_fu_1206_p4 | ph_hit_3_1_V_read);
assign tmp_110_fu_2778_p1 = ph_hit_2_8_V_read[23:0];
assign tmp_111_fu_2808_p3 = phzvl_3_3_V_read[ap_const_lv32_1];
assign tmp_112_fu_2824_p3 = phzvl_3_4_V_read[ap_const_lv32_1];
assign tmp_113_fu_2868_p3 = phzvl_3_5_V_read[ap_const_lv32_1];
assign tmp_114_fu_2912_p3 = phzvl_3_6_V_read[ap_const_lv32_1];
assign tmp_115_fu_2956_p3 = phzvl_3_7_V_read[ap_const_lv32_1];
assign tmp_116_fu_3000_p3 = phzvl_3_8_V_read[ap_const_lv32_1];
assign tmp_117_fu_3044_p3 = phzvl_4_3_V_read[ap_const_lv32_1];
assign tmp_118_fu_3070_p3 = phzvl_4_4_V_read[ap_const_lv32_1];
assign tmp_119_fu_3114_p3 = phzvl_4_5_V_read[ap_const_lv32_1];
assign tmp_11_fu_1262_p4 = {{p_Val2_8_fu_1250_p3[ap_const_lv32_77 : ap_const_lv32_4C]}};
assign tmp_120_fu_3158_p3 = phzvl_4_6_V_read[ap_const_lv32_1];
assign tmp_121_fu_3202_p3 = phzvl_4_7_V_read[ap_const_lv32_1];
assign tmp_122_fu_3246_p3 = phzvl_4_8_V_read[ap_const_lv32_1];
assign tmp_123_fu_3308_p1 = ph_hit_0_7_V_read[23:0];
assign tmp_124_fu_3318_p1 = ph_hit_0_6_V_read[18:0];
assign tmp_125_fu_3340_p1 = ph_hit_0_8_V_read[23:0];
assign tmp_126_fu_3350_p1 = tmp_48_fu_3312_p2[18:0];
assign tmp_127_fu_3372_p1 = ph_hit_1_6_V_read[23:0];
assign tmp_128_fu_3382_p1 = tmp_52_fu_3344_p2[18:0];
assign tmp_129_fu_3404_p1 = ph_hit_1_7_V_read[23:0];
assign tmp_12_fu_906_p1 = phzvl_1_0_V_read[0:0];
assign tmp_130_fu_3414_p1 = tmp_56_fu_3376_p2[17:0];
assign tmp_131_fu_3436_p1 = ph_hit_1_8_V_read[23:0];
assign tmp_132_fu_3446_p1 = tmp_60_fu_3408_p2[18:0];
assign tmp_133_fu_3468_p3 = phzvl_2_3_V_read[ap_const_lv32_1];
assign tmp_134_fu_3484_p3 = phzvl_2_4_V_read[ap_const_lv32_1];
assign tmp_135_fu_3528_p3 = phzvl_2_5_V_read[ap_const_lv32_1];
assign tmp_136_fu_3572_p3 = phzvl_2_6_V_read[ap_const_lv32_1];
assign tmp_137_fu_3616_p3 = phzvl_2_7_V_read[ap_const_lv32_1];
assign tmp_138_fu_3660_p3 = phzvl_2_8_V_read[ap_const_lv32_1];
assign tmp_139_fu_3704_p3 = phzvl_3_3_V_read[ap_const_lv32_2];
assign tmp_13_fu_1272_p2 = (tmp_11_fu_1262_p4 | ph_hit_3_2_V_read);
assign tmp_140_fu_3720_p3 = phzvl_3_4_V_read[ap_const_lv32_2];
assign tmp_141_fu_3764_p3 = phzvl_3_5_V_read[ap_const_lv32_2];
assign tmp_142_fu_3808_p3 = phzvl_3_6_V_read[ap_const_lv32_2];
assign tmp_143_fu_3852_p3 = phzvl_3_7_V_read[ap_const_lv32_2];
assign tmp_144_fu_3896_p3 = phzvl_3_8_V_read[ap_const_lv32_2];
assign tmp_14_fu_1344_p4 = {{p_Val2_9_fu_1332_p3[ap_const_lv32_52 : ap_const_lv32_27]}};
assign tmp_15_fu_920_p1 = ph_hit_1_0_V_read[23:0];
assign tmp_16_fu_1354_p2 = (tmp_14_fu_1344_p4 | ph_hit_4_1_V_read);
assign tmp_17_fu_1400_p4 = {{p_Val2_10_fu_1388_p3[ap_const_lv32_77 : ap_const_lv32_4C]}};
assign tmp_18_fu_950_p1 = phzvl_1_1_V_read[0:0];
assign tmp_19_fu_1410_p2 = (tmp_17_fu_1400_p4 | ph_hit_4_2_V_read);
assign tmp_1_fu_796_p1 = ph_hit_0_0_V_read[23:0];
assign tmp_20_fu_1712_p4 = {{p_Val2_16_fu_1696_p3[ap_const_lv32_52 : ap_const_lv32_27]}};
assign tmp_21_fu_964_p1 = ph_hit_1_1_V_read[23:0];
assign tmp_22_fu_1722_p2 = (tmp_20_fu_1712_p4 | ph_hit_2_1_V_read);
assign tmp_23_fu_1772_p4 = {{p_Val2_17_fu_1756_p3[ap_const_lv32_77 : ap_const_lv32_4C]}};
assign tmp_24_fu_994_p1 = phzvl_1_2_V_read[0:0];
assign tmp_25_fu_1782_p2 = (tmp_23_fu_1772_p4 | ph_hit_2_2_V_read);
assign tmp_26_fu_3290_p4 = {{ph_hit_0_6_V_read[ap_const_lv32_17 : ap_const_lv32_13]}};
assign tmp_27_fu_1008_p1 = ph_hit_1_2_V_read[23:0];
assign tmp_28_fu_1038_p1 = phzvl_2_0_V_read[0:0];
assign tmp_29_fu_1064_p1 = phzvl_2_1_V_read[0:0];
assign tmp_2_fu_818_p1 = phzvl_0_1_V_read[0:0];
assign tmp_30_fu_1084_p3 = p_Val2_5_fu_1056_p3[ap_const_lv32_50];
assign tmp_31_fu_1120_p1 = phzvl_2_2_V_read[0:0];
assign tmp_32_fu_1140_p3 = p_Val2_6_fu_1112_p3[ap_const_lv32_78];
assign tmp_33_fu_1176_p1 = phzvl_3_0_V_read[0:0];
assign tmp_34_fu_1202_p1 = phzvl_3_1_V_read[0:0];
assign tmp_35_fu_1222_p3 = p_Val2_7_fu_1194_p3[ap_const_lv32_53];
assign tmp_36_fu_1258_p1 = phzvl_3_2_V_read[0:0];
assign tmp_37_fu_1278_p3 = p_Val2_8_fu_1250_p3[ap_const_lv32_78];
assign tmp_38_fu_1314_p1 = phzvl_4_0_V_read[0:0];
assign tmp_39_fu_1340_p1 = phzvl_4_1_V_read[0:0];
assign tmp_3_fu_832_p1 = ph_hit_0_1_V_read[23:0];
assign tmp_40_fu_1360_p3 = p_Val2_9_fu_1332_p3[ap_const_lv32_53];
assign tmp_41_fu_1396_p1 = phzvl_4_2_V_read[0:0];
assign tmp_42_fu_1416_p3 = p_Val2_10_fu_1388_p3[ap_const_lv32_78];
assign tmp_43_fu_1452_p3 = phzvl_0_0_V_read[ap_const_lv32_1];
assign tmp_44_fu_1468_p3 = phzvl_0_1_V_read[ap_const_lv32_1];
assign tmp_45_fu_1512_p3 = phzvl_0_2_V_read[ap_const_lv32_1];
assign tmp_46_fu_1556_p3 = phzvl_1_0_V_read[ap_const_lv32_1];
assign tmp_47_fu_1600_p3 = phzvl_1_1_V_read[ap_const_lv32_1];
assign tmp_48_fu_3312_p2 = (tmp_123_fu_3308_p1 | p_Result_96_fu_3300_p3);
assign tmp_49_fu_1644_p3 = phzvl_1_2_V_read[ap_const_lv32_1];
assign tmp_4_fu_862_p1 = phzvl_0_2_V_read[0:0];
assign tmp_50_fu_3322_p4 = {{tmp_48_fu_3312_p2[ap_const_lv32_17 : ap_const_lv32_13]}};
assign tmp_51_fu_1688_p3 = phzvl_2_0_V_read[ap_const_lv32_1];
assign tmp_52_fu_3344_p2 = (tmp_125_fu_3340_p1 | p_Result_97_fu_3332_p3);
assign tmp_53_fu_1704_p3 = phzvl_2_1_V_read[ap_const_lv32_1];
assign tmp_54_fu_3354_p4 = {{tmp_52_fu_3344_p2[ap_const_lv32_17 : ap_const_lv32_13]}};
assign tmp_55_fu_1728_p3 = p_Val2_16_fu_1696_p3[ap_const_lv32_53];
assign tmp_56_fu_3376_p2 = (tmp_127_fu_3372_p1 | p_Result_98_fu_3364_p3);
assign tmp_57_fu_1764_p3 = phzvl_2_2_V_read[ap_const_lv32_1];
assign tmp_58_fu_3386_p4 = {{tmp_56_fu_3376_p2[ap_const_lv32_17 : ap_const_lv32_12]}};
assign tmp_59_fu_1788_p3 = p_Val2_17_fu_1756_p3[ap_const_lv32_78];
assign tmp_5_fu_1068_p4 = {{p_Val2_5_fu_1056_p3[ap_const_lv32_4F : ap_const_lv32_24]}};
assign tmp_60_fu_3408_p2 = (tmp_129_fu_3404_p1 | p_Result_99_fu_3396_p3);
assign tmp_61_fu_1824_p1 = phzvl_3_3_V_read[0:0];
assign tmp_62_fu_3418_p4 = {{tmp_60_fu_3408_p2[ap_const_lv32_17 : ap_const_lv32_13]}};
assign tmp_63_fu_1828_p1 = ph_hit_3_3_V_read[23:0];
assign tmp_65_fu_1850_p1 = phzvl_3_4_V_read[0:0];
assign tmp_66_fu_1864_p1 = ph_hit_3_4_V_read[23:0];
assign tmp_67_fu_1894_p1 = phzvl_3_5_V_read[0:0];
assign tmp_68_fu_1908_p1 = ph_hit_3_5_V_read[23:0];
assign tmp_69_fu_1938_p1 = phzvl_3_6_V_read[0:0];
assign tmp_6_fu_1078_p2 = (tmp_5_fu_1068_p4 | ph_hit_2_1_V_read);
assign tmp_70_fu_1952_p1 = ph_hit_3_6_V_read[23:0];
assign tmp_71_fu_1982_p1 = phzvl_3_7_V_read[0:0];
assign tmp_72_fu_1996_p1 = ph_hit_3_7_V_read[23:0];
assign tmp_73_fu_2026_p1 = phzvl_3_8_V_read[0:0];
assign tmp_74_fu_2040_p1 = ph_hit_3_8_V_read[23:0];
assign tmp_75_fu_2070_p1 = phzvl_4_3_V_read[0:0];
assign tmp_76_fu_2074_p1 = ph_hit_4_3_V_read[23:0];
assign tmp_77_fu_2096_p1 = phzvl_4_4_V_read[0:0];
assign tmp_78_fu_2110_p1 = ph_hit_4_4_V_read[23:0];
assign tmp_79_fu_2140_p1 = phzvl_4_5_V_read[0:0];
assign tmp_7_fu_876_p1 = ph_hit_0_2_V_read[23:0];
assign tmp_80_fu_2154_p1 = ph_hit_4_5_V_read[23:0];
assign tmp_81_fu_2184_p1 = phzvl_4_6_V_read[0:0];
assign tmp_82_fu_2198_p1 = ph_hit_4_6_V_read[23:0];
assign tmp_83_fu_2228_p1 = phzvl_4_7_V_read[0:0];
assign tmp_84_fu_2242_p1 = ph_hit_4_7_V_read[23:0];
assign tmp_85_fu_2272_p1 = phzvl_4_8_V_read[0:0];
assign tmp_86_fu_2286_p1 = ph_hit_4_8_V_read[23:0];
assign tmp_87_fu_2316_p1 = phzvl_0_3_V_read[0:0];
assign tmp_88_fu_2320_p1 = ph_hit_0_3_V_read[23:0];
assign tmp_89_fu_2342_p1 = phzvl_0_4_V_read[0:0];
assign tmp_8_fu_1124_p4 = {{p_Val2_6_fu_1112_p3[ap_const_lv32_77 : ap_const_lv32_4C]}};
assign tmp_90_fu_2356_p1 = ph_hit_0_4_V_read[23:0];
assign tmp_91_fu_2386_p1 = phzvl_0_5_V_read[0:0];
assign tmp_92_fu_2400_p1 = ph_hit_0_5_V_read[23:0];
assign tmp_93_fu_2430_p1 = phzvl_1_3_V_read[0:0];
assign tmp_94_fu_2444_p1 = ph_hit_1_3_V_read[23:0];
assign tmp_95_fu_2474_p1 = phzvl_1_4_V_read[0:0];
assign tmp_96_fu_2488_p1 = ph_hit_1_4_V_read[23:0];
assign tmp_97_fu_2518_p1 = phzvl_1_5_V_read[0:0];
assign tmp_98_fu_2532_p1 = ph_hit_1_5_V_read[23:0];
assign tmp_99_fu_2562_p1 = phzvl_2_3_V_read[0:0];
assign tmp_9_fu_1134_p2 = (tmp_8_fu_1124_p4 | ph_hit_2_2_V_read);
assign tmp_fu_792_p1 = phzvl_0_0_V_read[0:0];
assign tmp_s_fu_1206_p4 = {{p_Val2_7_fu_1194_p3[ap_const_lv32_52 : ap_const_lv32_27]}};
endmodule //sp_zones_actual
|
// file: clk_wiz_v3_6.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____25.000______0.000______50.0_____1000.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module clk_wiz_v3_6
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (4.000),
.CLKFX_DIVIDE (8),
.CLKFX_MULTIPLY (2),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk0));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:47:01 05/24/2016
// Design Name:
// Module Name: Contador_AD
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Contador_AD(
input rst,
input [1:0] en,
input [7:0] Cambio,
input got_data,
input clk,
output reg [(N-1):0] Cuenta
);
parameter N = 6;
parameter X = 59;
always @(posedge clk)
if (en == 2'd0)
begin
if (rst)
Cuenta <= 0;
else if (Cambio == 8'h75 && got_data)
begin
if (Cuenta == X)
Cuenta <= 0;
else
Cuenta <= Cuenta + 1'd1;
end
else if (Cambio == 8'h72 && got_data)
begin
if (Cuenta == 0)
Cuenta <= X;
else
Cuenta <= Cuenta - 1'd1;
end
else
Cuenta <= Cuenta;
end
else Cuenta <= Cuenta;
endmodule
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
//Date : Wed Oct 18 20:30:30 2017
//Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_V
`define SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fill_diode ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_V |
/*---------------------------------------------------------------------------------------------------------------------
-- Author: Peter Hasza, [email protected]
--
-- Create Date: 04/02/2017
-- Module Name: CLK_gen_simple
-- Project Name: AXI_SPI_IF
-- Description:
-- Simple Clock generator module. The purpose of a less resourceful implementation of the SPI interface
-- SCLK generation in case of modulo 2 clock ratio.
-- The use case clock ratios:
-- - clk_div 2,4,8
-- But the module can handle any modulo 2 clock ratios.
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2017.apr.2 | hp3265 || Initial version
--
-----------------------------------------------------------------------------------------------------------------------*/
module CLK_gen_simple(
input clk_i,
output clk_o
);
parameter g_clk_div;
localparam c_counter_width = clog2(g_clk_div);
reg [c_counter_width:0] clk_cnt_y = 0;
always @(posedge clk_i)
clk_cnt_y <= clk_cnt_y + 1;
assign clk_o = clk_cnt_y[c_counter_width];
end module; |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_SN_SYMBOL_V
/**
* udp_dlatch$P_pp$PKG$sN: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$P_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PKG_SN_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR3_BLACKBOX_V
`define SKY130_FD_SC_LP__XOR3_BLACKBOX_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR3_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FA_SYMBOL_V
`define SKY130_FD_SC_MS__FA_SYMBOL_V
/**
* fa: Full adder.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fa (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FA_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DLYGATE4SD1_BEHAVIORAL_PP_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__dlygate4sd1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD1_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03:52:17 12/13/2016
// Design Name:
// Module Name: n2s
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module n2s(
input clk,
input rst,
input [7:0] num,
input deal,
output [127:0] str
);
wire [399:0] uStr, dStr;
reg [399:0] uAns, dAns;
reg [30:0] counter;
wire [3:0] b [2:0];
wire [7:0] tmp;
wire rfd1, rfd2;
assign str = (deal)? uAns:dAns;
div div1 (
.clk(clk), // input clk
.rfd(rfd1), // output rfd
.dividend(num), // input [7 : 0] dividend
.divisor(8'd10), // input [7 : 0] divisor
.quotient(tmp), // output [7 : 0] quotient
.fractional(b[0])
);
div div2 (
.clk(clk), // input clk
.rfd(rfd2), // output rfd
.dividend(tmp), // input [7 : 0] dividend
.divisor(8'd10), // input [7 : 0] divisor
.quotient(b[2]), // output [7 : 0] quotient
.fractional(b[1])
);
assign uStr = {" Last answer=",8'h30+b[2],8'h30+b[1],8'h30+b[0]," "};
assign dStr = {" Current answer=",8'h30+b[2],8'h30+b[1],8'h30+b[0]," "};
// counter
always@(posedge clk, posedge rst)
begin
if(rst) counter <= 0;
else counter <= (counter[28:23] < 34)? counter+1 : 0;
end
// uAns
always@(posedge clk, posedge rst)
begin
if(rst) uAns <= uStr;
else begin
case(counter[28:23])
0 : uAns <= {uStr[399:272]};
1 : uAns <= {uStr[391:264]};
2 : uAns <= {uStr[383:256]};
3 : uAns <= {uStr[375:248]};
4 : uAns <= {uStr[367:240]};
5 : uAns <= {uStr[359:232]};
6 : uAns <= {uStr[351:224]};
7 : uAns <= {uStr[343:216]};
8 : uAns <= {uStr[335:208]};
9 : uAns <= {uStr[327:200]};
10: uAns <= {uStr[319:192]};
11: uAns <= {uStr[311:184]};
12: uAns <= {uStr[303:176]};
13: uAns <= {uStr[295:168]};
14: uAns <= {uStr[287:160]};
15: uAns <= {uStr[279:152]};
16: uAns <= {uStr[271:144]};
17: uAns <= {uStr[263:136]};
18: uAns <= {uStr[255:128]};
19: uAns <= {uStr[247:120]};
10: uAns <= {uStr[239:112]};
21: uAns <= {uStr[231:104]};
22: uAns <= {uStr[223:96 ]};
23: uAns <= {uStr[215:88 ]};
24: uAns <= {uStr[207:80 ]};
25: uAns <= {uStr[199:72 ]};
26: uAns <= {uStr[191:64 ]};
27: uAns <= {uStr[183:56 ]};
28: uAns <= {uStr[175:48 ]};
29: uAns <= {uStr[167:40 ]};
30: uAns <= {uStr[159:32 ]};
31: uAns <= {uStr[151:24 ]};
32: uAns <= {uStr[143:16 ]};
33: uAns <= {uStr[135:8 ]};
default: uAns <= uAns;
endcase
end
end
// dAns
always@(posedge clk, posedge rst)
begin
if(rst) dAns <= dStr;
else begin
case(counter[28:23])
0 : dAns <= {dStr[135:8 ]};
1 : dAns <= {dStr[143:16 ]};
2 : dAns <= {dStr[151:24 ]};
3 : dAns <= {dStr[159:32 ]};
4 : dAns <= {dStr[167:40 ]};
5 : dAns <= {dStr[175:48 ]};
6 : dAns <= {dStr[183:56 ]};
7 : dAns <= {dStr[191:64 ]};
8 : dAns <= {dStr[199:72 ]};
9 : dAns <= {dStr[207:80 ]};
10: dAns <= {dStr[215:88 ]};
11: dAns <= {dStr[223:96 ]};
12: dAns <= {dStr[231:104]};
13: dAns <= {dStr[239:112]};
14: dAns <= {dStr[247:120]};
15: dAns <= {dStr[255:128]};
16: dAns <= {dStr[263:136]};
17: dAns <= {dStr[271:144]};
18: dAns <= {dStr[279:152]};
19: dAns <= {dStr[287:160]};
10: dAns <= {dStr[295:168]};
21: dAns <= {dStr[303:176]};
22: dAns <= {dStr[311:184]};
23: dAns <= {dStr[319:192]};
24: dAns <= {dStr[327:200]};
25: dAns <= {dStr[335:208]};
26: dAns <= {dStr[343:216]};
27: dAns <= {dStr[351:224]};
28: dAns <= {dStr[359:232]};
29: dAns <= {dStr[367:240]};
30: dAns <= {dStr[375:248]};
31: dAns <= {dStr[383:256]};
32: dAns <= {dStr[391:264]};
33: dAns <= {dStr[399:272]};
default: dAns <= dAns;
endcase
end
end
endmodule |
/*
* Copyright (C) 2017 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
*/
`timescale 1ns / 1ps
// divide a double precision float by 3e9 0x41E65A0BC0000000
// 63: sign, 62:52 exponent with bias of 1023, 51:0 mantissa
//
module div_3e9
(
input c,
input [62:0] i, // double float without sign bit
input iv,
output reg [62:0] o,
output reg [10:0] oe,
output reg ov = 0);
reg [53:0] sr;
reg [6:0] state = 0;
wire [53:0] sub = sr - 54'h165A0BC0000000;
always @ (posedge c)
begin
if(iv)
oe <= i[62:52] - (1023+31);
else if(state == 64)
oe <= o[62] ? oe : oe-1'b1;
if(iv)
state <= 1'b1;
else if(state == 64)
state <= 1'b0;
else
state <= state + (state != 0);
if(iv)
sr <= {2'b01,i[51:0]};
else
sr <= sub[53] ? {sr[52:0],1'b0} : {sub[52:0],1'b0};
if(state == 64)
o <= o[62] ? o : {o[61:0],1'b0};
else if(state != 0)
o <= {o[61:0], ~sub[53]};
ov <= (state == 64);
end
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule
|
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////////////////////////////
// Company: Universidad de Costa Rica
// Engineer: jOSHUA tORRES mORALES (A76478)
//
// Create Date: 15:41:50 09/06/2015
// Design Name:
// Module Name: Fifo_Lifo
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
///////////////////////////////////////////////////////////////////////////////////////////////////////
module Fifo_Lifo(
input Wrclk, // Write Clock, also Read Clock in stack Mode.
input Rdclk, // Read Clock , only used in Queue Mode.
input Rst, // Reset, must be in high state at least one clock cycle to empty the Stack/Queue.
input Wren, // Write Enable Signal for the RAM module.
input Rden, // Read Enable Signal for the RAM module.
input [15:0] Datain , // Data to Stack/Queue.
output [15:0] Dataout, // Data from Stack/Queue.
output Full, // Stack is Full Signal, High = True.
output Empty // Stack is Empty Signal, High = True.
);
//Parameters
parameter MODE = 0 ; // Mode Selection: 0 for Stack mode, 1 for Queue mode.
parameter DEPTH = (1 << ADDR_WIDTH) ; // Stack/Queue Size
parameter SIZE = 8 ; // Word Size (8-32 bits)
parameter ADDR_WIDTH = 3 ; // Address Size
//Internal variables
reg [ADDR_WIDTH-1:0] wr_pointer;
reg [ADDR_WIDTH-1:0] rd_pointer;
reg [ADDR_WIDTH :0] status_cnt;
reg [SIZE-1:0] data_out ;
wire [SIZE-1:0] data_ram ;
//Inputs,Outputs
//Wires
//Internal Circuitry
//Ram Instantiation
ram #(
.dat_width(SIZE),
.adr_width(ADDR_WIDTH),
.mem_size (DEPTH)
) XIFO_RAM(
.dat_i(data_ram) ,
.dat_o(Dataout) ,
.adr_wr_i(wr_pointer) ,
.adr_rd_i(rd_pointer) ,
.we_i(Wren) ,
.rde_i(Rden) ,
.clk(Rdclk)
);
endmodule
|
//*******************************************************************************************
//Author: Yejoong Kim
//Last Modified: Jul 27 2017
//Description : Isolation gate interface for LRC & MBUS controller (FLPv3L)
//Update History: Jun 27 2017 - First Commit (Yejoong Kim)
//*******************************************************************************************
module flpv3l_mbus_isolation (
input MBC_ISOLATE,
// Layer Ctrl --> MBus Ctrl
input [31:0] TX_ADDR_uniso,
input [31:0] TX_DATA_uniso,
input TX_PEND_uniso,
input TX_REQ_uniso,
input TX_PRIORITY_uniso,
input RX_ACK_uniso,
input TX_RESP_ACK_uniso,
output [31:0] TX_ADDR,
output [31:0] TX_DATA,
output TX_PEND,
output TX_REQ,
output TX_PRIORITY,
output RX_ACK,
output TX_RESP_ACK,
// MBus Ctrl --> Other
input LRC_SLEEP_uniso,
input LRC_CLKENB_uniso,
input LRC_RESET_uniso,
input LRC_ISOLATE_uniso,
output LRC_SLEEP,
output LRC_SLEEPB,
output LRC_CLKENB,
output LRC_CLKEN,
output LRC_RESET,
output LRC_RESETB,
output LRC_ISOLATE
);
wire LRC_ISOLATE_B;
wire LRC_ISOLATE_unbuf;
wire LRC_ISOLATE_B_unbuf;
wire MBC_ISOLATE_B;
wire LRC_CLKENB_B;
wire LRC_RESET_B_int;
wire LRC_SLEEP_B;
genvar i;
generate
for (i=0; i<32; i=i+1) begin : GEN_TX_ADDR_DATA
AND2LLX1HVT_TSMC90 AND2_TX_ADDR (.A(LRC_ISOLATE_B), .B(TX_ADDR_uniso[i]), .Y(TX_ADDR[i]) );
AND2LLX1HVT_TSMC90 AND2_TX_DATA (.A(LRC_ISOLATE_B), .B(TX_DATA_uniso[i]), .Y(TX_DATA[i]) );
end
endgenerate
AND2LLX1HVT_TSMC90 AND2_TX_PEND (.A(LRC_ISOLATE_B), .B(TX_PEND_uniso), .Y(TX_PEND) );
AND2LLX1HVT_TSMC90 AND2_TX_REQ (.A(LRC_ISOLATE_B), .B(TX_REQ_uniso), .Y(TX_REQ) );
AND2LLX1HVT_TSMC90 AND2_TX_PRIORITY(.A(LRC_ISOLATE_B), .B(TX_PRIORITY_uniso), .Y(TX_PRIORITY) );
AND2LLX1HVT_TSMC90 AND2_RX_ACK (.A(LRC_ISOLATE_B), .B(RX_ACK_uniso), .Y(RX_ACK) );
AND2LLX1HVT_TSMC90 AND2_TX_RESP_ACK (.A(LRC_ISOLATE_B), .B(TX_RESP_ACK_uniso), .Y(TX_RESP_ACK) );
INVLLX8HVT_TSMC90 INV_MBC_ISOLATE (.A(MBC_ISOLATE), .Y(MBC_ISOLATE_B) );
NOR2LLX1HVT_TSMC90 NOR2_LRC_SLEEP (.A(MBC_ISOLATE), .B(LRC_SLEEP_uniso), .Y(LRC_SLEEP_B) );
NOR2LLX1HVT_TSMC90 NOR2_LRC_CLKENB (.A(MBC_ISOLATE), .B(LRC_CLKENB_uniso), .Y(LRC_CLKENB_B) );
NOR2LLX1HVT_TSMC90 NOR2_LRC_RESET (.A(MBC_ISOLATE), .B(LRC_RESET_uniso), .Y(LRC_RESET_B_int) );
NOR2LLX1HVT_TSMC90 NOR2_LRC_ISOLATE(.A(MBC_ISOLATE), .B(LRC_ISOLATE_uniso), .Y(LRC_ISOLATE_B_unbuf) );
INVLLX8HVT_TSMC90 INV_LRC_ISOLATE_B_0_0 (.A(LRC_ISOLATE_B_unbuf), .Y(LRC_ISOLATE_unbuf) );
INVLLX8HVT_TSMC90 INV_LRC_ISOLATE_B_0_1 (.A(LRC_ISOLATE_B_unbuf), .Y(LRC_ISOLATE_unbuf) );
INVLLX8HVT_TSMC90 INV_LRC_ISOLATE_B_0_2 (.A(LRC_ISOLATE_B_unbuf), .Y(LRC_ISOLATE_unbuf) );
INVLLX8HVT_TSMC90 INV_LRC_ISOLATE_B_0_3 (.A(LRC_ISOLATE_B_unbuf), .Y(LRC_ISOLATE_unbuf) );
INVLLX8HVT_TSMC90 INV_LRC_ISOLATE_B_1_0 (.A(LRC_ISOLATE_unbuf), .Y(LRC_ISOLATE_B) );
INVLLX8HVT_TSMC90 INV_LRC_ISOLATE_B_1_1 (.A(LRC_ISOLATE_unbuf), .Y(LRC_ISOLATE_B) );
INVLLX8HVT_TSMC90 INV_LRC_ISOLATE_B_1_2 (.A(LRC_ISOLATE_unbuf), .Y(LRC_ISOLATE_B) );
INVLLX8HVT_TSMC90 INV_LRC_ISOLATE_B_1_3 (.A(LRC_ISOLATE_unbuf), .Y(LRC_ISOLATE_B) );
INVLLX8HVT_TSMC90 INV_LRC_SLEEP_0 (.A(LRC_SLEEP_B), .Y(LRC_SLEEP) );
INVLLX8HVT_TSMC90 INV_LRC_SLEEPB_0 (.A(LRC_SLEEP), .Y(LRC_SLEEPB) );
INVLLX8HVT_TSMC90 INV_LRC_CLKENB (.A(LRC_CLKENB_B), .Y(LRC_CLKENB) );
INVLLX8HVT_TSMC90 INV_LRC_CLKEN (.A(LRC_CLKENB), .Y(LRC_CLKEN) );
INVLLX8HVT_TSMC90 INV_LRC_RESET (.A(LRC_RESET_B_int), .Y(LRC_RESET) );
INVLLX8HVT_TSMC90 INV_LRC_RESETB (.A(LRC_RESET), .Y(LRC_RESETB) );
INVLLX8HVT_TSMC90 INV_LRC_ISOLATE (.A(LRC_ISOLATE_B), .Y(LRC_ISOLATE) );
endmodule // flpv3l_mbus_isolation
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : fetch_ref_chroma.v
// Author : Yufeng Bai
// Email : [email protected]
//
//-------------------------------------------------------------------
//
// Modified : 2015-09-02 by HLL
// Description : rotate by sys_start_i
// Modified : 2015-09-17 by HLL
// Description : ref_chroma provided in the order of uvuvuv...
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module fetch_ref_chroma (
clk ,
rstn ,
sysif_start_i ,
sysif_total_y_i ,
mc_cur_y_i ,
mc_ref_x_i ,
mc_ref_y_i ,
mc_ref_rden_i ,
mc_ref_sel_i ,
mc_ref_pel_o ,
ext_load_done_i ,
ext_load_data_i ,
ext_load_addr_i ,
ext_load_valid_i
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input sysif_start_i ;
input [`PIC_Y_WIDTH-1:0] sysif_total_y_i ;
input [`PIC_Y_WIDTH-1:0] mc_cur_y_i ;
input [6-1:0] mc_ref_x_i ; // mc ref x
input [6-1:0] mc_ref_y_i ; // mc ref y
input [1-1:0] mc_ref_rden_i ; // mc ref read enable
input [1-1:0] mc_ref_sel_i ; // "mc ref read sel: cb
output [8*`PIXEL_WIDTH-1:0] mc_ref_pel_o ; // mc ref pixel
input [1-1:0] ext_load_done_i ; // load current lcu done
input [96*`PIXEL_WIDTH-1:0] ext_load_data_i ; // load current lcu data
input [6-1:0] ext_load_addr_i ;
input [1-1:0] ext_load_valid_i; // load current lcu data valid
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
reg rotate ;
reg [6-1 : 0] mc_ref_y ;
reg [6-1 : 0] mc_ref_x ;
reg [1-1 : 0] mc_ref_sel ;
wire [1-1 : 0] ref_u_wen ,ref_u_0_wen ,ref_u_1_wen ,ref_v_wen ,ref_v_0_wen ,ref_v_1_wen ;
wire [6-1 : 0] ref_u_waddr ,ref_u_0_waddr ,ref_u_1_waddr ,ref_v_waddr ,ref_v_0_waddr ,ref_v_1_waddr ;
wire [48*`PIXEL_WIDTH-1 : 0] ref_u_wdata ,ref_u_0_wdata ,ref_u_1_wdata ,ref_v_wdata ,ref_v_0_wdata ,ref_v_1_wdata ;
wire [1-1:0] ref_u_rden ,ref_u_0_rden ,ref_u_1_rden ,ref_v_rden ,ref_v_0_rden ,ref_v_1_rden ;
wire [6-1:0] ref_u_raddr ,ref_u_0_raddr ,ref_u_1_raddr ,ref_v_raddr ,ref_v_0_raddr ,ref_v_1_raddr ;
wire [48*`PIXEL_WIDTH-1 : 0] ref_u_rdata ,ref_u_0_rdata ,ref_u_1_rdata ,ref_v_rdata ,ref_v_0_rdata ,ref_v_1_rdata ;
wire [48*`PIXEL_WIDTH-1 : 0] mc_ref_pel ;
wire [48*`PIXEL_WIDTH-1 : 0] ref_data ;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always @ (*) begin
if(mc_cur_y_i == 'd0)
mc_ref_y = (mc_ref_y_i < 'd8) ? 'd0 : mc_ref_y_i - 'd8;
else if(mc_cur_y_i == sysif_total_y_i)
mc_ref_y = (mc_ref_y_i >= 'd40) ? 'd39 : mc_ref_y_i;
else
mc_ref_y = mc_ref_y_i;
end
assign ref_u_wen = ext_load_valid_i ;
assign ref_u_waddr = ext_load_addr_i ;
assign ref_u_wdata = ext_load_data_i[96*`PIXEL_WIDTH-1 : 48*`PIXEL_WIDTH] ;
assign ref_u_rden = mc_ref_rden_i & (~mc_ref_sel_i);
assign ref_u_raddr = mc_ref_y;
assign ref_v_wen = ext_load_valid_i ;
assign ref_v_waddr = ext_load_addr_i ;
assign ref_v_wdata = ext_load_data_i[48*`PIXEL_WIDTH-1 : 00*`PIXEL_WIDTH] ;
assign ref_v_rden = mc_ref_rden_i & ( mc_ref_sel_i);
assign ref_v_raddr = mc_ref_y;
assign ref_data = mc_ref_sel ? ref_v_rdata : ref_u_rdata;
assign mc_ref_pel = ref_data << ({mc_ref_x,3'b0});
assign mc_ref_pel_o = mc_ref_pel[48*`PIXEL_WIDTH-1:40*`PIXEL_WIDTH];
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
mc_ref_x <= 'd0;
mc_ref_sel <= 'd0;
end
else if (mc_ref_rden_i) begin
mc_ref_x <= mc_ref_x_i;
mc_ref_sel <= mc_ref_sel_i;
end
end
always @(posedge clk or negedge rstn ) begin
if( !rstn )
rotate <= 0 ;
else if( sysif_start_i ) begin
rotate <= !rotate ;
end
end
assign ref_u_0_wen = rotate ? ref_u_wen : 0 ;
assign ref_u_0_waddr = rotate ? ref_u_waddr : 0 ;
assign ref_u_0_wdata = rotate ? ref_u_wdata : 0 ;
assign ref_u_1_wen = rotate ? 0 : ref_u_wen ;
assign ref_u_1_waddr = rotate ? 0 : ref_u_waddr ;
assign ref_u_1_wdata = rotate ? 0 : ref_u_wdata ;
assign ref_u_0_rden = rotate ? 0 : ref_u_rden ;
assign ref_u_0_raddr = rotate ? 0 : ref_u_raddr ;
assign ref_u_1_rden = rotate ? ref_u_rden : 0 ;
assign ref_u_1_raddr = rotate ? ref_u_raddr : 0 ;
assign ref_u_rdata = rotate ? ref_u_1_rdata : ref_u_0_rdata ;
assign ref_v_0_wen = rotate ? ref_v_wen : 0 ;
assign ref_v_0_waddr = rotate ? ref_v_waddr : 0 ;
assign ref_v_0_wdata = rotate ? ref_v_wdata : 0 ;
assign ref_v_1_wen = rotate ? 0 : ref_v_wen ;
assign ref_v_1_waddr = rotate ? 0 : ref_v_waddr ;
assign ref_v_1_wdata = rotate ? 0 : ref_v_wdata ;
assign ref_v_0_rden = rotate ? 0 : ref_v_rden ;
assign ref_v_0_raddr = rotate ? 0 : ref_v_raddr ;
assign ref_v_1_rden = rotate ? ref_v_rden : 0 ;
assign ref_v_1_raddr = rotate ? ref_v_raddr : 0 ;
assign ref_v_rdata = rotate ? ref_v_1_rdata : ref_v_0_rdata ;
// ********************************************
//
// mem
//
// ********************************************
wrap_ref_chroma ref_chroma_u_0 (
.clk (clk ),
.rstn (rstn ),
.wrif_en_i (ref_u_0_wen ),
.wrif_addr_i (ref_u_0_waddr ),
.wrif_data_i (ref_u_0_wdata ),
.rdif_en_i (ref_u_0_rden ),
.rdif_addr_i (ref_u_0_raddr ),
.rdif_pdata_o (ref_u_0_rdata )
);
wrap_ref_chroma ref_chroma_v_0 (
.clk (clk ),
.rstn (rstn ),
.wrif_en_i (ref_v_0_wen ),
.wrif_addr_i (ref_v_0_waddr ),
.wrif_data_i (ref_v_0_wdata ),
.rdif_en_i (ref_v_0_rden ),
.rdif_addr_i (ref_v_0_raddr ),
.rdif_pdata_o (ref_v_0_rdata )
);
wrap_ref_chroma ref_chroma_u_1 (
.clk (clk ),
.rstn (rstn ),
.wrif_en_i (ref_u_1_wen ),
.wrif_addr_i (ref_u_1_waddr ),
.wrif_data_i (ref_u_1_wdata ),
.rdif_en_i (ref_u_1_rden ),
.rdif_addr_i (ref_u_1_raddr ),
.rdif_pdata_o (ref_u_1_rdata )
);
wrap_ref_chroma ref_chroma_v_1 (
.clk (clk ),
.rstn (rstn ),
.wrif_en_i (ref_v_1_wen ),
.wrif_addr_i (ref_v_1_waddr ),
.wrif_data_i (ref_v_1_wdata ),
.rdif_en_i (ref_v_1_rden ),
.rdif_addr_i (ref_v_1_raddr ),
.rdif_pdata_o (ref_v_1_rdata )
);
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: alt_rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.1 Build 150 06/03/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module alt_rom (
address,
clock,
q);
input [11:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./bootrom.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./bootrom.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
Copyright (c) 2014-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream UART
*/
module uart_rx #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
/*
* UART interface
*/
input wire rxd,
/*
* Status
*/
output wire busy,
output wire overrun_error,
output wire frame_error,
/*
* Configuration
*/
input wire [15:0] prescale
);
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
reg output_axis_tvalid_reg = 0;
reg rxd_reg = 1;
reg busy_reg = 0;
reg overrun_error_reg = 0;
reg frame_error_reg = 0;
reg [DATA_WIDTH-1:0] data_reg = 0;
reg [18:0] prescale_reg = 0;
reg [3:0] bit_cnt = 0;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign busy = busy_reg;
assign overrun_error = overrun_error_reg;
assign frame_error = frame_error_reg;
always @(posedge clk) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
rxd_reg <= 1;
prescale_reg <= 0;
bit_cnt <= 0;
busy_reg <= 0;
overrun_error_reg <= 0;
frame_error_reg <= 0;
end else begin
rxd_reg <= rxd;
overrun_error_reg <= 0;
frame_error_reg <= 0;
if (output_axis_tvalid & output_axis_tready) begin
output_axis_tvalid_reg <= 0;
end
if (prescale_reg > 0) begin
prescale_reg <= prescale_reg - 1;
end else if (bit_cnt > 0) begin
if (bit_cnt > DATA_WIDTH+1) begin
if (~rxd_reg) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3)-1;
end else begin
bit_cnt <= 0;
prescale_reg <= 0;
end
end else if (bit_cnt > 1) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3)-1;
data_reg <= {rxd_reg, data_reg[DATA_WIDTH-1:1]};
end else if (bit_cnt == 1) begin
bit_cnt <= bit_cnt - 1;
if (rxd_reg) begin
output_axis_tdata_reg <= data_reg;
output_axis_tvalid_reg <= 1;
overrun_error_reg <= output_axis_tvalid_reg;
end else begin
frame_error_reg <= 1;
end
end
end else begin
busy_reg <= 0;
if (~rxd_reg) begin
prescale_reg <= (prescale << 2)-2;
bit_cnt <= DATA_WIDTH+2;
data_reg <= 0;
busy_reg <= 1;
end
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:48:24 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_0_0/system_axi_gpio_0_0_stub.v
// Design : system_axi_gpio_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2016.4" *)
module system_axi_gpio_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, gpio_io_i, gpio_io_o,
gpio_io_t)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[19:0],gpio_io_o[19:0],gpio_io_t[19:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output ip2intc_irpt;
input [19:0]gpio_io_i;
output [19:0]gpio_io_o;
output [19:0]gpio_io_t;
endmodule
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Tue Nov 5 11:22:19 EST 2013
//
//
// Ports:
// Name I/O size props
// wci_s_0_SResp O 2 const
// wci_s_0_SData O 32 const
// wci_s_0_SThreadBusy O 1 const
// wci_s_0_SFlag O 2 const
// wci_s_1_SResp O 2 reg
// wci_s_1_SData O 32 reg
// wci_s_1_SThreadBusy O 1
// wci_s_1_SFlag O 2
// wci_s_2_SResp O 2 reg
// wci_s_2_SData O 32 reg
// wci_s_2_SThreadBusy O 1
// wci_s_2_SFlag O 2
// wci_s_3_SResp O 2 reg
// wci_s_3_SData O 32 reg
// wci_s_3_SThreadBusy O 1
// wci_s_3_SFlag O 2
// wci_s_4_SResp O 2 reg
// wci_s_4_SData O 32 reg
// wci_s_4_SThreadBusy O 1
// wci_s_4_SFlag O 2
// wci_s_5_SResp O 2 const
// wci_s_5_SData O 32 const
// wci_s_5_SThreadBusy O 1 const
// wci_s_5_SFlag O 2 const
// wci_s_6_SResp O 2 const
// wci_s_6_SData O 32 const
// wci_s_6_SThreadBusy O 1 const
// wci_s_6_SFlag O 2 const
// wci_s_7_SResp O 2 const
// wci_s_7_SData O 32 const
// wci_s_7_SThreadBusy O 1 const
// wci_s_7_SFlag O 2 const
// wti_s_0_SThreadBusy O 1 const
// wti_s_0_SReset_n O 1 const
// wti_s_1_SThreadBusy O 1 const
// wti_s_1_SReset_n O 1 const
// wti_s_2_SThreadBusy O 1 const
// wti_s_2_SReset_n O 1 const
// wmiM0_MCmd O 3
// wmiM0_MReqLast O 1
// wmiM0_MReqInfo O 1
// wmiM0_MAddrSpace O 1
// wmiM0_MAddr O 14
// wmiM0_MBurstLength O 12
// wmiM0_MDataValid O 1
// wmiM0_MDataLast O 1
// wmiM0_MData O 32
// wmiM0_MDataByteEn O 4
// wmiM0_MFlag O 32
// wmiM0_MReset_n O 1
// wmiM1_MCmd O 3
// wmiM1_MReqLast O 1
// wmiM1_MReqInfo O 1
// wmiM1_MAddrSpace O 1
// wmiM1_MAddr O 14
// wmiM1_MBurstLength O 12
// wmiM1_MDataValid O 1
// wmiM1_MDataLast O 1
// wmiM1_MData O 32
// wmiM1_MDataByteEn O 4
// wmiM1_MFlag O 32
// wmiM1_MReset_n O 1
// wmemiM0_MCmd O 3 reg
// wmemiM0_MReqLast O 1 reg
// wmemiM0_MAddr O 36 reg
// wmemiM0_MBurstLength O 12 reg
// wmemiM0_MDataValid O 1 reg
// wmemiM0_MDataLast O 1 reg
// wmemiM0_MData O 128 reg
// wmemiM0_MDataByteEn O 16 reg
// wmemiM0_MReset_n O 1
// wsi_s_adc_SThreadBusy O 1
// wsi_s_adc_SReset_n O 1
// wsi_m_dac_MCmd O 3
// wsi_m_dac_MReqLast O 1
// wsi_m_dac_MBurstPrecise O 1
// wsi_m_dac_MBurstLength O 12
// wsi_m_dac_MData O 32 reg
// wsi_m_dac_MByteEn O 4 reg
// wsi_m_dac_MReqInfo O 8
// wsi_m_dac_MReset_n O 1
// uuid O 512 const
// RST_N_rst_0 I 1 unused
// RST_N_rst_1 I 1 reset
// RST_N_rst_2 I 1 reset
// RST_N_rst_3 I 1 reset
// RST_N_rst_4 I 1 reset
// RST_N_rst_5 I 1 unused
// RST_N_rst_6 I 1 unused
// RST_N_rst_7 I 1 unused
// CLK I 1 clock
// RST_N I 1 unused
// wci_s_0_MCmd I 3 unused
// wci_s_0_MAddrSpace I 1 unused
// wci_s_0_MByteEn I 4 unused
// wci_s_0_MAddr I 32 unused
// wci_s_0_MData I 32 unused
// wci_s_0_MFlag I 2 unused
// wci_s_1_MCmd I 3
// wci_s_1_MAddrSpace I 1
// wci_s_1_MByteEn I 4
// wci_s_1_MAddr I 32
// wci_s_1_MData I 32
// wci_s_1_MFlag I 2 unused
// wci_s_2_MCmd I 3
// wci_s_2_MAddrSpace I 1
// wci_s_2_MByteEn I 4
// wci_s_2_MAddr I 32
// wci_s_2_MData I 32
// wci_s_2_MFlag I 2 unused
// wci_s_3_MCmd I 3
// wci_s_3_MAddrSpace I 1
// wci_s_3_MByteEn I 4
// wci_s_3_MAddr I 32
// wci_s_3_MData I 32
// wci_s_3_MFlag I 2 unused
// wci_s_4_MCmd I 3
// wci_s_4_MAddrSpace I 1
// wci_s_4_MByteEn I 4
// wci_s_4_MAddr I 32
// wci_s_4_MData I 32
// wci_s_4_MFlag I 2 unused
// wci_s_5_MCmd I 3 unused
// wci_s_5_MAddrSpace I 1 unused
// wci_s_5_MByteEn I 4 unused
// wci_s_5_MAddr I 32 unused
// wci_s_5_MData I 32 unused
// wci_s_5_MFlag I 2 unused
// wci_s_6_MCmd I 3 unused
// wci_s_6_MAddrSpace I 1 unused
// wci_s_6_MByteEn I 4 unused
// wci_s_6_MAddr I 32 unused
// wci_s_6_MData I 32 unused
// wci_s_6_MFlag I 2 unused
// wci_s_7_MCmd I 3 unused
// wci_s_7_MAddrSpace I 1 unused
// wci_s_7_MByteEn I 4 unused
// wci_s_7_MAddr I 32 unused
// wci_s_7_MData I 32 unused
// wci_s_7_MFlag I 2 unused
// wti_s_0_MCmd I 3 unused
// wti_s_0_MData I 64 unused
// wti_s_1_MCmd I 3 unused
// wti_s_1_MData I 64 unused
// wti_s_2_MCmd I 3 unused
// wti_s_2_MData I 64 unused
// wmiM0_SResp I 2
// wmiM0_SData I 32
// wmiM0_SFlag I 32 reg
// wmiM1_SResp I 2
// wmiM1_SData I 32
// wmiM1_SFlag I 32 reg
// wmemiM0_SResp I 2
// wmemiM0_SData I 128
// wsi_s_adc_MCmd I 3
// wsi_s_adc_MBurstLength I 12
// wsi_s_adc_MData I 32
// wsi_s_adc_MByteEn I 4
// wsi_s_adc_MReqInfo I 8
// wmiM0_SThreadBusy I 1 reg
// wmiM0_SDataThreadBusy I 1 reg
// wmiM0_SRespLast I 1 unused
// wmiM0_SReset_n I 1 reg
// wmiM1_SThreadBusy I 1 reg
// wmiM1_SDataThreadBusy I 1 reg
// wmiM1_SRespLast I 1 unused
// wmiM1_SReset_n I 1 reg
// wmemiM0_SRespLast I 1
// wmemiM0_SCmdAccept I 1
// wmemiM0_SDataAccept I 1
// wsi_s_adc_MReqLast I 1
// wsi_s_adc_MBurstPrecise I 1
// wsi_s_adc_MReset_n I 1 reg
// wsi_m_dac_SThreadBusy I 1 reg
// wsi_m_dac_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkOCApp4B(RST_N_rst_0,
RST_N_rst_1,
RST_N_rst_2,
RST_N_rst_3,
RST_N_rst_4,
RST_N_rst_5,
RST_N_rst_6,
RST_N_rst_7,
CLK,
RST_N,
wci_s_0_MCmd,
wci_s_0_MAddrSpace,
wci_s_0_MByteEn,
wci_s_0_MAddr,
wci_s_0_MData,
wci_s_0_SResp,
wci_s_0_SData,
wci_s_0_SThreadBusy,
wci_s_0_SFlag,
wci_s_0_MFlag,
wci_s_1_MCmd,
wci_s_1_MAddrSpace,
wci_s_1_MByteEn,
wci_s_1_MAddr,
wci_s_1_MData,
wci_s_1_SResp,
wci_s_1_SData,
wci_s_1_SThreadBusy,
wci_s_1_SFlag,
wci_s_1_MFlag,
wci_s_2_MCmd,
wci_s_2_MAddrSpace,
wci_s_2_MByteEn,
wci_s_2_MAddr,
wci_s_2_MData,
wci_s_2_SResp,
wci_s_2_SData,
wci_s_2_SThreadBusy,
wci_s_2_SFlag,
wci_s_2_MFlag,
wci_s_3_MCmd,
wci_s_3_MAddrSpace,
wci_s_3_MByteEn,
wci_s_3_MAddr,
wci_s_3_MData,
wci_s_3_SResp,
wci_s_3_SData,
wci_s_3_SThreadBusy,
wci_s_3_SFlag,
wci_s_3_MFlag,
wci_s_4_MCmd,
wci_s_4_MAddrSpace,
wci_s_4_MByteEn,
wci_s_4_MAddr,
wci_s_4_MData,
wci_s_4_SResp,
wci_s_4_SData,
wci_s_4_SThreadBusy,
wci_s_4_SFlag,
wci_s_4_MFlag,
wci_s_5_MCmd,
wci_s_5_MAddrSpace,
wci_s_5_MByteEn,
wci_s_5_MAddr,
wci_s_5_MData,
wci_s_5_SResp,
wci_s_5_SData,
wci_s_5_SThreadBusy,
wci_s_5_SFlag,
wci_s_5_MFlag,
wci_s_6_MCmd,
wci_s_6_MAddrSpace,
wci_s_6_MByteEn,
wci_s_6_MAddr,
wci_s_6_MData,
wci_s_6_SResp,
wci_s_6_SData,
wci_s_6_SThreadBusy,
wci_s_6_SFlag,
wci_s_6_MFlag,
wci_s_7_MCmd,
wci_s_7_MAddrSpace,
wci_s_7_MByteEn,
wci_s_7_MAddr,
wci_s_7_MData,
wci_s_7_SResp,
wci_s_7_SData,
wci_s_7_SThreadBusy,
wci_s_7_SFlag,
wci_s_7_MFlag,
wti_s_0_MCmd,
wti_s_0_MData,
wti_s_0_SThreadBusy,
wti_s_0_SReset_n,
wti_s_1_MCmd,
wti_s_1_MData,
wti_s_1_SThreadBusy,
wti_s_1_SReset_n,
wti_s_2_MCmd,
wti_s_2_MData,
wti_s_2_SThreadBusy,
wti_s_2_SReset_n,
wmiM0_MCmd,
wmiM0_MReqLast,
wmiM0_MReqInfo,
wmiM0_MAddrSpace,
wmiM0_MAddr,
wmiM0_MBurstLength,
wmiM0_MDataValid,
wmiM0_MDataLast,
wmiM0_MData,
wmiM0_MDataByteEn,
wmiM0_SResp,
wmiM0_SData,
wmiM0_SThreadBusy,
wmiM0_SDataThreadBusy,
wmiM0_SRespLast,
wmiM0_SFlag,
wmiM0_MFlag,
wmiM0_MReset_n,
wmiM0_SReset_n,
wmiM1_MCmd,
wmiM1_MReqLast,
wmiM1_MReqInfo,
wmiM1_MAddrSpace,
wmiM1_MAddr,
wmiM1_MBurstLength,
wmiM1_MDataValid,
wmiM1_MDataLast,
wmiM1_MData,
wmiM1_MDataByteEn,
wmiM1_SResp,
wmiM1_SData,
wmiM1_SThreadBusy,
wmiM1_SDataThreadBusy,
wmiM1_SRespLast,
wmiM1_SFlag,
wmiM1_MFlag,
wmiM1_MReset_n,
wmiM1_SReset_n,
wmemiM0_MCmd,
wmemiM0_MReqLast,
wmemiM0_MAddr,
wmemiM0_MBurstLength,
wmemiM0_MDataValid,
wmemiM0_MDataLast,
wmemiM0_MData,
wmemiM0_MDataByteEn,
wmemiM0_SResp,
wmemiM0_SRespLast,
wmemiM0_SData,
wmemiM0_SCmdAccept,
wmemiM0_SDataAccept,
wmemiM0_MReset_n,
wsi_s_adc_MCmd,
wsi_s_adc_MReqLast,
wsi_s_adc_MBurstPrecise,
wsi_s_adc_MBurstLength,
wsi_s_adc_MData,
wsi_s_adc_MByteEn,
wsi_s_adc_MReqInfo,
wsi_s_adc_SThreadBusy,
wsi_s_adc_SReset_n,
wsi_s_adc_MReset_n,
wsi_m_dac_MCmd,
wsi_m_dac_MReqLast,
wsi_m_dac_MBurstPrecise,
wsi_m_dac_MBurstLength,
wsi_m_dac_MData,
wsi_m_dac_MByteEn,
wsi_m_dac_MReqInfo,
wsi_m_dac_SThreadBusy,
wsi_m_dac_MReset_n,
wsi_m_dac_SReset_n,
uuid);
parameter [0 : 0] hasDebugLogic = 1'b0;
input RST_N_rst_0;
input RST_N_rst_1;
input RST_N_rst_2;
input RST_N_rst_3;
input RST_N_rst_4;
input RST_N_rst_5;
input RST_N_rst_6;
input RST_N_rst_7;
input CLK;
input RST_N;
// action method wci_s_0_mCmd
input [2 : 0] wci_s_0_MCmd;
// action method wci_s_0_mAddrSpace
input wci_s_0_MAddrSpace;
// action method wci_s_0_mByteEn
input [3 : 0] wci_s_0_MByteEn;
// action method wci_s_0_mAddr
input [31 : 0] wci_s_0_MAddr;
// action method wci_s_0_mData
input [31 : 0] wci_s_0_MData;
// value method wci_s_0_sResp
output [1 : 0] wci_s_0_SResp;
// value method wci_s_0_sData
output [31 : 0] wci_s_0_SData;
// value method wci_s_0_sThreadBusy
output wci_s_0_SThreadBusy;
// value method wci_s_0_sFlag
output [1 : 0] wci_s_0_SFlag;
// action method wci_s_0_mFlag
input [1 : 0] wci_s_0_MFlag;
// action method wci_s_1_mCmd
input [2 : 0] wci_s_1_MCmd;
// action method wci_s_1_mAddrSpace
input wci_s_1_MAddrSpace;
// action method wci_s_1_mByteEn
input [3 : 0] wci_s_1_MByteEn;
// action method wci_s_1_mAddr
input [31 : 0] wci_s_1_MAddr;
// action method wci_s_1_mData
input [31 : 0] wci_s_1_MData;
// value method wci_s_1_sResp
output [1 : 0] wci_s_1_SResp;
// value method wci_s_1_sData
output [31 : 0] wci_s_1_SData;
// value method wci_s_1_sThreadBusy
output wci_s_1_SThreadBusy;
// value method wci_s_1_sFlag
output [1 : 0] wci_s_1_SFlag;
// action method wci_s_1_mFlag
input [1 : 0] wci_s_1_MFlag;
// action method wci_s_2_mCmd
input [2 : 0] wci_s_2_MCmd;
// action method wci_s_2_mAddrSpace
input wci_s_2_MAddrSpace;
// action method wci_s_2_mByteEn
input [3 : 0] wci_s_2_MByteEn;
// action method wci_s_2_mAddr
input [31 : 0] wci_s_2_MAddr;
// action method wci_s_2_mData
input [31 : 0] wci_s_2_MData;
// value method wci_s_2_sResp
output [1 : 0] wci_s_2_SResp;
// value method wci_s_2_sData
output [31 : 0] wci_s_2_SData;
// value method wci_s_2_sThreadBusy
output wci_s_2_SThreadBusy;
// value method wci_s_2_sFlag
output [1 : 0] wci_s_2_SFlag;
// action method wci_s_2_mFlag
input [1 : 0] wci_s_2_MFlag;
// action method wci_s_3_mCmd
input [2 : 0] wci_s_3_MCmd;
// action method wci_s_3_mAddrSpace
input wci_s_3_MAddrSpace;
// action method wci_s_3_mByteEn
input [3 : 0] wci_s_3_MByteEn;
// action method wci_s_3_mAddr
input [31 : 0] wci_s_3_MAddr;
// action method wci_s_3_mData
input [31 : 0] wci_s_3_MData;
// value method wci_s_3_sResp
output [1 : 0] wci_s_3_SResp;
// value method wci_s_3_sData
output [31 : 0] wci_s_3_SData;
// value method wci_s_3_sThreadBusy
output wci_s_3_SThreadBusy;
// value method wci_s_3_sFlag
output [1 : 0] wci_s_3_SFlag;
// action method wci_s_3_mFlag
input [1 : 0] wci_s_3_MFlag;
// action method wci_s_4_mCmd
input [2 : 0] wci_s_4_MCmd;
// action method wci_s_4_mAddrSpace
input wci_s_4_MAddrSpace;
// action method wci_s_4_mByteEn
input [3 : 0] wci_s_4_MByteEn;
// action method wci_s_4_mAddr
input [31 : 0] wci_s_4_MAddr;
// action method wci_s_4_mData
input [31 : 0] wci_s_4_MData;
// value method wci_s_4_sResp
output [1 : 0] wci_s_4_SResp;
// value method wci_s_4_sData
output [31 : 0] wci_s_4_SData;
// value method wci_s_4_sThreadBusy
output wci_s_4_SThreadBusy;
// value method wci_s_4_sFlag
output [1 : 0] wci_s_4_SFlag;
// action method wci_s_4_mFlag
input [1 : 0] wci_s_4_MFlag;
// action method wci_s_5_mCmd
input [2 : 0] wci_s_5_MCmd;
// action method wci_s_5_mAddrSpace
input wci_s_5_MAddrSpace;
// action method wci_s_5_mByteEn
input [3 : 0] wci_s_5_MByteEn;
// action method wci_s_5_mAddr
input [31 : 0] wci_s_5_MAddr;
// action method wci_s_5_mData
input [31 : 0] wci_s_5_MData;
// value method wci_s_5_sResp
output [1 : 0] wci_s_5_SResp;
// value method wci_s_5_sData
output [31 : 0] wci_s_5_SData;
// value method wci_s_5_sThreadBusy
output wci_s_5_SThreadBusy;
// value method wci_s_5_sFlag
output [1 : 0] wci_s_5_SFlag;
// action method wci_s_5_mFlag
input [1 : 0] wci_s_5_MFlag;
// action method wci_s_6_mCmd
input [2 : 0] wci_s_6_MCmd;
// action method wci_s_6_mAddrSpace
input wci_s_6_MAddrSpace;
// action method wci_s_6_mByteEn
input [3 : 0] wci_s_6_MByteEn;
// action method wci_s_6_mAddr
input [31 : 0] wci_s_6_MAddr;
// action method wci_s_6_mData
input [31 : 0] wci_s_6_MData;
// value method wci_s_6_sResp
output [1 : 0] wci_s_6_SResp;
// value method wci_s_6_sData
output [31 : 0] wci_s_6_SData;
// value method wci_s_6_sThreadBusy
output wci_s_6_SThreadBusy;
// value method wci_s_6_sFlag
output [1 : 0] wci_s_6_SFlag;
// action method wci_s_6_mFlag
input [1 : 0] wci_s_6_MFlag;
// action method wci_s_7_mCmd
input [2 : 0] wci_s_7_MCmd;
// action method wci_s_7_mAddrSpace
input wci_s_7_MAddrSpace;
// action method wci_s_7_mByteEn
input [3 : 0] wci_s_7_MByteEn;
// action method wci_s_7_mAddr
input [31 : 0] wci_s_7_MAddr;
// action method wci_s_7_mData
input [31 : 0] wci_s_7_MData;
// value method wci_s_7_sResp
output [1 : 0] wci_s_7_SResp;
// value method wci_s_7_sData
output [31 : 0] wci_s_7_SData;
// value method wci_s_7_sThreadBusy
output wci_s_7_SThreadBusy;
// value method wci_s_7_sFlag
output [1 : 0] wci_s_7_SFlag;
// action method wci_s_7_mFlag
input [1 : 0] wci_s_7_MFlag;
// action method wti_s_0_mCmd
input [2 : 0] wti_s_0_MCmd;
// action method wti_s_0_mData
input [63 : 0] wti_s_0_MData;
// value method wti_s_0_sThreadBusy
output wti_s_0_SThreadBusy;
// value method wti_s_0_sReset_n
output wti_s_0_SReset_n;
// action method wti_s_1_mCmd
input [2 : 0] wti_s_1_MCmd;
// action method wti_s_1_mData
input [63 : 0] wti_s_1_MData;
// value method wti_s_1_sThreadBusy
output wti_s_1_SThreadBusy;
// value method wti_s_1_sReset_n
output wti_s_1_SReset_n;
// action method wti_s_2_mCmd
input [2 : 0] wti_s_2_MCmd;
// action method wti_s_2_mData
input [63 : 0] wti_s_2_MData;
// value method wti_s_2_sThreadBusy
output wti_s_2_SThreadBusy;
// value method wti_s_2_sReset_n
output wti_s_2_SReset_n;
// value method wmiM0_mCmd
output [2 : 0] wmiM0_MCmd;
// value method wmiM0_mReqLast
output wmiM0_MReqLast;
// value method wmiM0_mReqInfo
output wmiM0_MReqInfo;
// value method wmiM0_mAddrSpace
output wmiM0_MAddrSpace;
// value method wmiM0_mAddr
output [13 : 0] wmiM0_MAddr;
// value method wmiM0_mBurstLength
output [11 : 0] wmiM0_MBurstLength;
// value method wmiM0_mDataValid
output wmiM0_MDataValid;
// value method wmiM0_mDataLast
output wmiM0_MDataLast;
// value method wmiM0_mData
output [31 : 0] wmiM0_MData;
// value method wmiM0_mDataInfo
// value method wmiM0_mDataByteEn
output [3 : 0] wmiM0_MDataByteEn;
// action method wmiM0_sResp
input [1 : 0] wmiM0_SResp;
// action method wmiM0_sData
input [31 : 0] wmiM0_SData;
// action method wmiM0_sThreadBusy
input wmiM0_SThreadBusy;
// action method wmiM0_sDataThreadBusy
input wmiM0_SDataThreadBusy;
// action method wmiM0_sRespLast
input wmiM0_SRespLast;
// action method wmiM0_sFlag
input [31 : 0] wmiM0_SFlag;
// value method wmiM0_mFlag
output [31 : 0] wmiM0_MFlag;
// value method wmiM0_mReset_n
output wmiM0_MReset_n;
// action method wmiM0_sReset_n
input wmiM0_SReset_n;
// value method wmiM1_mCmd
output [2 : 0] wmiM1_MCmd;
// value method wmiM1_mReqLast
output wmiM1_MReqLast;
// value method wmiM1_mReqInfo
output wmiM1_MReqInfo;
// value method wmiM1_mAddrSpace
output wmiM1_MAddrSpace;
// value method wmiM1_mAddr
output [13 : 0] wmiM1_MAddr;
// value method wmiM1_mBurstLength
output [11 : 0] wmiM1_MBurstLength;
// value method wmiM1_mDataValid
output wmiM1_MDataValid;
// value method wmiM1_mDataLast
output wmiM1_MDataLast;
// value method wmiM1_mData
output [31 : 0] wmiM1_MData;
// value method wmiM1_mDataInfo
// value method wmiM1_mDataByteEn
output [3 : 0] wmiM1_MDataByteEn;
// action method wmiM1_sResp
input [1 : 0] wmiM1_SResp;
// action method wmiM1_sData
input [31 : 0] wmiM1_SData;
// action method wmiM1_sThreadBusy
input wmiM1_SThreadBusy;
// action method wmiM1_sDataThreadBusy
input wmiM1_SDataThreadBusy;
// action method wmiM1_sRespLast
input wmiM1_SRespLast;
// action method wmiM1_sFlag
input [31 : 0] wmiM1_SFlag;
// value method wmiM1_mFlag
output [31 : 0] wmiM1_MFlag;
// value method wmiM1_mReset_n
output wmiM1_MReset_n;
// action method wmiM1_sReset_n
input wmiM1_SReset_n;
// value method wmemiM0_mCmd
output [2 : 0] wmemiM0_MCmd;
// value method wmemiM0_mReqLast
output wmemiM0_MReqLast;
// value method wmemiM0_mAddr
output [35 : 0] wmemiM0_MAddr;
// value method wmemiM0_mBurstLength
output [11 : 0] wmemiM0_MBurstLength;
// value method wmemiM0_mDataValid
output wmemiM0_MDataValid;
// value method wmemiM0_mDataLast
output wmemiM0_MDataLast;
// value method wmemiM0_mData
output [127 : 0] wmemiM0_MData;
// value method wmemiM0_mDataByteEn
output [15 : 0] wmemiM0_MDataByteEn;
// action method wmemiM0_sResp
input [1 : 0] wmemiM0_SResp;
// action method wmemiM0_sRespLast
input wmemiM0_SRespLast;
// action method wmemiM0_sData
input [127 : 0] wmemiM0_SData;
// action method wmemiM0_sCmdAccept
input wmemiM0_SCmdAccept;
// action method wmemiM0_sDataAccept
input wmemiM0_SDataAccept;
// value method wmemiM0_mReset_n
output wmemiM0_MReset_n;
// action method wsi_s_adc_mCmd
input [2 : 0] wsi_s_adc_MCmd;
// action method wsi_s_adc_mReqLast
input wsi_s_adc_MReqLast;
// action method wsi_s_adc_mBurstPrecise
input wsi_s_adc_MBurstPrecise;
// action method wsi_s_adc_mBurstLength
input [11 : 0] wsi_s_adc_MBurstLength;
// action method wsi_s_adc_mData
input [31 : 0] wsi_s_adc_MData;
// action method wsi_s_adc_mByteEn
input [3 : 0] wsi_s_adc_MByteEn;
// action method wsi_s_adc_mReqInfo
input [7 : 0] wsi_s_adc_MReqInfo;
// action method wsi_s_adc_mDataInfo
// value method wsi_s_adc_sThreadBusy
output wsi_s_adc_SThreadBusy;
// value method wsi_s_adc_sReset_n
output wsi_s_adc_SReset_n;
// action method wsi_s_adc_mReset_n
input wsi_s_adc_MReset_n;
// value method wsi_m_dac_mCmd
output [2 : 0] wsi_m_dac_MCmd;
// value method wsi_m_dac_mReqLast
output wsi_m_dac_MReqLast;
// value method wsi_m_dac_mBurstPrecise
output wsi_m_dac_MBurstPrecise;
// value method wsi_m_dac_mBurstLength
output [11 : 0] wsi_m_dac_MBurstLength;
// value method wsi_m_dac_mData
output [31 : 0] wsi_m_dac_MData;
// value method wsi_m_dac_mByteEn
output [3 : 0] wsi_m_dac_MByteEn;
// value method wsi_m_dac_mReqInfo
output [7 : 0] wsi_m_dac_MReqInfo;
// value method wsi_m_dac_mDataInfo
// action method wsi_m_dac_sThreadBusy
input wsi_m_dac_SThreadBusy;
// value method wsi_m_dac_mReset_n
output wsi_m_dac_MReset_n;
// action method wsi_m_dac_sReset_n
input wsi_m_dac_SReset_n;
// value method uuid
output [511 : 0] uuid;
// signals for module outputs
wire [511 : 0] uuid;
wire [127 : 0] wmemiM0_MData;
wire [35 : 0] wmemiM0_MAddr;
wire [31 : 0] wci_s_0_SData,
wci_s_1_SData,
wci_s_2_SData,
wci_s_3_SData,
wci_s_4_SData,
wci_s_5_SData,
wci_s_6_SData,
wci_s_7_SData,
wmiM0_MData,
wmiM0_MFlag,
wmiM1_MData,
wmiM1_MFlag,
wsi_m_dac_MData;
wire [15 : 0] wmemiM0_MDataByteEn;
wire [13 : 0] wmiM0_MAddr, wmiM1_MAddr;
wire [11 : 0] wmemiM0_MBurstLength,
wmiM0_MBurstLength,
wmiM1_MBurstLength,
wsi_m_dac_MBurstLength;
wire [7 : 0] wsi_m_dac_MReqInfo;
wire [3 : 0] wmiM0_MDataByteEn, wmiM1_MDataByteEn, wsi_m_dac_MByteEn;
wire [2 : 0] wmemiM0_MCmd, wmiM0_MCmd, wmiM1_MCmd, wsi_m_dac_MCmd;
wire [1 : 0] wci_s_0_SFlag,
wci_s_0_SResp,
wci_s_1_SFlag,
wci_s_1_SResp,
wci_s_2_SFlag,
wci_s_2_SResp,
wci_s_3_SFlag,
wci_s_3_SResp,
wci_s_4_SFlag,
wci_s_4_SResp,
wci_s_5_SFlag,
wci_s_5_SResp,
wci_s_6_SFlag,
wci_s_6_SResp,
wci_s_7_SFlag,
wci_s_7_SResp;
wire wci_s_0_SThreadBusy,
wci_s_1_SThreadBusy,
wci_s_2_SThreadBusy,
wci_s_3_SThreadBusy,
wci_s_4_SThreadBusy,
wci_s_5_SThreadBusy,
wci_s_6_SThreadBusy,
wci_s_7_SThreadBusy,
wmemiM0_MDataLast,
wmemiM0_MDataValid,
wmemiM0_MReqLast,
wmemiM0_MReset_n,
wmiM0_MAddrSpace,
wmiM0_MDataLast,
wmiM0_MDataValid,
wmiM0_MReqInfo,
wmiM0_MReqLast,
wmiM0_MReset_n,
wmiM1_MAddrSpace,
wmiM1_MDataLast,
wmiM1_MDataValid,
wmiM1_MReqInfo,
wmiM1_MReqLast,
wmiM1_MReset_n,
wsi_m_dac_MBurstPrecise,
wsi_m_dac_MReqLast,
wsi_m_dac_MReset_n,
wsi_s_adc_SReset_n,
wsi_s_adc_SThreadBusy,
wti_s_0_SReset_n,
wti_s_0_SThreadBusy,
wti_s_1_SReset_n,
wti_s_1_SThreadBusy,
wti_s_2_SReset_n,
wti_s_2_SThreadBusy;
// inlined wires
wire [31 : 0] tieOff0_wci_Es_mAddr_w$wget,
tieOff0_wci_Es_mData_w$wget,
tieOff5_wci_Es_mAddr_w$wget,
tieOff5_wci_Es_mData_w$wget,
tieOff6_wci_Es_mAddr_w$wget,
tieOff6_wci_Es_mData_w$wget,
tieOff7_wci_Es_mAddr_w$wget,
tieOff7_wci_Es_mData_w$wget;
wire [3 : 0] tieOff0_wci_Es_mByteEn_w$wget,
tieOff5_wci_Es_mByteEn_w$wget,
tieOff6_wci_Es_mByteEn_w$wget,
tieOff7_wci_Es_mByteEn_w$wget;
wire [2 : 0] tieOff0_wci_Es_mCmd_w$wget,
tieOff5_wci_Es_mCmd_w$wget,
tieOff6_wci_Es_mCmd_w$wget,
tieOff7_wci_Es_mCmd_w$wget;
wire tieOff0_wci_Es_mAddrSpace_w$wget,
tieOff0_wci_Es_mAddrSpace_w$whas,
tieOff0_wci_Es_mAddr_w$whas,
tieOff0_wci_Es_mByteEn_w$whas,
tieOff0_wci_Es_mCmd_w$whas,
tieOff0_wci_Es_mData_w$whas,
tieOff5_wci_Es_mAddrSpace_w$wget,
tieOff5_wci_Es_mAddrSpace_w$whas,
tieOff5_wci_Es_mAddr_w$whas,
tieOff5_wci_Es_mByteEn_w$whas,
tieOff5_wci_Es_mCmd_w$whas,
tieOff5_wci_Es_mData_w$whas,
tieOff6_wci_Es_mAddrSpace_w$wget,
tieOff6_wci_Es_mAddrSpace_w$whas,
tieOff6_wci_Es_mAddr_w$whas,
tieOff6_wci_Es_mByteEn_w$whas,
tieOff6_wci_Es_mCmd_w$whas,
tieOff6_wci_Es_mData_w$whas,
tieOff7_wci_Es_mAddrSpace_w$wget,
tieOff7_wci_Es_mAddrSpace_w$whas,
tieOff7_wci_Es_mAddr_w$whas,
tieOff7_wci_Es_mByteEn_w$whas,
tieOff7_wci_Es_mCmd_w$whas,
tieOff7_wci_Es_mData_w$whas;
// ports of submodule appW1
wire [127 : 0] appW1$wmemiM0_MData, appW1$wmemiM0_SData;
wire [35 : 0] appW1$wmemiM0_MAddr;
wire [31 : 0] appW1$wciS0_MAddr, appW1$wciS0_MData, appW1$wciS0_SData;
wire [15 : 0] appW1$wmemiM0_MDataByteEn;
wire [11 : 0] appW1$wmemiM0_MBurstLength;
wire [3 : 0] appW1$wciS0_MByteEn;
wire [2 : 0] appW1$wciS0_MCmd, appW1$wmemiM0_MCmd;
wire [1 : 0] appW1$wciS0_MFlag,
appW1$wciS0_SFlag,
appW1$wciS0_SResp,
appW1$wmemiM0_SResp;
wire appW1$wciS0_MAddrSpace,
appW1$wciS0_SThreadBusy,
appW1$wmemiM0_MDataLast,
appW1$wmemiM0_MDataValid,
appW1$wmemiM0_MReqLast,
appW1$wmemiM0_MReset_n,
appW1$wmemiM0_SCmdAccept,
appW1$wmemiM0_SDataAccept,
appW1$wmemiM0_SRespLast;
// ports of submodule appW2
wire [31 : 0] appW2$wciS0_MAddr,
appW2$wciS0_MData,
appW2$wciS0_SData,
appW2$wmiM0_MData,
appW2$wmiM0_MFlag,
appW2$wmiM0_SData,
appW2$wmiM0_SFlag,
appW2$wsiM0_MData,
appW2$wsiS0_MData;
wire [13 : 0] appW2$wmiM0_MAddr;
wire [11 : 0] appW2$wmiM0_MBurstLength,
appW2$wsiM0_MBurstLength,
appW2$wsiS0_MBurstLength;
wire [7 : 0] appW2$wsiM0_MReqInfo, appW2$wsiS0_MReqInfo;
wire [3 : 0] appW2$wciS0_MByteEn,
appW2$wmiM0_MDataByteEn,
appW2$wsiM0_MByteEn,
appW2$wsiS0_MByteEn;
wire [2 : 0] appW2$wciS0_MCmd,
appW2$wmiM0_MCmd,
appW2$wsiM0_MCmd,
appW2$wsiS0_MCmd;
wire [1 : 0] appW2$wciS0_MFlag,
appW2$wciS0_SFlag,
appW2$wciS0_SResp,
appW2$wmiM0_SResp;
wire appW2$wciS0_MAddrSpace,
appW2$wciS0_SThreadBusy,
appW2$wmiM0_MAddrSpace,
appW2$wmiM0_MDataLast,
appW2$wmiM0_MDataValid,
appW2$wmiM0_MReqInfo,
appW2$wmiM0_MReqLast,
appW2$wmiM0_MReset_n,
appW2$wmiM0_SDataThreadBusy,
appW2$wmiM0_SReset_n,
appW2$wmiM0_SRespLast,
appW2$wmiM0_SThreadBusy,
appW2$wsiM0_MBurstPrecise,
appW2$wsiM0_MReqLast,
appW2$wsiM0_MReset_n,
appW2$wsiM0_SReset_n,
appW2$wsiM0_SThreadBusy,
appW2$wsiS0_MBurstPrecise,
appW2$wsiS0_MReqLast,
appW2$wsiS0_MReset_n,
appW2$wsiS0_SReset_n,
appW2$wsiS0_SThreadBusy;
// ports of submodule appW3
wire [31 : 0] appW3$wciS0_MAddr,
appW3$wciS0_MData,
appW3$wciS0_SData,
appW3$wsiM0_MData,
appW3$wsiS0_MData;
wire [11 : 0] appW3$wsiM0_MBurstLength, appW3$wsiS0_MBurstLength;
wire [7 : 0] appW3$wsiM0_MReqInfo, appW3$wsiS0_MReqInfo;
wire [3 : 0] appW3$wciS0_MByteEn, appW3$wsiM0_MByteEn, appW3$wsiS0_MByteEn;
wire [2 : 0] appW3$wciS0_MCmd, appW3$wsiM0_MCmd, appW3$wsiS0_MCmd;
wire [1 : 0] appW3$wciS0_MFlag, appW3$wciS0_SFlag, appW3$wciS0_SResp;
wire appW3$wciS0_MAddrSpace,
appW3$wciS0_SThreadBusy,
appW3$wsiM0_MBurstPrecise,
appW3$wsiM0_MReqLast,
appW3$wsiM0_MReset_n,
appW3$wsiM0_SReset_n,
appW3$wsiM0_SThreadBusy,
appW3$wsiS0_MBurstPrecise,
appW3$wsiS0_MReqLast,
appW3$wsiS0_MReset_n,
appW3$wsiS0_SReset_n,
appW3$wsiS0_SThreadBusy;
// ports of submodule appW4
wire [31 : 0] appW4$wciS0_MAddr,
appW4$wciS0_MData,
appW4$wciS0_SData,
appW4$wmiM0_MData,
appW4$wmiM0_MFlag,
appW4$wmiM0_SData,
appW4$wmiM0_SFlag,
appW4$wsiM0_MData,
appW4$wsiS0_MData;
wire [13 : 0] appW4$wmiM0_MAddr;
wire [11 : 0] appW4$wmiM0_MBurstLength,
appW4$wsiM0_MBurstLength,
appW4$wsiS0_MBurstLength;
wire [7 : 0] appW4$wsiM0_MReqInfo, appW4$wsiS0_MReqInfo;
wire [3 : 0] appW4$wciS0_MByteEn,
appW4$wmiM0_MDataByteEn,
appW4$wsiM0_MByteEn,
appW4$wsiS0_MByteEn;
wire [2 : 0] appW4$wciS0_MCmd,
appW4$wmiM0_MCmd,
appW4$wsiM0_MCmd,
appW4$wsiS0_MCmd;
wire [1 : 0] appW4$wciS0_MFlag,
appW4$wciS0_SFlag,
appW4$wciS0_SResp,
appW4$wmiM0_SResp;
wire appW4$wciS0_MAddrSpace,
appW4$wciS0_SThreadBusy,
appW4$wmiM0_MAddrSpace,
appW4$wmiM0_MDataLast,
appW4$wmiM0_MDataValid,
appW4$wmiM0_MReqInfo,
appW4$wmiM0_MReqLast,
appW4$wmiM0_MReset_n,
appW4$wmiM0_SDataThreadBusy,
appW4$wmiM0_SReset_n,
appW4$wmiM0_SRespLast,
appW4$wmiM0_SThreadBusy,
appW4$wsiM0_MBurstPrecise,
appW4$wsiM0_MReqLast,
appW4$wsiM0_MReset_n,
appW4$wsiM0_SReset_n,
appW4$wsiM0_SThreadBusy,
appW4$wsiS0_MBurstPrecise,
appW4$wsiS0_MReqLast,
appW4$wsiS0_MReset_n,
appW4$wsiS0_SReset_n,
appW4$wsiS0_SThreadBusy;
// ports of submodule id
wire [511 : 0] id$uuid;
// value method wci_s_0_sResp
assign wci_s_0_SResp = 2'd0 ;
// value method wci_s_0_sData
assign wci_s_0_SData = 32'hAAAAAAAA ;
// value method wci_s_0_sThreadBusy
assign wci_s_0_SThreadBusy = 1'd1 ;
// value method wci_s_0_sFlag
assign wci_s_0_SFlag = 2'b0 ;
// value method wci_s_1_sResp
assign wci_s_1_SResp = appW1$wciS0_SResp ;
// value method wci_s_1_sData
assign wci_s_1_SData = appW1$wciS0_SData ;
// value method wci_s_1_sThreadBusy
assign wci_s_1_SThreadBusy = appW1$wciS0_SThreadBusy ;
// value method wci_s_1_sFlag
assign wci_s_1_SFlag = appW1$wciS0_SFlag ;
// value method wci_s_2_sResp
assign wci_s_2_SResp = appW2$wciS0_SResp ;
// value method wci_s_2_sData
assign wci_s_2_SData = appW2$wciS0_SData ;
// value method wci_s_2_sThreadBusy
assign wci_s_2_SThreadBusy = appW2$wciS0_SThreadBusy ;
// value method wci_s_2_sFlag
assign wci_s_2_SFlag = appW2$wciS0_SFlag ;
// value method wci_s_3_sResp
assign wci_s_3_SResp = appW3$wciS0_SResp ;
// value method wci_s_3_sData
assign wci_s_3_SData = appW3$wciS0_SData ;
// value method wci_s_3_sThreadBusy
assign wci_s_3_SThreadBusy = appW3$wciS0_SThreadBusy ;
// value method wci_s_3_sFlag
assign wci_s_3_SFlag = appW3$wciS0_SFlag ;
// value method wci_s_4_sResp
assign wci_s_4_SResp = appW4$wciS0_SResp ;
// value method wci_s_4_sData
assign wci_s_4_SData = appW4$wciS0_SData ;
// value method wci_s_4_sThreadBusy
assign wci_s_4_SThreadBusy = appW4$wciS0_SThreadBusy ;
// value method wci_s_4_sFlag
assign wci_s_4_SFlag = appW4$wciS0_SFlag ;
// value method wci_s_5_sResp
assign wci_s_5_SResp = 2'd0 ;
// value method wci_s_5_sData
assign wci_s_5_SData = 32'hAAAAAAAA ;
// value method wci_s_5_sThreadBusy
assign wci_s_5_SThreadBusy = 1'd1 ;
// value method wci_s_5_sFlag
assign wci_s_5_SFlag = 2'b0 ;
// value method wci_s_6_sResp
assign wci_s_6_SResp = 2'd0 ;
// value method wci_s_6_sData
assign wci_s_6_SData = 32'hAAAAAAAA ;
// value method wci_s_6_sThreadBusy
assign wci_s_6_SThreadBusy = 1'd1 ;
// value method wci_s_6_sFlag
assign wci_s_6_SFlag = 2'b0 ;
// value method wci_s_7_sResp
assign wci_s_7_SResp = 2'd0 ;
// value method wci_s_7_sData
assign wci_s_7_SData = 32'hAAAAAAAA ;
// value method wci_s_7_sThreadBusy
assign wci_s_7_SThreadBusy = 1'd1 ;
// value method wci_s_7_sFlag
assign wci_s_7_SFlag = 2'b0 ;
// value method wti_s_0_sThreadBusy
assign wti_s_0_SThreadBusy = 1'h0 ;
// value method wti_s_0_sReset_n
assign wti_s_0_SReset_n = 1'h0 ;
// value method wti_s_1_sThreadBusy
assign wti_s_1_SThreadBusy = 1'h0 ;
// value method wti_s_1_sReset_n
assign wti_s_1_SReset_n = 1'h0 ;
// value method wti_s_2_sThreadBusy
assign wti_s_2_SThreadBusy = 1'h0 ;
// value method wti_s_2_sReset_n
assign wti_s_2_SReset_n = 1'h0 ;
// value method wmiM0_mCmd
assign wmiM0_MCmd = appW2$wmiM0_MCmd ;
// value method wmiM0_mReqLast
assign wmiM0_MReqLast = appW2$wmiM0_MReqLast ;
// value method wmiM0_mReqInfo
assign wmiM0_MReqInfo = appW2$wmiM0_MReqInfo ;
// value method wmiM0_mAddrSpace
assign wmiM0_MAddrSpace = appW2$wmiM0_MAddrSpace ;
// value method wmiM0_mAddr
assign wmiM0_MAddr = appW2$wmiM0_MAddr ;
// value method wmiM0_mBurstLength
assign wmiM0_MBurstLength = appW2$wmiM0_MBurstLength ;
// value method wmiM0_mDataValid
assign wmiM0_MDataValid = appW2$wmiM0_MDataValid ;
// value method wmiM0_mDataLast
assign wmiM0_MDataLast = appW2$wmiM0_MDataLast ;
// value method wmiM0_mData
assign wmiM0_MData = appW2$wmiM0_MData ;
// value method wmiM0_mDataByteEn
assign wmiM0_MDataByteEn = appW2$wmiM0_MDataByteEn ;
// value method wmiM0_mFlag
assign wmiM0_MFlag = appW2$wmiM0_MFlag ;
// value method wmiM0_mReset_n
assign wmiM0_MReset_n = appW2$wmiM0_MReset_n ;
// value method wmiM1_mCmd
assign wmiM1_MCmd = appW4$wmiM0_MCmd ;
// value method wmiM1_mReqLast
assign wmiM1_MReqLast = appW4$wmiM0_MReqLast ;
// value method wmiM1_mReqInfo
assign wmiM1_MReqInfo = appW4$wmiM0_MReqInfo ;
// value method wmiM1_mAddrSpace
assign wmiM1_MAddrSpace = appW4$wmiM0_MAddrSpace ;
// value method wmiM1_mAddr
assign wmiM1_MAddr = appW4$wmiM0_MAddr ;
// value method wmiM1_mBurstLength
assign wmiM1_MBurstLength = appW4$wmiM0_MBurstLength ;
// value method wmiM1_mDataValid
assign wmiM1_MDataValid = appW4$wmiM0_MDataValid ;
// value method wmiM1_mDataLast
assign wmiM1_MDataLast = appW4$wmiM0_MDataLast ;
// value method wmiM1_mData
assign wmiM1_MData = appW4$wmiM0_MData ;
// value method wmiM1_mDataByteEn
assign wmiM1_MDataByteEn = appW4$wmiM0_MDataByteEn ;
// value method wmiM1_mFlag
assign wmiM1_MFlag = appW4$wmiM0_MFlag ;
// value method wmiM1_mReset_n
assign wmiM1_MReset_n = appW4$wmiM0_MReset_n ;
// value method wmemiM0_mCmd
assign wmemiM0_MCmd = appW1$wmemiM0_MCmd ;
// value method wmemiM0_mReqLast
assign wmemiM0_MReqLast = appW1$wmemiM0_MReqLast ;
// value method wmemiM0_mAddr
assign wmemiM0_MAddr = appW1$wmemiM0_MAddr ;
// value method wmemiM0_mBurstLength
assign wmemiM0_MBurstLength = appW1$wmemiM0_MBurstLength ;
// value method wmemiM0_mDataValid
assign wmemiM0_MDataValid = appW1$wmemiM0_MDataValid ;
// value method wmemiM0_mDataLast
assign wmemiM0_MDataLast = appW1$wmemiM0_MDataLast ;
// value method wmemiM0_mData
assign wmemiM0_MData = appW1$wmemiM0_MData ;
// value method wmemiM0_mDataByteEn
assign wmemiM0_MDataByteEn = appW1$wmemiM0_MDataByteEn ;
// value method wmemiM0_mReset_n
assign wmemiM0_MReset_n = appW1$wmemiM0_MReset_n ;
// value method wsi_s_adc_sThreadBusy
assign wsi_s_adc_SThreadBusy = appW2$wsiS0_SThreadBusy ;
// value method wsi_s_adc_sReset_n
assign wsi_s_adc_SReset_n = appW2$wsiS0_SReset_n ;
// value method wsi_m_dac_mCmd
assign wsi_m_dac_MCmd = appW4$wsiM0_MCmd ;
// value method wsi_m_dac_mReqLast
assign wsi_m_dac_MReqLast = appW4$wsiM0_MReqLast ;
// value method wsi_m_dac_mBurstPrecise
assign wsi_m_dac_MBurstPrecise = appW4$wsiM0_MBurstPrecise ;
// value method wsi_m_dac_mBurstLength
assign wsi_m_dac_MBurstLength = appW4$wsiM0_MBurstLength ;
// value method wsi_m_dac_mData
assign wsi_m_dac_MData = appW4$wsiM0_MData ;
// value method wsi_m_dac_mByteEn
assign wsi_m_dac_MByteEn = appW4$wsiM0_MByteEn ;
// value method wsi_m_dac_mReqInfo
assign wsi_m_dac_MReqInfo = appW4$wsiM0_MReqInfo ;
// value method wsi_m_dac_mReset_n
assign wsi_m_dac_MReset_n = appW4$wsiM0_MReset_n ;
// value method uuid
assign uuid = id$uuid ;
// submodule appW1
mkMemiTestWorker #(.hasDebugLogic(hasDebugLogic)) appW1(.wciS0_Clk(CLK),
.wciS0_MReset_n(RST_N_rst_1),
.wciS0_MAddr(appW1$wciS0_MAddr),
.wciS0_MAddrSpace(appW1$wciS0_MAddrSpace),
.wciS0_MByteEn(appW1$wciS0_MByteEn),
.wciS0_MCmd(appW1$wciS0_MCmd),
.wciS0_MData(appW1$wciS0_MData),
.wciS0_MFlag(appW1$wciS0_MFlag),
.wmemiM0_SData(appW1$wmemiM0_SData),
.wmemiM0_SResp(appW1$wmemiM0_SResp),
.wmemiM0_SRespLast(appW1$wmemiM0_SRespLast),
.wmemiM0_SCmdAccept(appW1$wmemiM0_SCmdAccept),
.wmemiM0_SDataAccept(appW1$wmemiM0_SDataAccept),
.wciS0_SResp(appW1$wciS0_SResp),
.wciS0_SData(appW1$wciS0_SData),
.wciS0_SThreadBusy(appW1$wciS0_SThreadBusy),
.wciS0_SFlag(appW1$wciS0_SFlag),
.wmemiM0_MCmd(appW1$wmemiM0_MCmd),
.wmemiM0_MReqLast(appW1$wmemiM0_MReqLast),
.wmemiM0_MAddr(appW1$wmemiM0_MAddr),
.wmemiM0_MBurstLength(appW1$wmemiM0_MBurstLength),
.wmemiM0_MDataValid(appW1$wmemiM0_MDataValid),
.wmemiM0_MDataLast(appW1$wmemiM0_MDataLast),
.wmemiM0_MData(appW1$wmemiM0_MData),
.wmemiM0_MDataByteEn(appW1$wmemiM0_MDataByteEn),
.wmemiM0_MReset_n(appW1$wmemiM0_MReset_n));
// submodule appW2
mkSMAdapter4B #(.smaCtrlInit(32'h00000001),
.hasDebugLogic(hasDebugLogic)) appW2(.wciS0_Clk(CLK),
.wciS0_MReset_n(RST_N_rst_2),
.wciS0_MAddr(appW2$wciS0_MAddr),
.wciS0_MAddrSpace(appW2$wciS0_MAddrSpace),
.wciS0_MByteEn(appW2$wciS0_MByteEn),
.wciS0_MCmd(appW2$wciS0_MCmd),
.wciS0_MData(appW2$wciS0_MData),
.wciS0_MFlag(appW2$wciS0_MFlag),
.wmiM0_SData(appW2$wmiM0_SData),
.wmiM0_SFlag(appW2$wmiM0_SFlag),
.wmiM0_SResp(appW2$wmiM0_SResp),
.wsiS0_MBurstLength(appW2$wsiS0_MBurstLength),
.wsiS0_MByteEn(appW2$wsiS0_MByteEn),
.wsiS0_MCmd(appW2$wsiS0_MCmd),
.wsiS0_MData(appW2$wsiS0_MData),
.wsiS0_MReqInfo(appW2$wsiS0_MReqInfo),
.wmiM0_SThreadBusy(appW2$wmiM0_SThreadBusy),
.wmiM0_SDataThreadBusy(appW2$wmiM0_SDataThreadBusy),
.wmiM0_SRespLast(appW2$wmiM0_SRespLast),
.wmiM0_SReset_n(appW2$wmiM0_SReset_n),
.wsiM0_SThreadBusy(appW2$wsiM0_SThreadBusy),
.wsiM0_SReset_n(appW2$wsiM0_SReset_n),
.wsiS0_MReqLast(appW2$wsiS0_MReqLast),
.wsiS0_MBurstPrecise(appW2$wsiS0_MBurstPrecise),
.wsiS0_MReset_n(appW2$wsiS0_MReset_n),
.wciS0_SResp(appW2$wciS0_SResp),
.wciS0_SData(appW2$wciS0_SData),
.wciS0_SThreadBusy(appW2$wciS0_SThreadBusy),
.wciS0_SFlag(appW2$wciS0_SFlag),
.wmiM0_MCmd(appW2$wmiM0_MCmd),
.wmiM0_MReqLast(appW2$wmiM0_MReqLast),
.wmiM0_MReqInfo(appW2$wmiM0_MReqInfo),
.wmiM0_MAddrSpace(appW2$wmiM0_MAddrSpace),
.wmiM0_MAddr(appW2$wmiM0_MAddr),
.wmiM0_MBurstLength(appW2$wmiM0_MBurstLength),
.wmiM0_MDataValid(appW2$wmiM0_MDataValid),
.wmiM0_MDataLast(appW2$wmiM0_MDataLast),
.wmiM0_MData(appW2$wmiM0_MData),
.wmiM0_MDataByteEn(appW2$wmiM0_MDataByteEn),
.wmiM0_MFlag(appW2$wmiM0_MFlag),
.wmiM0_MReset_n(appW2$wmiM0_MReset_n),
.wsiM0_MCmd(appW2$wsiM0_MCmd),
.wsiM0_MReqLast(appW2$wsiM0_MReqLast),
.wsiM0_MBurstPrecise(appW2$wsiM0_MBurstPrecise),
.wsiM0_MBurstLength(appW2$wsiM0_MBurstLength),
.wsiM0_MData(appW2$wsiM0_MData),
.wsiM0_MByteEn(appW2$wsiM0_MByteEn),
.wsiM0_MReqInfo(appW2$wsiM0_MReqInfo),
.wsiM0_MReset_n(appW2$wsiM0_MReset_n),
.wsiS0_SThreadBusy(appW2$wsiS0_SThreadBusy),
.wsiS0_SReset_n(appW2$wsiS0_SReset_n));
// submodule appW3
mkBiasWorker4B #(.hasDebugLogic(hasDebugLogic)) appW3(.wciS0_Clk(CLK),
.wciS0_MReset_n(RST_N_rst_3),
.wciS0_MAddr(appW3$wciS0_MAddr),
.wciS0_MAddrSpace(appW3$wciS0_MAddrSpace),
.wciS0_MByteEn(appW3$wciS0_MByteEn),
.wciS0_MCmd(appW3$wciS0_MCmd),
.wciS0_MData(appW3$wciS0_MData),
.wciS0_MFlag(appW3$wciS0_MFlag),
.wsiS0_MBurstLength(appW3$wsiS0_MBurstLength),
.wsiS0_MByteEn(appW3$wsiS0_MByteEn),
.wsiS0_MCmd(appW3$wsiS0_MCmd),
.wsiS0_MData(appW3$wsiS0_MData),
.wsiS0_MReqInfo(appW3$wsiS0_MReqInfo),
.wsiS0_MReqLast(appW3$wsiS0_MReqLast),
.wsiS0_MBurstPrecise(appW3$wsiS0_MBurstPrecise),
.wsiS0_MReset_n(appW3$wsiS0_MReset_n),
.wsiM0_SThreadBusy(appW3$wsiM0_SThreadBusy),
.wsiM0_SReset_n(appW3$wsiM0_SReset_n),
.wciS0_SResp(appW3$wciS0_SResp),
.wciS0_SData(appW3$wciS0_SData),
.wciS0_SThreadBusy(appW3$wciS0_SThreadBusy),
.wciS0_SFlag(appW3$wciS0_SFlag),
.wsiS0_SThreadBusy(appW3$wsiS0_SThreadBusy),
.wsiS0_SReset_n(appW3$wsiS0_SReset_n),
.wsiM0_MCmd(appW3$wsiM0_MCmd),
.wsiM0_MReqLast(appW3$wsiM0_MReqLast),
.wsiM0_MBurstPrecise(appW3$wsiM0_MBurstPrecise),
.wsiM0_MBurstLength(appW3$wsiM0_MBurstLength),
.wsiM0_MData(appW3$wsiM0_MData),
.wsiM0_MByteEn(appW3$wsiM0_MByteEn),
.wsiM0_MReqInfo(appW3$wsiM0_MReqInfo),
.wsiM0_MReset_n(appW3$wsiM0_MReset_n));
// submodule appW4
mkSMAdapter4B #(.smaCtrlInit(32'h00000002),
.hasDebugLogic(hasDebugLogic)) appW4(.wciS0_Clk(CLK),
.wciS0_MReset_n(RST_N_rst_4),
.wciS0_MAddr(appW4$wciS0_MAddr),
.wciS0_MAddrSpace(appW4$wciS0_MAddrSpace),
.wciS0_MByteEn(appW4$wciS0_MByteEn),
.wciS0_MCmd(appW4$wciS0_MCmd),
.wciS0_MData(appW4$wciS0_MData),
.wciS0_MFlag(appW4$wciS0_MFlag),
.wmiM0_SData(appW4$wmiM0_SData),
.wmiM0_SFlag(appW4$wmiM0_SFlag),
.wmiM0_SResp(appW4$wmiM0_SResp),
.wsiS0_MBurstLength(appW4$wsiS0_MBurstLength),
.wsiS0_MByteEn(appW4$wsiS0_MByteEn),
.wsiS0_MCmd(appW4$wsiS0_MCmd),
.wsiS0_MData(appW4$wsiS0_MData),
.wsiS0_MReqInfo(appW4$wsiS0_MReqInfo),
.wmiM0_SThreadBusy(appW4$wmiM0_SThreadBusy),
.wmiM0_SDataThreadBusy(appW4$wmiM0_SDataThreadBusy),
.wmiM0_SRespLast(appW4$wmiM0_SRespLast),
.wmiM0_SReset_n(appW4$wmiM0_SReset_n),
.wsiM0_SThreadBusy(appW4$wsiM0_SThreadBusy),
.wsiM0_SReset_n(appW4$wsiM0_SReset_n),
.wsiS0_MReqLast(appW4$wsiS0_MReqLast),
.wsiS0_MBurstPrecise(appW4$wsiS0_MBurstPrecise),
.wsiS0_MReset_n(appW4$wsiS0_MReset_n),
.wciS0_SResp(appW4$wciS0_SResp),
.wciS0_SData(appW4$wciS0_SData),
.wciS0_SThreadBusy(appW4$wciS0_SThreadBusy),
.wciS0_SFlag(appW4$wciS0_SFlag),
.wmiM0_MCmd(appW4$wmiM0_MCmd),
.wmiM0_MReqLast(appW4$wmiM0_MReqLast),
.wmiM0_MReqInfo(appW4$wmiM0_MReqInfo),
.wmiM0_MAddrSpace(appW4$wmiM0_MAddrSpace),
.wmiM0_MAddr(appW4$wmiM0_MAddr),
.wmiM0_MBurstLength(appW4$wmiM0_MBurstLength),
.wmiM0_MDataValid(appW4$wmiM0_MDataValid),
.wmiM0_MDataLast(appW4$wmiM0_MDataLast),
.wmiM0_MData(appW4$wmiM0_MData),
.wmiM0_MDataByteEn(appW4$wmiM0_MDataByteEn),
.wmiM0_MFlag(appW4$wmiM0_MFlag),
.wmiM0_MReset_n(appW4$wmiM0_MReset_n),
.wsiM0_MCmd(appW4$wsiM0_MCmd),
.wsiM0_MReqLast(appW4$wsiM0_MReqLast),
.wsiM0_MBurstPrecise(appW4$wsiM0_MBurstPrecise),
.wsiM0_MBurstLength(appW4$wsiM0_MBurstLength),
.wsiM0_MData(appW4$wsiM0_MData),
.wsiM0_MByteEn(appW4$wsiM0_MByteEn),
.wsiM0_MReqInfo(appW4$wsiM0_MReqInfo),
.wsiM0_MReset_n(appW4$wsiM0_MReset_n),
.wsiS0_SThreadBusy(appW4$wsiS0_SThreadBusy),
.wsiS0_SReset_n(appW4$wsiS0_SReset_n));
// submodule id
mkUUID id(.uuid(id$uuid));
// inlined wires
assign tieOff0_wci_Es_mCmd_w$wget = wci_s_0_MCmd ;
assign tieOff0_wci_Es_mCmd_w$whas = 1'd1 ;
assign tieOff0_wci_Es_mAddrSpace_w$wget = wci_s_0_MAddrSpace ;
assign tieOff0_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign tieOff0_wci_Es_mByteEn_w$wget = wci_s_0_MByteEn ;
assign tieOff0_wci_Es_mByteEn_w$whas = 1'd1 ;
assign tieOff0_wci_Es_mAddr_w$wget = wci_s_0_MAddr ;
assign tieOff0_wci_Es_mAddr_w$whas = 1'd1 ;
assign tieOff0_wci_Es_mData_w$wget = wci_s_0_MData ;
assign tieOff0_wci_Es_mData_w$whas = 1'd1 ;
assign tieOff5_wci_Es_mCmd_w$wget = wci_s_5_MCmd ;
assign tieOff5_wci_Es_mCmd_w$whas = 1'd1 ;
assign tieOff5_wci_Es_mAddrSpace_w$wget = wci_s_5_MAddrSpace ;
assign tieOff5_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign tieOff5_wci_Es_mByteEn_w$wget = wci_s_5_MByteEn ;
assign tieOff5_wci_Es_mByteEn_w$whas = 1'd1 ;
assign tieOff5_wci_Es_mAddr_w$wget = wci_s_5_MAddr ;
assign tieOff5_wci_Es_mAddr_w$whas = 1'd1 ;
assign tieOff5_wci_Es_mData_w$wget = wci_s_5_MData ;
assign tieOff5_wci_Es_mData_w$whas = 1'd1 ;
assign tieOff6_wci_Es_mCmd_w$wget = wci_s_6_MCmd ;
assign tieOff6_wci_Es_mCmd_w$whas = 1'd1 ;
assign tieOff6_wci_Es_mAddrSpace_w$wget = wci_s_6_MAddrSpace ;
assign tieOff6_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign tieOff6_wci_Es_mByteEn_w$wget = wci_s_6_MByteEn ;
assign tieOff6_wci_Es_mByteEn_w$whas = 1'd1 ;
assign tieOff6_wci_Es_mAddr_w$wget = wci_s_6_MAddr ;
assign tieOff6_wci_Es_mAddr_w$whas = 1'd1 ;
assign tieOff6_wci_Es_mData_w$wget = wci_s_6_MData ;
assign tieOff6_wci_Es_mData_w$whas = 1'd1 ;
assign tieOff7_wci_Es_mCmd_w$wget = wci_s_7_MCmd ;
assign tieOff7_wci_Es_mCmd_w$whas = 1'd1 ;
assign tieOff7_wci_Es_mAddrSpace_w$wget = wci_s_7_MAddrSpace ;
assign tieOff7_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign tieOff7_wci_Es_mByteEn_w$wget = wci_s_7_MByteEn ;
assign tieOff7_wci_Es_mByteEn_w$whas = 1'd1 ;
assign tieOff7_wci_Es_mAddr_w$wget = wci_s_7_MAddr ;
assign tieOff7_wci_Es_mAddr_w$whas = 1'd1 ;
assign tieOff7_wci_Es_mData_w$wget = wci_s_7_MData ;
assign tieOff7_wci_Es_mData_w$whas = 1'd1 ;
// submodule appW1
assign appW1$wciS0_MAddr = wci_s_1_MAddr ;
assign appW1$wciS0_MAddrSpace = wci_s_1_MAddrSpace ;
assign appW1$wciS0_MByteEn = wci_s_1_MByteEn ;
assign appW1$wciS0_MCmd = wci_s_1_MCmd ;
assign appW1$wciS0_MData = wci_s_1_MData ;
assign appW1$wciS0_MFlag = wci_s_1_MFlag ;
assign appW1$wmemiM0_SData = wmemiM0_SData ;
assign appW1$wmemiM0_SResp = wmemiM0_SResp ;
assign appW1$wmemiM0_SRespLast = wmemiM0_SRespLast ;
assign appW1$wmemiM0_SCmdAccept = wmemiM0_SCmdAccept ;
assign appW1$wmemiM0_SDataAccept = wmemiM0_SDataAccept ;
// submodule appW2
assign appW2$wciS0_MAddr = wci_s_2_MAddr ;
assign appW2$wciS0_MAddrSpace = wci_s_2_MAddrSpace ;
assign appW2$wciS0_MByteEn = wci_s_2_MByteEn ;
assign appW2$wciS0_MCmd = wci_s_2_MCmd ;
assign appW2$wciS0_MData = wci_s_2_MData ;
assign appW2$wciS0_MFlag = wci_s_2_MFlag ;
assign appW2$wmiM0_SData = wmiM0_SData ;
assign appW2$wmiM0_SFlag = wmiM0_SFlag ;
assign appW2$wmiM0_SResp = wmiM0_SResp ;
assign appW2$wsiS0_MBurstLength = wsi_s_adc_MBurstLength ;
assign appW2$wsiS0_MByteEn = wsi_s_adc_MByteEn ;
assign appW2$wsiS0_MCmd = wsi_s_adc_MCmd ;
assign appW2$wsiS0_MData = wsi_s_adc_MData ;
assign appW2$wsiS0_MReqInfo = wsi_s_adc_MReqInfo ;
assign appW2$wmiM0_SThreadBusy = wmiM0_SThreadBusy ;
assign appW2$wmiM0_SDataThreadBusy = wmiM0_SDataThreadBusy ;
assign appW2$wmiM0_SRespLast = wmiM0_SRespLast ;
assign appW2$wmiM0_SReset_n = wmiM0_SReset_n ;
assign appW2$wsiM0_SThreadBusy = appW3$wsiS0_SThreadBusy ;
assign appW2$wsiM0_SReset_n = appW3$wsiS0_SReset_n ;
assign appW2$wsiS0_MReqLast = wsi_s_adc_MReqLast ;
assign appW2$wsiS0_MBurstPrecise = wsi_s_adc_MBurstPrecise ;
assign appW2$wsiS0_MReset_n = wsi_s_adc_MReset_n ;
// submodule appW3
assign appW3$wciS0_MAddr = wci_s_3_MAddr ;
assign appW3$wciS0_MAddrSpace = wci_s_3_MAddrSpace ;
assign appW3$wciS0_MByteEn = wci_s_3_MByteEn ;
assign appW3$wciS0_MCmd = wci_s_3_MCmd ;
assign appW3$wciS0_MData = wci_s_3_MData ;
assign appW3$wciS0_MFlag = wci_s_3_MFlag ;
assign appW3$wsiS0_MBurstLength = appW2$wsiM0_MBurstLength ;
assign appW3$wsiS0_MByteEn = appW2$wsiM0_MByteEn ;
assign appW3$wsiS0_MCmd = appW2$wsiM0_MCmd ;
assign appW3$wsiS0_MData = appW2$wsiM0_MData ;
assign appW3$wsiS0_MReqInfo = appW2$wsiM0_MReqInfo ;
assign appW3$wsiS0_MReqLast = appW2$wsiM0_MReqLast ;
assign appW3$wsiS0_MBurstPrecise = appW2$wsiM0_MBurstPrecise ;
assign appW3$wsiS0_MReset_n = appW2$wsiM0_MReset_n ;
assign appW3$wsiM0_SThreadBusy = appW4$wsiS0_SThreadBusy ;
assign appW3$wsiM0_SReset_n = appW4$wsiS0_SReset_n ;
// submodule appW4
assign appW4$wciS0_MAddr = wci_s_4_MAddr ;
assign appW4$wciS0_MAddrSpace = wci_s_4_MAddrSpace ;
assign appW4$wciS0_MByteEn = wci_s_4_MByteEn ;
assign appW4$wciS0_MCmd = wci_s_4_MCmd ;
assign appW4$wciS0_MData = wci_s_4_MData ;
assign appW4$wciS0_MFlag = wci_s_4_MFlag ;
assign appW4$wmiM0_SData = wmiM1_SData ;
assign appW4$wmiM0_SFlag = wmiM1_SFlag ;
assign appW4$wmiM0_SResp = wmiM1_SResp ;
assign appW4$wsiS0_MBurstLength = appW3$wsiM0_MBurstLength ;
assign appW4$wsiS0_MByteEn = appW3$wsiM0_MByteEn ;
assign appW4$wsiS0_MCmd = appW3$wsiM0_MCmd ;
assign appW4$wsiS0_MData = appW3$wsiM0_MData ;
assign appW4$wsiS0_MReqInfo = appW3$wsiM0_MReqInfo ;
assign appW4$wmiM0_SThreadBusy = wmiM1_SThreadBusy ;
assign appW4$wmiM0_SDataThreadBusy = wmiM1_SDataThreadBusy ;
assign appW4$wmiM0_SRespLast = wmiM1_SRespLast ;
assign appW4$wmiM0_SReset_n = wmiM1_SReset_n ;
assign appW4$wsiM0_SThreadBusy = wsi_m_dac_SThreadBusy ;
assign appW4$wsiM0_SReset_n = wsi_m_dac_SReset_n ;
assign appW4$wsiS0_MReqLast = appW3$wsiM0_MReqLast ;
assign appW4$wsiS0_MBurstPrecise = appW3$wsiM0_MBurstPrecise ;
assign appW4$wsiS0_MReset_n = appW3$wsiM0_MReset_n ;
endmodule // mkOCApp4B
|
//////////////////////////////////////////////////////////////////////////////////
// Company: RMIT University
// Engineer: Matthew Myungha Kim
// [email protected], [email protected]
//
// Create Date: 16:54:00 06/03/2014
// Design Name: tb_signal_gen
// Module Name: tb_signal_gen
// Project Name: Streaming Media on Null Convention Logic
// Description: Testbenc for "Testbench signal generation" for gates test
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module tb_signal_gen;
// Praramers
parameter INPUT_PORTS = 3;
// Inputs
reg clk;
reg rst;
reg req;
// Outputs
wire [INPUT_PORTS-1:0] stm_value;
wire gnt;
// Instantiate the Unit Under Test (UUT)
signal_gen
#(.INPUT_PORTS(INPUT_PORTS))
uut (
.clk(clk),
.rst(rst),
.req(req),
.stm_value(stm_value),
.gnt(gnt)
);
parameter PERIOD = 10;
always begin
clk = 1'b0;
#(PERIOD/2)
clk = 1'b1;
#(PERIOD/2);
end
initial begin
// Initialize Inputs
rst = 1;
req = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
req = 0;
// Add stimulus here
#100;
req = 1;
$display($time, " << Starting the Simulation >>");
#100;
req = 0;
$monitor(" %0d %b", $time, gnt);
wait(gnt)
begin
$display($time, " << Finishing the Simulation >>");
$stop;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFBBP_TB_V
`define SKY130_FD_SC_HD__SDFBBP_TB_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfbbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 SET_B = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 D = 1'b1;
#220 RESET_B = 1'b1;
#240 SCD = 1'b1;
#260 SCE = 1'b1;
#280 SET_B = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 D = 1'b0;
#400 RESET_B = 1'b0;
#420 SCD = 1'b0;
#440 SCE = 1'b0;
#460 SET_B = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 SET_B = 1'b1;
#660 SCE = 1'b1;
#680 SCD = 1'b1;
#700 RESET_B = 1'b1;
#720 D = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 SET_B = 1'bx;
#840 SCE = 1'bx;
#860 SCD = 1'bx;
#880 RESET_B = 1'bx;
#900 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__sdfbbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFBBP_TB_V
|
(** * Hoare: Lógica de Hoare, Parte I *)
Require Export Imp.
(** nos dois ultimos capítulos, nós começamos a aplicar as ferramentas
matemáticas desenvolvidas na primeira parte do curso para estudar
a teoria de uma pequena linguagem de programação, Imp.
- Nós definimos um tipo de _árvores de sintaxe abstrata_ para o Imp,
juntamente com uma _relação de avaliação_ (uma função parcial sobre os
estados) que especifica a _semântica operacional_ de programas.
A linguagem que definimos, embora pequena, capitura algumas das
características chaves desenvolvidas em linguagens como C, C++ e Java, incluindo
a noção fundamental de estado mutável e alguns controles de estruturas comuns.
- Nós provamos uma série de _propriedades metateóricas_ -- "meta"
no sentido de que eles são propriedades da linguagem como um todo,
ao invés de propriedades de programas específicos da linguagem.
Isso incluiu:
- determinismo da avaliação
- equivalência de algumas maneiras diferentes de escrever as definições (por
exemplo, definições funcionais e relacionais da avaliação de expressão aritmética)
- terminação garantida de certas classes de programas
- correção (no sentido de preservação) de uma série de transformações úteis de
programas
- equivalência de comportamento de programas (no capítulo [Equiv]).
Se nós parássemos aqui, nós já poderiamos ter algo útil: um conjunto
de ferramentas para definir e discutir linguagens de programação e
funcionalidades de linguagem que são matematicamente precisas,
fexíveis e fáceis de se trabalhar, aplicadas a um conjunto de
propriedades chave. Todas essas propriedades são coisas que designers
de liguagem, escritores de compiladores e usuários podem querer
conhecer. De fato, muitas delas são tão fundamentais para o nosso
entendimento das linguagens de programação que lidamos que nós
podemos não reconhecê-las conscientemente como "teoremas". Mas
propriedades que parecem intuitivamente óbvias podem às vezes ser
bastante sutis (em alguns casos, até sutilmente erradas!).
Nós vamos retornar para o tema de propriedades metateóricas de linguagens
inteiras mais tarde no curso, quando discutimos _tipos_ e _solidez
de escrita_. Nesse capítulo, entretanto, nós vamos tornar para um
diferente conjunto de problemas.
Nosso objetivo é para ver como executar alguns exemplos simples de
_verificação de programa_ -- ex., usando a definição precisa de Imp para provar
formalmente que programas particulares satisfazem especificações particulares do
comportamento deles. Nós iremos desenvolver um sistema de raciocínio chamado
_Lógica Floyd-Hoare_ -- frequentemente encurtado para apenas _Lógica de Hoare_
-- em que cada construção sintática de Imp é equipado com um único, "regra de prova"
genérica que pode ser usado para razão composicionalmente sobre a corretude de programas
envolvendo esta construção.
A Lógica de Hoare se origina na década de 1960, e continua a ser
objeto de intensa pesquisa até os dias atuais. Situa-se no centro
de uma infinidade de ferramentas que estão sendo usadas no meio
acadêmico e na indústria para especificar e verificar sistemas
de software reais. *)
(* ####################################################### *)
(** * Lógica de Hoare *)
(** A Lógica de Hoare combina duas belas ideias: uma forma natural de escrever
_especificações_ de programas e uma _técnica de prova composicional_ para provar que os
programas são corretos com relação a tais especificações -- no qual queremos dizer como
"composicional" que a estrutura das provas refletem diretamente a estrutura dos programas
sobre os quais são gerados. *)
(* ####################################################### *)
(** ** Asserções *)
(** Para falar a respeito de especificações de programas, a primeira
coisa que nós precisamos é de uma maneira de fazer _asserções_ a
respeito de propriedades que mantém um ponto particular durante a
execução do programa -- isto é, afirmações a respeito do estado
atual da memória quando a execução do programa alcança determinado
ponto. Formalmente, uma asserção é somente uma família de
proposições idexadas por um [state] (estado). *)
Definition Assertion := state -> Prop.
(** **** Exercício: nível 1, opcional (assertions) *)
Module ExAssertions.
(** Paraphrase the following assertions in English. *)
Definition as1 : Assertion := fun st => st X = 3.
Definition as2 : Assertion := fun st => st X <= st Y.
Definition as3 : Assertion :=
fun st => st X = 3 \/ st X <= st Y.
Definition as4 : Assertion :=
fun st => st Z * st Z <= st X /\
~ (((S (st Z)) * (S (st Z))) <= st X).
Definition as5 : Assertion := fun st => True.
Definition as6 : Assertion := fun st => False.
(* PREENCHER *)
End ExAssertions.
(** [] *)
(* ####################################################### *)
(** ** Notação para Asserções *)
(** Esse meio de escrever asserções pode ser um pouco pesado,
por duas razões: (1) cada asserção que nós alguma vez escrevermos vai
ser com [fun st => ]; e (2) o estado [st] é o único que nunca usamos para
procurar variáveis (nunca precisaremos falar sobre dois estados de memória
diferentes ao mesmo tempo). Para discurssão informal de exemplos, vamos
adotar algumas convenções simplificadoras: deixaremos de lado o [fun st =>]
inicial, e iremos escrever somente [X] para significar [st X]. Então, ao
em vez de escrever *)
(**
fun st => (st Z) * (st Z) <= m /\
~ ((S (st Z)) * (S (st Z)) <= m)
we'll write just
Z * Z <= m /\ ~((S Z) * (S Z) <= m).
*)
(** Dado duas asserções [P] e [Q], nós dizemos que [P] _implica_ [Q],
escrito [P ->> Q] (em ASCII, [P -][>][> Q]), se, sempre que [P] satisfaz algum
estado [st], [Q] também satisfaz. *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
Notation "P ->> Q" :=
(assert_implies P Q) (at level 80) : hoare_spec_scope.
Open Scope hoare_spec_scope.
(** Também teremos a oportunidade de usar a variante de implicação "sse"
entre as afirmações: *)
Notation "P <<->> Q" :=
(P ->> Q /\ Q ->> P) (at level 80) : hoare_spec_scope.
(* ####################################################### *)
(** ** Triplas de Hoare *)
(** Em seguida, precisamos de uma maneira de fazer declarações formais a respeito do
comportamento dos comandos. *)
(** Devido ao fato de que o comportamento de um comando é transformar
um estado em outro, é natural expressar afirmações a respeito de
comandos em termos de asserções que são verdade antes e depois do
comando executar:
- "Se o comando [c] é iniciado em um estado satisfazendo a asserção
[P], e se [c] eventualmente termina em algum estado final,
então esse estado final satisfará a asserção [Q]."
Tal afirmação é chamado um _Tripla de Hoare_. A propriedade [P] é
chamado de _pré-condição_ de [c], enquanto [Q] é _pós-condição_. Formalmente: *)
Definition hoare_triple
(P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
(** Já que estaremos trabalhando muito com triplas de Hoare, é útil ter
uma notação compacta:
{{P}} c {{Q}}.
*)
(** (A notação tradicional é [{P} c {Q}], mas chaves individuais já são usadas para
outras coisas no Coq.) *)
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level)
: hoare_spec_scope.
(** (A anotação [hoare_spec_scope] aqui diz ao Coq que essa notação
não é global mas tem a intenção de ser usada em contextos
particulares. A [Open Scope] diz ao Coq que esse arquivo é um
desses contextos.) *)
(** **** Exercício: nível 1, opcional (triples) *)
(** Paraphrase the following Hoare triples in English.
1) {{True}} c {{X = 5}}
2) {{X = m}} c {{X = m + 5)}}
3) {{X <= Y}} c {{Y <= X}}
4) {{True}} c {{False}}
5) {{X = m}}
c
{{Y = real_fact m}}.
6) {{True}}
c
{{(Z * Z) <= m /\ ~ (((S Z) * (S Z)) <= m)}}
*)
(** [] *)
(** **** Exercise: 1 star, optional (valid_triples) *)
(** Qual das triplas de Hoare a seguir são _válidas_ -- isto é, a
relação alegada entre [P], [c], e [Q] é verdadeira?
1) {{True}} X ::= 5 {{X = 5}}
2) {{X = 2}} X ::= X + 1 {{X = 3}}
3) {{True}} X ::= 5; Y ::= 0 {{X = 5}}
4) {{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
5) {{True}} SKIP {{False}}
6) {{False}} SKIP {{True}}
7) {{True}} WHILE True DO SKIP END {{False}}
8) {{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
9) {{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
*)
(* PREENCHER *)
(** [] *)
(** (Note que nós estamos usando notações matemáticas informal para
expressões dentro de comandos, para legibilidade, em vez de códigos formal deles
[aexp] e [bexp]. Nós iremos continuar fazendo ao longo do capítulo.) *)
(** Para nos aquecer para o que está vindo, aqui estão dois fatos
simples sobre triplas de Hoare. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ####################################################### *)
(** ** Regras de Demonstração *)
(** O objetivo da lógica de Hoare é proporcionar um método _composicional_ para provar a
validade das triplas de Hoare. Ou seja, a estrutura de uma prova para a correção de um
programa deve espelhar a estrutura do próprio programa. Para este fim, nas seções abaixo,
iremos introduzir uma regra para o raciocínio sobre cada uma das diferentes formas
sintáticas de comandos no Imp - um para atribuição, um para o sequenciamento, um para
condicionais, etc. - além de um par de regras "estruturais" para unir tudo. Nós
provaremos que os programas estão corretos usando estas regras de prova, sem nunca
desdobrar a definição de [hoare_triple]. *)
(* ####################################################### *)
(** *** Atribuição *)
(** A regra para atribuição é a mais fundamentas das regras de prova da
lógica de Hoare. Aqui está como ela funciona.
Considere essa tripla de Hoare (válida):
{{ Y = 1 }} X ::= Y {{ X = 1 }}
Em português: se nós começarmos em um estado onde o valor de [Y]
é [1] e nós assinalarmos [Y] a [X], então nós iremos terminar em um
estado onde [X] é [1]. Isso é, a propriedade de ser igual a [1] é
transferida de [Y] para [X].
Similarmente, em
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
a mesma propriedade (sendo igual a um) é transferida para
[X] a partir da expressão [Y + Z] no lado direito da
atribuição.
Mais geralmente, se [a] é _qualquer_ expressão aritmética, então
{{ a = 1 }} X ::= a {{ X = 1 }}
é uma tripla de Hoare válida.
Isso pode ser tornado ainda mais geral. Para concluir que uma
propriedade _arbitrária_ [Q] é satisfeita depois de [X :: = a],
temos que assumir que [Q] é satisfeita antes de [X :: = a], porém
_com todas as ocorrências de_ [X] substituídas por [a] em [Q].
Isso leva à regra de Hoare para atribuição
{{ Q [X |-> a] }} X ::= a {{ Q }}
onde "[Q [X |-> a]]" é pronunciado "[Q] onde [a] é substituído
por [X]".
Por exemplo, a seguir se encontram aplicações válidas para a regra de atribuição:
{{ (X <= 5) [X |-> X + 1]
i.e., X + 1 <= 5 }}
X ::= X + 1
{{ X <= 5 }}
{{ (X = 3) [X |-> 3]
i.e., 3 = 3}}
X ::= 3
{{ X = 3 }}
{{ (0 <= X /\ X <= 5) [X |-> 3]
i.e., (0 <= 3 /\ 3 <= 5)}}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
*)
(** Para formalizar a regra, nos devemos primeiramente formalizar
a ideia de "substituir uma expressão por uma variável Imp em uma
asserção." Isso é, dada uma proposição [P], uma variável [X] e uma
expressão aritmética [a], nós queremos derivar outra proposição [P']
que é o mesmo que [P] exceto que, sempre que [P] menciona [X], [P']
deve mencionar [a].
Desde que [P] é uma proposição arbitrária do Coq, nós não podemos
diretamente "editar" seu texto. Em vez disso, nós podemos alcançar o
efeito que queremos calculando [P] em um estado atualizado: *)
Definition assn_sub X a P : Assertion :=
fun (st : state) =>
P (update st X (aeval st a)).
Notation "P [ X |-> a ]" := (assn_sub X a P) (at level 10).
(** Isto é, [P [X |-> a]] é uma asserção [P'] que é apenas como [P]
exceto que, sempre que [P] procura a variável [X] no estado atual, [P']
ao invés disso usa o valor da expressão [a].
Para ver como isso funciona, vamos calcular o que acontece com um par
de exemplos. Primeiro, suponha que [P'] é [(X <= 5) [X |-> 3]] -- ou
seja, mais formalmente, [P'] é a expressão Coq
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (ANum 3))),
que é simplificada para
fun st =>
(fun st' => st' X <= 5)
(update st X 3)
e é simplificada mais ainda para
fun st =>
((update st X 3) X) <= 5)
e por uma simplificação maior para
fun st =>
(3 <= 5).
Isto é, [P'] é a asserção de que [3] é inferior ou igual a [5]
(como esperado).
Para um exemplo mais interessante, suponha que [P'] é [(X <= 5) [X |-> X+1]].
Formalmente, [P'] é a expressão Coq fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (APlus (AId X) (ANum 1)))),
sendo simplificado para
fun st =>
(((update st X (aeval st (APlus (AId X) (ANum 1))))) X) <= 5
e simplificado mais ainda para
fun st =>
(aeval st (APlus (AId X) (ANum 1))) <= 5.
Ou seja, [P'] é a afirmação de que [X+1] é, no máximo, [5]. *)
(** Agora nós podemos dar a regra de prova precisa para atribuição:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X ::= a {{Q}}
*)
(** Nós podemos provar formalmente que essa regra é de fato válida. *)
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Aqui está uma primeira prova formal usando esta regra. *)
Example assn_sub_example :
{{(fun st => st X = 3) [X |-> ANum 3]}}
(X ::= (ANum 3))
{{fun st => st X = 3}}.
Proof.
apply hoare_asgn. Qed.
(** **** Exercício: nível 2 (hoare_asgn_examples) *)
(** Translate these informal Hoare triples...
1) {{ (X <= 5) [X |-> X + 1] }}
X ::= X + 1
{{ X <= 5 }}
2) {{ (0 <= X /\ X <= 5) [X |-> 3] }}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
...into formal statements [assn_sub_ex1, assn_sub_ex2]
and use [hoare_asgn] to prove them. *)
(* PREENCHER *)
(** [] *)
(** **** Exercício: nível 2 (hoare_asgn_wrong) *)
(** A regra de atribuição parece ser de trás para frente para quase todos
que a veem pela primeira vez. Se ela ainda parece ser de trás para
frente para você, pode ser útil pensar um pouco sobre regras
alternativas "de frente para trás". Aqui está uma aparentemente
natural:
------------------------------ (hoare_asgn_wrong)
{{ True }} X ::= a {{ X = a }}
Dê um contraexemplo mostrando que esta regra é incorreta
(informalmente). Dica: a regra quantifica universalmente
sobre a expressão aritmética [a], e seu contraexemplo
precisa apresentar um [a] para o qual a regra não funciona. *)
(* PREENCHER *)
(** [] *)
(** **** Exercício: nível 3, avançado (hoare_asgn_fwd) *)
(** No entanto, usando uma variável auxiliar [m] para lembrar o valor original de [X],
podemos definir uma regra de Hoare para atribuição que faz, intuitivamente, ser de
"avançar" no lugar de ir de trás pra frente.
------------------------------------------ (hoare_asgn_fwd)
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P st' /\ st X = aeval st' a }}
(onde st' = update st X m)
Note que nós usamos o valor original de [X] para reconstruir o
estado [st'] antes da atribuição. Prove que essa regra é correta
(a primeira hipótese é o axioma extensionalmente funcional, que
você vai precisar em determinado momento). Também note que essa
regra é mais complicada que [hoare_asgn].
*)
Theorem hoare_asgn_fwd :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall m a P,
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P (update st X m) /\ st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality m a P.
(* PREENCHER *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_fwd_exists) *)
(** Outra maneira de definir uma regra avançada para atribuições é
quantificar existencialmente sobre o valor anterior da variável
atribuida.
------------------------------------------ (hoare_asgn_fwd_exists)
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (update st X m) /\
st X = aeval (update st X m) a }}
*)
(* Esta regra foi proposta por Nick Giannarakis e Zoe Paraskevopoulou. *)
Theorem hoare_asgn_fwd_exists :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall a P,
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (update st X m) /\
st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality a P.
(* PREENCHER *) Admitted.
(** [] *)
(* ####################################################### *)
(** *** Consequência *)
(** Às vezes, as pré-condições e pós-condições que recebemos das regras
de Hoare não serão exatamente aquelas que nós queremos na situação
particular que temos em mãos -- elas podem ser logicamente
equivalentes, mas ter uma forma sintática diferente que seja
incapaz de unificar com a meta que estamos tentando provar, ou
elas realmente podem ser logicamente mais fracas
(para pré-condições) ou mais fortes (para pós-condições) do que
a que nós precisamos.
Por exemplo, enquanto {{(X = 3) [X |-> 3]}} X ::= 3 {{X = 3}} decorre diretamente da
regra de atribuição, {{True}} X ::= 3 {{X = 3}} não. Esta tripla é válida, porém não
é uma instância de [hoare_asgn] pois [True] e [(X = 3) [X |-> 3]] não são afirmações
sintaticamente iguais. No entanto, eles são logicamente equivalente, por isso, se uma
tripla é válida, então o outro deve certamente ser também. Poderíamos capturar essa
observação com a seguinte regra:
{{P'}} c {{Q}}
P <<->> P'
----------------------------- (hoare_consequence_pre_equiv)
{{P}} c {{Q}}
Indo um pouco mais além nessa linha de pensamento, nós podemos
ver que fortificar uma pré-condição ou enfraquecer a pós-condição
de uma tripla válida sempre produz outra tripla válida. essa
observação é capturada por duas _Regras de Consequência_.
{{P'}} c {{Q}}
P ->> P'
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' ->> Q
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
*)
(** Seguem as versões formais: *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
(** Por exemplo, nós podemos usar a primeira regra da consequência assim:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
Ou, formalmente...
*)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => st X = 1}}.
Proof.
apply hoare_consequence_pre
with (P' := (fun st => st X = 1) [X |-> ANum 1]).
apply hoare_asgn.
intros st H. unfold assn_sub, update. simpl. reflexivity.
Qed.
(** Finalmente, por conveniente em algumas provas, nós podemos declarar uma
regra "combinada" de consequência que nos permite varias ambas as pré-condições e
as pós-condições.
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
apply hoare_consequence_pre with (P' := P').
apply hoare_consequence_post with (Q' := Q').
assumption. assumption. assumption. Qed.
(* ####################################################### *)
(** *** Digressão: a tática [eapply] *)
(** Este é um bom momento para introduzir um outro recurso conveniente
de Coq. Tivemos que escrever "[with (P' := ...)]" explicitamente
nas provas de [hoare_asgn_example1] e [hoare_consequence] acima,
para nos certificarmos de que todas as metavariáveis nas
premissas da regra [hoare_consequence_pre] receberiam valores
específicos. (Uma vez que [P'] não aparece na conclusão de
[hoare_consequence_pre], o processo de unificar a conclusão
com a meta atual não restringe [P'] a uma asserção específica.
Isto é um pouco chato pois tanto a asserção é longa demais como o próximo passo a
ser feito com [hoare_asgn_example1] -- a aplicação da regra [hoare_asgn] -- irá nos
dizer exatamente o que deveria ser! Nós podemos usar [eapply] no lugar de
[apply] para dizer ao Coq, essencialmente, "Tenha calma: a parte que está faltando
será preenchida em breve." *)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => st X = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H. reflexivity. Qed.
(** Geralmente, a tática [eapply H] funciona como [apply H] exceto que,
ao invés de falhar se unificar a meta com a conclusão de [H] não
determina como instanciar todas as variáveis que aparecem nas
premissas de [H], [eapply H] vai substituir essas variáveis com
as chamadas _variáveis existenciais_ (escritas [?nnn]) como espaços
reservados para expressões que serão determinados (por uma posterior
unificação) mais tarde na prova. *)
(** A fim de que [Qed] suceda, toda variáveis existênciais precisam
ser determinadas até o fim da prova. Caso contrário Coq
irá (com razão) recusar aceitar a prova. Se lembre que as táticas do Coq
constroem objetos de prova, e objetos de prova contendo variáveis
existênciais não são completos. *)
Lemma silly1 : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(forall x y : nat, P x y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. apply HP.
(** Coq dar um alerta depois de [apply HP]:
Sem mais submetas mas variáveis existencial não-instanciados.
Existential 1 =
?171 : [P : nat -> nat -> Prop
Q : nat -> Prop
HP : forall x y : nat, P x y
HQ : forall x y : nat, P x y -> Q x |- nat]
(dependent evars: ?171 open,)
Você pode usar Grab Existential Variables.
Tentar terminar a prova com [Qed] da um erro:
<<
Erro: Tentativa de salvar uma prova com variáveis existenciais ainda não instanciado.
>> *)
Abort.
(** Uma restrição adicional é que as variáveis existenciais não podem ser
instanciadas com termos contendo variáveis (ordinárias) que não
existiam no momento em que a variável existencial foi criada. *)
Lemma silly2 :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. destruct HP as [y HP'].
(** A execução de [apply HP'] acima falha com o seguinte erro:
Error: Impossible to unify "?175" with "y".
Existe um concerto fácil para este caso:
executar [destruct HP] _antes_ de [eapply HQ].
*)
Abort.
Lemma silly2_fixed :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP'].
eapply HQ. apply HP'.
Qed.
(** No último passo nós fizemos [apply HP'] o qual unifica a variável
existencial na meta com a variável [y]. A tática [assumption] não
funciona nesse caso, devido ao fato de ela não poder lidar com
variáveis existenciais. Contudo, Coq também fornece uma tática
[eassumption] que resolve a meta se uma das premissas corresponde
à meta até instâncias de variáveis existenciais. Nós podemos usar
isso ao invés de [apply HP']. *)
Lemma silly2_eassumption : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP']. eapply HQ. eassumption.
Qed.
(** **** Exercício: nível 2 (hoare_asgn_examples_2) *)
(** Traduzir as triplas de Hoare informais...
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
...em afirmações formais [assn_sub_ex1', assn_sub_ex2'] e
usar [hoare_asgn] e [hoare_consequence_pre] para prova-las. *)
(* PREENCHER *)
(** [] *)
(* ####################################################### *)
(** *** Skip *)
(** Uma vez que [SKIP] não muda o estado, ele preserva qualquer
propriedade P:
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ####################################################### *)
(** *** Sequenciamento *)
(** De maneira mais interessante, se o comando [c1] leva qualquer
estado onde [P] é satisfeita a um estado onde [Q] é satisfeita,
e se [c2] leva qualquer estado onde [Q] é satisfeita a um onde
[R] é satisfeita, então fazendo [c1] seguido de [c2] levará
qualquer estado onde [P] é satisfeita a um onde [R] é
satisfeita:
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); assumption. Qed.
(** Perceba que, na regra formal [hoare_seq], as premisas são dadas numa ordem contrária
([c2] before [c1]). Isto combina com o fluxo natural de informações em muitas situações
na qual usamos a regra: o caminho natural para construir uma prova na lógica de Hoare é
começar no fim do programa (com uma pós-condição final) e empurrar as pós-condições de
volta até chegar em seu início. *)
(** Informalmente, um modo legal de gravar uma prova usando a regra de
sequência é como um "programa decorado" onde a asserção intermediária
[Q] é escrita entre [c1] e [c2;]
{{ a = n }}
X ::= a;;
{{ X = n }} <---- decoração para Q
SKIP
{{ X = n }}
*)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a;; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
Case "right part of seq".
apply hoare_skip.
Case "left part of seq".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity. Qed.
(** Vamos frequentemente utilizar [hoare_seq] e
[hoare_consequence_pre] em combinação com a tática [eapply],
como feito acima. *)
(** **** Exercício: nível 2 (hoare_asgn_example4) *)
(** Traduza este "programa decorado" para uma prova formal:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1;;
{{ X = 1 }} ->>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
*)
Example hoare_asgn_example4 :
{{fun st => True}} (X ::= (ANum 1);; Y ::= (ANum 2))
{{fun st => st X = 1 /\ st Y = 2}}.
Proof.
(* PREENCHER *) Admitted.
(** [] *)
(** **** Exercício: nível 3 (swap_exercise) *)
(** Escrever um programa Imp [c] que troca os valores de [X] e [Y]
e mostrar (em Coq) que ele satisfaz a seguinte
especificação:
{{X <= Y}} c {{Y <= X}}
*)
Definition swap_program : com :=
(* PREENCHER *) admit.
Theorem swap_exercise :
{{fun st => st X <= st Y}}
swap_program
{{fun st => st Y <= st X}}.
Proof.
(* PREENCHER *) Admitted.
(** [] *)
(** **** Exercício: nível 3 (hoarestate1) *)
(** Explique por que a seguinte proposição não pode ser provada:
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}}
(X ::= (ANum 3);; Y ::= a)
{{fun st => st Y = n}}.
*)
(* PREENCHER *)
(** [] *)
(* ####################################################### *)
(** *** Condicionais *)
(** Que ordenação de regra nós queremos para raciocinar a respeito
de comandos condicionais? Certamente, se a mesma asserção [Q]
se mantém depois de executar cada branch, então ela se mantém
depois de toda a condicional. Então nós devemos ser tentados a
escrever:
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
Contudo, isso é muito fraco. Por exemplo, usando essa regra,
nós não podemos mostrar que:
{{ True }}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
uma vez que a regra não diz nada sobre o estado em que as atribuições
tomam lugar nos ramos "then" e "else". *)
(** Mas nós podemos realmente dizer algo mais preciso. No ramo
"then", nós sabemos que a expressão booleana [b] avalia para [verdadeiro],
e no ramo "else", nós sabemos que ele avalia para o [falso].
Fazendo esta informação disponívelna premissa da regra nos da mais informações
para trabalhar com ele quando racioncinamos sobre o comportamento de [c1] e [c2]
(ex., as razões do por que que eles estabelecem a pós-condição [Q]).*)
(**
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
*)
(** Para interpretar essa regra formalmente, precisamos trabalhar um
pouco. A rigor, a asserção que nós escrevemos, [P /\ b], é a
conjunção de uma asserção com uma expressão booleana -- ou seja,
ela não faz checagem de tipo. Para corrigir isso, precisamos de
uma maneira de formalmente "erguer" qualquer bexp [b] para
uma asserção. Vamos escrever [bassn b] para a asserção "a
expressão booleana [b] é avaliada para [true] (no estado dado)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(** Alguns fatos úteis acerca de [bassn] são: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(** Agora podemos formalizar a regra de prova Hoare para condicionais e prová-lo que está
correto. *)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
Case "b is true".
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
Case "b is false".
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(* ####################################################### *)
(** * Lógica de Hoare: até agora *)
(**
Ideia: crie uma _lógica de domínio específico_ para raciocinar
a respeito de propriedades de programas Imp.
- Isso esconde os detalhes de baixo nível da semântica do programa
- Leva a um processo de raciocínio composicional
A estrutura básica é dada pela _Tripla de Hoare_ na forma:
{{P}} c {{Q}}
]]
- [P] e [Q] são predicados sobre o estado do programa Imp
- "Se o comando [c] é iniciado em um estado satisfazendo a afirmação
[P], e se [c] eventualmente termina em algum estado final,
então esse estado final satisfará a afirmação [Q]."
*)
(** ** Regras da lógica de Hoare (parcial) *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
(** *** Exemplo *)
(** Aqui esta uma prova formal que o programa que nós
usamos para motivar as regras satisfaz a especificação que nós demos. *)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => st X <= st Y}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update, assert_implies.
simpl. intros st [_ H].
apply beq_nat_true in H.
rewrite H. omega.
Case "Else".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, update, assert_implies.
simpl; intros st _. omega.
Qed.
(** **** Exercício: nível 2 (if_minus_plus) *)
(** Provar a seguinte tripla de Hoare usando [hoare_if]: *)
Theorem if_minus_plus :
{{fun st => True}}
IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI
{{fun st => st Y = st X + st Z}}.
Proof.
(* PREENCHER *) Admitted.
(* ####################################################### *)
(** *** Exercício: Condicionais de ramificação única *)
(** **** Exercício: nível 4 (if1_hoare) *)
(** Neste exercício iremos estender Imp com "condicionais unilaterais" com a forma
[IF1 b THEN c FI]. Aqui, [b] é uma expressão booleana e [c] um comando. Se [b] for
avaliada como [true], então o comando [c] é avaliado. Se [b] for avaliada como [false],
então [IF1 b THEN c FI] não faz nada.
Nós recomendamos que você faça esse exercício antes dos que seguem,
pois ele deve ajudar a solidificar seu entendimento do material. *)
(** O primeiro passo é extender a sintaxe de comandos e introduzir
as notações usuais. (Já fizemos isso para você. Nós usamos um módulo
separado para previnir poluir o contexto para identificadores global.) *)
Module If1.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CIf1 : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "CIF1" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'IF1' b 'THEN' c 'FI'" :=
(CIf1 b c) (at level 80, right associativity).
(** Em seguida, precisamos estender a relação de avaliação para acomodar
os ramos de [IF1]. Isso é para você fazer... Que regra(s) precisam
ser adicionadas a [Ceval] para avaliar condicionais unilaterais? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
(* PREENCHER *)
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* PREENCHER *)
].
(** Agora iremos repetir (literalmente) a definição e notação das triplas de Hoare. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Finalmente, nós (isto é, você) precisa declarar e provar um teorema
[hoare_if1], que expressa uma regra de prova de lógica de Hoare
apropriada para condicionais unilaterais. Tente criar uma regra que
é sólida e tão precisa como for possível. *)
(* PREENCHER *)
(** Para um crédito total, provar formalmente que sua regra é
precisa o suficiente para mostra a seguinte tripla de Hoare [hoare_if1_good]:
{{ X + Y = Z }}
IF1 Y <> 0 THEN
X ::= X + Y
FI
{{ X = Z }}
*)
(** Dica: Sua prova desta tripla pode precisar usar outra
regra de prova também. Por nós estarmos trabalhando em um módulo separado,
você irá precisar compiar aqui as regras que você achar necessário. *)
Lemma hoare_if1_good :
{{ fun st => st X + st Y = st Z }}
IF1 BNot (BEq (AId Y) (ANum 0)) THEN
X ::= APlus (AId X) (AId Y)
FI
{{ fun st => st X = st Z }}.
Proof. (* PREENCHER *) Admitted.
End If1.
(** [] *)
(* ####################################################### *)
(** *** Laços *)
(** Finalmente, precisamos de uma regra para o raciocínio sobre laços while. *)
(** Suponha que nós temos um laço
WHILE b DO c END
e nós queremos encontrar uma pré-condição [P] e uma pós-condição
[Q] tal que
{{P}} WHILE b DO c END {{Q}}
é uma tripla válida. *)
(** *** *)
(** Primeiro de tudo, vamos pensar a respeito do caso onde [b] é falso no
começo -- isto é, vamos assumir que o corpo do loop nunca executa
ompletamente. Nesse caso, o loop se comporta como [SKIP], então nós
devemos ser tentados a escrever: *)
(**
{{P}} WHILE b DO c END {{P}}.
*)
(**
Mas, como observamos acima para a condicional, sabemos um
pouco mais ao final -- não somente [P], mas também o fato que
[b] é falso em um estado atual. Então podemos enriquecer um
pouco a pós-condição:
*)
(**
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(**
E sobre o caso onde o corpo do laço _does_ é executado?
Para garantir que [P] satisfaz quando o laço finalmente sai, nós certamente
precisamos ter certeza que o comando [c] garante que [P] satisfaz a qualquer
momento que [c] termina.
Além disse, desde que [P] satisfaça no começo da primeira execução de [c],
e uma vez que cada execução de [c] reestabelece [P] quando ele termina, nós
sempre assumimos que [P] satisfaz o inicio de [c]. Isso nos leva para a seguinte
regra:
*)
(**
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(**
Isso é quase a regra que queremos, mas novamente ela pode ser
melhorada um pouco: no começo do corpo do laço, sabemos não
apenas que [P] é satisfeita, mas também que a guarda [b] é
verdadeira no estado atual. Isso nos dá um pouco mais de
informações para usar no raciocínio sobre [c] (mostrando
que estabelece o invariante no momento em que termina).
Isso nos dá a versão final da regra:
*)
(**
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
A proposição [P] é chamada o _invariante_ do laço.
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Como nós vimos anteriormente, nós precisamos raciocinar por
indução com [He] pois, no caso de repetir o laço, as hipóteses
associadas tratam do laço completo ao invés de somente [c]. *)
remember (WHILE b DO c END) as wcom eqn:Heqwcom.
ceval_cases (induction He) Case;
try (inversion Heqwcom); subst; clear Heqwcom.
Case "E_WhileEnd".
split. assumption. apply bexp_eval_false. assumption.
Case "E_WhileLoop".
apply IHHe2. reflexivity.
apply (Hhoare st st'). assumption.
split. assumption. apply bexp_eval_true. assumption.
Qed.
(**
Uma sutileza na terminologia é que chamar uma asserção [P] de "invariante de laço"
(loop invariant) não significa apenas que ele é preservado pelo corpo do laço em
questão (ou seja, [{{P}} c {{P}}], no qual [c] é o corpo do laço), mas sim que [P]
_junto com o fato de que a guarda do laço é verdadeira_ é uma pré-condição suficiente
de [c] para assegurar [P] como uma pós-condição.
Isso é uma exigência levemente (mas significantemente) mais fraca.
Por exemplo, se [P] é a asserção [X = 0], então [P] _é_ uma invariante
do loop
WHILE X = 2 DO X := 1 END
embora isso seja claramente _não_ preservado pelo corpo do loop.
*)
Example while_example :
{{fun st => st X <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => st X = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, assert_implies, update. simpl.
intros st [H1 H2]. apply ble_nat_true in H2. omega.
unfold bassn, assert_implies. intros st [Hle Hb].
simpl in Hb. destruct (ble_nat (st X) 2) eqn : Heqle.
apply ex_falso_quodlibet. apply Hb; reflexivity.
apply ble_nat_false in Heqle. omega.
Qed.
(** *** *)
(** Nós podemos utilizar a regra _while_ para provar a seguinte tripla
de Hoare, que pode ser surpreendente ao início... *)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
(* WORKED IN CLASS *)
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
apply hoare_post_true. intros st. apply I.
Case "Loop invariant and negated guard imply postcondition".
simpl. intros st [Hinv Hguard].
apply ex_falso_quodlibet. apply Hguard. reflexivity.
Case "Precondition implies invariant".
intros st H. constructor. Qed.
(** Claro, esse resultado não é surpresa se nós lembrarmos que
a definição de [hoare_triple] asserta que a pós-condição deve satisfazer
_apenas_ quando o comando terminar. Se o comando não terminar, nós podemos
provar qualquer coisa que nós quisermos sobre a pós-condição. *)
(** Regras de Hoare que só falam sobre comandos que são encerrados
são muitas vezes ditos descreverem a lógica de correção
"parcial". É possível também fornecer regras de Hoare para correção
"total", que se aproveita do fato de que os comandos terminam.
No entanto, neste curso vamos falar apenas sobre correção parcial. *)
(* ####################################################### *)
(** *** Exercício: [REPEAT] *)
Module RepeatExercise.
(** **** Exercício: nível 4, avançado (hoare_repeat) *)
(** Neste exercício iremos adicionar um novo comando para a nossa linguagem de comandos:
[REPEAT] c [UNTIL] a [END]. Você irá escrever a regra de avaliação para [repeat] e
adicionar uma nova regra de Hoare para este comando. *)
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] se comporta como [WHILE], exceto que a guarda do loop é
checada _depois_ de cada execução do corpo, com o loop repetindo
tão longo quanto a guarda permaneça _falsa_. Por causa disso, o
corpo vai sempre executar pelo menos uma vez. *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE"
| Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(** [Diego]Adicionar novas regras para [REPEAT] no [ceval] abaixo. Você pode
usar as regras para [WHILE] como guia, mas lembrar que o corpo de um
[REPEAT] sempre deve ser executado ao menos uma vez, e que o loop termina
quando a guarda se torna verdadeira. Então atualizar a tática [ceval_cases]
para lidar com os casos adicionados. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ;; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
(* PREENCHER *)
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass"
| Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* PREENCHER *)
].
(** As duas definições acima, copiadas aqui usam o novo [ceval]. *)
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st || st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level).
(** Para se certificar de que você tem as regras de avaliação corretas para
[REPEAT], provar que [ex1_repeat] avalia corretamente. *)
Definition ex1_repeat :=
REPEAT
X ::= ANum 1;;
Y ::= APlus (AId Y) (ANum 1)
UNTIL (BEq (AId X) (ANum 1)) END.
Theorem ex1_repeat_works :
ex1_repeat / empty_state ||
update (update empty_state X 1) Y 1.
Proof.
(* PREENCHER *) Admitted.
(** Agora declare e prove um teorema, [hoare_repeat], que expresse uma regra de prova
apropriada para comandos [repeat]. Use [hoare_while] como um modelo, criando sua
regra de modo mais preciso possível. *)
(* PREENCHER *)
(** Para o crédito total, tenha certeza (informalmente) que sua regra pode
ser usada para provar a seguinte tripla de Hoare válida:
{{ X > 0 }}
REPEAT
Y ::= X;;
X ::= X - 1
UNTIL X = 0 END
{{ X = 0 /\ Y > 0 }}
*)
End RepeatExercise.
(** [] *)
(* ####################################################### *)
(** ** Exercício: [HAVOC] *)
(** **** Exercício: nível 3 (himp_hoare) *)
(** Nesse exercício, vamos derivar regras de prova para o comando
[HAVOC] que foi estudado no capítulo anterior. Primeiramente, vamos
enclausurar esse trabalho em um módulo separado, e relembrar a sintaxe e
a semântica big-step dos comandos Himp. *)
Module Himp.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' X" := (CHavoc X) (at level 60).
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall (st : state) (X : id) (n : nat),
(HAVOC X) / st || update st X n
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_Havoc" ].
(** A definição da tripla de Hoare é exatamente como antes. Não como nossa
noção de programas equivalente, ao qual teve consequências sutis com os comandos
ocasionalmente não-terminados (exercício [havoc_diverge]), esta definição ainda é
completamente satisfatória. Convença de você mesmo antes de prosseguir.*)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st', c / st || st' -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Complete the Hoare rule for [HAVOC] commands below by defining
[havoc_pre] and prove that the resulting rule is correct. *)
Definition havoc_pre (X : id) (Q : Assertion) : Assertion :=
(* PREENCHER *) admit.
Theorem hoare_havoc : forall (Q : Assertion) (X : id),
{{ havoc_pre X Q }} HAVOC X {{ Q }}.
Proof.
(* PREENCHER *) Admitted.
End Himp.
(** [] *)
(* ####################################################### *)
(** ** Lista completa de regras para a lógica de Hoare *)
(** Acima, nós introduzimos a Lógica de Hoare como uma ferramenta
para o raciocínio sobre programas Imp. No restante deste
capítulo, vamos explorar uma forma sistemática de usar
a Lógica de Hoare para provar propriedades sobre programas.
As regras da Lógica de Hoare são as seguintes: *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
No próximo capítulo, iremos ver como essas regras são usadas para provar que os
programas satisfazem as especificações de seus comportamentos.
*)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2_1_V
`define SKY130_FD_SC_LS__MUX2_1_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__mux2_1 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__mux2_1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2_1_V
|
module core256k(
input wire clk,
input wire reset,
input wire power,
input wire sw_single_step,
input wire sw_restart,
input wire membus_wr_rs_p0,
input wire membus_rq_cyc_p0,
input wire membus_rd_rq_p0,
input wire membus_wr_rq_p0,
input wire [21:35] membus_ma_p0,
input wire [18:21] membus_sel_p0,
input wire membus_fmc_select_p0,
input wire [0:35] membus_mb_in_p0,
output wire membus_addr_ack_p0,
output wire membus_rd_rs_p0,
output wire [0:35] membus_mb_out_p0,
input wire membus_wr_rs_p1,
input wire membus_rq_cyc_p1,
input wire membus_rd_rq_p1,
input wire membus_wr_rq_p1,
input wire [21:35] membus_ma_p1,
input wire [18:21] membus_sel_p1,
input wire membus_fmc_select_p1,
input wire [0:35] membus_mb_in_p1,
output wire membus_addr_ack_p1,
output wire membus_rd_rs_p1,
output wire [0:35] membus_mb_out_p1,
input wire membus_wr_rs_p2,
input wire membus_rq_cyc_p2,
input wire membus_rd_rq_p2,
input wire membus_wr_rq_p2,
input wire [21:35] membus_ma_p2,
input wire [18:21] membus_sel_p2,
input wire membus_fmc_select_p2,
input wire [0:35] membus_mb_in_p2,
output wire membus_addr_ack_p2,
output wire membus_rd_rs_p2,
output wire [0:35] membus_mb_out_p2,
input wire membus_wr_rs_p3,
input wire membus_rq_cyc_p3,
input wire membus_rd_rq_p3,
input wire membus_wr_rq_p3,
input wire [21:35] membus_ma_p3,
input wire [18:21] membus_sel_p3,
input wire membus_fmc_select_p3,
input wire [0:35] membus_mb_in_p3,
output wire membus_addr_ack_p3,
output wire membus_rd_rs_p3,
output wire [0:35] membus_mb_out_p3,
// 36 bit Avalon Master
output wire [17:0] m_address,
output reg m_write,
output reg m_read,
output wire [35:0] m_writedata,
input wire [35:0] m_readdata,
input wire m_waitrequest
);
// TODO: SP
wire cmc_sp = 0;
reg [18:35] cma;
reg cma_rd_rq, cma_wr_rq;
reg [0:35] cmb;
// TODO: interleave
wire cmpc_p0_rq =
~membus_fmc_select_p0 &
membus_rq_cyc_p0 &
cmc_await_rq;
wire cmpc_p1_rq =
~membus_fmc_select_p1 &
membus_rq_cyc_p1 &
cmc_await_rq;
wire cmpc_p2_rq =
~membus_fmc_select_p2 &
membus_rq_cyc_p2 &
cmc_await_rq;
wire cmpc_p3_rq =
~membus_fmc_select_p3 &
membus_rq_cyc_p3 &
cmc_await_rq;
wire [18:35] ma_p0 = { membus_sel_p0[18:21], membus_ma_p0[22:35] };
wire [18:35] ma_p1 = { membus_sel_p1[18:21], membus_ma_p1[22:35] };
wire [18:35] ma_p2 = { membus_sel_p2[18:21], membus_ma_p2[22:35] };
wire [18:35] ma_p3 = { membus_sel_p3[18:21], membus_ma_p3[22:35] };
wire [18:35] ma_in =
{18{cmc_p0_sel}}&ma_p0 |
{18{cmc_p1_sel}}&ma_p1 |
{18{cmc_p2_sel}}&ma_p2 |
{18{cmc_p3_sel}}&ma_p3;
wire rd_rq_in =
cmc_p0_sel&membus_rd_rq_p0 |
cmc_p1_sel&membus_rd_rq_p1 |
cmc_p2_sel&membus_rd_rq_p2 |
cmc_p3_sel&membus_rd_rq_p3;
wire wr_rq_in =
cmc_p0_sel&membus_wr_rq_p0 |
cmc_p1_sel&membus_wr_rq_p1 |
cmc_p2_sel&membus_wr_rq_p2 |
cmc_p3_sel&membus_wr_rq_p3;
wire [0:35] mb_in =
{36{cmc_p0_sel}}&membus_mb_in_p0 |
{36{cmc_p1_sel}}&membus_mb_in_p1 |
{36{cmc_p2_sel}}&membus_mb_in_p2 |
{36{cmc_p3_sel}}&membus_mb_in_p3;
pa cmpc_pa0(clk, reset, cmc_t1b&cmc_p0_sel, membus_addr_ack_p0);
pa cmpc_pa1(clk, reset, cmc_t1b&cmc_p1_sel, membus_addr_ack_p1);
pa cmpc_pa2(clk, reset, cmc_t1b&cmc_p2_sel, membus_addr_ack_p2);
pa cmpc_pa3(clk, reset, cmc_t1b&cmc_p3_sel, membus_addr_ack_p3);
assign membus_rd_rs_p0 = cmc_rd_rs&cmc_p0_sel;
assign membus_rd_rs_p1 = cmc_rd_rs&cmc_p1_sel;
assign membus_rd_rs_p2 = cmc_rd_rs&cmc_p2_sel;
assign membus_rd_rs_p3 = cmc_rd_rs&cmc_p3_sel;
assign membus_mb_out_p0 = sa & {36{stb_pulse & cmc_p0_sel}};
assign membus_mb_out_p1 = sa & {36{stb_pulse & cmc_p1_sel}};
assign membus_mb_out_p2 = sa & {36{stb_pulse & cmc_p2_sel}};
assign membus_mb_out_p3 = sa & {36{stb_pulse & cmc_p3_sel}};
wire cmpc_rs_set = membus_wr_rs_p0 & cmc_p0_sel |
membus_wr_rs_p1 & cmc_p1_sel |
membus_wr_rs_p2 & cmc_p2_sel |
membus_wr_rs_p3 & cmc_p3_sel;
// TODO: this is all wrong
wire pwr_t1, pwr_t2, pwr_t3;
wire cmc_await_rq_reset, cmc_pwr_clr, cmc_pwr_start;
pg pg0(clk, reset, power, pwr_t1);
// 200ms
ldly1us dly0(clk, reset, pwr_t1, pwr_t2, cmc_await_rq_reset);
// 100μs
ldly1us dly1(clk, reset, pwr_t2, pwr_t3, cmc_pwr_clr);
pa pa0(clk, reset, pwr_t3, cmc_pwr_start);
// core control, we don't really have a use for it
reg cmc_read, cmc_write, cmc_inh;
reg cmc_rq_sync, cmc_cyc_done;
reg cmc_await_rq, cmc_pse_sync, cmc_proc_rs, cmc_stop;
reg cmc_p0_act, cmc_p1_act, cmc_p2_act, cmc_p3_act;
reg cmc_last_proc;
// TODO: SP
wire cmc_p0_sel = cmc_p0_act;
wire cmc_p1_sel = cmc_p1_act;
wire cmc_p2_sel = cmc_p2_act;
wire cmc_p3_sel = cmc_p3_act;
wire cmc_t0, cmc_t1b, cmc_t1a, cmc_t2, cmc_t3;
wire cmc_t4, cmc_t5, cmc_t6, cmc_t6p;
wire cmc_t0_D, cmc_t2_D1;
wire cmc_t3_D1, cmc_t3_D2;
wire cmc_restart;
wire cmc_start;
wire cmc_state_clr;
wire cmc_pn_act = cmc_p0_act | cmc_p1_act | cmc_p2_act | cmc_p3_act;
wire cmc_aw_rq_set = cmc_t0_D & ~cmc_pn_act;
wire cmc_rq_sync_set = cmc_t0_D & ~cmc_sp & cmc_pn_act;
wire cmc_jam_cma = cmc_t1b;
wire cmc_cmb_clr;
wire cmc_read_off;
wire cmc_pse_sync_set;
wire strobe_sense;
wire cmc_rd_rs;
wire cmpc_rs_set_D;
wire cmc_proc_rs_pulse;
pa pa1(clk, reset,
(cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq),
cmc_t0);
pa pa2(clk, reset, cmc_restart | cmc_pwr_start, cmc_start);
pa pa3(clk, reset, cmc_start | cmc_t3_D1, cmc_t5);
pa pa4(clk, reset, cmc_start | cmc_t3_D2, cmc_t6p);
pa pa5(clk, reset,
cmc_start | cmc_t3 & ~cma_wr_rq | cmc_proc_rs_pulse,
cmc_state_clr);
pa pa6(clk, reset, cmc_rq_sync&cmc_cyc_done, cmc_t1b);
pa pa7(clk, reset, cmc_t1b, cmc_t1a);
pa pa9(clk, reset,
cmc_t1b | cmc_pse_sync_set&cma_rd_rq&cma_wr_rq,
cmc_cmb_clr);
pa pa11(clk, reset, cmc_t2_D1&cma_rd_rq, strobe_sense);
pa pa12(clk, reset, stb_pulse, cmc_rd_rs);
pa pa13(clk, reset, cmc_pse_sync&(cmc_proc_rs | ~cma_wr_rq), cmc_t3);
pa pa14(clk, reset, cmc_proc_rs, cmc_proc_rs_pulse);
// probably wrong
pa pa15(clk, reset, sw_restart, cmc_restart);
dly250ns dly2(clk, reset, cmc_t6p, cmc_t6);
dly100ns dly3(clk, reset, cmc_t0, cmc_t0_D);
dly250ns dly4(clk, reset, cmc_t1a, cmc_t2);
dly200ns dly5(clk, reset, cmc_t2, cmc_read_off);
dly100ns dly6(clk, reset, rd_pulse, cmc_pse_sync_set);
// Variable 35-100ns
dly70ns dly7(clk, reset, cmc_t2, cmc_t2_D1);
dly50ns dly9(clk, reset, cmc_t3, cmc_t4);
dly500ns dly10(clk, reset, cmc_t4, cmc_t3_D1);
dly200ns dly11(clk, reset, cmc_t3_D1, cmc_t3_D2);
dly50ns dly12(clk, reset, cmpc_rs_set, cmpc_rs_set_D);
reg [0:35] sa; // "sense amplifiers"
wire [17:0] core_addr = cma[18:35];
assign m_address = core_addr;
assign m_writedata = cmb;
reg stb_sync, stb_done;
wire stb_pulse;
pa pa100(clk, reset, stb_sync&stb_done, stb_pulse);
reg rd_sync, rd_done;
wire rd_pulse;
pa pa101(clk, reset, rd_sync&rd_done, rd_pulse);
reg wr_sync, wr_done;
wire wr_pulse;
pa pa102(clk, reset, wr_sync&wr_done, wr_pulse);
always @(posedge clk or posedge reset) begin
if(reset) begin
m_read <= 0;
m_write <= 0;
sa <= 0;
stb_sync <= 0;
stb_done <= 0;
rd_sync <= 0;
rd_done <= 0;
wr_sync <= 0;
wr_done <= 0;
// value doesn't matter
cmc_last_proc <= 0;
// these should probably be reset but aren't
cmc_proc_rs <= 0;
cmc_pse_sync <= 0;
end else begin
if(m_write & ~m_waitrequest) begin
m_write <= 0;
wr_done <= 1;
end
if(m_read & ~m_waitrequest) begin
m_read <= 0;
sa <= m_readdata;
stb_done <= 1;
end
if(cmc_start)
wr_done <= 1;
if(cmc_state_clr) begin
cmc_p0_act <= 0;
cmc_p1_act <= 0;
cmc_p2_act <= 0;
cmc_p3_act <= 0;
end
if(cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq) begin
if(cmpc_p0_rq) begin
cmc_p0_act <= 1;
cmc_p1_act <= 0;
cmc_p2_act <= 0;
cmc_p3_act <= 0;
end else if(cmpc_p1_rq) begin
cmc_p0_act <= 0;
cmc_p1_act <= 1;
cmc_p2_act <= 0;
cmc_p3_act <= 0;
end else if(cmpc_p2_rq & cmpc_p3_rq) begin
cmc_p0_act <= 0;
cmc_p1_act <= 0;
cmc_p2_act <= cmc_last_proc;
cmc_p3_act <= ~cmc_last_proc;
cmc_last_proc <= ~cmc_last_proc;
end else if(cmpc_p2_rq) begin
cmc_p0_act <= 0;
cmc_p1_act <= 0;
cmc_p2_act <= 1;
cmc_p3_act <= 0;
end else if(cmpc_p3_rq) begin
cmc_p0_act <= 0;
cmc_p1_act <= 0;
cmc_p2_act <= 0;
cmc_p3_act <= 1;
end
end
if(cmc_t2) begin
if(cmc_p2_act)
cmc_last_proc <= 0;
if(cmc_p3_act)
cmc_last_proc <= 1;
end
if(cmc_t0 | cmc_await_rq_reset)
cmc_await_rq <= 0;
if(cmc_t5 | cmc_aw_rq_set)
cmc_await_rq <= 1;
if(cmc_start | cmc_pwr_clr)
cmc_rq_sync <= 0;
if(cmc_rq_sync_set | cmc_t0 & cmc_sp)
cmc_rq_sync <= 1;
if(cmc_pwr_clr)
cmc_cyc_done <= 0;
if(wr_pulse & ~cmc_stop)
cmc_cyc_done <= 1;
if(cmc_t6)
wr_sync <= 1;
if(cmc_t1b) begin
cmc_pse_sync <= 0;
cmc_proc_rs <= 0;
cmc_stop <= 0;
end
// actually through another PA
if(cmc_pse_sync_set)
cmc_pse_sync <= 1;
if(cmpc_rs_set_D)
cmc_proc_rs <= 1;
if(cmc_start)
cmc_stop <= 0;
if(cmc_t2 & sw_single_step)
cmc_stop <= 1;
if(cmc_t2) begin
cmc_rq_sync <= 0;
cmc_cyc_done <= 0;
end
if(cmc_jam_cma) begin
cma <= ma_in;
cma_rd_rq <= rd_rq_in;
cma_wr_rq <= wr_rq_in;
end
cmb <= cmb | mb_in;
if(cmc_cmb_clr)
cmb <= 0;
if(strobe_sense)
stb_sync <= 1;
if(stb_pulse) begin
stb_sync <= 0;
stb_done <= 0;
rd_done <= 1;
cmb <= cmb | sa;
end
/* Core */
if(cmc_pwr_clr | cmc_t5) begin
cmc_read <= 0;
cmc_write <= 0;
cmc_inh <= 0;
end
if(cmc_t1a) begin
cmc_read <= 1;
m_read <= cma_rd_rq;
stb_done <= 0;
rd_done <= ~cma_rd_rq;
cmc_write <= 0;
end
if(cmc_read_off) begin
cmc_read <= 0;
rd_sync <= 1;
end
if(rd_pulse) begin
rd_sync <= 0;
rd_done <= 0;
end
if(cmc_t3) begin
cmc_inh <= 1;
m_write <= cma_wr_rq;
wr_done <= ~cma_wr_rq;
end
if(cmc_t4) begin
cmc_write <= 1;
cmc_read <= 0;
end
if(wr_pulse) begin
wr_sync <= 0;
wr_done <= 0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2OI_TB_V
`define SKY130_FD_SC_HD__A2BB2OI_TB_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a2bb2oi.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_hd__a2bb2oi dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2OI_TB_V
|
// Automatically generated: write_netlist -wrapapp -verilog -module reconflogic-wrapadt7310.v
module MyReconfigLogic (
input Reset_n_i,
input Clk_i,
input AdcConvComplete_i,
output AdcDoConvert_o,
input[9:0] AdcValue_i,
input I2C_Busy_i,
output[7:0] I2C_DataIn_o,
input[7:0] I2C_DataOut_i,
output[15:0] I2C_Divider800_o,
output I2C_ErrAckParam_o,
input I2C_Error_i,
output I2C_F100_400_n_o,
input I2C_FIFOEmpty_i,
input I2C_FIFOFull_i,
output I2C_FIFOReadNext_o,
output I2C_FIFOWrite_o,
output[3:0] I2C_ReadCount_o,
output I2C_ReceiveSend_n_o,
output I2C_StartProcess_o,
input[7:0] Inputs_i,
output[7:0] Outputs_o,
output[4:0] ReconfModuleIRQs_o,
output SPI_CPHA_o,
output SPI_CPOL_o,
output[7:0] SPI_DataIn_o,
input[7:0] SPI_DataOut_i,
input SPI_FIFOEmpty_i,
input SPI_FIFOFull_i,
output SPI_LSBFE_o,
output SPI_ReadNext_o,
output[7:0] SPI_SPPR_SPR_o,
input SPI_Transmission_i,
output SPI_Write_o,
input[7:0] ReconfModuleIn_i,
output[7:0] ReconfModuleOut_o,
input[7:0] I2C_Errors_i,
input[13:0] PerAddr_i,
input[15:0] PerDIn_i,
input[1:0] PerWr_i,
input PerEn_i,
output[15:0] CfgIntfDOut_o,
output[15:0] ParamIntfDOut_o
);
wire [15:0] PeriodCounterPreset_s;
wire [15:0] SPICounterPresetH_s;
wire [15:0] SPICounterPresetL_s;
wire [15:0] SensorValue_s;
wire [15:0] Threshold_s;
wire [0:0] CfgClk_s;
wire CfgMode_s;
wire [0:0] CfgShift_s;
wire CfgDataOut_s;
wire [0:0] CfgDataIn_s;
wire [2:0] ParamWrAddr_s;
wire [15:0] ParamWrData_s;
wire ParamWr_s;
wire [0:0] ParamRdAddr_s;
wire [15:0] ParamRdData_s;
TODO: implement
wire Params_s;
wire [0:0] I2C_ErrAckParam_s;
wire ParamI2C_Divider800Enable_s;
wire ParamI2C_ErrAckParamEnable_s;
wire ParamPeriodCounterPresetEnable_s;
wire ParamSPICounterPresetHEnable_s;
wire ParamSPICounterPresetLEnable_s;
wire ParamThresholdEnable_s;
// Configuration Interface
CfgIntf #(
.BaseAddr('h0180),
.NumCfgs(1)
) CfgIntf_0 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.PerAddr_i(PerAddr_i),
.PerDIn_i(PerDIn_i),
.PerDOut_o(CfgIntfDOut_o),
.PerWr_i(PerWr_i),
.PerEn_i(PerEn_i),
.CfgClk_o(CfgClk_s),
.CfgMode_o(CfgMode_s),
.CfgShift_o(CfgShift_s),
.CfgDataOut_o(CfgDataOut_s),
.CfgDataIn_i(CfgDataIn_s)
);
// Parameterization Interface: 6 write addresses, 2 read addresses
ParamIntf #(
.BaseAddr('h0188),
.WrAddrWidth(3),
.RdAddrWidth(1)
) ParamIntf_0 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.PerAddr_i(PerAddr_i),
.PerDIn_i(PerDIn_i),
.PerDOut_o(ParamIntfDOut_o),
.PerWr_i(PerWr_i),
.PerEn_i(PerEn_i),
.ParamWrAddr_o(ParamWrAddr_s),
.ParamWrData_o(ParamWrData_s),
.ParamWr_o(ParamWr_s),
.ParamRdAddr_o(ParamRdAddr_s),
.ParamRdData_i(ParamRdData_s)
);
ADT7310 ADT7310_0 (
.ADT7310CS_n_o(Outputs_o[0]),
.CpuIntr_o(ReconfModuleIRQs_o[0]),
.SPI_Data_o(SPI_DataIn_o),
.SPI_Data_i(SPI_DataOut_i),
.SPI_FIFOEmpty_i(SPI_FIFOEmpty_i),
.SPI_FIFOFull_i(SPI_FIFOFull_i),
.SPI_ReadNext_o(SPI_ReadNext_o),
.SPI_Transmission_i(SPI_Transmission_i),
.SPI_Write_o(SPI_Write_o),
.Enable_i(ReconfModuleIn_i[0]),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i),
.PeriodCounterPreset_i(PeriodCounterPreset_s),
.SPICounterPresetH_i(SPICounterPresetH_s),
.SPICounterPresetL_i(SPICounterPresetL_s),
.SensorValue_o(SensorValue_s),
.Threshold_i(Threshold_s)
);
assign AdcDoConvert_o = 1'b0;
assign I2C_DataIn_o = 8'b00000000;
assign I2C_F100_400_n_o = 1'b0;
assign I2C_FIFOReadNext_o = 1'b0;
assign I2C_FIFOWrite_o = 1'b0;
assign I2C_ReadCount_o = 4'b0000;
assign I2C_ReceiveSend_n_o = 1'b0;
assign I2C_StartProcess_o = 1'b0;
assign Outputs_o[1] = 1'b0;
assign Outputs_o[2] = 1'b0;
assign Outputs_o[3] = 1'b0;
assign Outputs_o[4] = 1'b0;
assign Outputs_o[5] = 1'b0;
assign Outputs_o[6] = 1'b0;
assign Outputs_o[7] = 1'b0;
assign ReconfModuleIRQs_o[1] = 1'b0;
assign ReconfModuleIRQs_o[2] = 1'b0;
assign ReconfModuleIRQs_o[3] = 1'b0;
assign ReconfModuleIRQs_o[4] = 1'b0;
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_LSBFE_o = 1'b0;
assign SPI_SPPR_SPR_o = 8'b00000000;
assign ReconfModuleOut_o[0] = 1'b0;
assign ReconfModuleOut_o[1] = 1'b0;
assign ReconfModuleOut_o[2] = 1'b0;
assign ReconfModuleOut_o[3] = 1'b0;
assign ReconfModuleOut_o[4] = 1'b0;
assign ReconfModuleOut_o[5] = 1'b0;
assign ReconfModuleOut_o[6] = 1'b0;
assign ReconfModuleOut_o[7] = 1'b0;
/* just a fixed value for the config interface */
assign CfgDataIn_s = 1'b0;
/* Param read address decoder
Synthesis: Accept undefined behavior if ParamRdAddr_s >= NumParams and
hope that the synthesis optimizes the MUX
Simulation: ModelSim complains "Fatal: (vsim-3421) Value x is out of range
0 to n.", even during param write cycles, because ParamRdAddr has the
source as ParamWrAddr. Use the parameter "-noindexcheck" during
compilation ("vcom"). Simulation works fine then, but ModelSim generates
numerous "INTERNAL ERROR"s to stdout, which seem harmless. */
assign ParamRdData_s = Params_s[to_integer(unsigned(ParamRdAddr_s))];
ParamOutReg #(
.Width(16)
) ParamOutReg_I2C_Divider800 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(I2C_Divider800_o),
.Enable_i(ParamI2C_Divider800Enable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(1)
) ParamOutReg_I2C_ErrAckParam (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(I2C_ErrAckParam_s),
.Enable_i(ParamI2C_ErrAckParamEnable_s),
.ParamWrData_i(ParamWrData_s[0:0])
);
ParamOutReg #(
.Width(16)
) ParamOutReg_PeriodCounterPreset (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(PeriodCounterPreset_s),
.Enable_i(ParamPeriodCounterPresetEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_SPICounterPresetH (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(SPICounterPresetH_s),
.Enable_i(ParamSPICounterPresetHEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_SPICounterPresetL (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(SPICounterPresetL_s),
.Enable_i(ParamSPICounterPresetLEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_Threshold (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(Threshold_s),
.Enable_i(ParamThresholdEnable_s),
.ParamWrData_i(ParamWrData_s)
);
assign I2C_ErrAckParam_o = I2C_ErrAckParam_s[0];
/* Address $00 */
assign Params_s[0] = { 8'b00000000, I2C_Errors_i };
/* Address $01 */
assign Params_s[1] = SensorValue_s;
/* Address $00 */
assign ParamI2C_Divider800Enable_s = TODO: implement;
/* Address $01 */
assign ParamI2C_ErrAckParamEnable_s = TODO: implement;
/* Address $02 */
assign ParamPeriodCounterPresetEnable_s = TODO: implement;
/* Address $03 */
assign ParamSPICounterPresetHEnable_s = TODO: implement;
/* Address $04 */
assign ParamSPICounterPresetLEnable_s = TODO: implement;
/* Address $05 */
assign ParamThresholdEnable_s = TODO: implement;
endmodule
|
// megafunction wizard: %ALTSQRT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTSQRT
// ============================================================
// File Name: sqrt_43.v
// Megafunction Name(s):
// ALTSQRT
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sqrt_43 (
clk,
ena,
radical,
q,
remainder);
input clk;
input ena;
input [42:0] radical;
output [21:0] q;
output [22:0] remainder;
wire [21:0] sub_wire0;
wire [22:0] sub_wire1;
wire [21:0] q = sub_wire0[21:0];
wire [22:0] remainder = sub_wire1[22:0];
altsqrt ALTSQRT_component (
.clk (clk),
.ena (ena),
.radical (radical),
.q (sub_wire0),
.remainder (sub_wire1)
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
defparam
ALTSQRT_component.pipeline = 5,
ALTSQRT_component.q_port_width = 22,
ALTSQRT_component.r_port_width = 23,
ALTSQRT_component.width = 43;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: PIPELINE NUMERIC "5"
// Retrieval info: CONSTANT: Q_PORT_WIDTH NUMERIC "22"
// Retrieval info: CONSTANT: R_PORT_WIDTH NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH NUMERIC "43"
// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
// Retrieval info: USED_PORT: ena 0 0 0 0 INPUT NODEFVAL "ena"
// Retrieval info: USED_PORT: q 0 0 22 0 OUTPUT NODEFVAL "q[21..0]"
// Retrieval info: USED_PORT: radical 0 0 43 0 INPUT NODEFVAL "radical[42..0]"
// Retrieval info: USED_PORT: remainder 0 0 23 0 OUTPUT NODEFVAL "remainder[22..0]"
// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
// Retrieval info: CONNECT: @ena 0 0 0 0 ena 0 0 0 0
// Retrieval info: CONNECT: @radical 0 0 43 0 radical 0 0 43 0
// Retrieval info: CONNECT: q 0 0 22 0 @q 0 0 22 0
// Retrieval info: CONNECT: remainder 0 0 23 0 @remainder 0 0 23 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_43.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_43.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_43.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_43.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_43_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_43_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR4B_PP_BLACKBOX_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4B_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32AI_2_V
`define SKY130_FD_SC_MS__O32AI_2_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o32ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o32ai_2 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32AI_2_V
|
module pipeline5(
clk_in,
RST,
ctrl_in,
data,
addr,
data_out,
addr_out,
en_out
);
// faz o include dos parameters das instrucoes
`include "params_proc.v"
// input / output
input clk_in, RST;
input [CTRL_WIDTH-1:0] ctrl_in;
input signed [DATA_WIDTH-1:0] data;
input [REG_ADDR_WIDTH-1:0] addr;
output reg signed [DATA_WIDTH-1:0] data_out;
output reg [REG_ADDR_WIDTH-1:0] addr_out;
output reg en_out;
// repasse dos enderecos data e addr
always @(posedge clk_in) begin
data_out <= data;
addr_out <= addr;
end
// execucao da gravacao nos registradores
always @(posedge clk_in) begin
if (!RST) begin
// rotina de reset
en_out <= 0;
end else begin
// Case para controle de habilitação de escrita no registrador de acordo com o opcode de entrada.
case (ctrl_in)
// ------------ Data Trasnfer -----------------
LW: en_out <= 1;
LW_IMM: en_out <= 1;
// ------------ Arithmetic -----------------
ADD: en_out <= 1;
SUB: en_out <= 1;
MUL: en_out <= 1;
DIV: en_out <= 1;
// ------------ Lógic -----------------
AND: en_out <= 1;
OR : en_out <= 1;
NOT: en_out <= 1;
// ------------ Control Transfer -----------------
// All default
default: en_out <= 0;
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBN_1_V
`define SKY130_FD_SC_LP__DLRBN_1_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbn_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbn_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBN_1_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:46:03 03/11/2015
// Design Name: Arithmetic_Logic_Unit
// Module Name: F:/ISE/work/cpu/cpu/ALU_Test.v
// Project Name: cpu
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Arithmetic_Logic_Unit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALU_Test;
// Inputs
reg [4:0] ctrl;
reg [15:0] data_in_A;
reg [15:0] data_in_B;
// Outputs
wire [15:0] data_out;
// Instantiate the Unit Under Test (UUT)
Arithmetic_Logic_Unit uut (
.data_out(data_out),
.ctrl(ctrl),
.data_in_A(data_in_A),
.data_in_B(data_in_B)
);
initial begin
// Initialize Inputs
ctrl = 0;
data_in_A = 2;
data_in_B = 8;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
ctrl = 1;
#50;
ctrl = 2;
#50;
ctrl = 3;
#50;
ctrl = 4;
#50;
ctrl = 5;
#50;
ctrl = 6;
#50;
ctrl = 7;
#50;
ctrl = 8;
#50;
ctrl = 9;
#50;
ctrl = 10;
#50;
ctrl = 11;
#50;
ctrl = 12;
#50;
ctrl = 13;
#50;
ctrl = 14;
#50;
ctrl = 15;
#50;
ctrl = 16;
#50;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRBP_SYMBOL_V
`define SKY130_FD_SC_LS__SDFRBP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRBP_SYMBOL_V
|
`timescale 1ns / 1ps
module rinse_mode
#(parameter WIDTH = 32, CLK_CH = 25, TIME_SCORE = 2)
(
input rinse_start, input start, input power, input [31:0]clk, input [2:0]weight,
output reg rinse_end_sign,
//light
output reg water_in_light, output reg rinsing_light,output reg water_out_light,
output [2:0]water_level, output reg dewatering_light, output reg [31:0]rinse_count,
output reg [2:0]state
);
reg [2:0]nextstate;
reg water_in_start, water_out_start, dewatering_start, rinsing_start; // submodules' start sign
wire [31:0]dewatering_count, rinsing_count, water_out_count, water_in_count; // count time
wire [2:0]water_level_rinse; // water level
wire water_in_end_sign, water_out_end_sign, dewatering_end_sign, rinsing_end_sign; // submodules' start sign
parameter water_out_state = 0, dewatering_state = 1, water_in_state = 2, rinsing_state = 3, rinse_end_state = 4;
initial begin
state = water_out_state;
nextstate = water_out_state;
water_out_light = 1'b0;
dewatering_light = 1'b0;
water_in_light = 1'b0;
rinsing_light = 1'b1; // light on when module start
water_in_start = 1'b0;
water_out_start = 1'b0;
dewatering_start = 1'b0;
rinsing_start = 1'b0;
end
assign water_level = (state == rinsing_state) ? weight : water_level_rinse;
// water_let mode run when start sign nd power are both true
water_let_mode #(WIDTH, CLK_CH, TIME_SCORE) WATER_IN_MODE (.water_in_end_sign(water_in_end_sign),
.water_in_start(water_in_start), // control water out
.water_out_start(water_out_start), // comtrol water in
.water_out_end_sign(water_out_end_sign),
.clk(clk),
.power(power),
.max_water_level(weight),
.start(start),
.water_level(water_level_rinse)
);
//count dewater time
timer #(WIDTH, CLK_CH, TIME_SCORE) DEWATERIGN_TIMER (.clk_src(clk),
.switch_power(power),
.switch_en(start),
.sum_count({{29{1'b0}},weight}),
.count_start_flag(dewatering_start),
.count_end_flag(dewatering_end_sign),
.count(dewatering_count)
);
//count rinse time
timer #(WIDTH, CLK_CH, TIME_SCORE) RINSING_TIMER (
.clk_src(clk),
.switch_power(power),
.switch_en(start),
.sum_count({{29{1'b0}},weight} * 2),
.count_start_flag(rinsing_start),
.count_end_flag(rinsing_end_sign),
.count(rinsing_count)
);
// change state
always @(posedge clk[0])
begin
if(rinse_start & power & start) state = nextstate;
else if(!(rinse_start & power)) state = water_out_state;
end
// control light
always @(posedge clk[CLK_CH])
if(rinse_start & power)
begin
case(state)
water_out_state: begin water_out_light = ~water_out_light; rinsing_light = 1'b1; end
dewatering_state: begin water_out_light = 1'b0; dewatering_light = ~dewatering_light; end
water_in_state: begin dewatering_light = 1'b0; water_in_light = ~water_in_light; end
rinsing_state: begin water_in_light = 1'b0; rinsing_light = ~rinsing_light; end
rinse_end_state: begin rinsing_light = 1'b0; end
endcase
end
else begin
water_out_light = 1'b0; dewatering_light = 1'b0; water_in_light = 1'b0; rinsing_light = 1'b1;
end
//control time and end sign
always @(posedge clk[0])
begin
if(rinse_start & power) begin
case(state)
water_out_state: begin rinse_count = {{29{1'b0}},weight} * 4 + {{29{1'b0}},water_level}; rinse_end_sign = 1'b0; end
dewatering_state: rinse_count = {{29{1'b0}},weight} * 3 + dewatering_count;
water_in_state: rinse_count = {{29{1'b0}},weight} * 3 - {{29{1'b0}},water_level};
rinsing_state: rinse_count = rinsing_count;
rinse_end_state: begin rinse_count = 0; rinse_end_sign = 1'b1; end
endcase
end
else begin
rinse_count = 0; rinse_end_sign = 1'b0;
end
end
// control submodules' start
always @(state or rinse_start or power or start)
if(rinse_start & power & start) begin
case(state)
water_out_state: begin water_out_start = 1'b1; water_in_start = 1'b0; dewatering_start = 1'b0; rinsing_start = 1'b0; end
dewatering_state: begin dewatering_start = 1'b1; water_out_start = 1'b0; water_in_start = 1'b0; rinsing_start = 1'b0; end
water_in_state: begin dewatering_start = 1'b0; water_in_start = 1'b1; water_out_start = 1'b0; rinsing_start = 1'b0; end
rinsing_state: begin water_in_start = 1'b0; rinsing_start = 1'b1; dewatering_start = 1'b0; water_out_start = 1'b0; end
rinse_end_state: begin water_in_start = 1'b0; rinsing_start = 1'b0; dewatering_start = 1'b0; water_out_start = 1'b0; end
endcase
end
else if(!(rinse_start & power)) begin
water_out_start = 1'b0; dewatering_start = 1'b0; water_in_start = 1'b0; rinsing_start = 1'b0;
end
// change nextstate when sign come
always @(water_in_end_sign or water_out_end_sign or dewatering_end_sign or rinsing_end_sign or rinse_start or power)
if(power & rinse_start)
begin
case(state)
water_out_state: begin
if(water_out_end_sign)
nextstate = dewatering_state;
else nextstate = water_out_state;
end
dewatering_state: begin
if(dewatering_end_sign)
nextstate = water_in_state;
else nextstate = dewatering_state;
end
water_in_state: begin
if(water_in_end_sign) nextstate = rinsing_state;
else nextstate = water_in_state;
end
rinsing_state: begin
if(rinsing_end_sign) nextstate = rinse_end_state;
else nextstate = rinsing_state;
end
rinse_end_state: begin
nextstate = rinse_end_state;
end
endcase
end else nextstate = water_out_state;
endmodule
|
//======================================================================
//
// chacha.v
// --------
// Top level wrapper for the ChaCha stream, cipher core providing
// a simple memory like interface with 32 bit data access.
//
//
// Copyright (c) 2013 Secworks Sweden AB
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module chacha(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] addr,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_KEYLEN = 8'h0a;
localparam KEYLEN_BIT = 0;
localparam ADDR_ROUNDS = 8'h0b;
localparam ROUNDS_HIGH_BIT = 4;
localparam ROUNDS_LOW_BIT = 0;
localparam ADDR_KEY0 = 8'h10;
localparam ADDR_KEY7 = 8'h17;
localparam ADDR_IV0 = 8'h20;
localparam ADDR_IV1 = 8'h21;
localparam ADDR_DATA_IN0 = 8'h40;
localparam ADDR_DATA_IN15 = 8'h4f;
localparam ADDR_DATA_OUT0 = 8'h80;
localparam ADDR_DATA_OUT15 = 8'h8f;
localparam CORE_NAME0 = 32'h63686163; // "chac"
localparam CORE_NAME1 = 32'h68612020; // "ha "
localparam CORE_VERSION = 32'h302e3830; // "0.80"
localparam DEFAULT_CTR_INIT = 64'h0;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg keylen_reg;
reg keylen_we;
reg [4 : 0] rounds_reg;
reg rounds_we;
reg [31 : 0] key_reg [0 : 7];
reg key_we;
reg [31 : 0] iv_reg[0 : 1];
reg iv_we;
reg [31 : 0] data_in_reg [0 : 15];
reg data_in_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [255 : 0] core_key;
wire [63 : 0] core_iv;
wire core_ready;
wire [511 : 0] core_data_in;
wire [511 : 0] core_data_out;
wire core_data_out_valid;
reg [31 : 0] tmp_read_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
assign core_iv = {iv_reg[0], iv_reg[1]};
assign core_data_in = {data_in_reg[00], data_in_reg[01], data_in_reg[02], data_in_reg[03],
data_in_reg[04], data_in_reg[05], data_in_reg[06], data_in_reg[07],
data_in_reg[08], data_in_reg[09], data_in_reg[10], data_in_reg[11],
data_in_reg[12], data_in_reg[13], data_in_reg[14], data_in_reg[15]};
assign read_data = tmp_read_data;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
chacha_core core (
.clk(clk),
.reset_n(reset_n),
.init(init_reg),
.next(next_reg),
.key(core_key),
.keylen(keylen_reg),
.iv(core_iv),
.ctr(DEFAULT_CTR_INIT),
.rounds(rounds_reg),
.data_in(core_data_in),
.ready(core_ready),
.data_out(core_data_out),
.data_out_valid(core_data_out_valid)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
init_reg <= 0;
next_reg <= 0;
keylen_reg <= 0;
rounds_reg <= 5'h0;
iv_reg[0] <= 32'h0;
iv_reg[1] <= 32'h0;
for (i = 0 ; i < 8 ; i = i + 1)
key_reg[i] <= 32'h0;
for (i = 0 ; i < 16 ; i = i + 1)
data_in_reg[i] <= 32'h0;
end
else
begin
init_reg <= init_new;
next_reg <= next_new;
if (keylen_we)
keylen_reg <= write_data[KEYLEN_BIT];
if (rounds_we)
rounds_reg <= write_data[ROUNDS_HIGH_BIT : ROUNDS_LOW_BIT];
if (key_we)
key_reg[addr[2 : 0]] <= write_data;
if (iv_we)
iv_reg[addr[0]] <= write_data;
if (data_in_we)
data_in_reg[addr[3 : 0]] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
// Address decoder logic.
//----------------------------------------------------------------
always @*
begin : addr_decoder
keylen_we = 1'h0;
rounds_we = 1'h0;
key_we = 1'h0;
iv_we = 1'h0;
data_in_we = 1'h0;
init_new = 1'h0;
next_new = 1'h0;
tmp_read_data = 32'h0;
if (cs)
begin
if (we)
begin
if (addr == ADDR_CTRL)
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
end
if (addr == ADDR_KEYLEN)
keylen_we = 1;
if (addr == ADDR_ROUNDS)
rounds_we = 1;
if ((addr >= ADDR_KEY0) && (addr <= ADDR_KEY7))
key_we = 1;
if ((addr >= ADDR_IV0) && (addr <= ADDR_IV1))
iv_we = 1;
if ((addr >= ADDR_DATA_IN0) && (addr <= ADDR_DATA_IN15))
data_in_we = 1;
end // if (we)
else
begin
if ((addr >= ADDR_KEY0) && (addr <= ADDR_KEY7))
tmp_read_data = key_reg[addr[2 : 0]];
if ((addr >= ADDR_DATA_OUT0) && (addr <= ADDR_DATA_OUT15))
tmp_read_data = core_data_out[(15 - (addr - ADDR_DATA_OUT0)) * 32 +: 32];
case (addr)
ADDR_NAME0: tmp_read_data = CORE_NAME0;
ADDR_NAME1: tmp_read_data = CORE_NAME1;
ADDR_VERSION: tmp_read_data = CORE_VERSION;
ADDR_CTRL: tmp_read_data = {30'h0, next_reg, init_reg};
ADDR_STATUS: tmp_read_data = {30'h0, core_data_out_valid, core_ready};
ADDR_KEYLEN: tmp_read_data = {31'h0, keylen_reg};
ADDR_ROUNDS: tmp_read_data = {27'h0, rounds_reg};
ADDR_IV0: tmp_read_data = iv_reg[0];
ADDR_IV1: tmp_read_data = iv_reg[1];
default:
begin
end
endcase // case (address)
end
end
end // addr_decoder
endmodule // chacha
//======================================================================
// EOF chacha.v
//======================================================================
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller wrapper
//
// File : alt_ddrx_controller_wrapper.v
//
// Abstract : This file is a wrapper that configures DDRx controller
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
//
module ddr3_int_alt_ddrx_controller_wrapper (
ctl_clk,
ctl_reset_n,
ctl_half_clk,
ctl_half_clk_reset_n,
local_ready,
local_read_req,
local_write_req,
local_wdata_req,
local_size,
local_burstbegin,
local_addr,
local_rdata_valid,
local_rdata_error,
local_rdata,
local_wdata,
local_be,
local_autopch_req,
local_multicast,
local_init_done,
local_refresh_req,
local_refresh_chip,
local_refresh_ack,
local_self_rfsh_req,
local_self_rfsh_chip,
local_self_rfsh_ack,
local_power_down_ack,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_req,
ctl_mem_clk_disable,
ctl_cal_byte_lane_sel_n,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_ba,
afi_addr,
afi_odt,
afi_rst_n,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_wlat,
afi_doing_read,
afi_rdata,
afi_rdata_valid,
csr_write_req,
csr_read_req,
csr_addr,
csr_be,
csr_wdata,
csr_waitrequest,
csr_rdata,
csr_rdata_valid,
ecc_interrupt,
bank_information,
bank_open
);
//Inserted Generics
localparam MEM_TYPE = "DDR3";
localparam LOCAL_SIZE_WIDTH = 7;
localparam LOCAL_ADDR_WIDTH = 25;
localparam LOCAL_DATA_WIDTH = 128;
localparam LOCAL_IF_TYPE = "AVALON";
localparam MEM_IF_CS_WIDTH = 1;
localparam MEM_IF_CHIP_BITS = 1;
localparam MEM_IF_CKE_WIDTH = 1;
localparam MEM_IF_ODT_WIDTH = 1;
localparam MEM_IF_ADDR_WIDTH = 14;
localparam MEM_IF_ROW_WIDTH = 14;
localparam MEM_IF_COL_WIDTH = 10;
localparam MEM_IF_BA_WIDTH = 3;
localparam MEM_IF_DQS_WIDTH = 4;
localparam MEM_IF_DQ_WIDTH = 32;
localparam MEM_IF_DM_WIDTH = 4;
localparam MEM_IF_CLK_PAIR_COUNT = 1;
localparam MEM_IF_CS_PER_DIMM = 1;
localparam DWIDTH_RATIO = 4;
localparam CTL_LOOK_AHEAD_DEPTH = 8;
localparam CTL_CMD_QUEUE_DEPTH = 8;
localparam CTL_HRB_ENABLED = 0;
localparam CTL_ECC_ENABLED = 0;
localparam CTL_ECC_RMW_ENABLED = 0;
localparam CTL_ECC_CSR_ENABLED = 0;
localparam CTL_CSR_ENABLED = 0;
localparam CTL_ODT_ENABLED = 0;
localparam CSR_ADDR_WIDTH = 16;
localparam CSR_DATA_WIDTH = 32;
localparam CTL_OUTPUT_REGD = 0;
localparam MEM_CAS_WR_LAT = 5;
localparam MEM_ADD_LAT = 0;
localparam MEM_TCL = 6;
localparam MEM_TRRD = 4;
localparam MEM_TFAW = 13;
localparam MEM_TRFC = 34;
localparam MEM_TREFI = 2341;
localparam MEM_TRCD = 5;
localparam MEM_TRP = 5;
localparam MEM_TWR = 5;
localparam MEM_TWTR = 4;
localparam MEM_TRTP = 4;
localparam MEM_TRAS = 12;
localparam MEM_TRC = 16;
localparam ADDR_ORDER = 0;
localparam MEM_AUTO_PD_CYCLES = 0;
localparam MEM_IF_RD_TO_WR_TURNAROUND_OCT = 2;
localparam MEM_IF_WR_TO_RD_TURNAROUND_OCT = 0;
localparam CTL_ECC_MULTIPLES_40_72 = 0;
localparam CTL_USR_REFRESH = 0;
localparam CTL_REGDIMM_ENABLED = 0;
localparam MULTICAST_WR_EN = 0;
localparam LOW_LATENCY = 0;
localparam CTL_DYNAMIC_BANK_ALLOCATION = 0;
localparam CTL_DYNAMIC_BANK_NUM = 4;
localparam ENABLE_BURST_MERGE = 0;
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output local_ready;
input local_read_req;
input local_write_req;
output local_wdata_req;
input [LOCAL_SIZE_WIDTH-1:0] local_size;
input local_burstbegin;
input [LOCAL_ADDR_WIDTH-1:0] local_addr;
output local_rdata_valid;
output local_rdata_error;
output [LOCAL_DATA_WIDTH-1:0] local_rdata;
input [LOCAL_DATA_WIDTH-1:0] local_wdata;
input [LOCAL_DATA_WIDTH/8-1:0] local_be;
input local_autopch_req;
input local_multicast;
output local_init_done;
input local_refresh_req;
input [MEM_IF_CS_WIDTH-1:0] local_refresh_chip;
output local_refresh_ack;
input local_self_rfsh_req;
input [MEM_IF_CS_WIDTH-1:0] local_self_rfsh_chip;
output local_self_rfsh_ack;
output local_power_down_ack;
input ctl_cal_success;
input ctl_cal_fail;
output ctl_cal_req;
output [MEM_IF_CLK_PAIR_COUNT - 1:0] ctl_mem_clk_disable;
output [(MEM_IF_DQS_WIDTH*MEM_IF_CS_WIDTH) - 1:0] ctl_cal_byte_lane_sel_n;
output [(MEM_IF_CKE_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cke;
output [(MEM_IF_CS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_ras_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_cas_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_we_n;
output [(MEM_IF_BA_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_ba;
output [(MEM_IF_ADDR_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_addr;
output [(MEM_IF_ODT_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_odt;
output [(DWIDTH_RATIO/2) - 1:0] afi_rst_n;
output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_dqs_burst;
output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_wdata_valid;
output [(MEM_IF_DQ_WIDTH*DWIDTH_RATIO) - 1:0] afi_wdata;
output [(MEM_IF_DM_WIDTH*DWIDTH_RATIO) - 1:0] afi_dm;
input [4:0] afi_wlat;
output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_doing_read;
input [(MEM_IF_DQ_WIDTH * DWIDTH_RATIO) - 1:0] afi_rdata;
input [(DWIDTH_RATIO/2) - 1:0] afi_rdata_valid;
input csr_write_req;
input csr_read_req;
input [CSR_ADDR_WIDTH - 1 : 0] csr_addr;
input [(CSR_DATA_WIDTH / 8) - 1 : 0] csr_be;
input [CSR_DATA_WIDTH - 1 : 0] csr_wdata;
output csr_waitrequest;
output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
output csr_rdata_valid;
output ecc_interrupt;
output [(MEM_IF_CS_WIDTH * (2 ** MEM_IF_BA_WIDTH) * MEM_IF_ROW_WIDTH) - 1:0] bank_information;
output [(MEM_IF_CS_WIDTH * (2 ** MEM_IF_BA_WIDTH)) - 1:0] bank_open;
alt_ddrx_controller # (
.MEM_TYPE ( MEM_TYPE ),
.LOCAL_SIZE_WIDTH ( LOCAL_SIZE_WIDTH ),
.LOCAL_ADDR_WIDTH ( LOCAL_ADDR_WIDTH ),
.LOCAL_DATA_WIDTH ( LOCAL_DATA_WIDTH ),
.LOCAL_IF_TYPE ( LOCAL_IF_TYPE ),
.MEM_IF_CS_WIDTH ( MEM_IF_CS_WIDTH ),
.MEM_IF_CHIP_BITS ( MEM_IF_CHIP_BITS ),
.MEM_IF_CKE_WIDTH ( MEM_IF_CKE_WIDTH ),
.MEM_IF_ODT_WIDTH ( MEM_IF_ODT_WIDTH ),
.MEM_IF_ADDR_WIDTH ( MEM_IF_ADDR_WIDTH ),
.MEM_IF_ROW_WIDTH ( MEM_IF_ROW_WIDTH ),
.MEM_IF_COL_WIDTH ( MEM_IF_COL_WIDTH ),
.MEM_IF_BA_WIDTH ( MEM_IF_BA_WIDTH ),
.MEM_IF_DQS_WIDTH ( MEM_IF_DQS_WIDTH ),
.MEM_IF_DQ_WIDTH ( MEM_IF_DQ_WIDTH ),
.MEM_IF_DM_WIDTH ( MEM_IF_DM_WIDTH ),
.MEM_IF_CLK_PAIR_COUNT ( MEM_IF_CLK_PAIR_COUNT ),
.MEM_IF_CS_PER_DIMM ( MEM_IF_CS_PER_DIMM ),
.DWIDTH_RATIO ( DWIDTH_RATIO ),
.CTL_LOOK_AHEAD_DEPTH ( CTL_LOOK_AHEAD_DEPTH ),
.CTL_CMD_QUEUE_DEPTH ( CTL_CMD_QUEUE_DEPTH ),
.CTL_HRB_ENABLED ( CTL_HRB_ENABLED ),
.CTL_ECC_ENABLED ( CTL_ECC_ENABLED ),
.CTL_ECC_RMW_ENABLED ( CTL_ECC_RMW_ENABLED ),
.CTL_ECC_CSR_ENABLED ( CTL_ECC_CSR_ENABLED ),
.CTL_ECC_MULTIPLES_40_72 ( CTL_ECC_MULTIPLES_40_72 ),
.CTL_CSR_ENABLED ( CTL_CSR_ENABLED ),
.CTL_ODT_ENABLED ( CTL_ODT_ENABLED ),
.CTL_REGDIMM_ENABLED ( CTL_REGDIMM_ENABLED ),
.CSR_ADDR_WIDTH ( CSR_ADDR_WIDTH ),
.CSR_DATA_WIDTH ( CSR_DATA_WIDTH ),
.CTL_OUTPUT_REGD ( CTL_OUTPUT_REGD ),
.CTL_USR_REFRESH ( CTL_USR_REFRESH ),
.MEM_CAS_WR_LAT ( MEM_CAS_WR_LAT ),
.MEM_ADD_LAT ( MEM_ADD_LAT ),
.MEM_TCL ( MEM_TCL ),
.MEM_TRRD ( MEM_TRRD ),
.MEM_TFAW ( MEM_TFAW ),
.MEM_TRFC ( MEM_TRFC ),
.MEM_TREFI ( MEM_TREFI ),
.MEM_TRCD ( MEM_TRCD ),
.MEM_TRP ( MEM_TRP ),
.MEM_TWR ( MEM_TWR ),
.MEM_TWTR ( MEM_TWTR ),
.MEM_TRTP ( MEM_TRTP ),
.MEM_TRAS ( MEM_TRAS ),
.MEM_TRC ( MEM_TRC ),
.MEM_AUTO_PD_CYCLES ( MEM_AUTO_PD_CYCLES ),
.MEM_IF_RD_TO_WR_TURNAROUND_OCT ( MEM_IF_RD_TO_WR_TURNAROUND_OCT ),
.MEM_IF_WR_TO_RD_TURNAROUND_OCT ( MEM_IF_WR_TO_RD_TURNAROUND_OCT ),
.ADDR_ORDER ( ADDR_ORDER ),
.MULTICAST_WR_EN ( MULTICAST_WR_EN ),
.LOW_LATENCY ( LOW_LATENCY ),
.CTL_DYNAMIC_BANK_ALLOCATION ( CTL_DYNAMIC_BANK_ALLOCATION ),
.CTL_DYNAMIC_BANK_NUM ( CTL_DYNAMIC_BANK_NUM ),
.ENABLE_BURST_MERGE ( ENABLE_BURST_MERGE )
) alt_ddrx_controller_inst (
.ctl_clk ( ctl_clk ),
.ctl_reset_n ( ctl_reset_n ),
.ctl_half_clk ( ctl_half_clk ),
.ctl_half_clk_reset_n ( ctl_half_clk_reset_n ),
.local_ready ( local_ready ),
.local_read_req ( local_read_req ),
.local_write_req ( local_write_req ),
.local_wdata_req ( local_wdata_req ),
.local_size ( local_size ),
.local_burstbegin ( local_burstbegin ),
.local_addr ( local_addr ),
.local_rdata_valid ( local_rdata_valid ),
.local_rdata_error ( local_rdata_error ),
.local_rdata ( local_rdata ),
.local_wdata ( local_wdata ),
.local_be ( local_be ),
.local_autopch_req ( local_autopch_req ),
.local_multicast ( local_multicast ),
.local_init_done ( local_init_done ),
.local_refresh_req ( local_refresh_req ),
.local_refresh_chip ( local_refresh_chip ),
.local_refresh_ack ( local_refresh_ack ),
.local_self_rfsh_req ( local_self_rfsh_req ),
.local_self_rfsh_chip ( local_self_rfsh_chip ),
.local_self_rfsh_ack ( local_self_rfsh_ack ),
.local_power_down_ack ( local_power_down_ack ),
.ctl_cal_success ( ctl_cal_success ),
.ctl_cal_fail ( ctl_cal_fail ),
.ctl_cal_req ( ctl_cal_req ),
.ctl_mem_clk_disable ( ctl_mem_clk_disable ),
.ctl_cal_byte_lane_sel_n ( ctl_cal_byte_lane_sel_n ),
.afi_cke ( afi_cke ),
.afi_cs_n ( afi_cs_n ),
.afi_ras_n ( afi_ras_n ),
.afi_cas_n ( afi_cas_n ),
.afi_we_n ( afi_we_n ),
.afi_ba ( afi_ba ),
.afi_addr ( afi_addr ),
.afi_odt ( afi_odt ),
.afi_rst_n ( afi_rst_n ),
.afi_dqs_burst ( afi_dqs_burst ),
.afi_wdata_valid ( afi_wdata_valid ),
.afi_wdata ( afi_wdata ),
.afi_dm ( afi_dm ),
.afi_wlat ( afi_wlat ),
.afi_doing_read ( afi_doing_read ),
.afi_doing_read_full ( ),
.afi_rdata ( afi_rdata ),
.afi_rdata_valid ( afi_rdata_valid ),
.csr_write_req ( csr_write_req ),
.csr_read_req ( csr_read_req ),
.csr_addr ( csr_addr ),
.csr_be ( csr_be ),
.csr_wdata ( csr_wdata ),
.csr_waitrequest ( csr_waitrequest ),
.csr_rdata ( csr_rdata ),
.csr_rdata_valid ( csr_rdata_valid ),
.ecc_interrupt ( ecc_interrupt ),
.bank_information ( bank_information ),
.bank_open ( bank_open )
);
endmodule
|
module command_issue(
clk,
rst,
controller_rb_l_o,
read_data_fifo_prog_full,
data_from_flash_en_o,
data_to_flash_en_o,
data_from_flash_o,
data_from_write_fifo,
data_from_gc_fifo,
command_in,
controller_command_fifo_empty_or_not,
finish_command_fifo_full,
controller_command_fifo_out_en,
read_page_en,
write_page_en,
erase_block_en,
addr,
data_to_flash,
data_to_read_fifo,
data_to_gc_fifo,
read_ready,
write_fifo_out_en,
read_fifo_in_en,
gc_fifo_out_en,
gc_fifo_in_en,
controller_command_fifo_in, //此处的controller_command_fifo实际上指的是finish_command_fifo
controller_command_fifo_in_en,
state
);
`include"ftl_define.v"
input clk;
input rst;
input controller_rb_l_o;
input read_data_fifo_prog_full;
input data_from_flash_en_o;
input data_to_flash_en_o;
input [FLASH_IO_WIDTH*4-1:0] data_from_flash_o;
input [FLASH_IO_WIDTH*4-1:0] data_from_write_fifo;
input [COMMAND_WIDTH-1:0] command_in;
input controller_command_fifo_empty_or_not;
input [FLASH_IO_WIDTH*4-1:0] data_from_gc_fifo;
input finish_command_fifo_full;
output controller_command_fifo_out_en;
output read_page_en;
output write_page_en;
output erase_block_en;
output [23:0] addr;
output [FLASH_IO_WIDTH*4-1:0] data_to_flash;
output [FLASH_IO_WIDTH*4-1:0] data_to_read_fifo;
output read_ready;
output write_fifo_out_en;
output read_fifo_in_en;
output [FLASH_IO_WIDTH*4-1:0] data_to_gc_fifo;
output gc_fifo_out_en;
output gc_fifo_in_en;
output [COMMAND_WIDTH-1:0]controller_command_fifo_in;
output controller_command_fifo_in_en;
output [4:0] state;
reg controller_command_fifo_out_en;
reg [COMMAND_WIDTH-1:0] command;
reg read_page_en;
reg write_page_en;
reg erase_block_en;
reg [23:0] addr;
wire [FLASH_IO_WIDTH*4-1:0] data_to_flash;
wire [FLASH_IO_WIDTH*4-1:0] data_to_read_fifo;
wire [FLASH_IO_WIDTH*4-1:0] data_to_gc_fifo;
reg read_ready;
wire write_fifo_out_en;
wire read_fifo_in_en;
wire gc_fifo_out_en;
wire gc_fifo_in_en;
reg [COMMAND_WIDTH-1:0]controller_command_fifo_in;
reg controller_command_fifo_in_en;
reg [4:0] state;
parameter IDLE =5'b00000;
parameter COMMAND_INTERPRET =5'b00001;
parameter ISSUE_READ =5'b00010;
parameter WAIT_A_CYCLE_FOR_READ =5'b00011;
parameter RECEIVE_READ_DATA =5'b00100;
parameter READ_END =5'b00101;
parameter ISSUE_WRITE =5'b00110;
parameter WAIT_A_CYCLE_FOR_WRITE =5'b00111;
parameter WAIT_WRITE =5'b01000;
parameter WRITE_END =5'b01001;
parameter ISSUE_MOVE =5'b01010;
parameter WAIT_A_CYCLE_FOR_MOVE_READ =5'b01011;
parameter RECEIVE_READ_DATA_FOR_MOVE =5'b01100;
parameter ISSUE_WRITE_FOR_MOVE =5'b01101;
parameter WAIT_A_CYCLE_FOR_MOVE_WRITE =5'b01110;
parameter WAIT_WRITE_FOR_MOVE =5'b01111;
parameter MOVE_END =5'b10000;
parameter ISSUE_ERASE =5'b10001;
parameter WAIT_A_CYCLE_FOR_ERASE =5'b10010;
parameter WAIT_ERASE =5'b10011;
parameter ERASE_END =5'b10100;
parameter FINISH =5'b10101;
reg io_or_gc;
reg [4:0] cycles;
assign write_fifo_out_en = (io_or_gc==1)? data_to_flash_en_o :1'b0;
assign gc_fifo_out_en = (io_or_gc==0)? data_to_flash_en_o :1'b0;
assign read_fifo_in_en = (io_or_gc==1)? data_from_flash_en_o :1'b0;
assign gc_fifo_in_en = (io_or_gc==0)? data_from_flash_en_o :1'b0;
assign data_to_flash = (io_or_gc==1)? data_from_write_fifo : data_from_gc_fifo;
// assign data_to_flash[0] = (io_or_gc==1)? data_from_write_fifo[7:0] :data_from_gc_fifo[7:0];
// assign data_to_flash[1] = (io_or_gc==1)? data_from_write_fifo[15:8] :data_from_gc_fifo[15:8];
// assign data_to_flash[2] = (io_or_gc==1)? data_from_write_fifo[23:16] :data_from_gc_fifo[23:16];
// assign data_to_flash[3] = (io_or_gc==1)? data_from_write_fifo[31:24] :data_from_gc_fifo[31:24];
assign data_to_read_fifo = (io_or_gc==1)? data_from_flash_o :32'b00000000_00000000_00000000_00000000;
assign data_to_gc_fifo = (io_or_gc==0)? data_from_flash_o :32'b00000000_00000000_00000000_00000000;
always@ (posedge clk or negedge rst)
begin
if(!rst)
begin
controller_command_fifo_out_en <= 0;
command <= 0;
read_page_en <= 0;
write_page_en <= 0;
erase_block_en <= 0;
addr <= 0;
read_ready <= 0;
state <= IDLE;
io_or_gc <= 1;
cycles <= 0;
end
else
begin
case (state)
IDLE://00
begin
if(controller_command_fifo_empty_or_not==0)
begin
command <= command_in;
controller_command_fifo_out_en<=1;
state <= COMMAND_INTERPRET;
end
else
state<=IDLE;
end
COMMAND_INTERPRET://01
begin
controller_command_fifo_out_en<=0;
case (command[127:126])
READ:
state <= ISSUE_READ;
WRITE:
state <= ISSUE_WRITE;
MOVE:
state <= ISSUE_MOVE;
ERASE:
state <= ISSUE_ERASE;
endcase
end
//////////////////////////////////////////////////////////////////////////////////////////read
ISSUE_READ://02
begin
if(controller_rb_l_o==1 && read_data_fifo_prog_full==0)
begin
io_or_gc <= 1;
read_page_en <= 1;
addr <= command[87:64];
read_ready <= 1;
cycles <= 0;
state <= WAIT_A_CYCLE_FOR_READ;
end
else
state<=ISSUE_READ;
end
WAIT_A_CYCLE_FOR_READ://03
begin
read_page_en <= 0;
if(cycles==2)
state <= RECEIVE_READ_DATA;
else
begin
cycles <= cycles+1;
state <= WAIT_A_CYCLE_FOR_READ;
end
end
RECEIVE_READ_DATA://04
begin
if(controller_rb_l_o==1 && finish_command_fifo_full==0)
begin
controller_command_fifo_in<=command;
controller_command_fifo_in_en<=1;
state <= READ_END;
end
else
state <= RECEIVE_READ_DATA;
end
READ_END://05
begin
controller_command_fifo_in_en<=0;
state <= FINISH;
end
////////////////////////////////////////////////////////////////////////////////////////////////write
ISSUE_WRITE://06
begin
if(controller_rb_l_o==1)
begin
io_or_gc <= 1;
write_page_en <= 1;
addr <= command[87:64];//物理地址
cycles <= 0;
state <= WAIT_A_CYCLE_FOR_WRITE;
end
else
state<=ISSUE_WRITE;
end
WAIT_A_CYCLE_FOR_WRITE://07
begin
write_page_en <= 0;
if(cycles==2)
state <= WAIT_WRITE;
else
begin
cycles <= cycles+1;
state <= WAIT_A_CYCLE_FOR_WRITE;
end
end
WAIT_WRITE://08
begin
if(controller_rb_l_o==1 && finish_command_fifo_full==0)
begin
if(command[125])
begin
controller_command_fifo_in<=command;
controller_command_fifo_in_en<=1;
end
else begin end
state <= WRITE_END;
end
else
state <= WAIT_WRITE;
end
WRITE_END://09
begin
controller_command_fifo_in_en<=0;
state <= FINISH;
end
////////////////////////////////////////////////////////////////////////////////////////////////move
ISSUE_MOVE://0a
begin
if(controller_rb_l_o == 1 & read_data_fifo_prog_full==0 )
begin
io_or_gc <= 0;
read_page_en <= 1;
addr <= command[24:0];
read_ready <= 1;
cycles <= 0;
state <= WAIT_A_CYCLE_FOR_MOVE_READ;
end
else
state<=ISSUE_MOVE;
end
WAIT_A_CYCLE_FOR_MOVE_READ://0b
begin
read_page_en <= 0;
if(cycles==2)
state <= RECEIVE_READ_DATA_FOR_MOVE;
else
begin
cycles <= cycles+1;
state <= WAIT_A_CYCLE_FOR_MOVE_READ;
end
end
RECEIVE_READ_DATA_FOR_MOVE://0c
begin
if(controller_rb_l_o)
begin
state <= ISSUE_WRITE_FOR_MOVE;
end
else
state <= WAIT_A_CYCLE_FOR_MOVE_READ;
end
ISSUE_WRITE_FOR_MOVE://0d
begin
write_page_en <= 1;
addr <= command[56:32];
cycles <= 0;
state <= WAIT_A_CYCLE_FOR_MOVE_WRITE;
end
WAIT_A_CYCLE_FOR_MOVE_WRITE://0e
begin
write_page_en <= 0;
if(cycles==2)
state <= WAIT_WRITE_FOR_MOVE;
else
begin
cycles <= cycles+1;
state <= WAIT_A_CYCLE_FOR_MOVE_WRITE;
end
end
WAIT_WRITE_FOR_MOVE://0f
begin
if(controller_rb_l_o)
begin
state <= MOVE_END;
end
else
state <= WAIT_WRITE_FOR_MOVE;
end
MOVE_END://10
begin
state <= FINISH;
end
/////////////////////////////////////////////////////////////////////////////////////////////////erase
ISSUE_ERASE://11
begin
if(controller_rb_l_o ==1 )
begin
erase_block_en <= 1;
addr <= command[24:0];
cycles <= 0;
state <= WAIT_A_CYCLE_FOR_ERASE;
end
else
state<=ISSUE_ERASE;
end
WAIT_A_CYCLE_FOR_ERASE://12
begin
erase_block_en <= 0;
if(cycles==2)
begin
state <= WAIT_ERASE;
cycles<=0;
end
else
begin
cycles <= cycles+1;
state<=WAIT_A_CYCLE_FOR_ERASE;
end
end
WAIT_ERASE://13
begin
if(controller_rb_l_o==1)
begin
cycles <= 0;
state <= ERASE_END;
end
else
state<=WAIT_ERASE;
end
ERASE_END://14
begin
if(cycles==8)
begin
state <= FINISH;
cycles<=0;
end
else
begin
state<=ERASE_END;
cycles <= cycles+1;
end
end
/////////////////////////////////////////////////////////////////////////////////////////////finish
FINISH://15
begin
state <= IDLE;
end
default: state <= IDLE;
endcase
end
end
endmodule
|
// bsg_hash_bank_reverse
//
// See paired module bsg_hash_bank.
// This module is the inverse; taking a bank number and an index, and producing the original address.
//
`include "bsg_defines.v"
module bsg_hash_bank_reverse #(parameter `BSG_INV_PARAM(banks_p), parameter `BSG_INV_PARAM(width_p), index_width_lp=$clog2((2**width_p+banks_p-1)/banks_p), lg_banks_lp=`BSG_SAFE_CLOG2(banks_p), debug_lp=0)
(/* input clk,*/
input [index_width_lp-1:0] index_i
, input [lg_banks_lp-1:0] bank_i
, output [width_p-1:0] o
);
if (banks_p == 1)
begin: hash1
assign o = index_i;
end
else
if (banks_p == 2)
begin: hash2
assign o = { bank_i, index_i };
end
else
if (~banks_p[0])
begin: hashpow2
assign o[width_p-1] = bank_i[0];
bsg_hash_bank_reverse #(.banks_p(banks_p >> 1),.width_p(width_p-1)) bhbr (/* .clk(clk) , */ .index_i(index_i[index_width_lp-1:0]),.bank_i(bank_i[lg_banks_lp-1:1]),.o(o[width_p-2:0]));
end
else
if ((banks_p & (banks_p+1)) == 0) // test for (2^N)-1
begin : hash3
if (width_p % lg_banks_lp)
begin : odd
wire _unused;
bsg_hash_bank_reverse #(.banks_p(banks_p),.width_p(width_p+1)) rhf
( /* .clk(clk),*/ .index_i({index_i, 1'b0}), .bank_i(bank_i), .o({o[width_p-1:0], _unused}));
end
else
begin : even
/* This is the hash function we implement.
Bank Zero, 0 XX XX --> 00 XX XX
Bank One, 0 XX XX --> 01 XX XX
Bank Two, 0 XX XX --> 10 XX XX
Bank Zero, 1 00 XX --> 11 00 XX
Bank One, 1 00 XX --> 11 01 XX
Bank Two, 1 00 XX --> 11 10 XX
Bank Zero, 1 01 00 --> 11 11 00
Bank One, 1 01 00 --> 11 11 01
Bank Two, 1 01 00 --> 11 11 10
Bank Zero, 1 01 01 --> 11 11 11
the algorithm is:
starting from the left; the first 00 you see, substitute the bank number
starting from the left; as long as you see 01, substitute 11.
*/
localparam frac_width_lp = width_p/lg_banks_lp;
wire [lg_banks_lp-1:0][frac_width_lp-1:0] unzippered;
wire [width_p-1:0] index_i_ext = (width_p) ' (index_i); // add 0's on
bsg_transpose #(.width_p(lg_banks_lp), .els_p(frac_width_lp)) unzip (.i(index_i_ext),.o(unzippered));
genvar j;
// and tuplets of lg_bank_lp-1 consecutive 0 bits
wire [frac_width_lp-1:0] zero_pair;
bsg_reduce_segmented #(.segments_p(frac_width_lp),.segment_width_p(lg_banks_lp),.nor_p(1)) brs
(.i(index_i_ext),.o(zero_pair));
wire [frac_width_lp-1:0] zero_pair_or_scan;
bsg_scan #(.width_p(frac_width_lp),.or_p(1)) scan
(.i(zero_pair),.o(zero_pair_or_scan));
// everything that is 0 should be converted to a 11
// the first 1 should be converted to the bank #
// the following 1's should just take the old bit values.
wire [frac_width_lp-1:0] first_one;
if (frac_width_lp > 1)
assign first_one = zero_pair_or_scan & ~{1'b0, zero_pair_or_scan[frac_width_lp-1:1]};
else
assign first_one = zero_pair_or_scan;
wire [lg_banks_lp-1:0][frac_width_lp-1:0] bits;
for (j = 0; j < lg_banks_lp; j=j+1)
begin: rof2
assign bits[j] = (zero_pair_or_scan & ~first_one & unzippered[j]) | (first_one & { frac_width_lp { bank_i[j] }}) | ~zero_pair_or_scan;
end
/* if (debug_lp)
begin
always @(negedge clk)
begin
$display ("%b %b -> ZP(%b) ZPS(%b) FO(%b) TB(%b) BB(%b) %b ",
index_i, bank_i, zero_pair, zero_pair_or_scan, first_one, top_bits, bot_bits, o);
end
end
*/
wire [width_p-1:0] transpose_lo;
bsg_transpose #(.els_p(lg_banks_lp), .width_p(frac_width_lp)) zip (.i({bits}),.o(transpose_lo));
assign o = transpose_lo[width_p-1:0];
end
end
else
initial
begin
assert(0) else $error("unhandled case, banks_p = ", banks_p);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_hash_bank_reverse)
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_ncio_prqq_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Description: Request Dqta Queue Buffer
// Top level Module: jbi_ncio_prqq_buf
// Where Instantiated: jbi_ncio
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
`include "jbi.h"
module jbi_ncio_prqq_buf(/*AUTOARG*/
// Outputs
prqq_rdata,
// Inputs
clk, hold, testmux_sel, scan_en, csr_16x81array_margin, prqq_csn_wr,
prqq_csn_rd, prqq_waddr, prqq_raddr, prqq_wdata
);
input clk;
input hold;
input testmux_sel;
input scan_en;
input [4:0] csr_16x81array_margin;
input prqq_csn_wr;
input prqq_csn_rd;
input [`JBI_PRQQ_ADDR_WIDTH-1:0] prqq_waddr;
input [`JBI_PRQQ_ADDR_WIDTH-1:0] prqq_raddr;
input [`JBI_PRQQ_WIDTH-1:0] prqq_wdata;
output [`JBI_PRQQ_WIDTH-1:0] prqq_rdata;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire [`JBI_PRQQ_WIDTH-1:0] prqq_rdata;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
wire [81-`JBI_PRQQ_WIDTH-1:0] dangle;
//
// Code start here
//
bw_rf_16x81 #(1, 1, 1, 0) u_prqq_buf
(.rd_clk(clk), // read clock
.wr_clk(clk), // read clock
.csn_rd(prqq_csn_rd), // read enable -- active low
.csn_wr(prqq_csn_wr), // write enable -- active low
.hold(hold), // Bypass signal -- unflopped -- bypass input data when 0
.scan_en(scan_en), // Scan enable unflopped
.margin(csr_16x81array_margin), // Delay for the circuits--- set to 10101
.rd_a(prqq_raddr), // read address
.wr_a(prqq_waddr), // Write address
.di({ {81-`JBI_PRQQ_WIDTH{1'b0}},
prqq_wdata[`JBI_PRQQ_WIDTH-1:0] }), // Data input
.testmux_sel(testmux_sel), // bypass signal -- unflopped -- testmux_sel = 1 bypasses di to do
.si(), // scan in -- NOT CONNECTED
.so(), // scan out -- TIED TO ZERO
.listen_out(), // Listening flop--
.do( {dangle,
prqq_rdata[`JBI_PRQQ_WIDTH-1:0]} ) // Data out
);
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
// iZsh <izsh at fail0verflow.com>, June 2014
//-----------------------------------------------------------------------------
// Defining modes and options. This must be aligned to the definitions in fpgaloader.h
// Note: the definitions here are without shifts
// Major modes:
`define FPGA_MAJOR_MODE_LF_ADC 0
`define FPGA_MAJOR_MODE_LF_EDGE_DETECT 1
`define FPGA_MAJOR_MODE_LF_PASSTHRU 2
`define FPGA_MAJOR_MODE_HF_READER 0
`define FPGA_MAJOR_MODE_HF_SIMULATOR 1
`define FPGA_MAJOR_MODE_HF_ISO14443A 2
`define FPGA_MAJOR_MODE_HF_SNOOP 3
`define FPGA_MAJOR_MODE_HF_GET_TRACE 4
`define FPGA_MAJOR_MODE_OFF 7
// Options for the generic HF reader
`define FPGA_HF_READER_MODE_RECEIVE_IQ 0
`define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE 1
`define FPGA_HF_READER_MODE_RECEIVE_PHASE 2
`define FPGA_HF_READER_MODE_SEND_FULL_MOD 3
`define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD 4
`define FPGA_HF_READER_MODE_SNIFF_IQ 5
`define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE 6
`define FPGA_HF_READER_MODE_SNIFF_PHASE 7
`define FPGA_HF_READER_SUBCARRIER_848_KHZ 0
`define FPGA_HF_READER_SUBCARRIER_424_KHZ 1
`define FPGA_HF_READER_SUBCARRIER_212_KHZ 2
// Options for the HF simulated tag, how to modulate
`define FPGA_HF_SIMULATOR_NO_MODULATION 0
`define FPGA_HF_SIMULATOR_MODULATE_BPSK 1
`define FPGA_HF_SIMULATOR_MODULATE_212K 2
`define FPGA_HF_SIMULATOR_MODULATE_424K 4
`define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 5
// Options for ISO14443A
`define FPGA_HF_ISO14443A_SNIFFER 0
`define FPGA_HF_ISO14443A_TAGSIM_LISTEN 1
`define FPGA_HF_ISO14443A_TAGSIM_MOD 2
`define FPGA_HF_ISO14443A_READER_LISTEN 3
`define FPGA_HF_ISO14443A_READER_MOD 4
`include "hi_reader.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "hi_sniffer.v"
`include "hi_get_trace.v"
`include "util.v"
module fpga_hf(
input spck, output miso, input mosi, input ncs,
input pck0, input ck_1356meg, input ck_1356megb,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk, output adc_noe,
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo,
output dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] conf_word;
reg trace_enable;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
4'b0010: trace_enable <= shift_reg[0]; // FPGA_CMD_TRACE_ENABLE
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
// select module (outputs) based on major mode
wire [2:0] major_mode = conf_word[7:5];
// configuring the HF reader
wire [1:0] subcarrier_frequency = conf_word[4:3];
wire [2:0] minor_mode = conf_word[2:0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
hi_reader hr(
ck_1356megb,
hr_pwr_lo, hr_pwr_hi, hr_pwr_oe1, hr_pwr_oe2, hr_pwr_oe3, hr_pwr_oe4,
adc_d, hr_adc_clk,
hr_ssp_frame, hr_ssp_din, ssp_dout, hr_ssp_clk,
hr_dbg,
subcarrier_frequency, minor_mode
);
hi_simulate hs(
ck_1356meg,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
hs_dbg,
minor_mode
);
hi_iso14443a hisn(
ck_1356meg,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
hisn_dbg,
minor_mode
);
hi_sniffer he(
ck_1356megb,
he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
adc_d, he_adc_clk,
he_ssp_frame, he_ssp_din, he_ssp_clk
);
hi_get_trace gt(
ck_1356megb,
adc_d, trace_enable, major_mode,
gt_ssp_frame, gt_ssp_din, gt_ssp_clk
);
// Major modes:
// 000 -- HF reader; subcarrier frequency and modulation depth selectable
// 001 -- HF simulated tag
// 010 -- HF ISO14443-A
// 011 -- HF Snoop
// 100 -- HF get trace
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, hr_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, gt_ssp_clk, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, hr_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, gt_ssp_din, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, hr_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, gt_ssp_frame, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, hr_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, hr_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, hr_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, hr_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, hr_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, hr_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, hr_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_dbg (major_mode, dbg, hr_dbg, hs_dbg, hisn_dbg, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
// not used
assign miso = 1'b0;
endmodule
|
// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1 162 at 2014.01.24.12:33:53
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_11"),
.ENUM_MEM_IF_TCWL ("TCWL_8"),
.ENUM_MEM_IF_TFAW ("TFAW_12"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (104),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2A_4_V
`define SKY130_FD_SC_HS__O2BB2A_4_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2bb2a_4 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2bb2a_4 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2A_4_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_never_assert
assert_never_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_never_assume
assert_never_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_never.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_never_assert (clk, reset_n, test_expr, xzcheck_enable);
input clk, reset_n, test_expr, xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_never_assume (clk, reset_n, test_expr, xzcheck_enable);
input clk, reset_n, test_expr, xzcheck_enable;
endmodule
|
//--------------------------------------------------------------------------------
//
// data_align.v
// Copyright (C) 2011 Ian Davis
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details:
// http://www.dangerousprototypes.com/ols
// http://www.gadgetfactory.net/gf/project/butterflylogic
// http://www.mygizmos.org/ols
//
// This module takes the sampled input, and shifts/compacts the data to
// eliminate any disabled groups. ie:
//
// Channels 0,1,2 are disabled:
// sto_data[7:0] = channel3 (sti_data[31:24])
//
// Channels 1,2 are disabled:
// sto_data[15:0] = {channel3,channel0} (sti_data[31:24],sti_data[7:0])
//
// Compacting the data like this allows for easier RLE & filling of SRAM.
//
//--------------------------------------------------------------------------------
`timescale 1ns/100ps
module data_align #(
parameter integer DW = 32, // data width
parameter integer KW = DW/8 // keep width
)(
// system signals
input wire clk,
input wire rst,
// configuration/control signals
input wire [3:0] disabledGroups,
// input stream
input wire sti_valid,
input wire [31:0] sti_data,
// output stream
output reg sto_valid,
output reg [31:0] sto_data
);
//
// Registers...
//
reg [1:0] insel0;
reg [1:0] insel1;
reg insel2;
//
// Input data mux...
//
always @ (posedge clk)
begin
case (insel0[1:0])
2'h3 : sto_data[ 7: 0] <= sti_data[31:24];
2'h2 : sto_data[ 7: 0] <= sti_data[23:16];
2'h1 : sto_data[ 7: 0] <= sti_data[15: 8];
default : sto_data[ 7: 0] <= sti_data[ 7: 0];
endcase
case (insel1[1:0])
2'h2 : sto_data[15: 8] <= sti_data[31:24];
2'h1 : sto_data[15: 8] <= sti_data[23:16];
default : sto_data[15: 8] <= sti_data[15: 8];
endcase
case (insel2)
1'b1 : sto_data[23:16] <= sti_data[31:24];
default : sto_data[23:16] <= sti_data[23:16];
endcase
sto_data[31:24] <= sti_data[31:24];
end
//
// This block computes the mux settings for mapping the various
// possible channels combinations onto the 32 bit BRAM block.
//
// If one group is selected, inputs are mapped to bits [7:0].
// If two groups are selected, inputs are mapped to bits [15:0].
// If three groups are selected, inputs are mapped to bits [23:0].
// Otherwise, input pass unchanged...
//
// Each "insel" signal controls the select for an output mux.
//
// ie: insel0 controls what is -output- on bits[7:0].
// Thus, if insel0 equal 2, sto_data[7:0] = sti_data[23:16]
//
always @(posedge clk)
begin
case (disabledGroups)
// 24 bit configs...
4'b0001 : begin insel2 <= 1'b1; insel1 <= 2'h1; insel0 <= 2'h1; end
4'b0010 : begin insel2 <= 1'b1; insel1 <= 2'h1; insel0 <= 2'h0; end
4'b0100 : begin insel2 <= 1'b1; insel1 <= 2'h0; insel0 <= 2'h0; end
// 16 bit configs...
4'b0011 : begin insel2 <= 1'b0; insel1 <= 2'h2; insel0 <= 2'h2; end
4'b0101 : begin insel2 <= 1'b0; insel1 <= 2'h2; insel0 <= 2'h1; end
4'b1001 : begin insel2 <= 1'b0; insel1 <= 2'h1; insel0 <= 2'h1; end
4'b0110 : begin insel2 <= 1'b0; insel1 <= 2'h2; insel0 <= 2'h0; end
4'b1010 : begin insel2 <= 1'b0; insel1 <= 2'h1; insel0 <= 2'h0; end
4'b1100 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h0; end
// 8 bit configs...
4'b0111 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h3; end
4'b1011 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h2; end
4'b1101 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h1; end
// remaining
default : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h0; end
endcase
end
always @(posedge clk, posedge rst)
if (rst) sto_valid <= 1'b0;
else sto_valid <= sti_valid;
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module cmd_seq
#(
parameter BASEADDR = 32'h0000,
parameter HIGHADDR = 32'h0000,
parameter ABUSWIDTH = 16,
parameter OUTPUTS = 1,
parameter CMD_MEM_SIZE = 2048
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire [OUTPUTS-1:0] CMD_CLK_OUT,
input wire CMD_CLK_IN,
input wire CMD_EXT_START_FLAG,
output wire CMD_EXT_START_ENABLE,
output wire [OUTPUTS-1:0] CMD_DATA,
output wire CMD_READY,
output wire CMD_START_FLAG
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
cmd_seq_core
#(
.CMD_MEM_SIZE(CMD_MEM_SIZE),
.ABUSWIDTH(ABUSWIDTH),
.OUTPUTS(OUTPUTS)
) i_cmd_seq_core
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CMD_CLK_OUT(CMD_CLK_OUT),
.CMD_CLK_IN(CMD_CLK_IN),
.CMD_EXT_START_FLAG(CMD_EXT_START_FLAG),
.CMD_EXT_START_ENABLE(CMD_EXT_START_ENABLE),
.CMD_DATA(CMD_DATA),
.CMD_READY(CMD_READY),
.CMD_START_FLAG(CMD_START_FLAG)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: phy_wrlvl.v
// /___/ /\ Date Last Modified: $Date: 2011/05/27 14:31:03 $
// \ \ / \ Date Created: Mon Jun 23 2008
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Memory initialization and overall master state control during
// initialization and calibration. Specifically, the following functions
// are performed:
// 1. Memory initialization (initial AR, mode register programming, etc.)
// 2. Initiating write leveling
// 3. Generate training pattern writes for read leveling. Generate
// memory readback for read leveling.
// This module has a DFI interface for providing control/address and write
// data to the rest of the PHY datapath during initialization/calibration.
// Once initialization is complete, control is passed to the MC.
// NOTES:
// 1. Multiple CS (multi-rank) not supported
// 2. DDR2 not supported
// 3. ODT not supported
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_wrlvl.v,v 1.16.8.2 2011/05/27 14:31:03 venkatp Exp $
**$Date: 2011/05/27 14:31:03 $
**$Author: venkatp $
**$Revision: 1.16.8.2 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_2/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/phy_wrlvl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_wrlvl #
(
parameter TCQ = 100,
parameter DQS_CNT_WIDTH = 3,
parameter DQ_WIDTH = 64,
parameter DQS_WIDTH = 2,
parameter DRAM_WIDTH = 8,
parameter RANKS = 1,
parameter nCK_PER_CLK = 4,
parameter CLK_PERIOD = 4,
parameter SIM_CAL_OPTION = "NONE"
)
(
input clk,
input rst,
input phy_ctl_ready,
input wr_level_start,
input wl_sm_start,
input [(DQ_WIDTH)-1:0] rd_data_rise0,
output reg dqs_po_dec_done,
output phy_ctl_rdy_dly,
output reg wr_level_done,
// to phy_init for cs logic
output wrlvl_rank_done,
output done_dqs_tap_inc,
output [DQS_CNT_WIDTH:0] po_stg2_wl_cnt,
// Fine delay line used only during write leveling
// Inc/dec Phaser_Out fine delay line
output reg dqs_po_stg2_f_incdec,
// Enable Phaser_Out fine delay inc/dec
output reg dqs_po_en_stg2_f,
// Coarse delay line used during write leveling
// only if 64 taps of fine delay line were not
// sufficient to detect a 0->1 transition
// Inc Phaser_Out coarse delay line
output reg dqs_wl_po_stg2_c_incdec,
// Enable Phaser_Out coarse delay inc/dec
output reg dqs_wl_po_en_stg2_c,
// Load Phaser_Out delay line
output reg po_counter_read_en,
input [8:0] po_counter_read_val,
// output reg dqs_wl_po_stg2_load,
// output reg [8:0] dqs_wl_po_stg2_reg_l,
// CK edge undetected
output reg wrlvl_err,
output reg [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,
output reg [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
// Debug ports
output [5:0] dbg_wl_tap_cnt,
output dbg_wl_edge_detect_valid,
output [(DQS_WIDTH)-1:0] dbg_rd_data_edge_detect,
output [DQS_CNT_WIDTH:0] dbg_dqs_count,
output [4:0] dbg_wl_state
);
localparam WL_IDLE = 5'h0;
localparam WL_INIT = 5'h1;
localparam WL_FINE_INC = 5'h2;
localparam WL_WAIT = 5'h3;
localparam WL_EDGE_CHECK = 5'h4;
localparam WL_DQS_CHECK = 5'h5;
localparam WL_DQS_CNT = 5'h6;
localparam WL_2RANK_TAP_DEC = 5'h7;
localparam WL_2RANK_DQS_CNT = 5'h8;
localparam WL_FINE_DEC = 5'h9;
localparam WL_FINE_DEC_WAIT = 5'hA;
localparam WL_CORSE_INC = 5'hB;
localparam WL_CORSE_INC_WAIT = 5'hC;
localparam WL_CORSE_INC_WAIT1 = 5'hD;
localparam WL_CORSE_INC_WAIT2 = 5'hE;
localparam WL_CORSE_DEC = 5'hF;
localparam WL_CORSE_DEC_WAIT = 5'h10;
localparam WL_FINE_INC_WAIT = 5'h11;
localparam WL_2RANK_FINAL_TAP = 5'h12;
localparam COARSE_TAPS = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 4 : 7;
integer i, j, k, l, p, q;
reg phy_ctl_ready_r1;
reg phy_ctl_ready_r2;
reg phy_ctl_ready_r3;
reg phy_ctl_ready_r4;
reg phy_ctl_ready_r5;
reg phy_ctl_ready_r6;
reg [DQS_CNT_WIDTH:0] dqs_count_r;
reg [1:0] rank_cnt_r;
reg [DQS_WIDTH-1:0] rd_data_rise_wl_r;
reg [DQS_WIDTH-1:0] rd_data_previous_r;
reg [DQS_WIDTH-1:0] rd_data_edge_detect_r;
reg wr_level_done_r;
reg wrlvl_rank_done_r;
reg wr_level_start_r;
reg [4:0] wl_state_r, wl_state_r1;
reg wl_edge_detect_valid_r;
reg [5:0] wl_tap_count_r;
reg [5:0] fine_dec_cnt;
reg [6*DQS_WIDTH-1:0] fine_inc;
reg [3*DQS_WIDTH-1:0] corse_dec;
reg [3*DQS_WIDTH-1:0] corse_inc;
reg dq_cnt_inc;
reg [2:0] stable_cnt;
reg flag_ck_negedge;
reg flag_init;
reg [3*DQS_WIDTH-1:0] corse_cnt;
reg [3*DQS_WIDTH-1:0] wl_corse_cnt[0:RANKS-1];
//reg [3*DQS_WIDTH-1:0] coarse_tap_inc;
reg [3*DQS_WIDTH-1:0] final_coarse_tap;
reg [6*DQS_WIDTH-1:0] add_smallest;
reg [6*DQS_WIDTH-1:0] add_largest;
//reg [6*DQS_WIDTH-1:0] fine_tap_inc;
//reg [6*DQS_WIDTH-1:0] fine_tap_dec;
reg wr_level_done_r1;
reg wr_level_done_r2;
reg wr_level_done_r3;
reg wr_level_done_r4;
reg wr_level_done_r5;
reg [6*DQS_WIDTH-1:0] wl_dqs_tap_count_r[0:RANKS-1];
reg [6*DQS_WIDTH-1:0] smallest;
reg [6*DQS_WIDTH-1:0] largest;
reg [6*DQS_WIDTH-1:0] final_val;
reg [5:0] po_dec_cnt[0:DQS_WIDTH-1];
reg done_dqs_dec;
reg [8:0] po_rdval_cnt;
reg po_cnt_dec;
reg dual_rnk_dec;
wire [DQS_CNT_WIDTH+2:0] dqs_count_w;
// Debug ports
assign dbg_wl_edge_detect_valid = wl_edge_detect_valid_r;
assign dbg_rd_data_edge_detect = rd_data_edge_detect_r;
assign dbg_wl_tap_cnt = wl_tap_count_r;
assign dbg_dqs_count = dqs_count_r;
assign dbg_wl_state = wl_state_r;
//**************************************************************************
// DQS count to hard PHY during write leveling using Phaser_OUT Stage2 delay
//**************************************************************************
assign po_stg2_wl_cnt = dqs_count_r;
assign wrlvl_rank_done = wrlvl_rank_done_r;
assign done_dqs_tap_inc = done_dqs_dec;
assign phy_ctl_rdy_dly = phy_ctl_ready_r6;
always @(posedge clk) begin
phy_ctl_ready_r1 <= #TCQ phy_ctl_ready;
phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1;
phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2;
phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3;
phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4;
phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5;
wr_level_done <= #TCQ done_dqs_dec;
end
always @(posedge clk) begin
if (rst)
po_counter_read_en <= #TCQ 1'b0;
else if (phy_ctl_ready_r1 && ~phy_ctl_ready_r2)
po_counter_read_en <= #TCQ 1'b1;
else
po_counter_read_en <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst) begin
po_rdval_cnt <= #TCQ 'd0;
end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin
po_rdval_cnt <= #TCQ po_counter_read_val;
end else if (po_rdval_cnt > 'd0) begin
if (po_cnt_dec)
po_rdval_cnt <= #TCQ po_rdval_cnt - 1;
else
po_rdval_cnt <= #TCQ po_rdval_cnt;
end else if (po_rdval_cnt == 'd0) begin
po_rdval_cnt <= #TCQ po_rdval_cnt;
end
end
always @(posedge clk) begin
if (rst) begin
po_cnt_dec <= #TCQ 1'b0;
end else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0)) begin
po_cnt_dec <= #TCQ ~po_cnt_dec;
end else if (po_rdval_cnt == 'd0) begin
po_cnt_dec <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
dqs_po_dec_done <= #TCQ 1'b0;
end else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) ||
(phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin
dqs_po_dec_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
wr_level_done_r1 <= #TCQ wr_level_done_r;
wr_level_done_r2 <= #TCQ wr_level_done_r1;
wr_level_done_r3 <= #TCQ wr_level_done_r2;
wr_level_done_r4 <= #TCQ wr_level_done_r3;
wr_level_done_r5 <= #TCQ wr_level_done_r4;
wl_po_coarse_cnt <= #TCQ final_coarse_tap;
for (l = 0; l < DQS_WIDTH; l = l + 1) begin
if (RANKS == 1)
wl_po_fine_cnt[6*l+:6] <= #TCQ smallest[6*l+:6];
else
wl_po_fine_cnt[6*l+:6] <= #TCQ final_val[6*l+:6];
end
end
generate
if (RANKS == 2) begin: dual_rank
always @(posedge clk) begin
if (rst)
done_dqs_dec <= #TCQ 1'b0;
else if (SIM_CAL_OPTION == "FAST_CAL")
done_dqs_dec <= #TCQ wr_level_done_r;
else if (wr_level_done_r5 && (wl_state_r == WL_IDLE))
done_dqs_dec <= #TCQ 1'b1;
end
end else begin: single_rank
always @(posedge clk) begin
if (rst)
done_dqs_dec <= #TCQ 1'b0;
else if (wr_level_done_r3)
done_dqs_dec <= #TCQ 1'b1;
end
end
endgenerate
// Storing DQS tap values at the end of each DQS write leveling
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < RANKS; k = k + 1) begin: rst_wl_dqs_tap_count_loop
wl_dqs_tap_count_r[k] <= #TCQ 'b0;
wl_corse_cnt[k] <= #TCQ 'b0;
end
end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_WAIT) |
(wl_state_r == WL_2RANK_TAP_DEC)) begin
wl_dqs_tap_count_r[rank_cnt_r][(6*dqs_count_r)+:6]
<= #TCQ wl_tap_count_r;
wl_corse_cnt[rank_cnt_r][3*dqs_count_r+:3]
<= #TCQ corse_cnt[3*dqs_count_r+:3];
end else if ((SIM_CAL_OPTION == "FAST_CAL") & (wl_state_r == WL_DQS_CHECK)) begin
for (p = 0; p < RANKS; p = p +1) begin: dqs_tap_rank_cnt
for(q = 0; q < DQS_WIDTH; q = q +1) begin: dqs_tap_dqs_cnt
wl_dqs_tap_count_r[p][(6*q)+:6] <= #TCQ wl_tap_count_r;
wl_corse_cnt[p][3*q+:3] <= #TCQ corse_cnt[2:0];
end
end
end
end
// Convert coarse delay to fine taps in case of unequal number of coarse
// taps between ranks. Assuming a difference of 1 coarse tap counts
// between ranks. A common fine and coarse tap value must be used for both ranks
// because Phaser_Out has only one rank register.
// Coarse tap1 = period(ps)*93/360 = 34 fine taps
// Other coarse taps = period(ps)*103/360 = 38 fine taps
generate
genvar cnt;
if (RANKS == 2) begin // Dual rank
for(cnt = 0; cnt < DQS_WIDTH; cnt = cnt +1) begin: coarse_dqs_cnt
always @(posedge clk) begin
if (rst) begin
//coarse_tap_inc[3*cnt+:3] <= #TCQ 'b0;
add_smallest[6*cnt+:6] <= #TCQ 'd0;
add_largest[6*cnt+:6] <= #TCQ 'd0;
final_coarse_tap[3*cnt+:3]<= #TCQ 'd0;
end else if (wr_level_done_r1 & ~wr_level_done_r2) begin
if (wl_corse_cnt[0][3*cnt+:3] == wl_corse_cnt[1][3*cnt+:3]) begin
// Both ranks have use the same number of coarse delay taps.
// No conversion of coarse tap to fine taps required.
//coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3];
final_coarse_tap[3*cnt+:3]<= #TCQ wl_corse_cnt[1][3*cnt+:3];
add_smallest[6*cnt+:6] <= #TCQ 'd0;
add_largest[6*cnt+:6] <= #TCQ 'd0;
end else if (wl_corse_cnt[0][3*cnt+:3] < wl_corse_cnt[1][3*cnt+:3]) begin
// Rank 0 uses fewer coarse delay taps than rank1.
// conversion of coarse tap to fine taps required for rank1.
// The final coarse count will the smaller value.
//coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3] - 1;
final_coarse_tap[3*cnt+:3]<= #TCQ wl_corse_cnt[1][3*cnt+:3] - 1;
if (wl_corse_cnt[0][3*cnt+:3] > 3'b000)
// Coarse tap 2 or higher being converted to fine taps
// This will be added to 'largest' value in final_val
// computation
add_largest[6*cnt+:6] <= #TCQ 'd38;
else
// Coarse tap 1 being converted to fine taps
// This will be added to 'largest' value in final_val
// computation
add_largest[6*cnt+:6] <= #TCQ 'd34;
end else if (wl_corse_cnt[0][3*cnt+:3] > wl_corse_cnt[1][3*cnt+:3]) begin
// This may be an unlikely scenario in a real system.
// Rank 0 uses more coarse delay taps than rank1.
// conversion of coarse tap to fine taps required.
//coarse_tap_inc[3*cnt+:3] <= #TCQ 'd0;
final_coarse_tap[3*cnt+:3]<= #TCQ wl_corse_cnt[1][3*cnt+:3];
if (wl_corse_cnt[1][3*cnt+:3] > 3'b000)
// Coarse tap 2 or higher being converted to fine taps
// This will be added to 'smallest' value in final_val
// computation
add_smallest[6*cnt+:6] <= #TCQ 'd38;
else
// Coarse tap 1 being converted to fine taps
// This will be added to 'smallest' value in
// final_val computation
add_smallest[6*cnt+:6] <= #TCQ 'd34;
end
end
end
end
end else begin
// Single rank
always @(posedge clk) begin
//coarse_tap_inc <= #TCQ 'd0;
final_coarse_tap <= #TCQ wl_corse_cnt[0];
add_smallest <= #TCQ 'd0;
add_largest <= #TCQ 'd0;
end
end
endgenerate
// Determine delay value for DQS in multirank system
// Assuming delay value is the smallest for rank 0 DQS
// and largest delay value for rank 4 DQS
// Set to smallest + ((largest-smallest)/2)
always @(posedge clk) begin
if (rst) begin
smallest <= #TCQ 'b0;
largest <= #TCQ 'b0;
end else if ((wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_2RANK_TAP_DEC)) begin
smallest[6*dqs_count_r+:6]
<= #TCQ wl_dqs_tap_count_r[0][6*dqs_count_r+:6];
largest[6*dqs_count_r+:6]
<= #TCQ wl_dqs_tap_count_r[RANKS-1][6*dqs_count_r+:6];
end else if ((SIM_CAL_OPTION == "FAST_CAL") &
wr_level_done_r1 & ~wr_level_done_r2) begin
for(i = 0; i < DQS_WIDTH; i = i +1) begin: smallest_dqs
smallest[6*i+:6]
<= #TCQ wl_dqs_tap_count_r[0][6*i+:6];
largest[6*i+:6]
<= #TCQ wl_dqs_tap_count_r[0][6*i+:6];
end
end
end
// final_val to be used for all DQSs in all ranks
genvar wr_i;
generate
for (wr_i = 0; wr_i < DQS_WIDTH; wr_i = wr_i +1) begin: gen_final_tap
always @(posedge clk) begin
if (rst)
final_val[6*wr_i+:6] <= #TCQ 'b0;
else if (wr_level_done_r2 && ~wr_level_done_r3) begin
if ((smallest[6*wr_i+:6] + add_smallest[6*wr_i+:6]) <
(largest[6*wr_i+:6] + add_largest[6*wr_i+:6]))
final_val[6*wr_i+:6] <= #TCQ
((smallest[6*wr_i+:6] + add_smallest[6*wr_i+:6]) +
(((largest[6*wr_i+:6] + add_largest[6*wr_i+:6]) -
(smallest[6*wr_i+:6] + add_smallest[6*wr_i+:6]))/2));
else if ((smallest[6*wr_i+:6] + add_smallest[6*wr_i+:6]) >
(largest[6*wr_i+:6] + add_largest[6*wr_i+:6]))
final_val[6*wr_i+:6] <= #TCQ
((largest[6*wr_i+:6] + add_largest[6*wr_i+:6]) +
(((smallest[6*wr_i+:6] + add_smallest[6*wr_i+:6]) -
(largest[6*wr_i+:6] + add_largest[6*wr_i+:6]))/2));
else if ((smallest[6*wr_i+:6] + add_smallest[6*wr_i+:6]) ==
(largest[6*wr_i+:6] + add_largest[6*wr_i+:6]))
final_val[6*wr_i+:6] <= #TCQ
(largest[6*wr_i+:6] + add_largest[6*wr_i+:6]);
end
end
end
endgenerate
// // fine tap inc/dec value for all DQSs in all ranks
// genvar dqs_i;
// generate
// for (dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i +1) begin: gen_fine_tap
// always @(posedge clk) begin
// if (rst)
// fine_tap_inc[6*dqs_i+:6] <= #TCQ 'd0;
// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0;
// else if (wr_level_done_r3 && ~wr_level_done_r4) begin
// fine_tap_inc[6*dqs_i+:6] <= #TCQ final_val[6*dqs_i+:6];
// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0;
// end
// end
// endgenerate
// Inc/Dec Phaser_Out stage 2 fine delay line
always @(posedge clk) begin
if (rst) begin
// Fine delay line used only during write leveling
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b0;
// Dec Phaser_Out fine delay (1)before write leveling,
// (2)if no 0 to 1 transition detected with 63 fine delay taps, or
// (3)dual rank case where fine taps for the first rank need to be 0
end else if (po_cnt_dec || (wl_state_r == WL_FINE_DEC)) begin
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b1;
// Inc Phaser_Out fine delay during write leveling
end else if (wl_state_r == WL_FINE_INC) begin
dqs_po_stg2_f_incdec <= #TCQ 1'b1;
dqs_po_en_stg2_f <= #TCQ 1'b1;
end else begin
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b0;
end
end
// Inc Phaser_Out stage 2 Coarse delay line
always @(posedge clk) begin
if (rst) begin
// Coarse delay line used during write leveling
// only if no 0->1 transition undetected with 64
// fine delay line taps
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0;
dqs_wl_po_en_stg2_c <= #TCQ 1'b0;
// Inc Phaser_Out coarse delay during write leveling
end else if (wl_state_r == WL_CORSE_INC) begin
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b1;
dqs_wl_po_en_stg2_c <= #TCQ 1'b1;
end else if (wl_state_r == WL_CORSE_DEC) begin
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0;
dqs_wl_po_en_stg2_c <= #TCQ 1'b1;
end else begin
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0;
dqs_wl_po_en_stg2_c <= #TCQ 1'b0;
end
end
// only storing the rise data for checking. The data comming back during
// write leveling will be a static value. Just checking for rise data is
// enough.
genvar rd_i;
generate
for(rd_i = 0; rd_i < DQS_WIDTH; rd_i = rd_i +1)begin: gen_rd
always @(posedge clk)
rd_data_rise_wl_r[rd_i] <=
#TCQ |rd_data_rise0[(rd_i*DRAM_WIDTH)+DRAM_WIDTH-1:rd_i*DRAM_WIDTH];
end
endgenerate
// storing the previous data for checking later.
always @(posedge clk)begin
if ((wl_state_r == WL_INIT) || (wl_state_r == WL_CORSE_INC_WAIT2) ||
(wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT) ||
(wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) ||
(wl_state_r == WL_CORSE_INC_WAIT1) ||
((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)))
rd_data_previous_r <= #TCQ rd_data_rise_wl_r;
end
// changed stable count from 3 to 7 because of fine tap resolution
always @(posedge clk)begin
if (rst | (wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_2RANK_TAP_DEC) |
(wl_state_r == WL_FINE_DEC))
stable_cnt <= #TCQ 3'd0;
else if ((wl_tap_count_r > 6'd0) &
(wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)) begin
if ((rd_data_previous_r[dqs_count_r] == rd_data_rise_wl_r[dqs_count_r])
& (stable_cnt < 3'd7))
stable_cnt <= #TCQ stable_cnt + 1;
else if (rd_data_previous_r[dqs_count_r] != rd_data_rise_wl_r[dqs_count_r])
stable_cnt <= #TCQ 3'd0;
end
end
// Flag to indicate negedge of CK detected and ignore 0->1 transitions
// in this region
always @(posedge clk)begin
if (rst | (wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_DQS_CHECK) | wr_level_done_r)
flag_ck_negedge <= #TCQ 1'd0;
else if (rd_data_previous_r[dqs_count_r] && ((stable_cnt > 3'd0) |
(wl_state_r == WL_FINE_DEC) | (wl_state_r == WL_FINE_DEC_WAIT)))
flag_ck_negedge <= #TCQ 1'd1;
else if (~rd_data_previous_r[dqs_count_r] && (stable_cnt == 3'd7))
//&& flag_ck_negedge)
flag_ck_negedge <= #TCQ 1'd0;
end
// Flag to inhibit rd_data_edge_detect_r before stable DQ
always @(posedge clk) begin
if (rst)
flag_init <= #TCQ 1'b1;
else if (wl_state_r == WL_INIT)
flag_init <= #TCQ 1'b0;
end
//checking for transition from 0 to 1
always @(posedge clk)begin
if (rst | flag_ck_negedge | flag_init | (wl_tap_count_r < 'd1))
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else if (rd_data_edge_detect_r[dqs_count_r] == 1'b1) begin
if ((wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT) ||
(wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) ||
(wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2))
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else
rd_data_edge_detect_r <= #TCQ rd_data_edge_detect_r;
end else if (rd_data_previous_r[dqs_count_r] && (stable_cnt < 3'd7))
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else
rd_data_edge_detect_r <= #TCQ (~rd_data_previous_r &
rd_data_rise_wl_r);
end
// registring the write level start signal
always@(posedge clk) begin
wr_level_start_r <= #TCQ wr_level_start;
end
// Assign dqs_count_r to dqs_count_w to perform the shift operation
// instead of multiply operation
assign dqs_count_w = {2'b00, dqs_count_r};
// state machine to initiate the write leveling sequence
// The state machine operates on one byte at a time.
// It will increment the delays to the DQS OSERDES
// and sample the DQ from the memory. When it detects
// a transition from 1 to 0 then the write leveling is considered
// done.
always @(posedge clk) begin
if(rst)begin
wrlvl_err <= #TCQ 1'b0;
wr_level_done_r <= #TCQ 1'b0;
wrlvl_rank_done_r <= #TCQ 1'b0;
dqs_count_r <= #TCQ {DQS_CNT_WIDTH+1{1'b0}};
dq_cnt_inc <= #TCQ 1'b1;
rank_cnt_r <= #TCQ 2'b00;
wl_state_r <= #TCQ WL_IDLE;
wl_state_r1 <= #TCQ WL_IDLE;
wl_edge_detect_valid_r <= #TCQ 1'b0;
wl_tap_count_r <= #TCQ 6'b0;
fine_dec_cnt <= #TCQ 6'b0;
fine_inc <= #TCQ {6*DQS_WIDTH{1'b0}};
corse_dec <= #TCQ {3*DQS_WIDTH{1'b0}};
corse_inc <= #TCQ {3*DQS_WIDTH{1'b0}};
corse_cnt <= #TCQ {3*DQS_WIDTH{1'b0}};
dual_rnk_dec <= #TCQ 1'b0;
end else begin
wl_state_r1 <= #TCQ wl_state_r;
case (wl_state_r)
WL_IDLE: begin
wrlvl_rank_done_r <= #TCQ 1'd0;
if(!wr_level_done_r & wr_level_start_r & wl_sm_start)
wl_state_r <= #TCQ WL_INIT;
end
WL_INIT: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
wrlvl_rank_done_r <= #TCQ 1'd0;
if(wl_sm_start)
wl_state_r <= #TCQ WL_EDGE_CHECK; //WL_FINE_INC;
end
// Inc DQS Phaser_Out Stage2 Fine Delay line
WL_FINE_INC: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
if (wr_level_done_r5) begin
wl_tap_count_r <= #TCQ 'd0;
wl_state_r <= #TCQ WL_FINE_INC_WAIT;
//if (fine_inc[6*dqs_count_r+:6] > 'd0)
if (fine_inc[(dqs_count_w << 2 + dqs_count_w << 1)+:6] > 'd0)
//fine_inc[6*dqs_count_r+:6] <=
// #TCQ fine_inc[6*dqs_count_r+:6] - 1;
fine_inc[(dqs_count_w << 2 + dqs_count_w << 1)+:6] <=
#TCQ fine_inc[(dqs_count_w << 2 + dqs_count_w << 1)+:6] - 1;
else
//fine_inc[6*dqs_count_r+:6] <=
// #TCQ fine_inc[6*dqs_count_r+:6];
fine_inc[(dqs_count_w << 2 + dqs_count_w << 1)+:6] <=
#TCQ fine_inc[(dqs_count_w << 2 + dqs_count_w << 1)+:6];
end else begin
wl_state_r <= #TCQ WL_WAIT;
wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1;
end
end
WL_FINE_INC_WAIT: begin
//if (fine_inc[6*dqs_count_r+:6] > 'd0)
if (fine_inc[(dqs_count_w << 2 + dqs_count_w << 1)+:6] > 'd0)
wl_state_r <= #TCQ WL_FINE_INC;
else if (dqs_count_r == (DQS_WIDTH-1))
wl_state_r <= #TCQ WL_IDLE;
else begin
wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
dqs_count_r <= #TCQ dqs_count_r + 1;
end
end
WL_FINE_DEC: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
wl_tap_count_r <= #TCQ 'd0;
wl_state_r <= #TCQ WL_FINE_DEC_WAIT;
if (fine_dec_cnt > 6'd0)
fine_dec_cnt <= #TCQ fine_dec_cnt - 1;
else
fine_dec_cnt <= #TCQ fine_dec_cnt;
end
WL_FINE_DEC_WAIT: begin
if (fine_dec_cnt > 6'd0)
wl_state_r <= #TCQ WL_FINE_DEC;
else if (dual_rnk_dec) begin
if (corse_dec[3*dqs_count_r+:3] > 'd0)
wl_state_r <= #TCQ WL_CORSE_DEC;
else
wl_state_r <= #TCQ WL_2RANK_DQS_CNT;
end else
wl_state_r <= #TCQ WL_CORSE_INC;
end
WL_CORSE_DEC: begin
wl_state_r <= #TCQ WL_CORSE_DEC_WAIT;
dual_rnk_dec <= #TCQ 1'b0;
if (corse_dec[3*dqs_count_r+:3] > 6'd0)
corse_dec[3*dqs_count_r+:3] <=
#TCQ corse_dec[3*dqs_count_r+:3] - 1;
else
corse_dec <= #TCQ corse_dec;
end
WL_CORSE_DEC_WAIT: begin
if (corse_dec[3*dqs_count_r+:3] > 6'd0)
wl_state_r <= #TCQ WL_CORSE_DEC;
else
wl_state_r <= #TCQ WL_2RANK_DQS_CNT;
end
WL_CORSE_INC: begin
wl_state_r <= #TCQ WL_CORSE_INC_WAIT;
if (~wr_level_done_r5)
corse_cnt[3*dqs_count_r+:3] <=
#TCQ corse_cnt[3*dqs_count_r+:3] + 1;
else if (corse_inc[3*dqs_count_r+:3] > 'd0)
corse_inc[3*dqs_count_r+:3] <=
#TCQ corse_inc[3*dqs_count_r+:3] - 1;
end
WL_CORSE_INC_WAIT: begin
if (~wr_level_done_r5 && wl_sm_start)
wl_state_r <= #TCQ WL_CORSE_INC_WAIT1;
else if (wr_level_done_r5) begin
if (corse_inc[3*dqs_count_r+:3] > 'd0)
wl_state_r <= #TCQ WL_CORSE_INC;
//else if (fine_inc[6*dqs_count_r+:6] > 'd0)
else if (fine_inc[(dqs_count_w << 2 + dqs_count_w << 1)+:6] > 'd0)
wl_state_r <= #TCQ WL_FINE_INC;
else if (dqs_count_r == (DQS_WIDTH-1))
wl_state_r <= #TCQ WL_IDLE;
else begin
wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
dqs_count_r <= #TCQ dqs_count_r + 1;
end
end
end
WL_CORSE_INC_WAIT1: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_CORSE_INC_WAIT2;
end
WL_CORSE_INC_WAIT2: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_WAIT;
end
WL_WAIT: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_EDGE_CHECK;
end
WL_EDGE_CHECK: begin // Look for the edge
if (wl_edge_detect_valid_r == 1'b0) begin
wl_state_r <= #TCQ WL_WAIT;
wl_edge_detect_valid_r <= #TCQ 1'b1;
end
// 0->1 transition detected with DQS
else if(rd_data_edge_detect_r[dqs_count_r] &&
wl_edge_detect_valid_r)
begin
wl_tap_count_r <= #TCQ wl_tap_count_r;
if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2))
wl_state_r <= #TCQ WL_DQS_CNT;
else
wl_state_r <= #TCQ WL_2RANK_TAP_DEC;
end
// No transition detected with 63 taps of fine delay
// increment coarse delay by 1 tap, reset fine delay to '0'
// and begin detection of 1 -> 0 transition again
else if (wl_tap_count_r > 6'd40) begin
if (corse_cnt[3*dqs_count_r+:3] < COARSE_TAPS) begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end else
wrlvl_err <= #TCQ 1'b1;
end else
wl_state_r <= #TCQ WL_FINE_INC;
end
WL_2RANK_TAP_DEC: begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
corse_dec <= #TCQ corse_cnt;
wl_edge_detect_valid_r <= #TCQ 1'b0;
dual_rnk_dec <= #TCQ 1'b1;
end
WL_DQS_CNT: begin
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(dqs_count_r == (DQS_WIDTH-1))) begin
dqs_count_r <= #TCQ dqs_count_r;
dq_cnt_inc <= #TCQ 1'b0;
end else begin
dqs_count_r <= #TCQ dqs_count_r + 1'b1;
dq_cnt_inc <= #TCQ 1'b1;
end
wl_state_r <= #TCQ WL_DQS_CHECK;
wl_edge_detect_valid_r <= #TCQ 1'b0;
end
WL_2RANK_DQS_CNT: begin
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(dqs_count_r == (DQS_WIDTH-1))) begin
dqs_count_r <= #TCQ dqs_count_r;
dq_cnt_inc <= #TCQ 1'b0;
end else begin
dqs_count_r <= #TCQ dqs_count_r + 1'b1;
dq_cnt_inc <= #TCQ 1'b1;
end
wl_state_r <= #TCQ WL_DQS_CHECK;
wl_edge_detect_valid_r <= #TCQ 1'b0;
dual_rnk_dec <= #TCQ 1'b0;
end
WL_DQS_CHECK: begin // check if all DQS have been calibrated
wl_tap_count_r <= #TCQ 5'b0;
if (dq_cnt_inc == 1'b0)begin
wrlvl_rank_done_r <= #TCQ 1'd1;
corse_cnt <= #TCQ {3*DQS_WIDTH{1'b0}};
if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2)) begin
wl_state_r <= #TCQ WL_IDLE;
dqs_count_r <= #TCQ 5'd0;
end else if (rank_cnt_r == RANKS-1) begin
// wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
wl_state_r <= #TCQ WL_IDLE;
dqs_count_r <= #TCQ dqs_count_r;
end else begin
wl_state_r <= #TCQ WL_INIT;
dqs_count_r <= #TCQ 5'd0;
end
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(rank_cnt_r == RANKS-1)) begin
wr_level_done_r <= #TCQ 1'd1;
rank_cnt_r <= #TCQ 2'b00;
end else begin
wr_level_done_r <= #TCQ 1'd0;
rank_cnt_r <= #TCQ rank_cnt_r + 1'b1;
end
end else
wl_state_r <= #TCQ WL_INIT;
end
WL_2RANK_FINAL_TAP: begin
if (wr_level_done_r4 && ~wr_level_done_r5) begin
corse_inc <= #TCQ final_coarse_tap;
fine_inc <= #TCQ final_val;
dqs_count_r <= #TCQ 5'd0;
end else if (wr_level_done_r5) begin
if (corse_inc[3*dqs_count_r+:3] > 'd0)
wl_state_r <= #TCQ WL_CORSE_INC;
//else if (fine_inc[6*dqs_count_r+:6] > 'd0)
else if (fine_inc[(dqs_count_w << 2 + dqs_count_w << 1)+:6] > 'd0)
wl_state_r <= #TCQ WL_FINE_INC;
end
end
endcase
end
end // always @ (posedge clk)
endmodule
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module basys3_demo (
input clk,
output tx,
input rx,
input [15:0] sw,
output [15:0] led
);
// Input 100MHz clock through a BUFG
wire clk100;
BUFG bufg100 (.I(clk), .O(clk100));
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk100) begin
reset_cnt <= reset_cnt + !resetn;
end
// A simple GPIO peripheral connected to LEDs
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign led = gpio[15:0];
always @(posedge clk100) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= {sw, gpio[15:0]};
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
// The picosoc
picosoc_noflash soc (
.clk (clk100),
.resetn (resetn ),
.ser_tx (tx),
.ser_rx (rx),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DECAP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__DECAP_BEHAVIORAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DECAP_BEHAVIORAL_PP_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_gt (
// drp interface
up_drp_qpll0_sel,
up_drp_qpll0_wr,
up_drp_qpll0_addr,
up_drp_qpll0_wdata,
up_drp_qpll0_rdata,
up_drp_qpll0_ready,
up_drp_qpll1_sel,
up_drp_qpll1_wr,
up_drp_qpll1_addr,
up_drp_qpll1_wdata,
up_drp_qpll1_rdata,
up_drp_qpll1_ready,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter integer GTH_OR_GTX_N = 0;
// drp interface
output up_drp_qpll0_sel;
output up_drp_qpll0_wr;
output [11:0] up_drp_qpll0_addr;
output [15:0] up_drp_qpll0_wdata;
input [15:0] up_drp_qpll0_rdata;
input up_drp_qpll0_ready;
output up_drp_qpll1_sel;
output up_drp_qpll1_wr;
output [11:0] up_drp_qpll1_addr;
output [15:0] up_drp_qpll1_wdata;
input [15:0] up_drp_qpll1_rdata;
input up_drp_qpll1_ready;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 'd0;
reg up_drp_qpll0_sel = 'd0;
reg up_drp_qpll0_wr = 'd0;
reg up_drp_qpll0_status = 'd0;
reg up_drp_qpll0_rwn = 'd0;
reg [11:0] up_drp_qpll0_addr = 'd0;
reg [15:0] up_drp_qpll0_wdata = 'd0;
reg [15:0] up_drp_qpll0_rdata_hold = 'd0;
reg up_drp_qpll1_sel = 'd0;
reg up_drp_qpll1_wr = 'd0;
reg up_drp_qpll1_status = 'd0;
reg up_drp_qpll1_rwn = 'd0;
reg [11:0] up_drp_qpll1_addr = 'd0;
reg [15:0] up_drp_qpll1_wdata = 'd0;
reg [15:0] up_drp_qpll1_rdata_hold = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h10) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h10) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_drp_qpll0_sel <= 'd0;
up_drp_qpll0_wr <= 'd0;
up_drp_qpll0_status <= 'd0;
up_drp_qpll0_rwn <= 'd0;
up_drp_qpll0_addr <= 'd0;
up_drp_qpll0_wdata <= 'd0;
up_drp_qpll0_rdata_hold <= 'd0;
up_drp_qpll1_sel <= 'd0;
up_drp_qpll1_wr <= 'd0;
up_drp_qpll1_status <= 'd0;
up_drp_qpll1_rwn <= 'd0;
up_drp_qpll1_addr <= 'd0;
up_drp_qpll1_wdata <= 'd0;
up_drp_qpll1_rdata_hold <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_drp_qpll0_sel <= 1'b1;
up_drp_qpll0_wr <= ~up_wdata[28];
end else begin
up_drp_qpll0_sel <= 1'b0;
up_drp_qpll0_wr <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_drp_qpll0_status <= 1'b1;
end else if (up_drp_qpll0_ready == 1'b1) begin
up_drp_qpll0_status <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_drp_qpll0_rwn <= up_wdata[28];
up_drp_qpll0_addr <= up_wdata[27:16];
up_drp_qpll0_wdata <= up_wdata[15:0];
end
if (up_drp_qpll0_ready == 1'b1) begin
up_drp_qpll0_rdata_hold <= up_drp_qpll0_rdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_drp_qpll1_sel <= 1'b1;
up_drp_qpll1_wr <= ~up_wdata[28];
end else begin
up_drp_qpll1_sel <= 1'b0;
up_drp_qpll1_wr <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_drp_qpll1_status <= 1'b1;
end else if (up_drp_qpll1_ready == 1'b1) begin
up_drp_qpll1_status <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_drp_qpll1_rwn <= up_wdata[28];
up_drp_qpll1_addr <= up_wdata[27:16];
up_drp_qpll1_wdata <= up_wdata[15:0];
end
if (up_drp_qpll1_ready == 1'b1) begin
up_drp_qpll1_rdata_hold <= up_drp_qpll1_rdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h14: up_rdata <= {3'd0, up_drp_qpll0_rwn,
up_drp_qpll0_addr, up_drp_qpll0_wdata};
8'h15: up_rdata <= {15'd0, up_drp_qpll0_status, up_drp_qpll0_rdata};
8'h24: up_rdata <= {3'd0, up_drp_qpll1_rwn,
up_drp_qpll1_addr, up_drp_qpll1_wdata};
8'h25: up_rdata <= {15'd0, up_drp_qpll1_status, up_drp_qpll1_rdata};
8'h3a: up_rdata <= GTH_OR_GTX_N;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* $Id: red_pitaya_pid_block.v 961 2014-01-21 11:40:39Z matej.oblak $
*
* @brief Red Pitaya PID controller.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
/*
* GENERAL DESCRIPTION:
*
* Proportional-integral-derivative (PID) controller.
*
*
* /---\ /---\ /-----------\
* IN --| - |----+--> | P | ---> | SUM & SAT | ---> OUT
* \---/ | \---/ \-----------/
* ^ | ^ ^
* | | /---\ | |
* set ---- +--> | I | --------- |
* point | \---/ |
* | |
* | /---\ |
* ---> | D | ------------
* \---/
*
*
* Proportional-integral-derivative (PID) controller is made from three parts.
*
* Error which is difference between set point and input signal is driven into
* propotional, integral and derivative part. Each calculates its own value which
* is then summed and saturated before given to output.
*
* Integral part has also separate input to reset integrator value to 0.
*
*/
module red_pitaya_pid_block #(
//parameters for gain control (binary points and total bitwidth)
parameter PSR = 12 ,
parameter ISR = 32 ,//official redpitaya: 18
parameter DSR = 10 ,
parameter GAINBITS = 24 ,
parameter DERIVATIVE = 0 , //disables differential gain if 0
//parameters for input pre-filter
parameter FILTERSTAGES = 4 ,
parameter FILTERSHIFTBITS = 5,
parameter FILTERMINBW = 5,
//enable arbitrary output saturation or not
parameter ARBITRARY_SATURATION = 1
)
(
// data
input clk_i , // clock
input rstn_i , // reset - active low
input [ 14-1: 0] dat_i , // input data
output [ 14-1: 0] dat_o , // output data
// communication with PS
input [ 16-1: 0] addr,
input wen,
input ren,
output reg ack,
output reg [ 32-1: 0] rdata,
input [ 32-1: 0] wdata
);
reg [ 14-1: 0] set_sp; // set point
reg [ 16-1: 0] set_ival; // integral value to set
reg ival_write;
reg [ GAINBITS-1: 0] set_kp; // Kp
reg [ GAINBITS-1: 0] set_ki; // Ki
reg [ GAINBITS-1: 0] set_kd; // Kd
reg [ 32-1: 0] set_filter; // filter setting
// limits if arbitrary saturation is enabled
reg signed [ 14-1:0] out_max;
reg signed [ 14-1:0] out_min;
reg normalization_on;
// System bus connection
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
set_sp <= 14'd0;
set_ival <= 14'd0;
set_kp <= {GAINBITS{1'b0}};
set_ki <= {GAINBITS{1'b0}};
set_kd <= {GAINBITS{1'b0}};
set_filter <= 32'd0;
ival_write <= 1'b0;
out_min <= {1'b1,{14-1{1'b0}}};
out_max <= {1'b0,{14-1{1'b1}}};
normalization_on <= 1'b0;
end
else begin
if (normalization_on == 1'b1)
set_kp <= norm_integral;
if (wen) begin
if (addr==16'h100) set_ival <= wdata[16-1:0];
if (addr==16'h104) set_sp <= wdata[14-1:0];
if ((addr==16'h108) && (normalization_on == 1'b0)) set_kp <= wdata[GAINBITS-1:0];
if (addr==16'h10C) set_ki <= wdata[GAINBITS-1:0];
if (addr==16'h110) set_kd <= wdata[GAINBITS-1:0];
if (addr==16'h120) set_filter <= wdata;
if (addr==16'h124) out_min <= wdata;
if (addr==16'h128) out_max <= wdata;
if (addr==16'h130) normalization_on <= wdata[0];
end
if (addr==16'h100 && wen)
ival_write <= 1'b1;
else
ival_write <= 1'b0;
casez (addr)
16'h100 : begin ack <= wen|ren; rdata <= int_shr; end
16'h104 : begin ack <= wen|ren; rdata <= {{32-14{1'b0}},set_sp}; end
16'h108 : begin ack <= wen|ren; rdata <= {{32-GAINBITS{1'b0}},set_kp}; end
16'h10C : begin ack <= wen|ren; rdata <= {{32-GAINBITS{1'b0}},set_ki}; end
16'h110 : begin ack <= wen|ren; rdata <= {{32-GAINBITS{1'b0}},set_kd}; end
16'h120 : begin ack <= wen|ren; rdata <= set_filter; end
16'h124 : begin ack <= wen|ren; rdata <= {{32-14{1'b0}},out_min}; end
16'h128 : begin ack <= wen|ren; rdata <= {{32-14{1'b0}},out_max}; end
16'h130 : begin ack <= wen|ren; rdata <= {{32-31{1'b0}},normalization_on}; end
16'h200 : begin ack <= wen|ren; rdata <= PSR; end
16'h204 : begin ack <= wen|ren; rdata <= ISR; end
16'h208 : begin ack <= wen|ren; rdata <= DSR; end
16'h20C : begin ack <= wen|ren; rdata <= GAINBITS; end
16'h220 : begin ack <= wen|ren; rdata <= FILTERSTAGES; end
16'h224 : begin ack <= wen|ren; rdata <= FILTERSHIFTBITS; end
16'h228 : begin ack <= wen|ren; rdata <= FILTERMINBW; end
default: begin ack <= wen|ren; rdata <= 32'h0; end
endcase
end
end
//-----------------------------
// cascaded set of FILTERSTAGES low- or high-pass filters
wire signed [14-1:0] dat_i_filtered;
red_pitaya_filter_block #(
.STAGES(FILTERSTAGES),
.SHIFTBITS(FILTERSHIFTBITS),
.SIGNALBITS(14),
.MINBW(FILTERMINBW)
)
pidfilter
(
.clk_i(clk_i),
.rstn_i(rstn_i),
.set_filter(set_filter),
.dat_i(dat_i),
.dat_o(dat_i_filtered)
);
//---------------------------------------------------------------------------------
// Set point error calculation - 1 cycle delay
reg [ 16-1: 0] error ;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
error <= 16'h0 ;
end
else begin
//error <= $signed(set_sp) - $signed(dat_i) ;
error <= normalization_on ? ($signed({set_sp, 1'b0}) - $signed(normalized_product)) : ($signed(dat_i_filtered) - $signed(set_sp)) ;
end
end
//---------------------------------------------------------------------------------
// Proportional part - 1 cycle delay
reg [15+GAINBITS-PSR-1: 0] kp_reg ;
wire [15+GAINBITS-1: 0] kp_mult ;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
kp_reg <= {15+GAINBITS-PSR{1'b0}};
end
else begin
kp_reg <= kp_mult[15+GAINBITS-1:PSR] ;
end
end
assign kp_mult = normalization_on ? ($signed(dat_i_offset) * $signed(set_kp)) : ($signed(error) * $signed(set_kp));
reg signed [14-1:0] dat_i_offset;
reg signed [15-1:0] normalized_product;
always @(posedge clk_i) begin
dat_i_offset <= $signed(dat_i) - $signed(set_kd[DSR+14-1:DSR]);
if ({(|kp_reg[15+GAINBITS-PSR-1:15]),kp_reg[15-1]} == 2'b01)
normalized_product <= {1'b0, {15-1{1'b1}}};
else if ({(|kp_reg[15+GAINBITS-PSR-1:15]),kp_reg[15-1]} == 2'b11)
normalized_product <= {{15-1{1'b0}},1'b1};
else
normalized_product <= kp_reg;
end
//---------------------------------------------------------------------------------
// Integrator - 2 cycles delay (but treat similar to proportional since it
// will become negligible at high frequencies where delay is important)
localparam IBW = ISR+16; //integrator bit-width. Over-represent the integral sum to record longterm drifts (overrepresented by 2 bits)
reg [16+GAINBITS-1: 0] ki_mult ;
wire [IBW : 0] int_sum ;
reg [IBW-1: 0] int_reg ;
wire [IBW-ISR-1: 0] int_shr ;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
ki_mult <= {15+GAINBITS{1'b0}};
int_reg <= {IBW{1'b0}};
end
else begin
ki_mult <= $signed(error) * $signed(set_ki) ;
if (ival_write)
int_reg <= { {IBW-16-ISR{set_ival[16-1]}},set_ival[16-1:0],{ISR{1'b0}}};
else if ((normalization_on==1'b1) && ({(|int_sum[IBW:ISR-PSR+GAINBITS]),int_sum[ISR-PSR+GAINBITS-1]} == 2'b01))
// positive saturation with normalization on
int_reg <= {{IBW-1-ISR+PSR-GAINBITS+1{1'b0}},{ISR-PSR+GAINBITS-1{1'b1}}};
else if ((normalization_on==1'b0) && (int_sum[IBW+1-1:IBW+1-2] == 2'b01)) //normal positive saturation
int_reg <= {1'b0,{IBW-1{1'b1}}};
else if ((normalization_on==1'b1) && ({(|int_sum[IBW:ISR-PSR+GAINBITS]),int_sum[ISR-PSR+GAINBITS-1]} == 2'b11)) // number is negative
int_reg <= {{IBW-1-ISR+PSR-1{1'b0}},{ISR-PSR+1{1'b1}}};
//int_reg <= {{GAINBITS-1{1'b0}}, 1'b1, {IBW-GAINBITS-1{1'b0}}};
else if ((normalization_on==1'b0) && (int_sum[IBW+1-1:IBW+1-2] == 2'b10)) //normal negative saturation
int_reg <= {1'b1,{IBW-1{1'b0}}};
else
int_reg <= int_sum[IBW-1:0]; // use sum as it is
end
end
assign int_sum = $signed(ki_mult) + $signed(int_reg) ;
assign int_shr = $signed(int_reg[IBW-1:ISR]) ;
wire [GAINBITS-1: 0] norm_integral;
assign norm_integral = $signed(int_reg[IBW-1:ISR-PSR]);
//---------------------------------------------------------------------------------
// Derivative - 2 cycles delay (but treat as 1 cycle because its not
// functional at the moment
wire [ 39-1: 0] kd_mult ;
reg [39-DSR-1: 0] kd_reg ;
reg [39-DSR-1: 0] kd_reg_r ;
reg [39-DSR : 0] kd_reg_s ;
generate
if (DERIVATIVE == 1) begin
wire [15+GAINBITS-1: 0] kd_mult;
reg [15+GAINBITS-DSR-1: 0] kd_reg;
reg [15+GAINBITS-DSR-1: 0] kd_reg_r;
reg [15+GAINBITS-DSR : 0] kd_reg_s;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
kd_reg <= {15+GAINBITS-DSR{1'b0}};
kd_reg_r <= {15+GAINBITS-DSR{1'b0}};
kd_reg_s <= {15+GAINBITS-DSR+1{1'b0}};
end
else begin
kd_reg <= kd_mult[15+GAINBITS-1:DSR] ;
kd_reg_r <= kd_reg;
kd_reg_s <= $signed(kd_reg) - $signed(kd_reg_r); //this is the end result
end
end
assign kd_mult = $signed(error) * $signed(set_kd) ;
end
else begin
wire [15+GAINBITS-DSR:0] kd_reg_s;
assign kd_reg_s = {15+GAINBITS-DSR+1{1'b0}};
end
endgenerate
//---------------------------------------------------------------------------------
// Sum together - saturate output - 1 cycle delay
localparam MAXBW = 17; //maximum possible bitwidth for pid_sum
wire [ MAXBW-1: 0] pid_sum;
reg signed [ 14-1: 0] pid_out;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
pid_out <= 14'b0;
end
else begin
if ({pid_sum[MAXBW-1],|pid_sum[MAXBW-2:13]} == 2'b01) //positive overflow
pid_out <= 14'h1FFF;
else if ({pid_sum[MAXBW-1],&pid_sum[MAXBW-2:13]} == 2'b10) //negative overflow
pid_out <= 14'h2000;
else
pid_out <= pid_sum[14-1:0];
end
end
assign pid_sum = (normalization_on) ? ($signed(error)): ($signed(kp_reg) + $signed(int_shr) + $signed(kd_reg_s));
generate
if (ARBITRARY_SATURATION == 0)
assign dat_o = pid_out;
else begin
reg signed [ 14-1:0] out_buffer;
always @(posedge clk_i) begin
if (pid_out >= out_max)
out_buffer <= out_max;
else if (pid_out <= out_min)
out_buffer <= out_min;
else
out_buffer <= pid_out;
end
assign dat_o = out_buffer;
end
endgenerate
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ninja3.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ninja3 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/ninja3.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/ninja3.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/ninja3.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja3.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja3.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja3.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja3.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja3_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja3_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4B_4_V
`define SKY130_FD_SC_MS__OR4B_4_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4b_4 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4b_4 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4B_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21A_2_V
`define SKY130_FD_SC_LP__O21A_2_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21a_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21a_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21A_2_V
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: ADDR_UNIT.v
// Version: 1.1 bug fix
// History: 1.0 first release of 30 Mai 2015
// Date: 7 October 2015
//
// Copyright (C) 2015 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// ADDR_UNIT generates data access addresses and controls data cache operation
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL, INDEX, ASIZE, SRC1, SRC2, BWD,
DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1, OP_RMW, PHASE_17,
NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, REG_OUT, BITSEL,
QWATWO );
input BCLK,BRESET;
input READ,WRITE,LDEA;
input NEWACC;
input CLRMSW,POST,FULLACC;
input [1:0] SRC2SEL;
input [3:0] INDEX;
input [1:0] ASIZE;
input [31:0] SRC1,SRC2;
input [1:0] BWD;
input [31:0] DISP;
input [31:0] PC_ARCHI,PC_ICACHE;
input DISP_OK;
input IO_READY;
input [5:0] ACC_STAT; // Feedback from data cache about the running access
input [1:0] MMU_UPDATE;
input [2:0] IC_TEX;
input [1:0] ABO_STAT;
input ADIVAR;
input RWVAL_1; // special access for RDVAL + WRVAL
input OP_RMW;
input PHASE_17;
input NO_TRAP;
input FPU_TRAP;
output READ_OUT,WRITE_OUT,ZTEST,RMW;
output [31:0] VADR;
output [31:0] ADDR;
output [1:0] SIZE;
output [3:0] PACKET;
output ACC_DONE;
output ABORT;
output REG_OUT;
output [2:0] BITSEL;
output reg QWATWO;
reg [31:0] VADR;
reg READ_OUT,write_reg,ZTEST,RMW;
reg [1:0] SIZE;
reg [3:0] PACKET;
reg [2:0] BITSEL;
reg [31:0] source2;
reg [31:0] index_val;
reg [31:0] vadr_reg;
reg [31:0] ea_reg;
reg [31:0] tos_offset;
reg [31:0] icache_adr;
reg [31:0] sign_ext_src1;
reg [31:12] pg_areg;
reg reg_out_i,next_reg;
reg ld_ea_reg;
reg acc_run,acc_ende,acc_step;
reg qwa_flag;
reg no_done;
reg frueh_ok;
reg io_rdy;
reg ABORT;
reg [1:0] tex_feld;
reg [2:0] u_ddt;
reg pg_op;
reg do_wr;
wire acc_ok,acc_err,io_acc;
wire acc_pass;
wire ca_hit;
wire [31:0] reg_adder;
wire [31:0] next_vadr;
wire [31:0] final_addr;
wire [31:0] pg_addr;
wire [1:0] inc_pack;
wire [3:0] index_sel;
wire ld_ea_i;
wire ea_ok;
wire qw_align;
wire init_acc;
wire in_page;
wire all_ok;
wire fa_out;
wire pg_test;
// ++++++++++++++++++++ Decoding ACC_STAT from data cache ++++++++++++++++++++++++++++
// ACC_STAT[5:0] : CA_HIT, IO_ACC, PROT_ERROR , ABO_LEVEL1 , ABORT , ACC_OK
assign ca_hit = ACC_STAT[5];
assign io_acc = ACC_STAT[4];
assign acc_err = ACC_STAT[3] | ACC_STAT[1]; // Abort or Protection Error
assign acc_ok = ACC_STAT[0] & ~pg_op;
assign acc_pass = ACC_STAT[0] & ZTEST;
always @(posedge BCLK) ABORT <= acc_err; // Signal to Steuerung - only a pulse
always @(posedge BCLK) if (acc_err) tex_feld <= ACC_STAT[3] ? 2'b11 : {~ACC_STAT[2],ACC_STAT[2]}; // for MSR
always @(posedge BCLK) if (acc_err) u_ddt <= {RMW,ABO_STAT[1],(WRITE_OUT | ZTEST)};
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(SRC2SEL or CLRMSW or SRC2 or PC_ARCHI or ea_reg)
case (SRC2SEL)
2'b00 : source2 = {(CLRMSW ? 16'h0000 : SRC2[31:16]),SRC2[15:0]}; // base reg, External Addressing with MOD
2'b01 : source2 = PC_ARCHI; // PC relative
2'b10 : source2 = 32'h0; // Absolute Addressing
2'b11 : source2 = ea_reg; // REUSE : 2. TOS
endcase
assign index_sel = POST ? 4'h0 : INDEX; // Alternative application of Index for POST Adder : POP from Stack
always @(BWD or SRC1)
casex (BWD)
2'b00 : sign_ext_src1 = {{24{SRC1[7]}}, SRC1[7:0]}; // Byte
2'b01 : sign_ext_src1 = {{16{SRC1[15]}},SRC1[15:0]}; // Word
default : sign_ext_src1 = SRC1;
endcase
always @(index_sel or sign_ext_src1 or SRC1)
casex (index_sel)
4'b1_0xx : index_val = sign_ext_src1; // für CASE
4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
4'b0_100 : index_val = SRC1;
4'b0_101 : index_val = {SRC1[30:0],1'b0};
4'b0_110 : index_val = {SRC1[29:0],2'b00};
4'b0_111 : index_val = {SRC1[28:0],3'b000};
default : index_val = 32'h0;
endcase
assign reg_adder = source2 + index_val; // SRC2 allows simple MOV with SRC1
assign final_addr = reg_adder + DISP; // That's the final access address
always @(posedge BCLK) if (LDEA && (index_sel[3:2] == 2'b11)) BITSEL <= SRC1[2:0]; // for Bit Opcodes in I_PFAD
always @(INDEX) // SP POP Operation & String Backward
case (INDEX[2:0])
3'b000 : tos_offset = 32'h0000_0001;
3'b001 : tos_offset = 32'h0000_0002;
3'b010 : tos_offset = 32'h0000_0004;
3'b011 : tos_offset = 32'h0000_0008;
3'b100 : tos_offset = 32'hFFFF_FFFF;
3'b101 : tos_offset = 32'hFFFF_FFFE;
3'b110 : tos_offset = 32'hFFFF_FFFC;
3'b111 : tos_offset = 32'hFFFF_FFF8;
endcase
always @(posedge BCLK or negedge BRESET)
if (!BRESET) ld_ea_reg <= 1'b0;
else ld_ea_reg <= (LDEA | ld_ea_reg) & ~DISP_OK;
assign ld_ea_i = (LDEA | ld_ea_reg) & DISP_OK;
assign ea_ok = (READ | WRITE | LDEA | ld_ea_reg) & ~FULLACC & DISP_OK;
always @(posedge BCLK) icache_adr <= PC_ICACHE;
// Memory for the calculated address for reuse and Register for POST modified addresses :
always @(posedge BCLK)
if (ld_ea_i)
begin
casex ({MMU_UPDATE[1],INDEX[0],POST})
3'b10x : ea_reg <= MMU_UPDATE[0] ? vadr_reg : icache_adr; // TEAR
3'b11x : ea_reg <= MMU_UPDATE[0] ?
{24'h0000_00,3'b101, u_ddt, tex_feld} // MSR
: {24'h0000_00,3'b100,IC_TEX[2],ABO_STAT[0],1'b0,IC_TEX[1:0]}; // only READ from ICACHE
3'b0x1 : ea_reg <= source2 + tos_offset ;
3'b0x0 : ea_reg <= final_addr;
endcase
end
assign ADDR = ea_reg; // used for ADDR opcode and TOS Addressing
// This pulse stores all parameters of access
assign init_acc = ((FULLACC ? (NEWACC & acc_ende) : acc_ende) | ~acc_run) & DISP_OK & (READ | WRITE) & ~ABORT & NO_TRAP;
assign fa_out = init_acc | ADIVAR; // special case for LMR IVAR,...
always @(fa_out or acc_ok or final_addr or qw_align or pg_op or pg_areg or vadr_reg or next_vadr)
casex ({fa_out,acc_ok})
2'b1x : VADR = {final_addr[31:3],(final_addr[2] | qw_align),final_addr[1:0]};
2'b00 : VADR = pg_op ? {pg_areg,12'h0} : vadr_reg;
2'b01 : VADR = next_vadr;
endcase
always @(posedge BCLK)
if (init_acc) vadr_reg <= {final_addr[31:3],(final_addr[2] | qw_align),final_addr[1:0]};
else
if (pg_op && ZTEST && acc_err) vadr_reg <= {pg_areg,12'h0}; // for TEAR !
else
if (acc_ok) vadr_reg <= next_vadr;
assign next_vadr = qwa_flag ? {vadr_reg[31:3],3'b000} : ({vadr_reg[31:2],2'b00} + 32'h0000_0004);
// Logic for Page border WRITE Test
assign pg_addr = final_addr + {29'h0,(ASIZE[1] & ASIZE[0]),ASIZE[1],(ASIZE[1] | ASIZE[0])};
always @(posedge BCLK) if (init_acc) pg_areg <= pg_addr[31:12];
assign pg_test = (final_addr[12] != pg_addr[12]) & ~OP_RMW; // At RMW no Test necessary
always @(posedge BCLK or negedge BRESET)
if (!BRESET) pg_op <= 1'b0;
else
pg_op <= init_acc ? (WRITE & ~RWVAL_1 & pg_test) : (pg_op & ~acc_pass & ~acc_err);
always @(posedge BCLK) do_wr <= pg_op & ZTEST & acc_pass; // All ok, Page exists => continue
always @(posedge BCLK or negedge BRESET)
if (!BRESET) READ_OUT <= 1'b0;
else
READ_OUT <= init_acc ? (READ & ~RWVAL_1) : (READ_OUT & ~acc_ende & ~acc_err);
always @(posedge BCLK or negedge BRESET)
if (!BRESET) write_reg <= 1'b0;
else
write_reg <= (init_acc ? (WRITE & ~RWVAL_1 & ~pg_test) : (write_reg & ~acc_ende & ~acc_err & ~FPU_TRAP)) | do_wr;
assign WRITE_OUT = write_reg & ~FPU_TRAP;
// Special case for RDVAL and WRVAL
always @(posedge BCLK or negedge BRESET)
if (!BRESET) ZTEST <= 1'b0;
else
ZTEST <= pg_op ? (~ZTEST | (~acc_pass & ~acc_err)) : (init_acc ? RWVAL_1 : (ZTEST & ~acc_ende & ~acc_err));
always @(posedge BCLK or negedge BRESET)
if (!BRESET) RMW <= 1'b0;
else
RMW <= init_acc ? (OP_RMW & PHASE_17) : (RMW & ~acc_ende & ~acc_err);
// Special case : first MSD access by aligned QWORD READ
assign qw_align = (final_addr[2:0] == 3'b000) & READ & (ASIZE == 2'b11);
always @(posedge BCLK) if (init_acc) qwa_flag <= qw_align;
always @(posedge BCLK or negedge BRESET) // central flag that shows the ADDR_UNIT is busy
if (!BRESET) acc_run <= 1'b0;
else
acc_run <= init_acc | (acc_run & ~acc_ende & ~acc_err & ~FPU_TRAP);
always @(posedge BCLK) if (init_acc) SIZE <= ASIZE;
assign inc_pack = (PACKET[1:0] == 2'b00) ? 2'b10 : {(SIZE[1] ^ SIZE[0]),(SIZE[1] & SIZE[0])};
// Counter for data packets 1 to 3 : special case aligned QWORD : only 2 packets. Additionally start address in bits 1 und 0.
// special coding (00) -> [01] -> (10) , [01] optional by QWORD and (10) shows always the end
always @(posedge BCLK)
if (init_acc) PACKET <= {2'b00,final_addr[1:0]};
else
if (acc_ok) PACKET <= PACKET + {inc_pack,2'b00};
// This signal is the End signal for the ADDR_UNIT internally.
always @(SIZE or PACKET or acc_ok)
casex ({SIZE,PACKET[3],PACKET[1:0]})
5'b00_x_xx : acc_ende = acc_ok; // Byte
5'b01_0_0x : acc_ende = acc_ok; // Word 1 packet
5'b01_0_10 : acc_ende = acc_ok; // 1 packet
5'b01_1_xx : acc_ende = acc_ok; // 2 packets
5'b10_0_00 : acc_ende = acc_ok; // DWord 1 packet
5'b10_1_xx : acc_ende = acc_ok; // 2 packets
5'b11_1_xx : acc_ende = acc_ok; // QWord at least 2 packets
default : acc_ende = 1'b0;
endcase
assign in_page = (vadr_reg[11:3] != 9'h1FF); // Access inside a page ? During WRITE address is increasing : 1. LSD 2. MSD
always @(SIZE or vadr_reg or in_page or PACKET)
casex (SIZE)
2'b01 : frueh_ok = (vadr_reg[3:2] != 2'b11); //Word
2'b10 : frueh_ok = (vadr_reg[3:2] != 2'b11); //DWord
2'b11 : frueh_ok = (PACKET[1:0] == 2'b00) ? (~vadr_reg[3] | ~vadr_reg[2]) : ((PACKET[3:2] == 2'b01) & (vadr_reg[3:2] != 2'b11));
default : frueh_ok = 1'b1; // Byte don't case
endcase
assign all_ok = SIZE[1] ? (PACKET[1:0] == 2'b00) : (PACKET[1:0] != 2'b11); // for DWord : Word
always @(SIZE or READ_OUT or frueh_ok or PACKET or all_ok or io_acc or acc_ok or qwa_flag or io_rdy or ca_hit)
casex ({SIZE,READ_OUT,frueh_ok,PACKET[3],io_acc,all_ok})
7'b00_xxxx_x : acc_step = acc_ok; // Byte, all ok
//
7'b01_xxxx_1 : acc_step = acc_ok; // Word : aligned access , only 1 packet
7'b01_1x1x_0 : acc_step = acc_ok; // READ must wait for all data
7'b01_0x1x_0 : acc_step = acc_ok; // WRITE Adr. ist not perfect and waits for last packet
7'b01_0100_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet
//
7'b10_xxxx_1 : acc_step = acc_ok; // DWord : aligned access , only 1 packet
7'b10_1x1x_0 : acc_step = acc_ok; // READ must wait for all data
7'b10_0x1x_0 : acc_step = acc_ok; // WRITE Adr. ist not perfect and waits for last packet
7'b10_0100_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet
// fast QWord READ : there would be a 2. acc_step if not ~PACK...
7'b11_1xxx_x : acc_step = acc_ok & ( (qwa_flag & ~io_rdy & ca_hit) ? ~PACKET[3] : PACKET[3] );
7'b11_0x1x_x : acc_step = acc_ok;
7'b11_0100_x : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet if not io_acc
default : acc_step = 1'b0;
endcase
// There is a 2. acc_step if packet (10) - this must be suppressed
always @(posedge BCLK or negedge BRESET)
if (!BRESET) no_done <= 1'b0;
else no_done <= (~acc_ende & acc_step) | (no_done & ~(acc_run & acc_ende));
// The final DONE Multiplexer
assign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok;
// Bugfix of 7.October 2015
always @(posedge BCLK) QWATWO <= acc_run & acc_ok & qwa_flag & ~io_rdy & ca_hit & ~PACKET[3] & (SIZE == 2'b11) & READ_OUT & ~no_done;
always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & (io_rdy | ~ca_hit) & acc_ok) | reg_out_i);
always @(posedge BCLK) io_rdy <= IO_READY & (WRITE_OUT | READ_OUT);
always @(posedge BCLK) next_reg <= (acc_step & ~qwa_flag) & (SIZE == 2'b11);
assign REG_OUT = reg_out_i | next_reg;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright 2010-2012 by Michael A. Morris, dba M. A. Morris & Associates
//
// All rights reserved. The source code contained herein is publicly released
// under the terms and conditions of the GNU Lesser Public License. No part of
// this source code may be reproduced or transmitted in any form or by any
// means, electronic or mechanical, including photocopying, recording, or any
// information storage and retrieval system in violation of the license under
// which the source code is released.
//
// The souce code contained herein is free; it may be redistributed and/or
// modified in accordance with the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either version 2.1 of
// the GNU Lesser General Public License, or any later version.
//
// The souce code contained herein is freely released WITHOUT ANY WARRANTY;
// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
// more details.)
//
// A copy of the GNU Lesser General Public License should have been received
// along with the source code contained herein; if not, a copy can be obtained
// by writing to:
//
// Free Software Foundation, Inc.
// 51 Franklin Street, Fifth Floor
// Boston, MA 02110-1301 USA
//
// Further, no use of this source code is permitted in any form or means
// without inclusion of this banner prominently in any derived works.
//
// Michael A. Morris
// Huntsville, AL
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: M. A. Morris & Associates
// Engineer: Michael A. Morris
//
// Create Date: 19:48:02 07/10/2010
// Design Name: Booth Multiplier (1 bit at a time)
// Module Name: Booth_Multiplier_1xA.v
// Project Name: Booth_Multiplier
// Target Devices: Spartan-3AN
// Tool versions: Xilinx ISE 10.1 SP3
//
// Description:
//
// This module implements a parameterized multiplier which uses the Booth
// algorithm for its implementation. The implementation is based on the
// algorithm described in "Computer Organization", Hamacher et al, McGraw-
// Hill Book Company, New York, NY, 1978, ISBN: 0-07-025681-0.
//
// Dependencies:
//
// Revision:
//
// 0.01 10G10 MAM File Created
//
// 1.00 12I02 MAM Changed parameterization from a power of 2 to the
// number of bits to match the other modules in this
// family of Booth multipliers. Made the structure of
// the module match that of the x2 and x4 modules.
//
// 1.10 12I03 MAM Changed the implementation technique of the partial
// product summer to match that of the x4A module. This
// reduces the adder to a single adder with a preceed-
// ing multiplexer that generates the proper operand as
// 0, M w/ no carry in, or ~M w/ carry input.
//
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Booth_Multiplier_1xA #(
parameter N = 16 // Width = N: multiplicand & multiplier
)(
input Rst, // Reset
input Clk, // Clock
input Ld, // Load Registers and Start Multiplier
input [(N - 1):0] M, // Multiplicand
input [(N - 1):0] R, // Multiplier
output reg Valid, // Product Valid
output reg [(2*N - 1):0] P // Product <= M * R
);
///////////////////////////////////////////////////////////////////////////////
//
// Local Parameters
//
///////////////////////////////////////////////////////////////////////////////
//
// Declarations
//
reg [4:0] Cntr; // Operation Counter
reg [1:0] Booth; // Booth Recoding Field
reg Guard; // Shift bit for Booth Recoding
reg [N:0] A; // Multiplicand w/ sign guard bit
reg [N:0] B; // Input Operand to Adder w/ sign guard bit
reg Ci; // Carry input to Adder
reg [N:0] S; // Adder w/ sign guard bit
wire [N:0] Hi; // Upper half of Product w/ sign guard
reg [2*N:0] Prod; // Double length product w/ sign guard bit
///////////////////////////////////////////////////////////////////////////////
//
// Implementation
//
always @(posedge Clk)
begin
if(Rst)
Cntr <= #1 0;
else if(Ld)
Cntr <= #1 N;
else if(|Cntr)
Cntr <= #1 (Cntr - 1);
end
// Multiplicand Register
// includes an additional bit to guard sign bit in the event the
// most negative value is provided as the multiplicand.
always @(posedge Clk)
begin
if(Rst)
A <= #1 0;
else if(Ld)
A <= #1 {M[N - 1], M};
end
// Compute Upper Partial Product: (N + 1) bits in width
always @(*) Booth <= {Prod[0], Guard}; // Booth's Multiplier Recoding field
assign Hi = Prod[2*N:N]; // Upper Half of the Product Register
always @(*)
begin
case(Booth)
2'b01 : {Ci, B} <= {1'b0, A};
2'b10 : {Ci, B} <= {1'b1, ~A};
default : {Ci, B} <= 0;
endcase
end
always @(*) S <= Hi + B + Ci;
// Register Partial products and shift right arithmetically.
// Product register has a sign extension guard bit.
always @(posedge Clk)
begin
if(Rst)
Prod <= #1 0;
else if(Ld)
Prod <= #1 R;
else if(|Cntr) // Arithmetic right shift 1 bit
Prod <= #1 {S[N], S, Prod[(N - 1):1]};
end
always @(posedge Clk)
begin
if(Rst)
Guard <= #1 0;
else if(Ld)
Guard <= #1 0;
else if(|Cntr)
Guard <= #1 Prod[0];
end
// Assign the product less the sign extension guard bit to the output port
always @(posedge Clk)
begin
if(Rst)
P <= #1 0;
else if(Cntr == 1)
P <= #1 {S, Prod[(N - 1):1]};
end
// Count the number of shifts
// This implementation does not use any optimizations to perform multiple
// bit shifts to skip over runs of 1s or 0s.
always @(posedge Clk)
begin
if(Rst)
Valid <= #1 0;
else
Valid <= #1 (Cntr == 1);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__SEDFXBP_PP_BLACKBOX_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sedfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXBP_PP_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Source Synchronous Input Deserializer
// /___/ /\ Filename : ISERDES.v
// \ \ / \ Timestamp : Thu Mar 11 16:44:07 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus.
// 03/18/05 - Changed SIM_TAPDELAY_VALUE to 75 from 78.
// 05/30/06 - CR 232324 -- Added timing checks for SR/REV wrt negedge CLKDIV
// 07/19/06 - CR 234556 fix. Added SIM_DELAY_D, SIM_SETUP_D_CLK and SIM_HOLD_D_CLK
// 10/13/06 - CR 424503 fix. False setup/hold warnings during post ngd simulation
// 10/13/06 - Fixed CR 426606
// 06/06/07 - Added wire declaration for internal signals
// 07/02/07 - CR 441960 -- made some params into localparams
// 04/15/08 - CR 468871 Negative SetupHold fix
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module ISERDES (O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2,
BITSLIP, CE1, CE2, CLK, CLKDIV, D, DLYCE, DLYINC, DLYRST, OCLK, REV, SHIFTIN1, SHIFTIN2, SR);
output O;
output Q1;
output Q2;
output Q3;
output Q4;
output Q5;
output Q6;
output SHIFTOUT1;
output SHIFTOUT2;
input BITSLIP;
input CE1;
input CE2;
input CLK;
input CLKDIV;
input D;
input DLYCE;
input DLYINC;
input DLYRST;
input OCLK;
input REV;
input SHIFTIN1;
input SHIFTIN2;
input SR;
parameter BITSLIP_ENABLE = "FALSE";
parameter DATA_RATE = "DDR";
parameter integer DATA_WIDTH = 4;
parameter [0:0] INIT_Q1 = 1'b0;
parameter [0:0] INIT_Q2 = 1'b0;
parameter [0:0] INIT_Q3 = 1'b0;
parameter [0:0] INIT_Q4 = 1'b0;
parameter INTERFACE_TYPE = "MEMORY";
parameter IOBDELAY = "NONE";
parameter IOBDELAY_TYPE = "DEFAULT";
parameter integer IOBDELAY_VALUE = 0;
parameter integer NUM_CE = 2;
parameter SERDES_MODE = "MASTER";
parameter integer SIM_DELAY_D = 0;
parameter integer SIM_SETUP_D_CLK = 0;
parameter integer SIM_HOLD_D_CLK = 0;
parameter [0:0] SRVAL_Q1 = 1'b0;
parameter [0:0] SRVAL_Q2 = 1'b0;
parameter [0:0] SRVAL_Q3 = 1'b0;
parameter [0:0] SRVAL_Q4 = 1'b0;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
localparam DELAY_D = (IOBDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
integer delay_count, delay_count_int;
integer clk_change_time, data_change_time;
integer return_code = 0;
//-----------------------------------------------------------------
//-------------- Function xsetuphold_chk -------------------------
//-----------------------------------------------------------------
function xsetuphold_chk;
input integer clk_time;
input integer data_time;
begin
xsetuphold_chk = 0;
if(data_time > clk_time)
begin
// CR 424503
// if((data_time - clk_time) <= SIM_HOLD_D_CLK)
if((data_time - clk_time) < SIM_HOLD_D_CLK)
begin
// write_hold_message;
$display ("** Error %m \$hold(CLK %d ps, D %d ps, %d ps \)", clk_time, data_time, SIM_HOLD_D_CLK);
xsetuphold_chk = 2;
end
end
else
begin
// CR 424503
// if((clk_time - data_time) <= SIM_SETUP_D_CLK)
if((clk_time - data_time) < SIM_SETUP_D_CLK)
begin
// write_setup_message;
$display ("** Error %m \$setup(CLK %d ps, D %d ps, %d ps \)", clk_time, data_time, SIM_SETUP_D_CLK);
xsetuphold_chk = 1;
end
end
end
endfunction
tri0 GSR = glbl.GSR;
reg [1:0] sel;
reg [3:0] data_width_int;
reg bts_q1, bts_q2, bts_q3;
reg c23, c45, c67;
reg ce1r, ce2r;
reg dataq1rnk2, dataq2rnk2, dataq3rnk2;
reg dataq3rnk1, dataq4rnk1, dataq5rnk1, dataq6rnk1;
reg dataq4rnk2, dataq5rnk2, dataq6rnk2;
reg ice, memmux, q2pmux;
reg mux, mux1, muxc;
reg notifier;
reg clkdiv_int, clkdivmux;
reg o_out = 0, q1_out = 0, q2_out = 0, q3_out = 0, q4_out = 0, q5_out = 0, q6_out = 0;
reg q1rnk2, q2rnk2, q3rnk2, q4rnk2, q5rnk2, q6rnk2;
reg q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3, q6rnk3;
reg q4rnk1, q5rnk1, q6rnk1, q6prnk1;
reg num_ce_int;
reg qr1, qr2, qhc1, qhc2, qlc1, qlc2;
reg shiftn2_in, shiftn1_in;
reg q1rnk1, q2nrnk1, q1prnk1, q2prnk1, q3rnk1;
reg serdes_mode_int, data_rate_int, bitslip_enable_int;
reg d_delay, o_delay;
wire shiftout1_out, shiftout2_out;
wire [1:0] sel1;
wire [2:0] bsmux;
wire [3:0] selrnk3;
wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3,
delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7,
delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11,
delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15,
delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19,
delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23,
delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27,
delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31,
delay_chain_32, delay_chain_33, delay_chain_34, delay_chain_35,
delay_chain_36, delay_chain_37, delay_chain_38, delay_chain_39,
delay_chain_40, delay_chain_41, delay_chain_42, delay_chain_43,
delay_chain_44, delay_chain_45, delay_chain_46, delay_chain_47,
delay_chain_48, delay_chain_49, delay_chain_50, delay_chain_51,
delay_chain_52, delay_chain_53, delay_chain_54, delay_chain_55,
delay_chain_56, delay_chain_57, delay_chain_58, delay_chain_59,
delay_chain_60, delay_chain_61, delay_chain_62, delay_chain_63;
wire bitslip_in;
wire ce1_in;
wire ce2_in;
wire clk_in;
wire clkdiv_in;
wire d_in;
wire dlyce_in;
wire dlyinc_in;
wire dlyrst_in;
wire gsr_in;
wire oclk_in;
wire rev_in;
wire sr_in;
wire shiftin1_in;
wire shiftin2_in;
buf b_o (O, o_out);
buf b_q1 (Q1, q1_out);
buf b_q2 (Q2, q2_out);
buf b_q3 (Q3, q3_out);
buf b_q4 (Q4, q4_out);
buf b_q5 (Q5, q5_out);
buf b_q6 (Q6, q6_out);
buf b_shiftout1 (SHIFTOUT1, shiftout1_out);
buf b_shiftout2 (SHIFTOUT2, shiftout2_out);
buf b_bitslip (bitslip_in, BITSLIP);
buf b_ce1 (ce1_in, CE1);
buf b_ce2 (ce2_in, CE2);
buf b_clk (clk_in, CLK);
buf b_clkdiv (clkdiv_in, CLKDIV);
buf b_d (d_in, D);
buf b_dlyce (dlyce_in, DLYCE);
buf b_dlyinc (dlyinc_in, DLYINC);
buf b_dlyrst (dlyrst_in, DLYRST);
buf b_gsr (gsr_in, GSR);
buf b_oclk (oclk_in, OCLK);
buf b_rev (rev_in, REV);
buf b_sr (sr_in, SR);
buf b_shiftin1 (shiftin1_in, SHIFTIN1);
buf b_shiftin2 (shiftin2_in, SHIFTIN2);
// workaround for XSIM
wire rev_in_AND_NOT_sr_in = rev_in & !sr_in;
wire NOT_rev_in_AND_sr_in = !rev_in & sr_in;
// WARNING !!!: This model may not work properly if the
// following parameters are changed.
// xilinx_internal_parameter on
parameter integer SIM_TAPDELAY_VALUE = 75;
// Parameter declarations for delays
localparam ffinp = 300;
localparam mxinp1 = 60;
localparam mxinp2 = 120;
// Delay parameters
localparam ffice = 300;
localparam mxice = 60;
// Delay parameter assignment
localparam ffbsc = 300;
localparam mxbsc = 60;
localparam mxinp1_my = 0;
// xilinx_internal_parameter off
initial begin
// --------CR 447760 DRC -- BITSLIP - INTERFACE_TYPE combination ------------------
if((INTERFACE_TYPE == "MEMORY") && (BITSLIP_ENABLE == "TRUE")) begin
$display("Attribute Syntax Error: BITSLIP_ENABLE is currently set to TRUE when INTERFACE_TYPE is set to MEMORY. This is an invalid configuration.");
#1 $finish;
end
else if((INTERFACE_TYPE == "NETWORKING") && (BITSLIP_ENABLE == "FALSE")) begin
$display ("Attribute Syntax Error: BITSLIP_ENABLE is currently set to FALSE when INTERFACE_TYPE is set to NETWORKING. If BITSLIP is not intended to be used, please set BITSLIP_ENABLE to TRUE and tie the BITSLIP port to ground.");
#1 $finish;
end
// ------------------------------------------------------------------------------------
if (IOBDELAY_VALUE < 0 || IOBDELAY_VALUE > 63) begin
$display("Attribute Syntax Error : The attribute IOBDELAY_VALUE on ISERDES instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 63", IOBDELAY_VALUE);
#1 $finish;
end
if (IOBDELAY_TYPE != "DEFAULT" && IOBDELAY_TYPE != "FIXED" && IOBDELAY_TYPE != "VARIABLE") begin
$display("Attribute Syntax Error : The attribute IOBDELAY_TYPE on ISERDES instance %m is set to %s. Legal values for this attribute are DEFAULT, FIXED or VARIABLE", IOBDELAY_TYPE);
#1 $finish;
end
case (SERDES_MODE)
"MASTER" : serdes_mode_int <= 1'b0;
"SLAVE" : serdes_mode_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDES instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
#1 $finish;
end
endcase // case(SERDES_MODE)
case (DATA_RATE)
"SDR" : data_rate_int <= 1'b1;
"DDR" : data_rate_int <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE on ISERDES instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE);
#1 $finish;
end
endcase // case(DATA_RATE)
case (BITSLIP_ENABLE)
"FALSE" : bitslip_enable_int <= 1'b0;
"TRUE" : bitslip_enable_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute BITSLIP_ENABLE on ISERDES instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", BITSLIP_ENABLE);
#1 $finish;
end
endcase // case(BITSLIP_ENABLE)
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0];
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDES instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH);
#1 $finish;
end
endcase // case(DATA_WIDTH)
case (NUM_CE)
1 : num_ce_int <= 1'b0;
2 : num_ce_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute NUM_CE on ISERDES instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE);
#1 $finish;
end
endcase // case(NUM_CE)
end // initial begin
assign sel1 = {serdes_mode_int, data_rate_int};
assign selrnk3 = {1'b1, bitslip_enable_int, 2'b00};
assign bsmux = {bitslip_enable_int, data_rate_int, muxc};
// GSR
always @(gsr_in) begin
if (gsr_in == 1'b1) begin
if (IOBDELAY_TYPE == "DEFAULT")
assign delay_count = 0;
else
assign delay_count = IOBDELAY_VALUE;
assign bts_q3 = 1'b0;
assign bts_q2 = 1'b0;
assign bts_q1 = 1'b0;
assign clkdiv_int = 1'b0;
assign ce1r = 1'b0;
assign ce2r = 1'b0;
assign q1rnk1 = INIT_Q1;
assign q2nrnk1 = INIT_Q2;
assign q1prnk1 = INIT_Q3;
assign q2prnk1 = INIT_Q4;
assign q3rnk1 = 1'b0;
assign q4rnk1 = 1'b0;
assign q5rnk1 = 1'b0;
assign q6rnk1 = 1'b0;
assign q6prnk1 = 1'b0;
assign q6rnk2 = 1'b0;
assign q5rnk2 = 1'b0;
assign q4rnk2 = 1'b0;
assign q3rnk2 = 1'b0;
assign q2rnk2 = 1'b0;
assign q1rnk2 = 1'b0;
assign q6rnk3 = 1'b0;
assign q5rnk3 = 1'b0;
assign q4rnk3 = 1'b0;
assign q3rnk3 = 1'b0;
assign q2rnk3 = 1'b0;
assign q1rnk3 = 1'b0;
end
else if (gsr_in == 1'b0) begin
deassign delay_count;
deassign bts_q3;
deassign bts_q2;
deassign bts_q1;
deassign clkdiv_int;
deassign ce1r;
deassign ce2r;
deassign q1rnk1;
deassign q2nrnk1;
deassign q1prnk1;
deassign q2prnk1;
deassign q3rnk1;
deassign q4rnk1;
deassign q5rnk1;
deassign q6rnk1;
deassign q6prnk1;
deassign q6rnk2;
deassign q5rnk2;
deassign q4rnk2;
deassign q3rnk2;
deassign q2rnk2;
deassign q1rnk2;
deassign q6rnk3;
deassign q5rnk3;
deassign q4rnk3;
deassign q3rnk3;
deassign q2rnk3;
deassign q1rnk3;
end // if (gsr_in == 1'b0)
end // always @ (gsr_in)
// IDELAY
always @(posedge clkdiv_in) begin
if (IOBDELAY_TYPE == "VARIABLE") begin
if (dlyrst_in == 1'b1) begin
delay_count = IOBDELAY_VALUE;
end
else if (dlyrst_in == 1'b0 && dlyce_in == 1'b1) begin
if (dlyinc_in == 1'b1) begin
if (delay_count < 63)
delay_count = delay_count + 1;
else if (delay_count == 63)
delay_count = 0;
end
else if (dlyinc_in == 1'b0) begin
if (delay_count > 0)
delay_count = delay_count - 1;
else if (delay_count == 0)
delay_count = 63;
end
end
end // if (IOBDELAY_TYPE == "VARIABLE")
end // always @ (posedge clkdiv_in)
// delay chain
assign #DELAY_D delay_chain_0 = d_in;
assign #SIM_TAPDELAY_VALUE delay_chain_1 = delay_chain_0;
assign #SIM_TAPDELAY_VALUE delay_chain_2 = delay_chain_1;
assign #SIM_TAPDELAY_VALUE delay_chain_3 = delay_chain_2;
assign #SIM_TAPDELAY_VALUE delay_chain_4 = delay_chain_3;
assign #SIM_TAPDELAY_VALUE delay_chain_5 = delay_chain_4;
assign #SIM_TAPDELAY_VALUE delay_chain_6 = delay_chain_5;
assign #SIM_TAPDELAY_VALUE delay_chain_7 = delay_chain_6;
assign #SIM_TAPDELAY_VALUE delay_chain_8 = delay_chain_7;
assign #SIM_TAPDELAY_VALUE delay_chain_9 = delay_chain_8;
assign #SIM_TAPDELAY_VALUE delay_chain_10 = delay_chain_9;
assign #SIM_TAPDELAY_VALUE delay_chain_11 = delay_chain_10;
assign #SIM_TAPDELAY_VALUE delay_chain_12 = delay_chain_11;
assign #SIM_TAPDELAY_VALUE delay_chain_13 = delay_chain_12;
assign #SIM_TAPDELAY_VALUE delay_chain_14 = delay_chain_13;
assign #SIM_TAPDELAY_VALUE delay_chain_15 = delay_chain_14;
assign #SIM_TAPDELAY_VALUE delay_chain_16 = delay_chain_15;
assign #SIM_TAPDELAY_VALUE delay_chain_17 = delay_chain_16;
assign #SIM_TAPDELAY_VALUE delay_chain_18 = delay_chain_17;
assign #SIM_TAPDELAY_VALUE delay_chain_19 = delay_chain_18;
assign #SIM_TAPDELAY_VALUE delay_chain_20 = delay_chain_19;
assign #SIM_TAPDELAY_VALUE delay_chain_21 = delay_chain_20;
assign #SIM_TAPDELAY_VALUE delay_chain_22 = delay_chain_21;
assign #SIM_TAPDELAY_VALUE delay_chain_23 = delay_chain_22;
assign #SIM_TAPDELAY_VALUE delay_chain_24 = delay_chain_23;
assign #SIM_TAPDELAY_VALUE delay_chain_25 = delay_chain_24;
assign #SIM_TAPDELAY_VALUE delay_chain_26 = delay_chain_25;
assign #SIM_TAPDELAY_VALUE delay_chain_27 = delay_chain_26;
assign #SIM_TAPDELAY_VALUE delay_chain_28 = delay_chain_27;
assign #SIM_TAPDELAY_VALUE delay_chain_29 = delay_chain_28;
assign #SIM_TAPDELAY_VALUE delay_chain_30 = delay_chain_29;
assign #SIM_TAPDELAY_VALUE delay_chain_31 = delay_chain_30;
assign #SIM_TAPDELAY_VALUE delay_chain_32 = delay_chain_31;
assign #SIM_TAPDELAY_VALUE delay_chain_33 = delay_chain_32;
assign #SIM_TAPDELAY_VALUE delay_chain_34 = delay_chain_33;
assign #SIM_TAPDELAY_VALUE delay_chain_35 = delay_chain_34;
assign #SIM_TAPDELAY_VALUE delay_chain_36 = delay_chain_35;
assign #SIM_TAPDELAY_VALUE delay_chain_37 = delay_chain_36;
assign #SIM_TAPDELAY_VALUE delay_chain_38 = delay_chain_37;
assign #SIM_TAPDELAY_VALUE delay_chain_39 = delay_chain_38;
assign #SIM_TAPDELAY_VALUE delay_chain_40 = delay_chain_39;
assign #SIM_TAPDELAY_VALUE delay_chain_41 = delay_chain_40;
assign #SIM_TAPDELAY_VALUE delay_chain_42 = delay_chain_41;
assign #SIM_TAPDELAY_VALUE delay_chain_43 = delay_chain_42;
assign #SIM_TAPDELAY_VALUE delay_chain_44 = delay_chain_43;
assign #SIM_TAPDELAY_VALUE delay_chain_45 = delay_chain_44;
assign #SIM_TAPDELAY_VALUE delay_chain_46 = delay_chain_45;
assign #SIM_TAPDELAY_VALUE delay_chain_47 = delay_chain_46;
assign #SIM_TAPDELAY_VALUE delay_chain_48 = delay_chain_47;
assign #SIM_TAPDELAY_VALUE delay_chain_49 = delay_chain_48;
assign #SIM_TAPDELAY_VALUE delay_chain_50 = delay_chain_49;
assign #SIM_TAPDELAY_VALUE delay_chain_51 = delay_chain_50;
assign #SIM_TAPDELAY_VALUE delay_chain_52 = delay_chain_51;
assign #SIM_TAPDELAY_VALUE delay_chain_53 = delay_chain_52;
assign #SIM_TAPDELAY_VALUE delay_chain_54 = delay_chain_53;
assign #SIM_TAPDELAY_VALUE delay_chain_55 = delay_chain_54;
assign #SIM_TAPDELAY_VALUE delay_chain_56 = delay_chain_55;
assign #SIM_TAPDELAY_VALUE delay_chain_57 = delay_chain_56;
assign #SIM_TAPDELAY_VALUE delay_chain_58 = delay_chain_57;
assign #SIM_TAPDELAY_VALUE delay_chain_59 = delay_chain_58;
assign #SIM_TAPDELAY_VALUE delay_chain_60 = delay_chain_59;
assign #SIM_TAPDELAY_VALUE delay_chain_61 = delay_chain_60;
assign #SIM_TAPDELAY_VALUE delay_chain_62 = delay_chain_61;
assign #SIM_TAPDELAY_VALUE delay_chain_63 = delay_chain_62;
// assign delay
always @(delay_count_int) begin
case (delay_count_int)
0: assign d_delay = delay_chain_0;
1: assign d_delay = delay_chain_1;
2: assign d_delay = delay_chain_2;
3: assign d_delay = delay_chain_3;
4: assign d_delay = delay_chain_4;
5: assign d_delay = delay_chain_5;
6: assign d_delay = delay_chain_6;
7: assign d_delay = delay_chain_7;
8: assign d_delay = delay_chain_8;
9: assign d_delay = delay_chain_9;
10: assign d_delay = delay_chain_10;
11: assign d_delay = delay_chain_11;
12: assign d_delay = delay_chain_12;
13: assign d_delay = delay_chain_13;
14: assign d_delay = delay_chain_14;
15: assign d_delay = delay_chain_15;
16: assign d_delay = delay_chain_16;
17: assign d_delay = delay_chain_17;
18: assign d_delay = delay_chain_18;
19: assign d_delay = delay_chain_19;
20: assign d_delay = delay_chain_20;
21: assign d_delay = delay_chain_21;
22: assign d_delay = delay_chain_22;
23: assign d_delay = delay_chain_23;
24: assign d_delay = delay_chain_24;
25: assign d_delay = delay_chain_25;
26: assign d_delay = delay_chain_26;
27: assign d_delay = delay_chain_27;
28: assign d_delay = delay_chain_28;
29: assign d_delay = delay_chain_29;
30: assign d_delay = delay_chain_30;
31: assign d_delay = delay_chain_31;
32: assign d_delay = delay_chain_32;
33: assign d_delay = delay_chain_33;
34: assign d_delay = delay_chain_34;
35: assign d_delay = delay_chain_35;
36: assign d_delay = delay_chain_36;
37: assign d_delay = delay_chain_37;
38: assign d_delay = delay_chain_38;
39: assign d_delay = delay_chain_39;
40: assign d_delay = delay_chain_40;
41: assign d_delay = delay_chain_41;
42: assign d_delay = delay_chain_42;
43: assign d_delay = delay_chain_43;
44: assign d_delay = delay_chain_44;
45: assign d_delay = delay_chain_45;
46: assign d_delay = delay_chain_46;
47: assign d_delay = delay_chain_47;
48: assign d_delay = delay_chain_48;
49: assign d_delay = delay_chain_49;
50: assign d_delay = delay_chain_50;
51: assign d_delay = delay_chain_51;
52: assign d_delay = delay_chain_52;
53: assign d_delay = delay_chain_53;
54: assign d_delay = delay_chain_54;
55: assign d_delay = delay_chain_55;
56: assign d_delay = delay_chain_56;
57: assign d_delay = delay_chain_57;
58: assign d_delay = delay_chain_58;
59: assign d_delay = delay_chain_59;
60: assign d_delay = delay_chain_60;
61: assign d_delay = delay_chain_61;
62: assign d_delay = delay_chain_62;
63: assign d_delay = delay_chain_63;
default:
assign d_delay = delay_chain_0;
endcase
end // always @ (delay_count_int)
// to workaround the glitches generated by mux of assign delay above
always @(delay_count)
delay_count_int <= #0 delay_count;
// Mux to O and o_delay
always @(d_in or d_delay) begin
case (IOBDELAY)
"NONE" : begin
o_delay <= d_in;
o_out <= d_in;
end
"IBUF" : begin
o_delay <= d_in;
o_out <= d_delay;
end
"IFD" : begin
o_delay <= d_delay;
o_out <= d_in;
end
"BOTH" : begin
o_delay <= d_delay;
o_out <= d_delay;
end
default : begin
$display("Attribute Syntax Error : The attribute IOBDELAY on ISERDES instance %m is set to %s. Legal values for this attribute are NONE, IBUF, IFD or BOTH", IOBDELAY);
$finish;
end
endcase // case(IOBDELAY)
end // always @ (d_in or d_delay)
// 1st rank of registers
// Asynchronous Operation
always @(posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
// 1st flop in rank 1 that is full featured
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q1 == 1'b1))
q1rnk1 <= # ffinp SRVAL_Q1;
else if (rev_in == 1'b1)
q1rnk1 <= # ffinp !SRVAL_Q1;
else if (ice == 1'b1)
q1rnk1 <= # ffinp o_delay;
end // always @ (posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
always @(posedge clk_in or posedge sr_in) begin
// rest of flops which are not full featured and don't have clock options
if (sr_in == 1'b1) begin
q5rnk1 <= # ffinp 1'b0;
q6rnk1 <= # ffinp 1'b0;
q6prnk1 <= # ffinp 1'b0;
end
else begin
q5rnk1 <= # ffinp dataq5rnk1;
q6rnk1 <= # ffinp dataq6rnk1;
q6prnk1 <= # ffinp q6rnk1;
end
end // always @ (posedge clk_in or sr_in)
// 2nd flop in rank 1
// Asynchronous Operation
always @(negedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q2 == 1'b1))
q2nrnk1 <= # ffinp SRVAL_Q2;
else if (rev_in == 1'b1)
q2nrnk1 <= # ffinp !SRVAL_Q2;
else if (ice == 1'b1)
q2nrnk1 <= # ffinp o_delay;
end // always @ (negedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 4th flop in rank 1 operating on the posedge for networking
// Asynchronous Operation
always @(posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q4 == 1'b1))
q2prnk1 <= # ffinp SRVAL_Q4;
else if (rev_in == 1'b1)
q2prnk1 <= # ffinp !SRVAL_Q4;
else if (ice == 1'b1)
q2prnk1 <= # ffinp q2nrnk1;
end // always @ (posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 3rd flop in 2nd rank which is full featured and has
// a choice of being clocked by oclk or clk
// Asynchronous Operation
always @(posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q3 == 1'b1))
q1prnk1 <= # ffinp SRVAL_Q3;
else if (rev_in == 1'b1)
q1prnk1 <= # ffinp !SRVAL_Q3;
else if (ice == 1'b1)
q1prnk1 <= # ffinp q1rnk1;
end // always @ (posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// 5th and 6th flops in rank 1 which are not full featured but can be clocked
// by either clk or oclk
always @(posedge memmux or posedge sr_in) begin
if (sr_in == 1'b1) begin
q3rnk1 <= # ffinp 1'b0;
q4rnk1 <= # ffinp 1'b0;
end
else begin
q3rnk1 <= # ffinp dataq3rnk1;
q4rnk1 <= # ffinp dataq4rnk1;
end
end // always @ (posedge memmux or posedge sr_in)
//////////////////////////////////////////
// Mux elements for the 1st rank
////////////////////////////////////////
// Optional inverter for q2p (4th flop in rank1)
always @ (memmux) begin
case (INTERFACE_TYPE)
"MEMORY" : q2pmux <= # mxinp1 !memmux;
"NETWORKING" : q2pmux <= # mxinp1 memmux;
default: q2pmux <= # mxinp1 !memmux;
endcase
end // always @ (memmux)
// 4 clock muxs in first rank
always @(clk_in or oclk_in) begin
case (INTERFACE_TYPE)
"MEMORY" : memmux <= # mxinp1 oclk_in;
"NETWORKING" : memmux <= # mxinp1 clk_in;
default : begin
$display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDES instance %m is set to %s. Legal values for this attribute are MEMORY or NETWORKING", INTERFACE_TYPE);
$finish;
end
endcase // case(INTERFACE_TYPE)
end // always @(clk_in or oclk_in)
// data input mux for q3, q4, q5 and q6
always @(sel1 or q1prnk1 or shiftin1_in or shiftin2_in) begin
case (sel1)
2'b00 : dataq3rnk1 <= # mxinp1 q1prnk1;
2'b01 : dataq3rnk1 <= # mxinp1 q1prnk1;
2'b10 : dataq3rnk1 <= # mxinp1 shiftin2_in;
2'b11 : dataq3rnk1 <= # mxinp1 shiftin1_in;
default : dataq3rnk1 <= # mxinp1 q1prnk1;
endcase // case(sel1)
end // always @(sel1 or q1prnk1 or SHIFTIN1 or SHIFTIN2)
always @(sel1 or q2prnk1 or q3rnk1 or shiftin1_in) begin
case (sel1)
2'b00 : dataq4rnk1 <= # mxinp1 q2prnk1;
2'b01 : dataq4rnk1 <= # mxinp1 q3rnk1;
2'b10 : dataq4rnk1 <= # mxinp1 shiftin1_in;
2'b11 : dataq4rnk1 <= # mxinp1 q3rnk1;
default : dataq4rnk1 <= # mxinp1 q2prnk1;
endcase // case(sel1)
end // always @(sel1 or q2prnk1 or q3rnk1 or SHIFTIN1)
always @(data_rate_int or q3rnk1 or q4rnk1) begin
case (data_rate_int)
1'b0 : dataq5rnk1 <= # mxinp1 q3rnk1;
1'b1 : dataq5rnk1 <= # mxinp1 q4rnk1;
default : dataq5rnk1 <= # mxinp1 q4rnk1;
endcase // case(DATA_RATE)
end
always @(data_rate_int or q4rnk1 or q5rnk1) begin
case (data_rate_int)
1'b0 : dataq6rnk1 <= # mxinp1 q4rnk1;
1'b1 : dataq6rnk1 <= # mxinp1 q5rnk1;
default : dataq6rnk1 <= # mxinp1 q5rnk1;
endcase // case(DATA_RATE)
end
// 2nd rank of registers
// clkdivmux to pass clkdiv_int or CLKDIV to rank 2
always @(bitslip_enable_int or clkdiv_int or clkdiv_in) begin
case (bitslip_enable_int)
1'b0 : clkdivmux <= # mxinp1 clkdiv_in;
1'b1 : clkdivmux <= # mxinp1 clkdiv_int;
default : clkdivmux <= # mxinp1 clkdiv_in;
endcase // case(BITSLIP_ENABLE)
end // always @(clkdiv_int or clkdiv_in)
// Asynchronous Operation
always @(posedge clkdivmux or posedge sr_in) begin
if (sr_in == 1'b1) begin
q1rnk2 <= # ffinp 1'b0;
q2rnk2 <= # ffinp 1'b0;
q3rnk2 <= # ffinp 1'b0;
q4rnk2 <= # ffinp 1'b0;
q5rnk2 <= # ffinp 1'b0;
q6rnk2 <= # ffinp 1'b0;
end
else begin
q1rnk2 <= # ffinp dataq1rnk2;
q2rnk2 <= # ffinp dataq2rnk2;
q3rnk2 <= # ffinp dataq3rnk2;
q4rnk2 <= # ffinp dataq4rnk2;
q5rnk2 <= # ffinp dataq5rnk2;
q6rnk2 <= # ffinp dataq6rnk2;
end
end // always @ (posedge clkdivmux or sr_in)
// Data mux for 2nd rank of flops
// Delay for mux set to 120
always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1) begin
casex (bsmux)
3'b00X : dataq1rnk2 <= # mxinp2 q2prnk1;
3'b100 : dataq1rnk2 <= # mxinp2 q2prnk1;
3'b101 : dataq1rnk2 <= # mxinp2 q1prnk1;
3'bX1X : dataq1rnk2 <= # mxinp2 q1rnk1;
default : dataq1rnk2 <= # mxinp2 q2prnk1;
endcase // casex(bsmux)
end // always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1)
always @(bsmux or q1prnk1 or q4rnk1) begin
casex (bsmux)
3'b00X : dataq2rnk2 <= # mxinp2 q1prnk1;
3'b100 : dataq2rnk2 <= # mxinp2 q1prnk1;
3'b101 : dataq2rnk2 <= # mxinp2 q4rnk1;
3'bX1X : dataq2rnk2 <= # mxinp2 q1prnk1;
default : dataq2rnk2 <= # mxinp2 q1prnk1;
endcase // casex(bsmux)
end // always @(bsmux or q1prnk1 or q4rnk1)
always @(bsmux or q3rnk1 or q4rnk1) begin
casex (bsmux)
3'b00X : dataq3rnk2 <= # mxinp2 q4rnk1;
3'b100 : dataq3rnk2 <= # mxinp2 q4rnk1;
3'b101 : dataq3rnk2 <= # mxinp2 q3rnk1;
3'bX1X : dataq3rnk2 <= # mxinp2 q3rnk1;
default : dataq3rnk2 <= # mxinp2 q4rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q3rnk1 or q4rnk1)
always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1) begin
casex (bsmux)
3'b00X : dataq4rnk2 <= # mxinp2 q3rnk1;
3'b100 : dataq4rnk2 <= # mxinp2 q3rnk1;
3'b101 : dataq4rnk2 <= # mxinp2 q6rnk1;
3'bX1X : dataq4rnk2 <= # mxinp2 q4rnk1;
default : dataq4rnk2 <= # mxinp2 q3rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1)
always @(bsmux or q5rnk1 or q6rnk1) begin
casex (bsmux)
3'b00X : dataq5rnk2 <= # mxinp2 q6rnk1;
3'b100 : dataq5rnk2 <= # mxinp2 q6rnk1;
3'b101 : dataq5rnk2 <= # mxinp2 q5rnk1;
3'bX1X : dataq5rnk2 <= # mxinp2 q5rnk1;
default : dataq5rnk2 <= # mxinp2 q6rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q5rnk1 or q6rnk1)
always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1) begin
casex (bsmux)
3'b00X : dataq6rnk2 <= # mxinp2 q5rnk1;
3'b100 : dataq6rnk2 <= # mxinp2 q5rnk1;
3'b101 : dataq6rnk2 <= # mxinp2 q6prnk1;
3'bX1X : dataq6rnk2 <= # mxinp2 q6rnk1;
default : dataq6rnk2 <= # mxinp2 q5rnk1;
endcase // casex(bsmux)
end // always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1)
// 3rd rank of registers
// Asynchronous Operation
always @(posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
q1rnk3 <= # ffinp 1'b0;
q2rnk3 <= # ffinp 1'b0;
q3rnk3 <= # ffinp 1'b0;
q4rnk3 <= # ffinp 1'b0;
q5rnk3 <= # ffinp 1'b0;
q6rnk3 <= # ffinp 1'b0;
end
else begin
q1rnk3 <= # ffinp q1rnk2;
q2rnk3 <= # ffinp q2rnk2;
q3rnk3 <= # ffinp q3rnk2;
q4rnk3 <= # ffinp q4rnk2;
q5rnk3 <= # ffinp q5rnk2;
q6rnk3 <= # ffinp q6rnk2;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Outputs
assign shiftout2_out = q5rnk1;
assign shiftout1_out = q6rnk1;
always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) begin
casex (selrnk3)
4'b0X00 : q1_out <= # mxinp1_my q1prnk1;
4'b0X01 : q1_out <= # mxinp1_my q1rnk1;
4'b0X10 : q1_out <= # mxinp1_my q1rnk1;
4'b10XX : q1_out <= # mxinp1_my q1rnk2;
4'b11XX : q1_out <= # mxinp1_my q1rnk3;
default : q1_out <= # mxinp1_my q1rnk2;
endcase // casex(selrnk3)
end // always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3)
always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) begin
casex (selrnk3)
4'b0X00 : q2_out <= # mxinp1_my q2prnk1;
4'b0X01 : q2_out <= # mxinp1_my q2prnk1;
4'b0X10 : q2_out <= # mxinp1_my q2nrnk1;
4'b10XX : q2_out <= # mxinp1_my q2rnk2;
4'b11XX : q2_out <= # mxinp1_my q2rnk3;
default : q2_out <= # mxinp1_my q2rnk2;
endcase // casex(selrnk3)
end // always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3)
always @(bitslip_enable_int or q3rnk2 or q3rnk3) begin
case (bitslip_enable_int)
1'b0 : q3_out <= # mxinp1_my q3rnk2;
1'b1 : q3_out <= # mxinp1_my q3rnk3;
endcase // case(BITSLIP_ENABLE)
end // always @ (q3rnk2 or q3rnk3)
always @(bitslip_enable_int or q4rnk2 or q4rnk3) begin
casex (bitslip_enable_int)
1'b0 : q4_out <= # mxinp1_my q4rnk2;
1'b1 : q4_out <= # mxinp1_my q4rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q4rnk2 or q4rnk3)
always @(bitslip_enable_int or q5rnk2 or q5rnk3) begin
casex (bitslip_enable_int)
1'b0 : q5_out <= # mxinp1_my q5rnk2;
1'b1 : q5_out <= # mxinp1_my q5rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q5rnk2 or q5rnk3)
always @(bitslip_enable_int or q6rnk2 or q6rnk3) begin
casex (bitslip_enable_int)
1'b0 : q6_out <= # mxinp1_my q6rnk2;
1'b1 : q6_out <= # mxinp1_my q6rnk3;
endcase // casex(BITSLIP_ENABLE)
end // always @ (q6rnk2 or q6rnk3)
// Set value of counter in bitslip controller
always @(data_rate_int or data_width_int) begin
casex ({data_rate_int, data_width_int})
5'b00100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b00110 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b01000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b01010 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10010 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10011 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b10101 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10110 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end
5'b10111 : begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end
5'b11000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end
default : begin
$display("DATA_WIDTH %d and DATA_RATE %s at %t is an illegal value", DATA_WIDTH, DATA_RATE, $time);
$finish;
end
endcase
end // always @ (data_rate_int or data_width_int)
///////////////////////////////////////////
// Bit slip controler
///////////////////////////////////////////
// Divide by 2 - 8 counter
// Asynchronous Operation
always @ (posedge qr2 or negedge clk_in) begin
if (qr2 == 1'b1) begin
clkdiv_int <= # ffbsc 1'b0;
bts_q1 <= # ffbsc 1'b0;
bts_q2 <= # ffbsc 1'b0;
bts_q3 <= # ffbsc 1'b0;
end
else if (qhc1 == 1'b0) begin
bts_q3 <= # ffbsc bts_q2;
bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1);
bts_q1 <= # ffbsc clkdiv_int;
clkdiv_int <= # ffbsc mux;
end
end // always @ (posedge qr2 or negedge clk_in)
// Synchronous Operation
always @ (negedge clk_in) begin
if (qr2 == 1'b1) begin
clkdiv_int <= # ffbsc 1'b0;
bts_q1 <= # ffbsc 1'b0;
bts_q2 <= # ffbsc 1'b0;
bts_q3 <= # ffbsc 1'b0;
end
else if (qhc1 == 1'b1) begin
clkdiv_int <= # ffbsc clkdiv_int;
bts_q1 <= # ffbsc bts_q1;
bts_q2 <= # ffbsc bts_q2;
bts_q3 <= # ffbsc bts_q3;
end
else begin
bts_q3 <= # ffbsc bts_q2;
bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1);
bts_q1 <= # ffbsc clkdiv_int;
clkdiv_int <= # ffbsc mux;
end
end // always @ (negedge clk_in)
// 4:1 selector mux and divider selections
always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3) begin
case (sel)
2'b00 : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1));
2'b01 : mux <= # mxbsc !(bts_q1 | (c45 & bts_q2));
2'b10 : mux <= # mxbsc !(bts_q2 | (c67 & bts_q3));
2'b11 : mux <= # mxbsc !bts_q3;
default : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1));
endcase
end // always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3)
// Bitslip control logic
// Low speed control flop
// Asynchronous Operation
always @ (posedge qr1 or posedge clkdiv_in) begin
if (qr1 == 1'b1) begin
qlc1 <= # ffbsc 1'b0;
qlc2 <= # ffbsc 1'b0;
end
else if (bitslip_in == 1'b0) begin
qlc1 <= # ffbsc qlc1;
qlc2 <= # ffbsc 1'b0;
end
else begin
qlc1 <= # ffbsc !qlc1;
qlc2 <= # ffbsc (bitslip_in & mux1);
end
end // always @ (posedge qr1 or posedge clkdiv_in)
// Mux to select between sdr "1" and ddr "0"
always @ (data_rate_int or qlc1) begin
case (data_rate_int)
1'b0 : mux1 <= # mxbsc qlc1;
1'b1 : mux1 <= # mxbsc 1'b1;
endcase
end
// High speed control flop
// Asynchronous Operation
always @ (posedge qr2 or negedge clk_in) begin
if (qr2 == 1'b1) begin
qhc1 <= # ffbsc 1'b0;
qhc2 <= # ffbsc 1'b0;
end
else begin
qhc1 <= # ffbsc (qlc2 & !qhc2);
qhc2 <= # ffbsc qlc2;
end
end // always @ (posedge qr2 or negedge clk_in)
// Mux that drives control line of mux in front
// of 2nd rank of flops
always @ (data_rate_int or mux1) begin
case (data_rate_int)
1'b0 : muxc <= # mxbsc mux1;
1'b1 : muxc <= # mxbsc 1'b0;
endcase
end
// Asynchronous set flops
// Low speed reset flop
// Asynchronous Operation
always @ (posedge sr_in or posedge clkdiv_in) begin
if (sr_in == 1'b1)
qr1 <= # ffbsc 1'b1;
else
qr1 <= # ffbsc 1'b0;
end // always @ (posedge sr_in or posedge clkdiv_in)
// High speed reset flop
// Asynchronous Operation
always @ (posedge sr_in or negedge clk_in) begin
if (sr_in == 1'b1)
qr2 <= # ffbsc 1'b1;
else
qr2 <= # ffbsc qr1;
end // always @ (posedge sr_in or negedge clk_in)
/////////////////////////////////////////////
// ICE
///////////////////////////////////////////
// Asynchronous Operation
always @ (posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
ce1r <= # ffice 1'b0;
ce2r <= # ffice 1'b0;
end
else begin
ce1r <= # ffice ce1_in;
ce2r <= # ffice ce2_in;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Output mux ice
always @ (num_ce_int or clkdiv_in or ce1_in or ce1r or ce2r) begin
case ({num_ce_int, clkdiv_in})
2'b00 : ice <= # mxice ce1_in;
2'b01 : ice <= # mxice ce1_in;
// 426606
2'b10 : ice <= # mxice ce2r;
2'b11 : ice <= # mxice ce1r;
default : ice <= # mxice ce1_in;
endcase
end
//*** Timing Checks Start here
//-------------------------------------------------------------------
//
//-------------------------------------------------------------------
always @(posedge CLK) begin
clk_change_time = $time;
return_code = xsetuphold_chk(clk_change_time, data_change_time);
end
always @(d_delay) begin
data_change_time = $time;
return_code = xsetuphold_chk(clk_change_time, data_change_time);
end
`ifndef XIL_TIMING
assign bitslip_in = BITSLIP;
assign clk_in = CLK;
assign ce1_in = CE1;
assign ce2_in = CE2;
assign clkdiv_in = CLKDIV;
assign d_in = D;
assign dlyinc_in = DLYINC;
assign dlyce_in = DLYCE;
assign dlyrst_in = DLYRST;
`endif
specify
(CLKDIV => Q1) = (100:100:100, 100:100:100);
(CLKDIV => Q2) = (100:100:100, 100:100:100);
(CLKDIV => Q3) = (100:100:100, 100:100:100);
(CLKDIV => Q4) = (100:100:100, 100:100:100);
(CLKDIV => Q5) = (100:100:100, 100:100:100);
(CLKDIV => Q6) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
(D => O) = (0:0:0, 0:0:0);
(SR => Q1) = (0:0:0, 0:0:0);
(SR => Q2) = (0:0:0, 0:0:0);
(SR => Q3) = (0:0:0, 0:0:0);
(SR => Q4) = (0:0:0, 0:0:0);
(SR => Q5) = (0:0:0, 0:0:0);
(SR => Q6) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in);
$setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in);
$setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in);
$setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier, , , clk_in, d_in);
$setuphold (posedge CLK, posedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in);
$setuphold (posedge CLK, negedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in);
$setuphold (negedge CLK, posedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in);
$setuphold (negedge CLK, negedge CE1, 0:0:0, 0:0:0, notifier, , , clk_in, ce1_in);
$setuphold (posedge CLKDIV, posedge CE1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce1_in);
$setuphold (posedge CLKDIV, negedge CE1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce1_in);
$setuphold (posedge CLKDIV, posedge CE2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce2_in);
$setuphold (posedge CLKDIV, negedge CE2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, ce2_in);
$setuphold (posedge CLKDIV, posedge BITSLIP, 0:0:0, 0:0:0, notifier, , , clkdiv_in, bitslip_in);
$setuphold (posedge CLKDIV, negedge BITSLIP, 0:0:0, 0:0:0, notifier, , , clkdiv_in, bitslip_in);
$setuphold (posedge CLKDIV, posedge DLYINC, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyinc_in);
$setuphold (posedge CLKDIV, negedge DLYINC, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyinc_in);
$setuphold (posedge CLKDIV, posedge DLYCE, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyce_in);
$setuphold (posedge CLKDIV, negedge DLYCE, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyce_in);
$setuphold (posedge CLKDIV, posedge DLYRST, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyrst_in);
$setuphold (posedge CLKDIV, negedge DLYRST, 0:0:0, 0:0:0, notifier, , , clkdiv_in, dlyrst_in);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLKDIV, 0:0:0, notifier);
$period (posedge OCLK, 0:0:0, notifier);
$recrem (negedge SR, posedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, posedge CLKDIV, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, posedge OCLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge REV, posedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge REV, posedge OCLK, 0:0:0, 0:0:0, notifier);
// CR 232324
$setuphold (posedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier);
$setuphold (negedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier);
$setuphold (negedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier);
$setuphold (negedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier);
$setuphold (negedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (posedge CLKDIV, 0:0:0, 0, notifier);
$width (posedge OCLK, 0:0:0, 0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (negedge CLKDIV, 0:0:0, 0, notifier);
$width (negedge OCLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule // ISERDES
`endcelldefine
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:19:47 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemWinner/MemWinner_funcsim.v
// Design : MemWinner
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "dist_mem_gen_v8_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "MemWinner,dist_mem_gen_v8_0,{}" *)
(* core_generation_info = "MemWinner,dist_mem_gen_v8_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_ADDR_WIDTH=5,C_DEFAULT_DATA=0,C_DEPTH=32,C_HAS_CLK=1,C_HAS_D=0,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=0,C_MEM_INIT_FILE=MemWinner.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=0,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=1,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=108,C_PARSER_TYPE=1}" *)
(* NotValidForBitStream *)
module MemWinner
(a,
clk,
spo);
input [4:0]a;
input clk;
output [107:0]spo;
wire [4:0]a;
wire clk;
wire [107:0]spo;
wire [107:0]NLW_U0_dpo_UNCONNECTED;
wire [107:0]NLW_U0_qdpo_UNCONNECTED;
wire [107:0]NLW_U0_qspo_UNCONNECTED;
(* C_FAMILY = "artix7" *)
(* C_HAS_D = "0" *)
(* C_HAS_DPO = "0" *)
(* C_HAS_DPRA = "0" *)
(* C_HAS_I_CE = "0" *)
(* C_HAS_QDPO = "0" *)
(* C_HAS_QDPO_CE = "0" *)
(* C_HAS_QDPO_CLK = "0" *)
(* C_HAS_QDPO_RST = "0" *)
(* C_HAS_QDPO_SRST = "0" *)
(* C_HAS_WE = "0" *)
(* C_MEM_TYPE = "0" *)
(* C_PIPELINE_STAGES = "0" *)
(* C_QCE_JOINED = "0" *)
(* C_QUALIFY_WE = "0" *)
(* C_REG_DPRA_INPUT = "0" *)
(* DONT_TOUCH *)
(* c_addr_width = "5" *)
(* c_default_data = "0" *)
(* c_depth = "32" *)
(* c_elaboration_dir = "./" *)
(* c_has_clk = "1" *)
(* c_has_qspo = "0" *)
(* c_has_qspo_ce = "0" *)
(* c_has_qspo_rst = "0" *)
(* c_has_qspo_srst = "0" *)
(* c_has_spo = "1" *)
(* c_mem_init_file = "MemWinner.mif" *)
(* c_parser_type = "1" *)
(* c_read_mif = "1" *)
(* c_reg_a_d_inputs = "1" *)
(* c_sync_enable = "1" *)
(* c_width = "108" *)
MemWinner_dist_mem_gen_v8_0__parameterized0 U0
(.a(a),
.clk(clk),
.d({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.dpo(NLW_U0_dpo_UNCONNECTED[107:0]),
.dpra({1'b0,1'b0,1'b0,1'b0,1'b0}),
.i_ce(1'b1),
.qdpo(NLW_U0_qdpo_UNCONNECTED[107:0]),
.qdpo_ce(1'b1),
.qdpo_clk(1'b0),
.qdpo_rst(1'b0),
.qdpo_srst(1'b0),
.qspo(NLW_U0_qspo_UNCONNECTED[107:0]),
.qspo_ce(1'b1),
.qspo_rst(1'b0),
.qspo_srst(1'b0),
.spo(spo),
.we(1'b0));
endmodule
(* ORIG_REF_NAME = "dist_mem_gen_v8_0" *) (* C_FAMILY = "artix7" *) (* C_ADDR_WIDTH = "5" *)
(* C_DEFAULT_DATA = "0" *) (* C_DEPTH = "32" *) (* C_HAS_CLK = "1" *)
(* C_HAS_D = "0" *) (* C_HAS_DPO = "0" *) (* C_HAS_DPRA = "0" *)
(* C_HAS_I_CE = "0" *) (* C_HAS_QDPO = "0" *) (* C_HAS_QDPO_CE = "0" *)
(* C_HAS_QDPO_CLK = "0" *) (* C_HAS_QDPO_RST = "0" *) (* C_HAS_QDPO_SRST = "0" *)
(* C_HAS_QSPO = "0" *) (* C_HAS_QSPO_CE = "0" *) (* C_HAS_QSPO_RST = "0" *)
(* C_HAS_QSPO_SRST = "0" *) (* C_HAS_SPO = "1" *) (* C_HAS_WE = "0" *)
(* C_MEM_INIT_FILE = "MemWinner.mif" *) (* C_ELABORATION_DIR = "./" *) (* C_MEM_TYPE = "0" *)
(* C_PIPELINE_STAGES = "0" *) (* C_QCE_JOINED = "0" *) (* C_QUALIFY_WE = "0" *)
(* C_READ_MIF = "1" *) (* C_REG_A_D_INPUTS = "1" *) (* C_REG_DPRA_INPUT = "0" *)
(* C_SYNC_ENABLE = "1" *) (* C_WIDTH = "108" *) (* C_PARSER_TYPE = "1" *)
module MemWinner_dist_mem_gen_v8_0__parameterized0
(a,
d,
dpra,
clk,
we,
i_ce,
qspo_ce,
qdpo_ce,
qdpo_clk,
qspo_rst,
qdpo_rst,
qspo_srst,
qdpo_srst,
spo,
dpo,
qspo,
qdpo);
input [4:0]a;
input [107:0]d;
input [4:0]dpra;
input clk;
input we;
input i_ce;
input qspo_ce;
input qdpo_ce;
input qdpo_clk;
input qspo_rst;
input qdpo_rst;
input qspo_srst;
input qdpo_srst;
output [107:0]spo;
output [107:0]dpo;
output [107:0]qspo;
output [107:0]qdpo;
wire \<const0> ;
wire [4:0]a;
wire clk;
wire [107:0]\^spo ;
assign dpo[107] = \<const0> ;
assign dpo[106] = \<const0> ;
assign dpo[105] = \<const0> ;
assign dpo[104] = \<const0> ;
assign dpo[103] = \<const0> ;
assign dpo[102] = \<const0> ;
assign dpo[101] = \<const0> ;
assign dpo[100] = \<const0> ;
assign dpo[99] = \<const0> ;
assign dpo[98] = \<const0> ;
assign dpo[97] = \<const0> ;
assign dpo[96] = \<const0> ;
assign dpo[95] = \<const0> ;
assign dpo[94] = \<const0> ;
assign dpo[93] = \<const0> ;
assign dpo[92] = \<const0> ;
assign dpo[91] = \<const0> ;
assign dpo[90] = \<const0> ;
assign dpo[89] = \<const0> ;
assign dpo[88] = \<const0> ;
assign dpo[87] = \<const0> ;
assign dpo[86] = \<const0> ;
assign dpo[85] = \<const0> ;
assign dpo[84] = \<const0> ;
assign dpo[83] = \<const0> ;
assign dpo[82] = \<const0> ;
assign dpo[81] = \<const0> ;
assign dpo[80] = \<const0> ;
assign dpo[79] = \<const0> ;
assign dpo[78] = \<const0> ;
assign dpo[77] = \<const0> ;
assign dpo[76] = \<const0> ;
assign dpo[75] = \<const0> ;
assign dpo[74] = \<const0> ;
assign dpo[73] = \<const0> ;
assign dpo[72] = \<const0> ;
assign dpo[71] = \<const0> ;
assign dpo[70] = \<const0> ;
assign dpo[69] = \<const0> ;
assign dpo[68] = \<const0> ;
assign dpo[67] = \<const0> ;
assign dpo[66] = \<const0> ;
assign dpo[65] = \<const0> ;
assign dpo[64] = \<const0> ;
assign dpo[63] = \<const0> ;
assign dpo[62] = \<const0> ;
assign dpo[61] = \<const0> ;
assign dpo[60] = \<const0> ;
assign dpo[59] = \<const0> ;
assign dpo[58] = \<const0> ;
assign dpo[57] = \<const0> ;
assign dpo[56] = \<const0> ;
assign dpo[55] = \<const0> ;
assign dpo[54] = \<const0> ;
assign dpo[53] = \<const0> ;
assign dpo[52] = \<const0> ;
assign dpo[51] = \<const0> ;
assign dpo[50] = \<const0> ;
assign dpo[49] = \<const0> ;
assign dpo[48] = \<const0> ;
assign dpo[47] = \<const0> ;
assign dpo[46] = \<const0> ;
assign dpo[45] = \<const0> ;
assign dpo[44] = \<const0> ;
assign dpo[43] = \<const0> ;
assign dpo[42] = \<const0> ;
assign dpo[41] = \<const0> ;
assign dpo[40] = \<const0> ;
assign dpo[39] = \<const0> ;
assign dpo[38] = \<const0> ;
assign dpo[37] = \<const0> ;
assign dpo[36] = \<const0> ;
assign dpo[35] = \<const0> ;
assign dpo[34] = \<const0> ;
assign dpo[33] = \<const0> ;
assign dpo[32] = \<const0> ;
assign dpo[31] = \<const0> ;
assign dpo[30] = \<const0> ;
assign dpo[29] = \<const0> ;
assign dpo[28] = \<const0> ;
assign dpo[27] = \<const0> ;
assign dpo[26] = \<const0> ;
assign dpo[25] = \<const0> ;
assign dpo[24] = \<const0> ;
assign dpo[23] = \<const0> ;
assign dpo[22] = \<const0> ;
assign dpo[21] = \<const0> ;
assign dpo[20] = \<const0> ;
assign dpo[19] = \<const0> ;
assign dpo[18] = \<const0> ;
assign dpo[17] = \<const0> ;
assign dpo[16] = \<const0> ;
assign dpo[15] = \<const0> ;
assign dpo[14] = \<const0> ;
assign dpo[13] = \<const0> ;
assign dpo[12] = \<const0> ;
assign dpo[11] = \<const0> ;
assign dpo[10] = \<const0> ;
assign dpo[9] = \<const0> ;
assign dpo[8] = \<const0> ;
assign dpo[7] = \<const0> ;
assign dpo[6] = \<const0> ;
assign dpo[5] = \<const0> ;
assign dpo[4] = \<const0> ;
assign dpo[3] = \<const0> ;
assign dpo[2] = \<const0> ;
assign dpo[1] = \<const0> ;
assign dpo[0] = \<const0> ;
assign qdpo[107] = \<const0> ;
assign qdpo[106] = \<const0> ;
assign qdpo[105] = \<const0> ;
assign qdpo[104] = \<const0> ;
assign qdpo[103] = \<const0> ;
assign qdpo[102] = \<const0> ;
assign qdpo[101] = \<const0> ;
assign qdpo[100] = \<const0> ;
assign qdpo[99] = \<const0> ;
assign qdpo[98] = \<const0> ;
assign qdpo[97] = \<const0> ;
assign qdpo[96] = \<const0> ;
assign qdpo[95] = \<const0> ;
assign qdpo[94] = \<const0> ;
assign qdpo[93] = \<const0> ;
assign qdpo[92] = \<const0> ;
assign qdpo[91] = \<const0> ;
assign qdpo[90] = \<const0> ;
assign qdpo[89] = \<const0> ;
assign qdpo[88] = \<const0> ;
assign qdpo[87] = \<const0> ;
assign qdpo[86] = \<const0> ;
assign qdpo[85] = \<const0> ;
assign qdpo[84] = \<const0> ;
assign qdpo[83] = \<const0> ;
assign qdpo[82] = \<const0> ;
assign qdpo[81] = \<const0> ;
assign qdpo[80] = \<const0> ;
assign qdpo[79] = \<const0> ;
assign qdpo[78] = \<const0> ;
assign qdpo[77] = \<const0> ;
assign qdpo[76] = \<const0> ;
assign qdpo[75] = \<const0> ;
assign qdpo[74] = \<const0> ;
assign qdpo[73] = \<const0> ;
assign qdpo[72] = \<const0> ;
assign qdpo[71] = \<const0> ;
assign qdpo[70] = \<const0> ;
assign qdpo[69] = \<const0> ;
assign qdpo[68] = \<const0> ;
assign qdpo[67] = \<const0> ;
assign qdpo[66] = \<const0> ;
assign qdpo[65] = \<const0> ;
assign qdpo[64] = \<const0> ;
assign qdpo[63] = \<const0> ;
assign qdpo[62] = \<const0> ;
assign qdpo[61] = \<const0> ;
assign qdpo[60] = \<const0> ;
assign qdpo[59] = \<const0> ;
assign qdpo[58] = \<const0> ;
assign qdpo[57] = \<const0> ;
assign qdpo[56] = \<const0> ;
assign qdpo[55] = \<const0> ;
assign qdpo[54] = \<const0> ;
assign qdpo[53] = \<const0> ;
assign qdpo[52] = \<const0> ;
assign qdpo[51] = \<const0> ;
assign qdpo[50] = \<const0> ;
assign qdpo[49] = \<const0> ;
assign qdpo[48] = \<const0> ;
assign qdpo[47] = \<const0> ;
assign qdpo[46] = \<const0> ;
assign qdpo[45] = \<const0> ;
assign qdpo[44] = \<const0> ;
assign qdpo[43] = \<const0> ;
assign qdpo[42] = \<const0> ;
assign qdpo[41] = \<const0> ;
assign qdpo[40] = \<const0> ;
assign qdpo[39] = \<const0> ;
assign qdpo[38] = \<const0> ;
assign qdpo[37] = \<const0> ;
assign qdpo[36] = \<const0> ;
assign qdpo[35] = \<const0> ;
assign qdpo[34] = \<const0> ;
assign qdpo[33] = \<const0> ;
assign qdpo[32] = \<const0> ;
assign qdpo[31] = \<const0> ;
assign qdpo[30] = \<const0> ;
assign qdpo[29] = \<const0> ;
assign qdpo[28] = \<const0> ;
assign qdpo[27] = \<const0> ;
assign qdpo[26] = \<const0> ;
assign qdpo[25] = \<const0> ;
assign qdpo[24] = \<const0> ;
assign qdpo[23] = \<const0> ;
assign qdpo[22] = \<const0> ;
assign qdpo[21] = \<const0> ;
assign qdpo[20] = \<const0> ;
assign qdpo[19] = \<const0> ;
assign qdpo[18] = \<const0> ;
assign qdpo[17] = \<const0> ;
assign qdpo[16] = \<const0> ;
assign qdpo[15] = \<const0> ;
assign qdpo[14] = \<const0> ;
assign qdpo[13] = \<const0> ;
assign qdpo[12] = \<const0> ;
assign qdpo[11] = \<const0> ;
assign qdpo[10] = \<const0> ;
assign qdpo[9] = \<const0> ;
assign qdpo[8] = \<const0> ;
assign qdpo[7] = \<const0> ;
assign qdpo[6] = \<const0> ;
assign qdpo[5] = \<const0> ;
assign qdpo[4] = \<const0> ;
assign qdpo[3] = \<const0> ;
assign qdpo[2] = \<const0> ;
assign qdpo[1] = \<const0> ;
assign qdpo[0] = \<const0> ;
assign qspo[107] = \<const0> ;
assign qspo[106] = \<const0> ;
assign qspo[105] = \<const0> ;
assign qspo[104] = \<const0> ;
assign qspo[103] = \<const0> ;
assign qspo[102] = \<const0> ;
assign qspo[101] = \<const0> ;
assign qspo[100] = \<const0> ;
assign qspo[99] = \<const0> ;
assign qspo[98] = \<const0> ;
assign qspo[97] = \<const0> ;
assign qspo[96] = \<const0> ;
assign qspo[95] = \<const0> ;
assign qspo[94] = \<const0> ;
assign qspo[93] = \<const0> ;
assign qspo[92] = \<const0> ;
assign qspo[91] = \<const0> ;
assign qspo[90] = \<const0> ;
assign qspo[89] = \<const0> ;
assign qspo[88] = \<const0> ;
assign qspo[87] = \<const0> ;
assign qspo[86] = \<const0> ;
assign qspo[85] = \<const0> ;
assign qspo[84] = \<const0> ;
assign qspo[83] = \<const0> ;
assign qspo[82] = \<const0> ;
assign qspo[81] = \<const0> ;
assign qspo[80] = \<const0> ;
assign qspo[79] = \<const0> ;
assign qspo[78] = \<const0> ;
assign qspo[77] = \<const0> ;
assign qspo[76] = \<const0> ;
assign qspo[75] = \<const0> ;
assign qspo[74] = \<const0> ;
assign qspo[73] = \<const0> ;
assign qspo[72] = \<const0> ;
assign qspo[71] = \<const0> ;
assign qspo[70] = \<const0> ;
assign qspo[69] = \<const0> ;
assign qspo[68] = \<const0> ;
assign qspo[67] = \<const0> ;
assign qspo[66] = \<const0> ;
assign qspo[65] = \<const0> ;
assign qspo[64] = \<const0> ;
assign qspo[63] = \<const0> ;
assign qspo[62] = \<const0> ;
assign qspo[61] = \<const0> ;
assign qspo[60] = \<const0> ;
assign qspo[59] = \<const0> ;
assign qspo[58] = \<const0> ;
assign qspo[57] = \<const0> ;
assign qspo[56] = \<const0> ;
assign qspo[55] = \<const0> ;
assign qspo[54] = \<const0> ;
assign qspo[53] = \<const0> ;
assign qspo[52] = \<const0> ;
assign qspo[51] = \<const0> ;
assign qspo[50] = \<const0> ;
assign qspo[49] = \<const0> ;
assign qspo[48] = \<const0> ;
assign qspo[47] = \<const0> ;
assign qspo[46] = \<const0> ;
assign qspo[45] = \<const0> ;
assign qspo[44] = \<const0> ;
assign qspo[43] = \<const0> ;
assign qspo[42] = \<const0> ;
assign qspo[41] = \<const0> ;
assign qspo[40] = \<const0> ;
assign qspo[39] = \<const0> ;
assign qspo[38] = \<const0> ;
assign qspo[37] = \<const0> ;
assign qspo[36] = \<const0> ;
assign qspo[35] = \<const0> ;
assign qspo[34] = \<const0> ;
assign qspo[33] = \<const0> ;
assign qspo[32] = \<const0> ;
assign qspo[31] = \<const0> ;
assign qspo[30] = \<const0> ;
assign qspo[29] = \<const0> ;
assign qspo[28] = \<const0> ;
assign qspo[27] = \<const0> ;
assign qspo[26] = \<const0> ;
assign qspo[25] = \<const0> ;
assign qspo[24] = \<const0> ;
assign qspo[23] = \<const0> ;
assign qspo[22] = \<const0> ;
assign qspo[21] = \<const0> ;
assign qspo[20] = \<const0> ;
assign qspo[19] = \<const0> ;
assign qspo[18] = \<const0> ;
assign qspo[17] = \<const0> ;
assign qspo[16] = \<const0> ;
assign qspo[15] = \<const0> ;
assign qspo[14] = \<const0> ;
assign qspo[13] = \<const0> ;
assign qspo[12] = \<const0> ;
assign qspo[11] = \<const0> ;
assign qspo[10] = \<const0> ;
assign qspo[9] = \<const0> ;
assign qspo[8] = \<const0> ;
assign qspo[7] = \<const0> ;
assign qspo[6] = \<const0> ;
assign qspo[5] = \<const0> ;
assign qspo[4] = \<const0> ;
assign qspo[3] = \<const0> ;
assign qspo[2] = \<const0> ;
assign qspo[1] = \<const0> ;
assign qspo[0] = \<const0> ;
assign spo[107:85] = \^spo [107:85];
assign spo[84] = \<const0> ;
assign spo[83] = \<const0> ;
assign spo[82:80] = \^spo [82:80];
assign spo[79] = \<const0> ;
assign spo[78] = \<const0> ;
assign spo[77] = \<const0> ;
assign spo[76] = \<const0> ;
assign spo[75:61] = \^spo [75:61];
assign spo[60] = \<const0> ;
assign spo[59] = \<const0> ;
assign spo[58] = \<const0> ;
assign spo[57] = \<const0> ;
assign spo[56:42] = \^spo [56:42];
assign spo[41] = \<const0> ;
assign spo[40] = \<const0> ;
assign spo[39] = \<const0> ;
assign spo[38] = \<const0> ;
assign spo[37:24] = \^spo [37:24];
assign spo[23] = \<const0> ;
assign spo[22] = \<const0> ;
assign spo[21] = \<const0> ;
assign spo[20:6] = \^spo [20:6];
assign spo[5] = \<const0> ;
assign spo[4] = \<const0> ;
assign spo[3] = \<const0> ;
assign spo[2:0] = \^spo [2:0];
GND GND
(.G(\<const0> ));
MemWinner_dist_mem_gen_v8_0_synth \synth_options.dist_mem_inst
(.a(a),
.clk(clk),
.spo({\^spo [107:85],\^spo [82:80],\^spo [75:61],\^spo [56:42],\^spo [37:24],\^spo [20:6],\^spo [2:0]}));
endmodule
(* ORIG_REF_NAME = "dist_mem_gen_v8_0_synth" *)
module MemWinner_dist_mem_gen_v8_0_synth
(spo,
a,
clk);
output [87:0]spo;
input [4:0]a;
input clk;
wire [4:0]a;
wire clk;
wire [87:0]spo;
MemWinner_rom__parameterized0 \gen_rom.rom_inst
(.a(a),
.clk(clk),
.spo(spo));
endmodule
(* ORIG_REF_NAME = "rom" *)
module MemWinner_rom__parameterized0
(spo,
a,
clk);
output [87:0]spo;
input [4:0]a;
input clk;
wire [4:0]a;
wire [4:0]a_reg;
wire clk;
wire [87:0]spo;
FDRE #(
.INIT(1'b0))
\a_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(a[0]),
.Q(a_reg[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\a_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(a[1]),
.Q(a_reg[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\a_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(a[2]),
.Q(a_reg[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\a_reg_reg[3]
(.C(clk),
.CE(1'b1),
.D(a[3]),
.Q(a_reg[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\a_reg_reg[4]
(.C(clk),
.CE(1'b1),
.D(a[4]),
.Q(a_reg[4]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00019FFF))
g0_b0
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00019FFF))
g0_b1
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[1]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00001F87))
g0_b10
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[7]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT5 #(
.INIT(32'h0001FF00))
g0_b100
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[80]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT5 #(
.INIT(32'h0001F800))
g0_b101
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[81]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT5 #(
.INIT(32'h0001FE00))
g0_b102
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[82]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT5 #(
.INIT(32'h00007FE0))
g0_b103
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[83]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT4 #(
.INIT(16'h003E))
g0_b104
(.I0(a_reg[1]),
.I1(a_reg[2]),
.I2(a_reg[3]),
.I3(a_reg[4]),
.O(spo[84]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT5 #(
.INIT(32'h000001FF))
g0_b105
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[85]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT5 #(
.INIT(32'h0000001F))
g0_b106
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[86]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT4 #(
.INIT(16'h0001))
g0_b107
(.I0(a_reg[1]),
.I1(a_reg[2]),
.I2(a_reg[3]),
.I3(a_reg[4]),
.O(spo[87]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h00000703))
g0_b11
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[8]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h00000703))
g0_b12
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[9]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'h01))
g0_b13
(.I0(a_reg[1]),
.I1(a_reg[2]),
.I2(a_reg[4]),
.O(spo[10]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'h01))
g0_b14
(.I0(a_reg[1]),
.I1(a_reg[2]),
.I2(a_reg[4]),
.O(spo[11]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'h01))
g0_b15
(.I0(a_reg[1]),
.I1(a_reg[2]),
.I2(a_reg[4]),
.O(spo[12]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'h01))
g0_b16
(.I0(a_reg[1]),
.I1(a_reg[2]),
.I2(a_reg[4]),
.O(spo[13]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'h01))
g0_b17
(.I0(a_reg[1]),
.I1(a_reg[2]),
.I2(a_reg[4]),
.O(spo[14]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b18
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[15]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b19
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[16]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00019FFF))
g0_b2
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[2]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b20
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[17]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00018003))
g0_b24
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[18]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h00018183))
g0_b25
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[19]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h00018183))
g0_b26
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[20]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h00018183))
g0_b27
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[21]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h00018183))
g0_b28
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[22]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h00018183))
g0_b29
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[23]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h00018183))
g0_b30
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[24]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h00018183))
g0_b31
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[25]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h00018183))
g0_b32
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[26]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h00018183))
g0_b33
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[27]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h00018183))
g0_b34
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[28]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b35
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[29]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b36
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[30]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b37
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[31]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b42
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[32]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b43
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[33]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b44
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[34]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'h0001F000))
g0_b45
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[35]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'h00007800))
g0_b46
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[36]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'h00003E00))
g0_b47
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[37]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'h04))
g0_b48
(.I0(a_reg[2]),
.I1(a_reg[3]),
.I2(a_reg[4]),
.O(spo[38]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'h000007C0))
g0_b49
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[39]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'h000001E0))
g0_b50
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[40]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'h000000F8))
g0_b51
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[41]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT4 #(
.INIT(16'h0006))
g0_b52
(.I0(a_reg[1]),
.I1(a_reg[2]),
.I2(a_reg[3]),
.I3(a_reg[4]),
.O(spo[42]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'h0000001F))
g0_b53
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[43]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b54
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[44]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b55
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[45]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b56
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[46]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00010000))
g0_b6
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[3]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b61
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[47]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b62
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[48]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b63
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[49]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'h0001F000))
g0_b64
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[50]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT5 #(
.INIT(32'h00007800))
g0_b65
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[51]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT5 #(
.INIT(32'h00003E00))
g0_b66
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[52]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'h04))
g0_b67
(.I0(a_reg[2]),
.I1(a_reg[3]),
.I2(a_reg[4]),
.O(spo[53]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'h000007C0))
g0_b68
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[54]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'h000001E0))
g0_b69
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[55]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h0001E078))
g0_b7
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[4]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT5 #(
.INIT(32'h000000F8))
g0_b70
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[56]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT4 #(
.INIT(16'h0006))
g0_b71
(.I0(a_reg[1]),
.I1(a_reg[2]),
.I2(a_reg[3]),
.I3(a_reg[4]),
.O(spo[57]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT5 #(
.INIT(32'h0000001F))
g0_b72
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[58]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b73
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[59]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b74
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[60]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b75
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[61]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h0001F9FE))
g0_b8
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[5]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b80
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[62]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b81
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[63]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT5 #(
.INIT(32'h0001FFFF))
g0_b82
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[64]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT4 #(
.INIT(16'h0001))
g0_b85
(.I0(a_reg[1]),
.I1(a_reg[2]),
.I2(a_reg[3]),
.I3(a_reg[4]),
.O(spo[65]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT5 #(
.INIT(32'h0000001F))
g0_b86
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[66]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT5 #(
.INIT(32'h000001FF))
g0_b87
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[67]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT4 #(
.INIT(16'h003E))
g0_b88
(.I0(a_reg[1]),
.I1(a_reg[2]),
.I2(a_reg[3]),
.I3(a_reg[4]),
.O(spo[68]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT5 #(
.INIT(32'h00007FE0))
g0_b89
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[69]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h0000FDFF))
g0_b9
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[6]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT5 #(
.INIT(32'h0001FE00))
g0_b90
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[70]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h0001F800))
g0_b91
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[71]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h0001FF00))
g0_b92
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[72]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h00007FF0))
g0_b93
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[73]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h000007FE))
g0_b94
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[74]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT2 #(
.INIT(4'h1))
g0_b95
(.I0(a_reg[3]),
.I1(a_reg[4]),
.O(spo[75]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'h01))
g0_b96
(.I0(a_reg[2]),
.I1(a_reg[3]),
.I2(a_reg[4]),
.O(spo[76]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT2 #(
.INIT(4'h1))
g0_b97
(.I0(a_reg[3]),
.I1(a_reg[4]),
.O(spo[77]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT5 #(
.INIT(32'h000007FE))
g0_b98
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[78]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT5 #(
.INIT(32'h00007FF0))
g0_b99
(.I0(a_reg[0]),
.I1(a_reg[1]),
.I2(a_reg[2]),
.I3(a_reg[3]),
.I4(a_reg[4]),
.O(spo[79]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 100ps/100ps
module ArbitorTest;
wire [1:0] w_grant_2;
wire [3:0] w_grant_4;
reg [3:0] r_request;
reg r_error;
FixedPriorityArbitor arbitor_2(
.i_request(r_request[1:0]),
.o_grant (w_grant_2 ));
FixedPriorityArbitor #(.width(4)) arbitor_4(
.i_request(r_request ),
.o_grant (w_grant_4 ));
always @ (posedge r_error) begin
$display("unexpected grant %b for request %b", w_grant_4, r_request);
end
initial begin
//$dumpfile("Arbitor.vcd");
//$dumpvars(0, arbitor_4);
r_error <= 1'b0;
r_request <= 4'b0000;
#1
r_error <= w_grant_4 != 4'b0000;
#1
r_request <= 4'b0001;
#1
r_error <= w_grant_4 != 4'b0001;
#1
r_request <= 4'b0010;
#1
r_error <= w_grant_4 != 4'b0010;
#1
r_request <= 4'b0100;
#1
r_error <= w_grant_4 != 4'b0100;
#1
r_request <= 4'b1000;
#1
r_error <= w_grant_4 != 4'b1000;
#1
r_request <= 4'b0101;
#1
r_error <= w_grant_4 != 4'b0001;
#1
r_request <= 4'b1110;
#1
r_error <= w_grant_4 != 4'b0010;
#1
r_request <= 4'b1111;
#1
r_error <= w_grant_4 != 4'b0001;
#1
$finish;
end
endmodule // ParityTest
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 31 20:13:47 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_rst_ps7_0_100M_0/system_rst_ps7_0_100M_0_sim_netlist.v
// Design : system_rst_ps7_0_100M_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_rst_ps7_0_100M_0
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "zynq" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
system_rst_ps7_0_100M_0_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module system_rst_ps7_0_100M_0_cdc_sync
(lpf_asr_reg,
scndry_out,
aux_reset_in,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
slowest_sync_clk);
output lpf_asr_reg;
output scndry_out;
input aux_reset_in;
input lpf_asr;
input [0:0]asr_lpf;
input p_1_in;
input p_2_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(asr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
(.I0(aux_reset_in),
.O(asr_d1));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_asr_i_1
(.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O(lpf_asr_reg));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module system_rst_ps7_0_100M_0_cdc_sync_0
(lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0]p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0]p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
(.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_exr_i_1
(.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O(lpf_exr_reg));
endmodule
(* ORIG_REF_NAME = "lpf" *)
module system_rst_ps7_0_100M_0_lpf
(lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0]p_3_out;
wire slowest_sync_clk;
system_rst_ps7_0_100M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
(.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk));
system_rst_ps7_0_100M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
(.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
\AUX_LPF[1].asr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_in1_in),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[2].asr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_2_in),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[3].asr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_1_in),
.Q(asr_lpf),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[1].exr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[3]),
.Q(p_3_out[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[2].exr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(p_3_out[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[3].exr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[1]),
.Q(p_3_out[0]),
.R(1'b0));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "SRL16" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF))
POR_SRL_I
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(slowest_sync_clk),
.D(1'b0),
.Q(Q));
FDRE #(
.INIT(1'b0))
lpf_asr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q(lpf_asr),
.R(1'b0));
FDRE #(
.INIT(1'b0))
lpf_exr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q(lpf_exr),
.R(1'b0));
LUT4 #(
.INIT(16'hFFEF))
lpf_int0
(.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O(lpf_int0__0));
FDRE #(
.INIT(1'b0))
lpf_int_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(lpf_int0__0),
.Q(lpf_int),
.R(1'b0));
endmodule
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
(* ORIG_REF_NAME = "proc_sys_reset" *)
module system_rst_ps7_0_100M_0_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn;
wire Core;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire bsr;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire pr;
wire slowest_sync_clk;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_3),
.Q(interconnect_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_4),
.Q(peripheral_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr),
.Q(bus_struct_reset),
.R(1'b0));
system_rst_ps7_0_100M_0_lpf EXT_LPF
(.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\PR_OUT_DFF[0].peripheral_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr),
.Q(peripheral_reset),
.R(1'b0));
system_rst_ps7_0_100M_0_sequence_psr SEQ
(.\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] (SEQ_n_4),
.Core(Core),
.bsr(bsr),
.lpf_int(lpf_int),
.pr(pr),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
mb_reset_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core),
.Q(mb_reset),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "sequence_psr" *)
module system_rst_ps7_0_100M_0_sequence_psr
(Core,
bsr,
pr,
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ,
lpf_int,
slowest_sync_clk);
output Core;
output bsr;
output pr;
output \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
output \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
input lpf_int;
input slowest_sync_clk;
wire \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
wire \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
wire Core;
wire Core_i_1_n_0;
wire bsr;
wire \bsr_dec_reg_n_0_[0] ;
wire \bsr_dec_reg_n_0_[2] ;
wire bsr_i_1_n_0;
wire \core_dec[0]_i_1_n_0 ;
wire \core_dec[2]_i_1_n_0 ;
wire \core_dec_reg_n_0_[0] ;
wire \core_dec_reg_n_0_[1] ;
wire from_sys_i_1_n_0;
wire lpf_int;
wire p_0_in;
wire [2:0]p_3_out;
wire [2:0]p_5_out;
wire pr;
wire pr_dec0__0;
wire \pr_dec_reg_n_0_[0] ;
wire \pr_dec_reg_n_0_[2] ;
wire pr_i_1_n_0;
wire seq_clr;
wire [5:0]seq_cnt;
wire seq_cnt_en;
wire slowest_sync_clk;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1
(.I0(bsr),
.O(\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1
(.I0(pr),
.O(\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
Core_i_1
(.I0(Core),
.I1(p_0_in),
.O(Core_i_1_n_0));
FDSE #(
.INIT(1'b0))
Core_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core_i_1_n_0),
.Q(Core),
.S(lpf_int));
system_rst_ps7_0_100M_0_upcnt_n SEQ_COUNTER
(.Q(seq_cnt),
.seq_clr(seq_clr),
.seq_cnt_en(seq_cnt_en),
.slowest_sync_clk(slowest_sync_clk));
LUT4 #(
.INIT(16'h0804))
\bsr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt[4]),
.O(p_5_out[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\bsr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\bsr_dec_reg_n_0_[0] ),
.O(p_5_out[2]));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[0]),
.Q(\bsr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[2]),
.Q(\bsr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
bsr_i_1
(.I0(bsr),
.I1(\bsr_dec_reg_n_0_[2] ),
.O(bsr_i_1_n_0));
FDSE #(
.INIT(1'b0))
bsr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr_i_1_n_0),
.Q(bsr),
.S(lpf_int));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8040))
\core_dec[0]_i_1
(.I0(seq_cnt[4]),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt_en),
.O(\core_dec[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\core_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\core_dec_reg_n_0_[0] ),
.O(\core_dec[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\core_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[0]_i_1_n_0 ),
.Q(\core_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_dec0__0),
.Q(\core_dec_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[2]_i_1_n_0 ),
.Q(p_0_in),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
from_sys_i_1
(.I0(Core),
.I1(seq_cnt_en),
.O(from_sys_i_1_n_0));
FDSE #(
.INIT(1'b0))
from_sys_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(from_sys_i_1_n_0),
.Q(seq_cnt_en),
.S(lpf_int));
LUT4 #(
.INIT(16'h0210))
pr_dec0
(.I0(seq_cnt[0]),
.I1(seq_cnt[1]),
.I2(seq_cnt[2]),
.I3(seq_cnt_en),
.O(pr_dec0__0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h1080))
\pr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[5]),
.I2(seq_cnt[3]),
.I3(seq_cnt[4]),
.O(p_3_out[0]));
LUT2 #(
.INIT(4'h8))
\pr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\pr_dec_reg_n_0_[0] ),
.O(p_3_out[2]));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[0]),
.Q(\pr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(\pr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
pr_i_1
(.I0(pr),
.I1(\pr_dec_reg_n_0_[2] ),
.O(pr_i_1_n_0));
FDSE #(
.INIT(1'b0))
pr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_i_1_n_0),
.Q(pr),
.S(lpf_int));
FDRE #(
.INIT(1'b0))
seq_clr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(1'b1),
.Q(seq_clr),
.R(lpf_int));
endmodule
(* ORIG_REF_NAME = "upcnt_n" *)
module system_rst_ps7_0_100M_0_upcnt_n
(Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk);
output [5:0]Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0]Q;
wire clear;
wire [5:0]q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1))
\q_int[0]_i_1
(.I0(Q[0]),
.O(q_int0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\q_int[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(q_int0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\q_int[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(q_int0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\q_int[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(q_int0[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\q_int[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(q_int0[4]));
LUT1 #(
.INIT(2'h1))
\q_int[5]_i_1
(.I0(seq_clr),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\q_int[5]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(q_int0[5]));
FDRE #(
.INIT(1'b1))
\q_int_reg[0]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[0]),
.Q(Q[0]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[1]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[1]),
.Q(Q[1]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[2]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[2]),
.Q(Q[2]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[3]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[3]),
.Q(Q[3]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[4]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[4]),
.Q(Q[4]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[5]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[5]),
.Q(Q[5]),
.R(clear));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 200MHz
* Reset: Push button, active high
*/
input wire clk_200mhz_p,
input wire clk_200mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_sgmii_rx_p,
input wire phy_sgmii_rx_n,
output wire phy_sgmii_tx_p,
output wire phy_sgmii_tx_n,
input wire phy_sgmii_clk_p,
input wire phy_sgmii_clk_n,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_200mhz_ibufg;
// Internal 125 MHz clock
wire clk_mmcm_out;
wire clk_int;
wire rst_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS
clk_200mhz_ibufgds_inst(
.I(clk_200mhz_p),
.IB(clk_200mhz_n),
.O(clk_200mhz_ibufg)
);
// MMCM instance
// 200 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 5, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(8),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(5.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_200mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_bufg_inst (
.I(clk_mmcm_out),
.O(clk_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.out(rst_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);
wire [7:0] led_int;
// SGMII interface to PHY
wire phy_gmii_clk_int;
wire phy_gmii_rst_int;
wire phy_gmii_clk_en_int;
wire [7:0] phy_gmii_txd_int;
wire phy_gmii_tx_en_int;
wire phy_gmii_tx_er_int;
wire [7:0] phy_gmii_rxd_int;
wire phy_gmii_rx_dv_int;
wire phy_gmii_rx_er_int;
wire phy_sgmii_userclk2;
wire phy_sgmii_resetdone;
assign phy_gmii_clk_int = phy_sgmii_userclk2;
sync_reset #(
.N(4)
)
sync_reset_pcspma_inst (
.clk(phy_gmii_clk_int),
.rst(rst_int || !phy_sgmii_resetdone),
.out(phy_gmii_rst_int)
);
wire [15:0] pcspma_status_vector;
wire pcspma_status_link_status = pcspma_status_vector[0];
wire pcspma_status_link_synchronization = pcspma_status_vector[1];
wire pcspma_status_rudi_c = pcspma_status_vector[2];
wire pcspma_status_rudi_i = pcspma_status_vector[3];
wire pcspma_status_rudi_invalid = pcspma_status_vector[4];
wire pcspma_status_rxdisperr = pcspma_status_vector[5];
wire pcspma_status_rxnotintable = pcspma_status_vector[6];
wire pcspma_status_phy_link_status = pcspma_status_vector[7];
wire [1:0] pcspma_status_remote_fault_encdg = pcspma_status_vector[9:8];
wire [1:0] pcspma_status_speed = pcspma_status_vector[11:10];
wire pcspma_status_duplex = pcspma_status_vector[12];
wire pcspma_status_remote_fault = pcspma_status_vector[13];
wire [1:0] pcspma_status_pause = pcspma_status_vector[15:14];
wire [4:0] pcspma_config_vector;
assign pcspma_config_vector[4] = 1'b1; // autonegotiation enable
assign pcspma_config_vector[3] = 1'b0; // isolate
assign pcspma_config_vector[2] = 1'b0; // power down
assign pcspma_config_vector[1] = 1'b0; // loopback enable
assign pcspma_config_vector[0] = 1'b0; // unidirectional enable
wire [15:0] pcspma_an_config_vector;
assign pcspma_an_config_vector[15] = 1'b1; // SGMII link status
assign pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
assign pcspma_an_config_vector[13:12] = 2'b01; // full duplex
assign pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
assign pcspma_an_config_vector[9] = 1'b0; // reserved
assign pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
assign pcspma_an_config_vector[6] = 1'b0; // reserved
assign pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
assign pcspma_an_config_vector[4:1] = 4'b0000; // reserved
assign pcspma_an_config_vector[0] = 1'b1; // SGMII
gig_ethernet_pcs_pma_0
eth_pcspma (
// Transceiver Interface
.gtrefclk_p (phy_sgmii_clk_p),
.gtrefclk_n (phy_sgmii_clk_n),
.gtrefclk_out (),
.gtrefclk_bufg_out (),
.txp (phy_sgmii_tx_p),
.txn (phy_sgmii_tx_n),
.rxp (phy_sgmii_rx_p),
.rxn (phy_sgmii_rx_n),
.resetdone (phy_sgmii_resetdone),
.userclk_out (),
.userclk2_out (phy_sgmii_userclk2),
.rxuserclk_out (),
.rxuserclk2_out (),
.independent_clock_bufg(clk_int),
.pma_reset_out (),
.mmcm_locked_out (),
.gt0_qplloutclk_out (),
.gt0_qplloutrefclk_out (),
// GMII Interface
.sgmii_clk_r (),
.sgmii_clk_f (),
.sgmii_clk_en (phy_gmii_clk_en_int),
.gmii_txd (phy_gmii_txd_int),
.gmii_tx_en (phy_gmii_tx_en_int),
.gmii_tx_er (phy_gmii_tx_er_int),
.gmii_rxd (phy_gmii_rxd_int),
.gmii_rx_dv (phy_gmii_rx_dv_int),
.gmii_rx_er (phy_gmii_rx_er_int),
.gmii_isolate (),
// Management: Alternative to MDIO Interface
.configuration_vector (pcspma_config_vector),
.an_interrupt (),
.an_adv_config_vector (pcspma_an_config_vector),
.an_restart_config (1'b0),
// Speed Control
.speed_is_10_100 (pcspma_status_speed != 2'b10),
.speed_is_100 (pcspma_status_speed == 2'b01),
// General IO's
.status_vector (pcspma_status_vector),
.reset (rst_int),
.signal_detect (1'b1)
);
// SGMII interface debug:
// SW1:1 (sw[0]) off for payload byte, on for status vector
// SW1:2 (sw[1]) off for LSB of status vector, on for MSB
assign led = sw[3] ? (sw[2] ? pcspma_status_vector[15:8] : pcspma_status_vector[7:0]) : led_int;
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led_int),
/*
* Ethernet: 1000BASE-T SGMII
*/
.phy_gmii_clk(phy_gmii_clk_int),
.phy_gmii_rst(phy_gmii_rst_int),
.phy_gmii_clk_en(phy_gmii_clk_en_int),
.phy_gmii_rxd(phy_gmii_rxd_int),
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
.phy_gmii_rx_er(phy_gmii_rx_er_int),
.phy_gmii_txd(phy_gmii_txd_int),
.phy_gmii_tx_en(phy_gmii_tx_en_int),
.phy_gmii_tx_er(phy_gmii_tx_er_int),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule
`resetall
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:38:41 03/01/2016
// Design Name:
// Module Name: Registro_universal
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Registro_Universal
(
input wire aumentar, //boton aumentar
input wire disminuir, //boton disminuir
input wire clk, //system clock
input wire reset, //system reset
input wire chip_select, //Control data
output wire out_aumentar, //boton aumentar
output wire out_disminuir //boton disminuir
);
//body
reg aumentar_actual,disminuir_actual,aumentar_next,disminuir_next;
//Combinacional
always@(posedge clk, posedge reset)
begin
if(reset)
begin
aumentar_actual <= 0;
disminuir_actual <= 0;
end
else
begin
aumentar_actual <= aumentar_next;
disminuir_actual <= disminuir_next;
end
end
//Secuencial
always@*
begin
case(chip_select)
1'b0: //Hold
begin
aumentar_next = aumentar_actual;
disminuir_next = disminuir_actual;
end
1'b1: //Load
begin
aumentar_next = aumentar;
disminuir_next = disminuir;
end
endcase
end
assign out_aumentar = aumentar_actual;
assign out_disminuir = disminuir_actual;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_TB_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_TB_V
/**
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer, vpb/vnb
* taps, double-row-height cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.v"
module top();
// Inputs are registered
reg A;
reg LOWLVPWR;
reg VPWR;
reg VGND;
reg VPB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
LOWLVPWR = 1'bX;
VGND = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 LOWLVPWR = 1'b0;
#60 VGND = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 LOWLVPWR = 1'b1;
#160 VGND = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 LOWLVPWR = 1'b0;
#260 VGND = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VGND = 1'b1;
#380 LOWLVPWR = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VGND = 1'bx;
#480 LOWLVPWR = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap dut (.A(A), .LOWLVPWR(LOWLVPWR), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_TB_V
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_usr_wr.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Mon Aug 28 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR/DDR2
//Purpose:
// This module instantiates the modules containing internal FIFOs
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_usr_wr #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_36_1 module. Please refer to
// the mig_36_1 module for actual values.
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter CS_BITS = 0,
parameter DQ_WIDTH = 72,
parameter APPDATA_WIDTH = 144,
parameter ECC_ENABLE = 0,
parameter ROW_WIDTH = 14
)
(
input clk0,
input clk90,
input rst0,
// Write data FIFO interface
input app_wdf_wren,
input [APPDATA_WIDTH-1:0] app_wdf_data,
input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
input wdf_rden,
output app_wdf_afull,
output [(2*DQ_WIDTH)-1:0] wdf_data,
output [((2*DQ_WIDTH)/8)-1:0] wdf_mask_data
);
// determine number of FIFO72's to use based on data width
// round up to next integer value when determining WDF_FIFO_NUM
localparam WDF_FIFO_NUM = (ECC_ENABLE) ? (APPDATA_WIDTH+63)/64 :
((2*DQ_WIDTH)+63)/64;
// MASK_WIDTH = number of bytes in data bus
localparam MASK_WIDTH = DQ_WIDTH/8;
wire [WDF_FIFO_NUM-1:0] i_wdf_afull;
wire [DQ_WIDTH-1:0] i_wdf_data_fall_in;
wire [DQ_WIDTH-1:0] i_wdf_data_fall_out;
wire [(64*WDF_FIFO_NUM)-1:0] i_wdf_data_in;
wire [(64*WDF_FIFO_NUM)-1:0] i_wdf_data_out;
wire [DQ_WIDTH-1:0] i_wdf_data_rise_in;
wire [DQ_WIDTH-1:0] i_wdf_data_rise_out;
wire [MASK_WIDTH-1:0] i_wdf_mask_data_fall_in;
wire [MASK_WIDTH-1:0] i_wdf_mask_data_fall_out;
wire [(8*WDF_FIFO_NUM)-1:0] i_wdf_mask_data_in;
wire [(8*WDF_FIFO_NUM)-1:0] i_wdf_mask_data_out;
wire [MASK_WIDTH-1:0] i_wdf_mask_data_rise_in;
wire [MASK_WIDTH-1:0] i_wdf_mask_data_rise_out;
reg rst_r;
// ECC signals
wire [(2*DQ_WIDTH)-1:0] i_wdf_data_out_ecc;
wire [((2*DQ_WIDTH)/8)-1:0] i_wdf_mask_data_out_ecc;
wire [63:0] i_wdf_mask_data_out_ecc_wire;
wire [((2*DQ_WIDTH)/8)-1:0] mask_data_in_ecc;
wire [63:0] mask_data_in_ecc_wire;
//***************************************************************************
assign app_wdf_afull = i_wdf_afull[0];
always @(posedge clk0 )
rst_r <= rst0;
genvar wdf_di_i;
genvar wdf_do_i;
genvar mask_i;
genvar wdf_i;
generate
if(ECC_ENABLE) begin // ECC code
assign wdf_data = i_wdf_data_out_ecc;
// the byte 9 dm is always held to 0
assign wdf_mask_data = i_wdf_mask_data_out_ecc;
// generate for write data fifo .
for (wdf_i = 0; wdf_i < WDF_FIFO_NUM; wdf_i = wdf_i + 1) begin: gen_wdf
FIFO36_72 #
(
.ALMOST_EMPTY_OFFSET (9'h007),
.ALMOST_FULL_OFFSET (9'h00F),
.DO_REG (1), // extra CC output delay
.EN_ECC_WRITE ("TRUE"),
.EN_ECC_READ ("FALSE"),
.EN_SYN ("FALSE"),
.FIRST_WORD_FALL_THROUGH ("FALSE")
)
u_wdf_ecc
(
.ALMOSTEMPTY (),
.ALMOSTFULL (i_wdf_afull[wdf_i]),
.DBITERR (),
.DO (i_wdf_data_out_ecc[((64*(wdf_i+1))+(wdf_i *8))-1:
(64*wdf_i)+(wdf_i *8)]),
.DOP (i_wdf_data_out_ecc[(72*(wdf_i+1))-1:
(64*(wdf_i+1))+ (8*wdf_i) ]),
.ECCPARITY (),
.EMPTY (),
.FULL (),
.RDCOUNT (),
.RDERR (),
.SBITERR (),
.WRCOUNT (),
.WRERR (),
.DI (app_wdf_data[(64*(wdf_i+1))-1:
(64*wdf_i)]),
.DIP (),
.RDCLK (clk90),
.RDEN (wdf_rden),
.RST (rst_r), // or can use rst0
.WRCLK (clk0),
.WREN (app_wdf_wren)
);
end
// remapping the mask data. The mask data from user i/f does not have
// the mask for the ECC byte. Assigning 0 to the ECC mask byte.
for (mask_i = 0; mask_i < (DQ_WIDTH)/36;
mask_i = mask_i +1) begin: gen_mask
assign mask_data_in_ecc[((8*(mask_i+1))+ mask_i)-1:((8*mask_i)+mask_i)]
= app_wdf_mask_data[(8*(mask_i+1))-1:8*(mask_i)] ;
assign mask_data_in_ecc[((8*(mask_i+1))+mask_i)] = 1'd0;
end
// assign ecc bits to temp variables to avoid
// sim warnings. Not all the 64 bits of the fifo
// are used in ECC mode.
assign mask_data_in_ecc_wire[((2*DQ_WIDTH)/8)-1:0] = mask_data_in_ecc;
assign mask_data_in_ecc_wire[63:((2*DQ_WIDTH)/8)] =
{(64-((2*DQ_WIDTH)/8)){1'b0}};
assign i_wdf_mask_data_out_ecc =
i_wdf_mask_data_out_ecc_wire[((2*DQ_WIDTH)/8)-1:0];
FIFO36_72 #
(
.ALMOST_EMPTY_OFFSET (9'h007),
.ALMOST_FULL_OFFSET (9'h00F),
.DO_REG (1), // extra CC output delay
.EN_ECC_WRITE ("TRUE"),
.EN_ECC_READ ("FALSE"),
.EN_SYN ("FALSE"),
.FIRST_WORD_FALL_THROUGH ("FALSE")
)
u_wdf_ecc_mask
(
.ALMOSTEMPTY (),
.ALMOSTFULL (),
.DBITERR (),
.DO (i_wdf_mask_data_out_ecc_wire),
.DOP (),
.ECCPARITY (),
.EMPTY (),
.FULL (),
.RDCOUNT (),
.RDERR (),
.SBITERR (),
.WRCOUNT (),
.WRERR (),
.DI (mask_data_in_ecc_wire),
.DIP (),
.RDCLK (clk90),
.RDEN (wdf_rden),
.RST (rst_r), // or can use rst0
.WRCLK (clk0),
.WREN (app_wdf_wren)
);
end else begin
//***********************************************************************
// Define intermediate buses:
assign i_wdf_data_rise_in
= app_wdf_data[DQ_WIDTH-1:0];
assign i_wdf_data_fall_in
= app_wdf_data[(2*DQ_WIDTH)-1:DQ_WIDTH];
assign i_wdf_mask_data_rise_in
= app_wdf_mask_data[MASK_WIDTH-1:0];
assign i_wdf_mask_data_fall_in
= app_wdf_mask_data[(2*MASK_WIDTH)-1:MASK_WIDTH];
//***********************************************************************
// Write data FIFO Input:
// Arrange DQ's so that the rise data and fall data are interleaved.
// the data arrives at the input of the wdf fifo as {fall,rise}.
// It is remapped as:
// {...fall[15:8],rise[15:8],fall[7:0],rise[7:0]}
// This is done to avoid having separate fifo's for rise and fall data
// and to keep rise/fall data for the same DQ's on same FIFO
// Data masks are interleaved in a similar manner
// NOTE: Initialization data from PHY_INIT module does not need to be
// interleaved - it's already in the correct format - and the same
// initialization pattern from PHY_INIT is sent to all write FIFOs
//***********************************************************************
for (wdf_di_i = 0; wdf_di_i < MASK_WIDTH;
wdf_di_i = wdf_di_i + 1) begin: gen_wdf_data_in
assign i_wdf_data_in[(16*wdf_di_i)+15:(16*wdf_di_i)]
= {i_wdf_data_fall_in[(8*wdf_di_i)+7:(8*wdf_di_i)],
i_wdf_data_rise_in[(8*wdf_di_i)+7:(8*wdf_di_i)]};
assign i_wdf_mask_data_in[(2*wdf_di_i)+1:(2*wdf_di_i)]
= {i_wdf_mask_data_fall_in[wdf_di_i],
i_wdf_mask_data_rise_in[wdf_di_i]};
end
//***********************************************************************
// Write data FIFO Output:
// FIFO DQ and mask outputs must be untangled and put in the standard
// format of {fall,rise}. Same goes for mask output
//***********************************************************************
for (wdf_do_i = 0; wdf_do_i < MASK_WIDTH;
wdf_do_i = wdf_do_i + 1) begin: gen_wdf_data_out
assign i_wdf_data_rise_out[(8*wdf_do_i)+7:(8*wdf_do_i)]
= i_wdf_data_out[(16*wdf_do_i)+7:(16*wdf_do_i)];
assign i_wdf_data_fall_out[(8*wdf_do_i)+7:(8*wdf_do_i)]
= i_wdf_data_out[(16*wdf_do_i)+15:(16*wdf_do_i)+8];
assign i_wdf_mask_data_rise_out[wdf_do_i]
= i_wdf_mask_data_out[2*wdf_do_i];
assign i_wdf_mask_data_fall_out[wdf_do_i]
= i_wdf_mask_data_out[(2*wdf_do_i)+1];
end
assign wdf_data = {i_wdf_data_fall_out,
i_wdf_data_rise_out};
assign wdf_mask_data = {i_wdf_mask_data_fall_out,
i_wdf_mask_data_rise_out};
//***********************************************************************
for (wdf_i = 0; wdf_i < WDF_FIFO_NUM; wdf_i = wdf_i + 1) begin: gen_wdf
FIFO36_72 #
(
.ALMOST_EMPTY_OFFSET (9'h007),
.ALMOST_FULL_OFFSET (9'h00F),
.DO_REG (1), // extra CC output delay
.EN_ECC_WRITE ("FALSE"),
.EN_ECC_READ ("FALSE"),
.EN_SYN ("FALSE"),
.FIRST_WORD_FALL_THROUGH ("FALSE")
)
u_wdf
(
.ALMOSTEMPTY (),
.ALMOSTFULL (i_wdf_afull[wdf_i]),
.DBITERR (),
.DO (i_wdf_data_out[(64*(wdf_i+1))-1:64*wdf_i]),
.DOP (i_wdf_mask_data_out[(8*(wdf_i+1))-1:8*wdf_i]),
.ECCPARITY (),
.EMPTY (),
.FULL (),
.RDCOUNT (),
.RDERR (),
.SBITERR (),
.WRCOUNT (),
.WRERR (),
.DI (i_wdf_data_in[(64*(wdf_i+1))-1:64*wdf_i]),
.DIP (i_wdf_mask_data_in[(8*(wdf_i+1))-1:8*wdf_i]),
.RDCLK (clk90),
.RDEN (wdf_rden),
.RST (rst_r), // or can use rst0
.WRCLK (clk0),
.WREN (app_wdf_wren)
);
end
end
endgenerate
endmodule
|
/*
$10 - RW 0000RPPP
$11 - RW 0 | 0 | 0 | 0 |ROD|RAD|BLK|RLK
R - RW RAM pages enable
PPP - RW Page number
ROD - RW Disable builtin ROM (enabled on reset/power on)
RAD - RW Disable BuiltIn RAM (disabled on reset/power on)
SLK - RW Disable write to sysboot aream (mapped external ram)
RLK - RW Disable write to RAM pages
*/
module pagesel (
input wire clk,
input wire rst,
input wire AD,
input wire [7:0] DI,
output reg [7:0] DO,
input wire rw,
input wire cs,
output reg [3:0] page,
output reg rampage_lock,
output reg sysboot_lock,
output reg bram_disable,
output reg brom_disable
);
always @ (posedge clk) begin
if (rst) begin
page <= 4'b0000;
rampage_lock <= 0;
sysboot_lock <= 0;
bram_disable <= 1;
brom_disable <= 0;
end else begin
if (cs) begin
if (rw) begin
if (AD) DO[3:0] <= {brom_disable, bram_disable, sysboot_lock, rampage_lock};
else DO[3:0] <= page;
end else begin
if (AD) begin
rampage_lock <= DI[0];
sysboot_lock <= DI[1];
bram_disable <= DI[2];
brom_disable <= DI[3];
end else page <= DI[3:0];
end
end
end
end
endmodule
|
/**
* bsg_cache_non_blocking_mhu.v
*
* Miss Handling Unit.
*
* @author tommy
*
*/
`include "bsg_defines.v"
module bsg_cache_non_blocking_mhu
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(id_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(ways_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p)
, parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p)
, parameter lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p)
, parameter byte_sel_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)
, parameter tag_width_lp=(addr_width_p-lg_sets_lp-lg_block_size_in_words_lp-byte_sel_width_lp)
, parameter data_mem_pkt_width_lp=
`bsg_cache_non_blocking_data_mem_pkt_width(ways_p,sets_p,block_size_in_words_p,data_width_p)
, parameter stat_mem_pkt_width_lp=
`bsg_cache_non_blocking_stat_mem_pkt_width(ways_p,sets_p)
, parameter tag_mem_pkt_width_lp=
`bsg_cache_non_blocking_tag_mem_pkt_width(ways_p,sets_p,data_width_p,tag_width_lp)
, parameter miss_fifo_entry_width_lp=
`bsg_cache_non_blocking_miss_fifo_entry_width(id_width_p,addr_width_p,data_width_p)
, parameter dma_cmd_width_lp=
`bsg_cache_non_blocking_dma_cmd_width(ways_p,sets_p,tag_width_lp)
)
(
input clk_i
, input reset_i
// cache management interface
, input mgmt_v_i
, output logic mgmt_yumi_o
, output logic mgmt_data_v_o
, output logic [data_width_p-1:0] mgmt_data_o
, output logic [id_width_p-1:0] mgmt_id_o
, input mgmt_data_yumi_i
, input bsg_cache_non_blocking_decode_s decode_tl_i
, input [addr_width_p-1:0] addr_tl_i
, input [id_width_p-1:0] id_tl_i
, output logic idle_o
, output logic recover_o
, input tl_block_loading_i
// data_mem
, output logic data_mem_pkt_v_o
, output logic [data_mem_pkt_width_lp-1:0] data_mem_pkt_o
, output logic [id_width_p-1:0] data_mem_pkt_id_o
, input data_mem_pkt_yumi_i
// stat_mem
, output logic stat_mem_pkt_v_o
, output logic [stat_mem_pkt_width_lp-1:0] stat_mem_pkt_o
, input [ways_p-1:0] dirty_i
, input [ways_p-2:0] lru_bits_i
// tag_mem
, output logic tag_mem_pkt_v_o
, output logic [tag_mem_pkt_width_lp-1:0] tag_mem_pkt_o
, input [ways_p-1:0] valid_tl_i
, input [ways_p-1:0] lock_tl_i
, input [ways_p-1:0][tag_width_lp-1:0] tag_tl_i
, input [lg_ways_lp-1:0] tag_hit_way_i
, input tag_hit_found_i
, output logic [lg_ways_lp-1:0] curr_mhu_way_id_o
, output logic [lg_sets_lp-1:0] curr_mhu_index_o
, output logic curr_mhu_v_o
// miss FIFO
, input miss_fifo_v_i
, input [miss_fifo_entry_width_lp-1:0] miss_fifo_entry_i
, output logic miss_fifo_yumi_o
, output bsg_cache_non_blocking_miss_fifo_op_e miss_fifo_yumi_op_o
, output logic miss_fifo_scan_not_dq_o
, output logic miss_fifo_rollback_o
, input miss_fifo_empty_i
// DMA
, output logic [dma_cmd_width_lp-1:0] dma_cmd_o
, output logic dma_cmd_v_o
, input [dma_cmd_width_lp-1:0] dma_cmd_return_i
, input dma_done_i
, input dma_pending_i
, output logic dma_ack_o
);
// localparam
//
localparam block_offset_width_lp = lg_block_size_in_words_lp+byte_sel_width_lp;
localparam mhu_dff_width_lp = `bsg_cache_non_blocking_mhu_dff_width(id_width_p,addr_width_p,tag_width_lp,ways_p);
// declare structs
//
`declare_bsg_cache_non_blocking_data_mem_pkt_s(ways_p,sets_p,block_size_in_words_p,data_width_p);
`declare_bsg_cache_non_blocking_stat_mem_pkt_s(ways_p,sets_p);
`declare_bsg_cache_non_blocking_tag_mem_pkt_s(ways_p,sets_p,data_width_p,tag_width_lp);
`declare_bsg_cache_non_blocking_miss_fifo_entry_s(id_width_p,addr_width_p,data_width_p);
`declare_bsg_cache_non_blocking_dma_cmd_s(ways_p,sets_p,tag_width_lp);
bsg_cache_non_blocking_data_mem_pkt_s data_mem_pkt;
bsg_cache_non_blocking_stat_mem_pkt_s stat_mem_pkt;
bsg_cache_non_blocking_tag_mem_pkt_s tag_mem_pkt;
bsg_cache_non_blocking_miss_fifo_entry_s miss_fifo_entry;
bsg_cache_non_blocking_dma_cmd_s dma_cmd_out, dma_cmd_return;
assign data_mem_pkt_o = data_mem_pkt;
assign stat_mem_pkt_o = stat_mem_pkt;
assign tag_mem_pkt_o = tag_mem_pkt;
assign miss_fifo_entry = miss_fifo_entry_i;
assign dma_cmd_o = dma_cmd_out;
assign dma_cmd_return = dma_cmd_return_i;
// mhu_state
//
mhu_state_e mhu_state_r;
mhu_state_e mhu_state_n;
// During DQ or SCAN mode, when secondary store is encountered, this flop is
// set to one. Later, when the stat_mem is being updated, set the dirty bit
// if this is 1'b1.
logic set_dirty_n, set_dirty_r;
// MHU flops
//
`declare_bsg_cache_non_blocking_mhu_dff_s(id_width_p,addr_width_p,tag_width_lp,ways_p);
bsg_cache_non_blocking_mhu_dff_s mhu_dff_r;
bsg_cache_non_blocking_mhu_dff_s mhu_dff_n;
logic mhu_dff_en;
bsg_dff_reset_en #(
.width_p(mhu_dff_width_lp)
,.reset_val_p(0)
) mhu_dff (
.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(mhu_dff_en)
,.data_i(mhu_dff_n)
,.data_o(mhu_dff_r)
);
assign mhu_dff_n = '{
decode : decode_tl_i,
valid : valid_tl_i,
lock : lock_tl_i,
tag : tag_tl_i,
tag_hit_way : tag_hit_way_i,
tag_hit_found : tag_hit_found_i,
id : id_tl_i,
addr : addr_tl_i
};
wire [lg_ways_lp-1:0] addr_way_mhu = mhu_dff_r.addr[block_offset_width_lp+lg_sets_lp+:lg_ways_lp];
wire [tag_width_lp-1:0] addr_tag_mhu = mhu_dff_r.addr[block_offset_width_lp+lg_sets_lp+:tag_width_lp];
wire [lg_sets_lp-1:0] addr_index_mhu = mhu_dff_r.addr[block_offset_width_lp+:lg_sets_lp];
// current dma_cmd
//
bsg_cache_non_blocking_dma_cmd_s curr_dma_cmd_r;
bsg_cache_non_blocking_dma_cmd_s curr_dma_cmd_n;
logic curr_dma_cmd_v_r, curr_dma_cmd_v_n;
logic [tag_width_lp-1:0] curr_miss_tag;
logic [lg_sets_lp-1:0] curr_miss_index;
logic [tag_width_lp-1:0] miss_fifo_tag;
logic [lg_sets_lp-1:0] miss_fifo_index;
logic is_secondary;
assign curr_miss_tag = curr_dma_cmd_r.refill_tag;
assign curr_miss_index = curr_dma_cmd_r.index;
assign miss_fifo_tag = miss_fifo_entry.addr[block_offset_width_lp+lg_sets_lp+:tag_width_lp];
assign miss_fifo_index = miss_fifo_entry.addr[block_offset_width_lp+:lg_sets_lp];
assign is_secondary = (curr_miss_tag == miss_fifo_tag) & (curr_miss_index == miss_fifo_index);
assign curr_mhu_v_o = curr_dma_cmd_v_r;
assign curr_mhu_index_o = curr_dma_cmd_r.index;
assign curr_mhu_way_id_o = curr_dma_cmd_r.way_id;
// Replacement Policy
//
// Try to find a way that is invalid and unlocked. There could be a way that is
// invalid in tag_mem, BUT has a pending DMA request on it. Those are
// considered to be NOT invalid.
// If invalid does not exist, pick the LRU. It is also possible that the LRU
// way has a pending DMA request, or it is locked. In such occasion, resort
// to the backup LRU.
logic invalid_exist;
logic [lg_ways_lp-1:0] invalid_way_id;
logic [lg_ways_lp-1:0] backup_lru_way_id;
logic [lg_ways_lp-1:0] replacement_way_id;
logic [ways_p-1:0] curr_miss_way_decode;
logic [ways_p-1:0] disabled_ways;
wire next_miss_index_match = curr_dma_cmd_v_r & (curr_dma_cmd_r.index == miss_fifo_index);
bsg_decode_with_v #(
.num_out_p(ways_p)
) curr_miss_way_demux (
.i(curr_dma_cmd_r.way_id)
,.v_i(next_miss_index_match)
,.o(curr_miss_way_decode)
);
bsg_priority_encode #(
.width_p(ways_p)
,.lo_to_hi_p(1)
) invalid_way_pe (
.i(~mhu_dff_r.valid & ~mhu_dff_r.lock & ~curr_miss_way_decode) // invalid and unlocked + not current miss
,.addr_o(invalid_way_id)
,.v_o(invalid_exist)
);
assign disabled_ways = mhu_dff_r.lock | curr_miss_way_decode;
logic [ways_p-2:0] modify_data_lo;
logic [ways_p-2:0] modify_mask_lo;
logic [ways_p-2:0] modified_lru_bits;
bsg_lru_pseudo_tree_backup #(
.ways_p(ways_p)
) lru_backup (
.disabled_ways_i(disabled_ways)
,.modify_data_o(modify_data_lo)
,.modify_mask_o(modify_mask_lo)
);
bsg_mux_bitwise #(
.width_p(ways_p-1)
) mux (
.data0_i(lru_bits_i)
,.data1_i(modify_data_lo)
,.sel_i(modify_mask_lo)
,.data_o(modified_lru_bits)
);
bsg_lru_pseudo_tree_encode #(
.ways_p(ways_p)
) lru_encode (
.lru_i(modified_lru_bits)
,.way_id_o(backup_lru_way_id)
);
assign replacement_way_id = invalid_exist
? invalid_way_id
: backup_lru_way_id;
logic replacement_dirty;
logic replacement_valid;
logic [tag_width_lp-1:0] replacement_tag;
assign replacement_dirty = dirty_i[replacement_way_id];
assign replacement_valid = mhu_dff_r.valid[replacement_way_id];
assign replacement_tag = mhu_dff_r.tag[replacement_way_id];
// block load counter
//
logic counter_clear;
logic counter_up;
logic [lg_block_size_in_words_lp-1:0] counter_r;
logic counter_max;
bsg_counter_clear_up #(
.max_val_p(block_size_in_words_p-1)
,.init_val_p(0)
) block_ld_counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(counter_clear)
,.up_i(counter_up)
,.count_o(counter_r)
);
assign counter_max = counter_r == (block_size_in_words_p-1);
// FSM
//
always_comb begin
mhu_state_n = mhu_state_r;
curr_dma_cmd_n = curr_dma_cmd_r;
curr_dma_cmd_v_n = curr_dma_cmd_v_r;
set_dirty_n = set_dirty_r;
mhu_dff_en = 1'b0;
idle_o = 1'b0;
recover_o = 1'b0;
mgmt_yumi_o = 1'b0;
mgmt_data_o = '0;
mgmt_data_v_o = 1'b0;
mgmt_id_o = mhu_dff_r.id;
data_mem_pkt_v_o = 1'b0;
data_mem_pkt.write_not_read = miss_fifo_entry.write_not_read;
data_mem_pkt_id_o = miss_fifo_entry.id;
data_mem_pkt.way_id = curr_dma_cmd_r.way_id;
data_mem_pkt.addr = miss_fifo_entry.block_load
? {curr_miss_index, counter_r}
: {curr_miss_index, miss_fifo_entry.addr[byte_sel_width_lp+:lg_block_size_in_words_lp]};
data_mem_pkt.sigext_op = miss_fifo_entry.sigext_op;
data_mem_pkt.size_op = miss_fifo_entry.block_load
? (2)'($clog2(data_width_p>>3))
: miss_fifo_entry.size_op;
data_mem_pkt.byte_sel = miss_fifo_entry.block_load
? {byte_sel_width_lp{1'b0}}
: miss_fifo_entry.addr[0+:byte_sel_width_lp];
data_mem_pkt.data = miss_fifo_entry.data;
data_mem_pkt.mask = miss_fifo_entry.mask;
data_mem_pkt.mask_op = miss_fifo_entry.mask_op;
stat_mem_pkt_v_o = 1'b0;
stat_mem_pkt = '0;
tag_mem_pkt_v_o = 1'b0;
tag_mem_pkt = '0;
dma_cmd_v_o = 1'b0;
dma_cmd_out = '0;
dma_ack_o = 1'b0;
miss_fifo_yumi_o = 1'b0;
miss_fifo_yumi_op_o = e_miss_fifo_dequeue;
miss_fifo_rollback_o = 1'b0;
miss_fifo_scan_not_dq_o = 1'b0;
counter_clear = 1'b0;
counter_up = 1'b0;
case (mhu_state_r)
// When MHU is idle, and there is no pending miss, cache management op may come in.
// Or MHU has just returned from completing the previous cache miss.
// For the cache mgmt op that requires data_eviction, it reads the
// stat_mem for dirty bits, as it moves to SEND_MGMT_DMA.
// There could be a pending DMA transaction, or it has already
// completed (dma_pending_i, dma_pending_o).
// Switch to WAIT_DMA_DONE in that case. Or wait for the miss FIFO to
// have a valid output.
MHU_IDLE: begin
// Flop the necesssary data coming from tl stage, and go to MGMT_OP.
if (mgmt_v_i) begin
mhu_dff_en = 1'b1;
mhu_state_n = MGMT_OP;
end
// Go to WAIT_DMA_DONE to wait for a DMA request that was previous
// sent out while transitioning out of DQ mode.
else if (dma_pending_i | dma_done_i) begin
mhu_state_n = WAIT_DMA_DONE;
end
// Wait for miss FIFO output to be valid.
// When TL block loading is in progress, then wait for it to finish.
else begin
idle_o = miss_fifo_empty_i;
tag_mem_pkt_v_o = miss_fifo_v_i;
tag_mem_pkt.index = miss_fifo_index;
tag_mem_pkt.opcode = e_tag_read;
stat_mem_pkt_v_o = miss_fifo_v_i;
stat_mem_pkt.index = miss_fifo_index;
stat_mem_pkt.opcode = e_stat_read;
mhu_state_n = (miss_fifo_v_i & ~tl_block_loading_i)
? READ_TAG1
: MHU_IDLE;
end
end
// MGMT OP
MGMT_OP: begin
mgmt_data_o = '0;
stat_mem_pkt.index = addr_index_mhu;
tag_mem_pkt.index = addr_index_mhu;
// TAGLA: return the tag address at the output.
if (mhu_dff_r.decode.tagla_op) begin
mgmt_yumi_o = mgmt_data_yumi_i;
mgmt_data_o = {mhu_dff_r.tag[addr_way_mhu], addr_index_mhu, {block_offset_width_lp{1'b0}}};
mgmt_data_v_o = 1'b1;
mhu_state_n = mgmt_data_yumi_i
? MHU_IDLE
: MGMT_OP;
end
// TAGLV: return the tag valid and lock bit at the output.
else if (mhu_dff_r.decode.taglv_op) begin
mgmt_yumi_o = mgmt_data_yumi_i;
mgmt_data_o = {{(data_width_p-2){1'b0}}, mhu_dff_r.lock[addr_way_mhu], mhu_dff_r.valid[addr_way_mhu]};
mgmt_data_v_o = 1'b1;
mhu_state_n = mgmt_data_yumi_i
? MHU_IDLE
: MGMT_OP;
end
// TAGST: also clears the stat_mem (dirty/LRU bits).
else if (mhu_dff_r.decode.tagst_op) begin
mgmt_yumi_o = mgmt_data_yumi_i;
mgmt_data_v_o = 1'b1;
stat_mem_pkt_v_o = mgmt_data_yumi_i;
stat_mem_pkt.opcode = e_stat_reset;
stat_mem_pkt.way_id = addr_way_mhu;
mhu_state_n = mgmt_data_yumi_i
? MHU_IDLE
: MGMT_OP;
end
// TAGFL:
// if the cache line is valid, read stat_mem to check dirty bit.
// otherwise, return 0;
else if (mhu_dff_r.decode.tagfl_op) begin
mgmt_yumi_o = ~mhu_dff_r.valid[addr_way_mhu] & mgmt_data_yumi_i;
mgmt_data_v_o = ~mhu_dff_r.valid[addr_way_mhu];
stat_mem_pkt_v_o = mhu_dff_r.valid[addr_way_mhu];
stat_mem_pkt.opcode = e_stat_read;
mhu_state_n = mhu_dff_r.valid[addr_way_mhu]
? SEND_MGMT_DMA
: MHU_IDLE;
end
// AFL/AFLINV:
// If there is tag hit, it reads the stat_mem.
// otherwise, return 0;
else if (mhu_dff_r.decode.afl_op | mhu_dff_r.decode.aflinv_op) begin
mgmt_yumi_o = ~mhu_dff_r.tag_hit_found & mgmt_data_yumi_i;
mgmt_data_v_o = ~mhu_dff_r.tag_hit_found;
stat_mem_pkt_v_o = mhu_dff_r.tag_hit_found;
stat_mem_pkt.opcode = e_stat_read;
mhu_state_n = mhu_dff_r.tag_hit_found
? SEND_MGMT_DMA
: MHU_IDLE;
end
// AINV: If there is tag hit, invalidate the cache line.
else if (mhu_dff_r.decode.ainv_op) begin
mgmt_yumi_o = mgmt_data_yumi_i;
mgmt_data_v_o = 1'b1;
stat_mem_pkt_v_o = mhu_dff_r.tag_hit_found;
stat_mem_pkt.way_id = mhu_dff_r.tag_hit_way;
stat_mem_pkt.opcode = e_stat_clear_dirty;
tag_mem_pkt_v_o = mhu_dff_r.tag_hit_found;
tag_mem_pkt.way_id = mhu_dff_r.tag_hit_way;
tag_mem_pkt.opcode = e_tag_invalidate;
mhu_state_n = mgmt_data_yumi_i
? MHU_IDLE
: MGMT_OP;
end
// ALOCK: if there is tag hit, then lock the line.
// If not, read stat_mem and send mgmt DMA.
else if (mhu_dff_r.decode.alock_op) begin
mgmt_yumi_o = mhu_dff_r.tag_hit_found & mgmt_data_yumi_i;
mgmt_data_v_o = mhu_dff_r.tag_hit_found;
stat_mem_pkt_v_o = ~mhu_dff_r.tag_hit_found;
stat_mem_pkt.opcode = e_stat_read;
tag_mem_pkt_v_o = mhu_dff_r.tag_hit_found & mgmt_data_yumi_i;
tag_mem_pkt.way_id = mhu_dff_r.tag_hit_way;
tag_mem_pkt.opcode = e_tag_lock;
mhu_state_n = mhu_dff_r.tag_hit_found
? (mgmt_data_yumi_i ? MHU_IDLE : MGMT_OP)
: SEND_MGMT_DMA;
end
// AUNLOCK: if there is tag hit, then unlock the line.
else if (mhu_dff_r.decode.aunlock_op) begin
mgmt_yumi_o = mgmt_data_yumi_i;
mgmt_data_v_o = 1'b1;
tag_mem_pkt_v_o = mhu_dff_r.tag_hit_found & mgmt_data_yumi_i;
tag_mem_pkt.way_id = mhu_dff_r.tag_hit_way;
tag_mem_pkt.opcode = e_tag_unlock;
mhu_state_n = mgmt_data_yumi_i
? MHU_IDLE
: MGMT_OP;
end
else begin
// This would never happen by design.
// Do nothing.
end
end
// Sending DMA for TAGFL,AFL,AFLINV,ALOCK.
// For TAGFL,AFL,AFLINV, if the block is dirty, then send out the dma
// cmd. Otherwise, return 0;
// For ALOCK, always send the dma cmd to bring in the missing block.
SEND_MGMT_DMA: begin
dma_cmd_v_o = mhu_dff_r.decode.alock_op
? 1'b1
: (mhu_dff_r.decode.tagfl_op
? dirty_i[addr_way_mhu]
: dirty_i[mhu_dff_r.tag_hit_way]);
dma_cmd_out.way_id = mhu_dff_r.decode.alock_op
? replacement_way_id
: (mhu_dff_r.decode.tagfl_op
? addr_way_mhu
: mhu_dff_r.tag_hit_way);
dma_cmd_out.index = addr_index_mhu;
dma_cmd_out.refill = mhu_dff_r.decode.alock_op;
dma_cmd_out.refill_tag = addr_tag_mhu; // don't care for flush ops.
dma_cmd_out.evict = mhu_dff_r.decode.alock_op
? (replacement_dirty & replacement_valid)
: 1'b1;
dma_cmd_out.evict_tag = mhu_dff_r.decode.alock_op
? replacement_tag
: (mhu_dff_r.decode.tagfl_op
? mhu_dff_r.tag[addr_way_mhu]
: mhu_dff_r.tag[mhu_dff_r.tag_hit_way]);
mgmt_yumi_o = mgmt_data_yumi_i
& ~mhu_dff_r.decode.alock_op
& (mhu_dff_r.decode.tagfl_op
? ~dirty_i[addr_way_mhu]
: ~dirty_i[mhu_dff_r.tag_hit_way]);
mgmt_data_v_o = ~mhu_dff_r.decode.alock_op
& (mhu_dff_r.decode.tagfl_op
? ~dirty_i[addr_way_mhu]
: ~dirty_i[mhu_dff_r.tag_hit_way]);
tag_mem_pkt_v_o = mgmt_data_yumi_i & mhu_dff_r.decode.aflinv_op & ~dirty_i[mhu_dff_r.tag_hit_way];
tag_mem_pkt.way_id = mhu_dff_r.tag_hit_way;
tag_mem_pkt.index = addr_index_mhu;
tag_mem_pkt.opcode = e_tag_invalidate;
mhu_state_n = mhu_dff_r.decode.alock_op
? WAIT_MGMT_DMA
: (mhu_dff_r.decode.tagfl_op
? (dirty_i[addr_way_mhu]
? WAIT_MGMT_DMA
: (mgmt_data_yumi_i ? MHU_IDLE : SEND_MGMT_DMA))
: (dirty_i[mhu_dff_r.tag_hit_way]
? WAIT_MGMT_DMA
: (mgmt_data_yumi_i ? MHU_IDLE : SEND_MGMT_DMA)));
end
// Waiting DMA for TAGFL,AFL,AFLINV,ALOCK.
WAIT_MGMT_DMA: begin
mgmt_yumi_o = mgmt_data_yumi_i;
stat_mem_pkt_v_o = dma_done_i & mgmt_data_yumi_i;
stat_mem_pkt.index = addr_index_mhu;
stat_mem_pkt.way_id = mhu_dff_r.decode.tagfl_op
? addr_way_mhu
: (mhu_dff_r.decode.alock_op
? replacement_way_id
: mhu_dff_r.tag_hit_way);
stat_mem_pkt.opcode = e_stat_clear_dirty;
tag_mem_pkt_v_o = mgmt_data_yumi_i & dma_done_i & (mhu_dff_r.decode.alock_op | mhu_dff_r.decode.aflinv_op);
tag_mem_pkt.way_id = mhu_dff_r.decode.alock_op
? replacement_way_id
: mhu_dff_r.tag_hit_way;
tag_mem_pkt.index = addr_index_mhu;
tag_mem_pkt.tag = addr_tag_mhu; // dont care for AFLINV.
tag_mem_pkt.opcode = mhu_dff_r.decode.alock_op
? e_tag_set_tag_and_lock
: e_tag_invalidate;
dma_ack_o = mgmt_data_yumi_i;
mgmt_data_v_o = dma_done_i;
mhu_state_n = (dma_done_i & mgmt_data_yumi_i)
? MHU_IDLE
: WAIT_MGMT_DMA;
end
// READ TAG1
READ_TAG1: begin
mhu_dff_en = 1'b1;
recover_o = 1'b1;
mhu_state_n = SEND_DMA_REQ1;
end
// sending DMA request for the first primary miss.
// This recover may seem redundant, but we want to stall TL until the
// dma_cmd has been sent out.
SEND_DMA_REQ1: begin
recover_o = 1'b1;
dma_cmd_v_o = 1'b1;
dma_cmd_out.way_id = replacement_way_id;
dma_cmd_out.index = miss_fifo_index;
dma_cmd_out.refill = 1'b1;
dma_cmd_out.evict = replacement_valid & replacement_dirty;
dma_cmd_out.refill_tag = miss_fifo_tag;
dma_cmd_out.evict_tag = replacement_tag;
mhu_state_n = WAIT_DMA_DONE;
end
// Wait for DMA to be done for load/store miss
// It might already be done.
WAIT_DMA_DONE: begin
dma_ack_o = dma_done_i;
curr_dma_cmd_n = dma_done_i
? dma_cmd_return
: curr_dma_cmd_r;
curr_dma_cmd_v_n = dma_done_i;
set_dirty_n = 1'b0;
counter_clear = 1'b1;
mhu_state_n = dma_done_i
? DEQUEUE_MODE
: WAIT_DMA_DONE;
end
// Dequeue and process secondary miss.
// When non-secondary is encounter, send out the next DMA.
// At this time, there is no pending DMA.
// If the FIFO is empty, then move to RECOVER, and update tag_and
// stat_mem.
// When the TL stage is block loading, we don't want to pause until it's
// over.
DEQUEUE_MODE: begin
data_mem_pkt_v_o = miss_fifo_v_i & is_secondary & ~tl_block_loading_i;
miss_fifo_yumi_o = data_mem_pkt_yumi_i
& (miss_fifo_entry.block_load
? counter_max
: 1'b1);
miss_fifo_yumi_op_o = e_miss_fifo_dequeue;
counter_up = data_mem_pkt_yumi_i
& miss_fifo_entry.block_load & ~counter_max;
counter_clear = data_mem_pkt_yumi_i
& miss_fifo_entry.block_load & counter_max;
stat_mem_pkt_v_o = ~tl_block_loading_i & (miss_fifo_empty_i | (miss_fifo_v_i & ~is_secondary));
stat_mem_pkt.way_id = curr_dma_cmd_r.way_id; // dont care for read
stat_mem_pkt.index = miss_fifo_empty_i
? curr_miss_index
: miss_fifo_index;
stat_mem_pkt.opcode = miss_fifo_empty_i // dont care for read
? (set_dirty_r
? e_stat_set_lru_and_dirty
: e_stat_set_lru_and_clear_dirty)
: e_stat_read;
tag_mem_pkt_v_o = ~tl_block_loading_i & (miss_fifo_empty_i | (miss_fifo_v_i & ~is_secondary));
tag_mem_pkt.way_id = curr_dma_cmd_r.way_id; // dont care for read
tag_mem_pkt.index = miss_fifo_empty_i
? curr_miss_index
: miss_fifo_index;
tag_mem_pkt.tag = curr_miss_tag; // dont care for read
tag_mem_pkt.opcode = miss_fifo_empty_i
? e_tag_set_tag
: e_tag_read;
set_dirty_n = set_dirty_r
? 1'b1
: data_mem_pkt_yumi_i & miss_fifo_entry.write_not_read;
mhu_state_n = tl_block_loading_i
? DEQUEUE_MODE
: (miss_fifo_empty_i
? RECOVER
: (miss_fifo_v_i
? (is_secondary ? DEQUEUE_MODE : READ_TAG2)
: DEQUEUE_MODE));
end
// READ TAG2
READ_TAG2: begin
mhu_dff_en = 1'b1;
recover_o = 1'b1;
mhu_state_n = SEND_DMA_REQ2;
end
// Send the DMA for the next miss.
// This recover may seem redundant, but we want to stall TL until the
// dma_cmd has been sent out.
SEND_DMA_REQ2: begin
recover_o = 1'b1;
dma_cmd_v_o = 1'b1;
dma_cmd_out.way_id = replacement_way_id;
dma_cmd_out.index = miss_fifo_index;
dma_cmd_out.refill = 1'b1;
dma_cmd_out.evict = replacement_dirty & replacement_valid;
dma_cmd_out.refill_tag = miss_fifo_tag;
dma_cmd_out.evict_tag = replacement_tag;
counter_clear = 1'b1;
mhu_state_n = SCAN_MODE;
end
// Scan for secondary misses, which is invalidated.
// non-secondary misses are skipped instead.
SCAN_MODE: begin
data_mem_pkt_v_o = miss_fifo_v_i & is_secondary & ~tl_block_loading_i;
miss_fifo_scan_not_dq_o = 1'b1;
miss_fifo_yumi_o = miss_fifo_v_i & (is_secondary
? (data_mem_pkt_yumi_i
& (miss_fifo_entry.block_load ? counter_max : 1'b1))
: 1'b1);
miss_fifo_yumi_op_o = is_secondary
? e_miss_fifo_invalidate
: e_miss_fifo_skip;
counter_up = data_mem_pkt_yumi_i
& miss_fifo_entry.block_load & ~counter_max;
counter_clear = data_mem_pkt_yumi_i
& miss_fifo_entry.block_load & counter_max;
stat_mem_pkt_v_o = miss_fifo_empty_i & ~tl_block_loading_i;
stat_mem_pkt.way_id = curr_dma_cmd_r.way_id;
stat_mem_pkt.index = curr_miss_index;
stat_mem_pkt.opcode = set_dirty_r
? e_stat_set_lru_and_dirty
: e_stat_set_lru_and_clear_dirty;
tag_mem_pkt_v_o = miss_fifo_empty_i & ~tl_block_loading_i;
tag_mem_pkt.way_id = curr_dma_cmd_r.way_id;
tag_mem_pkt.index = curr_miss_index;
tag_mem_pkt.tag = curr_miss_tag;
tag_mem_pkt.opcode = e_tag_set_tag;
set_dirty_n = set_dirty_r
? 1'b1
: data_mem_pkt_yumi_i & miss_fifo_entry.write_not_read;
mhu_state_n = tl_block_loading_i
? SCAN_MODE
: (miss_fifo_empty_i
? RECOVER
: SCAN_MODE);
end
// Recover
// TL stage will read the tag_mem.
RECOVER: begin
recover_o = 1'b1;
miss_fifo_rollback_o = 1'b1;
curr_dma_cmd_v_n = 1'b0;
mhu_state_n = MHU_IDLE;
end
// this should never happen.
default: begin
mhu_state_n = MHU_IDLE;
end
endcase
end
// synopsys sync_set_reset "reset_i"
always_ff @ (posedge clk_i) begin
if (reset_i) begin
mhu_state_r <= MHU_IDLE;
curr_dma_cmd_r <= '0;
curr_dma_cmd_v_r <= 1'b0;
set_dirty_r <= 1'b0;
end
else begin
mhu_state_r <= mhu_state_n;
curr_dma_cmd_r <= curr_dma_cmd_n;
curr_dma_cmd_v_r <= curr_dma_cmd_v_n;
set_dirty_r <= set_dirty_n;
end
end
// synopsys translate_off
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
if (dma_cmd_v_o)
assert(~mhu_dff_r.lock[replacement_way_id])
else $error("[BSG_ERROR] MHU cannot replace a locked way.");
if (mhu_state_r == MHU_IDLE & mgmt_v_i)
assert(~dma_done_i & ~dma_pending_i & ~miss_fifo_v_i)
else $error("[BSG_ERROR] cache management op cannot enter the pipeline, when there is a pending load/store miss");
end
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_non_blocking_mhu)
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