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//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module nukv_Predicate_Eval_Pipeline_v2 #(
parameter MEMORY_WIDTH = 512,
parameter META_WIDTH = 96,
parameter GENERATE_COMMANDS = 1,
parameter SUPPORT_SCANS = 0,
parameter PIPE_DEPTH = 1
)
(
// Clock
input wire clk,
input wire rst,
input wire [META_WIDTH+MEMORY_WIDTH-1:0] pred_data,
input wire pred_valid,
input wire pred_scan,
output wire pred_ready,
input wire [MEMORY_WIDTH-1:0] value_data,
input wire value_valid,
input wire value_last,
input wire value_drop,
output wire value_ready,
output wire [MEMORY_WIDTH-1:0] output_data,
output wire output_valid,
output wire output_last,
output wire output_drop,
input wire output_ready,
input scan_on_outside,
output wire cmd_valid,
output wire[15:0] cmd_length,
output wire[META_WIDTH-1:0] cmd_meta,
input wire cmd_ready,
output wire error_input
);
localparam MAX_DEPTH = 9;
wire[META_WIDTH+MEMORY_WIDTH-1:0] prarr_data [0:MAX_DEPTH-1];
wire[MAX_DEPTH-1:0] prarr_valid ;
wire[MAX_DEPTH-1:0] prarr_scan ;
wire[MAX_DEPTH-1:0] prarr_ready ;
wire[MAX_DEPTH-1:0] prarr_in_ready ;
wire [MEMORY_WIDTH-1:0] varr_data [0:MAX_DEPTH];
wire [MAX_DEPTH:0] varr_valid;
wire [MAX_DEPTH:0] varr_last;
wire [MAX_DEPTH:0] varr_drop;
wire [MAX_DEPTH:0] varr_ready;
assign varr_data[0] = value_data;
assign varr_valid[0] = value_valid;
assign varr_last[0] = value_last;
assign varr_drop[0] = value_drop;
assign value_ready = varr_ready[0];
assign output_data = varr_data[MAX_DEPTH];
assign output_valid = varr_valid[MAX_DEPTH];
assign output_last = varr_last[MAX_DEPTH];
assign output_drop = varr_drop[MAX_DEPTH];
assign varr_ready[MAX_DEPTH] = output_ready;
assign pred_ready = &prarr_in_ready;
generate
genvar i;
for (i=0; i<MAX_DEPTH; i=i+1) begin
if (i<PIPE_DEPTH-1) begin
nukv_fifogen #(
.DATA_SIZE(48+96+1),
.ADDR_BITS(7)
) fifo_predconfig (
.clk(clk),
.rst(rst),
.s_axis_tdata({pred_data[META_WIDTH+i*48 +: 48],pred_data[META_WIDTH-1:0], pred_scan}),
.s_axis_tvalid(pred_valid & pred_ready),
.s_axis_tready(prarr_in_ready[i]),
.m_axis_tdata({prarr_data[i],prarr_scan[i]}),
.m_axis_tvalid(prarr_valid[i]),
.m_axis_tready(prarr_ready[i])
);
nukv_Predicate_Eval #(.SUPPORT_SCANS(SUPPORT_SCANS))
pred_eval
(
.clk(clk),
.rst(rst),
.pred_data(prarr_data[i]),
.pred_valid(prarr_valid[i]),
.pred_ready(prarr_ready[i]),
.pred_scan((SUPPORT_SCANS==1) ? prarr_scan[i] : 0),
.value_data(varr_data[i]),
.value_last(varr_last[i]),
.value_drop(varr_drop[i]),
.value_valid(varr_valid[i]),
.value_ready(varr_ready[i]),
.output_valid(varr_valid[i+1]),
.output_ready(varr_ready[i+1]),
.output_data(varr_data[i+1]),
.output_last(varr_last[i+1]),
.output_drop(varr_drop[i+1]),
.scan_on_outside(scan_on_outside)
);
end else if (i==PIPE_DEPTH-1) begin
nukv_fifogen #(
.DATA_SIZE(48+96+1),
.ADDR_BITS(7)
) fifo_predconfig (
.clk(clk),
.rst(rst),
.s_axis_tdata({pred_data[META_WIDTH+i*48 +: 48],pred_data[META_WIDTH-1:0], pred_scan}),
.s_axis_tvalid(pred_valid & pred_ready),
.s_axis_tready(prarr_in_ready[i]),
.m_axis_tdata({prarr_data[i],prarr_scan[i]}),
.m_axis_tvalid(prarr_valid[i]),
.m_axis_tready(prarr_ready[i])
);
nukv_Predicate_Eval #(.SUPPORT_SCANS(SUPPORT_SCANS))
pred_eval
(
.clk(clk),
.rst(rst),
.pred_data(prarr_data[i]),
.pred_valid(prarr_valid[i]),
.pred_ready(prarr_ready[i]),
.pred_scan((SUPPORT_SCANS==1) ? prarr_scan[i] : 0),
.value_data(varr_data[i]),
.value_last(varr_last[i]),
.value_drop(varr_drop[i]),
.value_valid(varr_valid[i]),
.value_ready(varr_ready[i]),
.output_valid(varr_valid[i+1]),
.output_ready(varr_ready[i+1]),
.output_data(varr_data[i+1]),
.output_last(varr_last[i+1]),
.output_drop(varr_drop[i+1]),
.scan_on_outside(scan_on_outside),
.error_input (error_input),
.cmd_valid (cmd_valid),
.cmd_length (cmd_length),
.cmd_meta (cmd_meta),
.cmd_ready (cmd_ready)
);
end else begin
assign prarr_in_ready[i] = 1;
assign varr_data[i+1] = varr_data[i];
assign varr_valid[i+1] = varr_valid[i];
assign varr_last[i+1] = varr_last[i];
assign varr_drop[i+1] = varr_drop[i];
assign varr_ready[i] = varr_ready[i+1];
end
end
endgenerate
endmodule |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
// Date : Tue Oct 4 21:22:12 2016
// Host : jorge-pc running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file
// /home/jorge/Documents/Karatsuba_FPU/Resultados/CORDIC/CORDIC_Arch3_Vivado/CORDIC_Arch3_Vivado.sim/tb_CORDIC_Arch3_single/synth/timing/testbench_CORDIC_Arch3_time_synth.v
// Design : CORDIC_Arch3
// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or
// synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING
(* EW = "8" *) (* EWR = "5" *) (* SW = "23" *)
(* SWR = "26" *) (* W = "32" *) (* iter_bits = "4" *)
(* mode = "1'b0" *)
(* NotValidForBitStream *)
module CORDIC_Arch3
(clk,
rst,
beg_fsm_cordic,
ack_cordic,
operation,
data_in,
shift_region_flag,
ready_cordic,
overflow_flag,
underflow_flag,
zero_flag,
busy,
data_output);
input clk;
input rst;
input beg_fsm_cordic;
input ack_cordic;
input operation;
input [31:0]data_in;
input [1:0]shift_region_flag;
output ready_cordic;
output overflow_flag;
output underflow_flag;
output zero_flag;
output busy;
output [31:0]data_output;
wire [7:0]A;
wire ITER_CONT_n_10;
wire ITER_CONT_n_100;
wire ITER_CONT_n_104;
wire ITER_CONT_n_107;
wire ITER_CONT_n_108;
wire ITER_CONT_n_109;
wire ITER_CONT_n_11;
wire ITER_CONT_n_118;
wire ITER_CONT_n_119;
wire ITER_CONT_n_12;
wire ITER_CONT_n_13;
wire ITER_CONT_n_14;
wire ITER_CONT_n_15;
wire ITER_CONT_n_16;
wire ITER_CONT_n_17;
wire ITER_CONT_n_18;
wire ITER_CONT_n_19;
wire ITER_CONT_n_20;
wire ITER_CONT_n_21;
wire ITER_CONT_n_22;
wire ITER_CONT_n_23;
wire ITER_CONT_n_24;
wire ITER_CONT_n_25;
wire ITER_CONT_n_26;
wire ITER_CONT_n_27;
wire ITER_CONT_n_28;
wire ITER_CONT_n_29;
wire ITER_CONT_n_30;
wire ITER_CONT_n_31;
wire ITER_CONT_n_32;
wire ITER_CONT_n_33;
wire ITER_CONT_n_34;
wire ITER_CONT_n_35;
wire ITER_CONT_n_36;
wire ITER_CONT_n_37;
wire ITER_CONT_n_38;
wire ITER_CONT_n_39;
wire ITER_CONT_n_40;
wire ITER_CONT_n_41;
wire ITER_CONT_n_42;
wire ITER_CONT_n_43;
wire ITER_CONT_n_44;
wire ITER_CONT_n_45;
wire ITER_CONT_n_46;
wire ITER_CONT_n_47;
wire ITER_CONT_n_48;
wire ITER_CONT_n_49;
wire ITER_CONT_n_5;
wire ITER_CONT_n_50;
wire ITER_CONT_n_51;
wire ITER_CONT_n_52;
wire ITER_CONT_n_53;
wire ITER_CONT_n_54;
wire ITER_CONT_n_55;
wire ITER_CONT_n_56;
wire ITER_CONT_n_57;
wire ITER_CONT_n_58;
wire ITER_CONT_n_59;
wire ITER_CONT_n_6;
wire ITER_CONT_n_60;
wire ITER_CONT_n_61;
wire ITER_CONT_n_62;
wire ITER_CONT_n_63;
wire ITER_CONT_n_64;
wire ITER_CONT_n_65;
wire ITER_CONT_n_66;
wire ITER_CONT_n_67;
wire ITER_CONT_n_68;
wire ITER_CONT_n_69;
wire ITER_CONT_n_7;
wire ITER_CONT_n_70;
wire ITER_CONT_n_71;
wire ITER_CONT_n_72;
wire ITER_CONT_n_73;
wire ITER_CONT_n_74;
wire ITER_CONT_n_75;
wire ITER_CONT_n_76;
wire ITER_CONT_n_77;
wire ITER_CONT_n_78;
wire ITER_CONT_n_79;
wire ITER_CONT_n_8;
wire ITER_CONT_n_80;
wire ITER_CONT_n_81;
wire ITER_CONT_n_82;
wire ITER_CONT_n_83;
wire ITER_CONT_n_84;
wire ITER_CONT_n_85;
wire ITER_CONT_n_86;
wire ITER_CONT_n_87;
wire ITER_CONT_n_88;
wire ITER_CONT_n_89;
wire ITER_CONT_n_9;
wire ITER_CONT_n_90;
wire ITER_CONT_n_91;
wire ITER_CONT_n_92;
wire ITER_CONT_n_93;
wire ITER_CONT_n_94;
wire ITER_CONT_n_95;
wire ITER_CONT_n_96;
wire ITER_CONT_n_97;
wire ITER_CONT_n_98;
wire ITER_CONT_n_99;
wire VAR_CONT_n_10;
wire VAR_CONT_n_11;
wire VAR_CONT_n_12;
wire VAR_CONT_n_13;
wire VAR_CONT_n_14;
wire VAR_CONT_n_15;
wire VAR_CONT_n_16;
wire VAR_CONT_n_17;
wire VAR_CONT_n_18;
wire VAR_CONT_n_19;
wire VAR_CONT_n_20;
wire VAR_CONT_n_21;
wire VAR_CONT_n_22;
wire VAR_CONT_n_23;
wire VAR_CONT_n_24;
wire VAR_CONT_n_25;
wire VAR_CONT_n_26;
wire VAR_CONT_n_27;
wire VAR_CONT_n_28;
wire VAR_CONT_n_29;
wire VAR_CONT_n_3;
wire VAR_CONT_n_30;
wire VAR_CONT_n_31;
wire VAR_CONT_n_32;
wire VAR_CONT_n_33;
wire VAR_CONT_n_34;
wire VAR_CONT_n_35;
wire VAR_CONT_n_36;
wire VAR_CONT_n_37;
wire VAR_CONT_n_38;
wire VAR_CONT_n_39;
wire VAR_CONT_n_40;
wire VAR_CONT_n_41;
wire VAR_CONT_n_42;
wire VAR_CONT_n_43;
wire VAR_CONT_n_44;
wire VAR_CONT_n_45;
wire VAR_CONT_n_46;
wire VAR_CONT_n_47;
wire VAR_CONT_n_48;
wire VAR_CONT_n_49;
wire VAR_CONT_n_5;
wire VAR_CONT_n_50;
wire VAR_CONT_n_51;
wire VAR_CONT_n_52;
wire VAR_CONT_n_53;
wire VAR_CONT_n_54;
wire VAR_CONT_n_55;
wire VAR_CONT_n_56;
wire VAR_CONT_n_57;
wire VAR_CONT_n_58;
wire VAR_CONT_n_59;
wire VAR_CONT_n_6;
wire VAR_CONT_n_60;
wire VAR_CONT_n_61;
wire VAR_CONT_n_62;
wire VAR_CONT_n_63;
wire VAR_CONT_n_64;
wire VAR_CONT_n_65;
wire VAR_CONT_n_66;
wire VAR_CONT_n_67;
wire VAR_CONT_n_68;
wire VAR_CONT_n_7;
wire VAR_CONT_n_8;
wire VAR_CONT_n_9;
wire [7:0]Y;
wire ack_cordic;
wire ack_cordic_IBUF;
wire beg_fsm_cordic;
wire beg_fsm_cordic_IBUF;
wire busy;
wire busy_OBUF;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire [3:0]cont_iter_out;
wire [1:0]cont_var_out;
wire d_ff1_operation_out;
wire [31:31]d_ff2_Y;
wire [31:31]d_ff2_Z;
wire d_ff3_sign_out;
wire d_ff4_Xn_n_0;
wire d_ff4_Xn_n_1;
wire d_ff4_Xn_n_10;
wire d_ff4_Xn_n_11;
wire d_ff4_Xn_n_12;
wire d_ff4_Xn_n_13;
wire d_ff4_Xn_n_14;
wire d_ff4_Xn_n_15;
wire d_ff4_Xn_n_16;
wire d_ff4_Xn_n_17;
wire d_ff4_Xn_n_18;
wire d_ff4_Xn_n_19;
wire d_ff4_Xn_n_2;
wire d_ff4_Xn_n_20;
wire d_ff4_Xn_n_21;
wire d_ff4_Xn_n_22;
wire d_ff4_Xn_n_23;
wire d_ff4_Xn_n_24;
wire d_ff4_Xn_n_25;
wire d_ff4_Xn_n_26;
wire d_ff4_Xn_n_27;
wire d_ff4_Xn_n_28;
wire d_ff4_Xn_n_29;
wire d_ff4_Xn_n_3;
wire d_ff4_Xn_n_30;
wire d_ff4_Xn_n_31;
wire d_ff4_Xn_n_4;
wire d_ff4_Xn_n_5;
wire d_ff4_Xn_n_6;
wire d_ff4_Xn_n_7;
wire d_ff4_Xn_n_8;
wire d_ff4_Xn_n_9;
wire d_ff4_Yn_n_0;
wire d_ff4_Yn_n_1;
wire d_ff4_Yn_n_10;
wire d_ff4_Yn_n_11;
wire d_ff4_Yn_n_12;
wire d_ff4_Yn_n_13;
wire d_ff4_Yn_n_14;
wire d_ff4_Yn_n_15;
wire d_ff4_Yn_n_16;
wire d_ff4_Yn_n_17;
wire d_ff4_Yn_n_18;
wire d_ff4_Yn_n_19;
wire d_ff4_Yn_n_2;
wire d_ff4_Yn_n_20;
wire d_ff4_Yn_n_21;
wire d_ff4_Yn_n_22;
wire d_ff4_Yn_n_23;
wire d_ff4_Yn_n_24;
wire d_ff4_Yn_n_25;
wire d_ff4_Yn_n_26;
wire d_ff4_Yn_n_27;
wire d_ff4_Yn_n_28;
wire d_ff4_Yn_n_29;
wire d_ff4_Yn_n_3;
wire d_ff4_Yn_n_30;
wire d_ff4_Yn_n_31;
wire d_ff4_Yn_n_4;
wire d_ff4_Yn_n_5;
wire d_ff4_Yn_n_6;
wire d_ff4_Yn_n_7;
wire d_ff4_Yn_n_8;
wire d_ff4_Yn_n_9;
wire d_ff4_Zn_n_0;
wire d_ff4_Zn_n_1;
wire d_ff4_Zn_n_10;
wire d_ff4_Zn_n_11;
wire d_ff4_Zn_n_12;
wire d_ff4_Zn_n_13;
wire d_ff4_Zn_n_14;
wire d_ff4_Zn_n_15;
wire d_ff4_Zn_n_16;
wire d_ff4_Zn_n_17;
wire d_ff4_Zn_n_18;
wire d_ff4_Zn_n_19;
wire d_ff4_Zn_n_2;
wire d_ff4_Zn_n_20;
wire d_ff4_Zn_n_21;
wire d_ff4_Zn_n_22;
wire d_ff4_Zn_n_23;
wire d_ff4_Zn_n_24;
wire d_ff4_Zn_n_25;
wire d_ff4_Zn_n_26;
wire d_ff4_Zn_n_27;
wire d_ff4_Zn_n_28;
wire d_ff4_Zn_n_29;
wire d_ff4_Zn_n_3;
wire d_ff4_Zn_n_30;
wire d_ff4_Zn_n_31;
wire d_ff4_Zn_n_4;
wire d_ff4_Zn_n_5;
wire d_ff4_Zn_n_6;
wire d_ff4_Zn_n_7;
wire d_ff4_Zn_n_8;
wire d_ff4_Zn_n_9;
wire [31:0]data_in;
wire [31:0]data_in_IBUF;
wire [26:0]data_out_LUT;
wire [31:0]data_output;
wire [31:0]data_output_OBUF;
wire enab_RB3;
wire enab_cont_iter;
wire enab_d_ff4_Yn;
wire enab_d_ff4_Zn;
wire enab_d_ff5_data_out;
wire enab_d_ff_RB1;
wire inst_CORDIC_FSM_v3_n_0;
wire inst_CORDIC_FSM_v3_n_1;
wire inst_CORDIC_FSM_v3_n_3;
wire inst_CORDIC_FSM_v3_n_4;
wire inst_CORDIC_FSM_v3_n_5;
wire inst_CORDIC_FSM_v3_n_6;
wire inst_CORDIC_FSM_v3_n_7;
wire inst_CORDIC_FSM_v3_n_8;
wire inst_CORDIC_FSM_v3_n_9;
wire inst_FPU_PIPELINED_FPADDSUB_n_10;
wire inst_FPU_PIPELINED_FPADDSUB_n_11;
wire inst_FPU_PIPELINED_FPADDSUB_n_12;
wire inst_FPU_PIPELINED_FPADDSUB_n_13;
wire inst_FPU_PIPELINED_FPADDSUB_n_14;
wire inst_FPU_PIPELINED_FPADDSUB_n_15;
wire inst_FPU_PIPELINED_FPADDSUB_n_16;
wire inst_FPU_PIPELINED_FPADDSUB_n_17;
wire inst_FPU_PIPELINED_FPADDSUB_n_18;
wire inst_FPU_PIPELINED_FPADDSUB_n_19;
wire inst_FPU_PIPELINED_FPADDSUB_n_2;
wire inst_FPU_PIPELINED_FPADDSUB_n_20;
wire inst_FPU_PIPELINED_FPADDSUB_n_21;
wire inst_FPU_PIPELINED_FPADDSUB_n_22;
wire inst_FPU_PIPELINED_FPADDSUB_n_23;
wire inst_FPU_PIPELINED_FPADDSUB_n_24;
wire inst_FPU_PIPELINED_FPADDSUB_n_25;
wire inst_FPU_PIPELINED_FPADDSUB_n_26;
wire inst_FPU_PIPELINED_FPADDSUB_n_27;
wire inst_FPU_PIPELINED_FPADDSUB_n_28;
wire inst_FPU_PIPELINED_FPADDSUB_n_29;
wire inst_FPU_PIPELINED_FPADDSUB_n_3;
wire inst_FPU_PIPELINED_FPADDSUB_n_30;
wire inst_FPU_PIPELINED_FPADDSUB_n_31;
wire inst_FPU_PIPELINED_FPADDSUB_n_32;
wire inst_FPU_PIPELINED_FPADDSUB_n_33;
wire inst_FPU_PIPELINED_FPADDSUB_n_37;
wire inst_FPU_PIPELINED_FPADDSUB_n_4;
wire inst_FPU_PIPELINED_FPADDSUB_n_5;
wire inst_FPU_PIPELINED_FPADDSUB_n_6;
wire inst_FPU_PIPELINED_FPADDSUB_n_7;
wire inst_FPU_PIPELINED_FPADDSUB_n_8;
wire inst_FPU_PIPELINED_FPADDSUB_n_9;
wire max_tick_iter;
wire op_add_subt;
wire operation;
wire operation_IBUF;
wire overflow_flag;
wire overflow_flag_OBUF;
wire [2:2]p_1_out;
wire ready_add_subt;
wire ready_cordic;
wire ready_cordic_OBUF;
wire reg_LUT_n_0;
wire reg_LUT_n_1;
wire reg_LUT_n_10;
wire reg_LUT_n_11;
wire reg_LUT_n_12;
wire reg_LUT_n_13;
wire reg_LUT_n_14;
wire reg_LUT_n_15;
wire reg_LUT_n_16;
wire reg_LUT_n_17;
wire reg_LUT_n_18;
wire reg_LUT_n_19;
wire reg_LUT_n_2;
wire reg_LUT_n_20;
wire reg_LUT_n_3;
wire reg_LUT_n_4;
wire reg_LUT_n_5;
wire reg_LUT_n_6;
wire reg_LUT_n_7;
wire reg_LUT_n_8;
wire reg_LUT_n_9;
wire reg_Z0_n_0;
wire reg_Z0_n_1;
wire reg_Z0_n_10;
wire reg_Z0_n_11;
wire reg_Z0_n_12;
wire reg_Z0_n_13;
wire reg_Z0_n_14;
wire reg_Z0_n_15;
wire reg_Z0_n_16;
wire reg_Z0_n_17;
wire reg_Z0_n_18;
wire reg_Z0_n_19;
wire reg_Z0_n_2;
wire reg_Z0_n_20;
wire reg_Z0_n_21;
wire reg_Z0_n_22;
wire reg_Z0_n_23;
wire reg_Z0_n_24;
wire reg_Z0_n_25;
wire reg_Z0_n_26;
wire reg_Z0_n_27;
wire reg_Z0_n_28;
wire reg_Z0_n_29;
wire reg_Z0_n_3;
wire reg_Z0_n_30;
wire reg_Z0_n_31;
wire reg_Z0_n_4;
wire reg_Z0_n_5;
wire reg_Z0_n_6;
wire reg_Z0_n_7;
wire reg_Z0_n_8;
wire reg_Z0_n_9;
wire reg_region_flag_n_0;
wire reg_region_flag_n_1;
wire reg_region_flag_n_10;
wire reg_region_flag_n_11;
wire reg_region_flag_n_12;
wire reg_region_flag_n_13;
wire reg_region_flag_n_14;
wire reg_region_flag_n_15;
wire reg_region_flag_n_16;
wire reg_region_flag_n_17;
wire reg_region_flag_n_18;
wire reg_region_flag_n_19;
wire reg_region_flag_n_2;
wire reg_region_flag_n_20;
wire reg_region_flag_n_21;
wire reg_region_flag_n_22;
wire reg_region_flag_n_23;
wire reg_region_flag_n_24;
wire reg_region_flag_n_25;
wire reg_region_flag_n_26;
wire reg_region_flag_n_27;
wire reg_region_flag_n_28;
wire reg_region_flag_n_29;
wire reg_region_flag_n_3;
wire reg_region_flag_n_30;
wire reg_region_flag_n_31;
wire reg_region_flag_n_4;
wire reg_region_flag_n_5;
wire reg_region_flag_n_6;
wire reg_region_flag_n_7;
wire reg_region_flag_n_8;
wire reg_region_flag_n_9;
wire reg_shift_x_n_0;
wire reg_shift_x_n_1;
wire reg_shift_x_n_10;
wire reg_shift_x_n_11;
wire reg_shift_x_n_12;
wire reg_shift_x_n_13;
wire reg_shift_x_n_14;
wire reg_shift_x_n_15;
wire reg_shift_x_n_16;
wire reg_shift_x_n_17;
wire reg_shift_x_n_18;
wire reg_shift_x_n_19;
wire reg_shift_x_n_2;
wire reg_shift_x_n_20;
wire reg_shift_x_n_21;
wire reg_shift_x_n_22;
wire reg_shift_x_n_23;
wire reg_shift_x_n_24;
wire reg_shift_x_n_25;
wire reg_shift_x_n_26;
wire reg_shift_x_n_27;
wire reg_shift_x_n_28;
wire reg_shift_x_n_29;
wire reg_shift_x_n_3;
wire reg_shift_x_n_30;
wire reg_shift_x_n_31;
wire reg_shift_x_n_4;
wire reg_shift_x_n_5;
wire reg_shift_x_n_6;
wire reg_shift_x_n_7;
wire reg_shift_x_n_8;
wire reg_shift_x_n_9;
wire reg_shift_y_n_0;
wire reg_shift_y_n_1;
wire reg_shift_y_n_10;
wire reg_shift_y_n_11;
wire reg_shift_y_n_12;
wire reg_shift_y_n_13;
wire reg_shift_y_n_14;
wire reg_shift_y_n_15;
wire reg_shift_y_n_16;
wire reg_shift_y_n_17;
wire reg_shift_y_n_18;
wire reg_shift_y_n_19;
wire reg_shift_y_n_2;
wire reg_shift_y_n_20;
wire reg_shift_y_n_21;
wire reg_shift_y_n_22;
wire reg_shift_y_n_23;
wire reg_shift_y_n_24;
wire reg_shift_y_n_25;
wire reg_shift_y_n_26;
wire reg_shift_y_n_27;
wire reg_shift_y_n_28;
wire reg_shift_y_n_29;
wire reg_shift_y_n_3;
wire reg_shift_y_n_30;
wire reg_shift_y_n_31;
wire reg_shift_y_n_4;
wire reg_shift_y_n_5;
wire reg_shift_y_n_6;
wire reg_shift_y_n_7;
wire reg_shift_y_n_8;
wire reg_shift_y_n_9;
wire reg_val_muxX_2stage_n_0;
wire reg_val_muxX_2stage_n_1;
wire reg_val_muxX_2stage_n_13;
wire reg_val_muxX_2stage_n_14;
wire reg_val_muxX_2stage_n_15;
wire reg_val_muxX_2stage_n_16;
wire reg_val_muxX_2stage_n_17;
wire reg_val_muxX_2stage_n_18;
wire reg_val_muxX_2stage_n_19;
wire reg_val_muxX_2stage_n_2;
wire reg_val_muxX_2stage_n_20;
wire reg_val_muxX_2stage_n_21;
wire reg_val_muxX_2stage_n_22;
wire reg_val_muxX_2stage_n_23;
wire reg_val_muxX_2stage_n_24;
wire reg_val_muxX_2stage_n_25;
wire reg_val_muxX_2stage_n_26;
wire reg_val_muxX_2stage_n_27;
wire reg_val_muxX_2stage_n_28;
wire reg_val_muxX_2stage_n_29;
wire reg_val_muxX_2stage_n_3;
wire reg_val_muxX_2stage_n_30;
wire reg_val_muxX_2stage_n_31;
wire reg_val_muxX_2stage_n_32;
wire reg_val_muxX_2stage_n_33;
wire reg_val_muxX_2stage_n_34;
wire reg_val_muxX_2stage_n_35;
wire reg_val_muxX_2stage_n_36;
wire reg_val_muxX_2stage_n_37;
wire reg_val_muxX_2stage_n_38;
wire reg_val_muxX_2stage_n_39;
wire reg_val_muxX_2stage_n_4;
wire reg_val_muxY_2stage_n_1;
wire reg_val_muxY_2stage_n_10;
wire reg_val_muxY_2stage_n_11;
wire reg_val_muxY_2stage_n_12;
wire reg_val_muxY_2stage_n_13;
wire reg_val_muxY_2stage_n_14;
wire reg_val_muxY_2stage_n_15;
wire reg_val_muxY_2stage_n_16;
wire reg_val_muxY_2stage_n_17;
wire reg_val_muxY_2stage_n_18;
wire reg_val_muxY_2stage_n_19;
wire reg_val_muxY_2stage_n_2;
wire reg_val_muxY_2stage_n_20;
wire reg_val_muxY_2stage_n_21;
wire reg_val_muxY_2stage_n_22;
wire reg_val_muxY_2stage_n_23;
wire reg_val_muxY_2stage_n_24;
wire reg_val_muxY_2stage_n_25;
wire reg_val_muxY_2stage_n_26;
wire reg_val_muxY_2stage_n_27;
wire reg_val_muxY_2stage_n_28;
wire reg_val_muxY_2stage_n_29;
wire reg_val_muxY_2stage_n_3;
wire reg_val_muxY_2stage_n_30;
wire reg_val_muxY_2stage_n_31;
wire reg_val_muxY_2stage_n_32;
wire reg_val_muxY_2stage_n_33;
wire reg_val_muxY_2stage_n_34;
wire reg_val_muxY_2stage_n_35;
wire reg_val_muxY_2stage_n_36;
wire reg_val_muxY_2stage_n_37;
wire reg_val_muxY_2stage_n_38;
wire reg_val_muxY_2stage_n_39;
wire reg_val_muxY_2stage_n_4;
wire reg_val_muxY_2stage_n_5;
wire reg_val_muxY_2stage_n_6;
wire reg_val_muxY_2stage_n_7;
wire reg_val_muxY_2stage_n_8;
wire reg_val_muxY_2stage_n_9;
wire reg_val_muxZ_2stage_n_1;
wire reg_val_muxZ_2stage_n_10;
wire reg_val_muxZ_2stage_n_11;
wire reg_val_muxZ_2stage_n_12;
wire reg_val_muxZ_2stage_n_13;
wire reg_val_muxZ_2stage_n_14;
wire reg_val_muxZ_2stage_n_15;
wire reg_val_muxZ_2stage_n_16;
wire reg_val_muxZ_2stage_n_17;
wire reg_val_muxZ_2stage_n_18;
wire reg_val_muxZ_2stage_n_19;
wire reg_val_muxZ_2stage_n_2;
wire reg_val_muxZ_2stage_n_20;
wire reg_val_muxZ_2stage_n_21;
wire reg_val_muxZ_2stage_n_22;
wire reg_val_muxZ_2stage_n_23;
wire reg_val_muxZ_2stage_n_24;
wire reg_val_muxZ_2stage_n_25;
wire reg_val_muxZ_2stage_n_26;
wire reg_val_muxZ_2stage_n_27;
wire reg_val_muxZ_2stage_n_28;
wire reg_val_muxZ_2stage_n_29;
wire reg_val_muxZ_2stage_n_3;
wire reg_val_muxZ_2stage_n_30;
wire reg_val_muxZ_2stage_n_31;
wire reg_val_muxZ_2stage_n_4;
wire reg_val_muxZ_2stage_n_5;
wire reg_val_muxZ_2stage_n_6;
wire reg_val_muxZ_2stage_n_7;
wire reg_val_muxZ_2stage_n_8;
wire reg_val_muxZ_2stage_n_9;
wire reset_reg_cordic;
wire rst;
wire rst0;
wire rst_IBUF;
wire [1:0]shift_region_flag;
wire [1:0]shift_region_flag_IBUF;
wire underflow_flag;
wire underflow_flag_OBUF;
wire zero_flag;
wire zero_flag_OBUF;
initial begin
$sdf_annotate("testbench_CORDIC_Arch3_time_synth.sdf",,,,"tool_control");
end
Up_counter ITER_CONT
(.CLK(clk_IBUF_BUFG),
.D({ITER_CONT_n_5,ITER_CONT_n_6,ITER_CONT_n_7,ITER_CONT_n_8,ITER_CONT_n_9,ITER_CONT_n_10,ITER_CONT_n_11,ITER_CONT_n_12,ITER_CONT_n_13,ITER_CONT_n_14,ITER_CONT_n_15,ITER_CONT_n_16,ITER_CONT_n_17,ITER_CONT_n_18,ITER_CONT_n_19,ITER_CONT_n_20,ITER_CONT_n_21,ITER_CONT_n_22,ITER_CONT_n_23,ITER_CONT_n_24,ITER_CONT_n_25,ITER_CONT_n_26,ITER_CONT_n_27,ITER_CONT_n_28,ITER_CONT_n_29,ITER_CONT_n_30,ITER_CONT_n_31,ITER_CONT_n_32,ITER_CONT_n_33,ITER_CONT_n_34,ITER_CONT_n_35,ITER_CONT_n_36}),
.E(enab_cont_iter),
.Q(cont_iter_out),
.\Q_reg[26] ({data_out_LUT[26:24],ITER_CONT_n_104,data_out_LUT[22:21],ITER_CONT_n_107,ITER_CONT_n_108,ITER_CONT_n_109,data_out_LUT[14],data_out_LUT[12:9],p_1_out,data_out_LUT[6],data_out_LUT[4],ITER_CONT_n_118,ITER_CONT_n_119,data_out_LUT[0]}),
.\Q_reg[31] ({ITER_CONT_n_37,ITER_CONT_n_38,ITER_CONT_n_39,ITER_CONT_n_40,ITER_CONT_n_41,ITER_CONT_n_42,ITER_CONT_n_43,ITER_CONT_n_44,ITER_CONT_n_45,ITER_CONT_n_46,ITER_CONT_n_47,ITER_CONT_n_48,ITER_CONT_n_49,ITER_CONT_n_50,ITER_CONT_n_51,ITER_CONT_n_52,ITER_CONT_n_53,ITER_CONT_n_54,ITER_CONT_n_55,ITER_CONT_n_56,ITER_CONT_n_57,ITER_CONT_n_58,ITER_CONT_n_59,ITER_CONT_n_60,ITER_CONT_n_61,ITER_CONT_n_62,ITER_CONT_n_63,ITER_CONT_n_64,ITER_CONT_n_65,ITER_CONT_n_66,ITER_CONT_n_67,ITER_CONT_n_68}),
.\Q_reg[31]_0 ({ITER_CONT_n_69,ITER_CONT_n_70,ITER_CONT_n_71,ITER_CONT_n_72,ITER_CONT_n_73,ITER_CONT_n_74,ITER_CONT_n_75,ITER_CONT_n_76,ITER_CONT_n_77,ITER_CONT_n_78,ITER_CONT_n_79,ITER_CONT_n_80,ITER_CONT_n_81,ITER_CONT_n_82,ITER_CONT_n_83,ITER_CONT_n_84,ITER_CONT_n_85,ITER_CONT_n_86,ITER_CONT_n_87,ITER_CONT_n_88,ITER_CONT_n_89,ITER_CONT_n_90,ITER_CONT_n_91,ITER_CONT_n_92,ITER_CONT_n_93,ITER_CONT_n_94,ITER_CONT_n_95,ITER_CONT_n_96,ITER_CONT_n_97,ITER_CONT_n_98,ITER_CONT_n_99,ITER_CONT_n_100}),
.\Q_reg[31]_1 ({d_ff4_Zn_n_0,d_ff4_Zn_n_1,d_ff4_Zn_n_2,d_ff4_Zn_n_3,d_ff4_Zn_n_4,d_ff4_Zn_n_5,d_ff4_Zn_n_6,d_ff4_Zn_n_7,d_ff4_Zn_n_8,d_ff4_Zn_n_9,d_ff4_Zn_n_10,d_ff4_Zn_n_11,d_ff4_Zn_n_12,d_ff4_Zn_n_13,d_ff4_Zn_n_14,d_ff4_Zn_n_15,d_ff4_Zn_n_16,d_ff4_Zn_n_17,d_ff4_Zn_n_18,d_ff4_Zn_n_19,d_ff4_Zn_n_20,d_ff4_Zn_n_21,d_ff4_Zn_n_22,d_ff4_Zn_n_23,d_ff4_Zn_n_24,d_ff4_Zn_n_25,d_ff4_Zn_n_26,d_ff4_Zn_n_27,d_ff4_Zn_n_28,d_ff4_Zn_n_29,d_ff4_Zn_n_30,d_ff4_Zn_n_31}),
.\Q_reg[31]_2 ({reg_Z0_n_0,reg_Z0_n_1,reg_Z0_n_2,reg_Z0_n_3,reg_Z0_n_4,reg_Z0_n_5,reg_Z0_n_6,reg_Z0_n_7,reg_Z0_n_8,reg_Z0_n_9,reg_Z0_n_10,reg_Z0_n_11,reg_Z0_n_12,reg_Z0_n_13,reg_Z0_n_14,reg_Z0_n_15,reg_Z0_n_16,reg_Z0_n_17,reg_Z0_n_18,reg_Z0_n_19,reg_Z0_n_20,reg_Z0_n_21,reg_Z0_n_22,reg_Z0_n_23,reg_Z0_n_24,reg_Z0_n_25,reg_Z0_n_26,reg_Z0_n_27,reg_Z0_n_28,reg_Z0_n_29,reg_Z0_n_30,reg_Z0_n_31}),
.\Q_reg[31]_3 ({d_ff4_Xn_n_0,d_ff4_Xn_n_1,d_ff4_Xn_n_2,d_ff4_Xn_n_3,d_ff4_Xn_n_4,d_ff4_Xn_n_5,d_ff4_Xn_n_6,d_ff4_Xn_n_7,d_ff4_Xn_n_8,d_ff4_Xn_n_9,d_ff4_Xn_n_10,d_ff4_Xn_n_11,d_ff4_Xn_n_12,d_ff4_Xn_n_13,d_ff4_Xn_n_14,d_ff4_Xn_n_15,d_ff4_Xn_n_16,d_ff4_Xn_n_17,d_ff4_Xn_n_18,d_ff4_Xn_n_19,d_ff4_Xn_n_20,d_ff4_Xn_n_21,d_ff4_Xn_n_22,d_ff4_Xn_n_23,d_ff4_Xn_n_24,d_ff4_Xn_n_25,d_ff4_Xn_n_26,d_ff4_Xn_n_27,d_ff4_Xn_n_28,d_ff4_Xn_n_29,d_ff4_Xn_n_30,d_ff4_Xn_n_31}),
.\Q_reg[31]_4 ({d_ff4_Yn_n_0,d_ff4_Yn_n_1,d_ff4_Yn_n_2,d_ff4_Yn_n_3,d_ff4_Yn_n_4,d_ff4_Yn_n_5,d_ff4_Yn_n_6,d_ff4_Yn_n_7,d_ff4_Yn_n_8,d_ff4_Yn_n_9,d_ff4_Yn_n_10,d_ff4_Yn_n_11,d_ff4_Yn_n_12,d_ff4_Yn_n_13,d_ff4_Yn_n_14,d_ff4_Yn_n_15,d_ff4_Yn_n_16,d_ff4_Yn_n_17,d_ff4_Yn_n_18,d_ff4_Yn_n_19,d_ff4_Yn_n_20,d_ff4_Yn_n_21,d_ff4_Yn_n_22,d_ff4_Yn_n_23,d_ff4_Yn_n_24,d_ff4_Yn_n_25,d_ff4_Yn_n_26,d_ff4_Yn_n_27,d_ff4_Yn_n_28,d_ff4_Yn_n_29,d_ff4_Yn_n_30,d_ff4_Yn_n_31}),
.SR(reset_reg_cordic),
.max_tick_iter(max_tick_iter));
Up_counter__parameterized0 VAR_CONT
(.CLK(clk_IBUF_BUFG),
.D({VAR_CONT_n_5,VAR_CONT_n_6,VAR_CONT_n_7,VAR_CONT_n_8,VAR_CONT_n_9,VAR_CONT_n_10,VAR_CONT_n_11,VAR_CONT_n_12,VAR_CONT_n_13,VAR_CONT_n_14,VAR_CONT_n_15,VAR_CONT_n_16,VAR_CONT_n_17,VAR_CONT_n_18,VAR_CONT_n_19,VAR_CONT_n_20,VAR_CONT_n_21,VAR_CONT_n_22,VAR_CONT_n_23,VAR_CONT_n_24,VAR_CONT_n_25,VAR_CONT_n_26,VAR_CONT_n_27,VAR_CONT_n_28,VAR_CONT_n_29,VAR_CONT_n_30,VAR_CONT_n_31,VAR_CONT_n_32,VAR_CONT_n_33,VAR_CONT_n_34,VAR_CONT_n_35,VAR_CONT_n_36}),
.E(enab_d_ff4_Zn),
.Q({reg_shift_y_n_0,reg_shift_y_n_1,reg_shift_y_n_2,reg_shift_y_n_3,reg_shift_y_n_4,reg_shift_y_n_5,reg_shift_y_n_6,reg_shift_y_n_7,reg_shift_y_n_8,reg_shift_y_n_9,reg_shift_y_n_10,reg_shift_y_n_11,reg_shift_y_n_12,reg_shift_y_n_13,reg_shift_y_n_14,reg_shift_y_n_15,reg_shift_y_n_16,reg_shift_y_n_17,reg_shift_y_n_18,reg_shift_y_n_19,reg_shift_y_n_20,reg_shift_y_n_21,reg_shift_y_n_22,reg_shift_y_n_23,reg_shift_y_n_24,reg_shift_y_n_25,reg_shift_y_n_26,reg_shift_y_n_27,reg_shift_y_n_28,reg_shift_y_n_29,reg_shift_y_n_30,reg_shift_y_n_31}),
.\Q_reg[29] ({reg_LUT_n_0,reg_LUT_n_1,reg_LUT_n_2,reg_LUT_n_3,reg_LUT_n_4,reg_LUT_n_5,reg_LUT_n_6,reg_LUT_n_7,reg_LUT_n_8,reg_LUT_n_9,reg_LUT_n_10,reg_LUT_n_11,reg_LUT_n_12,reg_LUT_n_13,reg_LUT_n_14,reg_LUT_n_15,reg_LUT_n_16,reg_LUT_n_17,reg_LUT_n_18,reg_LUT_n_19,reg_LUT_n_20}),
.\Q_reg[31] (VAR_CONT_n_3),
.\Q_reg[31]_0 (enab_d_ff4_Yn),
.\Q_reg[31]_1 ({VAR_CONT_n_37,VAR_CONT_n_38,VAR_CONT_n_39,VAR_CONT_n_40,VAR_CONT_n_41,VAR_CONT_n_42,VAR_CONT_n_43,VAR_CONT_n_44,VAR_CONT_n_45,VAR_CONT_n_46,VAR_CONT_n_47,VAR_CONT_n_48,VAR_CONT_n_49,VAR_CONT_n_50,VAR_CONT_n_51,VAR_CONT_n_52,VAR_CONT_n_53,VAR_CONT_n_54,VAR_CONT_n_55,VAR_CONT_n_56,VAR_CONT_n_57,VAR_CONT_n_58,VAR_CONT_n_59,VAR_CONT_n_60,VAR_CONT_n_61,VAR_CONT_n_62,VAR_CONT_n_63,VAR_CONT_n_64,VAR_CONT_n_65,VAR_CONT_n_66,VAR_CONT_n_67,VAR_CONT_n_68}),
.\Q_reg[31]_2 ({reg_shift_x_n_0,reg_shift_x_n_1,reg_shift_x_n_2,reg_shift_x_n_3,reg_shift_x_n_4,reg_shift_x_n_5,reg_shift_x_n_6,reg_shift_x_n_7,reg_shift_x_n_8,reg_shift_x_n_9,reg_shift_x_n_10,reg_shift_x_n_11,reg_shift_x_n_12,reg_shift_x_n_13,reg_shift_x_n_14,reg_shift_x_n_15,reg_shift_x_n_16,reg_shift_x_n_17,reg_shift_x_n_18,reg_shift_x_n_19,reg_shift_x_n_20,reg_shift_x_n_21,reg_shift_x_n_22,reg_shift_x_n_23,reg_shift_x_n_24,reg_shift_x_n_25,reg_shift_x_n_26,reg_shift_x_n_27,reg_shift_x_n_28,reg_shift_x_n_29,reg_shift_x_n_30,reg_shift_x_n_31}),
.\Q_reg[31]_3 ({d_ff2_Z,reg_val_muxZ_2stage_n_1,reg_val_muxZ_2stage_n_2,reg_val_muxZ_2stage_n_3,reg_val_muxZ_2stage_n_4,reg_val_muxZ_2stage_n_5,reg_val_muxZ_2stage_n_6,reg_val_muxZ_2stage_n_7,reg_val_muxZ_2stage_n_8,reg_val_muxZ_2stage_n_9,reg_val_muxZ_2stage_n_10,reg_val_muxZ_2stage_n_11,reg_val_muxZ_2stage_n_12,reg_val_muxZ_2stage_n_13,reg_val_muxZ_2stage_n_14,reg_val_muxZ_2stage_n_15,reg_val_muxZ_2stage_n_16,reg_val_muxZ_2stage_n_17,reg_val_muxZ_2stage_n_18,reg_val_muxZ_2stage_n_19,reg_val_muxZ_2stage_n_20,reg_val_muxZ_2stage_n_21,reg_val_muxZ_2stage_n_22,reg_val_muxZ_2stage_n_23,reg_val_muxZ_2stage_n_24,reg_val_muxZ_2stage_n_25,reg_val_muxZ_2stage_n_26,reg_val_muxZ_2stage_n_27,reg_val_muxZ_2stage_n_28,reg_val_muxZ_2stage_n_29,reg_val_muxZ_2stage_n_30,reg_val_muxZ_2stage_n_31}),
.\Q_reg[31]_4 ({reg_val_muxX_2stage_n_4,A,reg_val_muxX_2stage_n_13,reg_val_muxX_2stage_n_14,reg_val_muxX_2stage_n_15,reg_val_muxX_2stage_n_16,reg_val_muxX_2stage_n_17,reg_val_muxX_2stage_n_18,reg_val_muxX_2stage_n_19,reg_val_muxX_2stage_n_20,reg_val_muxX_2stage_n_21,reg_val_muxX_2stage_n_22,reg_val_muxX_2stage_n_23,reg_val_muxX_2stage_n_24,reg_val_muxX_2stage_n_25,reg_val_muxX_2stage_n_26,reg_val_muxX_2stage_n_27,reg_val_muxX_2stage_n_28,reg_val_muxX_2stage_n_29,reg_val_muxX_2stage_n_30,reg_val_muxX_2stage_n_31,reg_val_muxX_2stage_n_32,reg_val_muxX_2stage_n_33,reg_val_muxX_2stage_n_34,reg_val_muxX_2stage_n_35}),
.\Q_reg[31]_5 ({d_ff2_Y,reg_val_muxY_2stage_n_1,reg_val_muxY_2stage_n_2,reg_val_muxY_2stage_n_3,reg_val_muxY_2stage_n_4,reg_val_muxY_2stage_n_5,reg_val_muxY_2stage_n_6,reg_val_muxY_2stage_n_7,reg_val_muxY_2stage_n_8,reg_val_muxY_2stage_n_9,reg_val_muxY_2stage_n_10,reg_val_muxY_2stage_n_11,reg_val_muxY_2stage_n_12,reg_val_muxY_2stage_n_13,reg_val_muxY_2stage_n_14,reg_val_muxY_2stage_n_15,reg_val_muxY_2stage_n_16,reg_val_muxY_2stage_n_17,reg_val_muxY_2stage_n_18,reg_val_muxY_2stage_n_19,reg_val_muxY_2stage_n_20,reg_val_muxY_2stage_n_21,reg_val_muxY_2stage_n_22,reg_val_muxY_2stage_n_23,reg_val_muxY_2stage_n_24,reg_val_muxY_2stage_n_25,reg_val_muxY_2stage_n_26,reg_val_muxY_2stage_n_27,reg_val_muxY_2stage_n_28,reg_val_muxY_2stage_n_29,reg_val_muxY_2stage_n_30,reg_val_muxY_2stage_n_31}),
.cont_var_out(cont_var_out),
.d_ff3_sign_out(d_ff3_sign_out),
.op_add_subt(op_add_subt),
.out({inst_CORDIC_FSM_v3_n_4,inst_CORDIC_FSM_v3_n_6}),
.ready_add_subt(ready_add_subt),
.rst_IBUF(rst_IBUF));
IBUF ack_cordic_IBUF_inst
(.I(ack_cordic),
.O(ack_cordic_IBUF));
IBUF beg_fsm_cordic_IBUF_inst
(.I(beg_fsm_cordic),
.O(beg_fsm_cordic_IBUF));
OBUF busy_OBUF_inst
(.I(busy_OBUF),
.O(busy));
BUFG clk_IBUF_BUFG_inst
(.I(clk_IBUF),
.O(clk_IBUF_BUFG));
IBUF clk_IBUF_inst
(.I(clk),
.O(clk_IBUF));
d_ff_en__parameterized8 d_ff4_Xn
(.AR(reset_reg_cordic),
.CLK(clk_IBUF_BUFG),
.E(VAR_CONT_n_3),
.Q({d_ff4_Xn_n_0,d_ff4_Xn_n_1,d_ff4_Xn_n_2,d_ff4_Xn_n_3,d_ff4_Xn_n_4,d_ff4_Xn_n_5,d_ff4_Xn_n_6,d_ff4_Xn_n_7,d_ff4_Xn_n_8,d_ff4_Xn_n_9,d_ff4_Xn_n_10,d_ff4_Xn_n_11,d_ff4_Xn_n_12,d_ff4_Xn_n_13,d_ff4_Xn_n_14,d_ff4_Xn_n_15,d_ff4_Xn_n_16,d_ff4_Xn_n_17,d_ff4_Xn_n_18,d_ff4_Xn_n_19,d_ff4_Xn_n_20,d_ff4_Xn_n_21,d_ff4_Xn_n_22,d_ff4_Xn_n_23,d_ff4_Xn_n_24,d_ff4_Xn_n_25,d_ff4_Xn_n_26,d_ff4_Xn_n_27,d_ff4_Xn_n_28,d_ff4_Xn_n_29,d_ff4_Xn_n_30,d_ff4_Xn_n_31}),
.\Q_reg[31]_0 ({inst_FPU_PIPELINED_FPADDSUB_n_2,inst_FPU_PIPELINED_FPADDSUB_n_3,inst_FPU_PIPELINED_FPADDSUB_n_4,inst_FPU_PIPELINED_FPADDSUB_n_5,inst_FPU_PIPELINED_FPADDSUB_n_6,inst_FPU_PIPELINED_FPADDSUB_n_7,inst_FPU_PIPELINED_FPADDSUB_n_8,inst_FPU_PIPELINED_FPADDSUB_n_9,inst_FPU_PIPELINED_FPADDSUB_n_10,inst_FPU_PIPELINED_FPADDSUB_n_11,inst_FPU_PIPELINED_FPADDSUB_n_12,inst_FPU_PIPELINED_FPADDSUB_n_13,inst_FPU_PIPELINED_FPADDSUB_n_14,inst_FPU_PIPELINED_FPADDSUB_n_15,inst_FPU_PIPELINED_FPADDSUB_n_16,inst_FPU_PIPELINED_FPADDSUB_n_17,inst_FPU_PIPELINED_FPADDSUB_n_18,inst_FPU_PIPELINED_FPADDSUB_n_19,inst_FPU_PIPELINED_FPADDSUB_n_20,inst_FPU_PIPELINED_FPADDSUB_n_21,inst_FPU_PIPELINED_FPADDSUB_n_22,inst_FPU_PIPELINED_FPADDSUB_n_23,inst_FPU_PIPELINED_FPADDSUB_n_24,inst_FPU_PIPELINED_FPADDSUB_n_25,inst_FPU_PIPELINED_FPADDSUB_n_26,inst_FPU_PIPELINED_FPADDSUB_n_27,inst_FPU_PIPELINED_FPADDSUB_n_28,inst_FPU_PIPELINED_FPADDSUB_n_29,inst_FPU_PIPELINED_FPADDSUB_n_30,inst_FPU_PIPELINED_FPADDSUB_n_31,inst_FPU_PIPELINED_FPADDSUB_n_32,inst_FPU_PIPELINED_FPADDSUB_n_33}));
d_ff_en__parameterized9 d_ff4_Yn
(.AR(reset_reg_cordic),
.CLK(clk_IBUF_BUFG),
.E(enab_d_ff4_Yn),
.Q({d_ff4_Yn_n_0,d_ff4_Yn_n_1,d_ff4_Yn_n_2,d_ff4_Yn_n_3,d_ff4_Yn_n_4,d_ff4_Yn_n_5,d_ff4_Yn_n_6,d_ff4_Yn_n_7,d_ff4_Yn_n_8,d_ff4_Yn_n_9,d_ff4_Yn_n_10,d_ff4_Yn_n_11,d_ff4_Yn_n_12,d_ff4_Yn_n_13,d_ff4_Yn_n_14,d_ff4_Yn_n_15,d_ff4_Yn_n_16,d_ff4_Yn_n_17,d_ff4_Yn_n_18,d_ff4_Yn_n_19,d_ff4_Yn_n_20,d_ff4_Yn_n_21,d_ff4_Yn_n_22,d_ff4_Yn_n_23,d_ff4_Yn_n_24,d_ff4_Yn_n_25,d_ff4_Yn_n_26,d_ff4_Yn_n_27,d_ff4_Yn_n_28,d_ff4_Yn_n_29,d_ff4_Yn_n_30,d_ff4_Yn_n_31}),
.\Q_reg[31]_0 ({inst_FPU_PIPELINED_FPADDSUB_n_2,inst_FPU_PIPELINED_FPADDSUB_n_3,inst_FPU_PIPELINED_FPADDSUB_n_4,inst_FPU_PIPELINED_FPADDSUB_n_5,inst_FPU_PIPELINED_FPADDSUB_n_6,inst_FPU_PIPELINED_FPADDSUB_n_7,inst_FPU_PIPELINED_FPADDSUB_n_8,inst_FPU_PIPELINED_FPADDSUB_n_9,inst_FPU_PIPELINED_FPADDSUB_n_10,inst_FPU_PIPELINED_FPADDSUB_n_11,inst_FPU_PIPELINED_FPADDSUB_n_12,inst_FPU_PIPELINED_FPADDSUB_n_13,inst_FPU_PIPELINED_FPADDSUB_n_14,inst_FPU_PIPELINED_FPADDSUB_n_15,inst_FPU_PIPELINED_FPADDSUB_n_16,inst_FPU_PIPELINED_FPADDSUB_n_17,inst_FPU_PIPELINED_FPADDSUB_n_18,inst_FPU_PIPELINED_FPADDSUB_n_19,inst_FPU_PIPELINED_FPADDSUB_n_20,inst_FPU_PIPELINED_FPADDSUB_n_21,inst_FPU_PIPELINED_FPADDSUB_n_22,inst_FPU_PIPELINED_FPADDSUB_n_23,inst_FPU_PIPELINED_FPADDSUB_n_24,inst_FPU_PIPELINED_FPADDSUB_n_25,inst_FPU_PIPELINED_FPADDSUB_n_26,inst_FPU_PIPELINED_FPADDSUB_n_27,inst_FPU_PIPELINED_FPADDSUB_n_28,inst_FPU_PIPELINED_FPADDSUB_n_29,inst_FPU_PIPELINED_FPADDSUB_n_30,inst_FPU_PIPELINED_FPADDSUB_n_31,inst_FPU_PIPELINED_FPADDSUB_n_32,inst_FPU_PIPELINED_FPADDSUB_n_33}));
d_ff_en__parameterized10 d_ff4_Zn
(.AR(reset_reg_cordic),
.CLK(clk_IBUF_BUFG),
.E(enab_d_ff4_Zn),
.Q({d_ff4_Zn_n_0,d_ff4_Zn_n_1,d_ff4_Zn_n_2,d_ff4_Zn_n_3,d_ff4_Zn_n_4,d_ff4_Zn_n_5,d_ff4_Zn_n_6,d_ff4_Zn_n_7,d_ff4_Zn_n_8,d_ff4_Zn_n_9,d_ff4_Zn_n_10,d_ff4_Zn_n_11,d_ff4_Zn_n_12,d_ff4_Zn_n_13,d_ff4_Zn_n_14,d_ff4_Zn_n_15,d_ff4_Zn_n_16,d_ff4_Zn_n_17,d_ff4_Zn_n_18,d_ff4_Zn_n_19,d_ff4_Zn_n_20,d_ff4_Zn_n_21,d_ff4_Zn_n_22,d_ff4_Zn_n_23,d_ff4_Zn_n_24,d_ff4_Zn_n_25,d_ff4_Zn_n_26,d_ff4_Zn_n_27,d_ff4_Zn_n_28,d_ff4_Zn_n_29,d_ff4_Zn_n_30,d_ff4_Zn_n_31}),
.\Q_reg[31]_0 ({inst_FPU_PIPELINED_FPADDSUB_n_2,inst_FPU_PIPELINED_FPADDSUB_n_3,inst_FPU_PIPELINED_FPADDSUB_n_4,inst_FPU_PIPELINED_FPADDSUB_n_5,inst_FPU_PIPELINED_FPADDSUB_n_6,inst_FPU_PIPELINED_FPADDSUB_n_7,inst_FPU_PIPELINED_FPADDSUB_n_8,inst_FPU_PIPELINED_FPADDSUB_n_9,inst_FPU_PIPELINED_FPADDSUB_n_10,inst_FPU_PIPELINED_FPADDSUB_n_11,inst_FPU_PIPELINED_FPADDSUB_n_12,inst_FPU_PIPELINED_FPADDSUB_n_13,inst_FPU_PIPELINED_FPADDSUB_n_14,inst_FPU_PIPELINED_FPADDSUB_n_15,inst_FPU_PIPELINED_FPADDSUB_n_16,inst_FPU_PIPELINED_FPADDSUB_n_17,inst_FPU_PIPELINED_FPADDSUB_n_18,inst_FPU_PIPELINED_FPADDSUB_n_19,inst_FPU_PIPELINED_FPADDSUB_n_20,inst_FPU_PIPELINED_FPADDSUB_n_21,inst_FPU_PIPELINED_FPADDSUB_n_22,inst_FPU_PIPELINED_FPADDSUB_n_23,inst_FPU_PIPELINED_FPADDSUB_n_24,inst_FPU_PIPELINED_FPADDSUB_n_25,inst_FPU_PIPELINED_FPADDSUB_n_26,inst_FPU_PIPELINED_FPADDSUB_n_27,inst_FPU_PIPELINED_FPADDSUB_n_28,inst_FPU_PIPELINED_FPADDSUB_n_29,inst_FPU_PIPELINED_FPADDSUB_n_30,inst_FPU_PIPELINED_FPADDSUB_n_31,inst_FPU_PIPELINED_FPADDSUB_n_32,inst_FPU_PIPELINED_FPADDSUB_n_33}));
d_ff_en__parameterized11 d_ff5_data_out
(.AR(reset_reg_cordic),
.CLK(clk_IBUF_BUFG),
.D({reg_region_flag_n_0,reg_region_flag_n_1,reg_region_flag_n_2,reg_region_flag_n_3,reg_region_flag_n_4,reg_region_flag_n_5,reg_region_flag_n_6,reg_region_flag_n_7,reg_region_flag_n_8,reg_region_flag_n_9,reg_region_flag_n_10,reg_region_flag_n_11,reg_region_flag_n_12,reg_region_flag_n_13,reg_region_flag_n_14,reg_region_flag_n_15,reg_region_flag_n_16,reg_region_flag_n_17,reg_region_flag_n_18,reg_region_flag_n_19,reg_region_flag_n_20,reg_region_flag_n_21,reg_region_flag_n_22,reg_region_flag_n_23,reg_region_flag_n_24,reg_region_flag_n_25,reg_region_flag_n_26,reg_region_flag_n_27,reg_region_flag_n_28,reg_region_flag_n_29,reg_region_flag_n_30,reg_region_flag_n_31}),
.E(enab_d_ff5_data_out),
.Q(data_output_OBUF));
IBUF \data_in_IBUF[0]_inst
(.I(data_in[0]),
.O(data_in_IBUF[0]));
IBUF \data_in_IBUF[10]_inst
(.I(data_in[10]),
.O(data_in_IBUF[10]));
IBUF \data_in_IBUF[11]_inst
(.I(data_in[11]),
.O(data_in_IBUF[11]));
IBUF \data_in_IBUF[12]_inst
(.I(data_in[12]),
.O(data_in_IBUF[12]));
IBUF \data_in_IBUF[13]_inst
(.I(data_in[13]),
.O(data_in_IBUF[13]));
IBUF \data_in_IBUF[14]_inst
(.I(data_in[14]),
.O(data_in_IBUF[14]));
IBUF \data_in_IBUF[15]_inst
(.I(data_in[15]),
.O(data_in_IBUF[15]));
IBUF \data_in_IBUF[16]_inst
(.I(data_in[16]),
.O(data_in_IBUF[16]));
IBUF \data_in_IBUF[17]_inst
(.I(data_in[17]),
.O(data_in_IBUF[17]));
IBUF \data_in_IBUF[18]_inst
(.I(data_in[18]),
.O(data_in_IBUF[18]));
IBUF \data_in_IBUF[19]_inst
(.I(data_in[19]),
.O(data_in_IBUF[19]));
IBUF \data_in_IBUF[1]_inst
(.I(data_in[1]),
.O(data_in_IBUF[1]));
IBUF \data_in_IBUF[20]_inst
(.I(data_in[20]),
.O(data_in_IBUF[20]));
IBUF \data_in_IBUF[21]_inst
(.I(data_in[21]),
.O(data_in_IBUF[21]));
IBUF \data_in_IBUF[22]_inst
(.I(data_in[22]),
.O(data_in_IBUF[22]));
IBUF \data_in_IBUF[23]_inst
(.I(data_in[23]),
.O(data_in_IBUF[23]));
IBUF \data_in_IBUF[24]_inst
(.I(data_in[24]),
.O(data_in_IBUF[24]));
IBUF \data_in_IBUF[25]_inst
(.I(data_in[25]),
.O(data_in_IBUF[25]));
IBUF \data_in_IBUF[26]_inst
(.I(data_in[26]),
.O(data_in_IBUF[26]));
IBUF \data_in_IBUF[27]_inst
(.I(data_in[27]),
.O(data_in_IBUF[27]));
IBUF \data_in_IBUF[28]_inst
(.I(data_in[28]),
.O(data_in_IBUF[28]));
IBUF \data_in_IBUF[29]_inst
(.I(data_in[29]),
.O(data_in_IBUF[29]));
IBUF \data_in_IBUF[2]_inst
(.I(data_in[2]),
.O(data_in_IBUF[2]));
IBUF \data_in_IBUF[30]_inst
(.I(data_in[30]),
.O(data_in_IBUF[30]));
IBUF \data_in_IBUF[31]_inst
(.I(data_in[31]),
.O(data_in_IBUF[31]));
IBUF \data_in_IBUF[3]_inst
(.I(data_in[3]),
.O(data_in_IBUF[3]));
IBUF \data_in_IBUF[4]_inst
(.I(data_in[4]),
.O(data_in_IBUF[4]));
IBUF \data_in_IBUF[5]_inst
(.I(data_in[5]),
.O(data_in_IBUF[5]));
IBUF \data_in_IBUF[6]_inst
(.I(data_in[6]),
.O(data_in_IBUF[6]));
IBUF \data_in_IBUF[7]_inst
(.I(data_in[7]),
.O(data_in_IBUF[7]));
IBUF \data_in_IBUF[8]_inst
(.I(data_in[8]),
.O(data_in_IBUF[8]));
IBUF \data_in_IBUF[9]_inst
(.I(data_in[9]),
.O(data_in_IBUF[9]));
OBUF \data_output_OBUF[0]_inst
(.I(data_output_OBUF[0]),
.O(data_output[0]));
OBUF \data_output_OBUF[10]_inst
(.I(data_output_OBUF[10]),
.O(data_output[10]));
OBUF \data_output_OBUF[11]_inst
(.I(data_output_OBUF[11]),
.O(data_output[11]));
OBUF \data_output_OBUF[12]_inst
(.I(data_output_OBUF[12]),
.O(data_output[12]));
OBUF \data_output_OBUF[13]_inst
(.I(data_output_OBUF[13]),
.O(data_output[13]));
OBUF \data_output_OBUF[14]_inst
(.I(data_output_OBUF[14]),
.O(data_output[14]));
OBUF \data_output_OBUF[15]_inst
(.I(data_output_OBUF[15]),
.O(data_output[15]));
OBUF \data_output_OBUF[16]_inst
(.I(data_output_OBUF[16]),
.O(data_output[16]));
OBUF \data_output_OBUF[17]_inst
(.I(data_output_OBUF[17]),
.O(data_output[17]));
OBUF \data_output_OBUF[18]_inst
(.I(data_output_OBUF[18]),
.O(data_output[18]));
OBUF \data_output_OBUF[19]_inst
(.I(data_output_OBUF[19]),
.O(data_output[19]));
OBUF \data_output_OBUF[1]_inst
(.I(data_output_OBUF[1]),
.O(data_output[1]));
OBUF \data_output_OBUF[20]_inst
(.I(data_output_OBUF[20]),
.O(data_output[20]));
OBUF \data_output_OBUF[21]_inst
(.I(data_output_OBUF[21]),
.O(data_output[21]));
OBUF \data_output_OBUF[22]_inst
(.I(data_output_OBUF[22]),
.O(data_output[22]));
OBUF \data_output_OBUF[23]_inst
(.I(data_output_OBUF[23]),
.O(data_output[23]));
OBUF \data_output_OBUF[24]_inst
(.I(data_output_OBUF[24]),
.O(data_output[24]));
OBUF \data_output_OBUF[25]_inst
(.I(data_output_OBUF[25]),
.O(data_output[25]));
OBUF \data_output_OBUF[26]_inst
(.I(data_output_OBUF[26]),
.O(data_output[26]));
OBUF \data_output_OBUF[27]_inst
(.I(data_output_OBUF[27]),
.O(data_output[27]));
OBUF \data_output_OBUF[28]_inst
(.I(data_output_OBUF[28]),
.O(data_output[28]));
OBUF \data_output_OBUF[29]_inst
(.I(data_output_OBUF[29]),
.O(data_output[29]));
OBUF \data_output_OBUF[2]_inst
(.I(data_output_OBUF[2]),
.O(data_output[2]));
OBUF \data_output_OBUF[30]_inst
(.I(data_output_OBUF[30]),
.O(data_output[30]));
OBUF \data_output_OBUF[31]_inst
(.I(data_output_OBUF[31]),
.O(data_output[31]));
OBUF \data_output_OBUF[3]_inst
(.I(data_output_OBUF[3]),
.O(data_output[3]));
OBUF \data_output_OBUF[4]_inst
(.I(data_output_OBUF[4]),
.O(data_output[4]));
OBUF \data_output_OBUF[5]_inst
(.I(data_output_OBUF[5]),
.O(data_output[5]));
OBUF \data_output_OBUF[6]_inst
(.I(data_output_OBUF[6]),
.O(data_output[6]));
OBUF \data_output_OBUF[7]_inst
(.I(data_output_OBUF[7]),
.O(data_output[7]));
OBUF \data_output_OBUF[8]_inst
(.I(data_output_OBUF[8]),
.O(data_output[8]));
OBUF \data_output_OBUF[9]_inst
(.I(data_output_OBUF[9]),
.O(data_output[9]));
CORDIC_FSM_v3 inst_CORDIC_FSM_v3
(.AR({inst_CORDIC_FSM_v3_n_0,inst_CORDIC_FSM_v3_n_1,rst0,inst_CORDIC_FSM_v3_n_3}),
.CLK(clk_IBUF_BUFG),
.E(inst_CORDIC_FSM_v3_n_8),
.\FSM_sequential_state_reg_reg[0]_0 (inst_CORDIC_FSM_v3_n_7),
.\FSM_sequential_state_reg_reg[2]_0 (inst_FPU_PIPELINED_FPADDSUB_n_37),
.\Q_reg[0] (enab_RB3),
.\Q_reg[1] (enab_d_ff_RB1),
.\Q_reg[31] (inst_CORDIC_FSM_v3_n_9),
.\Q_reg[31]_0 (enab_d_ff5_data_out),
.\Q_reg[31]_1 (reset_reg_cordic),
.ack_cordic_IBUF(ack_cordic_IBUF),
.beg_fsm_cordic_IBUF(beg_fsm_cordic_IBUF),
.cont_var_out(cont_var_out),
.max_tick_iter(max_tick_iter),
.out({inst_CORDIC_FSM_v3_n_4,inst_CORDIC_FSM_v3_n_5,inst_CORDIC_FSM_v3_n_6}),
.ready_cordic_OBUF(ready_cordic_OBUF),
.rst_IBUF(rst_IBUF),
.\temp_reg[0] (enab_cont_iter),
.\temp_reg[1] (enab_d_ff4_Zn));
FPU_PIPELINED_FPADDSUB inst_FPU_PIPELINED_FPADDSUB
(.AR({inst_CORDIC_FSM_v3_n_0,inst_CORDIC_FSM_v3_n_1,rst0,inst_CORDIC_FSM_v3_n_3}),
.CLK(clk_IBUF_BUFG),
.D({VAR_CONT_n_5,VAR_CONT_n_6,VAR_CONT_n_7,VAR_CONT_n_8,VAR_CONT_n_9,VAR_CONT_n_10,VAR_CONT_n_11,VAR_CONT_n_12,VAR_CONT_n_13,VAR_CONT_n_14,VAR_CONT_n_15,VAR_CONT_n_16,VAR_CONT_n_17,VAR_CONT_n_18,VAR_CONT_n_19,VAR_CONT_n_20,VAR_CONT_n_21,VAR_CONT_n_22,VAR_CONT_n_23,VAR_CONT_n_24,VAR_CONT_n_25,VAR_CONT_n_26,VAR_CONT_n_27,VAR_CONT_n_28,VAR_CONT_n_29,VAR_CONT_n_30,VAR_CONT_n_31,VAR_CONT_n_32,VAR_CONT_n_33,VAR_CONT_n_34,VAR_CONT_n_35,VAR_CONT_n_36}),
.E(inst_CORDIC_FSM_v3_n_9),
.\FSM_sequential_state_reg_reg[1] (inst_CORDIC_FSM_v3_n_7),
.\FSM_sequential_state_reg_reg[2] ({inst_CORDIC_FSM_v3_n_4,inst_CORDIC_FSM_v3_n_5}),
.Q(busy_OBUF),
.\Q_reg[31] ({inst_FPU_PIPELINED_FPADDSUB_n_2,inst_FPU_PIPELINED_FPADDSUB_n_3,inst_FPU_PIPELINED_FPADDSUB_n_4,inst_FPU_PIPELINED_FPADDSUB_n_5,inst_FPU_PIPELINED_FPADDSUB_n_6,inst_FPU_PIPELINED_FPADDSUB_n_7,inst_FPU_PIPELINED_FPADDSUB_n_8,inst_FPU_PIPELINED_FPADDSUB_n_9,inst_FPU_PIPELINED_FPADDSUB_n_10,inst_FPU_PIPELINED_FPADDSUB_n_11,inst_FPU_PIPELINED_FPADDSUB_n_12,inst_FPU_PIPELINED_FPADDSUB_n_13,inst_FPU_PIPELINED_FPADDSUB_n_14,inst_FPU_PIPELINED_FPADDSUB_n_15,inst_FPU_PIPELINED_FPADDSUB_n_16,inst_FPU_PIPELINED_FPADDSUB_n_17,inst_FPU_PIPELINED_FPADDSUB_n_18,inst_FPU_PIPELINED_FPADDSUB_n_19,inst_FPU_PIPELINED_FPADDSUB_n_20,inst_FPU_PIPELINED_FPADDSUB_n_21,inst_FPU_PIPELINED_FPADDSUB_n_22,inst_FPU_PIPELINED_FPADDSUB_n_23,inst_FPU_PIPELINED_FPADDSUB_n_24,inst_FPU_PIPELINED_FPADDSUB_n_25,inst_FPU_PIPELINED_FPADDSUB_n_26,inst_FPU_PIPELINED_FPADDSUB_n_27,inst_FPU_PIPELINED_FPADDSUB_n_28,inst_FPU_PIPELINED_FPADDSUB_n_29,inst_FPU_PIPELINED_FPADDSUB_n_30,inst_FPU_PIPELINED_FPADDSUB_n_31,inst_FPU_PIPELINED_FPADDSUB_n_32,inst_FPU_PIPELINED_FPADDSUB_n_33}),
.\Q_reg[31]_0 ({VAR_CONT_n_37,VAR_CONT_n_38,VAR_CONT_n_39,VAR_CONT_n_40,VAR_CONT_n_41,VAR_CONT_n_42,VAR_CONT_n_43,VAR_CONT_n_44,VAR_CONT_n_45,VAR_CONT_n_46,VAR_CONT_n_47,VAR_CONT_n_48,VAR_CONT_n_49,VAR_CONT_n_50,VAR_CONT_n_51,VAR_CONT_n_52,VAR_CONT_n_53,VAR_CONT_n_54,VAR_CONT_n_55,VAR_CONT_n_56,VAR_CONT_n_57,VAR_CONT_n_58,VAR_CONT_n_59,VAR_CONT_n_60,VAR_CONT_n_61,VAR_CONT_n_62,VAR_CONT_n_63,VAR_CONT_n_64,VAR_CONT_n_65,VAR_CONT_n_66,VAR_CONT_n_67,VAR_CONT_n_68}),
.op_add_subt(op_add_subt),
.out(inst_FPU_PIPELINED_FPADDSUB_n_37),
.overflow_flag({overflow_flag_OBUF,underflow_flag_OBUF,zero_flag_OBUF}),
.ready_add_subt(ready_add_subt));
IBUF operation_IBUF_inst
(.I(operation),
.O(operation_IBUF));
OBUF overflow_flag_OBUF_inst
(.I(overflow_flag_OBUF),
.O(overflow_flag));
OBUF ready_cordic_OBUF_inst
(.I(ready_cordic_OBUF),
.O(ready_cordic));
d_ff_en__parameterized7 reg_LUT
(.CLK(clk_IBUF_BUFG),
.D({data_out_LUT[26:24],ITER_CONT_n_104,data_out_LUT[22:21],ITER_CONT_n_107,ITER_CONT_n_108,ITER_CONT_n_109,data_out_LUT[14],data_out_LUT[12:9],p_1_out,data_out_LUT[6],data_out_LUT[4],ITER_CONT_n_118,ITER_CONT_n_119,data_out_LUT[0]}),
.E(enab_RB3),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({reg_LUT_n_0,reg_LUT_n_1,reg_LUT_n_2,reg_LUT_n_3,reg_LUT_n_4,reg_LUT_n_5,reg_LUT_n_6,reg_LUT_n_7,reg_LUT_n_8,reg_LUT_n_9,reg_LUT_n_10,reg_LUT_n_11,reg_LUT_n_12,reg_LUT_n_13,reg_LUT_n_14,reg_LUT_n_15,reg_LUT_n_16,reg_LUT_n_17,reg_LUT_n_18,reg_LUT_n_19,reg_LUT_n_20}));
d_ff_en__parameterized1 reg_Z0
(.CLK(clk_IBUF_BUFG),
.D(data_in_IBUF),
.E(enab_d_ff_RB1),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({reg_Z0_n_0,reg_Z0_n_1,reg_Z0_n_2,reg_Z0_n_3,reg_Z0_n_4,reg_Z0_n_5,reg_Z0_n_6,reg_Z0_n_7,reg_Z0_n_8,reg_Z0_n_9,reg_Z0_n_10,reg_Z0_n_11,reg_Z0_n_12,reg_Z0_n_13,reg_Z0_n_14,reg_Z0_n_15,reg_Z0_n_16,reg_Z0_n_17,reg_Z0_n_18,reg_Z0_n_19,reg_Z0_n_20,reg_Z0_n_21,reg_Z0_n_22,reg_Z0_n_23,reg_Z0_n_24,reg_Z0_n_25,reg_Z0_n_26,reg_Z0_n_27,reg_Z0_n_28,reg_Z0_n_29,reg_Z0_n_30,reg_Z0_n_31}));
d_ff_en reg_operation
(.CLK(clk_IBUF_BUFG),
.E(enab_d_ff_RB1),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.d_ff1_operation_out(d_ff1_operation_out),
.operation_IBUF(operation_IBUF));
d_ff_en__parameterized0 reg_region_flag
(.CLK(clk_IBUF_BUFG),
.D({reg_region_flag_n_0,reg_region_flag_n_1,reg_region_flag_n_2,reg_region_flag_n_3,reg_region_flag_n_4,reg_region_flag_n_5,reg_region_flag_n_6,reg_region_flag_n_7,reg_region_flag_n_8,reg_region_flag_n_9,reg_region_flag_n_10,reg_region_flag_n_11,reg_region_flag_n_12,reg_region_flag_n_13,reg_region_flag_n_14,reg_region_flag_n_15,reg_region_flag_n_16,reg_region_flag_n_17,reg_region_flag_n_18,reg_region_flag_n_19,reg_region_flag_n_20,reg_region_flag_n_21,reg_region_flag_n_22,reg_region_flag_n_23,reg_region_flag_n_24,reg_region_flag_n_25,reg_region_flag_n_26,reg_region_flag_n_27,reg_region_flag_n_28,reg_region_flag_n_29,reg_region_flag_n_30,reg_region_flag_n_31}),
.E(enab_d_ff_RB1),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({d_ff4_Yn_n_0,d_ff4_Yn_n_1,d_ff4_Yn_n_2,d_ff4_Yn_n_3,d_ff4_Yn_n_4,d_ff4_Yn_n_5,d_ff4_Yn_n_6,d_ff4_Yn_n_7,d_ff4_Yn_n_8,d_ff4_Yn_n_9,d_ff4_Yn_n_10,d_ff4_Yn_n_11,d_ff4_Yn_n_12,d_ff4_Yn_n_13,d_ff4_Yn_n_14,d_ff4_Yn_n_15,d_ff4_Yn_n_16,d_ff4_Yn_n_17,d_ff4_Yn_n_18,d_ff4_Yn_n_19,d_ff4_Yn_n_20,d_ff4_Yn_n_21,d_ff4_Yn_n_22,d_ff4_Yn_n_23,d_ff4_Yn_n_24,d_ff4_Yn_n_25,d_ff4_Yn_n_26,d_ff4_Yn_n_27,d_ff4_Yn_n_28,d_ff4_Yn_n_29,d_ff4_Yn_n_30,d_ff4_Yn_n_31}),
.\Q_reg[31] ({d_ff4_Xn_n_0,d_ff4_Xn_n_1,d_ff4_Xn_n_2,d_ff4_Xn_n_3,d_ff4_Xn_n_4,d_ff4_Xn_n_5,d_ff4_Xn_n_6,d_ff4_Xn_n_7,d_ff4_Xn_n_8,d_ff4_Xn_n_9,d_ff4_Xn_n_10,d_ff4_Xn_n_11,d_ff4_Xn_n_12,d_ff4_Xn_n_13,d_ff4_Xn_n_14,d_ff4_Xn_n_15,d_ff4_Xn_n_16,d_ff4_Xn_n_17,d_ff4_Xn_n_18,d_ff4_Xn_n_19,d_ff4_Xn_n_20,d_ff4_Xn_n_21,d_ff4_Xn_n_22,d_ff4_Xn_n_23,d_ff4_Xn_n_24,d_ff4_Xn_n_25,d_ff4_Xn_n_26,d_ff4_Xn_n_27,d_ff4_Xn_n_28,d_ff4_Xn_n_29,d_ff4_Xn_n_30,d_ff4_Xn_n_31}),
.d_ff1_operation_out(d_ff1_operation_out),
.\shift_region_flag[1] (shift_region_flag_IBUF));
d_ff_en__parameterized5 reg_shift_x
(.CLK(clk_IBUF_BUFG),
.D({reg_val_muxX_2stage_n_4,Y,reg_val_muxX_2stage_n_13,reg_val_muxX_2stage_n_14,reg_val_muxX_2stage_n_15,reg_val_muxX_2stage_n_16,reg_val_muxX_2stage_n_17,reg_val_muxX_2stage_n_18,reg_val_muxX_2stage_n_19,reg_val_muxX_2stage_n_20,reg_val_muxX_2stage_n_21,reg_val_muxX_2stage_n_22,reg_val_muxX_2stage_n_23,reg_val_muxX_2stage_n_24,reg_val_muxX_2stage_n_25,reg_val_muxX_2stage_n_26,reg_val_muxX_2stage_n_27,reg_val_muxX_2stage_n_28,reg_val_muxX_2stage_n_29,reg_val_muxX_2stage_n_30,reg_val_muxX_2stage_n_31,reg_val_muxX_2stage_n_32,reg_val_muxX_2stage_n_33,reg_val_muxX_2stage_n_34,reg_val_muxX_2stage_n_35}),
.E(enab_RB3),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({reg_shift_x_n_0,reg_shift_x_n_1,reg_shift_x_n_2,reg_shift_x_n_3,reg_shift_x_n_4,reg_shift_x_n_5,reg_shift_x_n_6,reg_shift_x_n_7,reg_shift_x_n_8,reg_shift_x_n_9,reg_shift_x_n_10,reg_shift_x_n_11,reg_shift_x_n_12,reg_shift_x_n_13,reg_shift_x_n_14,reg_shift_x_n_15,reg_shift_x_n_16,reg_shift_x_n_17,reg_shift_x_n_18,reg_shift_x_n_19,reg_shift_x_n_20,reg_shift_x_n_21,reg_shift_x_n_22,reg_shift_x_n_23,reg_shift_x_n_24,reg_shift_x_n_25,reg_shift_x_n_26,reg_shift_x_n_27,reg_shift_x_n_28,reg_shift_x_n_29,reg_shift_x_n_30,reg_shift_x_n_31}));
d_ff_en__parameterized6 reg_shift_y
(.CLK(clk_IBUF_BUFG),
.D({d_ff2_Y,reg_val_muxY_2stage_n_32,reg_val_muxY_2stage_n_33,reg_val_muxY_2stage_n_34,reg_val_muxY_2stage_n_35,reg_val_muxY_2stage_n_36,reg_val_muxY_2stage_n_37,reg_val_muxY_2stage_n_38,reg_val_muxY_2stage_n_39,reg_val_muxY_2stage_n_9,reg_val_muxY_2stage_n_10,reg_val_muxY_2stage_n_11,reg_val_muxY_2stage_n_12,reg_val_muxY_2stage_n_13,reg_val_muxY_2stage_n_14,reg_val_muxY_2stage_n_15,reg_val_muxY_2stage_n_16,reg_val_muxY_2stage_n_17,reg_val_muxY_2stage_n_18,reg_val_muxY_2stage_n_19,reg_val_muxY_2stage_n_20,reg_val_muxY_2stage_n_21,reg_val_muxY_2stage_n_22,reg_val_muxY_2stage_n_23,reg_val_muxY_2stage_n_24,reg_val_muxY_2stage_n_25,reg_val_muxY_2stage_n_26,reg_val_muxY_2stage_n_27,reg_val_muxY_2stage_n_28,reg_val_muxY_2stage_n_29,reg_val_muxY_2stage_n_30,reg_val_muxY_2stage_n_31}),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.\FSM_sequential_state_reg_reg[2] (enab_RB3),
.Q({reg_shift_y_n_0,reg_shift_y_n_1,reg_shift_y_n_2,reg_shift_y_n_3,reg_shift_y_n_4,reg_shift_y_n_5,reg_shift_y_n_6,reg_shift_y_n_7,reg_shift_y_n_8,reg_shift_y_n_9,reg_shift_y_n_10,reg_shift_y_n_11,reg_shift_y_n_12,reg_shift_y_n_13,reg_shift_y_n_14,reg_shift_y_n_15,reg_shift_y_n_16,reg_shift_y_n_17,reg_shift_y_n_18,reg_shift_y_n_19,reg_shift_y_n_20,reg_shift_y_n_21,reg_shift_y_n_22,reg_shift_y_n_23,reg_shift_y_n_24,reg_shift_y_n_25,reg_shift_y_n_26,reg_shift_y_n_27,reg_shift_y_n_28,reg_shift_y_n_29,reg_shift_y_n_30,reg_shift_y_n_31}));
d_ff_en_0 reg_sign
(.CLK(clk_IBUF_BUFG),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.\FSM_sequential_state_reg_reg[2] (enab_RB3),
.Q(d_ff2_Z),
.d_ff3_sign_out(d_ff3_sign_out));
d_ff_en__parameterized2 reg_val_muxX_2stage
(.CLK(clk_IBUF_BUFG),
.D({ITER_CONT_n_37,ITER_CONT_n_38,ITER_CONT_n_39,ITER_CONT_n_40,ITER_CONT_n_41,ITER_CONT_n_42,ITER_CONT_n_43,ITER_CONT_n_44,ITER_CONT_n_45,ITER_CONT_n_46,ITER_CONT_n_47,ITER_CONT_n_48,ITER_CONT_n_49,ITER_CONT_n_50,ITER_CONT_n_51,ITER_CONT_n_52,ITER_CONT_n_53,ITER_CONT_n_54,ITER_CONT_n_55,ITER_CONT_n_56,ITER_CONT_n_57,ITER_CONT_n_58,ITER_CONT_n_59,ITER_CONT_n_60,ITER_CONT_n_61,ITER_CONT_n_62,ITER_CONT_n_63,ITER_CONT_n_64,ITER_CONT_n_65,ITER_CONT_n_66,ITER_CONT_n_67,ITER_CONT_n_68}),
.E(inst_CORDIC_FSM_v3_n_8),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({reg_val_muxX_2stage_n_4,A,reg_val_muxX_2stage_n_13,reg_val_muxX_2stage_n_14,reg_val_muxX_2stage_n_15,reg_val_muxX_2stage_n_16,reg_val_muxX_2stage_n_17,reg_val_muxX_2stage_n_18,reg_val_muxX_2stage_n_19,reg_val_muxX_2stage_n_20,reg_val_muxX_2stage_n_21,reg_val_muxX_2stage_n_22,reg_val_muxX_2stage_n_23,reg_val_muxX_2stage_n_24,reg_val_muxX_2stage_n_25,reg_val_muxX_2stage_n_26,reg_val_muxX_2stage_n_27,reg_val_muxX_2stage_n_28,reg_val_muxX_2stage_n_29,reg_val_muxX_2stage_n_30,reg_val_muxX_2stage_n_31,reg_val_muxX_2stage_n_32,reg_val_muxX_2stage_n_33,reg_val_muxX_2stage_n_34,reg_val_muxX_2stage_n_35}),
.\Q_reg[26]_0 ({reg_val_muxX_2stage_n_36,reg_val_muxX_2stage_n_37,reg_val_muxX_2stage_n_38,reg_val_muxX_2stage_n_39}),
.S({reg_val_muxX_2stage_n_0,reg_val_muxX_2stage_n_1,reg_val_muxX_2stage_n_2,reg_val_muxX_2stage_n_3}),
.\temp_reg[3] (cont_iter_out));
d_ff_en__parameterized3 reg_val_muxY_2stage
(.CLK(clk_IBUF_BUFG),
.D({reg_val_muxY_2stage_n_32,reg_val_muxY_2stage_n_33,reg_val_muxY_2stage_n_34,reg_val_muxY_2stage_n_35,reg_val_muxY_2stage_n_36,reg_val_muxY_2stage_n_37,reg_val_muxY_2stage_n_38,reg_val_muxY_2stage_n_39}),
.E(inst_CORDIC_FSM_v3_n_8),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({d_ff2_Y,reg_val_muxY_2stage_n_1,reg_val_muxY_2stage_n_2,reg_val_muxY_2stage_n_3,reg_val_muxY_2stage_n_4,reg_val_muxY_2stage_n_5,reg_val_muxY_2stage_n_6,reg_val_muxY_2stage_n_7,reg_val_muxY_2stage_n_8,reg_val_muxY_2stage_n_9,reg_val_muxY_2stage_n_10,reg_val_muxY_2stage_n_11,reg_val_muxY_2stage_n_12,reg_val_muxY_2stage_n_13,reg_val_muxY_2stage_n_14,reg_val_muxY_2stage_n_15,reg_val_muxY_2stage_n_16,reg_val_muxY_2stage_n_17,reg_val_muxY_2stage_n_18,reg_val_muxY_2stage_n_19,reg_val_muxY_2stage_n_20,reg_val_muxY_2stage_n_21,reg_val_muxY_2stage_n_22,reg_val_muxY_2stage_n_23,reg_val_muxY_2stage_n_24,reg_val_muxY_2stage_n_25,reg_val_muxY_2stage_n_26,reg_val_muxY_2stage_n_27,reg_val_muxY_2stage_n_28,reg_val_muxY_2stage_n_29,reg_val_muxY_2stage_n_30,reg_val_muxY_2stage_n_31}),
.\temp_reg[3] (cont_iter_out),
.\temp_reg[3]_0 ({ITER_CONT_n_69,ITER_CONT_n_70,ITER_CONT_n_71,ITER_CONT_n_72,ITER_CONT_n_73,ITER_CONT_n_74,ITER_CONT_n_75,ITER_CONT_n_76,ITER_CONT_n_77,ITER_CONT_n_78,ITER_CONT_n_79,ITER_CONT_n_80,ITER_CONT_n_81,ITER_CONT_n_82,ITER_CONT_n_83,ITER_CONT_n_84,ITER_CONT_n_85,ITER_CONT_n_86,ITER_CONT_n_87,ITER_CONT_n_88,ITER_CONT_n_89,ITER_CONT_n_90,ITER_CONT_n_91,ITER_CONT_n_92,ITER_CONT_n_93,ITER_CONT_n_94,ITER_CONT_n_95,ITER_CONT_n_96,ITER_CONT_n_97,ITER_CONT_n_98,ITER_CONT_n_99,ITER_CONT_n_100}));
d_ff_en__parameterized4 reg_val_muxZ_2stage
(.CLK(clk_IBUF_BUFG),
.D({ITER_CONT_n_5,ITER_CONT_n_6,ITER_CONT_n_7,ITER_CONT_n_8,ITER_CONT_n_9,ITER_CONT_n_10,ITER_CONT_n_11,ITER_CONT_n_12,ITER_CONT_n_13,ITER_CONT_n_14,ITER_CONT_n_15,ITER_CONT_n_16,ITER_CONT_n_17,ITER_CONT_n_18,ITER_CONT_n_19,ITER_CONT_n_20,ITER_CONT_n_21,ITER_CONT_n_22,ITER_CONT_n_23,ITER_CONT_n_24,ITER_CONT_n_25,ITER_CONT_n_26,ITER_CONT_n_27,ITER_CONT_n_28,ITER_CONT_n_29,ITER_CONT_n_30,ITER_CONT_n_31,ITER_CONT_n_32,ITER_CONT_n_33,ITER_CONT_n_34,ITER_CONT_n_35,ITER_CONT_n_36}),
.E(inst_CORDIC_FSM_v3_n_8),
.\FSM_sequential_state_reg_reg[1] (reset_reg_cordic),
.Q({d_ff2_Z,reg_val_muxZ_2stage_n_1,reg_val_muxZ_2stage_n_2,reg_val_muxZ_2stage_n_3,reg_val_muxZ_2stage_n_4,reg_val_muxZ_2stage_n_5,reg_val_muxZ_2stage_n_6,reg_val_muxZ_2stage_n_7,reg_val_muxZ_2stage_n_8,reg_val_muxZ_2stage_n_9,reg_val_muxZ_2stage_n_10,reg_val_muxZ_2stage_n_11,reg_val_muxZ_2stage_n_12,reg_val_muxZ_2stage_n_13,reg_val_muxZ_2stage_n_14,reg_val_muxZ_2stage_n_15,reg_val_muxZ_2stage_n_16,reg_val_muxZ_2stage_n_17,reg_val_muxZ_2stage_n_18,reg_val_muxZ_2stage_n_19,reg_val_muxZ_2stage_n_20,reg_val_muxZ_2stage_n_21,reg_val_muxZ_2stage_n_22,reg_val_muxZ_2stage_n_23,reg_val_muxZ_2stage_n_24,reg_val_muxZ_2stage_n_25,reg_val_muxZ_2stage_n_26,reg_val_muxZ_2stage_n_27,reg_val_muxZ_2stage_n_28,reg_val_muxZ_2stage_n_29,reg_val_muxZ_2stage_n_30,reg_val_muxZ_2stage_n_31}));
IBUF rst_IBUF_inst
(.I(rst),
.O(rst_IBUF));
IBUF \shift_region_flag_IBUF[0]_inst
(.I(shift_region_flag[0]),
.O(shift_region_flag_IBUF[0]));
IBUF \shift_region_flag_IBUF[1]_inst
(.I(shift_region_flag[1]),
.O(shift_region_flag_IBUF[1]));
Simple_Subt shift_x
(.D(Y),
.Q(A[6:0]),
.\Q_reg[26] ({reg_val_muxX_2stage_n_36,reg_val_muxX_2stage_n_37,reg_val_muxX_2stage_n_38,reg_val_muxX_2stage_n_39}),
.S({reg_val_muxX_2stage_n_0,reg_val_muxX_2stage_n_1,reg_val_muxX_2stage_n_2,reg_val_muxX_2stage_n_3}));
OBUF underflow_flag_OBUF_inst
(.I(underflow_flag_OBUF),
.O(underflow_flag));
OBUF zero_flag_OBUF_inst
(.I(zero_flag_OBUF),
.O(zero_flag));
endmodule
module CORDIC_FSM_v3
(AR,
out,
\FSM_sequential_state_reg_reg[0]_0 ,
E,
\Q_reg[31] ,
\Q_reg[31]_0 ,
\Q_reg[0] ,
\Q_reg[1] ,
\temp_reg[0] ,
ready_cordic_OBUF,
\Q_reg[31]_1 ,
rst_IBUF,
\FSM_sequential_state_reg_reg[2]_0 ,
CLK,
max_tick_iter,
\temp_reg[1] ,
ack_cordic_IBUF,
cont_var_out,
beg_fsm_cordic_IBUF);
output [3:0]AR;
output [2:0]out;
output [0:0]\FSM_sequential_state_reg_reg[0]_0 ;
output [0:0]E;
output [0:0]\Q_reg[31] ;
output [0:0]\Q_reg[31]_0 ;
output [0:0]\Q_reg[0] ;
output [0:0]\Q_reg[1] ;
output [0:0]\temp_reg[0] ;
output ready_cordic_OBUF;
output [0:0]\Q_reg[31]_1 ;
input rst_IBUF;
input [0:0]\FSM_sequential_state_reg_reg[2]_0 ;
input CLK;
input max_tick_iter;
input [0:0]\temp_reg[1] ;
input ack_cordic_IBUF;
input [1:0]cont_var_out;
input beg_fsm_cordic_IBUF;
wire [3:0]AR;
wire CLK;
wire [0:0]E;
wire \FSM_sequential_state_reg[0]_i_1_n_0 ;
wire \FSM_sequential_state_reg[0]_i_2_n_0 ;
wire \FSM_sequential_state_reg[1]_i_1_n_0 ;
wire \FSM_sequential_state_reg[2]_i_1_n_0 ;
wire [0:0]\FSM_sequential_state_reg_reg[0]_0 ;
wire [0:0]\FSM_sequential_state_reg_reg[2]_0 ;
wire [0:0]\Q_reg[0] ;
wire [0:0]\Q_reg[1] ;
wire [0:0]\Q_reg[31] ;
wire [0:0]\Q_reg[31]_0 ;
wire [0:0]\Q_reg[31]_1 ;
wire ack_cordic_IBUF;
wire beg_fsm_cordic_IBUF;
wire [1:0]cont_var_out;
wire max_tick_iter;
(* RTL_KEEP = "yes" *) wire [2:0]out;
wire ready_cordic_OBUF;
wire rst_IBUF;
wire [0:0]\temp_reg[0] ;
wire [0:0]\temp_reg[1] ;
LUT6 #(
.INIT(64'h02A2FFFF02A20000))
\FSM_sequential_state_reg[0]_i_1
(.I0(out[2]),
.I1(\temp_reg[1] ),
.I2(out[1]),
.I3(ack_cordic_IBUF),
.I4(out[0]),
.I5(\FSM_sequential_state_reg[0]_i_2_n_0 ),
.O(\FSM_sequential_state_reg[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB888FFFFB888CCCC))
\FSM_sequential_state_reg[0]_i_2
(.I0(max_tick_iter),
.I1(out[1]),
.I2(cont_var_out[1]),
.I3(cont_var_out[0]),
.I4(out[2]),
.I5(beg_fsm_cordic_IBUF),
.O(\FSM_sequential_state_reg[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h7C3C4C3C))
\FSM_sequential_state_reg[1]_i_1
(.I0(ack_cordic_IBUF),
.I1(out[1]),
.I2(out[0]),
.I3(out[2]),
.I4(\temp_reg[1] ),
.O(\FSM_sequential_state_reg[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'h74FFCC00))
\FSM_sequential_state_reg[2]_i_1
(.I0(ack_cordic_IBUF),
.I1(out[0]),
.I2(max_tick_iter),
.I3(out[1]),
.I4(out[2]),
.O(\FSM_sequential_state_reg[2]_i_1_n_0 ));
LUT4 #(
.INIT(16'hFF08))
\FSM_sequential_state_reg[2]_i_2__0
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(\FSM_sequential_state_reg_reg[0]_0 ));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(rst_IBUF),
.D(\FSM_sequential_state_reg[0]_i_1_n_0 ),
.Q(out[0]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[1]
(.C(CLK),
.CE(1'b1),
.CLR(rst_IBUF),
.D(\FSM_sequential_state_reg[1]_i_1_n_0 ),
.Q(out[1]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[2]
(.C(CLK),
.CE(1'b1),
.CLR(rst_IBUF),
.D(\FSM_sequential_state_reg[2]_i_1_n_0 ),
.Q(out[2]));
LUT4 #(
.INIT(16'hFF08))
\Q[0]_i_1__7
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(AR[2]));
LUT4 #(
.INIT(16'hFF08))
\Q[14]_i_2
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(AR[3]));
LUT3 #(
.INIT(8'h02))
\Q[1]_i_1
(.I0(out[0]),
.I1(out[2]),
.I2(out[1]),
.O(\Q_reg[1] ));
LUT3 #(
.INIT(8'h01))
\Q[1]_i_2
(.I0(out[1]),
.I1(out[0]),
.I2(out[2]),
.O(\Q_reg[31]_1 ));
LUT3 #(
.INIT(8'h40))
\Q[29]_i_1
(.I0(out[2]),
.I1(out[0]),
.I2(out[1]),
.O(\Q_reg[0] ));
LUT4 #(
.INIT(16'hA800))
\Q[31]_i_1
(.I0(out[2]),
.I1(out[0]),
.I2(max_tick_iter),
.I3(out[1]),
.O(\Q_reg[31]_0 ));
LUT3 #(
.INIT(8'h02))
\Q[31]_i_1__7
(.I0(out[1]),
.I1(out[0]),
.I2(out[2]),
.O(E));
LUT3 #(
.INIT(8'h04))
\Q[31]_i_1__8
(.I0(out[1]),
.I1(out[2]),
.I2(\FSM_sequential_state_reg_reg[2]_0 ),
.O(\Q_reg[31] ));
LUT4 #(
.INIT(16'hFF08))
\Q[31]_i_2
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(AR[1]));
LUT4 #(
.INIT(16'hFF08))
\Q[6]_i_2
(.I0(out[1]),
.I1(out[2]),
.I2(out[0]),
.I3(rst_IBUF),
.O(AR[0]));
LUT3 #(
.INIT(8'h80))
ready_cordic_OBUF_inst_i_1
(.I0(out[1]),
.I1(out[0]),
.I2(out[2]),
.O(ready_cordic_OBUF));
LUT3 #(
.INIT(8'h40))
\temp[3]_i_1
(.I0(out[0]),
.I1(out[2]),
.I2(out[1]),
.O(\temp_reg[0] ));
endmodule
module Comparator
(CO,
\Q_reg[2] ,
\Q_reg[6] ,
S,
\Q_reg[14] ,
\Q_reg[14]_0 ,
\Q_reg[22] ,
\Q_reg[22]_0 ,
DI,
\Q_reg[30] ,
\Q_reg[9] ,
\Q_reg[21] ,
\Q_reg[30]_0 );
output [0:0]CO;
output [0:0]\Q_reg[2] ;
input [3:0]\Q_reg[6] ;
input [3:0]S;
input [3:0]\Q_reg[14] ;
input [3:0]\Q_reg[14]_0 ;
input [3:0]\Q_reg[22] ;
input [3:0]\Q_reg[22]_0 ;
input [3:0]DI;
input [3:0]\Q_reg[30] ;
input [3:0]\Q_reg[9] ;
input [3:0]\Q_reg[21] ;
input [2:0]\Q_reg[30]_0 ;
wire [0:0]CO;
wire [3:0]DI;
wire [3:0]\Q_reg[14] ;
wire [3:0]\Q_reg[14]_0 ;
wire [3:0]\Q_reg[21] ;
wire [3:0]\Q_reg[22] ;
wire [3:0]\Q_reg[22]_0 ;
wire [0:0]\Q_reg[2] ;
wire [3:0]\Q_reg[30] ;
wire [2:0]\Q_reg[30]_0 ;
wire [3:0]\Q_reg[6] ;
wire [3:0]\Q_reg[9] ;
wire [3:0]S;
wire eqXY_o_carry__0_n_0;
wire eqXY_o_carry__0_n_1;
wire eqXY_o_carry__0_n_2;
wire eqXY_o_carry__0_n_3;
wire eqXY_o_carry__1_n_2;
wire eqXY_o_carry__1_n_3;
wire eqXY_o_carry_n_0;
wire eqXY_o_carry_n_1;
wire eqXY_o_carry_n_2;
wire eqXY_o_carry_n_3;
wire gtXY_o_carry__0_n_0;
wire gtXY_o_carry__0_n_1;
wire gtXY_o_carry__0_n_2;
wire gtXY_o_carry__0_n_3;
wire gtXY_o_carry__1_n_0;
wire gtXY_o_carry__1_n_1;
wire gtXY_o_carry__1_n_2;
wire gtXY_o_carry__1_n_3;
wire gtXY_o_carry__2_n_1;
wire gtXY_o_carry__2_n_2;
wire gtXY_o_carry__2_n_3;
wire gtXY_o_carry_n_0;
wire gtXY_o_carry_n_1;
wire gtXY_o_carry_n_2;
wire gtXY_o_carry_n_3;
wire [3:0]NLW_eqXY_o_carry_O_UNCONNECTED;
wire [3:0]NLW_eqXY_o_carry__0_O_UNCONNECTED;
wire [3:3]NLW_eqXY_o_carry__1_CO_UNCONNECTED;
wire [3:0]NLW_eqXY_o_carry__1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__0_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__2_O_UNCONNECTED;
CARRY4 eqXY_o_carry
(.CI(1'b0),
.CO({eqXY_o_carry_n_0,eqXY_o_carry_n_1,eqXY_o_carry_n_2,eqXY_o_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry_O_UNCONNECTED[3:0]),
.S(\Q_reg[9] ));
CARRY4 eqXY_o_carry__0
(.CI(eqXY_o_carry_n_0),
.CO({eqXY_o_carry__0_n_0,eqXY_o_carry__0_n_1,eqXY_o_carry__0_n_2,eqXY_o_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry__0_O_UNCONNECTED[3:0]),
.S(\Q_reg[21] ));
CARRY4 eqXY_o_carry__1
(.CI(eqXY_o_carry__0_n_0),
.CO({NLW_eqXY_o_carry__1_CO_UNCONNECTED[3],\Q_reg[2] ,eqXY_o_carry__1_n_2,eqXY_o_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry__1_O_UNCONNECTED[3:0]),
.S({1'b0,\Q_reg[30]_0 }));
CARRY4 gtXY_o_carry
(.CI(1'b0),
.CO({gtXY_o_carry_n_0,gtXY_o_carry_n_1,gtXY_o_carry_n_2,gtXY_o_carry_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[6] ),
.O(NLW_gtXY_o_carry_O_UNCONNECTED[3:0]),
.S(S));
CARRY4 gtXY_o_carry__0
(.CI(gtXY_o_carry_n_0),
.CO({gtXY_o_carry__0_n_0,gtXY_o_carry__0_n_1,gtXY_o_carry__0_n_2,gtXY_o_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[14] ),
.O(NLW_gtXY_o_carry__0_O_UNCONNECTED[3:0]),
.S(\Q_reg[14]_0 ));
CARRY4 gtXY_o_carry__1
(.CI(gtXY_o_carry__0_n_0),
.CO({gtXY_o_carry__1_n_0,gtXY_o_carry__1_n_1,gtXY_o_carry__1_n_2,gtXY_o_carry__1_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[22] ),
.O(NLW_gtXY_o_carry__1_O_UNCONNECTED[3:0]),
.S(\Q_reg[22]_0 ));
CARRY4 gtXY_o_carry__2
(.CI(gtXY_o_carry__1_n_0),
.CO({CO,gtXY_o_carry__2_n_1,gtXY_o_carry__2_n_2,gtXY_o_carry__2_n_3}),
.CYINIT(1'b0),
.DI(DI),
.O(NLW_gtXY_o_carry__2_O_UNCONNECTED[3:0]),
.S(\Q_reg[30] ));
endmodule
module FPU_PIPELINED_FPADDSUB
(ready_add_subt,
Q,
\Q_reg[31] ,
overflow_flag,
out,
CLK,
AR,
E,
op_add_subt,
\FSM_sequential_state_reg_reg[1] ,
D,
\Q_reg[31]_0 ,
\FSM_sequential_state_reg_reg[2] );
output ready_add_subt;
output [0:0]Q;
output [31:0]\Q_reg[31] ;
output [2:0]overflow_flag;
output [0:0]out;
input CLK;
input [3:0]AR;
input [0:0]E;
input op_add_subt;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
input [31:0]D;
input [31:0]\Q_reg[31]_0 ;
input [1:0]\FSM_sequential_state_reg_reg[2] ;
wire ADD_OVRFLW_NRM;
wire ADD_OVRFLW_NRM2;
wire [3:0]AR;
wire CLK;
wire [31:0]D;
wire [24:2]DMP_mant_SFG_SWR;
wire [25:0]\Data_array_SWR[2]_1 ;
wire [25:18]\Data_array_SWR[3]_0 ;
wire [15:14]\Data_array_SWR[4]_4 ;
wire [17:2]\Data_array_SWR[5]_2 ;
wire [25:1]\Data_array_SWR[6]_3 ;
wire [0:0]E;
wire EXP_STAGE_DMP_n_1;
wire EXP_STAGE_DMP_n_10;
wire EXP_STAGE_DMP_n_11;
wire EXP_STAGE_DMP_n_12;
wire EXP_STAGE_DMP_n_13;
wire EXP_STAGE_DMP_n_14;
wire EXP_STAGE_DMP_n_15;
wire EXP_STAGE_DMP_n_16;
wire EXP_STAGE_DMP_n_17;
wire EXP_STAGE_DMP_n_18;
wire EXP_STAGE_DMP_n_19;
wire EXP_STAGE_DMP_n_2;
wire EXP_STAGE_DMP_n_20;
wire EXP_STAGE_DMP_n_21;
wire EXP_STAGE_DMP_n_22;
wire EXP_STAGE_DMP_n_23;
wire EXP_STAGE_DMP_n_24;
wire EXP_STAGE_DMP_n_25;
wire EXP_STAGE_DMP_n_26;
wire EXP_STAGE_DMP_n_27;
wire EXP_STAGE_DMP_n_28;
wire EXP_STAGE_DMP_n_29;
wire EXP_STAGE_DMP_n_3;
wire EXP_STAGE_DMP_n_30;
wire EXP_STAGE_DMP_n_31;
wire EXP_STAGE_DMP_n_32;
wire EXP_STAGE_DMP_n_4;
wire EXP_STAGE_DMP_n_5;
wire EXP_STAGE_DMP_n_6;
wire EXP_STAGE_DMP_n_7;
wire EXP_STAGE_DMP_n_8;
wire EXP_STAGE_DMP_n_9;
wire EXP_STAGE_DmP_n_10;
wire EXP_STAGE_DmP_n_11;
wire EXP_STAGE_DmP_n_12;
wire EXP_STAGE_DmP_n_13;
wire EXP_STAGE_DmP_n_14;
wire EXP_STAGE_DmP_n_15;
wire EXP_STAGE_DmP_n_16;
wire EXP_STAGE_DmP_n_17;
wire EXP_STAGE_DmP_n_18;
wire EXP_STAGE_DmP_n_19;
wire EXP_STAGE_DmP_n_20;
wire EXP_STAGE_DmP_n_21;
wire EXP_STAGE_DmP_n_22;
wire EXP_STAGE_DmP_n_23;
wire EXP_STAGE_DmP_n_24;
wire EXP_STAGE_DmP_n_25;
wire EXP_STAGE_DmP_n_26;
wire EXP_STAGE_DmP_n_27;
wire EXP_STAGE_DmP_n_28;
wire EXP_STAGE_DmP_n_3;
wire EXP_STAGE_DmP_n_4;
wire EXP_STAGE_DmP_n_5;
wire EXP_STAGE_DmP_n_6;
wire EXP_STAGE_DmP_n_7;
wire EXP_STAGE_DmP_n_8;
wire EXP_STAGE_DmP_n_9;
wire EXP_STAGE_FLAGS_n_0;
wire EXP_STAGE_FLAGS_n_1;
wire EXP_STAGE_FLAGS_n_2;
wire FSM_enable_input_internal;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [1:0]\FSM_sequential_state_reg_reg[2] ;
wire INPUT_STAGE_FLAGS_n_1;
wire INPUT_STAGE_OPERANDX_n_0;
wire INPUT_STAGE_OPERANDX_n_1;
wire INPUT_STAGE_OPERANDX_n_10;
wire INPUT_STAGE_OPERANDX_n_11;
wire INPUT_STAGE_OPERANDX_n_12;
wire INPUT_STAGE_OPERANDX_n_13;
wire INPUT_STAGE_OPERANDX_n_14;
wire INPUT_STAGE_OPERANDX_n_15;
wire INPUT_STAGE_OPERANDX_n_16;
wire INPUT_STAGE_OPERANDX_n_17;
wire INPUT_STAGE_OPERANDX_n_18;
wire INPUT_STAGE_OPERANDX_n_19;
wire INPUT_STAGE_OPERANDX_n_2;
wire INPUT_STAGE_OPERANDX_n_20;
wire INPUT_STAGE_OPERANDX_n_21;
wire INPUT_STAGE_OPERANDX_n_22;
wire INPUT_STAGE_OPERANDX_n_23;
wire INPUT_STAGE_OPERANDX_n_24;
wire INPUT_STAGE_OPERANDX_n_25;
wire INPUT_STAGE_OPERANDX_n_26;
wire INPUT_STAGE_OPERANDX_n_27;
wire INPUT_STAGE_OPERANDX_n_28;
wire INPUT_STAGE_OPERANDX_n_29;
wire INPUT_STAGE_OPERANDX_n_3;
wire INPUT_STAGE_OPERANDX_n_30;
wire INPUT_STAGE_OPERANDX_n_31;
wire INPUT_STAGE_OPERANDX_n_32;
wire INPUT_STAGE_OPERANDX_n_33;
wire INPUT_STAGE_OPERANDX_n_34;
wire INPUT_STAGE_OPERANDX_n_35;
wire INPUT_STAGE_OPERANDX_n_36;
wire INPUT_STAGE_OPERANDX_n_37;
wire INPUT_STAGE_OPERANDX_n_38;
wire INPUT_STAGE_OPERANDX_n_39;
wire INPUT_STAGE_OPERANDX_n_40;
wire INPUT_STAGE_OPERANDX_n_41;
wire INPUT_STAGE_OPERANDX_n_42;
wire INPUT_STAGE_OPERANDX_n_43;
wire INPUT_STAGE_OPERANDX_n_44;
wire INPUT_STAGE_OPERANDX_n_45;
wire INPUT_STAGE_OPERANDX_n_46;
wire INPUT_STAGE_OPERANDX_n_47;
wire INPUT_STAGE_OPERANDX_n_48;
wire INPUT_STAGE_OPERANDX_n_49;
wire INPUT_STAGE_OPERANDX_n_5;
wire INPUT_STAGE_OPERANDX_n_50;
wire INPUT_STAGE_OPERANDX_n_51;
wire INPUT_STAGE_OPERANDX_n_52;
wire INPUT_STAGE_OPERANDX_n_53;
wire INPUT_STAGE_OPERANDX_n_54;
wire INPUT_STAGE_OPERANDX_n_55;
wire INPUT_STAGE_OPERANDX_n_56;
wire INPUT_STAGE_OPERANDX_n_57;
wire INPUT_STAGE_OPERANDX_n_58;
wire INPUT_STAGE_OPERANDX_n_59;
wire INPUT_STAGE_OPERANDX_n_6;
wire INPUT_STAGE_OPERANDX_n_60;
wire INPUT_STAGE_OPERANDX_n_61;
wire INPUT_STAGE_OPERANDX_n_62;
wire INPUT_STAGE_OPERANDX_n_63;
wire INPUT_STAGE_OPERANDX_n_64;
wire INPUT_STAGE_OPERANDX_n_65;
wire INPUT_STAGE_OPERANDX_n_66;
wire INPUT_STAGE_OPERANDX_n_67;
wire INPUT_STAGE_OPERANDX_n_68;
wire INPUT_STAGE_OPERANDX_n_69;
wire INPUT_STAGE_OPERANDX_n_7;
wire INPUT_STAGE_OPERANDX_n_70;
wire INPUT_STAGE_OPERANDX_n_71;
wire INPUT_STAGE_OPERANDX_n_72;
wire INPUT_STAGE_OPERANDX_n_8;
wire INPUT_STAGE_OPERANDX_n_9;
wire INPUT_STAGE_OPERANDY_n_0;
wire INPUT_STAGE_OPERANDY_n_10;
wire INPUT_STAGE_OPERANDY_n_11;
wire INPUT_STAGE_OPERANDY_n_12;
wire INPUT_STAGE_OPERANDY_n_13;
wire INPUT_STAGE_OPERANDY_n_14;
wire INPUT_STAGE_OPERANDY_n_15;
wire INPUT_STAGE_OPERANDY_n_16;
wire INPUT_STAGE_OPERANDY_n_17;
wire INPUT_STAGE_OPERANDY_n_18;
wire INPUT_STAGE_OPERANDY_n_19;
wire INPUT_STAGE_OPERANDY_n_2;
wire INPUT_STAGE_OPERANDY_n_20;
wire INPUT_STAGE_OPERANDY_n_21;
wire INPUT_STAGE_OPERANDY_n_22;
wire INPUT_STAGE_OPERANDY_n_23;
wire INPUT_STAGE_OPERANDY_n_24;
wire INPUT_STAGE_OPERANDY_n_25;
wire INPUT_STAGE_OPERANDY_n_26;
wire INPUT_STAGE_OPERANDY_n_27;
wire INPUT_STAGE_OPERANDY_n_28;
wire INPUT_STAGE_OPERANDY_n_29;
wire INPUT_STAGE_OPERANDY_n_3;
wire INPUT_STAGE_OPERANDY_n_30;
wire INPUT_STAGE_OPERANDY_n_31;
wire INPUT_STAGE_OPERANDY_n_32;
wire INPUT_STAGE_OPERANDY_n_33;
wire INPUT_STAGE_OPERANDY_n_4;
wire INPUT_STAGE_OPERANDY_n_5;
wire INPUT_STAGE_OPERANDY_n_6;
wire INPUT_STAGE_OPERANDY_n_7;
wire INPUT_STAGE_OPERANDY_n_8;
wire INPUT_STAGE_OPERANDY_n_9;
wire [4:0]LZD_raw_out_EWR;
wire MuxXY_n_0;
wire MuxXY_n_1;
wire MuxXY_n_10;
wire MuxXY_n_11;
wire MuxXY_n_12;
wire MuxXY_n_13;
wire MuxXY_n_14;
wire MuxXY_n_15;
wire MuxXY_n_16;
wire MuxXY_n_17;
wire MuxXY_n_18;
wire MuxXY_n_19;
wire MuxXY_n_2;
wire MuxXY_n_20;
wire MuxXY_n_21;
wire MuxXY_n_22;
wire MuxXY_n_23;
wire MuxXY_n_24;
wire MuxXY_n_25;
wire MuxXY_n_26;
wire MuxXY_n_27;
wire MuxXY_n_28;
wire MuxXY_n_29;
wire MuxXY_n_3;
wire MuxXY_n_30;
wire MuxXY_n_31;
wire MuxXY_n_32;
wire MuxXY_n_33;
wire MuxXY_n_34;
wire MuxXY_n_35;
wire MuxXY_n_36;
wire MuxXY_n_37;
wire MuxXY_n_38;
wire MuxXY_n_39;
wire MuxXY_n_4;
wire MuxXY_n_40;
wire MuxXY_n_41;
wire MuxXY_n_42;
wire MuxXY_n_43;
wire MuxXY_n_44;
wire MuxXY_n_45;
wire MuxXY_n_46;
wire MuxXY_n_47;
wire MuxXY_n_48;
wire MuxXY_n_49;
wire MuxXY_n_5;
wire MuxXY_n_50;
wire MuxXY_n_51;
wire MuxXY_n_52;
wire MuxXY_n_53;
wire MuxXY_n_54;
wire MuxXY_n_55;
wire MuxXY_n_56;
wire MuxXY_n_57;
wire MuxXY_n_58;
wire MuxXY_n_6;
wire MuxXY_n_7;
wire MuxXY_n_8;
wire MuxXY_n_9;
wire NRM_STAGE_DMP_exp_n_0;
wire NRM_STAGE_DMP_exp_n_1;
wire NRM_STAGE_DMP_exp_n_2;
wire NRM_STAGE_DMP_exp_n_3;
wire NRM_STAGE_DMP_exp_n_4;
wire NRM_STAGE_DMP_exp_n_5;
wire NRM_STAGE_DMP_exp_n_6;
wire NRM_STAGE_DMP_exp_n_7;
wire NRM_STAGE_FLAGS_n_2;
wire NRM_STAGE_FLAGS_n_3;
wire NRM_STAGE_FLAGS_n_4;
wire NRM_STAGE_Raw_mant_n_30;
wire OP_FLAG_INIT;
wire OVRFLW_FLAG_FRMT;
wire [0:0]Q;
wire \Q[12]_i_10_n_0 ;
wire \Q[12]_i_11_n_0 ;
wire \Q[12]_i_8_n_0 ;
wire \Q[12]_i_9_n_0 ;
wire \Q[16]_i_10_n_0 ;
wire \Q[16]_i_11_n_0 ;
wire \Q[16]_i_8_n_0 ;
wire \Q[16]_i_9_n_0 ;
wire \Q[20]_i_10_n_0 ;
wire \Q[20]_i_11_n_0 ;
wire \Q[20]_i_8_n_0 ;
wire \Q[20]_i_9_n_0 ;
wire \Q[24]_i_10_n_0 ;
wire \Q[24]_i_11_n_0 ;
wire \Q[24]_i_8_n_0 ;
wire \Q[24]_i_9_n_0 ;
wire \Q[4]_i_10_n_0 ;
wire \Q[4]_i_11_n_0 ;
wire \Q[4]_i_9_n_0 ;
wire \Q[8]_i_10_n_0 ;
wire \Q[8]_i_11_n_0 ;
wire \Q[8]_i_8__0_n_0 ;
wire \Q[8]_i_9__0_n_0 ;
wire [31:0]\Q_reg[31] ;
wire [31:0]\Q_reg[31]_0 ;
wire [25:0]Raw_mant_SGF;
wire SFT2FRMT_STAGE_FLAGS_n_1;
wire SFT2FRMT_STAGE_FLAGS_n_3;
wire SFT2FRMT_STAGE_VARS_n_0;
wire SFT2FRMT_STAGE_VARS_n_1;
wire SFT2FRMT_STAGE_VARS_n_10;
wire SFT2FRMT_STAGE_VARS_n_11;
wire SFT2FRMT_STAGE_VARS_n_12;
wire SFT2FRMT_STAGE_VARS_n_13;
wire SFT2FRMT_STAGE_VARS_n_14;
wire SFT2FRMT_STAGE_VARS_n_15;
wire SFT2FRMT_STAGE_VARS_n_16;
wire SFT2FRMT_STAGE_VARS_n_17;
wire SFT2FRMT_STAGE_VARS_n_18;
wire SFT2FRMT_STAGE_VARS_n_19;
wire SFT2FRMT_STAGE_VARS_n_2;
wire SFT2FRMT_STAGE_VARS_n_20;
wire SFT2FRMT_STAGE_VARS_n_21;
wire SFT2FRMT_STAGE_VARS_n_22;
wire SFT2FRMT_STAGE_VARS_n_23;
wire SFT2FRMT_STAGE_VARS_n_3;
wire SFT2FRMT_STAGE_VARS_n_4;
wire SFT2FRMT_STAGE_VARS_n_5;
wire SFT2FRMT_STAGE_VARS_n_6;
wire SFT2FRMT_STAGE_VARS_n_7;
wire SFT2FRMT_STAGE_VARS_n_8;
wire SFT2FRMT_STAGE_VARS_n_9;
wire SGF_STAGE_DMP_n_0;
wire SGF_STAGE_DMP_n_1;
wire SGF_STAGE_DMP_n_10;
wire SGF_STAGE_DMP_n_11;
wire SGF_STAGE_DMP_n_2;
wire SGF_STAGE_DMP_n_3;
wire SGF_STAGE_DMP_n_35;
wire SGF_STAGE_DMP_n_36;
wire SGF_STAGE_DMP_n_37;
wire SGF_STAGE_DMP_n_38;
wire SGF_STAGE_DMP_n_39;
wire SGF_STAGE_DMP_n_4;
wire SGF_STAGE_DMP_n_40;
wire SGF_STAGE_DMP_n_41;
wire SGF_STAGE_DMP_n_42;
wire SGF_STAGE_DMP_n_43;
wire SGF_STAGE_DMP_n_44;
wire SGF_STAGE_DMP_n_45;
wire SGF_STAGE_DMP_n_46;
wire SGF_STAGE_DMP_n_47;
wire SGF_STAGE_DMP_n_48;
wire SGF_STAGE_DMP_n_49;
wire SGF_STAGE_DMP_n_5;
wire SGF_STAGE_DMP_n_50;
wire SGF_STAGE_DMP_n_51;
wire SGF_STAGE_DMP_n_52;
wire SGF_STAGE_DMP_n_53;
wire SGF_STAGE_DMP_n_54;
wire SGF_STAGE_DMP_n_55;
wire SGF_STAGE_DMP_n_6;
wire SGF_STAGE_DMP_n_7;
wire SGF_STAGE_DMP_n_8;
wire SGF_STAGE_DMP_n_9;
wire SGF_STAGE_DmP_mant_n_0;
wire SGF_STAGE_DmP_mant_n_1;
wire SGF_STAGE_DmP_mant_n_10;
wire SGF_STAGE_DmP_mant_n_11;
wire SGF_STAGE_DmP_mant_n_12;
wire SGF_STAGE_DmP_mant_n_13;
wire SGF_STAGE_DmP_mant_n_14;
wire SGF_STAGE_DmP_mant_n_15;
wire SGF_STAGE_DmP_mant_n_16;
wire SGF_STAGE_DmP_mant_n_17;
wire SGF_STAGE_DmP_mant_n_18;
wire SGF_STAGE_DmP_mant_n_19;
wire SGF_STAGE_DmP_mant_n_2;
wire SGF_STAGE_DmP_mant_n_20;
wire SGF_STAGE_DmP_mant_n_21;
wire SGF_STAGE_DmP_mant_n_22;
wire SGF_STAGE_DmP_mant_n_24;
wire SGF_STAGE_DmP_mant_n_25;
wire SGF_STAGE_DmP_mant_n_26;
wire SGF_STAGE_DmP_mant_n_27;
wire SGF_STAGE_DmP_mant_n_28;
wire SGF_STAGE_DmP_mant_n_29;
wire SGF_STAGE_DmP_mant_n_3;
wire SGF_STAGE_DmP_mant_n_30;
wire SGF_STAGE_DmP_mant_n_31;
wire SGF_STAGE_DmP_mant_n_32;
wire SGF_STAGE_DmP_mant_n_33;
wire SGF_STAGE_DmP_mant_n_34;
wire SGF_STAGE_DmP_mant_n_35;
wire SGF_STAGE_DmP_mant_n_36;
wire SGF_STAGE_DmP_mant_n_37;
wire SGF_STAGE_DmP_mant_n_38;
wire SGF_STAGE_DmP_mant_n_39;
wire SGF_STAGE_DmP_mant_n_4;
wire SGF_STAGE_DmP_mant_n_40;
wire SGF_STAGE_DmP_mant_n_41;
wire SGF_STAGE_DmP_mant_n_42;
wire SGF_STAGE_DmP_mant_n_43;
wire SGF_STAGE_DmP_mant_n_44;
wire SGF_STAGE_DmP_mant_n_45;
wire SGF_STAGE_DmP_mant_n_46;
wire SGF_STAGE_DmP_mant_n_47;
wire SGF_STAGE_DmP_mant_n_48;
wire SGF_STAGE_DmP_mant_n_49;
wire SGF_STAGE_DmP_mant_n_5;
wire SGF_STAGE_DmP_mant_n_51;
wire SGF_STAGE_DmP_mant_n_6;
wire SGF_STAGE_DmP_mant_n_7;
wire SGF_STAGE_DmP_mant_n_8;
wire SGF_STAGE_DmP_mant_n_9;
wire SGF_STAGE_FLAGS_n_0;
wire SGF_STAGE_FLAGS_n_1;
wire SHT1_STAGE_DMP_n_0;
wire SHT1_STAGE_DMP_n_1;
wire SHT1_STAGE_DMP_n_10;
wire SHT1_STAGE_DMP_n_11;
wire SHT1_STAGE_DMP_n_12;
wire SHT1_STAGE_DMP_n_13;
wire SHT1_STAGE_DMP_n_14;
wire SHT1_STAGE_DMP_n_15;
wire SHT1_STAGE_DMP_n_16;
wire SHT1_STAGE_DMP_n_17;
wire SHT1_STAGE_DMP_n_18;
wire SHT1_STAGE_DMP_n_19;
wire SHT1_STAGE_DMP_n_2;
wire SHT1_STAGE_DMP_n_20;
wire SHT1_STAGE_DMP_n_21;
wire SHT1_STAGE_DMP_n_22;
wire SHT1_STAGE_DMP_n_23;
wire SHT1_STAGE_DMP_n_24;
wire SHT1_STAGE_DMP_n_25;
wire SHT1_STAGE_DMP_n_26;
wire SHT1_STAGE_DMP_n_27;
wire SHT1_STAGE_DMP_n_28;
wire SHT1_STAGE_DMP_n_29;
wire SHT1_STAGE_DMP_n_3;
wire SHT1_STAGE_DMP_n_30;
wire SHT1_STAGE_DMP_n_4;
wire SHT1_STAGE_DMP_n_5;
wire SHT1_STAGE_DMP_n_6;
wire SHT1_STAGE_DMP_n_7;
wire SHT1_STAGE_DMP_n_8;
wire SHT1_STAGE_DMP_n_9;
wire SHT1_STAGE_DmP_mant_n_0;
wire SHT1_STAGE_DmP_mant_n_1;
wire SHT1_STAGE_DmP_mant_n_10;
wire SHT1_STAGE_DmP_mant_n_11;
wire SHT1_STAGE_DmP_mant_n_12;
wire SHT1_STAGE_DmP_mant_n_13;
wire SHT1_STAGE_DmP_mant_n_14;
wire SHT1_STAGE_DmP_mant_n_15;
wire SHT1_STAGE_DmP_mant_n_16;
wire SHT1_STAGE_DmP_mant_n_17;
wire SHT1_STAGE_DmP_mant_n_18;
wire SHT1_STAGE_DmP_mant_n_19;
wire SHT1_STAGE_DmP_mant_n_2;
wire SHT1_STAGE_DmP_mant_n_20;
wire SHT1_STAGE_DmP_mant_n_21;
wire SHT1_STAGE_DmP_mant_n_22;
wire SHT1_STAGE_DmP_mant_n_3;
wire SHT1_STAGE_DmP_mant_n_4;
wire SHT1_STAGE_DmP_mant_n_5;
wire SHT1_STAGE_DmP_mant_n_6;
wire SHT1_STAGE_DmP_mant_n_7;
wire SHT1_STAGE_DmP_mant_n_8;
wire SHT1_STAGE_DmP_mant_n_9;
wire SHT1_STAGE_FLAGS_n_0;
wire SHT1_STAGE_FLAGS_n_1;
wire SHT1_STAGE_FLAGS_n_2;
wire SHT1_STAGE_sft_amount_n_0;
wire SHT2_SHIFT_DATA_n_0;
wire SHT2_SHIFT_DATA_n_1;
wire SHT2_SHIFT_DATA_n_2;
wire SHT2_STAGE_DMP_n_0;
wire SHT2_STAGE_DMP_n_1;
wire SHT2_STAGE_DMP_n_10;
wire SHT2_STAGE_DMP_n_11;
wire SHT2_STAGE_DMP_n_12;
wire SHT2_STAGE_DMP_n_13;
wire SHT2_STAGE_DMP_n_14;
wire SHT2_STAGE_DMP_n_15;
wire SHT2_STAGE_DMP_n_16;
wire SHT2_STAGE_DMP_n_17;
wire SHT2_STAGE_DMP_n_18;
wire SHT2_STAGE_DMP_n_19;
wire SHT2_STAGE_DMP_n_2;
wire SHT2_STAGE_DMP_n_20;
wire SHT2_STAGE_DMP_n_21;
wire SHT2_STAGE_DMP_n_22;
wire SHT2_STAGE_DMP_n_23;
wire SHT2_STAGE_DMP_n_24;
wire SHT2_STAGE_DMP_n_25;
wire SHT2_STAGE_DMP_n_26;
wire SHT2_STAGE_DMP_n_27;
wire SHT2_STAGE_DMP_n_28;
wire SHT2_STAGE_DMP_n_29;
wire SHT2_STAGE_DMP_n_3;
wire SHT2_STAGE_DMP_n_30;
wire SHT2_STAGE_DMP_n_4;
wire SHT2_STAGE_DMP_n_5;
wire SHT2_STAGE_DMP_n_6;
wire SHT2_STAGE_DMP_n_7;
wire SHT2_STAGE_DMP_n_8;
wire SHT2_STAGE_DMP_n_9;
wire SHT2_STAGE_FLAGS_n_0;
wire SHT2_STAGE_FLAGS_n_1;
wire SHT2_STAGE_FLAGS_n_2;
wire SHT2_STAGE_SHFTVARS1_n_0;
wire SHT2_STAGE_SHFTVARS1_n_1;
wire SHT2_STAGE_SHFTVARS1_n_10;
wire SHT2_STAGE_SHFTVARS1_n_11;
wire SHT2_STAGE_SHFTVARS1_n_12;
wire SHT2_STAGE_SHFTVARS1_n_13;
wire SHT2_STAGE_SHFTVARS1_n_2;
wire SHT2_STAGE_SHFTVARS1_n_3;
wire SHT2_STAGE_SHFTVARS1_n_4;
wire SHT2_STAGE_SHFTVARS1_n_5;
wire SHT2_STAGE_SHFTVARS1_n_6;
wire SHT2_STAGE_SHFTVARS1_n_7;
wire SHT2_STAGE_SHFTVARS1_n_8;
wire SHT2_STAGE_SHFTVARS1_n_9;
wire SHT2_STAGE_SHFTVARS2_n_0;
wire SHT2_STAGE_SHFTVARS2_n_1;
wire SHT2_STAGE_SHFTVARS2_n_2;
wire SHT2_STAGE_SHFTVARS2_n_3;
wire SHT2_STAGE_SHFTVARS2_n_4;
wire SHT2_STAGE_SHFTVARS2_n_5;
wire SHT2_STAGE_SHFTVARS2_n_7;
wire SIGN_FLAG_INIT;
wire [4:1]Shift_amount_EXP_EW;
wire [2:0]Shift_amount_SHT1_EWR;
wire [1:1]Shift_reg_FLAGS_7;
wire UNDRFLW_FLAG_FRMT;
wire _inferred__1_carry__0_n_0;
wire _inferred__1_carry__0_n_1;
wire _inferred__1_carry__0_n_2;
wire _inferred__1_carry__0_n_3;
wire _inferred__1_carry_n_0;
wire _inferred__1_carry_n_1;
wire _inferred__1_carry_n_2;
wire _inferred__1_carry_n_3;
wire bit_shift_SHT1;
wire enable_shift_reg;
wire eqXY;
wire [8:0]exp_rslt_NRM2_EW1;
wire [31:31]formatted_number_W;
wire gtXY;
wire inst_ShiftRegister_n_1;
wire inst_ShiftRegister_n_2;
wire inst_ShiftRegister_n_4;
wire inst_ShiftRegister_n_6;
wire inst_ShiftRegister_n_7;
wire intAS;
wire [31:31]intDX_EWSW;
wire [31:31]intDY_EWSW;
wire left_right_SHT1;
wire left_right_SHT2;
wire load0;
wire op_add_subt;
wire [0:0]out;
wire [2:0]overflow_flag;
wire [1:0]p_0_in;
wire p_2_in;
wire ready_add_subt;
wire [25:0]sftr_odat_SHT2_SWR;
wire [4:2]shft_value_mux_o_EWR;
wire [4:2]shift_value_SHT2_EWR;
wire [3:0]NLW__inferred__1_carry__1_CO_UNCONNECTED;
wire [3:1]NLW__inferred__1_carry__1_O_UNCONNECTED;
RegisterAdd__parameterized1 EXP_STAGE_DMP
(.AR({AR[3:2],AR[0]}),
.CLK(CLK),
.D({Shift_amount_EXP_EW[2],EXP_STAGE_DMP_n_1}),
.Q({EXP_STAGE_DMP_n_2,EXP_STAGE_DMP_n_3,EXP_STAGE_DMP_n_4,EXP_STAGE_DMP_n_5,EXP_STAGE_DMP_n_6,EXP_STAGE_DMP_n_7,EXP_STAGE_DMP_n_8,EXP_STAGE_DMP_n_9,EXP_STAGE_DMP_n_10,EXP_STAGE_DMP_n_11,EXP_STAGE_DMP_n_12,EXP_STAGE_DMP_n_13,EXP_STAGE_DMP_n_14,EXP_STAGE_DMP_n_15,EXP_STAGE_DMP_n_16,EXP_STAGE_DMP_n_17,EXP_STAGE_DMP_n_18,EXP_STAGE_DMP_n_19,EXP_STAGE_DMP_n_20,EXP_STAGE_DMP_n_21,EXP_STAGE_DMP_n_22,EXP_STAGE_DMP_n_23,EXP_STAGE_DMP_n_24,EXP_STAGE_DMP_n_25,EXP_STAGE_DMP_n_26,EXP_STAGE_DMP_n_27,EXP_STAGE_DMP_n_28,EXP_STAGE_DMP_n_29,EXP_STAGE_DMP_n_30,EXP_STAGE_DMP_n_31,EXP_STAGE_DMP_n_32}),
.\Q_reg[25]_0 ({EXP_STAGE_DmP_n_3,EXP_STAGE_DmP_n_4,EXP_STAGE_DmP_n_5}),
.\Q_reg[30]_0 ({MuxXY_n_0,MuxXY_n_1,MuxXY_n_2,MuxXY_n_3,MuxXY_n_4,MuxXY_n_5,MuxXY_n_6,MuxXY_n_7,MuxXY_n_8,MuxXY_n_9,MuxXY_n_10,MuxXY_n_11,MuxXY_n_12,MuxXY_n_13,MuxXY_n_14,MuxXY_n_15,MuxXY_n_16,MuxXY_n_17,MuxXY_n_18,MuxXY_n_19,MuxXY_n_20,MuxXY_n_21,MuxXY_n_22,MuxXY_n_23,MuxXY_n_24,MuxXY_n_25,MuxXY_n_26,MuxXY_n_27,MuxXY_n_28,MuxXY_n_29,MuxXY_n_30}),
.\Q_reg[6]_0 (inst_ShiftRegister_n_1));
RegisterAdd__parameterized2 EXP_STAGE_DmP
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({Shift_amount_EXP_EW[4:3],Shift_amount_EXP_EW[1]}),
.Q({EXP_STAGE_DmP_n_3,EXP_STAGE_DmP_n_4,EXP_STAGE_DmP_n_5,EXP_STAGE_DmP_n_6,EXP_STAGE_DmP_n_7,EXP_STAGE_DmP_n_8,EXP_STAGE_DmP_n_9,EXP_STAGE_DmP_n_10,EXP_STAGE_DmP_n_11,EXP_STAGE_DmP_n_12,EXP_STAGE_DmP_n_13,EXP_STAGE_DmP_n_14,EXP_STAGE_DmP_n_15,EXP_STAGE_DmP_n_16,EXP_STAGE_DmP_n_17,EXP_STAGE_DmP_n_18,EXP_STAGE_DmP_n_19,EXP_STAGE_DmP_n_20,EXP_STAGE_DmP_n_21,EXP_STAGE_DmP_n_22,EXP_STAGE_DmP_n_23,EXP_STAGE_DmP_n_24,EXP_STAGE_DmP_n_25,EXP_STAGE_DmP_n_26,EXP_STAGE_DmP_n_27,EXP_STAGE_DmP_n_28}),
.\Q_reg[27]_0 ({EXP_STAGE_DMP_n_5,EXP_STAGE_DMP_n_6,EXP_STAGE_DMP_n_7,EXP_STAGE_DMP_n_8,EXP_STAGE_DMP_n_9}),
.\Q_reg[27]_1 ({MuxXY_n_31,MuxXY_n_32,MuxXY_n_33,MuxXY_n_34,MuxXY_n_35,MuxXY_n_36,MuxXY_n_37,MuxXY_n_38,MuxXY_n_39,MuxXY_n_40,MuxXY_n_41,MuxXY_n_42,MuxXY_n_43,MuxXY_n_44,MuxXY_n_45,MuxXY_n_46,MuxXY_n_47,MuxXY_n_48,MuxXY_n_49,MuxXY_n_50,MuxXY_n_51,MuxXY_n_52,MuxXY_n_53,MuxXY_n_54,MuxXY_n_55,MuxXY_n_56,MuxXY_n_57,MuxXY_n_58}),
.\Q_reg[6]_0 (inst_ShiftRegister_n_1));
RegisterAdd__parameterized3 EXP_STAGE_FLAGS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({SIGN_FLAG_INIT,OP_FLAG_INIT,INPUT_STAGE_FLAGS_n_1}),
.Q({EXP_STAGE_FLAGS_n_0,EXP_STAGE_FLAGS_n_1,EXP_STAGE_FLAGS_n_2}),
.\Q_reg[6] (inst_ShiftRegister_n_1));
RegisterAdd FRMT_STAGE_DATAOUT
(.AR({AR[3],AR[1]}),
.CLK(CLK),
.D({formatted_number_W,SFT2FRMT_STAGE_VARS_n_15,SFT2FRMT_STAGE_VARS_n_16,SFT2FRMT_STAGE_VARS_n_17,SFT2FRMT_STAGE_VARS_n_18,SFT2FRMT_STAGE_VARS_n_19,SFT2FRMT_STAGE_VARS_n_20,SFT2FRMT_STAGE_VARS_n_21,SFT2FRMT_STAGE_VARS_n_22,SHT2_SHIFT_DATA_n_0,SHT2_STAGE_SHFTVARS1_n_0,SHT2_STAGE_SHFTVARS1_n_1,SHT2_STAGE_SHFTVARS1_n_2,SHT2_STAGE_SHFTVARS1_n_3,SHT2_STAGE_SHFTVARS1_n_4,SHT2_STAGE_SHFTVARS1_n_5,SHT2_STAGE_SHFTVARS1_n_6,SHT2_STAGE_SHFTVARS1_n_7,SHT2_STAGE_SHFTVARS2_n_0,SHT2_STAGE_SHFTVARS2_n_1,SHT2_SHIFT_DATA_n_1,SHT2_SHIFT_DATA_n_2,SHT2_STAGE_SHFTVARS2_n_2,SHT2_STAGE_SHFTVARS2_n_3,SHT2_STAGE_SHFTVARS2_n_4,SHT2_STAGE_SHFTVARS2_n_5,SHT2_STAGE_SHFTVARS1_n_8,SHT2_STAGE_SHFTVARS1_n_9,SHT2_STAGE_SHFTVARS1_n_10,SHT2_STAGE_SHFTVARS1_n_11,SHT2_STAGE_SHFTVARS1_n_12,SHT2_STAGE_SHFTVARS1_n_13}),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q(inst_ShiftRegister_n_6),
.\Q_reg[31]_0 (\Q_reg[31] ),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT),
.exp_rslt_NRM2_EW1(exp_rslt_NRM2_EW1));
RegisterAdd__parameterized21 FRMT_STAGE_FLAGS
(.AR(AR[2:1]),
.CLK(CLK),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q(inst_ShiftRegister_n_6),
.\Q_reg[0]_0 (SFT2FRMT_STAGE_FLAGS_n_3),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT),
.overflow_flag(overflow_flag));
RegisterAdd__parameterized0 INPUT_STAGE_FLAGS
(.CLK(CLK),
.CO(eqXY),
.D(INPUT_STAGE_FLAGS_n_1),
.E(E),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.Q(intDY_EWSW),
.\Q_reg[31] (intDX_EWSW),
.intAS(intAS),
.op_add_subt(op_add_subt));
RegisterAdd_1 INPUT_STAGE_OPERANDX
(.AR(AR[0]),
.CLK(CLK),
.D(OP_FLAG_INIT),
.DI({INPUT_STAGE_OPERANDX_n_0,INPUT_STAGE_OPERANDX_n_1,INPUT_STAGE_OPERANDX_n_2,INPUT_STAGE_OPERANDX_n_3}),
.E(E),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.Q({intDX_EWSW,INPUT_STAGE_OPERANDX_n_5,INPUT_STAGE_OPERANDX_n_6,INPUT_STAGE_OPERANDX_n_7,INPUT_STAGE_OPERANDX_n_8,INPUT_STAGE_OPERANDX_n_9,INPUT_STAGE_OPERANDX_n_10,INPUT_STAGE_OPERANDX_n_11,INPUT_STAGE_OPERANDX_n_12,INPUT_STAGE_OPERANDX_n_13,INPUT_STAGE_OPERANDX_n_14,INPUT_STAGE_OPERANDX_n_15,INPUT_STAGE_OPERANDX_n_16,INPUT_STAGE_OPERANDX_n_17,INPUT_STAGE_OPERANDX_n_18,INPUT_STAGE_OPERANDX_n_19,INPUT_STAGE_OPERANDX_n_20,INPUT_STAGE_OPERANDX_n_21,INPUT_STAGE_OPERANDX_n_22,INPUT_STAGE_OPERANDX_n_23,INPUT_STAGE_OPERANDX_n_24,INPUT_STAGE_OPERANDX_n_25,INPUT_STAGE_OPERANDX_n_26,INPUT_STAGE_OPERANDX_n_27,INPUT_STAGE_OPERANDX_n_28,INPUT_STAGE_OPERANDX_n_29,INPUT_STAGE_OPERANDX_n_30,INPUT_STAGE_OPERANDX_n_31,INPUT_STAGE_OPERANDX_n_32,INPUT_STAGE_OPERANDX_n_33,INPUT_STAGE_OPERANDX_n_34,INPUT_STAGE_OPERANDX_n_35}),
.\Q_reg[2]_0 ({INPUT_STAGE_OPERANDX_n_36,INPUT_STAGE_OPERANDX_n_37,INPUT_STAGE_OPERANDX_n_38,INPUT_STAGE_OPERANDX_n_39}),
.\Q_reg[2]_1 ({INPUT_STAGE_OPERANDX_n_44,INPUT_STAGE_OPERANDX_n_45,INPUT_STAGE_OPERANDX_n_46,INPUT_STAGE_OPERANDX_n_47}),
.\Q_reg[2]_2 ({INPUT_STAGE_OPERANDX_n_48,INPUT_STAGE_OPERANDX_n_49,INPUT_STAGE_OPERANDX_n_50,INPUT_STAGE_OPERANDX_n_51}),
.\Q_reg[2]_3 ({INPUT_STAGE_OPERANDX_n_52,INPUT_STAGE_OPERANDX_n_53,INPUT_STAGE_OPERANDX_n_54,INPUT_STAGE_OPERANDX_n_55}),
.\Q_reg[2]_4 ({INPUT_STAGE_OPERANDX_n_56,INPUT_STAGE_OPERANDX_n_57,INPUT_STAGE_OPERANDX_n_58,INPUT_STAGE_OPERANDX_n_59}),
.\Q_reg[2]_5 ({INPUT_STAGE_OPERANDX_n_60,INPUT_STAGE_OPERANDX_n_61,INPUT_STAGE_OPERANDX_n_62,INPUT_STAGE_OPERANDX_n_63}),
.\Q_reg[2]_6 ({INPUT_STAGE_OPERANDX_n_64,INPUT_STAGE_OPERANDX_n_65,INPUT_STAGE_OPERANDX_n_66,INPUT_STAGE_OPERANDX_n_67}),
.\Q_reg[2]_7 ({INPUT_STAGE_OPERANDX_n_68,INPUT_STAGE_OPERANDX_n_69,INPUT_STAGE_OPERANDX_n_70}),
.\Q_reg[2]_8 ({INPUT_STAGE_OPERANDX_n_71,INPUT_STAGE_OPERANDX_n_72}),
.\Q_reg[31]_0 ({intDY_EWSW,INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}),
.\Q_reg[31]_1 (\Q_reg[31]_0 ),
.S({INPUT_STAGE_OPERANDX_n_40,INPUT_STAGE_OPERANDX_n_41,INPUT_STAGE_OPERANDX_n_42,INPUT_STAGE_OPERANDX_n_43}),
.intAS(intAS));
RegisterAdd_2 INPUT_STAGE_OPERANDY
(.CLK(CLK),
.D(D),
.E(E),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.Q({intDY_EWSW,INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}),
.\Q_reg[2]_0 (INPUT_STAGE_OPERANDY_n_33),
.\Q_reg[30]_0 (INPUT_STAGE_OPERANDX_n_5),
.S(INPUT_STAGE_OPERANDY_n_0));
Comparator Magnitude_Comparator
(.CO(gtXY),
.DI({INPUT_STAGE_OPERANDX_n_0,INPUT_STAGE_OPERANDX_n_1,INPUT_STAGE_OPERANDX_n_2,INPUT_STAGE_OPERANDX_n_3}),
.\Q_reg[14] ({INPUT_STAGE_OPERANDX_n_44,INPUT_STAGE_OPERANDX_n_45,INPUT_STAGE_OPERANDX_n_46,INPUT_STAGE_OPERANDX_n_47}),
.\Q_reg[14]_0 ({INPUT_STAGE_OPERANDX_n_48,INPUT_STAGE_OPERANDX_n_49,INPUT_STAGE_OPERANDX_n_50,INPUT_STAGE_OPERANDX_n_51}),
.\Q_reg[21] ({INPUT_STAGE_OPERANDX_n_60,INPUT_STAGE_OPERANDX_n_61,INPUT_STAGE_OPERANDX_n_62,INPUT_STAGE_OPERANDX_n_63}),
.\Q_reg[22] ({INPUT_STAGE_OPERANDX_n_56,INPUT_STAGE_OPERANDX_n_57,INPUT_STAGE_OPERANDX_n_58,INPUT_STAGE_OPERANDX_n_59}),
.\Q_reg[22]_0 ({INPUT_STAGE_OPERANDX_n_64,INPUT_STAGE_OPERANDX_n_65,INPUT_STAGE_OPERANDX_n_66,INPUT_STAGE_OPERANDX_n_67}),
.\Q_reg[2] (eqXY),
.\Q_reg[30] ({INPUT_STAGE_OPERANDY_n_33,INPUT_STAGE_OPERANDX_n_68,INPUT_STAGE_OPERANDX_n_69,INPUT_STAGE_OPERANDX_n_70}),
.\Q_reg[30]_0 ({INPUT_STAGE_OPERANDY_n_0,INPUT_STAGE_OPERANDX_n_71,INPUT_STAGE_OPERANDX_n_72}),
.\Q_reg[6] ({INPUT_STAGE_OPERANDX_n_36,INPUT_STAGE_OPERANDX_n_37,INPUT_STAGE_OPERANDX_n_38,INPUT_STAGE_OPERANDX_n_39}),
.\Q_reg[9] ({INPUT_STAGE_OPERANDX_n_52,INPUT_STAGE_OPERANDX_n_53,INPUT_STAGE_OPERANDX_n_54,INPUT_STAGE_OPERANDX_n_55}),
.S({INPUT_STAGE_OPERANDX_n_40,INPUT_STAGE_OPERANDX_n_41,INPUT_STAGE_OPERANDX_n_42,INPUT_STAGE_OPERANDX_n_43}));
MultiplexTxT MuxXY
(.CO(gtXY),
.Q({INPUT_STAGE_OPERANDX_n_5,INPUT_STAGE_OPERANDX_n_6,INPUT_STAGE_OPERANDX_n_7,INPUT_STAGE_OPERANDX_n_8,INPUT_STAGE_OPERANDX_n_9,INPUT_STAGE_OPERANDX_n_10,INPUT_STAGE_OPERANDX_n_11,INPUT_STAGE_OPERANDX_n_12,INPUT_STAGE_OPERANDX_n_13,INPUT_STAGE_OPERANDX_n_14,INPUT_STAGE_OPERANDX_n_15,INPUT_STAGE_OPERANDX_n_16,INPUT_STAGE_OPERANDX_n_17,INPUT_STAGE_OPERANDX_n_18,INPUT_STAGE_OPERANDX_n_19,INPUT_STAGE_OPERANDX_n_20,INPUT_STAGE_OPERANDX_n_21,INPUT_STAGE_OPERANDX_n_22,INPUT_STAGE_OPERANDX_n_23,INPUT_STAGE_OPERANDX_n_24,INPUT_STAGE_OPERANDX_n_25,INPUT_STAGE_OPERANDX_n_26,INPUT_STAGE_OPERANDX_n_27,INPUT_STAGE_OPERANDX_n_28,INPUT_STAGE_OPERANDX_n_29,INPUT_STAGE_OPERANDX_n_30,INPUT_STAGE_OPERANDX_n_31,INPUT_STAGE_OPERANDX_n_32,INPUT_STAGE_OPERANDX_n_33,INPUT_STAGE_OPERANDX_n_34,INPUT_STAGE_OPERANDX_n_35}),
.\Q_reg[27] ({MuxXY_n_31,MuxXY_n_32,MuxXY_n_33,MuxXY_n_34,MuxXY_n_35,MuxXY_n_36,MuxXY_n_37,MuxXY_n_38,MuxXY_n_39,MuxXY_n_40,MuxXY_n_41,MuxXY_n_42,MuxXY_n_43,MuxXY_n_44,MuxXY_n_45,MuxXY_n_46,MuxXY_n_47,MuxXY_n_48,MuxXY_n_49,MuxXY_n_50,MuxXY_n_51,MuxXY_n_52,MuxXY_n_53,MuxXY_n_54,MuxXY_n_55,MuxXY_n_56,MuxXY_n_57,MuxXY_n_58}),
.\Q_reg[30] ({MuxXY_n_0,MuxXY_n_1,MuxXY_n_2,MuxXY_n_3,MuxXY_n_4,MuxXY_n_5,MuxXY_n_6,MuxXY_n_7,MuxXY_n_8,MuxXY_n_9,MuxXY_n_10,MuxXY_n_11,MuxXY_n_12,MuxXY_n_13,MuxXY_n_14,MuxXY_n_15,MuxXY_n_16,MuxXY_n_17,MuxXY_n_18,MuxXY_n_19,MuxXY_n_20,MuxXY_n_21,MuxXY_n_22,MuxXY_n_23,MuxXY_n_24,MuxXY_n_25,MuxXY_n_26,MuxXY_n_27,MuxXY_n_28,MuxXY_n_29,MuxXY_n_30}),
.\Q_reg[30]_0 ({INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}));
RegisterAdd__parameterized19 NRM_STAGE_DMP_exp
(.AR(AR[0]),
.CLK(CLK),
.Q({NRM_STAGE_DMP_exp_n_0,NRM_STAGE_DMP_exp_n_1,NRM_STAGE_DMP_exp_n_2,NRM_STAGE_DMP_exp_n_3,NRM_STAGE_DMP_exp_n_4,NRM_STAGE_DMP_exp_n_5,NRM_STAGE_DMP_exp_n_6,NRM_STAGE_DMP_exp_n_7}),
.\Q_reg[2]_0 (inst_ShiftRegister_n_4),
.\Q_reg[30] ({SGF_STAGE_DMP_n_4,SGF_STAGE_DMP_n_5,SGF_STAGE_DMP_n_6,SGF_STAGE_DMP_n_7,SGF_STAGE_DMP_n_8,SGF_STAGE_DMP_n_9,SGF_STAGE_DMP_n_10,SGF_STAGE_DMP_n_11}));
RegisterAdd__parameterized20 NRM_STAGE_FLAGS
(.AR(AR[0]),
.CLK(CLK),
.D(shft_value_mux_o_EWR[2]),
.Q({ADD_OVRFLW_NRM,NRM_STAGE_FLAGS_n_2,NRM_STAGE_FLAGS_n_3}),
.\Q_reg[0]_0 (NRM_STAGE_Raw_mant_n_30),
.\Q_reg[1]_0 (SHT1_STAGE_sft_amount_n_0),
.\Q_reg[1]_1 ({SGF_STAGE_FLAGS_n_0,SGF_STAGE_FLAGS_n_1,p_0_in[0]}),
.\Q_reg[22] ({LZD_raw_out_EWR[2],LZD_raw_out_EWR[0]}),
.\Q_reg[25] (NRM_STAGE_FLAGS_n_4),
.\Q_reg[25]_0 (\Data_array_SWR[2]_1 [25]),
.\Q_reg[2]_0 ({inst_ShiftRegister_n_4,Shift_reg_FLAGS_7}),
.\Q_reg[2]_1 ({Shift_amount_SHT1_EWR[2],Shift_amount_SHT1_EWR[0]}));
RegisterAdd__parameterized18 NRM_STAGE_Raw_mant
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D(\Data_array_SWR[2]_1 [24:0]),
.Q({inst_ShiftRegister_n_4,Shift_reg_FLAGS_7}),
.\Q_reg[12]_0 (LZD_raw_out_EWR),
.\Q_reg[12]_1 (NRM_STAGE_Raw_mant_n_30),
.\Q_reg[1]_0 (bit_shift_SHT1),
.\Q_reg[1]_1 (SHT1_STAGE_sft_amount_n_0),
.\Q_reg[1]_2 (Raw_mant_SGF),
.\Q_reg[22]_0 ({SHT1_STAGE_DmP_mant_n_0,SHT1_STAGE_DmP_mant_n_1,SHT1_STAGE_DmP_mant_n_2,SHT1_STAGE_DmP_mant_n_3,SHT1_STAGE_DmP_mant_n_4,SHT1_STAGE_DmP_mant_n_5,SHT1_STAGE_DmP_mant_n_6,SHT1_STAGE_DmP_mant_n_7,SHT1_STAGE_DmP_mant_n_8,SHT1_STAGE_DmP_mant_n_9,SHT1_STAGE_DmP_mant_n_10,SHT1_STAGE_DmP_mant_n_11,SHT1_STAGE_DmP_mant_n_12,SHT1_STAGE_DmP_mant_n_13,SHT1_STAGE_DmP_mant_n_14,SHT1_STAGE_DmP_mant_n_15,SHT1_STAGE_DmP_mant_n_16,SHT1_STAGE_DmP_mant_n_17,SHT1_STAGE_DmP_mant_n_18,SHT1_STAGE_DmP_mant_n_19,SHT1_STAGE_DmP_mant_n_20,SHT1_STAGE_DmP_mant_n_21,SHT1_STAGE_DmP_mant_n_22}),
.\Q_reg[2]_0 (NRM_STAGE_FLAGS_n_4),
.\Q_reg[2]_1 (ADD_OVRFLW_NRM));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1
(.I0(SGF_STAGE_DmP_mant_n_35),
.I1(SGF_STAGE_DMP_n_41),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[10]));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1
(.I0(SGF_STAGE_DmP_mant_n_34),
.I1(SGF_STAGE_DMP_n_40),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[11]));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1
(.I0(SGF_STAGE_DmP_mant_n_33),
.I1(SGF_STAGE_DMP_n_39),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[12]));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_10
(.I0(DMP_mant_SFG_SWR[10]),
.I1(SGF_STAGE_DmP_mant_n_14),
.O(\Q[12]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_11
(.I0(DMP_mant_SFG_SWR[9]),
.I1(SGF_STAGE_DmP_mant_n_15),
.O(\Q[12]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_8
(.I0(DMP_mant_SFG_SWR[12]),
.I1(SGF_STAGE_DmP_mant_n_12),
.O(\Q[12]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_9
(.I0(DMP_mant_SFG_SWR[11]),
.I1(SGF_STAGE_DmP_mant_n_13),
.O(\Q[12]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1
(.I0(SGF_STAGE_DmP_mant_n_40),
.I1(SGF_STAGE_DMP_n_46),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[13]));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1
(.I0(SGF_STAGE_DmP_mant_n_39),
.I1(SGF_STAGE_DMP_n_45),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[14]));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1
(.I0(SGF_STAGE_DmP_mant_n_38),
.I1(SGF_STAGE_DMP_n_44),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[15]));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1
(.I0(SGF_STAGE_DmP_mant_n_37),
.I1(SGF_STAGE_DMP_n_43),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[16]));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_10
(.I0(DMP_mant_SFG_SWR[14]),
.I1(SGF_STAGE_DmP_mant_n_10),
.O(\Q[16]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_11
(.I0(DMP_mant_SFG_SWR[13]),
.I1(SGF_STAGE_DmP_mant_n_11),
.O(\Q[16]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_8
(.I0(DMP_mant_SFG_SWR[16]),
.I1(SGF_STAGE_DmP_mant_n_8),
.O(\Q[16]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_9
(.I0(DMP_mant_SFG_SWR[15]),
.I1(SGF_STAGE_DmP_mant_n_9),
.O(\Q[16]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1
(.I0(SGF_STAGE_DmP_mant_n_44),
.I1(SGF_STAGE_DMP_n_50),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[17]));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1
(.I0(SGF_STAGE_DmP_mant_n_43),
.I1(SGF_STAGE_DMP_n_49),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[18]));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1
(.I0(SGF_STAGE_DmP_mant_n_42),
.I1(SGF_STAGE_DMP_n_48),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[19]));
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1
(.I0(SGF_STAGE_DmP_mant_n_28),
.I1(SGF_STAGE_DMP_n_3),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[1]));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1
(.I0(SGF_STAGE_DmP_mant_n_41),
.I1(SGF_STAGE_DMP_n_47),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[20]));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_10
(.I0(DMP_mant_SFG_SWR[18]),
.I1(SGF_STAGE_DmP_mant_n_6),
.O(\Q[20]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_11
(.I0(DMP_mant_SFG_SWR[17]),
.I1(SGF_STAGE_DmP_mant_n_7),
.O(\Q[20]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_8
(.I0(DMP_mant_SFG_SWR[20]),
.I1(SGF_STAGE_DmP_mant_n_4),
.O(\Q[20]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_9
(.I0(DMP_mant_SFG_SWR[19]),
.I1(SGF_STAGE_DmP_mant_n_5),
.O(\Q[20]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1
(.I0(SGF_STAGE_DmP_mant_n_48),
.I1(SGF_STAGE_DMP_n_55),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[21]));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1
(.I0(SGF_STAGE_DmP_mant_n_47),
.I1(SGF_STAGE_DMP_n_54),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[22]));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1
(.I0(SGF_STAGE_DmP_mant_n_46),
.I1(SGF_STAGE_DMP_n_53),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[23]));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1
(.I0(SGF_STAGE_DmP_mant_n_45),
.I1(SGF_STAGE_DMP_n_52),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[24]));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_10
(.I0(DMP_mant_SFG_SWR[22]),
.I1(SGF_STAGE_DmP_mant_n_2),
.O(\Q[24]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_11
(.I0(DMP_mant_SFG_SWR[21]),
.I1(SGF_STAGE_DmP_mant_n_3),
.O(\Q[24]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_8
(.I0(DMP_mant_SFG_SWR[24]),
.I1(SGF_STAGE_DmP_mant_n_0),
.O(\Q[24]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_9
(.I0(DMP_mant_SFG_SWR[23]),
.I1(SGF_STAGE_DmP_mant_n_1),
.O(\Q[24]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1
(.I0(SGF_STAGE_DmP_mant_n_49),
.I1(SGF_STAGE_DmP_mant_n_51),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[25]));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1
(.I0(SGF_STAGE_DmP_mant_n_27),
.I1(SGF_STAGE_DMP_n_2),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[2]));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1
(.I0(SGF_STAGE_DmP_mant_n_26),
.I1(SGF_STAGE_DMP_n_1),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[3]));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1
(.I0(SGF_STAGE_DmP_mant_n_25),
.I1(SGF_STAGE_DMP_n_0),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[4]));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_10
(.I0(DMP_mant_SFG_SWR[3]),
.I1(SGF_STAGE_DmP_mant_n_21),
.O(\Q[4]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_11
(.I0(DMP_mant_SFG_SWR[2]),
.I1(SGF_STAGE_DmP_mant_n_22),
.O(\Q[4]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_9
(.I0(DMP_mant_SFG_SWR[4]),
.I1(SGF_STAGE_DmP_mant_n_20),
.O(\Q[4]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1
(.I0(SGF_STAGE_DmP_mant_n_32),
.I1(SGF_STAGE_DMP_n_38),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[5]));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1
(.I0(SGF_STAGE_DmP_mant_n_31),
.I1(SGF_STAGE_DMP_n_37),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[6]));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1
(.I0(SGF_STAGE_DmP_mant_n_30),
.I1(SGF_STAGE_DMP_n_36),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[7]));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1
(.I0(SGF_STAGE_DmP_mant_n_29),
.I1(SGF_STAGE_DMP_n_35),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[8]));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_10
(.I0(DMP_mant_SFG_SWR[6]),
.I1(SGF_STAGE_DmP_mant_n_18),
.O(\Q[8]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_11
(.I0(DMP_mant_SFG_SWR[5]),
.I1(SGF_STAGE_DmP_mant_n_19),
.O(\Q[8]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_8__0
(.I0(DMP_mant_SFG_SWR[8]),
.I1(SGF_STAGE_DmP_mant_n_16),
.O(\Q[8]_i_8__0_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_9__0
(.I0(DMP_mant_SFG_SWR[7]),
.I1(SGF_STAGE_DmP_mant_n_17),
.O(\Q[8]_i_9__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1
(.I0(SGF_STAGE_DmP_mant_n_36),
.I1(SGF_STAGE_DMP_n_42),
.I2(p_0_in[1]),
.O(Raw_mant_SGF[9]));
RegisterAdd__parameterized22 Ready_reg
(.AR(AR[1]),
.CLK(CLK),
.Q(inst_ShiftRegister_n_6),
.ready_add_subt(ready_add_subt));
RegisterAdd__parameterized14 SFT2FRMT_STAGE_FLAGS
(.AR(AR[2]),
.CLK(CLK),
.D(formatted_number_W),
.DI(SFT2FRMT_STAGE_FLAGS_n_1),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({ADD_OVRFLW_NRM2,SFT2FRMT_STAGE_FLAGS_n_3}),
.\Q_reg[1]_0 (Shift_reg_FLAGS_7),
.\Q_reg[2]_0 ({ADD_OVRFLW_NRM,NRM_STAGE_FLAGS_n_2,NRM_STAGE_FLAGS_n_3}),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
RegisterAdd__parameterized13 SFT2FRMT_STAGE_VARS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({SFT2FRMT_STAGE_VARS_n_15,SFT2FRMT_STAGE_VARS_n_16,SFT2FRMT_STAGE_VARS_n_17,SFT2FRMT_STAGE_VARS_n_18,SFT2FRMT_STAGE_VARS_n_19,SFT2FRMT_STAGE_VARS_n_20,SFT2FRMT_STAGE_VARS_n_21,SFT2FRMT_STAGE_VARS_n_22}),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q(ADD_OVRFLW_NRM2),
.\Q_reg[1]_0 (SFT2FRMT_STAGE_VARS_n_23),
.\Q_reg[1]_1 (Shift_reg_FLAGS_7),
.\Q_reg[1]_2 ({LZD_raw_out_EWR,NRM_STAGE_DMP_exp_n_0,NRM_STAGE_DMP_exp_n_1,NRM_STAGE_DMP_exp_n_2,NRM_STAGE_DMP_exp_n_3,NRM_STAGE_DMP_exp_n_4,NRM_STAGE_DMP_exp_n_5,NRM_STAGE_DMP_exp_n_6,NRM_STAGE_DMP_exp_n_7}),
.\Q_reg[30] ({SFT2FRMT_STAGE_VARS_n_4,SFT2FRMT_STAGE_VARS_n_5,SFT2FRMT_STAGE_VARS_n_6,SFT2FRMT_STAGE_VARS_n_7}),
.\Q_reg[30]_0 ({SFT2FRMT_STAGE_VARS_n_8,SFT2FRMT_STAGE_VARS_n_9,SFT2FRMT_STAGE_VARS_n_10,SFT2FRMT_STAGE_VARS_n_11,SFT2FRMT_STAGE_VARS_n_12,SFT2FRMT_STAGE_VARS_n_13,SFT2FRMT_STAGE_VARS_n_14}),
.S({SFT2FRMT_STAGE_VARS_n_0,SFT2FRMT_STAGE_VARS_n_1,SFT2FRMT_STAGE_VARS_n_2,SFT2FRMT_STAGE_VARS_n_3}),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT),
.exp_rslt_NRM2_EW1(exp_rslt_NRM2_EW1[7:0]));
RegisterAdd__parameterized15 SGF_STAGE_DMP
(.AR({AR[3:2],AR[0]}),
.CLK(CLK),
.CO(SGF_STAGE_DMP_n_51),
.E(load0),
.O({SGF_STAGE_DMP_n_0,SGF_STAGE_DMP_n_1,SGF_STAGE_DMP_n_2,SGF_STAGE_DMP_n_3}),
.Q({SGF_STAGE_DMP_n_4,SGF_STAGE_DMP_n_5,SGF_STAGE_DMP_n_6,SGF_STAGE_DMP_n_7,SGF_STAGE_DMP_n_8,SGF_STAGE_DMP_n_9,SGF_STAGE_DMP_n_10,SGF_STAGE_DMP_n_11,DMP_mant_SFG_SWR}),
.\Q_reg[10]_0 ({\Q[12]_i_8_n_0 ,\Q[12]_i_9_n_0 ,\Q[12]_i_10_n_0 ,\Q[12]_i_11_n_0 }),
.\Q_reg[12]_0 ({SGF_STAGE_DMP_n_39,SGF_STAGE_DMP_n_40,SGF_STAGE_DMP_n_41,SGF_STAGE_DMP_n_42}),
.\Q_reg[14]_0 ({\Q[16]_i_8_n_0 ,\Q[16]_i_9_n_0 ,\Q[16]_i_10_n_0 ,\Q[16]_i_11_n_0 }),
.\Q_reg[16]_0 ({SGF_STAGE_DMP_n_43,SGF_STAGE_DMP_n_44,SGF_STAGE_DMP_n_45,SGF_STAGE_DMP_n_46}),
.\Q_reg[18]_0 ({\Q[20]_i_8_n_0 ,\Q[20]_i_9_n_0 ,\Q[20]_i_10_n_0 ,\Q[20]_i_11_n_0 }),
.\Q_reg[20]_0 ({SGF_STAGE_DMP_n_47,SGF_STAGE_DMP_n_48,SGF_STAGE_DMP_n_49,SGF_STAGE_DMP_n_50}),
.\Q_reg[22]_0 ({\Q[24]_i_8_n_0 ,\Q[24]_i_9_n_0 ,\Q[24]_i_10_n_0 ,\Q[24]_i_11_n_0 }),
.\Q_reg[24]_0 ({SGF_STAGE_DMP_n_52,SGF_STAGE_DMP_n_53,SGF_STAGE_DMP_n_54,SGF_STAGE_DMP_n_55}),
.\Q_reg[30]_0 ({SHT2_STAGE_DMP_n_0,SHT2_STAGE_DMP_n_1,SHT2_STAGE_DMP_n_2,SHT2_STAGE_DMP_n_3,SHT2_STAGE_DMP_n_4,SHT2_STAGE_DMP_n_5,SHT2_STAGE_DMP_n_6,SHT2_STAGE_DMP_n_7,SHT2_STAGE_DMP_n_8,SHT2_STAGE_DMP_n_9,SHT2_STAGE_DMP_n_10,SHT2_STAGE_DMP_n_11,SHT2_STAGE_DMP_n_12,SHT2_STAGE_DMP_n_13,SHT2_STAGE_DMP_n_14,SHT2_STAGE_DMP_n_15,SHT2_STAGE_DMP_n_16,SHT2_STAGE_DMP_n_17,SHT2_STAGE_DMP_n_18,SHT2_STAGE_DMP_n_19,SHT2_STAGE_DMP_n_20,SHT2_STAGE_DMP_n_21,SHT2_STAGE_DMP_n_22,SHT2_STAGE_DMP_n_23,SHT2_STAGE_DMP_n_24,SHT2_STAGE_DMP_n_25,SHT2_STAGE_DMP_n_26,SHT2_STAGE_DMP_n_27,SHT2_STAGE_DMP_n_28,SHT2_STAGE_DMP_n_29,SHT2_STAGE_DMP_n_30}),
.\Q_reg[6]_0 ({\Q[8]_i_8__0_n_0 ,\Q[8]_i_9__0_n_0 ,\Q[8]_i_10_n_0 ,\Q[8]_i_11_n_0 }),
.\Q_reg[8]_0 ({SGF_STAGE_DMP_n_35,SGF_STAGE_DMP_n_36,SGF_STAGE_DMP_n_37,SGF_STAGE_DMP_n_38}),
.S({\Q[4]_i_9_n_0 ,\Q[4]_i_10_n_0 ,\Q[4]_i_11_n_0 ,SGF_STAGE_DmP_mant_n_24}));
RegisterAdd__parameterized16 SGF_STAGE_DmP_mant
(.AR(AR),
.CLK(CLK),
.CO(p_2_in),
.D(sftr_odat_SHT2_SWR),
.E(load0),
.O({SGF_STAGE_DmP_mant_n_25,SGF_STAGE_DmP_mant_n_26,SGF_STAGE_DmP_mant_n_27,SGF_STAGE_DmP_mant_n_28}),
.Q({SGF_STAGE_DmP_mant_n_0,SGF_STAGE_DmP_mant_n_1,SGF_STAGE_DmP_mant_n_2,SGF_STAGE_DmP_mant_n_3,SGF_STAGE_DmP_mant_n_4,SGF_STAGE_DmP_mant_n_5,SGF_STAGE_DmP_mant_n_6,SGF_STAGE_DmP_mant_n_7,SGF_STAGE_DmP_mant_n_8,SGF_STAGE_DmP_mant_n_9,SGF_STAGE_DmP_mant_n_10,SGF_STAGE_DmP_mant_n_11,SGF_STAGE_DmP_mant_n_12,SGF_STAGE_DmP_mant_n_13,SGF_STAGE_DmP_mant_n_14,SGF_STAGE_DmP_mant_n_15,SGF_STAGE_DmP_mant_n_16,SGF_STAGE_DmP_mant_n_17,SGF_STAGE_DmP_mant_n_18,SGF_STAGE_DmP_mant_n_19,SGF_STAGE_DmP_mant_n_20,SGF_STAGE_DmP_mant_n_21,SGF_STAGE_DmP_mant_n_22,Raw_mant_SGF[0]}),
.\Q_reg[12]_0 ({SGF_STAGE_DmP_mant_n_33,SGF_STAGE_DmP_mant_n_34,SGF_STAGE_DmP_mant_n_35,SGF_STAGE_DmP_mant_n_36}),
.\Q_reg[16]_0 ({SGF_STAGE_DmP_mant_n_37,SGF_STAGE_DmP_mant_n_38,SGF_STAGE_DmP_mant_n_39,SGF_STAGE_DmP_mant_n_40}),
.\Q_reg[20]_0 ({SGF_STAGE_DmP_mant_n_41,SGF_STAGE_DmP_mant_n_42,SGF_STAGE_DmP_mant_n_43,SGF_STAGE_DmP_mant_n_44}),
.\Q_reg[22]_0 (DMP_mant_SFG_SWR),
.\Q_reg[22]_1 (SGF_STAGE_DMP_n_51),
.\Q_reg[24]_0 ({SGF_STAGE_DmP_mant_n_45,SGF_STAGE_DmP_mant_n_46,SGF_STAGE_DmP_mant_n_47,SGF_STAGE_DmP_mant_n_48}),
.\Q_reg[25]_0 (SGF_STAGE_DmP_mant_n_49),
.\Q_reg[25]_1 (SGF_STAGE_DmP_mant_n_51),
.\Q_reg[8]_0 ({SGF_STAGE_DmP_mant_n_29,SGF_STAGE_DmP_mant_n_30,SGF_STAGE_DmP_mant_n_31,SGF_STAGE_DmP_mant_n_32}),
.S(SGF_STAGE_DmP_mant_n_24));
RegisterAdd__parameterized17 SGF_STAGE_FLAGS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.CO(p_2_in),
.E(load0),
.Q(p_0_in[1]),
.\Q_reg[2]_0 ({SGF_STAGE_FLAGS_n_0,SGF_STAGE_FLAGS_n_1,p_0_in[0]}),
.\Q_reg[2]_1 ({SHT2_STAGE_FLAGS_n_0,SHT2_STAGE_FLAGS_n_1,SHT2_STAGE_FLAGS_n_2}));
RegisterAdd__parameterized4 SHT1_STAGE_DMP
(.AR({AR[3:2],AR[0]}),
.CLK(CLK),
.D({EXP_STAGE_DMP_n_2,EXP_STAGE_DMP_n_3,EXP_STAGE_DMP_n_4,EXP_STAGE_DMP_n_5,EXP_STAGE_DMP_n_6,EXP_STAGE_DMP_n_7,EXP_STAGE_DMP_n_8,EXP_STAGE_DMP_n_9,EXP_STAGE_DMP_n_10,EXP_STAGE_DMP_n_11,EXP_STAGE_DMP_n_12,EXP_STAGE_DMP_n_13,EXP_STAGE_DMP_n_14,EXP_STAGE_DMP_n_15,EXP_STAGE_DMP_n_16,EXP_STAGE_DMP_n_17,EXP_STAGE_DMP_n_18,EXP_STAGE_DMP_n_19,EXP_STAGE_DMP_n_20,EXP_STAGE_DMP_n_21,EXP_STAGE_DMP_n_22,EXP_STAGE_DMP_n_23,EXP_STAGE_DMP_n_24,EXP_STAGE_DMP_n_25,EXP_STAGE_DMP_n_26,EXP_STAGE_DMP_n_27,EXP_STAGE_DMP_n_28,EXP_STAGE_DMP_n_29,EXP_STAGE_DMP_n_30,EXP_STAGE_DMP_n_31,EXP_STAGE_DMP_n_32}),
.Q({SHT1_STAGE_DMP_n_0,SHT1_STAGE_DMP_n_1,SHT1_STAGE_DMP_n_2,SHT1_STAGE_DMP_n_3,SHT1_STAGE_DMP_n_4,SHT1_STAGE_DMP_n_5,SHT1_STAGE_DMP_n_6,SHT1_STAGE_DMP_n_7,SHT1_STAGE_DMP_n_8,SHT1_STAGE_DMP_n_9,SHT1_STAGE_DMP_n_10,SHT1_STAGE_DMP_n_11,SHT1_STAGE_DMP_n_12,SHT1_STAGE_DMP_n_13,SHT1_STAGE_DMP_n_14,SHT1_STAGE_DMP_n_15,SHT1_STAGE_DMP_n_16,SHT1_STAGE_DMP_n_17,SHT1_STAGE_DMP_n_18,SHT1_STAGE_DMP_n_19,SHT1_STAGE_DMP_n_20,SHT1_STAGE_DMP_n_21,SHT1_STAGE_DMP_n_22,SHT1_STAGE_DMP_n_23,SHT1_STAGE_DMP_n_24,SHT1_STAGE_DMP_n_25,SHT1_STAGE_DMP_n_26,SHT1_STAGE_DMP_n_27,SHT1_STAGE_DMP_n_28,SHT1_STAGE_DMP_n_29,SHT1_STAGE_DMP_n_30}),
.\Q_reg[5]_0 (inst_ShiftRegister_n_2));
RegisterAdd__parameterized5 SHT1_STAGE_DmP_mant
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({EXP_STAGE_DmP_n_6,EXP_STAGE_DmP_n_7,EXP_STAGE_DmP_n_8,EXP_STAGE_DmP_n_9,EXP_STAGE_DmP_n_10,EXP_STAGE_DmP_n_11,EXP_STAGE_DmP_n_12,EXP_STAGE_DmP_n_13,EXP_STAGE_DmP_n_14,EXP_STAGE_DmP_n_15,EXP_STAGE_DmP_n_16,EXP_STAGE_DmP_n_17,EXP_STAGE_DmP_n_18,EXP_STAGE_DmP_n_19,EXP_STAGE_DmP_n_20,EXP_STAGE_DmP_n_21,EXP_STAGE_DmP_n_22,EXP_STAGE_DmP_n_23,EXP_STAGE_DmP_n_24,EXP_STAGE_DmP_n_25,EXP_STAGE_DmP_n_26,EXP_STAGE_DmP_n_27,EXP_STAGE_DmP_n_28}),
.Q({SHT1_STAGE_DmP_mant_n_0,SHT1_STAGE_DmP_mant_n_1,SHT1_STAGE_DmP_mant_n_2,SHT1_STAGE_DmP_mant_n_3,SHT1_STAGE_DmP_mant_n_4,SHT1_STAGE_DmP_mant_n_5,SHT1_STAGE_DmP_mant_n_6,SHT1_STAGE_DmP_mant_n_7,SHT1_STAGE_DmP_mant_n_8,SHT1_STAGE_DmP_mant_n_9,SHT1_STAGE_DmP_mant_n_10,SHT1_STAGE_DmP_mant_n_11,SHT1_STAGE_DmP_mant_n_12,SHT1_STAGE_DmP_mant_n_13,SHT1_STAGE_DmP_mant_n_14,SHT1_STAGE_DmP_mant_n_15,SHT1_STAGE_DmP_mant_n_16,SHT1_STAGE_DmP_mant_n_17,SHT1_STAGE_DmP_mant_n_18,SHT1_STAGE_DmP_mant_n_19,SHT1_STAGE_DmP_mant_n_20,SHT1_STAGE_DmP_mant_n_21,SHT1_STAGE_DmP_mant_n_22}),
.\Q_reg[5]_0 (inst_ShiftRegister_n_2));
RegisterAdd__parameterized7 SHT1_STAGE_FLAGS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({EXP_STAGE_FLAGS_n_0,EXP_STAGE_FLAGS_n_1,EXP_STAGE_FLAGS_n_2}),
.Q({SHT1_STAGE_FLAGS_n_0,SHT1_STAGE_FLAGS_n_1,SHT1_STAGE_FLAGS_n_2}),
.\Q_reg[5] (inst_ShiftRegister_n_2));
RegisterAdd__parameterized6 SHT1_STAGE_sft_amount
(.AR(AR[2]),
.CLK(CLK),
.D(shft_value_mux_o_EWR[4:3]),
.Q({Shift_amount_SHT1_EWR[2],Shift_amount_SHT1_EWR[0]}),
.\Q_reg[1]_0 ({LZD_raw_out_EWR[4:3],LZD_raw_out_EWR[1]}),
.\Q_reg[23] (SHT1_STAGE_sft_amount_n_0),
.\Q_reg[26] ({Shift_amount_EXP_EW,EXP_STAGE_DMP_n_1}),
.\Q_reg[2]_0 (ADD_OVRFLW_NRM),
.\Q_reg[5] ({inst_ShiftRegister_n_2,Shift_reg_FLAGS_7}));
RegisterAdd__parameterized9 SHT2_SHIFT_DATA
(.CLK(CLK),
.D({SHT2_SHIFT_DATA_n_0,SHT2_SHIFT_DATA_n_1,SHT2_SHIFT_DATA_n_2}),
.\Data_array_SWR[4]_4 (\Data_array_SWR[4]_4 ),
.\Data_array_SWR[6]_3 (\Data_array_SWR[6]_3 [1]),
.E(inst_ShiftRegister_n_7),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({left_right_SHT2,SHT2_STAGE_SHFTVARS2_n_7}),
.\Q_reg[13]_0 (\Data_array_SWR[3]_0 ),
.\Q_reg[25]_0 ({sftr_odat_SHT2_SWR[25:24],sftr_odat_SHT2_SWR[13:12],sftr_odat_SHT2_SWR[0]}),
.\Q_reg[2]_0 (\Data_array_SWR[2]_1 ),
.\Q_reg[4]_0 (\Data_array_SWR[6]_3 [25:24]),
.\Q_reg[4]_1 (shift_value_SHT2_EWR),
.\Q_reg[8]_0 ({\Data_array_SWR[5]_2 [17:16],\Data_array_SWR[5]_2 [11:2]}),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
RegisterAdd__parameterized8 SHT2_STAGE_DMP
(.AR({AR[3:2],AR[0]}),
.CLK(CLK),
.D({SHT1_STAGE_DMP_n_0,SHT1_STAGE_DMP_n_1,SHT1_STAGE_DMP_n_2,SHT1_STAGE_DMP_n_3,SHT1_STAGE_DMP_n_4,SHT1_STAGE_DMP_n_5,SHT1_STAGE_DMP_n_6,SHT1_STAGE_DMP_n_7,SHT1_STAGE_DMP_n_8,SHT1_STAGE_DMP_n_9,SHT1_STAGE_DMP_n_10,SHT1_STAGE_DMP_n_11,SHT1_STAGE_DMP_n_12,SHT1_STAGE_DMP_n_13,SHT1_STAGE_DMP_n_14,SHT1_STAGE_DMP_n_15,SHT1_STAGE_DMP_n_16,SHT1_STAGE_DMP_n_17,SHT1_STAGE_DMP_n_18,SHT1_STAGE_DMP_n_19,SHT1_STAGE_DMP_n_20,SHT1_STAGE_DMP_n_21,SHT1_STAGE_DMP_n_22,SHT1_STAGE_DMP_n_23,SHT1_STAGE_DMP_n_24,SHT1_STAGE_DMP_n_25,SHT1_STAGE_DMP_n_26,SHT1_STAGE_DMP_n_27,SHT1_STAGE_DMP_n_28,SHT1_STAGE_DMP_n_29,SHT1_STAGE_DMP_n_30}),
.Q({SHT2_STAGE_DMP_n_0,SHT2_STAGE_DMP_n_1,SHT2_STAGE_DMP_n_2,SHT2_STAGE_DMP_n_3,SHT2_STAGE_DMP_n_4,SHT2_STAGE_DMP_n_5,SHT2_STAGE_DMP_n_6,SHT2_STAGE_DMP_n_7,SHT2_STAGE_DMP_n_8,SHT2_STAGE_DMP_n_9,SHT2_STAGE_DMP_n_10,SHT2_STAGE_DMP_n_11,SHT2_STAGE_DMP_n_12,SHT2_STAGE_DMP_n_13,SHT2_STAGE_DMP_n_14,SHT2_STAGE_DMP_n_15,SHT2_STAGE_DMP_n_16,SHT2_STAGE_DMP_n_17,SHT2_STAGE_DMP_n_18,SHT2_STAGE_DMP_n_19,SHT2_STAGE_DMP_n_20,SHT2_STAGE_DMP_n_21,SHT2_STAGE_DMP_n_22,SHT2_STAGE_DMP_n_23,SHT2_STAGE_DMP_n_24,SHT2_STAGE_DMP_n_25,SHT2_STAGE_DMP_n_26,SHT2_STAGE_DMP_n_27,SHT2_STAGE_DMP_n_28,SHT2_STAGE_DMP_n_29,SHT2_STAGE_DMP_n_30}),
.\Q_reg[4]_0 (Q));
RegisterAdd__parameterized12 SHT2_STAGE_FLAGS
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D({SHT1_STAGE_FLAGS_n_0,SHT1_STAGE_FLAGS_n_1,SHT1_STAGE_FLAGS_n_2}),
.Q({SHT2_STAGE_FLAGS_n_0,SHT2_STAGE_FLAGS_n_1,SHT2_STAGE_FLAGS_n_2}),
.\Q_reg[4] (Q));
RegisterAdd__parameterized10 SHT2_STAGE_SHFTVARS1
(.CLK(CLK),
.D({SHT2_STAGE_SHFTVARS1_n_0,SHT2_STAGE_SHFTVARS1_n_1,SHT2_STAGE_SHFTVARS1_n_2,SHT2_STAGE_SHFTVARS1_n_3,SHT2_STAGE_SHFTVARS1_n_4,SHT2_STAGE_SHFTVARS1_n_5,SHT2_STAGE_SHFTVARS1_n_6,SHT2_STAGE_SHFTVARS1_n_7,SHT2_STAGE_SHFTVARS1_n_8,SHT2_STAGE_SHFTVARS1_n_9,SHT2_STAGE_SHFTVARS1_n_10,SHT2_STAGE_SHFTVARS1_n_11,SHT2_STAGE_SHFTVARS1_n_12,SHT2_STAGE_SHFTVARS1_n_13}),
.\Data_array_SWR[4]_4 (\Data_array_SWR[4]_4 ),
.E(inst_ShiftRegister_n_7),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({left_right_SHT2,SHT2_STAGE_SHFTVARS2_n_7}),
.\Q_reg[0] ({\Data_array_SWR[5]_2 [17:16],\Data_array_SWR[5]_2 [9:2]}),
.\Q_reg[16] (shift_value_SHT2_EWR),
.\Q_reg[23] ({sftr_odat_SHT2_SWR[23:16],sftr_odat_SHT2_SWR[7:1]}),
.\Q_reg[25] ({\Data_array_SWR[6]_3 [25:24],\Data_array_SWR[6]_3 [15:14],\Data_array_SWR[6]_3 [9:8]}),
.\Q_reg[25]_0 (\Data_array_SWR[3]_0 ),
.\Q_reg[4]_0 (\Data_array_SWR[6]_3 [1]),
.\Q_reg[4]_1 (shft_value_mux_o_EWR),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
RegisterAdd__parameterized11 SHT2_STAGE_SHFTVARS2
(.CLK(CLK),
.D({SHT2_STAGE_SHFTVARS2_n_0,SHT2_STAGE_SHFTVARS2_n_1,SHT2_STAGE_SHFTVARS2_n_2,SHT2_STAGE_SHFTVARS2_n_3,SHT2_STAGE_SHFTVARS2_n_4,SHT2_STAGE_SHFTVARS2_n_5}),
.E(inst_ShiftRegister_n_7),
.\FSM_sequential_state_reg_reg[1] (\FSM_sequential_state_reg_reg[1] ),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({left_right_SHT2,SHT2_STAGE_SHFTVARS2_n_7}),
.\Q_reg[0]_0 ({\Data_array_SWR[5]_2 [17:16],\Data_array_SWR[5]_2 [11:10]}),
.\Q_reg[15] ({sftr_odat_SHT2_SWR[15:14],sftr_odat_SHT2_SWR[11:8]}),
.\Q_reg[1]_0 ({left_right_SHT1,bit_shift_SHT1}),
.\Q_reg[4] ({\Data_array_SWR[6]_3 [15:14],\Data_array_SWR[6]_3 [9:8]}),
.\Q_reg[4]_0 (shift_value_SHT2_EWR[4]),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _inferred__1_carry
(.CI(1'b0),
.CO({_inferred__1_carry_n_0,_inferred__1_carry_n_1,_inferred__1_carry_n_2,_inferred__1_carry_n_3}),
.CYINIT(SFT2FRMT_STAGE_VARS_n_14),
.DI({SFT2FRMT_STAGE_VARS_n_11,SFT2FRMT_STAGE_VARS_n_12,SFT2FRMT_STAGE_VARS_n_13,SFT2FRMT_STAGE_FLAGS_n_1}),
.O(exp_rslt_NRM2_EW1[3:0]),
.S({SFT2FRMT_STAGE_VARS_n_0,SFT2FRMT_STAGE_VARS_n_1,SFT2FRMT_STAGE_VARS_n_2,SFT2FRMT_STAGE_VARS_n_3}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _inferred__1_carry__0
(.CI(_inferred__1_carry_n_0),
.CO({_inferred__1_carry__0_n_0,_inferred__1_carry__0_n_1,_inferred__1_carry__0_n_2,_inferred__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({SFT2FRMT_STAGE_VARS_n_8,SFT2FRMT_STAGE_VARS_n_9,ADD_OVRFLW_NRM2,SFT2FRMT_STAGE_VARS_n_10}),
.O(exp_rslt_NRM2_EW1[7:4]),
.S({SFT2FRMT_STAGE_VARS_n_4,SFT2FRMT_STAGE_VARS_n_5,SFT2FRMT_STAGE_VARS_n_6,SFT2FRMT_STAGE_VARS_n_7}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 _inferred__1_carry__1
(.CI(_inferred__1_carry__0_n_0),
.CO(NLW__inferred__1_carry__1_CO_UNCONNECTED[3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW__inferred__1_carry__1_O_UNCONNECTED[3:1],exp_rslt_NRM2_EW1[8]}),
.S({1'b0,1'b0,1'b0,SFT2FRMT_STAGE_VARS_n_23}));
FSM_INPUT_ENABLE inst_FSM_INPUT_ENABLE
(.CLK(CLK),
.D(FSM_enable_input_internal),
.E(enable_shift_reg),
.\FSM_sequential_state_reg_reg[1]_0 (\FSM_sequential_state_reg_reg[1] ),
.\FSM_sequential_state_reg_reg[2]_0 (\FSM_sequential_state_reg_reg[2] ),
.out(out));
ShiftRegister inst_ShiftRegister
(.AR({AR[2],AR[0]}),
.CLK(CLK),
.D(FSM_enable_input_internal),
.E(load0),
.\FSM_sequential_state_reg_reg[0] (enable_shift_reg),
.Q({inst_ShiftRegister_n_1,inst_ShiftRegister_n_2,Q,inst_ShiftRegister_n_4,Shift_reg_FLAGS_7,inst_ShiftRegister_n_6}),
.\Q_reg[1]_0 (inst_ShiftRegister_n_7),
.\Q_reg[1]_1 ({left_right_SHT1,bit_shift_SHT1}),
.\Q_reg[2]_0 (ADD_OVRFLW_NRM));
sgn_result result_sign_bit
(.CO(gtXY),
.D(SIGN_FLAG_INIT),
.Q(intDY_EWSW),
.\Q_reg[30] (eqXY),
.\Q_reg[31] (intDX_EWSW),
.intAS(intAS));
endmodule
module FSM_INPUT_ENABLE
(out,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1]_0 ,
\FSM_sequential_state_reg_reg[2]_0 );
output [0:0]out;
output [0:0]E;
output [0:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1]_0 ;
input [1:0]\FSM_sequential_state_reg_reg[2]_0 ;
wire CLK;
wire [0:0]D;
wire [0:0]E;
wire \FSM_sequential_state_reg[0]_i_1_n_0 ;
wire \FSM_sequential_state_reg[1]_i_1_n_0 ;
wire \FSM_sequential_state_reg[2]_i_1_n_0 ;
wire [0:0]\FSM_sequential_state_reg_reg[1]_0 ;
wire [1:0]\FSM_sequential_state_reg_reg[2]_0 ;
(* RTL_KEEP = "yes" *) wire [0:0]out;
(* RTL_KEEP = "yes" *) wire [1:0]state_reg;
LUT5 #(
.INIT(32'h14145514))
\FSM_sequential_state_reg[0]_i_1
(.I0(state_reg[0]),
.I1(state_reg[1]),
.I2(out),
.I3(\FSM_sequential_state_reg_reg[2]_0 [1]),
.I4(\FSM_sequential_state_reg_reg[2]_0 [0]),
.O(\FSM_sequential_state_reg[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'h26))
\FSM_sequential_state_reg[1]_i_1
(.I0(state_reg[0]),
.I1(state_reg[1]),
.I2(out),
.O(\FSM_sequential_state_reg[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'h38))
\FSM_sequential_state_reg[2]_i_1
(.I0(state_reg[0]),
.I1(state_reg[1]),
.I2(out),
.O(\FSM_sequential_state_reg[2]_i_1_n_0 ));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[1]_0 ),
.D(\FSM_sequential_state_reg[0]_i_1_n_0 ),
.Q(state_reg[0]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[1]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[1]_0 ),
.D(\FSM_sequential_state_reg[1]_i_1_n_0 ),
.Q(state_reg[1]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[2]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[1]_0 ),
.D(\FSM_sequential_state_reg[2]_i_1_n_0 ),
.Q(out));
LUT1 #(
.INIT(2'h1))
\Q[6]_i_1__0
(.I0(out),
.O(D));
LUT3 #(
.INIT(8'h7E))
__0
(.I0(state_reg[0]),
.I1(out),
.I2(state_reg[1]),
.O(E));
endmodule
module MultiplexTxT
(\Q_reg[30] ,
\Q_reg[27] ,
Q,
\Q_reg[30]_0 ,
CO);
output [30:0]\Q_reg[30] ;
output [27:0]\Q_reg[27] ;
input [30:0]Q;
input [30:0]\Q_reg[30]_0 ;
input [0:0]CO;
wire [0:0]CO;
wire [30:0]Q;
wire [27:0]\Q_reg[27] ;
wire [30:0]\Q_reg[30] ;
wire [30:0]\Q_reg[30]_0 ;
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\Q[0]_i_1
(.I0(Q[0]),
.I1(\Q_reg[30]_0 [0]),
.I2(CO),
.O(\Q_reg[30] [0]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\Q[0]_i_1__0
(.I0(\Q_reg[30]_0 [0]),
.I1(Q[0]),
.I2(CO),
.O(\Q_reg[27] [0]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1
(.I0(Q[10]),
.I1(\Q_reg[30]_0 [10]),
.I2(CO),
.O(\Q_reg[30] [10]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1__0
(.I0(\Q_reg[30]_0 [10]),
.I1(Q[10]),
.I2(CO),
.O(\Q_reg[27] [10]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1
(.I0(Q[11]),
.I1(\Q_reg[30]_0 [11]),
.I2(CO),
.O(\Q_reg[30] [11]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1__0
(.I0(\Q_reg[30]_0 [11]),
.I1(Q[11]),
.I2(CO),
.O(\Q_reg[27] [11]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1
(.I0(Q[12]),
.I1(\Q_reg[30]_0 [12]),
.I2(CO),
.O(\Q_reg[30] [12]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1__0
(.I0(\Q_reg[30]_0 [12]),
.I1(Q[12]),
.I2(CO),
.O(\Q_reg[27] [12]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1
(.I0(Q[13]),
.I1(\Q_reg[30]_0 [13]),
.I2(CO),
.O(\Q_reg[30] [13]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1__0
(.I0(\Q_reg[30]_0 [13]),
.I1(Q[13]),
.I2(CO),
.O(\Q_reg[27] [13]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1
(.I0(Q[14]),
.I1(\Q_reg[30]_0 [14]),
.I2(CO),
.O(\Q_reg[30] [14]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1__0
(.I0(\Q_reg[30]_0 [14]),
.I1(Q[14]),
.I2(CO),
.O(\Q_reg[27] [14]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1
(.I0(Q[15]),
.I1(\Q_reg[30]_0 [15]),
.I2(CO),
.O(\Q_reg[30] [15]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1__0
(.I0(\Q_reg[30]_0 [15]),
.I1(Q[15]),
.I2(CO),
.O(\Q_reg[27] [15]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1
(.I0(Q[16]),
.I1(\Q_reg[30]_0 [16]),
.I2(CO),
.O(\Q_reg[30] [16]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1__0
(.I0(\Q_reg[30]_0 [16]),
.I1(Q[16]),
.I2(CO),
.O(\Q_reg[27] [16]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1
(.I0(Q[17]),
.I1(\Q_reg[30]_0 [17]),
.I2(CO),
.O(\Q_reg[30] [17]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1__0
(.I0(\Q_reg[30]_0 [17]),
.I1(Q[17]),
.I2(CO),
.O(\Q_reg[27] [17]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1
(.I0(Q[18]),
.I1(\Q_reg[30]_0 [18]),
.I2(CO),
.O(\Q_reg[30] [18]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1__0
(.I0(\Q_reg[30]_0 [18]),
.I1(Q[18]),
.I2(CO),
.O(\Q_reg[27] [18]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1
(.I0(Q[19]),
.I1(\Q_reg[30]_0 [19]),
.I2(CO),
.O(\Q_reg[30] [19]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1__0
(.I0(\Q_reg[30]_0 [19]),
.I1(Q[19]),
.I2(CO),
.O(\Q_reg[27] [19]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1
(.I0(Q[1]),
.I1(\Q_reg[30]_0 [1]),
.I2(CO),
.O(\Q_reg[30] [1]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1__0
(.I0(\Q_reg[30]_0 [1]),
.I1(Q[1]),
.I2(CO),
.O(\Q_reg[27] [1]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1
(.I0(Q[20]),
.I1(\Q_reg[30]_0 [20]),
.I2(CO),
.O(\Q_reg[30] [20]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1__0
(.I0(\Q_reg[30]_0 [20]),
.I1(Q[20]),
.I2(CO),
.O(\Q_reg[27] [20]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1
(.I0(Q[21]),
.I1(\Q_reg[30]_0 [21]),
.I2(CO),
.O(\Q_reg[30] [21]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1__0
(.I0(\Q_reg[30]_0 [21]),
.I1(Q[21]),
.I2(CO),
.O(\Q_reg[27] [21]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1
(.I0(Q[22]),
.I1(\Q_reg[30]_0 [22]),
.I2(CO),
.O(\Q_reg[30] [22]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1__0
(.I0(\Q_reg[30]_0 [22]),
.I1(Q[22]),
.I2(CO),
.O(\Q_reg[27] [22]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1
(.I0(Q[23]),
.I1(\Q_reg[30]_0 [23]),
.I2(CO),
.O(\Q_reg[30] [23]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1__0
(.I0(\Q_reg[30]_0 [23]),
.I1(Q[23]),
.I2(CO),
.O(\Q_reg[27] [23]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1
(.I0(Q[24]),
.I1(\Q_reg[30]_0 [24]),
.I2(CO),
.O(\Q_reg[30] [24]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1__0
(.I0(\Q_reg[30]_0 [24]),
.I1(Q[24]),
.I2(CO),
.O(\Q_reg[27] [24]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1
(.I0(Q[25]),
.I1(\Q_reg[30]_0 [25]),
.I2(CO),
.O(\Q_reg[30] [25]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1__0
(.I0(\Q_reg[30]_0 [25]),
.I1(Q[25]),
.I2(CO),
.O(\Q_reg[27] [25]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hAC))
\Q[26]_i_1
(.I0(Q[26]),
.I1(\Q_reg[30]_0 [26]),
.I2(CO),
.O(\Q_reg[30] [26]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hAC))
\Q[26]_i_1__0
(.I0(\Q_reg[30]_0 [26]),
.I1(Q[26]),
.I2(CO),
.O(\Q_reg[27] [26]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hAC))
\Q[27]_i_1
(.I0(Q[27]),
.I1(\Q_reg[30]_0 [27]),
.I2(CO),
.O(\Q_reg[30] [27]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hAC))
\Q[27]_i_1__0
(.I0(\Q_reg[30]_0 [27]),
.I1(Q[27]),
.I2(CO),
.O(\Q_reg[27] [27]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hAC))
\Q[28]_i_1
(.I0(Q[28]),
.I1(\Q_reg[30]_0 [28]),
.I2(CO),
.O(\Q_reg[30] [28]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hAC))
\Q[29]_i_1
(.I0(Q[29]),
.I1(\Q_reg[30]_0 [29]),
.I2(CO),
.O(\Q_reg[30] [29]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1
(.I0(Q[2]),
.I1(\Q_reg[30]_0 [2]),
.I2(CO),
.O(\Q_reg[30] [2]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1__0
(.I0(\Q_reg[30]_0 [2]),
.I1(Q[2]),
.I2(CO),
.O(\Q_reg[27] [2]));
LUT3 #(
.INIT(8'hAC))
\Q[30]_i_1
(.I0(Q[30]),
.I1(\Q_reg[30]_0 [30]),
.I2(CO),
.O(\Q_reg[30] [30]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1
(.I0(Q[3]),
.I1(\Q_reg[30]_0 [3]),
.I2(CO),
.O(\Q_reg[30] [3]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1__0
(.I0(\Q_reg[30]_0 [3]),
.I1(Q[3]),
.I2(CO),
.O(\Q_reg[27] [3]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1
(.I0(Q[4]),
.I1(\Q_reg[30]_0 [4]),
.I2(CO),
.O(\Q_reg[30] [4]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1__0
(.I0(\Q_reg[30]_0 [4]),
.I1(Q[4]),
.I2(CO),
.O(\Q_reg[27] [4]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1
(.I0(Q[5]),
.I1(\Q_reg[30]_0 [5]),
.I2(CO),
.O(\Q_reg[30] [5]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1__0
(.I0(\Q_reg[30]_0 [5]),
.I1(Q[5]),
.I2(CO),
.O(\Q_reg[27] [5]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1
(.I0(Q[6]),
.I1(\Q_reg[30]_0 [6]),
.I2(CO),
.O(\Q_reg[30] [6]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1__0
(.I0(\Q_reg[30]_0 [6]),
.I1(Q[6]),
.I2(CO),
.O(\Q_reg[27] [6]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1
(.I0(Q[7]),
.I1(\Q_reg[30]_0 [7]),
.I2(CO),
.O(\Q_reg[30] [7]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1__0
(.I0(\Q_reg[30]_0 [7]),
.I1(Q[7]),
.I2(CO),
.O(\Q_reg[27] [7]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1
(.I0(Q[8]),
.I1(\Q_reg[30]_0 [8]),
.I2(CO),
.O(\Q_reg[30] [8]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1__0
(.I0(\Q_reg[30]_0 [8]),
.I1(Q[8]),
.I2(CO),
.O(\Q_reg[27] [8]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1
(.I0(Q[9]),
.I1(\Q_reg[30]_0 [9]),
.I2(CO),
.O(\Q_reg[30] [9]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1__0
(.I0(\Q_reg[30]_0 [9]),
.I1(Q[9]),
.I2(CO),
.O(\Q_reg[27] [9]));
endmodule
module RegisterAdd
(UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[31]_0 ,
exp_rslt_NRM2_EW1,
Q,
D,
CLK,
AR);
output UNDRFLW_FLAG_FRMT;
output OVRFLW_FLAG_FRMT;
output [31:0]\Q_reg[31]_0 ;
input [8:0]exp_rslt_NRM2_EW1;
input [0:0]Q;
input [31:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [31:0]D;
wire OVRFLW_FLAG_FRMT;
wire [0:0]Q;
wire \Q[1]_i_2__1_n_0 ;
wire \Q[2]_i_2__0_n_0 ;
wire [31:0]\Q_reg[31]_0 ;
wire UNDRFLW_FLAG_FRMT;
wire [8:0]exp_rslt_NRM2_EW1;
LUT5 #(
.INIT(32'h00000001))
\Q[1]_i_1__9
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(exp_rslt_NRM2_EW1[6]),
.I2(exp_rslt_NRM2_EW1[8]),
.I3(exp_rslt_NRM2_EW1[7]),
.I4(\Q[1]_i_2__1_n_0 ),
.O(UNDRFLW_FLAG_FRMT));
LUT5 #(
.INIT(32'hFFFFFFFE))
\Q[1]_i_2__1
(.I0(exp_rslt_NRM2_EW1[2]),
.I1(exp_rslt_NRM2_EW1[0]),
.I2(exp_rslt_NRM2_EW1[1]),
.I3(exp_rslt_NRM2_EW1[4]),
.I4(exp_rslt_NRM2_EW1[3]),
.O(\Q[1]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'hEAAAAAAAAAAAAAAA))
\Q[2]_i_1__7
(.I0(exp_rslt_NRM2_EW1[8]),
.I1(\Q[2]_i_2__0_n_0 ),
.I2(exp_rslt_NRM2_EW1[1]),
.I3(exp_rslt_NRM2_EW1[0]),
.I4(exp_rslt_NRM2_EW1[3]),
.I5(exp_rslt_NRM2_EW1[2]),
.O(OVRFLW_FLAG_FRMT));
LUT4 #(
.INIT(16'h8000))
\Q[2]_i_2__0
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(exp_rslt_NRM2_EW1[4]),
.I2(exp_rslt_NRM2_EW1[6]),
.I3(exp_rslt_NRM2_EW1[7]),
.O(\Q[2]_i_2__0_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[0]),
.Q(\Q_reg[31]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[10]),
.Q(\Q_reg[31]_0 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[11]),
.Q(\Q_reg[31]_0 [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[12]),
.Q(\Q_reg[31]_0 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[13]),
.Q(\Q_reg[31]_0 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[14]),
.Q(\Q_reg[31]_0 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[15]),
.Q(\Q_reg[31]_0 [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[16]),
.Q(\Q_reg[31]_0 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[17]),
.Q(\Q_reg[31]_0 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[18]),
.Q(\Q_reg[31]_0 [18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[19]),
.Q(\Q_reg[31]_0 [19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[1]),
.Q(\Q_reg[31]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[20]),
.Q(\Q_reg[31]_0 [20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[21]),
.Q(\Q_reg[31]_0 [21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[22]),
.Q(\Q_reg[31]_0 [22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[23]),
.Q(\Q_reg[31]_0 [23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[24]),
.Q(\Q_reg[31]_0 [24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[25]),
.Q(\Q_reg[31]_0 [25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[26]),
.Q(\Q_reg[31]_0 [26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[27]),
.Q(\Q_reg[31]_0 [27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[28]),
.Q(\Q_reg[31]_0 [28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[29]),
.Q(\Q_reg[31]_0 [29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[2]),
.Q(\Q_reg[31]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[30]),
.Q(\Q_reg[31]_0 [30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[31]),
.Q(\Q_reg[31]_0 [31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[3]),
.Q(\Q_reg[31]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[4]),
.Q(\Q_reg[31]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[5]),
.Q(\Q_reg[31]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[6]),
.Q(\Q_reg[31]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(D[7]),
.Q(\Q_reg[31]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[8]),
.Q(\Q_reg[31]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(D[9]),
.Q(\Q_reg[31]_0 [9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_1
(DI,
Q,
\Q_reg[2]_0 ,
S,
\Q_reg[2]_1 ,
\Q_reg[2]_2 ,
\Q_reg[2]_3 ,
\Q_reg[2]_4 ,
\Q_reg[2]_5 ,
\Q_reg[2]_6 ,
\Q_reg[2]_7 ,
\Q_reg[2]_8 ,
D,
\Q_reg[31]_0 ,
intAS,
E,
\Q_reg[31]_1 ,
CLK,
\FSM_sequential_state_reg_reg[1] ,
AR);
output [3:0]DI;
output [31:0]Q;
output [3:0]\Q_reg[2]_0 ;
output [3:0]S;
output [3:0]\Q_reg[2]_1 ;
output [3:0]\Q_reg[2]_2 ;
output [3:0]\Q_reg[2]_3 ;
output [3:0]\Q_reg[2]_4 ;
output [3:0]\Q_reg[2]_5 ;
output [3:0]\Q_reg[2]_6 ;
output [2:0]\Q_reg[2]_7 ;
output [1:0]\Q_reg[2]_8 ;
output [0:0]D;
input [31:0]\Q_reg[31]_0 ;
input intAS;
input [0:0]E;
input [31:0]\Q_reg[31]_1 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [3:0]DI;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire [3:0]\Q_reg[2]_0 ;
wire [3:0]\Q_reg[2]_1 ;
wire [3:0]\Q_reg[2]_2 ;
wire [3:0]\Q_reg[2]_3 ;
wire [3:0]\Q_reg[2]_4 ;
wire [3:0]\Q_reg[2]_5 ;
wire [3:0]\Q_reg[2]_6 ;
wire [2:0]\Q_reg[2]_7 ;
wire [1:0]\Q_reg[2]_8 ;
wire [31:0]\Q_reg[31]_0 ;
wire [31:0]\Q_reg[31]_1 ;
wire [3:0]S;
wire intAS;
LUT3 #(
.INIT(8'h96))
\Q[1]_i_1__8
(.I0(Q[31]),
.I1(\Q_reg[31]_0 [31]),
.I2(intAS),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_1 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[31]_1 [9]),
.Q(Q[9]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_1
(.I0(Q[21]),
.I1(\Q_reg[31]_0 [21]),
.I2(\Q_reg[31]_0 [23]),
.I3(Q[23]),
.I4(\Q_reg[31]_0 [22]),
.I5(Q[22]),
.O(\Q_reg[2]_5 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_2
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(\Q_reg[31]_0 [20]),
.I3(Q[20]),
.I4(\Q_reg[31]_0 [19]),
.I5(Q[19]),
.O(\Q_reg[2]_5 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_3
(.I0(Q[15]),
.I1(\Q_reg[31]_0 [15]),
.I2(\Q_reg[31]_0 [17]),
.I3(Q[17]),
.I4(\Q_reg[31]_0 [16]),
.I5(Q[16]),
.O(\Q_reg[2]_5 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_4
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(\Q_reg[31]_0 [14]),
.I3(Q[14]),
.I4(\Q_reg[31]_0 [13]),
.I5(Q[13]),
.O(\Q_reg[2]_5 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__1_i_2
(.I0(Q[27]),
.I1(\Q_reg[31]_0 [27]),
.I2(\Q_reg[31]_0 [29]),
.I3(Q[29]),
.I4(\Q_reg[31]_0 [28]),
.I5(Q[28]),
.O(\Q_reg[2]_8 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__1_i_3
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(\Q_reg[31]_0 [26]),
.I3(Q[26]),
.I4(\Q_reg[31]_0 [25]),
.I5(Q[25]),
.O(\Q_reg[2]_8 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_1
(.I0(Q[9]),
.I1(\Q_reg[31]_0 [9]),
.I2(\Q_reg[31]_0 [11]),
.I3(Q[11]),
.I4(\Q_reg[31]_0 [10]),
.I5(Q[10]),
.O(\Q_reg[2]_3 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_2
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(\Q_reg[31]_0 [8]),
.I3(Q[8]),
.I4(\Q_reg[31]_0 [7]),
.I5(Q[7]),
.O(\Q_reg[2]_3 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_3
(.I0(Q[3]),
.I1(\Q_reg[31]_0 [3]),
.I2(\Q_reg[31]_0 [5]),
.I3(Q[5]),
.I4(\Q_reg[31]_0 [4]),
.I5(Q[4]),
.O(\Q_reg[2]_3 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_4
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(\Q_reg[31]_0 [2]),
.I3(Q[2]),
.I4(\Q_reg[31]_0 [1]),
.I5(Q[1]),
.O(\Q_reg[2]_3 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_1
(.I0(Q[14]),
.I1(\Q_reg[31]_0 [14]),
.I2(\Q_reg[31]_0 [15]),
.I3(Q[15]),
.O(\Q_reg[2]_1 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_2
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(\Q_reg[31]_0 [13]),
.I3(Q[13]),
.O(\Q_reg[2]_1 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_3
(.I0(Q[10]),
.I1(\Q_reg[31]_0 [10]),
.I2(\Q_reg[31]_0 [11]),
.I3(Q[11]),
.O(\Q_reg[2]_1 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_4
(.I0(Q[8]),
.I1(\Q_reg[31]_0 [8]),
.I2(\Q_reg[31]_0 [9]),
.I3(Q[9]),
.O(\Q_reg[2]_1 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_5
(.I0(Q[14]),
.I1(\Q_reg[31]_0 [14]),
.I2(Q[15]),
.I3(\Q_reg[31]_0 [15]),
.O(\Q_reg[2]_2 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_6
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(Q[13]),
.I3(\Q_reg[31]_0 [13]),
.O(\Q_reg[2]_2 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_7
(.I0(Q[10]),
.I1(\Q_reg[31]_0 [10]),
.I2(Q[11]),
.I3(\Q_reg[31]_0 [11]),
.O(\Q_reg[2]_2 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_8
(.I0(Q[8]),
.I1(\Q_reg[31]_0 [8]),
.I2(Q[9]),
.I3(\Q_reg[31]_0 [9]),
.O(\Q_reg[2]_2 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_1
(.I0(Q[22]),
.I1(\Q_reg[31]_0 [22]),
.I2(\Q_reg[31]_0 [23]),
.I3(Q[23]),
.O(\Q_reg[2]_4 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_2
(.I0(Q[20]),
.I1(\Q_reg[31]_0 [20]),
.I2(\Q_reg[31]_0 [21]),
.I3(Q[21]),
.O(\Q_reg[2]_4 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_3
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(\Q_reg[31]_0 [19]),
.I3(Q[19]),
.O(\Q_reg[2]_4 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_4
(.I0(Q[16]),
.I1(\Q_reg[31]_0 [16]),
.I2(\Q_reg[31]_0 [17]),
.I3(Q[17]),
.O(\Q_reg[2]_4 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_5
(.I0(Q[22]),
.I1(\Q_reg[31]_0 [22]),
.I2(Q[23]),
.I3(\Q_reg[31]_0 [23]),
.O(\Q_reg[2]_6 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_6
(.I0(Q[20]),
.I1(\Q_reg[31]_0 [20]),
.I2(Q[21]),
.I3(\Q_reg[31]_0 [21]),
.O(\Q_reg[2]_6 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_7
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(Q[19]),
.I3(\Q_reg[31]_0 [19]),
.O(\Q_reg[2]_6 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_8
(.I0(Q[16]),
.I1(\Q_reg[31]_0 [16]),
.I2(Q[17]),
.I3(\Q_reg[31]_0 [17]),
.O(\Q_reg[2]_6 [0]));
LUT2 #(
.INIT(4'h2))
gtXY_o_carry__2_i_1
(.I0(Q[30]),
.I1(\Q_reg[31]_0 [30]),
.O(DI[3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_2
(.I0(Q[28]),
.I1(\Q_reg[31]_0 [28]),
.I2(\Q_reg[31]_0 [29]),
.I3(Q[29]),
.O(DI[2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_3
(.I0(Q[26]),
.I1(\Q_reg[31]_0 [26]),
.I2(\Q_reg[31]_0 [27]),
.I3(Q[27]),
.O(DI[1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_4
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(\Q_reg[31]_0 [25]),
.I3(Q[25]),
.O(DI[0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_6
(.I0(Q[28]),
.I1(\Q_reg[31]_0 [28]),
.I2(Q[29]),
.I3(\Q_reg[31]_0 [29]),
.O(\Q_reg[2]_7 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_7
(.I0(Q[26]),
.I1(\Q_reg[31]_0 [26]),
.I2(Q[27]),
.I3(\Q_reg[31]_0 [27]),
.O(\Q_reg[2]_7 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_8
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(Q[25]),
.I3(\Q_reg[31]_0 [25]),
.O(\Q_reg[2]_7 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_1
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(\Q_reg[31]_0 [7]),
.I3(Q[7]),
.O(\Q_reg[2]_0 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_2
(.I0(Q[4]),
.I1(\Q_reg[31]_0 [4]),
.I2(\Q_reg[31]_0 [5]),
.I3(Q[5]),
.O(\Q_reg[2]_0 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_3
(.I0(Q[2]),
.I1(\Q_reg[31]_0 [2]),
.I2(\Q_reg[31]_0 [3]),
.I3(Q[3]),
.O(\Q_reg[2]_0 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_4
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(\Q_reg[31]_0 [1]),
.I3(Q[1]),
.O(\Q_reg[2]_0 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_5
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(Q[7]),
.I3(\Q_reg[31]_0 [7]),
.O(S[3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_6
(.I0(Q[4]),
.I1(\Q_reg[31]_0 [4]),
.I2(Q[5]),
.I3(\Q_reg[31]_0 [5]),
.O(S[2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_7
(.I0(Q[2]),
.I1(\Q_reg[31]_0 [2]),
.I2(Q[3]),
.I3(\Q_reg[31]_0 [3]),
.O(S[1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_8
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(Q[1]),
.I3(\Q_reg[31]_0 [1]),
.O(S[0]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_2
(S,
Q,
\Q_reg[2]_0 ,
\Q_reg[30]_0 ,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [0:0]S;
output [31:0]Q;
output [0:0]\Q_reg[2]_0 ;
input [0:0]\Q_reg[30]_0 ;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire [0:0]\Q_reg[2]_0 ;
wire [0:0]\Q_reg[30]_0 ;
wire [0:0]S;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
LUT2 #(
.INIT(4'h9))
eqXY_o_carry__1_i_1
(.I0(Q[30]),
.I1(\Q_reg[30]_0 ),
.O(S));
LUT2 #(
.INIT(4'h9))
gtXY_o_carry__2_i_5
(.I0(Q[30]),
.I1(\Q_reg[30]_0 ),
.O(\Q_reg[2]_0 ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized0
(intAS,
D,
E,
op_add_subt,
CLK,
\FSM_sequential_state_reg_reg[1] ,
Q,
\Q_reg[31] ,
CO);
output intAS;
output [0:0]D;
input [0:0]E;
input op_add_subt;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
input [0:0]Q;
input [0:0]\Q_reg[31] ;
input [0:0]CO;
wire CLK;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [0:0]Q;
wire [0:0]\Q_reg[31] ;
wire intAS;
wire op_add_subt;
LUT4 #(
.INIT(16'h9600))
\Q[0]_i_1__10
(.I0(intAS),
.I1(Q),
.I2(\Q_reg[31] ),
.I3(CO),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(op_add_subt),
.Q(intAS));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized1
(D,
Q,
\Q_reg[25]_0 ,
\Q_reg[6]_0 ,
\Q_reg[30]_0 ,
CLK,
AR);
output [1:0]D;
output [30:0]Q;
input [2:0]\Q_reg[25]_0 ;
input [0:0]\Q_reg[6]_0 ;
input [30:0]\Q_reg[30]_0 ;
input CLK;
input [2:0]AR;
wire [2:0]AR;
wire CLK;
wire [1:0]D;
wire [30:0]Q;
wire [2:0]\Q_reg[25]_0 ;
wire [30:0]\Q_reg[30]_0 ;
wire [0:0]\Q_reg[6]_0 ;
LUT2 #(
.INIT(4'h6))
\Q[0]_i_1__11
(.I0(Q[23]),
.I1(\Q_reg[25]_0 [0]),
.O(D[0]));
LUT6 #(
.INIT(64'h4F04B0FBB0FB4F04))
\Q[2]_i_1__9
(.I0(Q[23]),
.I1(\Q_reg[25]_0 [0]),
.I2(Q[24]),
.I3(\Q_reg[25]_0 [1]),
.I4(\Q_reg[25]_0 [2]),
.I5(Q[25]),
.O(D[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized10
(D,
\Q_reg[25] ,
\Q_reg[23] ,
\Q_reg[16] ,
\Q_reg[4]_0 ,
Q,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[0] ,
\Q_reg[25]_0 ,
\Data_array_SWR[4]_4 ,
E,
\Q_reg[4]_1 ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [13:0]D;
output [5:0]\Q_reg[25] ;
output [14:0]\Q_reg[23] ;
output [2:0]\Q_reg[16] ;
input [0:0]\Q_reg[4]_0 ;
input [1:0]Q;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [9:0]\Q_reg[0] ;
input [7:0]\Q_reg[25]_0 ;
input [1:0]\Data_array_SWR[4]_4 ;
input [0:0]E;
input [2:0]\Q_reg[4]_1 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [13:0]D;
wire [1:0]\Data_array_SWR[4]_4 ;
wire [21:18]\Data_array_SWR[5]_2 ;
wire [23:2]\Data_array_SWR[6]_3 ;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [9:0]\Q_reg[0] ;
wire [2:0]\Q_reg[16] ;
wire [14:0]\Q_reg[23] ;
wire [5:0]\Q_reg[25] ;
wire [7:0]\Q_reg[25]_0 ;
wire [0:0]\Q_reg[4]_0 ;
wire [2:0]\Q_reg[4]_1 ;
wire UNDRFLW_FLAG_FRMT;
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[0]_i_1__12
(.I0(\Data_array_SWR[6]_3 [23]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [2]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[0]));
LUT6 #(
.INIT(64'hCDC8DDDDCDC88888))
\Q[12]_i_3__0
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [1]),
.I5(\Data_array_SWR[4]_4 [0]),
.O(\Q_reg[25] [2]));
LUT6 #(
.INIT(64'hCDC8DDDDCDC88888))
\Q[13]_i_3__0
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [1]),
.I5(\Data_array_SWR[4]_4 [1]),
.O(\Q_reg[25] [3]));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'h02))
\Q[14]_i_1__7
(.I0(\Q_reg[23] [7]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'h02))
\Q[15]_i_1__6
(.I0(\Q_reg[23] [8]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[7]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[16]_i_1__6
(.I0(\Q_reg[25] [1]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[16] [2]),
.I4(\Q_reg[0] [8]),
.O(\Q_reg[23] [7]));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[16]_i_1__8
(.I0(\Data_array_SWR[6]_3 [7]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [18]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[8]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[16]_i_2__0
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [5]),
.O(\Data_array_SWR[6]_3 [7]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[16]_i_2__1
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [7]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [7]),
.O(\Q_reg[25] [1]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[16]_i_3__0
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [0]),
.O(\Data_array_SWR[6]_3 [18]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[17]_i_1__6
(.I0(\Q_reg[25] [0]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[16] [2]),
.I4(\Q_reg[0] [9]),
.O(\Q_reg[23] [8]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[17]_i_1__7
(.I0(\Data_array_SWR[6]_3 [6]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [19]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[9]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[17]_i_2__0
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [4]),
.O(\Data_array_SWR[6]_3 [6]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[17]_i_2__1
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [6]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [6]),
.O(\Q_reg[25] [0]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[17]_i_3__0
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [1]),
.O(\Data_array_SWR[6]_3 [19]));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\Q[18]_i_1__6
(.I0(\Data_array_SWR[6]_3 [7]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [18]),
.O(\Q_reg[23] [9]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[18]_i_1__8
(.I0(\Data_array_SWR[6]_3 [5]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [20]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\Q[18]_i_2__0
(.I0(\Data_array_SWR[5]_2 [21]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [3]),
.O(\Data_array_SWR[6]_3 [5]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[18]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [6]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [2]),
.O(\Data_array_SWR[6]_3 [20]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[18]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [7]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [3]),
.O(\Data_array_SWR[5]_2 [21]));
LUT3 #(
.INIT(8'hB8))
\Q[19]_i_1__6
(.I0(\Data_array_SWR[6]_3 [6]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [19]),
.O(\Q_reg[23] [10]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[19]_i_1__7
(.I0(\Data_array_SWR[6]_3 [4]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [21]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[11]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\Q[19]_i_2__0
(.I0(\Data_array_SWR[5]_2 [20]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [2]),
.O(\Data_array_SWR[6]_3 [4]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[19]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [7]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [3]),
.O(\Data_array_SWR[6]_3 [21]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[19]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [6]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [2]),
.O(\Data_array_SWR[5]_2 [20]));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\Q[1]_i_1__10
(.I0(\Q_reg[25] [4]),
.I1(Q[1]),
.I2(\Q_reg[4]_0 ),
.O(\Q_reg[23] [0]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[1]_i_1__13
(.I0(\Data_array_SWR[6]_3 [22]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [3]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\Q[20]_i_1__6
(.I0(\Data_array_SWR[6]_3 [5]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [20]),
.O(\Q_reg[23] [11]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[20]_i_1__8
(.I0(\Data_array_SWR[6]_3 [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [22]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\Q[20]_i_2__0
(.I0(\Data_array_SWR[5]_2 [19]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [1]),
.O(\Data_array_SWR[6]_3 [3]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[20]_i_3
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [4]),
.O(\Data_array_SWR[6]_3 [22]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[20]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [5]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [1]),
.O(\Data_array_SWR[5]_2 [19]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\Q[21]_i_1__7
(.I0(\Data_array_SWR[6]_3 [4]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [21]),
.O(\Q_reg[23] [12]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[21]_i_1__8
(.I0(\Data_array_SWR[6]_3 [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [23]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\Q[21]_i_2__0
(.I0(\Data_array_SWR[5]_2 [18]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [0]),
.O(\Data_array_SWR[6]_3 [2]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[21]_i_3
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [5]),
.O(\Data_array_SWR[6]_3 [23]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[21]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [4]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [0]),
.O(\Data_array_SWR[5]_2 [18]));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\Q[22]_i_1__7
(.I0(\Data_array_SWR[6]_3 [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [22]),
.O(\Q_reg[23] [13]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[22]_i_3
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [6]),
.O(\Q_reg[25] [4]));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\Q[23]_i_1__7
(.I0(\Data_array_SWR[6]_3 [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [23]),
.O(\Q_reg[23] [14]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[25]_i_4__0
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [7]),
.O(\Q_reg[25] [5]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[2]_i_1__12
(.I0(\Data_array_SWR[6]_3 [21]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [4]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\Q[2]_i_1__8
(.I0(\Data_array_SWR[6]_3 [23]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [2]),
.O(\Q_reg[23] [1]));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\Q[3]_i_1__7
(.I0(\Data_array_SWR[6]_3 [22]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [3]),
.O(\Q_reg[23] [2]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[3]_i_1__9
(.I0(\Data_array_SWR[6]_3 [20]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [5]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[4]_i_1__10
(.I0(\Data_array_SWR[6]_3 [19]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [6]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\Q[4]_i_1__8
(.I0(\Data_array_SWR[6]_3 [21]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [4]),
.O(\Q_reg[23] [3]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\Q[5]_i_1__6
(.I0(\Data_array_SWR[6]_3 [20]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [5]),
.O(\Q_reg[23] [4]));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[5]_i_1__7
(.I0(\Data_array_SWR[6]_3 [18]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [7]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\Q[6]_i_1__9
(.I0(\Data_array_SWR[6]_3 [19]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [6]),
.O(\Q_reg[23] [5]));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\Q[7]_i_1__7
(.I0(\Data_array_SWR[6]_3 [18]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [7]),
.O(\Q_reg[23] [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[4]_1 [0]),
.Q(\Q_reg[16] [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[4]_1 [1]),
.Q(\Q_reg[16] [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[4]_1 [2]),
.Q(\Q_reg[16] [2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized11
(D,
Q,
\Q_reg[15] ,
\Q_reg[4] ,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[4]_0 ,
\Q_reg[0]_0 ,
E,
\Q_reg[1]_0 ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [5:0]D;
output [1:0]Q;
output [5:0]\Q_reg[15] ;
input [3:0]\Q_reg[4] ;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [0:0]\Q_reg[4]_0 ;
input [3:0]\Q_reg[0]_0 ;
input [0:0]E;
input [1:0]\Q_reg[1]_0 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [5:0]D;
wire [11:10]\Data_array_SWR[6]_3 ;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [3:0]\Q_reg[0]_0 ;
wire [5:0]\Q_reg[15] ;
wire [1:0]\Q_reg[1]_0 ;
wire [3:0]\Q_reg[4] ;
wire [0:0]\Q_reg[4]_0 ;
wire UNDRFLW_FLAG_FRMT;
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\Q[10]_i_1__9
(.I0(\Q_reg[4] [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [10]),
.O(\Q_reg[15] [2]));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\Q[11]_i_1__9
(.I0(\Q_reg[4] [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [11]),
.O(\Q_reg[15] [3]));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[12]_i_1__9
(.I0(\Data_array_SWR[6]_3 [11]),
.I1(Q[1]),
.I2(\Q_reg[4] [2]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\Q[12]_i_2__1
(.I0(Q[0]),
.I1(\Q_reg[4]_0 ),
.I2(\Q_reg[0]_0 [1]),
.O(\Data_array_SWR[6]_3 [11]));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[13]_i_1__7
(.I0(\Data_array_SWR[6]_3 [10]),
.I1(Q[1]),
.I2(\Q_reg[4] [3]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\Q[13]_i_2__0
(.I0(Q[0]),
.I1(\Q_reg[4]_0 ),
.I2(\Q_reg[0]_0 [0]),
.O(\Data_array_SWR[6]_3 [10]));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_1__8
(.I0(\Data_array_SWR[6]_3 [11]),
.I1(Q[1]),
.I2(\Q_reg[4] [2]),
.O(\Q_reg[15] [4]));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_1__7
(.I0(\Data_array_SWR[6]_3 [10]),
.I1(Q[1]),
.I2(\Q_reg[4] [3]),
.O(\Q_reg[15] [5]));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'h02))
\Q[6]_i_1__8
(.I0(\Q_reg[15] [0]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'h02))
\Q[7]_i_1__6
(.I0(\Q_reg[15] [1]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[1]));
LUT5 #(
.INIT(32'hB8FFB800))
\Q[8]_i_1__8
(.I0(Q[0]),
.I1(\Q_reg[4]_0 ),
.I2(\Q_reg[0]_0 [3]),
.I3(Q[1]),
.I4(\Q_reg[4] [0]),
.O(\Q_reg[15] [0]));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[8]_i_1__9
(.I0(\Q_reg[4] [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [10]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[2]));
LUT5 #(
.INIT(32'hB8FFB800))
\Q[9]_i_1__8
(.I0(Q[0]),
.I1(\Q_reg[4]_0 ),
.I2(\Q_reg[0]_0 [2]),
.I3(Q[1]),
.I4(\Q_reg[4] [1]),
.O(\Q_reg[15] [1]));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[9]_i_1__9
(.I0(\Q_reg[4] [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6]_3 [11]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[1]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[1]_0 [1]),
.Q(Q[1]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized12
(Q,
\Q_reg[4] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[4] ;
input [2:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[4] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR[0]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR[1]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR[0]),
.D(D[2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized13
(S,
\Q_reg[30] ,
\Q_reg[30]_0 ,
D,
\Q_reg[1]_0 ,
Q,
exp_rslt_NRM2_EW1,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[1]_1 ,
\Q_reg[1]_2 ,
CLK,
AR);
output [3:0]S;
output [3:0]\Q_reg[30] ;
output [6:0]\Q_reg[30]_0 ;
output [7:0]D;
output [0:0]\Q_reg[1]_0 ;
input [0:0]Q;
input [7:0]exp_rslt_NRM2_EW1;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [0:0]\Q_reg[1]_1 ;
input [12:0]\Q_reg[1]_2 ;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [7:0]D;
wire OVRFLW_FLAG_FRMT;
wire [0:0]Q;
wire [0:0]\Q_reg[1]_0 ;
wire [0:0]\Q_reg[1]_1 ;
wire [12:0]\Q_reg[1]_2 ;
wire [3:0]\Q_reg[30] ;
wire [6:0]\Q_reg[30]_0 ;
wire \Q_reg_n_0_[10] ;
wire \Q_reg_n_0_[11] ;
wire \Q_reg_n_0_[12] ;
wire \Q_reg_n_0_[7] ;
wire \Q_reg_n_0_[8] ;
wire \Q_reg_n_0_[9] ;
wire [3:0]S;
wire UNDRFLW_FLAG_FRMT;
wire [7:0]exp_rslt_NRM2_EW1;
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hFE))
\Q[23]_i_1__6
(.I0(exp_rslt_NRM2_EW1[0]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hFE))
\Q[24]_i_1__7
(.I0(exp_rslt_NRM2_EW1[1]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hFE))
\Q[25]_i_1__7
(.I0(exp_rslt_NRM2_EW1[2]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hFE))
\Q[26]_i_1__6
(.I0(exp_rslt_NRM2_EW1[3]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hFE))
\Q[27]_i_1__5
(.I0(exp_rslt_NRM2_EW1[4]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hFE))
\Q[28]_i_1__5
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hFE))
\Q[29]_i_1__6
(.I0(exp_rslt_NRM2_EW1[6]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hFE))
\Q[30]_i_1__5
(.I0(exp_rslt_NRM2_EW1[7]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [0]),
.Q(\Q_reg[30]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [10]),
.Q(\Q_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [11]),
.Q(\Q_reg_n_0_[11] ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [12]),
.Q(\Q_reg_n_0_[12] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [1]),
.Q(\Q_reg[30]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [2]),
.Q(\Q_reg[30]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [3]),
.Q(\Q_reg[30]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [4]),
.Q(\Q_reg[30]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [5]),
.Q(\Q_reg[30]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [6]),
.Q(\Q_reg[30]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [7]),
.Q(\Q_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [8]),
.Q(\Q_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[1]_1 ),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [9]),
.Q(\Q_reg_n_0_[9] ));
LUT2 #(
.INIT(4'h9))
_inferred__1_carry__0_i_1
(.I0(\Q_reg[30]_0 [6]),
.I1(\Q_reg_n_0_[7] ),
.O(\Q_reg[30] [3]));
LUT2 #(
.INIT(4'h9))
_inferred__1_carry__0_i_2
(.I0(\Q_reg[30]_0 [5]),
.I1(\Q_reg[30]_0 [6]),
.O(\Q_reg[30] [2]));
LUT2 #(
.INIT(4'h9))
_inferred__1_carry__0_i_3
(.I0(\Q_reg[30]_0 [5]),
.I1(Q),
.O(\Q_reg[30] [1]));
LUT3 #(
.INIT(8'hE1))
_inferred__1_carry__0_i_4
(.I0(Q),
.I1(\Q_reg_n_0_[12] ),
.I2(\Q_reg[30]_0 [4]),
.O(\Q_reg[30] [0]));
LUT1 #(
.INIT(2'h1))
_inferred__1_carry__1_i_1
(.I0(\Q_reg_n_0_[7] ),
.O(\Q_reg[1]_0 ));
LUT3 #(
.INIT(8'hE1))
_inferred__1_carry_i_2
(.I0(Q),
.I1(\Q_reg_n_0_[11] ),
.I2(\Q_reg[30]_0 [3]),
.O(S[3]));
LUT3 #(
.INIT(8'hE1))
_inferred__1_carry_i_3
(.I0(Q),
.I1(\Q_reg_n_0_[10] ),
.I2(\Q_reg[30]_0 [2]),
.O(S[2]));
LUT3 #(
.INIT(8'hE1))
_inferred__1_carry_i_4
(.I0(Q),
.I1(\Q_reg_n_0_[9] ),
.I2(\Q_reg[30]_0 [1]),
.O(S[1]));
LUT2 #(
.INIT(4'hE))
_inferred__1_carry_i_5
(.I0(\Q_reg_n_0_[8] ),
.I1(Q),
.O(S[0]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized14
(D,
DI,
Q,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[1]_0 ,
\Q_reg[2]_0 ,
CLK,
AR);
output [0:0]D;
output [0:0]DI;
output [1:0]Q;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [0:0]\Q_reg[1]_0 ;
input [2:0]\Q_reg[2]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [0:0]DI;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [0:0]\Q_reg[1]_0 ;
wire [2:0]\Q_reg[2]_0 ;
wire SIGN_FLAG_SHT1SHT2;
wire UNDRFLW_FLAG_FRMT;
LUT3 #(
.INIT(8'h0E))
\Q[31]_i_1__6
(.I0(UNDRFLW_FLAG_FRMT),
.I1(SIGN_FLAG_SHT1SHT2),
.I2(OVRFLW_FLAG_FRMT),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[2]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[2]_0 [1]),
.Q(SIGN_FLAG_SHT1SHT2));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[2]_0 [2]),
.Q(Q[1]));
LUT1 #(
.INIT(2'h1))
_inferred__1_carry_i_1
(.I0(Q[1]),
.O(DI));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized15
(O,
Q,
\Q_reg[8]_0 ,
\Q_reg[12]_0 ,
\Q_reg[16]_0 ,
\Q_reg[20]_0 ,
CO,
\Q_reg[24]_0 ,
S,
\Q_reg[6]_0 ,
\Q_reg[10]_0 ,
\Q_reg[14]_0 ,
\Q_reg[18]_0 ,
\Q_reg[22]_0 ,
E,
\Q_reg[30]_0 ,
CLK,
AR);
output [3:0]O;
output [30:0]Q;
output [3:0]\Q_reg[8]_0 ;
output [3:0]\Q_reg[12]_0 ;
output [3:0]\Q_reg[16]_0 ;
output [3:0]\Q_reg[20]_0 ;
output [0:0]CO;
output [3:0]\Q_reg[24]_0 ;
input [3:0]S;
input [3:0]\Q_reg[6]_0 ;
input [3:0]\Q_reg[10]_0 ;
input [3:0]\Q_reg[14]_0 ;
input [3:0]\Q_reg[18]_0 ;
input [3:0]\Q_reg[22]_0 ;
input [0:0]E;
input [30:0]\Q_reg[30]_0 ;
input CLK;
input [2:0]AR;
wire [2:0]AR;
wire CLK;
wire [0:0]CO;
wire [0:0]E;
wire [3:0]O;
wire [30:0]Q;
wire [3:0]\Q_reg[10]_0 ;
wire [3:0]\Q_reg[12]_0 ;
wire \Q_reg[12]_i_3_n_0 ;
wire \Q_reg[12]_i_3_n_1 ;
wire \Q_reg[12]_i_3_n_2 ;
wire \Q_reg[12]_i_3_n_3 ;
wire [3:0]\Q_reg[14]_0 ;
wire [3:0]\Q_reg[16]_0 ;
wire \Q_reg[16]_i_3_n_0 ;
wire \Q_reg[16]_i_3_n_1 ;
wire \Q_reg[16]_i_3_n_2 ;
wire \Q_reg[16]_i_3_n_3 ;
wire [3:0]\Q_reg[18]_0 ;
wire [3:0]\Q_reg[20]_0 ;
wire \Q_reg[20]_i_3_n_0 ;
wire \Q_reg[20]_i_3_n_1 ;
wire \Q_reg[20]_i_3_n_2 ;
wire \Q_reg[20]_i_3_n_3 ;
wire [3:0]\Q_reg[22]_0 ;
wire [3:0]\Q_reg[24]_0 ;
wire \Q_reg[24]_i_3_n_1 ;
wire \Q_reg[24]_i_3_n_2 ;
wire \Q_reg[24]_i_3_n_3 ;
wire [30:0]\Q_reg[30]_0 ;
wire \Q_reg[4]_i_3_n_0 ;
wire \Q_reg[4]_i_3_n_1 ;
wire \Q_reg[4]_i_3_n_2 ;
wire \Q_reg[4]_i_3_n_3 ;
wire [3:0]\Q_reg[6]_0 ;
wire [3:0]\Q_reg[8]_0 ;
wire \Q_reg[8]_i_3_n_0 ;
wire \Q_reg[8]_i_3_n_1 ;
wire \Q_reg[8]_i_3_n_2 ;
wire \Q_reg[8]_i_3_n_3 ;
wire [3:0]S;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [12]),
.Q(Q[12]));
CARRY4 \Q_reg[12]_i_3
(.CI(\Q_reg[8]_i_3_n_0 ),
.CO({\Q_reg[12]_i_3_n_0 ,\Q_reg[12]_i_3_n_1 ,\Q_reg[12]_i_3_n_2 ,\Q_reg[12]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[10:7]),
.O(\Q_reg[12]_0 ),
.S(\Q_reg[10]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [16]),
.Q(Q[16]));
CARRY4 \Q_reg[16]_i_3
(.CI(\Q_reg[12]_i_3_n_0 ),
.CO({\Q_reg[16]_i_3_n_0 ,\Q_reg[16]_i_3_n_1 ,\Q_reg[16]_i_3_n_2 ,\Q_reg[16]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[14:11]),
.O(\Q_reg[16]_0 ),
.S(\Q_reg[14]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [20]),
.Q(Q[20]));
CARRY4 \Q_reg[20]_i_3
(.CI(\Q_reg[16]_i_3_n_0 ),
.CO({\Q_reg[20]_i_3_n_0 ,\Q_reg[20]_i_3_n_1 ,\Q_reg[20]_i_3_n_2 ,\Q_reg[20]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[18:15]),
.O(\Q_reg[20]_0 ),
.S(\Q_reg[18]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[30]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [24]),
.Q(Q[24]));
CARRY4 \Q_reg[24]_i_3
(.CI(\Q_reg[20]_i_3_n_0 ),
.CO({CO,\Q_reg[24]_i_3_n_1 ,\Q_reg[24]_i_3_n_2 ,\Q_reg[24]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[22:19]),
.O(\Q_reg[24]_0 ),
.S(\Q_reg[22]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[30]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [4]),
.Q(Q[4]));
CARRY4 \Q_reg[4]_i_3
(.CI(1'b0),
.CO({\Q_reg[4]_i_3_n_0 ,\Q_reg[4]_i_3_n_1 ,\Q_reg[4]_i_3_n_2 ,\Q_reg[4]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({Q[2:0],1'b0}),
.O(O),
.S(S));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [8]),
.Q(Q[8]));
CARRY4 \Q_reg[8]_i_3
(.CI(\Q_reg[4]_i_3_n_0 ),
.CO({\Q_reg[8]_i_3_n_0 ,\Q_reg[8]_i_3_n_1 ,\Q_reg[8]_i_3_n_2 ,\Q_reg[8]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[6:3]),
.O(\Q_reg[8]_0 ),
.S(\Q_reg[6]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(\Q_reg[30]_0 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized16
(Q,
S,
O,
\Q_reg[8]_0 ,
\Q_reg[12]_0 ,
\Q_reg[16]_0 ,
\Q_reg[20]_0 ,
\Q_reg[24]_0 ,
\Q_reg[25]_0 ,
CO,
\Q_reg[25]_1 ,
\Q_reg[22]_0 ,
\Q_reg[22]_1 ,
E,
D,
CLK,
AR);
output [23:0]Q;
output [0:0]S;
output [3:0]O;
output [3:0]\Q_reg[8]_0 ;
output [3:0]\Q_reg[12]_0 ;
output [3:0]\Q_reg[16]_0 ;
output [3:0]\Q_reg[20]_0 ;
output [3:0]\Q_reg[24]_0 ;
output [0:0]\Q_reg[25]_0 ;
output [0:0]CO;
output [0:0]\Q_reg[25]_1 ;
input [22:0]\Q_reg[22]_0 ;
input [0:0]\Q_reg[22]_1 ;
input [0:0]E;
input [25:0]D;
input CLK;
input [3:0]AR;
wire [3:0]AR;
wire CLK;
wire [0:0]CO;
wire [25:0]D;
wire [0:0]E;
wire [3:0]O;
wire [23:0]Q;
wire \Q[12]_i_4__1_n_0 ;
wire \Q[12]_i_5__1_n_0 ;
wire \Q[12]_i_6__0_n_0 ;
wire \Q[12]_i_7__0_n_0 ;
wire \Q[16]_i_4__0_n_0 ;
wire \Q[16]_i_5_n_0 ;
wire \Q[16]_i_6_n_0 ;
wire \Q[16]_i_7_n_0 ;
wire \Q[20]_i_4__0_n_0 ;
wire \Q[20]_i_5__0_n_0 ;
wire \Q[20]_i_6_n_0 ;
wire \Q[20]_i_7_n_0 ;
wire \Q[24]_i_4_n_0 ;
wire \Q[24]_i_5_n_0 ;
wire \Q[24]_i_6_n_0 ;
wire \Q[24]_i_7_n_0 ;
wire \Q[2]_i_3_n_0 ;
wire \Q[4]_i_4_n_0 ;
wire \Q[4]_i_5_n_0 ;
wire \Q[4]_i_6_n_0 ;
wire \Q[4]_i_7_n_0 ;
wire \Q[4]_i_8_n_0 ;
wire \Q[8]_i_4__0_n_0 ;
wire \Q[8]_i_5__0_n_0 ;
wire \Q[8]_i_6__0_n_0 ;
wire \Q[8]_i_7__0_n_0 ;
wire [3:0]\Q_reg[12]_0 ;
wire \Q_reg[12]_i_2_n_0 ;
wire \Q_reg[12]_i_2_n_1 ;
wire \Q_reg[12]_i_2_n_2 ;
wire \Q_reg[12]_i_2_n_3 ;
wire [3:0]\Q_reg[16]_0 ;
wire \Q_reg[16]_i_2_n_0 ;
wire \Q_reg[16]_i_2_n_1 ;
wire \Q_reg[16]_i_2_n_2 ;
wire \Q_reg[16]_i_2_n_3 ;
wire [3:0]\Q_reg[20]_0 ;
wire \Q_reg[20]_i_2_n_0 ;
wire \Q_reg[20]_i_2_n_1 ;
wire \Q_reg[20]_i_2_n_2 ;
wire \Q_reg[20]_i_2_n_3 ;
wire [22:0]\Q_reg[22]_0 ;
wire [0:0]\Q_reg[22]_1 ;
wire [3:0]\Q_reg[24]_0 ;
wire \Q_reg[24]_i_2_n_0 ;
wire \Q_reg[24]_i_2_n_1 ;
wire \Q_reg[24]_i_2_n_2 ;
wire \Q_reg[24]_i_2_n_3 ;
wire [0:0]\Q_reg[25]_0 ;
wire [0:0]\Q_reg[25]_1 ;
wire \Q_reg[4]_i_2_n_0 ;
wire \Q_reg[4]_i_2_n_1 ;
wire \Q_reg[4]_i_2_n_2 ;
wire \Q_reg[4]_i_2_n_3 ;
wire [3:0]\Q_reg[8]_0 ;
wire \Q_reg[8]_i_2_n_0 ;
wire \Q_reg[8]_i_2_n_1 ;
wire \Q_reg[8]_i_2_n_2 ;
wire \Q_reg[8]_i_2_n_3 ;
wire \Q_reg_n_0_[1] ;
wire \Q_reg_n_0_[25] ;
wire [3:0]\NLW_Q_reg[25]_i_2_CO_UNCONNECTED ;
wire [3:1]\NLW_Q_reg[25]_i_2_O_UNCONNECTED ;
wire [3:0]\NLW_Q_reg[2]_i_2_CO_UNCONNECTED ;
wire [3:1]\NLW_Q_reg[2]_i_2_O_UNCONNECTED ;
assign S[0] = \Q_reg_n_0_[1] ;
LUT2 #(
.INIT(4'h9))
\Q[12]_i_4__1
(.I0(Q[11]),
.I1(\Q_reg[22]_0 [10]),
.O(\Q[12]_i_4__1_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_5__1
(.I0(Q[10]),
.I1(\Q_reg[22]_0 [9]),
.O(\Q[12]_i_5__1_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_6__0
(.I0(Q[9]),
.I1(\Q_reg[22]_0 [8]),
.O(\Q[12]_i_6__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_7__0
(.I0(Q[8]),
.I1(\Q_reg[22]_0 [7]),
.O(\Q[12]_i_7__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_4__0
(.I0(Q[15]),
.I1(\Q_reg[22]_0 [14]),
.O(\Q[16]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_5
(.I0(Q[14]),
.I1(\Q_reg[22]_0 [13]),
.O(\Q[16]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_6
(.I0(Q[13]),
.I1(\Q_reg[22]_0 [12]),
.O(\Q[16]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_7
(.I0(Q[12]),
.I1(\Q_reg[22]_0 [11]),
.O(\Q[16]_i_7_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_4__0
(.I0(Q[19]),
.I1(\Q_reg[22]_0 [18]),
.O(\Q[20]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_5__0
(.I0(Q[18]),
.I1(\Q_reg[22]_0 [17]),
.O(\Q[20]_i_5__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_6
(.I0(Q[17]),
.I1(\Q_reg[22]_0 [16]),
.O(\Q[20]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_7
(.I0(Q[16]),
.I1(\Q_reg[22]_0 [15]),
.O(\Q[20]_i_7_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_4
(.I0(Q[23]),
.I1(\Q_reg[22]_0 [22]),
.O(\Q[24]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_5
(.I0(Q[22]),
.I1(\Q_reg[22]_0 [21]),
.O(\Q[24]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_6
(.I0(Q[21]),
.I1(\Q_reg[22]_0 [20]),
.O(\Q[24]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_7
(.I0(Q[20]),
.I1(\Q_reg[22]_0 [19]),
.O(\Q[24]_i_7_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[2]_i_3
(.I0(\Q_reg_n_0_[25] ),
.O(\Q[2]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[4]_i_4
(.I0(Q[0]),
.O(\Q[4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_5
(.I0(Q[3]),
.I1(\Q_reg[22]_0 [2]),
.O(\Q[4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_6
(.I0(Q[2]),
.I1(\Q_reg[22]_0 [1]),
.O(\Q[4]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_7
(.I0(Q[1]),
.I1(\Q_reg[22]_0 [0]),
.O(\Q[4]_i_7_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[4]_i_8
(.I0(\Q_reg_n_0_[1] ),
.O(\Q[4]_i_8_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_4__0
(.I0(Q[7]),
.I1(\Q_reg[22]_0 [6]),
.O(\Q[8]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_5__0
(.I0(Q[6]),
.I1(\Q_reg[22]_0 [5]),
.O(\Q[8]_i_5__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_6__0
(.I0(Q[5]),
.I1(\Q_reg[22]_0 [4]),
.O(\Q[8]_i_6__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_7__0
(.I0(Q[4]),
.I1(\Q_reg[22]_0 [3]),
.O(\Q[8]_i_7__0_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[10]),
.Q(Q[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[11]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[12]),
.Q(Q[11]));
CARRY4 \Q_reg[12]_i_2
(.CI(\Q_reg[8]_i_2_n_0 ),
.CO({\Q_reg[12]_i_2_n_0 ,\Q_reg[12]_i_2_n_1 ,\Q_reg[12]_i_2_n_2 ,\Q_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [10:7]),
.O(\Q_reg[12]_0 ),
.S({\Q[12]_i_4__1_n_0 ,\Q[12]_i_5__1_n_0 ,\Q[12]_i_6__0_n_0 ,\Q[12]_i_7__0_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[13]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[14]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[15]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[16]),
.Q(Q[15]));
CARRY4 \Q_reg[16]_i_2
(.CI(\Q_reg[12]_i_2_n_0 ),
.CO({\Q_reg[16]_i_2_n_0 ,\Q_reg[16]_i_2_n_1 ,\Q_reg[16]_i_2_n_2 ,\Q_reg[16]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [14:11]),
.O(\Q_reg[16]_0 ),
.S({\Q[16]_i_4__0_n_0 ,\Q[16]_i_5_n_0 ,\Q[16]_i_6_n_0 ,\Q[16]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[17]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[18]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[19]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(D[1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[20]),
.Q(Q[19]));
CARRY4 \Q_reg[20]_i_2
(.CI(\Q_reg[16]_i_2_n_0 ),
.CO({\Q_reg[20]_i_2_n_0 ,\Q_reg[20]_i_2_n_1 ,\Q_reg[20]_i_2_n_2 ,\Q_reg[20]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [18:15]),
.O(\Q_reg[20]_0 ),
.S({\Q[20]_i_4__0_n_0 ,\Q[20]_i_5__0_n_0 ,\Q[20]_i_6_n_0 ,\Q[20]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(D[21]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(D[22]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(D[23]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR[2]),
.D(D[24]),
.Q(Q[23]));
CARRY4 \Q_reg[24]_i_2
(.CI(\Q_reg[20]_i_2_n_0 ),
.CO({\Q_reg[24]_i_2_n_0 ,\Q_reg[24]_i_2_n_1 ,\Q_reg[24]_i_2_n_2 ,\Q_reg[24]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [22:19]),
.O(\Q_reg[24]_0 ),
.S({\Q[24]_i_4_n_0 ,\Q[24]_i_5_n_0 ,\Q[24]_i_6_n_0 ,\Q[24]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[25]),
.Q(\Q_reg_n_0_[25] ));
CARRY4 \Q_reg[25]_i_2
(.CI(\Q_reg[24]_i_2_n_0 ),
.CO(\NLW_Q_reg[25]_i_2_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_Q_reg[25]_i_2_O_UNCONNECTED [3:1],\Q_reg[25]_0 }),
.S({1'b0,1'b0,1'b0,\Q_reg_n_0_[25] }));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[2]),
.Q(Q[1]));
CARRY4 \Q_reg[2]_i_2
(.CI(\Q_reg[22]_1 ),
.CO({\NLW_Q_reg[2]_i_2_CO_UNCONNECTED [3:2],CO,\NLW_Q_reg[2]_i_2_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\Q_reg_n_0_[25] }),
.O({\NLW_Q_reg[2]_i_2_O_UNCONNECTED [3:1],\Q_reg[25]_1 }),
.S({1'b0,1'b0,1'b1,\Q[2]_i_3_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[3]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[4]),
.Q(Q[3]));
CARRY4 \Q_reg[4]_i_2
(.CI(1'b0),
.CO({\Q_reg[4]_i_2_n_0 ,\Q_reg[4]_i_2_n_1 ,\Q_reg[4]_i_2_n_2 ,\Q_reg[4]_i_2_n_3 }),
.CYINIT(\Q[4]_i_4_n_0 ),
.DI({\Q_reg[22]_0 [2:0],1'b0}),
.O(O),
.S({\Q[4]_i_5_n_0 ,\Q[4]_i_6_n_0 ,\Q[4]_i_7_n_0 ,\Q[4]_i_8_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[5]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[6]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[7]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[8]),
.Q(Q[7]));
CARRY4 \Q_reg[8]_i_2
(.CI(\Q_reg[4]_i_2_n_0 ),
.CO({\Q_reg[8]_i_2_n_0 ,\Q_reg[8]_i_2_n_1 ,\Q_reg[8]_i_2_n_2 ,\Q_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[22]_0 [6:3]),
.O(\Q_reg[8]_0 ),
.S({\Q[8]_i_4__0_n_0 ,\Q[8]_i_5__0_n_0 ,\Q[8]_i_6__0_n_0 ,\Q[8]_i_7__0_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR[3]),
.D(D[9]),
.Q(Q[8]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized17
(\Q_reg[2]_0 ,
Q,
CO,
E,
\Q_reg[2]_1 ,
CLK,
AR);
output [2:0]\Q_reg[2]_0 ;
output [0:0]Q;
input [0:0]CO;
input [0:0]E;
input [2:0]\Q_reg[2]_1 ;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [0:0]CO;
wire [0:0]E;
wire [0:0]Q;
wire [2:0]\Q_reg[2]_0 ;
wire [2:0]\Q_reg[2]_1 ;
LUT2 #(
.INIT(4'h2))
\Q[2]_i_1__11
(.I0(CO),
.I1(Q),
.O(\Q_reg[2]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[2]_1 [0]),
.Q(\Q_reg[2]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR[1]),
.D(\Q_reg[2]_1 [1]),
.Q(Q));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR[0]),
.D(\Q_reg[2]_1 [2]),
.Q(\Q_reg[2]_0 [1]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized18
(D,
\Q_reg[12]_0 ,
\Q_reg[12]_1 ,
\Q_reg[1]_0 ,
\Q_reg[1]_1 ,
\Q_reg[2]_0 ,
Q,
\Q_reg[2]_1 ,
\Q_reg[22]_0 ,
\Q_reg[1]_2 ,
CLK,
AR);
output [24:0]D;
output [4:0]\Q_reg[12]_0 ;
output [0:0]\Q_reg[12]_1 ;
input [0:0]\Q_reg[1]_0 ;
input \Q_reg[1]_1 ;
input \Q_reg[2]_0 ;
input [1:0]Q;
input [0:0]\Q_reg[2]_1 ;
input [22:0]\Q_reg[22]_0 ;
input [25:0]\Q_reg[1]_2 ;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [24:0]D;
wire [1:0]Q;
wire \Q[0]_i_2_n_0 ;
wire \Q[10]_i_2__0_n_0 ;
wire \Q[10]_i_2_n_0 ;
wire \Q[10]_i_3_n_0 ;
wire \Q[10]_i_4_n_0 ;
wire \Q[11]_i_2_n_0 ;
wire \Q[12]_i_2__0_n_0 ;
wire \Q[12]_i_2_n_0 ;
wire \Q[12]_i_3_n_0 ;
wire \Q[12]_i_4_n_0 ;
wire \Q[12]_i_5_n_0 ;
wire \Q[12]_i_6_n_0 ;
wire \Q[12]_i_7_n_0 ;
wire \Q[13]_i_2_n_0 ;
wire \Q[14]_i_2__0_n_0 ;
wire \Q[15]_i_2_n_0 ;
wire \Q[16]_i_2_n_0 ;
wire \Q[17]_i_2_n_0 ;
wire \Q[18]_i_2_n_0 ;
wire \Q[19]_i_2_n_0 ;
wire \Q[1]_i_2__0_n_0 ;
wire \Q[20]_i_2_n_0 ;
wire \Q[21]_i_2_n_0 ;
wire \Q[22]_i_2_n_0 ;
wire \Q[23]_i_2_n_0 ;
wire \Q[24]_i_2_n_0 ;
wire \Q[24]_i_3_n_0 ;
wire \Q[2]_i_2_n_0 ;
wire \Q[3]_i_2_n_0 ;
wire \Q[4]_i_2_n_0 ;
wire \Q[5]_i_2_n_0 ;
wire \Q[6]_i_2__0_n_0 ;
wire \Q[7]_i_2_n_0 ;
wire \Q[8]_i_2__0_n_0 ;
wire \Q[8]_i_2_n_0 ;
wire \Q[8]_i_3_n_0 ;
wire \Q[8]_i_4_n_0 ;
wire \Q[8]_i_5_n_0 ;
wire \Q[8]_i_6_n_0 ;
wire \Q[8]_i_7_n_0 ;
wire \Q[8]_i_8_n_0 ;
wire \Q[8]_i_9_n_0 ;
wire \Q[9]_i_10_n_0 ;
wire \Q[9]_i_11_n_0 ;
wire \Q[9]_i_2__0_n_0 ;
wire \Q[9]_i_2_n_0 ;
wire \Q[9]_i_3_n_0 ;
wire \Q[9]_i_4_n_0 ;
wire \Q[9]_i_5_n_0 ;
wire \Q[9]_i_6_n_0 ;
wire \Q[9]_i_7_n_0 ;
wire \Q[9]_i_8_n_0 ;
wire \Q[9]_i_9_n_0 ;
wire [4:0]\Q_reg[12]_0 ;
wire [0:0]\Q_reg[12]_1 ;
wire [0:0]\Q_reg[1]_0 ;
wire \Q_reg[1]_1 ;
wire [25:0]\Q_reg[1]_2 ;
wire [22:0]\Q_reg[22]_0 ;
wire \Q_reg[2]_0 ;
wire [0:0]\Q_reg[2]_1 ;
wire \Q_reg_n_0_[10] ;
wire \Q_reg_n_0_[11] ;
wire \Q_reg_n_0_[12] ;
wire \Q_reg_n_0_[13] ;
wire \Q_reg_n_0_[14] ;
wire \Q_reg_n_0_[15] ;
wire \Q_reg_n_0_[16] ;
wire \Q_reg_n_0_[17] ;
wire \Q_reg_n_0_[18] ;
wire \Q_reg_n_0_[19] ;
wire \Q_reg_n_0_[1] ;
wire \Q_reg_n_0_[20] ;
wire \Q_reg_n_0_[21] ;
wire \Q_reg_n_0_[22] ;
wire \Q_reg_n_0_[23] ;
wire \Q_reg_n_0_[24] ;
wire \Q_reg_n_0_[25] ;
wire \Q_reg_n_0_[2] ;
wire \Q_reg_n_0_[3] ;
wire \Q_reg_n_0_[4] ;
wire \Q_reg_n_0_[5] ;
wire \Q_reg_n_0_[6] ;
wire \Q_reg_n_0_[7] ;
wire \Q_reg_n_0_[8] ;
wire \Q_reg_n_0_[9] ;
LUT6 #(
.INIT(64'hFFFFFFC0FFA0FFC0))
\Q[0]_i_1__8
(.I0(\Q[3]_i_2_n_0 ),
.I1(\Q[2]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[0]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[1]_i_2__0_n_0 ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'h20))
\Q[0]_i_2
(.I0(\Q_reg_n_0_[25] ),
.I1(\Q_reg[2]_1 ),
.I2(Q[0]),
.O(\Q[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[10]_i_1__6
(.I0(\Q[13]_i_2_n_0 ),
.I1(\Q[12]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[11]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[10]_i_2__0_n_0 ),
.O(D[10]));
LUT6 #(
.INIT(64'h0001000000010001))
\Q[10]_i_1__7
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg_n_0_[23] ),
.I2(\Q_reg_n_0_[24] ),
.I3(\Q_reg_n_0_[25] ),
.I4(\Q[10]_i_2_n_0 ),
.I5(\Q[10]_i_3_n_0 ),
.O(\Q_reg[12]_0 [2]));
LUT6 #(
.INIT(64'h00808888AAAAAAAA))
\Q[10]_i_2
(.I0(\Q[12]_i_6_n_0 ),
.I1(\Q[12]_i_3_n_0 ),
.I2(\Q_reg[12]_1 ),
.I3(\Q_reg_n_0_[1] ),
.I4(\Q[12]_i_2_n_0 ),
.I5(\Q[10]_i_4_n_0 ),
.O(\Q[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[10]_i_2__0
(.I0(\Q_reg_n_0_[15] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[10] ),
.I4(\Q_reg[22]_0 [8]),
.O(\Q[10]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT4 #(
.INIT(16'h0001))
\Q[10]_i_3
(.I0(\Q_reg_n_0_[21] ),
.I1(\Q_reg_n_0_[20] ),
.I2(\Q_reg_n_0_[19] ),
.I3(\Q_reg_n_0_[18] ),
.O(\Q[10]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT4 #(
.INIT(16'h0001))
\Q[10]_i_4
(.I0(\Q_reg_n_0_[11] ),
.I1(\Q_reg_n_0_[10] ),
.I2(\Q_reg_n_0_[13] ),
.I3(\Q_reg_n_0_[12] ),
.O(\Q[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[11]_i_1__6
(.I0(\Q[14]_i_2__0_n_0 ),
.I1(\Q[13]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[12]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[11]_i_2_n_0 ),
.O(D[11]));
LUT5 #(
.INIT(32'h8000AAAA))
\Q[11]_i_1__7
(.I0(\Q[12]_i_5_n_0 ),
.I1(\Q[12]_i_3_n_0 ),
.I2(\Q[12]_i_2_n_0 ),
.I3(\Q_reg_n_0_[1] ),
.I4(\Q[12]_i_4_n_0 ),
.O(\Q_reg[12]_0 [3]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[11]_i_2
(.I0(\Q_reg_n_0_[14] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q_reg[22]_0 [9]),
.O(\Q[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[12]_i_1__6
(.I0(\Q[15]_i_2_n_0 ),
.I1(\Q[14]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[13]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[12]_i_2__0_n_0 ),
.O(D[12]));
LUT6 #(
.INIT(64'hFDFF000000000000))
\Q[12]_i_1__7
(.I0(\Q[12]_i_2_n_0 ),
.I1(\Q_reg_n_0_[1] ),
.I2(\Q_reg[12]_1 ),
.I3(\Q[12]_i_3_n_0 ),
.I4(\Q[12]_i_4_n_0 ),
.I5(\Q[12]_i_5_n_0 ),
.O(\Q_reg[12]_0 [4]));
LUT4 #(
.INIT(16'h0001))
\Q[12]_i_2
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg_n_0_[2] ),
.I2(\Q_reg_n_0_[5] ),
.I3(\Q_reg_n_0_[4] ),
.O(\Q[12]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT5 #(
.INIT(32'hFB3BC808))
\Q[12]_i_2__0
(.I0(\Q_reg_n_0_[13] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[12] ),
.I4(\Q_reg[22]_0 [10]),
.O(\Q[12]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT4 #(
.INIT(16'h0001))
\Q[12]_i_3
(.I0(\Q_reg_n_0_[9] ),
.I1(\Q_reg_n_0_[8] ),
.I2(\Q_reg_n_0_[6] ),
.I3(\Q_reg_n_0_[7] ),
.O(\Q[12]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT5 #(
.INIT(32'h00010000))
\Q[12]_i_4
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[13] ),
.I2(\Q_reg_n_0_[10] ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q[12]_i_6_n_0 ),
.O(\Q[12]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT5 #(
.INIT(32'h00010000))
\Q[12]_i_5
(.I0(\Q_reg_n_0_[18] ),
.I1(\Q_reg_n_0_[19] ),
.I2(\Q_reg_n_0_[20] ),
.I3(\Q_reg_n_0_[21] ),
.I4(\Q[12]_i_7_n_0 ),
.O(\Q[12]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT4 #(
.INIT(16'h0001))
\Q[12]_i_6
(.I0(\Q_reg_n_0_[17] ),
.I1(\Q_reg_n_0_[16] ),
.I2(\Q_reg_n_0_[15] ),
.I3(\Q_reg_n_0_[14] ),
.O(\Q[12]_i_6_n_0 ));
LUT4 #(
.INIT(16'h0001))
\Q[12]_i_7
(.I0(\Q_reg_n_0_[25] ),
.I1(\Q_reg_n_0_[24] ),
.I2(\Q_reg_n_0_[23] ),
.I3(\Q_reg_n_0_[22] ),
.O(\Q[12]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_1__5
(.I0(\Q[16]_i_2_n_0 ),
.I1(\Q[15]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[14]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[13]_i_2_n_0 ),
.O(D[13]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[13]_i_2
(.I0(\Q_reg_n_0_[12] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[13] ),
.I4(\Q_reg[22]_0 [11]),
.O(\Q[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[14]_i_1__6
(.I0(\Q[17]_i_2_n_0 ),
.I1(\Q[16]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[15]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[14]_i_2__0_n_0 ),
.O(D[14]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[14]_i_2__0
(.I0(\Q_reg_n_0_[11] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[14] ),
.I4(\Q_reg[22]_0 [12]),
.O(\Q[14]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[15]_i_1__5
(.I0(\Q[18]_i_2_n_0 ),
.I1(\Q[17]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[16]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[15]_i_2_n_0 ),
.O(D[15]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[15]_i_2
(.I0(\Q_reg_n_0_[10] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[15] ),
.I4(\Q_reg[22]_0 [13]),
.O(\Q[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_1__5
(.I0(\Q[19]_i_2_n_0 ),
.I1(\Q[18]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[17]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[16]_i_2_n_0 ),
.O(D[16]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[16]_i_2
(.I0(\Q_reg_n_0_[9] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[16] ),
.I4(\Q_reg[22]_0 [14]),
.O(\Q[16]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_1__5
(.I0(\Q[20]_i_2_n_0 ),
.I1(\Q[19]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[18]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[17]_i_2_n_0 ),
.O(D[17]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[17]_i_2
(.I0(\Q_reg_n_0_[8] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[17] ),
.I4(\Q_reg[22]_0 [15]),
.O(\Q[17]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_1__5
(.I0(\Q[21]_i_2_n_0 ),
.I1(\Q[20]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[19]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[18]_i_2_n_0 ),
.O(D[18]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[18]_i_2
(.I0(\Q_reg_n_0_[7] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[18] ),
.I4(\Q_reg[22]_0 [16]),
.O(\Q[18]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_1__5
(.I0(\Q[22]_i_2_n_0 ),
.I1(\Q[21]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[20]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[19]_i_2_n_0 ),
.O(D[19]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[19]_i_2
(.I0(\Q_reg_n_0_[6] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[19] ),
.I4(\Q_reg[22]_0 [17]),
.O(\Q[19]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[1]_i_1__6
(.I0(\Q[4]_i_2_n_0 ),
.I1(\Q[3]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[2]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[1]_i_2__0_n_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT4 #(
.INIT(16'h8C80))
\Q[1]_i_2__0
(.I0(\Q_reg_n_0_[1] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[24] ),
.O(\Q[1]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_1__5
(.I0(\Q[23]_i_2_n_0 ),
.I1(\Q[22]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[21]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[20]_i_2_n_0 ),
.O(D[20]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[20]_i_2
(.I0(\Q_reg_n_0_[5] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[20] ),
.I4(\Q_reg[22]_0 [18]),
.O(\Q[20]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_1__6
(.I0(\Q[24]_i_2_n_0 ),
.I1(\Q[23]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[22]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[21]_i_2_n_0 ),
.O(D[21]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[21]_i_2
(.I0(\Q_reg_n_0_[4] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[21] ),
.I4(\Q_reg[22]_0 [19]),
.O(\Q[21]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[22]_i_1__6
(.I0(\Q[24]_i_3_n_0 ),
.I1(\Q[24]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[23]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[22]_i_2_n_0 ),
.O(D[22]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[22]_i_2
(.I0(\Q_reg_n_0_[3] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[22] ),
.I4(\Q_reg[22]_0 [20]),
.O(\Q[22]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0EFEFAFA0E0E0))
\Q[23]_i_1__5
(.I0(\Q_reg[1]_0 ),
.I1(\Q[24]_i_3_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[24]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[23]_i_2_n_0 ),
.O(D[23]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[23]_i_2
(.I0(\Q_reg_n_0_[2] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[23] ),
.I4(\Q_reg[22]_0 [21]),
.O(\Q[23]_i_2_n_0 ));
LUT4 #(
.INIT(16'h00E2))
\Q[24]_i_1__6
(.I0(\Q[24]_i_2_n_0 ),
.I1(\Q_reg[2]_0 ),
.I2(\Q[24]_i_3_n_0 ),
.I3(\Q_reg[1]_1 ),
.O(D[24]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT5 #(
.INIT(32'hFB3BC808))
\Q[24]_i_2
(.I0(\Q_reg_n_0_[1] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[24] ),
.I4(\Q_reg[22]_0 [22]),
.O(\Q[24]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT4 #(
.INIT(16'hFB3B))
\Q[24]_i_3
(.I0(\Q_reg[12]_1 ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[25] ),
.O(\Q[24]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[2]_i_1__5
(.I0(\Q[5]_i_2_n_0 ),
.I1(\Q[4]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[3]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[2]_i_2_n_0 ),
.O(D[2]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[2]_i_2
(.I0(\Q_reg_n_0_[23] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[2] ),
.I4(\Q_reg[22]_0 [0]),
.O(\Q[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[3]_i_1__5
(.I0(\Q[6]_i_2__0_n_0 ),
.I1(\Q[5]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[4]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[3]_i_2_n_0 ),
.O(D[3]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[3]_i_2
(.I0(\Q_reg_n_0_[22] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[3] ),
.I4(\Q_reg[22]_0 [1]),
.O(\Q[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[4]_i_1__6
(.I0(\Q[7]_i_2_n_0 ),
.I1(\Q[6]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[5]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[4]_i_2_n_0 ),
.O(D[4]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[4]_i_2
(.I0(\Q_reg_n_0_[21] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[4] ),
.I4(\Q_reg[22]_0 [2]),
.O(\Q[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[5]_i_1__5
(.I0(\Q[8]_i_2__0_n_0 ),
.I1(\Q[7]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[6]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[5]_i_2_n_0 ),
.O(D[5]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[5]_i_2
(.I0(\Q_reg_n_0_[20] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[5] ),
.I4(\Q_reg[22]_0 [3]),
.O(\Q[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[6]_i_1__7
(.I0(\Q[9]_i_2__0_n_0 ),
.I1(\Q[8]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[7]_i_2_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[6]_i_2__0_n_0 ),
.O(D[6]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[6]_i_2__0
(.I0(\Q_reg_n_0_[19] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[6] ),
.I4(\Q_reg[22]_0 [4]),
.O(\Q[6]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[7]_i_1__5
(.I0(\Q[10]_i_2__0_n_0 ),
.I1(\Q[9]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[8]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[7]_i_2_n_0 ),
.O(D[7]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[7]_i_2
(.I0(\Q_reg_n_0_[18] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[7] ),
.I4(\Q_reg[22]_0 [5]),
.O(\Q[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[8]_i_1__6
(.I0(\Q[11]_i_2_n_0 ),
.I1(\Q[10]_i_2__0_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[9]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[8]_i_2__0_n_0 ),
.O(D[8]));
LUT6 #(
.INIT(64'h00000000FFFF00AE))
\Q[8]_i_1__7
(.I0(\Q[8]_i_2_n_0 ),
.I1(\Q[8]_i_3_n_0 ),
.I2(\Q[8]_i_4_n_0 ),
.I3(\Q[8]_i_5_n_0 ),
.I4(\Q_reg_n_0_[24] ),
.I5(\Q_reg_n_0_[25] ),
.O(\Q_reg[12]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[8]_i_2
(.I0(\Q[8]_i_6_n_0 ),
.I1(\Q_reg_n_0_[22] ),
.I2(\Q_reg_n_0_[20] ),
.I3(\Q_reg_n_0_[18] ),
.O(\Q[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[8]_i_2__0
(.I0(\Q_reg_n_0_[17] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[8] ),
.I4(\Q_reg[22]_0 [6]),
.O(\Q[8]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF55045555))
\Q[8]_i_3
(.I0(\Q_reg_n_0_[7] ),
.I1(\Q_reg_n_0_[4] ),
.I2(\Q_reg_n_0_[5] ),
.I3(\Q_reg_n_0_[6] ),
.I4(\Q[8]_i_7_n_0 ),
.I5(\Q[8]_i_8_n_0 ),
.O(\Q[8]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT4 #(
.INIT(16'hFEFF))
\Q[8]_i_4
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg_n_0_[17] ),
.I2(\Q_reg_n_0_[13] ),
.I3(\Q[8]_i_9_n_0 ),
.O(\Q[8]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT5 #(
.INIT(32'hBABBBABA))
\Q[8]_i_5
(.I0(\Q_reg_n_0_[23] ),
.I1(\Q_reg_n_0_[22] ),
.I2(\Q_reg_n_0_[21] ),
.I3(\Q_reg_n_0_[20] ),
.I4(\Q_reg_n_0_[19] ),
.O(\Q[8]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT4 #(
.INIT(16'h00F2))
\Q[8]_i_6
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg_n_0_[15] ),
.I2(\Q_reg_n_0_[16] ),
.I3(\Q_reg_n_0_[17] ),
.O(\Q[8]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFFFFBABB))
\Q[8]_i_7
(.I0(\Q_reg_n_0_[5] ),
.I1(\Q_reg_n_0_[2] ),
.I2(\Q_reg_n_0_[1] ),
.I3(\Q_reg[12]_1 ),
.I4(\Q_reg_n_0_[3] ),
.O(\Q[8]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT4 #(
.INIT(16'hEFEE))
\Q[8]_i_8
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[8] ),
.I2(\Q_reg_n_0_[11] ),
.I3(\Q_reg_n_0_[10] ),
.O(\Q[8]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT4 #(
.INIT(16'hFF0B))
\Q[8]_i_9
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg_n_0_[9] ),
.I2(\Q_reg_n_0_[11] ),
.I3(\Q_reg_n_0_[12] ),
.O(\Q[8]_i_9_n_0 ));
LUT2 #(
.INIT(4'h1))
\Q[9]_i_10
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg_n_0_[11] ),
.O(\Q[9]_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT2 #(
.INIT(4'h1))
\Q[9]_i_11
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg_n_0_[15] ),
.O(\Q[9]_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[9]_i_1__6
(.I0(\Q[12]_i_2__0_n_0 ),
.I1(\Q[11]_i_2_n_0 ),
.I2(\Q_reg[1]_1 ),
.I3(\Q[10]_i_2__0_n_0 ),
.I4(\Q_reg[2]_0 ),
.I5(\Q[9]_i_2__0_n_0 ),
.O(D[9]));
LUT6 #(
.INIT(64'h1111111110001010))
\Q[9]_i_1__7
(.I0(\Q_reg_n_0_[25] ),
.I1(\Q_reg_n_0_[24] ),
.I2(\Q[9]_i_2_n_0 ),
.I3(\Q[9]_i_3_n_0 ),
.I4(\Q[9]_i_4_n_0 ),
.I5(\Q[9]_i_5_n_0 ),
.O(\Q_reg[12]_0 [1]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT2 #(
.INIT(4'h1))
\Q[9]_i_2
(.I0(\Q_reg_n_0_[20] ),
.I1(\Q_reg_n_0_[21] ),
.O(\Q[9]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[9]_i_2__0
(.I0(\Q_reg_n_0_[16] ),
.I1(Q[0]),
.I2(\Q_reg[2]_1 ),
.I3(\Q_reg_n_0_[9] ),
.I4(\Q_reg[22]_0 [7]),
.O(\Q[9]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h00808888AAAAAAAA))
\Q[9]_i_3
(.I0(\Q[9]_i_6_n_0 ),
.I1(\Q[9]_i_7_n_0 ),
.I2(\Q[9]_i_8_n_0 ),
.I3(\Q[9]_i_9_n_0 ),
.I4(\Q[9]_i_10_n_0 ),
.I5(\Q[9]_i_11_n_0 ),
.O(\Q[9]_i_3_n_0 ));
LUT2 #(
.INIT(4'h1))
\Q[9]_i_4
(.I0(\Q_reg_n_0_[18] ),
.I1(\Q_reg_n_0_[19] ),
.O(\Q[9]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT2 #(
.INIT(4'hE))
\Q[9]_i_5
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg_n_0_[23] ),
.O(\Q[9]_i_5_n_0 ));
LUT2 #(
.INIT(4'h1))
\Q[9]_i_6
(.I0(\Q_reg_n_0_[16] ),
.I1(\Q_reg_n_0_[17] ),
.O(\Q[9]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT2 #(
.INIT(4'h1))
\Q[9]_i_7
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[13] ),
.O(\Q[9]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT2 #(
.INIT(4'h1))
\Q[9]_i_8
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg_n_0_[9] ),
.O(\Q[9]_i_8_n_0 ));
LUT6 #(
.INIT(64'h1110111011101111))
\Q[9]_i_9
(.I0(\Q_reg_n_0_[6] ),
.I1(\Q_reg_n_0_[7] ),
.I2(\Q_reg_n_0_[4] ),
.I3(\Q_reg_n_0_[5] ),
.I4(\Q_reg_n_0_[2] ),
.I5(\Q_reg_n_0_[3] ),
.O(\Q[9]_i_9_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [0]),
.Q(\Q_reg[12]_1 ));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [10]),
.Q(\Q_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [11]),
.Q(\Q_reg_n_0_[11] ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [12]),
.Q(\Q_reg_n_0_[12] ));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [13]),
.Q(\Q_reg_n_0_[13] ));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [14]),
.Q(\Q_reg_n_0_[14] ));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [15]),
.Q(\Q_reg_n_0_[15] ));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [16]),
.Q(\Q_reg_n_0_[16] ));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [17]),
.Q(\Q_reg_n_0_[17] ));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [18]),
.Q(\Q_reg_n_0_[18] ));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [19]),
.Q(\Q_reg_n_0_[19] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [20]),
.Q(\Q_reg_n_0_[20] ));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [21]),
.Q(\Q_reg_n_0_[21] ));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [22]),
.Q(\Q_reg_n_0_[22] ));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [23]),
.Q(\Q_reg_n_0_[23] ));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [24]),
.Q(\Q_reg_n_0_[24] ));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[0]),
.D(\Q_reg[1]_2 [25]),
.Q(\Q_reg_n_0_[25] ));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [2]),
.Q(\Q_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [3]),
.Q(\Q_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [4]),
.Q(\Q_reg_n_0_[4] ));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [5]),
.Q(\Q_reg_n_0_[5] ));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [6]),
.Q(\Q_reg_n_0_[6] ));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [7]),
.Q(\Q_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [8]),
.Q(\Q_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(Q[1]),
.CLR(AR[1]),
.D(\Q_reg[1]_2 [9]),
.Q(\Q_reg_n_0_[9] ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized19
(Q,
\Q_reg[2]_0 ,
\Q_reg[30] ,
CLK,
AR);
output [7:0]Q;
input [0:0]\Q_reg[2]_0 ;
input [7:0]\Q_reg[30] ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [7:0]Q;
wire [0:0]\Q_reg[2]_0 ;
wire [7:0]\Q_reg[30] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [7]),
.Q(Q[7]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized2
(D,
Q,
\Q_reg[27]_0 ,
\Q_reg[6]_0 ,
\Q_reg[27]_1 ,
CLK,
AR);
output [2:0]D;
output [25:0]Q;
input [4:0]\Q_reg[27]_0 ;
input [0:0]\Q_reg[6]_0 ;
input [27:0]\Q_reg[27]_1 ;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [2:0]D;
wire [25:0]Q;
wire \Q[4]_i_2__0_n_0 ;
wire [4:0]\Q_reg[27]_0 ;
wire [27:0]\Q_reg[27]_1 ;
wire [0:0]\Q_reg[6]_0 ;
wire \Q_reg_n_0_[26] ;
wire \Q_reg_n_0_[27] ;
LUT4 #(
.INIT(16'h2DD2))
\Q[1]_i_1__11
(.I0(Q[23]),
.I1(\Q_reg[27]_0 [0]),
.I2(Q[24]),
.I3(\Q_reg[27]_0 [1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'h69))
\Q[3]_i_1__8
(.I0(\Q[4]_i_2__0_n_0 ),
.I1(\Q_reg_n_0_[26] ),
.I2(\Q_reg[27]_0 [3]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT5 #(
.INIT(32'h718E8E71))
\Q[4]_i_1__9
(.I0(\Q[4]_i_2__0_n_0 ),
.I1(\Q_reg[27]_0 [3]),
.I2(\Q_reg_n_0_[26] ),
.I3(\Q_reg_n_0_[27] ),
.I4(\Q_reg[27]_0 [4]),
.O(D[2]));
LUT6 #(
.INIT(64'hD4DD4444DDDDD4DD))
\Q[4]_i_2__0
(.I0(Q[25]),
.I1(\Q_reg[27]_0 [2]),
.I2(\Q_reg[27]_0 [0]),
.I3(Q[23]),
.I4(\Q_reg[27]_0 [1]),
.I5(Q[24]),
.O(\Q[4]_i_2__0_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [26]),
.Q(\Q_reg_n_0_[26] ));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [27]),
.Q(\Q_reg_n_0_[27] ));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[1]),
.D(\Q_reg[27]_1 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR[0]),
.D(\Q_reg[27]_1 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized20
(D,
Q,
\Q_reg[25] ,
\Q_reg[25]_0 ,
\Q_reg[22] ,
\Q_reg[2]_0 ,
\Q_reg[2]_1 ,
\Q_reg[0]_0 ,
\Q_reg[1]_0 ,
\Q_reg[1]_1 ,
CLK,
AR);
output [0:0]D;
output [2:0]Q;
output \Q_reg[25] ;
output [0:0]\Q_reg[25]_0 ;
input [1:0]\Q_reg[22] ;
input [1:0]\Q_reg[2]_0 ;
input [1:0]\Q_reg[2]_1 ;
input [0:0]\Q_reg[0]_0 ;
input \Q_reg[1]_0 ;
input [2:0]\Q_reg[1]_1 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[0]_0 ;
wire \Q_reg[1]_0 ;
wire [2:0]\Q_reg[1]_1 ;
wire [1:0]\Q_reg[22] ;
wire \Q_reg[25] ;
wire [0:0]\Q_reg[25]_0 ;
wire [1:0]\Q_reg[2]_0 ;
wire [1:0]\Q_reg[2]_1 ;
LUT5 #(
.INIT(32'h000088FB))
\Q[25]_i_2
(.I0(Q[2]),
.I1(\Q_reg[2]_0 [0]),
.I2(\Q_reg[0]_0 ),
.I3(\Q_reg[25] ),
.I4(\Q_reg[1]_0 ),
.O(\Q_reg[25]_0 ));
LUT4 #(
.INIT(16'hEEF0))
\Q[25]_i_3
(.I0(Q[2]),
.I1(\Q_reg[22] [0]),
.I2(\Q_reg[2]_1 [0]),
.I3(\Q_reg[2]_0 [0]),
.O(\Q_reg[25] ));
LUT4 #(
.INIT(16'h4F40))
\Q[2]_i_1__6
(.I0(Q[2]),
.I1(\Q_reg[22] [1]),
.I2(\Q_reg[2]_0 [0]),
.I3(\Q_reg[2]_1 [1]),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_1 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_1 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_1 [2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized21
(overflow_flag,
Q,
OVRFLW_FLAG_FRMT,
CLK,
AR,
UNDRFLW_FLAG_FRMT,
\Q_reg[0]_0 );
output [2:0]overflow_flag;
input [0:0]Q;
input OVRFLW_FLAG_FRMT;
input CLK;
input [1:0]AR;
input UNDRFLW_FLAG_FRMT;
input [0:0]\Q_reg[0]_0 ;
wire [1:0]AR;
wire CLK;
wire OVRFLW_FLAG_FRMT;
wire [0:0]Q;
wire [0:0]\Q_reg[0]_0 ;
wire UNDRFLW_FLAG_FRMT;
wire [2:0]overflow_flag;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(Q),
.CLR(AR[1]),
.D(\Q_reg[0]_0 ),
.Q(overflow_flag[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(UNDRFLW_FLAG_FRMT),
.Q(overflow_flag[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(Q),
.CLR(AR[0]),
.D(OVRFLW_FLAG_FRMT),
.Q(overflow_flag[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized22
(ready_add_subt,
Q,
CLK,
AR);
output ready_add_subt;
input [0:0]Q;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]Q;
wire ready_add_subt;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(AR),
.D(Q),
.Q(ready_add_subt));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized3
(Q,
\Q_reg[6] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[6] ;
input [2:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[6] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR[0]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR[1]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR[0]),
.D(D[2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized4
(Q,
\Q_reg[5]_0 ,
D,
CLK,
AR);
output [30:0]Q;
input [0:0]\Q_reg[5]_0 ;
input [30:0]D;
input CLK;
input [2:0]AR;
wire [2:0]AR;
wire CLK;
wire [30:0]D;
wire [30:0]Q;
wire [0:0]\Q_reg[5]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[2]),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized5
(Q,
\Q_reg[5]_0 ,
D,
CLK,
AR);
output [22:0]Q;
input [0:0]\Q_reg[5]_0 ;
input [22:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [22:0]D;
wire [22:0]Q;
wire [0:0]\Q_reg[5]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[1]),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR[0]),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized6
(\Q_reg[23] ,
Q,
D,
\Q_reg[5] ,
\Q_reg[2]_0 ,
\Q_reg[1]_0 ,
\Q_reg[26] ,
CLK,
AR);
output \Q_reg[23] ;
output [1:0]Q;
output [1:0]D;
input [1:0]\Q_reg[5] ;
input [0:0]\Q_reg[2]_0 ;
input [2:0]\Q_reg[1]_0 ;
input [4:0]\Q_reg[26] ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [1:0]D;
wire [1:0]Q;
wire [2:0]\Q_reg[1]_0 ;
wire \Q_reg[23] ;
wire [4:0]\Q_reg[26] ;
wire [0:0]\Q_reg[2]_0 ;
wire [1:0]\Q_reg[5] ;
wire [4:1]Shift_amount_SHT1_EWR;
LUT4 #(
.INIT(16'h2E22))
\Q[25]_i_4
(.I0(Shift_amount_SHT1_EWR[1]),
.I1(\Q_reg[5] [0]),
.I2(\Q_reg[2]_0 ),
.I3(\Q_reg[1]_0 [0]),
.O(\Q_reg[23] ));
LUT4 #(
.INIT(16'h2E22))
\Q[3]_i_1__6
(.I0(Shift_amount_SHT1_EWR[3]),
.I1(\Q_reg[5] [0]),
.I2(\Q_reg[2]_0 ),
.I3(\Q_reg[1]_0 [1]),
.O(D[0]));
LUT4 #(
.INIT(16'h2E22))
\Q[4]_i_1__7
(.I0(Shift_amount_SHT1_EWR[4]),
.I1(\Q_reg[5] [0]),
.I2(\Q_reg[2]_0 ),
.I3(\Q_reg[1]_0 [2]),
.O(D[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [1]),
.Q(Shift_amount_SHT1_EWR[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [2]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [3]),
.Q(Shift_amount_SHT1_EWR[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5] [1]),
.CLR(AR),
.D(\Q_reg[26] [4]),
.Q(Shift_amount_SHT1_EWR[4]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized7
(Q,
\Q_reg[5] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[5] ;
input [2:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[5] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR[0]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR[1]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR[0]),
.D(D[2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized8
(Q,
\Q_reg[4]_0 ,
D,
CLK,
AR);
output [30:0]Q;
input [0:0]\Q_reg[4]_0 ;
input [30:0]D;
input CLK;
input [2:0]AR;
wire [2:0]AR;
wire CLK;
wire [30:0]D;
wire [30:0]Q;
wire [0:0]\Q_reg[4]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[1]),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[0]),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR[2]),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized9
(D,
\Data_array_SWR[6]_3 ,
\Q_reg[25]_0 ,
\Q_reg[8]_0 ,
\Q_reg[13]_0 ,
\Data_array_SWR[4]_4 ,
Q,
\Q_reg[4]_0 ,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[4]_1 ,
E,
\Q_reg[2]_0 ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [2:0]D;
output [0:0]\Data_array_SWR[6]_3 ;
output [4:0]\Q_reg[25]_0 ;
output [11:0]\Q_reg[8]_0 ;
output [7:0]\Q_reg[13]_0 ;
output [1:0]\Data_array_SWR[4]_4 ;
input [1:0]Q;
input [1:0]\Q_reg[4]_0 ;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [2:0]\Q_reg[4]_1 ;
input [0:0]E;
input [25:0]\Q_reg[2]_0 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [2:0]D;
wire [17:0]\Data_array_SWR[3]_0 ;
wire [1:0]\Data_array_SWR[4]_4 ;
wire [13:0]\Data_array_SWR[5]_2 ;
wire [0:0]\Data_array_SWR[6]_3 ;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [7:0]\Q_reg[13]_0 ;
wire [4:0]\Q_reg[25]_0 ;
wire [25:0]\Q_reg[2]_0 ;
wire [1:0]\Q_reg[4]_0 ;
wire [2:0]\Q_reg[4]_1 ;
wire [11:0]\Q_reg[8]_0 ;
wire UNDRFLW_FLAG_FRMT;
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT5 #(
.INIT(32'hFF00B8B8))
\Q[0]_i_1__13
(.I0(\Q_reg[8]_0 [10]),
.I1(\Q_reg[4]_1 [2]),
.I2(\Data_array_SWR[5]_2 [0]),
.I3(\Q_reg[4]_0 [1]),
.I4(Q[1]),
.O(\Q_reg[25]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'h02))
\Q[10]_i_1__8
(.I0(\Q_reg[25]_0 [1]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'h02))
\Q[11]_i_1__8
(.I0(\Q_reg[25]_0 [2]),
.I1(UNDRFLW_FLAG_FRMT),
.I2(OVRFLW_FLAG_FRMT),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT5 #(
.INIT(32'hF0BBF088))
\Q[12]_i_1__8
(.I0(\Data_array_SWR[5]_2 [13]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[4]_1 [2]),
.I4(\Data_array_SWR[5]_2 [12]),
.O(\Q_reg[25]_0 [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[12]_i_4__0
(.I0(\Q_reg[13]_0 [5]),
.I1(\Q_reg[13]_0 [1]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [15]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [11]),
.O(\Q_reg[8]_0 [9]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\Q[12]_i_5__0
(.I0(\Q_reg[13]_0 [0]),
.I1(\Q_reg[4]_1 [0]),
.I2(\Data_array_SWR[3]_0 [14]),
.O(\Data_array_SWR[4]_4 [0]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT5 #(
.INIT(32'hF0BBF088))
\Q[13]_i_1__6
(.I0(\Data_array_SWR[5]_2 [12]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[4]_1 [2]),
.I4(\Data_array_SWR[5]_2 [13]),
.O(\Q_reg[25]_0 [2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_2__1
(.I0(\Q_reg[13]_0 [6]),
.I1(\Q_reg[13]_0 [2]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [16]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [12]),
.O(\Data_array_SWR[5]_2 [12]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_3
(.I0(\Q_reg[13]_0 [7]),
.I1(\Q_reg[13]_0 [3]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [17]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [13]),
.O(\Data_array_SWR[5]_2 [13]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_4
(.I0(\Q_reg[13]_0 [4]),
.I1(\Q_reg[13]_0 [0]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [14]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [10]),
.O(\Q_reg[8]_0 [8]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\Q[13]_i_5
(.I0(\Q_reg[13]_0 [1]),
.I1(\Q_reg[4]_1 [0]),
.I2(\Data_array_SWR[3]_0 [15]),
.O(\Data_array_SWR[4]_4 [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_3
(.I0(\Q_reg[13]_0 [3]),
.I1(\Data_array_SWR[3]_0 [17]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [13]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [9]),
.O(\Q_reg[8]_0 [7]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_4
(.I0(\Q_reg[13]_0 [1]),
.I1(\Data_array_SWR[3]_0 [15]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [11]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [7]),
.O(\Q_reg[8]_0 [5]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_3
(.I0(Q[0]),
.I1(\Q_reg[13]_0 [7]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Q_reg[13]_0 [3]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [17]),
.O(\Q_reg[8]_0 [11]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_4
(.I0(\Q_reg[13]_0 [0]),
.I1(\Data_array_SWR[3]_0 [14]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [10]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [6]),
.O(\Q_reg[8]_0 [4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_4__0
(.I0(\Q_reg[13]_0 [2]),
.I1(\Data_array_SWR[3]_0 [16]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [12]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [8]),
.O(\Q_reg[8]_0 [6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_5
(.I0(\Data_array_SWR[3]_0 [17]),
.I1(\Data_array_SWR[3]_0 [13]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [9]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [5]),
.O(\Q_reg[8]_0 [3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_5
(.I0(\Data_array_SWR[3]_0 [16]),
.I1(\Data_array_SWR[3]_0 [12]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [8]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [4]),
.O(\Q_reg[8]_0 [2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_5
(.I0(\Data_array_SWR[3]_0 [15]),
.I1(\Data_array_SWR[3]_0 [11]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [7]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [3]),
.O(\Q_reg[8]_0 [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_5
(.I0(\Data_array_SWR[3]_0 [14]),
.I1(\Data_array_SWR[3]_0 [10]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [6]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [2]),
.O(\Q_reg[8]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[22]_i_1__8
(.I0(\Data_array_SWR[6]_3 ),
.I1(Q[1]),
.I2(\Q_reg[4]_0 [0]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(D[2]));
LUT3 #(
.INIT(8'hB8))
\Q[22]_i_2__0
(.I0(\Q_reg[8]_0 [11]),
.I1(\Q_reg[4]_1 [2]),
.I2(\Data_array_SWR[5]_2 [1]),
.O(\Data_array_SWR[6]_3 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[22]_i_4
(.I0(\Data_array_SWR[3]_0 [13]),
.I1(\Data_array_SWR[3]_0 [9]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [5]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [1]),
.O(\Data_array_SWR[5]_2 [1]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\Q[24]_i_1__8
(.I0(\Data_array_SWR[6]_3 ),
.I1(Q[1]),
.I2(\Q_reg[4]_0 [0]),
.O(\Q_reg[25]_0 [3]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT5 #(
.INIT(32'hB8FFB800))
\Q[25]_i_1__8
(.I0(\Q_reg[8]_0 [10]),
.I1(\Q_reg[4]_1 [2]),
.I2(\Data_array_SWR[5]_2 [0]),
.I3(Q[1]),
.I4(\Q_reg[4]_0 [1]),
.O(\Q_reg[25]_0 [4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[25]_i_2__0
(.I0(Q[0]),
.I1(\Q_reg[13]_0 [6]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Q_reg[13]_0 [2]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [16]),
.O(\Q_reg[8]_0 [10]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[25]_i_3__0
(.I0(\Data_array_SWR[3]_0 [12]),
.I1(\Data_array_SWR[3]_0 [8]),
.I2(\Q_reg[4]_1 [1]),
.I3(\Data_array_SWR[3]_0 [4]),
.I4(\Q_reg[4]_1 [0]),
.I5(\Data_array_SWR[3]_0 [0]),
.O(\Data_array_SWR[5]_2 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [0]),
.Q(\Data_array_SWR[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [10]),
.Q(\Data_array_SWR[3]_0 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [11]),
.Q(\Data_array_SWR[3]_0 [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [12]),
.Q(\Data_array_SWR[3]_0 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [13]),
.Q(\Data_array_SWR[3]_0 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [14]),
.Q(\Data_array_SWR[3]_0 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [15]),
.Q(\Data_array_SWR[3]_0 [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [16]),
.Q(\Data_array_SWR[3]_0 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [17]),
.Q(\Data_array_SWR[3]_0 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [18]),
.Q(\Q_reg[13]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [19]),
.Q(\Q_reg[13]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [1]),
.Q(\Data_array_SWR[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [20]),
.Q(\Q_reg[13]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [21]),
.Q(\Q_reg[13]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [22]),
.Q(\Q_reg[13]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [23]),
.Q(\Q_reg[13]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [24]),
.Q(\Q_reg[13]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [25]),
.Q(\Q_reg[13]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [2]),
.Q(\Data_array_SWR[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [3]),
.Q(\Data_array_SWR[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [4]),
.Q(\Data_array_SWR[3]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [5]),
.Q(\Data_array_SWR[3]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [6]),
.Q(\Data_array_SWR[3]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [7]),
.Q(\Data_array_SWR[3]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [8]),
.Q(\Data_array_SWR[3]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\Q_reg[2]_0 [9]),
.Q(\Data_array_SWR[3]_0 [9]));
endmodule
module ShiftRegister
(E,
Q,
\Q_reg[1]_0 ,
\Q_reg[1]_1 ,
\Q_reg[2]_0 ,
\FSM_sequential_state_reg_reg[0] ,
D,
CLK,
AR);
output [0:0]E;
output [5:0]Q;
output [0:0]\Q_reg[1]_0 ;
output [1:0]\Q_reg[1]_1 ;
input [0:0]\Q_reg[2]_0 ;
input [0:0]\FSM_sequential_state_reg_reg[0] ;
input [0:0]D;
input CLK;
input [1:0]AR;
wire [1:0]AR;
wire CLK;
wire [0:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[0] ;
wire [5:0]Q;
wire [0:0]\Q_reg[1]_0 ;
wire [1:0]\Q_reg[1]_1 ;
wire [0:0]\Q_reg[2]_0 ;
wire \Q_reg_n_0_[3] ;
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT2 #(
.INIT(4'h8))
\Q[0]_i_1__9
(.I0(Q[1]),
.I1(\Q_reg[2]_0 ),
.O(\Q_reg[1]_1 [0]));
LUT2 #(
.INIT(4'h2))
\Q[1]_i_1__7
(.I0(Q[1]),
.I1(\Q_reg[2]_0 ),
.O(\Q_reg[1]_1 [1]));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT2 #(
.INIT(4'hE))
\Q[25]_i_1__6
(.I0(Q[1]),
.I1(Q[3]),
.O(\Q_reg[1]_0 ));
LUT2 #(
.INIT(4'h2))
\Q[30]_i_1__6
(.I0(\Q_reg_n_0_[3] ),
.I1(Q[0]),
.O(E));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[1]),
.D(Q[1]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(Q[2]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(\Q_reg_n_0_[3] ),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(Q[3]),
.Q(\Q_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(Q[4]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(Q[5]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[0] ),
.CLR(AR[0]),
.D(D),
.Q(Q[5]));
endmodule
module Simple_Subt
(D,
Q,
\Q_reg[26] ,
S);
output [7:0]D;
input [6:0]Q;
input [3:0]\Q_reg[26] ;
input [3:0]S;
wire [7:0]D;
wire [6:0]Q;
wire [3:0]\Q_reg[26] ;
wire [3:0]S;
wire Y_carry__0_n_1;
wire Y_carry__0_n_2;
wire Y_carry__0_n_3;
wire Y_carry_n_0;
wire Y_carry_n_1;
wire Y_carry_n_2;
wire Y_carry_n_3;
wire [3:3]NLW_Y_carry__0_CO_UNCONNECTED;
CARRY4 Y_carry
(.CI(1'b0),
.CO({Y_carry_n_0,Y_carry_n_1,Y_carry_n_2,Y_carry_n_3}),
.CYINIT(1'b1),
.DI(Q[3:0]),
.O(D[3:0]),
.S(\Q_reg[26] ));
CARRY4 Y_carry__0
(.CI(Y_carry_n_0),
.CO({NLW_Y_carry__0_CO_UNCONNECTED[3],Y_carry__0_n_1,Y_carry__0_n_2,Y_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Q[6:4]}),
.O(D[7:4]),
.S(S));
endmodule
module Up_counter
(Q,
max_tick_iter,
D,
\Q_reg[31] ,
\Q_reg[31]_0 ,
\Q_reg[26] ,
\Q_reg[31]_1 ,
\Q_reg[31]_2 ,
\Q_reg[31]_3 ,
\Q_reg[31]_4 ,
SR,
E,
CLK);
output [3:0]Q;
output max_tick_iter;
output [31:0]D;
output [31:0]\Q_reg[31] ;
output [31:0]\Q_reg[31]_0 ;
output [19:0]\Q_reg[26] ;
input [31:0]\Q_reg[31]_1 ;
input [31:0]\Q_reg[31]_2 ;
input [31:0]\Q_reg[31]_3 ;
input [31:0]\Q_reg[31]_4 ;
input [0:0]SR;
input [0:0]E;
input CLK;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [19:0]\Q_reg[26] ;
wire [31:0]\Q_reg[31] ;
wire [31:0]\Q_reg[31]_0 ;
wire [31:0]\Q_reg[31]_1 ;
wire [31:0]\Q_reg[31]_2 ;
wire [31:0]\Q_reg[31]_3 ;
wire [31:0]\Q_reg[31]_4 ;
wire [0:0]SR;
wire max_tick_iter;
wire [3:0]p_0_in;
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h8000))
\FSM_sequential_state_reg[2]_i_2
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(max_tick_iter));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7465))
\Q[0]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.O(\Q_reg[26] [0]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[0]_i_1__0
(.I0(\Q_reg[31]_1 [0]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [0]),
.O(D[0]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[0]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [0]),
.O(\Q_reg[31]_0 [0]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[0]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [0]),
.O(\Q_reg[31] [0]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h7445))
\Q[10]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[1]),
.O(\Q_reg[26] [7]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[10]_i_1__0
(.I0(\Q_reg[31]_1 [10]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [10]),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[10]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [10]),
.O(\Q_reg[31] [10]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[10]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [10]),
.O(\Q_reg[31]_0 [10]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h55EF))
\Q[11]_i_1
(.I0(Q[2]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[3]),
.O(\Q_reg[26] [8]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[11]_i_1__0
(.I0(\Q_reg[31]_1 [11]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [11]),
.O(D[11]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[11]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [11]),
.O(\Q_reg[31]_0 [11]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[11]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [11]),
.O(\Q_reg[31] [11]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h6474))
\Q[12]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.O(\Q_reg[26] [9]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[12]_i_1__0
(.I0(\Q_reg[31]_1 [12]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [12]),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[12]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [12]),
.O(\Q_reg[31] [12]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[12]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [12]),
.O(\Q_reg[31]_0 [12]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[13]_i_1
(.I0(\Q_reg[31]_1 [13]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [13]),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[13]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [13]),
.O(\Q_reg[31] [13]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[13]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [13]),
.O(\Q_reg[31]_0 [13]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h54BE))
\Q[14]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.O(\Q_reg[26] [10]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[14]_i_1__0
(.I0(\Q_reg[31]_1 [14]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [14]),
.O(D[14]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[14]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [14]),
.O(\Q_reg[31] [14]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[14]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [14]),
.O(\Q_reg[31]_0 [14]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[15]_i_1
(.I0(\Q_reg[31]_1 [15]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [15]),
.O(D[15]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[15]_i_1__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [15]),
.O(\Q_reg[31]_0 [15]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[15]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [15]),
.O(\Q_reg[31] [15]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[16]_i_1
(.I0(\Q_reg[31]_1 [16]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [16]),
.O(D[16]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[16]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [16]),
.O(\Q_reg[31] [16]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[16]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [16]),
.O(\Q_reg[31]_0 [16]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h5B))
\Q[16]_i_1__7
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[2]),
.O(\Q_reg[26] [11]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[17]_i_1
(.I0(\Q_reg[31]_1 [17]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [17]),
.O(D[17]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[17]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [17]),
.O(\Q_reg[31] [17]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[17]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [17]),
.O(\Q_reg[31]_0 [17]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[18]_i_1
(.I0(\Q_reg[31]_1 [18]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [18]),
.O(D[18]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[18]_i_1__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [18]),
.O(\Q_reg[31]_0 [18]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[18]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [18]),
.O(\Q_reg[31] [18]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h5E))
\Q[18]_i_1__7
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.O(\Q_reg[26] [12]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[19]_i_1
(.I0(\Q_reg[31]_1 [19]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [19]),
.O(D[19]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[19]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [19]),
.O(\Q_reg[31] [19]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[19]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [19]),
.O(\Q_reg[31]_0 [19]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[1]_i_1__0
(.I0(\Q_reg[31]_1 [1]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[1]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [1]),
.O(\Q_reg[31] [1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h55AB))
\Q[1]_i_1__12
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[2]),
.O(\Q_reg[26] [1]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[1]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [1]),
.O(\Q_reg[31]_0 [1]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[20]_i_1
(.I0(\Q_reg[31]_1 [20]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [20]),
.O(D[20]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[20]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [20]),
.O(\Q_reg[31] [20]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[20]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [20]),
.O(\Q_reg[31]_0 [20]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'h5E))
\Q[20]_i_1__7
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[2]),
.O(\Q_reg[26] [13]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h55FE))
\Q[21]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(\Q_reg[26] [14]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[21]_i_1__0
(.I0(\Q_reg[31]_1 [21]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [21]),
.O(D[21]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[21]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [21]),
.O(\Q_reg[31]_0 [21]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[21]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [21]),
.O(\Q_reg[31] [21]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h7))
\Q[22]_i_1
(.I0(Q[3]),
.I1(Q[2]),
.O(\Q_reg[26] [15]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[22]_i_1__0
(.I0(\Q_reg[31]_1 [22]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [22]),
.O(D[22]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[22]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [22]),
.O(\Q_reg[31]_0 [22]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[22]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [22]),
.O(\Q_reg[31] [22]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[23]_i_1
(.I0(\Q_reg[31]_1 [23]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [23]),
.O(D[23]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[23]_i_1__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [23]),
.O(\Q_reg[31]_0 [23]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[23]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [23]),
.O(\Q_reg[31] [23]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h6A))
\Q[23]_i_1__8
(.I0(Q[0]),
.I1(Q[2]),
.I2(Q[3]),
.O(\Q_reg[26] [16]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h708F))
\Q[24]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[1]),
.O(\Q_reg[26] [17]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[24]_i_1__0
(.I0(\Q_reg[31]_1 [24]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [24]),
.O(D[24]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[24]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [24]),
.O(\Q_reg[31] [24]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[24]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [24]),
.O(\Q_reg[31]_0 [24]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h0787))
\Q[25]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\Q_reg[26] [18]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[25]_i_1__0
(.I0(\Q_reg[31]_1 [25]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [25]),
.O(D[25]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[25]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [25]),
.O(\Q_reg[31] [25]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[25]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [25]),
.O(\Q_reg[31]_0 [25]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h007F))
\Q[26]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[3]),
.O(\Q_reg[26] [19]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[26]_i_1__0
(.I0(\Q_reg[31]_1 [26]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [26]),
.O(D[26]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[26]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [26]),
.O(\Q_reg[31] [26]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[26]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [26]),
.O(\Q_reg[31]_0 [26]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[27]_i_1
(.I0(\Q_reg[31]_1 [27]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [27]),
.O(D[27]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[27]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [27]),
.O(\Q_reg[31] [27]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[27]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [27]),
.O(\Q_reg[31]_0 [27]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[28]_i_1
(.I0(\Q_reg[31]_1 [28]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [28]),
.O(D[28]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[28]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [28]),
.O(\Q_reg[31] [28]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[28]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [28]),
.O(\Q_reg[31]_0 [28]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[29]_i_1__0
(.I0(\Q_reg[31]_1 [29]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [29]),
.O(D[29]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[29]_i_1__1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [29]),
.O(\Q_reg[31] [29]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[29]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [29]),
.O(\Q_reg[31]_0 [29]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[2]_i_1
(.I0(\Q_reg[31]_1 [2]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [2]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[2]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [2]),
.O(\Q_reg[31] [2]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[2]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [2]),
.O(\Q_reg[31]_0 [2]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0858))
\Q[2]_i_1__10
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\Q_reg[26] [2]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[30]_i_1
(.I0(\Q_reg[31]_1 [30]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [30]),
.O(D[30]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[30]_i_1__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [30]),
.O(\Q_reg[31]_0 [30]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[30]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [30]),
.O(\Q_reg[31] [30]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[31]_i_1__3
(.I0(\Q_reg[31]_1 [31]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [31]),
.O(D[31]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[31]_i_1__4
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(\Q_reg[31]_4 [31]),
.O(\Q_reg[31]_0 [31]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[31]_i_2__0
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(\Q_reg[31]_3 [31]),
.O(\Q_reg[31] [31]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[3]_i_1
(.I0(\Q_reg[31]_1 [3]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [3]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[3]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [3]),
.O(\Q_reg[31] [3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[3]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [3]),
.O(\Q_reg[31]_0 [3]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h01F3))
\Q[4]_i_1
(.I0(Q[0]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[2]),
.O(\Q_reg[26] [3]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[4]_i_1__0
(.I0(\Q_reg[31]_1 [4]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [4]),
.O(D[4]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[4]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [4]),
.O(\Q_reg[31]_0 [4]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[4]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [4]),
.O(\Q_reg[31] [4]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[5]_i_1
(.I0(\Q_reg[31]_1 [5]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [5]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[5]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [5]),
.O(\Q_reg[31] [5]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[5]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [5]),
.O(\Q_reg[31]_0 [5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h5443))
\Q[6]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(\Q_reg[26] [4]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[6]_i_1__1
(.I0(\Q_reg[31]_1 [6]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [6]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[6]_i_1__2
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [6]),
.O(\Q_reg[31] [6]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[6]_i_1__3
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [6]),
.O(\Q_reg[31]_0 [6]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[7]_i_1
(.I0(\Q_reg[31]_1 [7]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'hFFFF0001))
\Q[7]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [7]),
.O(\Q_reg[31] [7]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[7]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [7]),
.O(\Q_reg[31]_0 [7]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT1 #(
.INIT(2'h1))
\Q[8]_i_1
(.I0(Q[2]),
.O(\Q_reg[26] [5]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[8]_i_1__0
(.I0(\Q_reg[31]_1 [8]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [8]),
.O(D[8]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[8]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [8]),
.O(\Q_reg[31]_0 [8]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[8]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [8]),
.O(\Q_reg[31] [8]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h55BF))
\Q[9]_i_1
(.I0(Q[2]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[3]),
.O(\Q_reg[26] [6]));
LUT6 #(
.INIT(64'hAAAAAAABAAAAAAA8))
\Q[9]_i_1__0
(.I0(\Q_reg[31]_1 [9]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[1]),
.I5(\Q_reg[31]_2 [9]),
.O(D[9]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'hFFFE0000))
\Q[9]_i_1__1
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_4 [9]),
.O(\Q_reg[31]_0 [9]));
LUT5 #(
.INIT(32'hFFFE0000))
\Q[9]_i_1__2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(\Q_reg[31]_3 [9]),
.O(\Q_reg[31] [9]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT1 #(
.INIT(2'h1))
\temp[0]_i_1
(.I0(Q[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h6))
\temp[1]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h78))
\temp[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h6AAA))
\temp[3]_i_2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.O(p_0_in[3]));
FDRE #(
.INIT(1'b0))
\temp_reg[0]
(.C(CLK),
.CE(E),
.D(p_0_in[0]),
.Q(Q[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\temp_reg[1]
(.C(CLK),
.CE(E),
.D(p_0_in[1]),
.Q(Q[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\temp_reg[2]
(.C(CLK),
.CE(E),
.D(p_0_in[2]),
.Q(Q[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\temp_reg[3]
(.C(CLK),
.CE(E),
.D(p_0_in[3]),
.Q(Q[3]),
.R(SR));
endmodule
(* ORIG_REF_NAME = "Up_counter" *)
module Up_counter__parameterized0
(E,
cont_var_out,
\Q_reg[31] ,
\Q_reg[31]_0 ,
D,
\Q_reg[31]_1 ,
op_add_subt,
ready_add_subt,
Q,
\Q_reg[31]_2 ,
\Q_reg[29] ,
\Q_reg[31]_3 ,
\Q_reg[31]_4 ,
\Q_reg[31]_5 ,
d_ff3_sign_out,
out,
rst_IBUF,
CLK);
output [0:0]E;
output [1:0]cont_var_out;
output [0:0]\Q_reg[31] ;
output [0:0]\Q_reg[31]_0 ;
output [31:0]D;
output [31:0]\Q_reg[31]_1 ;
output op_add_subt;
input ready_add_subt;
input [31:0]Q;
input [31:0]\Q_reg[31]_2 ;
input [20:0]\Q_reg[29] ;
input [31:0]\Q_reg[31]_3 ;
input [31:0]\Q_reg[31]_4 ;
input [31:0]\Q_reg[31]_5 ;
input d_ff3_sign_out;
input [1:0]out;
input rst_IBUF;
input CLK;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [31:0]Q;
wire [20:0]\Q_reg[29] ;
wire [0:0]\Q_reg[31] ;
wire [0:0]\Q_reg[31]_0 ;
wire [31:0]\Q_reg[31]_1 ;
wire [31:0]\Q_reg[31]_2 ;
wire [31:0]\Q_reg[31]_3 ;
wire [31:0]\Q_reg[31]_4 ;
wire [31:0]\Q_reg[31]_5 ;
wire [1:0]cont_var_out;
wire d_ff3_sign_out;
wire op_add_subt;
wire [1:0]out;
wire ready_add_subt;
wire rst_IBUF;
wire \temp[0]_i_1_n_0 ;
wire \temp[1]_i_1_n_0 ;
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[0]_i_1__3
(.I0(\Q_reg[29] [0]),
.I1(Q[0]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [0]),
.I4(cont_var_out[1]),
.O(D[0]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[0]_i_1__4
(.I0(\Q_reg[31]_3 [0]),
.I1(\Q_reg[31]_4 [0]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [0]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [0]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h6))
\Q[0]_i_1__6
(.I0(cont_var_out[0]),
.I1(d_ff3_sign_out),
.O(op_add_subt));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[10]_i_1__3
(.I0(\Q_reg[29] [7]),
.I1(Q[10]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [10]),
.I4(cont_var_out[1]),
.O(D[10]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[10]_i_1__4
(.I0(\Q_reg[31]_3 [10]),
.I1(\Q_reg[31]_4 [10]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [10]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [10]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[11]_i_1__3
(.I0(\Q_reg[29] [8]),
.I1(Q[11]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [11]),
.I4(cont_var_out[1]),
.O(D[11]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[11]_i_1__4
(.I0(\Q_reg[31]_3 [11]),
.I1(\Q_reg[31]_4 [11]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [11]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [11]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[12]_i_1__3
(.I0(\Q_reg[29] [9]),
.I1(Q[12]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [12]),
.I4(cont_var_out[1]),
.O(D[12]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[12]_i_1__4
(.I0(\Q_reg[31]_3 [12]),
.I1(\Q_reg[31]_4 [12]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [12]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [12]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[13]_i_1__2
(.I0(\Q_reg[29] [12]),
.I1(Q[13]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [13]),
.I4(cont_var_out[1]),
.O(D[13]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[13]_i_1__3
(.I0(\Q_reg[31]_3 [13]),
.I1(\Q_reg[31]_4 [13]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [13]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [13]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[14]_i_1__3
(.I0(\Q_reg[29] [10]),
.I1(Q[14]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [14]),
.I4(cont_var_out[1]),
.O(D[14]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[14]_i_1__4
(.I0(\Q_reg[31]_3 [14]),
.I1(\Q_reg[31]_4 [14]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [14]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [14]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[15]_i_1__2
(.I0(\Q_reg[29] [13]),
.I1(Q[15]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [15]),
.I4(cont_var_out[1]),
.O(D[15]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[15]_i_1__3
(.I0(\Q_reg[31]_3 [15]),
.I1(\Q_reg[31]_4 [15]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [15]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [15]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[16]_i_1__2
(.I0(\Q_reg[29] [11]),
.I1(Q[16]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [16]),
.I4(cont_var_out[1]),
.O(D[16]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[16]_i_1__3
(.I0(\Q_reg[31]_3 [16]),
.I1(\Q_reg[31]_4 [16]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [16]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [16]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[17]_i_1__2
(.I0(\Q_reg[29] [13]),
.I1(Q[17]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [17]),
.I4(cont_var_out[1]),
.O(D[17]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[17]_i_1__3
(.I0(\Q_reg[31]_3 [17]),
.I1(\Q_reg[31]_4 [17]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [17]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [17]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[18]_i_1__2
(.I0(\Q_reg[29] [12]),
.I1(Q[18]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [18]),
.I4(cont_var_out[1]),
.O(D[18]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[18]_i_1__3
(.I0(\Q_reg[31]_3 [18]),
.I1(\Q_reg[31]_4 [18]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [18]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [18]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[19]_i_1__2
(.I0(\Q_reg[29] [15]),
.I1(Q[19]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [19]),
.I4(cont_var_out[1]),
.O(D[19]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[19]_i_1__3
(.I0(\Q_reg[31]_3 [19]),
.I1(\Q_reg[31]_4 [19]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [19]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [19]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[1]_i_1__3
(.I0(\Q_reg[29] [1]),
.I1(Q[1]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [1]),
.I4(cont_var_out[1]),
.O(D[1]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[1]_i_1__4
(.I0(\Q_reg[31]_3 [1]),
.I1(\Q_reg[31]_4 [1]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [1]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [1]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[20]_i_1__2
(.I0(\Q_reg[29] [13]),
.I1(Q[20]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [20]),
.I4(cont_var_out[1]),
.O(D[20]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[20]_i_1__3
(.I0(\Q_reg[31]_3 [20]),
.I1(\Q_reg[31]_4 [20]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [20]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [20]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[21]_i_1__3
(.I0(\Q_reg[29] [14]),
.I1(Q[21]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [21]),
.I4(cont_var_out[1]),
.O(D[21]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[21]_i_1__4
(.I0(\Q_reg[31]_3 [21]),
.I1(\Q_reg[31]_4 [21]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [21]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [21]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[22]_i_1__3
(.I0(\Q_reg[29] [15]),
.I1(Q[22]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [22]),
.I4(cont_var_out[1]),
.O(D[22]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[22]_i_1__4
(.I0(\Q_reg[31]_3 [22]),
.I1(\Q_reg[31]_4 [22]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [22]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [22]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[23]_i_1__2
(.I0(\Q_reg[29] [16]),
.I1(Q[23]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [23]),
.I4(cont_var_out[1]),
.O(D[23]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[23]_i_1__3
(.I0(\Q_reg[31]_3 [23]),
.I1(\Q_reg[31]_4 [23]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [23]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [23]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[24]_i_1__3
(.I0(\Q_reg[29] [17]),
.I1(Q[24]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [24]),
.I4(cont_var_out[1]),
.O(D[24]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[24]_i_1__4
(.I0(\Q_reg[31]_3 [24]),
.I1(\Q_reg[31]_4 [24]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [24]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [24]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[25]_i_1__3
(.I0(\Q_reg[29] [18]),
.I1(Q[25]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [25]),
.I4(cont_var_out[1]),
.O(D[25]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[25]_i_1__4
(.I0(\Q_reg[31]_3 [25]),
.I1(\Q_reg[31]_4 [25]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [25]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [25]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[26]_i_1__3
(.I0(\Q_reg[29] [19]),
.I1(Q[26]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [26]),
.I4(cont_var_out[1]),
.O(D[26]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[26]_i_1__4
(.I0(\Q_reg[31]_3 [26]),
.I1(\Q_reg[31]_4 [26]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [26]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [26]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[27]_i_1__2
(.I0(\Q_reg[29] [20]),
.I1(Q[27]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [27]),
.I4(cont_var_out[1]),
.O(D[27]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[27]_i_1__3
(.I0(\Q_reg[31]_3 [27]),
.I1(\Q_reg[31]_4 [27]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [27]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [27]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[28]_i_1__2
(.I0(\Q_reg[29] [20]),
.I1(Q[28]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [28]),
.I4(cont_var_out[1]),
.O(D[28]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[28]_i_1__3
(.I0(\Q_reg[31]_3 [28]),
.I1(\Q_reg[31]_4 [28]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [28]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [28]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[29]_i_1__3
(.I0(\Q_reg[29] [20]),
.I1(Q[29]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [29]),
.I4(cont_var_out[1]),
.O(D[29]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[29]_i_1__4
(.I0(\Q_reg[31]_3 [29]),
.I1(\Q_reg[31]_4 [29]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [29]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [29]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[2]_i_1__2
(.I0(\Q_reg[29] [2]),
.I1(Q[2]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [2]),
.I4(cont_var_out[1]),
.O(D[2]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[2]_i_1__3
(.I0(\Q_reg[31]_3 [2]),
.I1(\Q_reg[31]_4 [2]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [2]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [2]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h3088))
\Q[30]_i_1__2
(.I0(Q[30]),
.I1(cont_var_out[0]),
.I2(\Q_reg[31]_2 [30]),
.I3(cont_var_out[1]),
.O(D[30]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[30]_i_1__3
(.I0(\Q_reg[31]_3 [30]),
.I1(\Q_reg[31]_4 [30]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [30]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [30]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'h08))
\Q[31]_i_1__0
(.I0(cont_var_out[1]),
.I1(ready_add_subt),
.I2(cont_var_out[0]),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'h04))
\Q[31]_i_1__1
(.I0(cont_var_out[1]),
.I1(ready_add_subt),
.I2(cont_var_out[0]),
.O(\Q_reg[31] ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'h40))
\Q[31]_i_1__2
(.I0(cont_var_out[1]),
.I1(ready_add_subt),
.I2(cont_var_out[0]),
.O(\Q_reg[31]_0 ));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[31]_i_1__5
(.I0(\Q_reg[31]_3 [31]),
.I1(\Q_reg[31]_4 [31]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [31]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [31]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h3088))
\Q[31]_i_2__1
(.I0(Q[31]),
.I1(cont_var_out[0]),
.I2(\Q_reg[31]_2 [31]),
.I3(cont_var_out[1]),
.O(D[31]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[3]_i_1__2
(.I0(\Q_reg[29] [11]),
.I1(Q[3]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [3]),
.I4(cont_var_out[1]),
.O(D[3]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[3]_i_1__3
(.I0(\Q_reg[31]_3 [3]),
.I1(\Q_reg[31]_4 [3]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [3]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [3]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[4]_i_1__3
(.I0(\Q_reg[29] [3]),
.I1(Q[4]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [4]),
.I4(cont_var_out[1]),
.O(D[4]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[4]_i_1__4
(.I0(\Q_reg[31]_3 [4]),
.I1(\Q_reg[31]_4 [4]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [4]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [4]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[5]_i_1__2
(.I0(\Q_reg[29] [10]),
.I1(Q[5]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [5]),
.I4(cont_var_out[1]),
.O(D[5]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[5]_i_1__3
(.I0(\Q_reg[31]_3 [5]),
.I1(\Q_reg[31]_4 [5]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [5]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [5]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[6]_i_1__4
(.I0(\Q_reg[29] [4]),
.I1(Q[6]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [6]),
.I4(cont_var_out[1]),
.O(D[6]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[6]_i_1__5
(.I0(\Q_reg[31]_3 [6]),
.I1(\Q_reg[31]_4 [6]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [6]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [6]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[7]_i_1__2
(.I0(\Q_reg[29] [8]),
.I1(Q[7]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [7]),
.I4(cont_var_out[1]),
.O(D[7]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[7]_i_1__3
(.I0(\Q_reg[31]_3 [7]),
.I1(\Q_reg[31]_4 [7]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [7]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [7]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[8]_i_1__3
(.I0(\Q_reg[29] [5]),
.I1(Q[8]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [8]),
.I4(cont_var_out[1]),
.O(D[8]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[8]_i_1__4
(.I0(\Q_reg[31]_3 [8]),
.I1(\Q_reg[31]_4 [8]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [8]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [8]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[9]_i_1__3
(.I0(\Q_reg[29] [6]),
.I1(Q[9]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_2 [9]),
.I4(cont_var_out[1]),
.O(D[9]));
LUT5 #(
.INIT(32'hAFA0C0C0))
\Q[9]_i_1__4
(.I0(\Q_reg[31]_3 [9]),
.I1(\Q_reg[31]_4 [9]),
.I2(cont_var_out[0]),
.I3(\Q_reg[31]_5 [9]),
.I4(cont_var_out[1]),
.O(\Q_reg[31]_1 [9]));
LUT5 #(
.INIT(32'h0000559A))
\temp[0]_i_1
(.I0(cont_var_out[0]),
.I1(out[0]),
.I2(out[1]),
.I3(ready_add_subt),
.I4(rst_IBUF),
.O(\temp[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000006656AAAA))
\temp[1]_i_1
(.I0(cont_var_out[1]),
.I1(ready_add_subt),
.I2(out[1]),
.I3(out[0]),
.I4(cont_var_out[0]),
.I5(rst_IBUF),
.O(\temp[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\temp_reg[0]
(.C(CLK),
.CE(1'b1),
.D(\temp[0]_i_1_n_0 ),
.Q(cont_var_out[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\temp_reg[1]
(.C(CLK),
.CE(1'b1),
.D(\temp[1]_i_1_n_0 ),
.Q(cont_var_out[1]),
.R(1'b0));
endmodule
module d_ff_en
(d_ff1_operation_out,
E,
operation_IBUF,
CLK,
\FSM_sequential_state_reg_reg[1] );
output d_ff1_operation_out;
input [0:0]E;
input operation_IBUF;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire d_ff1_operation_out;
wire operation_IBUF;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(operation_IBUF),
.Q(d_ff1_operation_out));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en_0
(d_ff3_sign_out,
\FSM_sequential_state_reg_reg[2] ,
Q,
CLK,
\FSM_sequential_state_reg_reg[1] );
output d_ff3_sign_out;
input [0:0]\FSM_sequential_state_reg_reg[2] ;
input [0:0]Q;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [0:0]\FSM_sequential_state_reg_reg[2] ;
wire [0:0]Q;
wire d_ff3_sign_out;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(Q),
.Q(d_ff3_sign_out));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized0
(D,
d_ff1_operation_out,
Q,
\Q_reg[31] ,
E,
\shift_region_flag[1] ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]D;
input d_ff1_operation_out;
input [31:0]Q;
input [31:0]\Q_reg[31] ;
input [0:0]E;
input [1:0]\shift_region_flag[1] ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire [31:0]\Q_reg[31] ;
wire d_ff1_operation_out;
wire [1:0]d_ff1_shift_region_flag_out;
wire [1:0]\shift_region_flag[1] ;
LUT5 #(
.INIT(32'hACCACAAC))
\Q[0]_i_1__5
(.I0(Q[0]),
.I1(\Q_reg[31] [0]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[0]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[10]_i_1__5
(.I0(Q[10]),
.I1(\Q_reg[31] [10]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[10]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[11]_i_1__5
(.I0(Q[11]),
.I1(\Q_reg[31] [11]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[11]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[12]_i_1__5
(.I0(Q[12]),
.I1(\Q_reg[31] [12]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[12]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[13]_i_1__4
(.I0(Q[13]),
.I1(\Q_reg[31] [13]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[13]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[14]_i_1__5
(.I0(Q[14]),
.I1(\Q_reg[31] [14]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[14]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[15]_i_1__4
(.I0(Q[15]),
.I1(\Q_reg[31] [15]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[15]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[16]_i_1__4
(.I0(Q[16]),
.I1(\Q_reg[31] [16]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[16]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[17]_i_1__4
(.I0(Q[17]),
.I1(\Q_reg[31] [17]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[17]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[18]_i_1__4
(.I0(Q[18]),
.I1(\Q_reg[31] [18]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[18]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[19]_i_1__4
(.I0(Q[19]),
.I1(\Q_reg[31] [19]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[19]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[1]_i_1__5
(.I0(Q[1]),
.I1(\Q_reg[31] [1]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[1]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[20]_i_1__4
(.I0(Q[20]),
.I1(\Q_reg[31] [20]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[20]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[21]_i_1__5
(.I0(Q[21]),
.I1(\Q_reg[31] [21]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[21]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[22]_i_1__5
(.I0(Q[22]),
.I1(\Q_reg[31] [22]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[22]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[23]_i_1__4
(.I0(Q[23]),
.I1(\Q_reg[31] [23]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[23]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[24]_i_1__5
(.I0(Q[24]),
.I1(\Q_reg[31] [24]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[24]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[25]_i_1__5
(.I0(Q[25]),
.I1(\Q_reg[31] [25]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[25]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[26]_i_1__5
(.I0(Q[26]),
.I1(\Q_reg[31] [26]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[26]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[27]_i_1__4
(.I0(Q[27]),
.I1(\Q_reg[31] [27]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[27]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[28]_i_1__4
(.I0(Q[28]),
.I1(\Q_reg[31] [28]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[28]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[29]_i_1__5
(.I0(Q[29]),
.I1(\Q_reg[31] [29]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[29]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[2]_i_1__4
(.I0(Q[2]),
.I1(\Q_reg[31] [2]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[2]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[30]_i_1__4
(.I0(Q[30]),
.I1(\Q_reg[31] [30]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[30]));
LUT5 #(
.INIT(32'hE77181E8))
\Q[31]_i_2__2
(.I0(d_ff1_operation_out),
.I1(d_ff1_shift_region_flag_out[1]),
.I2(Q[31]),
.I3(d_ff1_shift_region_flag_out[0]),
.I4(\Q_reg[31] [31]),
.O(D[31]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[3]_i_1__4
(.I0(Q[3]),
.I1(\Q_reg[31] [3]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[3]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[4]_i_1__5
(.I0(Q[4]),
.I1(\Q_reg[31] [4]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[4]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[5]_i_1__4
(.I0(Q[5]),
.I1(\Q_reg[31] [5]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[5]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[6]_i_1__6
(.I0(Q[6]),
.I1(\Q_reg[31] [6]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[6]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[7]_i_1__4
(.I0(Q[7]),
.I1(\Q_reg[31] [7]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[7]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[8]_i_1__5
(.I0(Q[8]),
.I1(\Q_reg[31] [8]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[8]));
LUT5 #(
.INIT(32'hACCACAAC))
\Q[9]_i_1__5
(.I0(Q[9]),
.I1(\Q_reg[31] [9]),
.I2(d_ff1_shift_region_flag_out[0]),
.I3(d_ff1_shift_region_flag_out[1]),
.I4(d_ff1_operation_out),
.O(D[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\shift_region_flag[1] [0]),
.Q(d_ff1_shift_region_flag_out[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\shift_region_flag[1] [1]),
.Q(d_ff1_shift_region_flag_out[1]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized1
(Q,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized10
(Q,
E,
\Q_reg[31]_0 ,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]\Q_reg[31]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire [31:0]Q;
wire [31:0]\Q_reg[31]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized11
(Q,
E,
D,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized2
(S,
Q,
\Q_reg[26]_0 ,
\temp_reg[3] ,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [3:0]S;
output [31:0]Q;
output [3:0]\Q_reg[26]_0 ;
input [3:0]\temp_reg[3] ;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire [3:0]\Q_reg[26]_0 ;
wire [3:0]S;
wire [3:0]\temp_reg[3] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
LUT1 #(
.INIT(2'h1))
Y_carry__0_i_1
(.I0(Q[30]),
.O(S[3]));
LUT1 #(
.INIT(2'h1))
Y_carry__0_i_2
(.I0(Q[29]),
.O(S[2]));
LUT1 #(
.INIT(2'h1))
Y_carry__0_i_3
(.I0(Q[28]),
.O(S[1]));
LUT1 #(
.INIT(2'h1))
Y_carry__0_i_4
(.I0(Q[27]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
Y_carry_i_1
(.I0(Q[26]),
.I1(\temp_reg[3] [3]),
.O(\Q_reg[26]_0 [3]));
LUT2 #(
.INIT(4'h9))
Y_carry_i_2
(.I0(Q[25]),
.I1(\temp_reg[3] [2]),
.O(\Q_reg[26]_0 [2]));
LUT2 #(
.INIT(4'h9))
Y_carry_i_3
(.I0(Q[24]),
.I1(\temp_reg[3] [1]),
.O(\Q_reg[26]_0 [1]));
LUT2 #(
.INIT(4'h9))
Y_carry_i_4
(.I0(Q[23]),
.I1(\temp_reg[3] [0]),
.O(\Q_reg[26]_0 [0]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized3
(Q,
D,
\temp_reg[3] ,
E,
\temp_reg[3]_0 ,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
output [7:0]D;
input [3:0]\temp_reg[3] ;
input [0:0]E;
input [31:0]\temp_reg[3]_0 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [7:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
wire \Q[26]_i_2_n_0 ;
wire \Q[26]_i_3_n_0 ;
wire \Q[26]_i_4_n_0 ;
wire \Q[26]_i_5_n_0 ;
wire \Q[30]_i_2_n_0 ;
wire \Q[30]_i_3_n_0 ;
wire \Q[30]_i_4_n_0 ;
wire \Q[30]_i_5_n_0 ;
wire \Q_reg[26]_i_1_n_0 ;
wire \Q_reg[26]_i_1_n_1 ;
wire \Q_reg[26]_i_1_n_2 ;
wire \Q_reg[26]_i_1_n_3 ;
wire \Q_reg[30]_i_1_n_1 ;
wire \Q_reg[30]_i_1_n_2 ;
wire \Q_reg[30]_i_1_n_3 ;
wire [3:0]\temp_reg[3] ;
wire [31:0]\temp_reg[3]_0 ;
wire [3:3]\NLW_Q_reg[30]_i_1_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h9))
\Q[26]_i_2
(.I0(Q[26]),
.I1(\temp_reg[3] [3]),
.O(\Q[26]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[26]_i_3
(.I0(Q[25]),
.I1(\temp_reg[3] [2]),
.O(\Q[26]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[26]_i_4
(.I0(Q[24]),
.I1(\temp_reg[3] [1]),
.O(\Q[26]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[26]_i_5
(.I0(Q[23]),
.I1(\temp_reg[3] [0]),
.O(\Q[26]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[30]_i_2
(.I0(Q[30]),
.O(\Q[30]_i_2_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[30]_i_3
(.I0(Q[29]),
.O(\Q[30]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[30]_i_4
(.I0(Q[28]),
.O(\Q[30]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[30]_i_5
(.I0(Q[27]),
.O(\Q[30]_i_5_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [26]),
.Q(Q[26]));
CARRY4 \Q_reg[26]_i_1
(.CI(1'b0),
.CO({\Q_reg[26]_i_1_n_0 ,\Q_reg[26]_i_1_n_1 ,\Q_reg[26]_i_1_n_2 ,\Q_reg[26]_i_1_n_3 }),
.CYINIT(1'b1),
.DI(Q[26:23]),
.O(D[3:0]),
.S({\Q[26]_i_2_n_0 ,\Q[26]_i_3_n_0 ,\Q[26]_i_4_n_0 ,\Q[26]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [30]),
.Q(Q[30]));
CARRY4 \Q_reg[30]_i_1
(.CI(\Q_reg[26]_i_1_n_0 ),
.CO({\NLW_Q_reg[30]_i_1_CO_UNCONNECTED [3],\Q_reg[30]_i_1_n_1 ,\Q_reg[30]_i_1_n_2 ,\Q_reg[30]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,Q[29:27]}),
.O(D[7:4]),
.S({\Q[30]_i_2_n_0 ,\Q[30]_i_3_n_0 ,\Q[30]_i_4_n_0 ,\Q[30]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(\temp_reg[3]_0 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized4
(Q,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized5
(Q,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized6
(Q,
\FSM_sequential_state_reg_reg[2] ,
D,
CLK,
\FSM_sequential_state_reg_reg[1] );
output [31:0]Q;
input [0:0]\FSM_sequential_state_reg_reg[2] ;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
wire CLK;
wire [31:0]D;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [0:0]\FSM_sequential_state_reg_reg[2] ;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized7
(Q,
E,
CLK,
\FSM_sequential_state_reg_reg[1] ,
D);
output [20:0]Q;
input [0:0]E;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[1] ;
input [19:0]D;
wire CLK;
wire [19:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[1] ;
wire [20:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[9]),
.Q(Q[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(1'b1),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[1] ),
.D(D[6]),
.Q(Q[6]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized8
(Q,
E,
\Q_reg[31]_0 ,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]\Q_reg[31]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire [31:0]Q;
wire [31:0]\Q_reg[31]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "d_ff_en" *)
module d_ff_en__parameterized9
(Q,
E,
\Q_reg[31]_0 ,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]\Q_reg[31]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire [31:0]Q;
wire [31:0]\Q_reg[31]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31]_0 [9]),
.Q(Q[9]));
endmodule
module sgn_result
(D,
\Q_reg[30] ,
Q,
intAS,
CO,
\Q_reg[31] );
output [0:0]D;
input [0:0]\Q_reg[30] ;
input [0:0]Q;
input intAS;
input [0:0]CO;
input [0:0]\Q_reg[31] ;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]Q;
wire [0:0]\Q_reg[30] ;
wire [0:0]\Q_reg[31] ;
wire intAS;
LUT5 #(
.INIT(32'hFF3C0014))
sgn_result_o
(.I0(\Q_reg[30] ),
.I1(Q),
.I2(intAS),
.I3(CO),
.I4(\Q_reg[31] ),
.O(D));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_16_V
`define SKY130_FD_SC_HVL__BUF_16_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_16_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41O_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A41O_BEHAVIORAL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a41o (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41O_BEHAVIORAL_V |
/*
* cpu. - five stage MIPS CPU.
*
* Many variables (wires) pass through several stages.
* The naming convention used for each stage is
* accomplished by appending the stage number (_s<num>).
* For example the variable named "data" which is
* in stage 2 and stage 3 would be named as follows.
*
* wire data_s2;
* wire data_s3;
*
* If the stage number is omitted it is assumed to
* be at the stage at which the variable is first
* established.
*/
`include "regr.v"
`include "im.v"
`include "regm.v"
`include "control.v"
`include "alu.v"
`include "alu_control.v"
`include "dm.v"
`ifndef DEBUG_CPU_STAGES
`define DEBUG_CPU_STAGES 0
`endif
module cpu(
input wire clk);
parameter NMEM = 20; // number in instruction memory
parameter IM_DATA = "im_data.txt";
// {{{ diagnostic outputs
initial begin
if (`DEBUG_CPU_STAGES) begin
$display("if_pc, if_instr, id_regrs, id_regrt, ex_alua, ex_alub, ex_aluctl, mem_memdata, mem_memread, mem_memwrite, wb_regdata, wb_regwrite");
$monitor("%x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x",
pc, /* if_pc */
inst, /* if_instr */
data1, /* id_regrs */
data2, /* id_regrt */
data1_s3, /* data1_s3 */
alusrc_data2, /* alusrc_data2 */
aluctl, /* ex_aluctl */
data2_s4, /* mem_memdata */
memread_s4, /* mem_memread */
memwrite_s4, /* mem_memwrite */
wrdata_s5, /* wb_regdata */
regwrite_s5 /* wb_regwrite */
);
end
end
// }}}
// {{{ flush control
reg flush_s1, flush_s2, flush_s3;
always @(*) begin
flush_s1 <= 1'b0;
flush_s2 <= 1'b0;
flush_s3 <= 1'b0;
if (pcsrc) begin
flush_s1 <= 1'b1;
flush_s2 <= 1'b1;
flush_s3 <= 1'b1;
end
end
// }}}
// {{{ stage 1, IF (fetch)
reg [31:0] pc;
initial begin
pc <= 32'd0;
end
wire [31:0] pc4; // PC + 4
assign pc4 = pc + 4;
always @(posedge clk) begin
if (stall_s1_s2)
pc <= pc;
else if (pcsrc == 1'b1)
pc <= baddr_s4;
else
pc <= pc4;
end
// pass PC + 4 to stage 2
wire [31:0] pc4_s2;
regr #(.N(32)) regr_pc4_s2(.clk(clk),
.hold(stall_s1_s2), .clear(flush_s1),
.in(pc4), .out(pc4_s2));
// instruction memory
wire [31:0] inst;
wire [31:0] inst_s2;
im #(.NMEM(NMEM), .IM_DATA(IM_DATA))
im1(.clk(clk), .addr(pc), .data(inst));
regr #(.N(32)) regr_im_s2(.clk(clk),
.hold(stall_s1_s2), .clear(flush_s1),
.in(inst), .out(inst_s2));
// }}}
// {{{ stage 2, ID (decode)
// decode instruction
wire [5:0] opcode;
wire [4:0] rs;
wire [4:0] rt;
wire [4:0] rd;
wire [15:0] imm;
wire [4:0] shamt;
wire [25:0] jimm; // jump, immediate
wire [31:0] seimm; // sign extended immediate
//
assign opcode = inst_s2[31:26];
assign rs = inst_s2[25:21];
assign rt = inst_s2[20:16];
assign rd = inst_s2[15:11];
assign imm = inst_s2[15:0];
assign shamt = inst_s2[10:6];
assign jimm = inst_s2[25:0];
assign seimm = {{16{inst_s2[15]}}, inst_s2[15:0]};
// register memory
wire [31:0] data1, data2;
regm regm1(.clk(clk), .read1(rs), .read2(rt),
.data1(data1), .data2(data2),
.regwrite(regwrite_s5), .wrreg(wrreg_s5),
.wrdata(wrdata_s5));
// pass rs to stage 3 (for forwarding)
wire [4:0] rs_s3;
regr #(.N(5)) regr_s2_rs(.clk(clk), .clear(1'b0), .hold(stall_s1_s2),
.in(rs), .out(rs_s3));
// transfer register data to stage 3
wire [31:0] data1_s3, data2_s3;
regr #(.N(64)) reg_s2_mem(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2),
.in({data1, data2}),
.out({data1_s3, data2_s3}));
// transfer seimm, rt, and rd to stage 3
wire [31:0] seimm_s3;
wire [4:0] rt_s3;
wire [4:0] rd_s3;
regr #(.N(32)) reg_s2_seimm(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2),
.in(seimm), .out(seimm_s3));
regr #(.N(10)) reg_s2_rt_rd(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2),
.in({rt, rd}), .out({rt_s3, rd_s3}));
// transfer PC + 4 to stage 3
wire [31:0] pc4_s3;
regr #(.N(32)) reg_pc4_s2(.clk(clk), .clear(1'b0), .hold(stall_s1_s2),
.in(pc4_s2), .out(pc4_s3));
// control (opcode -> ...)
wire regdst;
wire [1:0] branch_s2;
wire memread;
wire memwrite;
wire memtoreg;
wire [1:0] aluop;
wire regwrite;
wire alusrc;
//
control ctl1(.opcode(opcode), .regdst(regdst),
.branch(branch_s2), .memread(memread),
.memtoreg(memtoreg), .aluop(aluop),
.memwrite(memwrite), .alusrc(alusrc),
.regwrite(regwrite));
// shift left, seimm
wire [31:0] seimm_sl2;
assign seimm_sl2 = {seimm[29:0], 2'b0}; // shift left 2 bits
// branch address
wire [31:0] baddr_s2;
assign baddr_s2 = pc4_s2 + seimm_sl2;
// transfer the control signals to stage 3
wire regdst_s3;
wire memread_s3;
wire memwrite_s3;
wire memtoreg_s3;
wire [1:0] aluop_s3;
wire regwrite_s3;
wire alusrc_s3;
// A bubble is inserted by setting all the control signals
// to zero (stall_s1_s2).
regr #(.N(8)) reg_s2_control(.clk(clk), .clear(stall_s1_s2), .hold(1'b0),
.in({regdst, memread, memwrite,
memtoreg, aluop, regwrite, alusrc}),
.out({regdst_s3, memread_s3, memwrite_s3,
memtoreg_s3, aluop_s3, regwrite_s3, alusrc_s3}));
wire [1:0] branch_s3;
regr #(.N(2)) branch_s2_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in(branch_s2), .out(branch_s3));
wire [31:0] baddr_s3;
regr #(.N(32)) baddr_s2_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in(baddr_s2), .out(baddr_s3));
// }}}
// {{{ stage 3, EX (execute)
// pass through some control signals to stage 4
wire regwrite_s4;
wire memtoreg_s4;
wire memread_s4;
wire memwrite_s4;
regr #(.N(4)) reg_s3(.clk(clk), .clear(flush_s2), .hold(1'b0),
.in({regwrite_s3, memtoreg_s3, memread_s3,
memwrite_s3}),
.out({regwrite_s4, memtoreg_s4, memread_s4,
memwrite_s4}));
// ALU
// second ALU input can come from an immediate value or data
wire [31:0] alusrc_data2;
assign alusrc_data2 = (alusrc_s3) ? seimm_s3 : fw_data2_s3;
// ALU control
wire [3:0] aluctl;
wire [5:0] funct;
assign funct = seimm_s3[5:0];
alu_control alu_ctl1(.funct(funct), .aluop(aluop_s3), .aluctl(aluctl));
// ALU
wire [31:0] alurslt;
reg [31:0] fw_data1_s3;
always @(*)
case (forward_a)
2'd1: fw_data1_s3 = alurslt_s4;
2'd2: fw_data1_s3 = wrdata_s5;
default: fw_data1_s3 = data1_s3;
endcase
wire zero_s3;
alu alu1(.ctl(aluctl), .a(fw_data1_s3), .b(alusrc_data2), .out(alurslt),
.zero(zero_s3));
wire zero_s4;
regr #(.N(1)) reg_zero_s3_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(zero_s3), .out(zero_s4));
// pass ALU result and zero to stage 4
wire [31:0] alurslt_s4;
regr #(.N(32)) reg_alurslt(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in({alurslt}),
.out({alurslt_s4}));
// pass data2 to stage 4
wire [31:0] data2_s4;
reg [31:0] fw_data2_s3;
always @(*)
case (forward_b)
2'd1: fw_data2_s3 = alurslt_s4;
2'd2: fw_data2_s3 = wrdata_s5;
default: fw_data2_s3 = data2_s3;
endcase
regr #(.N(32)) reg_data2_s3(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(fw_data2_s3), .out(data2_s4));
// write register
wire [4:0] wrreg;
wire [4:0] wrreg_s4;
assign wrreg = (regdst_s3) ? rd_s3 : rt_s3;
// pass to stage 4
regr #(.N(5)) reg_wrreg(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(wrreg), .out(wrreg_s4));
wire [1:0] branch_s4;
regr #(.N(2)) branch_s3_s4(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(branch_s3), .out(branch_s4));
wire [31:0] baddr_s4;
regr #(.N(32)) baddr_s3_s4(.clk(clk), .clear(flush_s3), .hold(1'b0),
.in(baddr_s3), .out(baddr_s4));
// }}}
// {{{ stage 4, MEM (memory)
// pass regwrite and memtoreg to stage 5
wire regwrite_s5;
wire memtoreg_s5;
regr #(.N(2)) reg_regwrite_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in({regwrite_s4, memtoreg_s4}),
.out({regwrite_s5, memtoreg_s5}));
// data memory
wire [31:0] rdata;
dm dm1(.clk(clk), .addr(alurslt_s4[8:2]), .rd(memread_s4), .wr(memwrite_s4),
.wdata(data2_s4), .rdata(rdata));
// pass read data to stage 5
wire [31:0] rdata_s5;
regr #(.N(32)) reg_rdata_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(rdata),
.out(rdata_s5));
// pass alurslt to stage 5
wire [31:0] alurslt_s5;
regr #(.N(32)) reg_alurslt_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(alurslt_s4),
.out(alurslt_s5));
// pass wrreg to stage 5
wire [4:0] wrreg_s5;
regr #(.N(5)) reg_wrreg_s4(.clk(clk), .clear(1'b0), .hold(1'b0),
.in(wrreg_s4),
.out(wrreg_s5));
// branch
reg pcsrc;
always @(*) begin
case (1'b1)
branch_s4[`BRANCH_BEQ]: pcsrc <= zero_s4;
branch_s4[`BRANCH_BNE]: pcsrc <= ~(zero_s4);
default: pcsrc <= 1'b0;
endcase
end
// }}}
// {{{ stage 5, WB (write back)
wire [31:0] wrdata_s5;
assign wrdata_s5 = (memtoreg_s5 == 1'b1) ? rdata_s5 : alurslt_s5;
// }}}
// {{{ forwarding
// stage 3 (MEM) -> stage 2 (EX)
// stage 4 (WB) -> stage 2 (EX)
reg [1:0] forward_a;
reg [1:0] forward_b;
always @(*) begin
// If the previous instruction (stage 4) would write,
// and it is a value we want to read (stage 3), forward it.
// data1 input to ALU
if ((regwrite_s4 == 1'b1) && (wrreg_s4 == rs_s3)) begin
forward_a <= 2'd1; // stage 4
end else if ((regwrite_s5 == 1'b1) && (wrreg_s5 == rs_s3)) begin
forward_a <= 2'd2; // stage 5
end else
forward_a <= 2'd0; // no forwarding
// data2 input to ALU
if ((regwrite_s4 == 1'b1) & (wrreg_s4 == rt_s3)) begin
forward_b <= 2'd1; // stage 5
end else if ((regwrite_s5 == 1'b1) && (wrreg_s5 == rt_s3)) begin
forward_b <= 2'd2; // stage 5
end else
forward_b <= 2'd0; // no forwarding
end
// }}}
// {{{ load use data hazard detection, signal stall
/* If an operation in stage 4 (MEM) loads from memory (e.g. lw)
* and the operation in stage 3 (EX) depends on this value,
* a stall must be performed. The memory read cannot
* be forwarded because memory access is too slow. It can
* be forwarded from stage 5 (WB) after a stall.
*
* lw $1, 16($10) ; I-type, rt_s3 = $1, memread_s3 = 1
* sw $1, 32($12) ; I-type, rt_s2 = $1, memread_s2 = 0
*
* lw $1, 16($3) ; I-type, rt_s3 = $1, memread_s3 = 1
* sw $2, 32($1) ; I-type, rt_s2 = $2, rs_s2 = $1, memread_s2 = 0
*
* lw $1, 16($3) ; I-type, rt_s3 = $1, memread_s3 = 1
* add $2, $1, $1 ; R-type, rs_s2 = $1, rt_s2 = $1, memread_s2 = 0
*/
reg stall_s1_s2;
always @(*) begin
if (memread_s3 == 1'b1 && ((rt == rt_s3) || (rs == rt_s3)) ) begin
stall_s1_s2 <= 1'b1; // perform a stall
end else
stall_s1_s2 <= 1'b0; // no stall
end
// }}}
endmodule
// vim:foldmethod=marker
|
module top (
fpga_clk_50,
fpga_reset_n,
fpga_led_output,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
hps_usb1_D0,
hps_usb1_D1,
hps_usb1_D2,
hps_usb1_D3,
hps_usb1_D4,
hps_usb1_D5,
hps_usb1_D6,
hps_usb1_D7,
hps_usb1_CLK,
hps_usb1_STP,
hps_usb1_DIR,
hps_usb1_NXT,
emac_mdio,
emac_mdc,
emac_tx_ctl,
emac_tx_clk,
emac_txd,
emac_rx_ctl,
emac_rx_clk,
emac_rxd,
sd_cmd,
sd_clk,
sd_d,
uart_rx,
uart_tx,
led,
i2c_sda,
i2c_scl,
///////// VGA /////////
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS
);
///////// VGA /////////
output wire [7:0] VGA_B;
output wire VGA_BLANK_N;
output wire VGA_CLK;
output wire [7:0] VGA_G;
output wire VGA_HS;
output wire [7:0] VGA_R;
output wire VGA_SYNC_N;
output wire VGA_VS;
input wire fpga_clk_50;
input wire fpga_reset_n;
output wire [3:0] fpga_led_output;
output wire [14:0] memory_mem_a;
output wire [2:0] memory_mem_ba;
output wire memory_mem_ck;
output wire memory_mem_ck_n;
output wire memory_mem_cke;
output wire memory_mem_cs_n;
output wire memory_mem_ras_n;
output wire memory_mem_cas_n;
output wire memory_mem_we_n;
output wire memory_mem_reset_n;
inout wire [31:0] memory_mem_dq;
inout wire [3:0] memory_mem_dqs;
inout wire [3:0] memory_mem_dqs_n;
output wire memory_mem_odt;
output wire [3:0] memory_mem_dm;
input wire memory_oct_rzqin;
inout wire emac_mdio;
output wire emac_mdc;
output wire emac_tx_ctl;
output wire emac_tx_clk;
output wire [3:0] emac_txd;
input wire emac_rx_ctl;
input wire emac_rx_clk;
input wire [3:0] emac_rxd;
inout wire hps_usb1_D0;
inout wire hps_usb1_D1;
inout wire hps_usb1_D2;
inout wire hps_usb1_D3;
inout wire hps_usb1_D4;
inout wire hps_usb1_D5;
inout wire hps_usb1_D6;
inout wire hps_usb1_D7;
input wire hps_usb1_CLK;
output wire hps_usb1_STP;
input wire hps_usb1_DIR;
input wire hps_usb1_NXT;
inout wire sd_cmd;
output wire sd_clk;
inout wire [3:0] sd_d;
input wire uart_rx;
output wire uart_tx;
inout wire led;
inout wire i2c_scl;
inout wire i2c_sda;
//=======================================================
// REG/WIRE declarations
//=======================================================
// internal wires and registers declaration
wire clk_65;
wire clk_130;
wire [7:0] vid_r,vid_g,vid_b;
wire vid_v_sync ;
wire vid_h_sync ;
wire vid_datavalid;
wire [29:0] fpga_internal_led;
wire kernel_clk;
//=======================================================
// Structural coding
//=======================================================
assign VGA_BLANK_N = 1'b1;
assign VGA_SYNC_N = 1'b0;
assign VGA_CLK = clk_65;
assign {VGA_B,VGA_G,VGA_R} = {vid_b,vid_g,vid_r};
assign VGA_VS = vid_v_sync;
assign VGA_HS = vid_h_sync;
vga_pll vga_pll_inst(
.refclk(fpga_clk_50), // refclk.clk
.rst(1'b0), // reset.reset
.outclk_0(clk_65), // outclk0.clk
.outclk_1(clk_130), // outclk1.clk
.locked() // locked.export
);
system the_system (
.reset_50_reset_n (fpga_reset_n),
.clk_50_clk (fpga_clk_50),
.kernel_clk_clk (kernel_clk),
.memory_mem_a (memory_mem_a),
.memory_mem_ba (memory_mem_ba),
.memory_mem_ck (memory_mem_ck),
.memory_mem_ck_n (memory_mem_ck_n),
.memory_mem_cke (memory_mem_cke),
.memory_mem_cs_n (memory_mem_cs_n),
.memory_mem_ras_n (memory_mem_ras_n),
.memory_mem_cas_n (memory_mem_cas_n),
.memory_mem_we_n (memory_mem_we_n),
.memory_mem_reset_n (memory_mem_reset_n),
.memory_mem_dq (memory_mem_dq),
.memory_mem_dqs (memory_mem_dqs),
.memory_mem_dqs_n (memory_mem_dqs_n),
.memory_mem_odt (memory_mem_odt),
.memory_mem_dm (memory_mem_dm),
.memory_oct_rzqin (memory_oct_rzqin),
.peripheral_hps_io_emac1_inst_MDIO (emac_mdio),
.peripheral_hps_io_emac1_inst_MDC (emac_mdc),
.peripheral_hps_io_emac1_inst_TX_CLK (emac_tx_clk),
.peripheral_hps_io_emac1_inst_TX_CTL (emac_tx_ctl),
.peripheral_hps_io_emac1_inst_TXD0 (emac_txd[0]),
.peripheral_hps_io_emac1_inst_TXD1 (emac_txd[1]),
.peripheral_hps_io_emac1_inst_TXD2 (emac_txd[2]),
.peripheral_hps_io_emac1_inst_TXD3 (emac_txd[3]),
.peripheral_hps_io_emac1_inst_RX_CLK (emac_rx_clk),
.peripheral_hps_io_emac1_inst_RX_CTL (emac_rx_ctl),
.peripheral_hps_io_emac1_inst_RXD0 (emac_rxd[0]),
.peripheral_hps_io_emac1_inst_RXD1 (emac_rxd[1]),
.peripheral_hps_io_emac1_inst_RXD2 (emac_rxd[2]),
.peripheral_hps_io_emac1_inst_RXD3 (emac_rxd[3]),
.peripheral_hps_io_sdio_inst_CMD (sd_cmd),
.peripheral_hps_io_sdio_inst_CLK (sd_clk),
.peripheral_hps_io_sdio_inst_D0 (sd_d[0]),
.peripheral_hps_io_sdio_inst_D1 (sd_d[1]),
.peripheral_hps_io_sdio_inst_D2 (sd_d[2]),
.peripheral_hps_io_sdio_inst_D3 (sd_d[3]),
.peripheral_hps_io_uart0_inst_RX (uart_rx),
.peripheral_hps_io_uart0_inst_TX (uart_tx),
.peripheral_hps_io_gpio_inst_GPIO53 (led),
.peripheral_hps_io_i2c1_inst_SDA (i2c_sda),
.peripheral_hps_io_i2c1_inst_SCL (i2c_scl),
//itc
.acl_iface_clock_130_clk (clk_130),
.acl_iface_alt_vip_itc_0_clocked_video_vid_clk (clk_65), // alt_vip_itc_0_clocked_video.vid_clk
.acl_iface_alt_vip_itc_0_clocked_video_vid_data ({vid_r,vid_g,vid_b}), // .vid_data
.acl_iface_alt_vip_itc_0_clocked_video_underflow (), // .underflow
.acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid (vid_datavalid), // .vid_datavalid
.acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync (vid_v_sync), // .vid_v_sync
.acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync (vid_h_sync), // .vid_h_sync
.acl_iface_alt_vip_itc_0_clocked_video_vid_f (), // .vid_f
.acl_iface_alt_vip_itc_0_clocked_video_vid_h (), // .vid_h
.acl_iface_alt_vip_itc_0_clocked_video_vid_v (),
.peripheral_hps_io_usb1_inst_D0 (hps_usb1_D0), // .hps_io_usb1_inst_D0
.peripheral_hps_io_usb1_inst_D1 (hps_usb1_D1), // .hps_io_usb1_inst_D1
.peripheral_hps_io_usb1_inst_D2 (hps_usb1_D2), // .hps_io_usb1_inst_D2
.peripheral_hps_io_usb1_inst_D3 (hps_usb1_D3), // .hps_io_usb1_inst_D3
.peripheral_hps_io_usb1_inst_D4 (hps_usb1_D4), // .hps_io_usb1_inst_D4
.peripheral_hps_io_usb1_inst_D5 (hps_usb1_D5), // .hps_io_usb1_inst_D5
.peripheral_hps_io_usb1_inst_D6 (hps_usb1_D6), // .hps_io_usb1_inst_D6
.peripheral_hps_io_usb1_inst_D7 (hps_usb1_D7), // .hps_io_usb1_inst_D7
.peripheral_hps_io_usb1_inst_CLK (hps_usb1_CLK), // .hps_io_usb1_inst_CLK
.peripheral_hps_io_usb1_inst_STP (hps_usb1_STP), // .hps_io_usb1_inst_STP
.peripheral_hps_io_usb1_inst_DIR (hps_usb1_DIR), // .hps_io_usb1_inst_DIR
.peripheral_hps_io_usb1_inst_NXT (hps_usb1_NXT) // .hps_io_usb1_inst_NXT
);
// module for visualizing the kernel clock with 4 LEDs
async_counter_30 AC30 (
.clk (kernel_clk),
.count (fpga_internal_led)
);
assign fpga_led_output[3:0] = ~fpga_internal_led[29:26];
endmodule
module async_counter_30(clk, count);
input clk;
output [29:0] count;
reg [14:0] count_a;
reg [14:0] count_b;
initial count_a = 15'b0;
initial count_b = 15'b0;
always @(negedge clk)
count_a <= count_a + 1'b1;
always @(negedge count_a[14])
count_b <= count_b + 1'b1;
assign count = {count_b, count_a};
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: COMMAND_PAGE.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module COMMAND_PAGE (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [15:0] data;
input [7:0] rdaddress;
input [8:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
// Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL "wraddress[8..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//================================================================--
// Design Unit : sn7402 (behaviour)
//
// File Name : behaviour.v
//
// Purpose : model of TTL SN7402 quad and IC
//
// Author : Daniel Guenther, Vancouver Island University
//
// Environmant : Icarus
//-------------------------------------------------------------------
// Revision List
// Version Author Date Changes
// 1.0 Daniel Guenther Nov 10 2016 filled in wire connections
//================================================================--
module sn7402 (P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14);
output reg P1, P4, P10, P13;
input P2, P3, P5, P6, P8, P9, P11, P12, P7, P14;
always @(P2, P3, P7, P14) begin
if ((P14 == 1'b 1) && (P7 == 1'b 0)) begin
P1 = ~(P2 | P3);
end
end
always @(P5, P6, P7, P14) begin
if ((P14 == 1'b 1) && (P7 == 1'b 0)) begin
P4 = ~(P5 | P6);
end
end
always @(P8, P9, P7, P14) begin
if ((P14 == 1'b 1) && (P7 == 1'b 0)) begin
P10 = ~(P8 | P9);
end
end
always @(P11, P12, P7, P14) begin
if ((P14 == 1'b 1) && (P7 == 1'b 0)) begin
P13 = ~(P11 | P12);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_POWER_LVC_WPAD_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_POWER_LVC_WPAD_PP_SYMBOL_V
/**
* top_power_lvc_wpad: A power pad with an ESD low-voltage clamp.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_power_lvc_wpad (
//# {{data|Data Signals}}
inout P_PAD ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
//# {{power|Power}}
inout BDY2_B2B ,
inout VSWITCH ,
inout P_CORE ,
inout VCCD ,
inout VCCHIB ,
inout VDDA ,
inout VDDIO ,
inout VDDIO_Q ,
inout DRN_LVC1 ,
inout DRN_LVC2 ,
inout OGC_LVC ,
inout SRC_BDY_LVC1,
inout SRC_BDY_LVC2,
inout VSSA ,
inout VSSD ,
inout VSSIO ,
inout VSSIO_Q
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_POWER_LVC_WPAD_PP_SYMBOL_V
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 100ps/100ps
module MultiplexerTest;
wire [2:0] w_data;
wire w_error;
reg [3:0] r_select;
reg r_disable_error_check;
reg r_error;
Multiplexer4 #(.width(3)) mux(
.i_data0 (3'b001 ),
.i_data1 (3'b010 ),
.i_data2 (3'b011 ),
.i_data3 (3'b100 ),
.i_select0(r_select[0]),
.i_select1(r_select[1]),
.i_select2(r_select[2]),
.i_select3(r_select[3]),
.o_data (w_data ),
.o_error (w_error ));
always @ (w_error or r_error) begin
if (w_error & !r_disable_error_check) begin
$display("unexpected error");
end
if (r_error) begin
$display("wrong data is selected");
end
end
initial begin
//$dumpfile("Multiplexer.vcd");
//$dumpvars(0, mux);
r_disable_error_check <= 1'b0;
r_error <= 1'b0;
r_select <= 4'b0001;
#1
r_error <= w_data != 3'b001;
#1
r_select <= 4'b0010;
#1
r_error <= w_data != 3'b010;
#1
r_select <= 4'b0100;
#1
r_error <= w_data != 3'b011;
#1
r_select <= 4'b1000;
#1
r_error <= w_data != 3'b100;
#1
r_disable_error_check <= 1'b1;
#1
r_select <= 4'b0011;
#1
r_error <= w_error != 1'b1;
#1
r_select <= 4'b0000;
#1
r_error <= w_error != 1'b1;
#1
$finish;
end
endmodule // MultiplexerTest
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22O_2_V
`define SKY130_FD_SC_HD__A22O_2_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a22o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a22o_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22O_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__EDFXTP_PP_BLACKBOX_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXTP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_LP_V
`define SKY130_FD_SC_LP__A41O_LP_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41o with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a41o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41o_lp (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41o_lp (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_LP_V
|
`include "defines.v"
module ex(
input wire rst,
//Ë͵½Ö´Ðн׶εÄÐÅÏ¢
input wire[`AluOpBus] aluop_i,
input wire[`AluSelBus] alusel_i,
input wire[`RegBus] reg1_i,
input wire[`RegBus] reg2_i,
input wire[`RegAddrBus] wd_i,
input wire wreg_i,
input wire[`RegBus] inst_i,
input wire[31:0] excepttype_i,
input wire[`RegBus] current_inst_address_i,
//HI¡¢LO¼Ä´æÆ÷µÄÖµ
input wire[`RegBus] hi_i,
input wire[`RegBus] lo_i,
//»Øд½×¶ÎµÄÖ¸ÁîÊÇ·ñҪдHI¡¢LO£¬ÓÃÓÚ¼ì²âHI¡¢LOµÄÊý¾ÝÏà¹Ø
input wire[`RegBus] wb_hi_i,
input wire[`RegBus] wb_lo_i,
input wire wb_whilo_i,
//·Ã´æ½×¶ÎµÄÖ¸ÁîÊÇ·ñҪдHI¡¢LO£¬ÓÃÓÚ¼ì²âHI¡¢LOµÄÊý¾ÝÏà¹Ø
input wire[`RegBus] mem_hi_i,
input wire[`RegBus] mem_lo_i,
input wire mem_whilo_i,
input wire[`DoubleRegBus] hilo_temp_i,
input wire[1:0] cnt_i,
//Óë³ý·¨Ä£¿éÏàÁ¬
input wire[`DoubleRegBus] div_result_i,
input wire div_ready_i,
//ÊÇ·ñתÒÆ¡¢ÒÔ¼°link address
input wire[`RegBus] link_address_i,
input wire is_in_delayslot_i,
//·Ã´æ½×¶ÎµÄÖ¸ÁîÊÇ·ñҪдCP0£¬ÓÃÀ´¼ì²âÊý¾ÝÏà¹Ø
input wire mem_cp0_reg_we,
input wire[4:0] mem_cp0_reg_write_addr,
input wire[`RegBus] mem_cp0_reg_data,
//»Øд½×¶ÎµÄÖ¸ÁîÊÇ·ñҪдCP0£¬ÓÃÀ´¼ì²âÊý¾ÝÏà¹Ø
input wire wb_cp0_reg_we,
input wire[4:0] wb_cp0_reg_write_addr,
input wire[`RegBus] wb_cp0_reg_data,
//ÓëCP0ÏàÁ¬£¬¶ÁÈ¡ÆäÖÐCP0¼Ä´æÆ÷µÄÖµ
input wire[`RegBus] cp0_reg_data_i,
output reg[4:0] cp0_reg_read_addr_o,
//ÏòÏÂÒ»Á÷Ë®¼¶´«µÝ£¬ÓÃÓÚдCP0ÖеļĴæÆ÷
output reg cp0_reg_we_o,
output reg[4:0] cp0_reg_write_addr_o,
output reg[`RegBus] cp0_reg_data_o,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output reg[`RegBus] wdata_o,
output reg[`RegBus] hi_o,
output reg[`RegBus] lo_o,
output reg whilo_o,
output reg[`DoubleRegBus] hilo_temp_o,
output reg[1:0] cnt_o,
output reg[`RegBus] div_opdata1_o,
output reg[`RegBus] div_opdata2_o,
output reg div_start_o,
output reg signed_div_o,
//ÏÂÃæÐÂÔöµÄ¼¸¸öÊä³öÊÇΪ¼ÓÔØ¡¢´æ´¢Ö¸Áî×¼±¸µÄ
output wire[`AluOpBus] aluop_o,
output wire[`RegBus] mem_addr_o,
output wire[`RegBus] reg2_o,
output wire[31:0] excepttype_o,
output wire is_in_delayslot_o,
output wire[`RegBus] current_inst_address_o,
output reg stallreq
);
reg[`RegBus] logicout;
reg[`RegBus] shiftres;
reg[`RegBus] moveres;
reg[`RegBus] arithmeticres;
reg[`DoubleRegBus] mulres;
reg[`RegBus] HI;
reg[`RegBus] LO;
wire[`RegBus] reg2_i_mux;
wire[`RegBus] reg1_i_not;
wire[`RegBus] result_sum;
wire ov_sum;
wire reg1_eq_reg2;
wire reg1_lt_reg2;
wire[`RegBus] opdata1_mult;
wire[`RegBus] opdata2_mult;
wire[`DoubleRegBus] hilo_temp;
reg[`DoubleRegBus] hilo_temp1;
reg stallreq_for_madd_msub;
reg stallreq_for_div;
reg trapassert;
reg breassert;
//aluop_o´«µÝµ½·Ã´æ½×¶Î£¬ÓÃÓÚ¼ÓÔØ¡¢´æ´¢Ö¸Áî
assign aluop_o = aluop_i;
//mem_addr´«µÝµ½·Ã´æ½×¶Î£¬ÊǼÓÔØ¡¢´æ´¢Ö¸Áî¶ÔÓ¦µÄ´æ´¢Æ÷µØÖ·
assign mem_addr_o = reg1_i + {{16{inst_i[15]}},inst_i[15:0]};
//½«Á½¸ö²Ù×÷ÊýÒ²´«µÝµ½·Ã´æ½×¶Î£¬Ò²ÊÇΪ¼ÇÔØ¡¢´æ´¢Ö¸Áî×¼±¸µÄ
assign reg2_o = reg2_i;
assign excepttype_o = {excepttype_i[31:12],breassert,trapassert,excepttype_i[9:8],8'h00};
assign is_in_delayslot_o = is_in_delayslot_i;
assign current_inst_address_o = current_inst_address_i;
always @ (*) begin
if(rst == `RstEnable) begin
logicout <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_OR_OP: begin
logicout <= reg1_i | reg2_i;
end
`EXE_AND_OP: begin
logicout <= reg1_i & reg2_i;
end
`EXE_NOR_OP: begin
logicout <= ~(reg1_i |reg2_i);
end
`EXE_XOR_OP: begin
logicout <= reg1_i ^ reg2_i;
end
default: begin
logicout <= `ZeroWord;
end
endcase
end //if
end //always
always @ (*) begin
if(rst == `RstEnable) begin
shiftres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLL_OP: begin
shiftres <= reg2_i << reg1_i[4:0] ;
end
`EXE_SRL_OP: begin
shiftres <= reg2_i >> reg1_i[4:0];
end
`EXE_SRA_OP: begin
shiftres <= ({32{reg2_i[31]}} << (6'd32-{1'b0, reg1_i[4:0]}))
| reg2_i >> reg1_i[4:0];
end
default: begin
shiftres <= `ZeroWord;
end
endcase
end //if
end //always
assign reg2_i_mux = ((aluop_i == `EXE_SUB_OP) || (aluop_i == `EXE_SUBU_OP) ||
(aluop_i == `EXE_SLT_OP)|| (aluop_i == `EXE_TLT_OP) ||
(aluop_i == `EXE_TLTI_OP) || (aluop_i == `EXE_TGE_OP) ||
(aluop_i == `EXE_TGEI_OP))
? (~reg2_i)+1 : reg2_i;
assign result_sum = reg1_i + reg2_i_mux;
/*assign ov_sum = ((!reg1_i[31] && !reg2_i_mux[31]) && result_sum[31]) ||
((reg1_i[31] && reg2_i_mux[31]) && (!result_sum[31])); */
assign reg1_lt_reg2 = ((aluop_i == `EXE_SLT_OP) || (aluop_i == `EXE_TLT_OP) ||
(aluop_i == `EXE_TLTI_OP) || (aluop_i == `EXE_TGE_OP) ||
(aluop_i == `EXE_TGEI_OP)) ?
((reg1_i[31] && !reg2_i[31]) ||
(!reg1_i[31] && !reg2_i[31] && result_sum[31])||
(reg1_i[31] && reg2_i[31] && result_sum[31]))
: (reg1_i < reg2_i);
assign reg1_i_not = ~reg1_i;
always @ (*) begin
if(rst == `RstEnable) begin
arithmeticres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLT_OP, `EXE_SLTU_OP: begin
arithmeticres <= reg1_lt_reg2 ;
end
`EXE_ADD_OP, `EXE_ADDU_OP, `EXE_ADDI_OP, `EXE_ADDIU_OP: begin
arithmeticres <= result_sum;
end
`EXE_SUB_OP, `EXE_SUBU_OP: begin
arithmeticres <= result_sum;
end
`EXE_CLZ_OP: begin
arithmeticres <= reg1_i[31] ? 0 : reg1_i[30] ? 1 : reg1_i[29] ? 2 :
reg1_i[28] ? 3 : reg1_i[27] ? 4 : reg1_i[26] ? 5 :
reg1_i[25] ? 6 : reg1_i[24] ? 7 : reg1_i[23] ? 8 :
reg1_i[22] ? 9 : reg1_i[21] ? 10 : reg1_i[20] ? 11 :
reg1_i[19] ? 12 : reg1_i[18] ? 13 : reg1_i[17] ? 14 :
reg1_i[16] ? 15 : reg1_i[15] ? 16 : reg1_i[14] ? 17 :
reg1_i[13] ? 18 : reg1_i[12] ? 19 : reg1_i[11] ? 20 :
reg1_i[10] ? 21 : reg1_i[9] ? 22 : reg1_i[8] ? 23 :
reg1_i[7] ? 24 : reg1_i[6] ? 25 : reg1_i[5] ? 26 :
reg1_i[4] ? 27 : reg1_i[3] ? 28 : reg1_i[2] ? 29 :
reg1_i[1] ? 30 : reg1_i[0] ? 31 : 32 ;
end
`EXE_CLO_OP: begin
arithmeticres <= (reg1_i_not[31] ? 0 : reg1_i_not[30] ? 1 : reg1_i_not[29] ? 2 :
reg1_i_not[28] ? 3 : reg1_i_not[27] ? 4 : reg1_i_not[26] ? 5 :
reg1_i_not[25] ? 6 : reg1_i_not[24] ? 7 : reg1_i_not[23] ? 8 :
reg1_i_not[22] ? 9 : reg1_i_not[21] ? 10 : reg1_i_not[20] ? 11 :
reg1_i_not[19] ? 12 : reg1_i_not[18] ? 13 : reg1_i_not[17] ? 14 :
reg1_i_not[16] ? 15 : reg1_i_not[15] ? 16 : reg1_i_not[14] ? 17 :
reg1_i_not[13] ? 18 : reg1_i_not[12] ? 19 : reg1_i_not[11] ? 20 :
reg1_i_not[10] ? 21 : reg1_i_not[9] ? 22 : reg1_i_not[8] ? 23 :
reg1_i_not[7] ? 24 : reg1_i_not[6] ? 25 : reg1_i_not[5] ? 26 :
reg1_i_not[4] ? 27 : reg1_i_not[3] ? 28 : reg1_i_not[2] ? 29 :
reg1_i_not[1] ? 30 : reg1_i_not[0] ? 31 : 32) ;
end
default: begin
arithmeticres <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
trapassert <= `TrapNotAssert;
end else begin
trapassert <= `TrapNotAssert;
case (aluop_i)
`EXE_TEQ_OP, `EXE_TEQI_OP: begin
if( reg1_i == reg2_i ) begin
trapassert <= `TrapAssert;
end
end
`EXE_TGE_OP, `EXE_TGEI_OP, `EXE_TGEIU_OP, `EXE_TGEU_OP: begin
if( ~reg1_lt_reg2 ) begin
trapassert <= `TrapAssert;
end
end
`EXE_TLT_OP, `EXE_TLTI_OP, `EXE_TLTIU_OP, `EXE_TLTU_OP: begin
if( reg1_lt_reg2 ) begin
trapassert <= `TrapAssert;
end
end
`EXE_TNE_OP, `EXE_TNEI_OP: begin
if( reg1_i != reg2_i ) begin
trapassert <= `TrapAssert;
end
end
default: begin
trapassert <= `TrapNotAssert;
end
endcase
end
end
always@ (*) begin
if(aluop_i == `EXE_BREAK_OP) begin
breassert <= 1'b1;
end else begin
breassert <= 1'b0;
end
end
//È¡µÃ³Ë·¨²Ù×÷µÄ²Ù×÷Êý£¬Èç¹ûÊÇÓзûºÅ³ý·¨ÇÒ²Ù×÷ÊýÊǸºÊý£¬ÄÇôȡ·´¼ÓÒ»
assign opdata1_mult = (((aluop_i == `EXE_MUL_OP) || (aluop_i == `EXE_MULT_OP) ||
(aluop_i == `EXE_MADD_OP) || (aluop_i == `EXE_MSUB_OP))
&& (reg1_i[31] == 1'b1)) ? (~reg1_i + 1) : reg1_i;
assign opdata2_mult = (((aluop_i == `EXE_MUL_OP) || (aluop_i == `EXE_MULT_OP) ||
(aluop_i == `EXE_MADD_OP) || (aluop_i == `EXE_MSUB_OP))
&& (reg2_i[31] == 1'b1)) ? (~reg2_i + 1) : reg2_i;
assign hilo_temp = opdata1_mult * opdata2_mult;
always @ (*) begin
if(rst == `RstEnable) begin
mulres <= {`ZeroWord,`ZeroWord};
end else if ((aluop_i == `EXE_MULT_OP) || (aluop_i == `EXE_MUL_OP) ||
(aluop_i == `EXE_MADD_OP) || (aluop_i == `EXE_MSUB_OP))begin
if(reg1_i[31] ^ reg2_i[31] == 1'b1) begin
mulres <= ~hilo_temp + 1;
end else begin
mulres <= hilo_temp;
end
end else begin
mulres <= hilo_temp;
end
end
//µÃµ½×îеÄHI¡¢LO¼Ä´æÆ÷µÄÖµ£¬´Ë´¦Òª½â¾öÖ¸ÁîÊý¾ÝÏà¹ØÎÊÌâ
always @ (*) begin
if(rst == `RstEnable) begin
{HI,LO} <= {`ZeroWord,`ZeroWord};
end else if(mem_whilo_i == `WriteEnable) begin
{HI,LO} <= {mem_hi_i,mem_lo_i};
end else if(wb_whilo_i == `WriteEnable) begin
{HI,LO} <= {wb_hi_i,wb_lo_i};
end else begin
{HI,LO} <= {hi_i,lo_i};
end
end
always @ (*) begin
stallreq = stallreq_for_madd_msub || stallreq_for_div;
end
//MADD¡¢MADDU¡¢MSUB¡¢MSUBUÖ¸Áî
always @ (*) begin
if(rst == `RstEnable) begin
hilo_temp_o <= {`ZeroWord,`ZeroWord};
cnt_o <= 2'b00;
stallreq_for_madd_msub <= `NoStop;
end else begin
case (aluop_i)
`EXE_MADD_OP, `EXE_MADDU_OP: begin
if(cnt_i == 2'b00) begin
hilo_temp_o <= mulres;
cnt_o <= 2'b01;
stallreq_for_madd_msub <= `Stop;
hilo_temp1 <= {`ZeroWord,`ZeroWord};
end else if(cnt_i == 2'b01) begin
hilo_temp_o <= {`ZeroWord,`ZeroWord};
cnt_o <= 2'b10;
hilo_temp1 <= hilo_temp_i + {HI,LO};
stallreq_for_madd_msub <= `NoStop;
end
end
`EXE_MSUB_OP, `EXE_MSUBU_OP: begin
if(cnt_i == 2'b00) begin
hilo_temp_o <= ~mulres + 1 ;
cnt_o <= 2'b01;
stallreq_for_madd_msub <= `Stop;
end else if(cnt_i == 2'b01)begin
hilo_temp_o <= {`ZeroWord,`ZeroWord};
cnt_o <= 2'b10;
hilo_temp1 <= hilo_temp_i + {HI,LO};
stallreq_for_madd_msub <= `NoStop;
end
end
default: begin
hilo_temp_o <= {`ZeroWord,`ZeroWord};
cnt_o <= 2'b00;
stallreq_for_madd_msub <= `NoStop;
end
endcase
end
end
//DIV¡¢DIVUÖ¸Áî
always @ (*) begin
if(rst == `RstEnable) begin
stallreq_for_div <= `NoStop;
div_opdata1_o <= `ZeroWord;
div_opdata2_o <= `ZeroWord;
div_start_o <= `DivStop;
signed_div_o <= 1'b0;
end else begin
stallreq_for_div <= `NoStop;
div_opdata1_o <= `ZeroWord;
div_opdata2_o <= `ZeroWord;
div_start_o <= `DivStop;
signed_div_o <= 1'b0;
case (aluop_i)
`EXE_DIV_OP: begin
if(div_ready_i == `DivResultNotReady) begin
div_opdata1_o <= reg1_i;
div_opdata2_o <= reg2_i;
div_start_o <= `DivStart;
signed_div_o <= 1'b1;
stallreq_for_div <= `Stop;
end else if(div_ready_i == `DivResultReady) begin
div_opdata1_o <= reg1_i;
div_opdata2_o <= reg2_i;
div_start_o <= `DivStop;
signed_div_o <= 1'b1;
stallreq_for_div <= `NoStop;
end else begin
div_opdata1_o <= `ZeroWord;
div_opdata2_o <= `ZeroWord;
div_start_o <= `DivStop;
signed_div_o <= 1'b0;
stallreq_for_div <= `NoStop;
end
end
`EXE_DIVU_OP: begin
if(div_ready_i == `DivResultNotReady) begin
div_opdata1_o <= reg1_i;
div_opdata2_o <= reg2_i;
div_start_o <= `DivStart;
signed_div_o <= 1'b0;
stallreq_for_div <= `Stop;
end else if(div_ready_i == `DivResultReady) begin
div_opdata1_o <= reg1_i;
div_opdata2_o <= reg2_i;
div_start_o <= `DivStop;
signed_div_o <= 1'b0;
stallreq_for_div <= `NoStop;
end else begin
div_opdata1_o <= `ZeroWord;
div_opdata2_o <= `ZeroWord;
div_start_o <= `DivStop;
signed_div_o <= 1'b0;
stallreq_for_div <= `NoStop;
end
end
default: begin
end
endcase
end
end
//MFHI¡¢MFLO¡¢MOVN¡¢MOVZÖ¸Áî
always @ (*) begin
if(rst == `RstEnable) begin
moveres <= `ZeroWord;
end else begin
moveres <= `ZeroWord;
case (aluop_i)
`EXE_MFHI_OP: begin
moveres <= HI;
end
`EXE_MFLO_OP: begin
moveres <= LO;
end
`EXE_MOVZ_OP: begin
moveres <= reg1_i;
end
`EXE_MOVN_OP: begin
moveres <= reg1_i;
end
`EXE_MFC0_OP: begin
cp0_reg_read_addr_o <= inst_i[15:11];
moveres <= cp0_reg_data_i;
if( mem_cp0_reg_we == `WriteEnable &&
mem_cp0_reg_write_addr == inst_i[15:11] ) begin
moveres <= mem_cp0_reg_data;
end else if( wb_cp0_reg_we == `WriteEnable &&
wb_cp0_reg_write_addr == inst_i[15:11] ) begin
moveres <= wb_cp0_reg_data;
end
end
default : begin
end
endcase
end
end
always @ (*) begin
wd_o <= wd_i;
wreg_o <= wreg_i;
case ( alusel_i )
`EXE_RES_LOGIC: begin
wdata_o <= logicout;
end
`EXE_RES_SHIFT: begin
wdata_o <= shiftres;
end
`EXE_RES_MOVE: begin
wdata_o <= moveres;
end
`EXE_RES_ARITHMETIC: begin
wdata_o <= arithmeticres;
end
`EXE_RES_MUL: begin
wdata_o <= mulres[31:0];
end
`EXE_RES_JUMP_BRANCH: begin
wdata_o <= link_address_i;
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
always @ (*) begin
if(rst == `RstEnable) begin
whilo_o <= `WriteDisable;
hi_o <= `ZeroWord;
lo_o <= `ZeroWord;
end else if((aluop_i == `EXE_MULT_OP) || (aluop_i == `EXE_MULTU_OP)) begin
whilo_o <= `WriteEnable;
hi_o <= mulres[63:32];
lo_o <= mulres[31:0];
end else if((aluop_i == `EXE_MADD_OP) || (aluop_i == `EXE_MADDU_OP)) begin
whilo_o <= `WriteEnable;
hi_o <= hilo_temp1[63:32];
lo_o <= hilo_temp1[31:0];
end else if((aluop_i == `EXE_MSUB_OP) || (aluop_i == `EXE_MSUBU_OP)) begin
whilo_o <= `WriteEnable;
hi_o <= hilo_temp1[63:32];
lo_o <= hilo_temp1[31:0];
end else if((aluop_i == `EXE_DIV_OP) || (aluop_i == `EXE_DIVU_OP)) begin
whilo_o <= `WriteEnable;
hi_o <= div_result_i[63:32];
lo_o <= div_result_i[31:0];
end else if(aluop_i == `EXE_MTHI_OP) begin
whilo_o <= `WriteEnable;
hi_o <= reg1_i;
lo_o <= LO;
end else if(aluop_i == `EXE_MTLO_OP) begin
whilo_o <= `WriteEnable;
hi_o <= HI;
lo_o <= reg1_i;
end else begin
whilo_o <= `WriteDisable;
hi_o <= `ZeroWord;
lo_o <= `ZeroWord;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
cp0_reg_write_addr_o <= 5'b00000;
cp0_reg_we_o <= `WriteDisable;
cp0_reg_data_o <= `ZeroWord;
end else if(aluop_i == `EXE_MTC0_OP) begin
cp0_reg_write_addr_o <= inst_i[15:11];
cp0_reg_we_o <= `WriteEnable;
cp0_reg_data_o <= reg1_i;
end else begin
cp0_reg_write_addr_o <= 5'b00000;
cp0_reg_we_o <= `WriteDisable;
cp0_reg_data_o <= `ZeroWord;
end
end
endmodule |
//
//`define ENABLE_EXPROM
`default_nettype none
module pcie_tlp (
// System
input pcie_clk,
input sys_rst,
// Management
input [6:0] rx_bar_hit,
input [7:0] bus_num,
input [4:0] dev_num,
input [2:0] func_num,
// Receive
input rx_st,
input rx_end,
input [15:0] rx_data,
input rx_malf,
// Transmit
output reg tx_req = 1'b0,
input tx_rdy,
output reg tx_st = 1'b0,
output tx_end,
output reg [15:0] tx_data,
input [8:0] tx_ca_ph,
input [12:0] tx_ca_pd,
input [8:0] tx_ca_nph,
input [12:0] tx_ca_npd,
input [8:0] tx_ca_cplh,
input [12:0] tx_ca_cpld,
input tx_ca_p_recheck,
input tx_ca_cpl_recheck,
// Receive credits
output reg [7:0] pd_num = 8'h0,
output reg ph_cr = 1'b0,
output reg pd_cr = 1'b0,
output reg nph_cr = 1'b0,
output reg npd_cr = 1'b0,
// Master FIFO
output reg mst_rd_en,
input mst_empty,
input [17:0] mst_dout,
output reg mst_wr_en,
input mst_full,
output reg [17:0] mst_din,
// Slave BUS
output reg [6:0] slv_bar_i,
output reg slv_ce_i,
output reg slv_we_i,
output reg [19:1] slv_adr_i,
output reg [15:0] slv_dat_i,
output reg [1:0] slv_sel_i,
input [15:0] slv_dat_o,
// Slave FIFO
output reg slv_rd_en,
input slv_empty,
input [17:0] slv_dout,
output reg slv_wr_en,
input slv_full,
output reg [17:0] slv_din,
// LED and Switches
input [7:0] dipsw,
output [7:0] led,
output [13:0] segled,
input btn
);
parameter [2:0]
TLP_MR = 3'h0,
TLP_MRdLk= 3'h1,
TLP_IO = 3'h2,
TLP_Cfg0 = 3'h3,
TLP_Cfg1 = 3'h4,
TLP_Msg = 3'h5,
TLP_Cpl = 3'h6,
TLP_CplLk= 3'h7;
reg [2:0] rx_comm = 3'h0;
//-----------------------------------------------------------------
// TLP receive
//-----------------------------------------------------------------
parameter [3:0]
RX_HEAD0 = 4'h0,
RX_HEAD1 = 4'h1,
RX_REQ2 = 4'h2,
RX_REQ3 = 4'h3,
RX_REQ4 = 4'h4,
RX_REQ5 = 4'h5,
RX_REQ6 = 4'h6,
RX_REQ7 = 4'h7,
RX_REQ = 4'h8,
RX_COMP2 = 4'h9,
RX_COMP3 = 4'ha,
RX_COMP4 = 4'hb,
RX_COMP5 = 4'hc,
RX_COMP6 = 4'hd,
RX_COMP7 = 4'he,
RX_COMP = 4'hf;
reg [3:0] rx_status = RX_HEAD0;
reg [1:0] rx_fmt = 2'b00;
reg [4:0] rx_type = 5'b00000;
reg [2:0] rx_tc = 2'b00;
reg rx_td = 1'b0, rx_ep = 1'b0;
reg [1:0] rx_attr = 2'b00;
reg [9:0] rx_length = 10'h0;
reg [15:0] rx_reqid = 16'h0;
reg [7:0] rx_tag = 8'h0;
reg [3:0] rx_lastbe = 4'h0, rx_firstbe = 4'h0;
reg [47:2] rx_addr = 46'h0000000000000000;
reg rx_tlph_valid = 1'b0;
reg [15:0] rx_data2 = 16'h0;
reg rx_end2 = 1'b0;
always @(posedge pcie_clk) begin
if (sys_rst) begin
rx_status <= RX_HEAD0;
rx_tlph_valid <= 1'b0;
pd_num <= 8'h0;
ph_cr <= 1'b0;
pd_cr <= 1'b0;
nph_cr <= 1'b0;
npd_cr <= 1'b0;
rx_data2[15:0] <= 16'h0;
rx_end2 <= 1'b0;
end else begin
rx_tlph_valid <= 1'b0;
pd_num <= 8'h0;
ph_cr <= 1'b0;
pd_cr <= 1'b0;
nph_cr <= 1'b0;
npd_cr <= 1'b0;
rx_data2 <= rx_data;
rx_end2 <= rx_end;
if ( rx_end == 1'b1 ) begin
case ( rx_comm )
TLP_MR, TLP_MRdLk: begin
`ifndef ENABLE_EXPROM
if ( rx_bar_hit[6:0] != 7'b0000000 ) begin
`endif
if ( rx_fmt[1] == 1'b0 ) begin
nph_cr <= 1'b1;
end else begin
ph_cr <= 1'b1;
pd_cr <= rx_fmt[1];
pd_num <= rx_length[1:0] == 2'b00 ? rx_length[9:2] : (rx_length[9:2] + 8'h1);
end
`ifndef ENABLE_EXPROM
end
`endif
end
TLP_IO, TLP_Cfg0, TLP_Cfg1: begin
nph_cr <= 1'b1;
npd_cr <= rx_fmt[1];
end
TLP_Msg: begin
ph_cr <= 1'b1;
if ( rx_fmt[1] == 1'b1 ) begin
pd_cr <= 1'b1;
pd_num <= rx_length[1:0] == 2'b00 ? rx_length[9:2] : (rx_length[9:2] + 8'h1);
end
end
TLP_Cpl: begin
end
TLP_CplLk: begin
end
endcase
rx_status <= RX_HEAD0;
end
case ( rx_status )
RX_HEAD0: begin
if ( rx_st == 1'b1 ) begin
rx_fmt [1:0] <= rx_data[14:13];
rx_type[4:0] <= rx_data[12: 8];
rx_tc [2:0] <= rx_data[ 6: 4];
if ( rx_data[12] == 1'b1 ) begin
rx_comm <= TLP_Msg;
end else begin
if ( rx_data[11] == 1'b0) begin
case ( rx_data[10:8] )
3'b000: rx_comm <= TLP_MR;
3'b001: rx_comm <= TLP_MRdLk;
3'b010: rx_comm <= TLP_IO;
3'b100: rx_comm <= TLP_Cfg0;
default:rx_comm <= TLP_Cfg1;
endcase
end else begin
if ( rx_data[8] == 1'b0 )
rx_comm <= TLP_Cpl;
else
rx_comm <= TLP_CplLk;
end
end
rx_status <= RX_HEAD1;
end
end
RX_HEAD1: begin
rx_td <= rx_data[15:15];
rx_ep <= rx_data[14:14];
rx_attr[1:0] <= rx_data[13:12];
rx_length[9:0] <= rx_data[ 9: 0];
if ( rx_type[3] == 1'b0 )
rx_status <= RX_REQ2;
else
rx_status <= RX_COMP2;
end
RX_REQ2: begin
rx_reqid[15:0] <= rx_data[15:0];
rx_status <= RX_REQ3;
end
RX_REQ3: begin
rx_tag[7:0] <= rx_data[15:8];
rx_lastbe[3:0] <= rx_data[7:4];
rx_firstbe[3:0] <= rx_data[3:0];
if ( rx_fmt[0] == 1'b0 ) begin // 64 or 32bit ??
rx_addr[47:32] <= 16'h0;
rx_status <= RX_REQ6;
end else
rx_status <= RX_REQ4;
end
RX_REQ4: begin
rx_status <= RX_REQ5;
end
RX_REQ5: begin
rx_addr[47:32] <= rx_data[15:0];
rx_status <= RX_REQ6;
end
RX_REQ6: begin
rx_addr[31:16] <= rx_data[15:0];
rx_tlph_valid <= 1'b1;
rx_status <= RX_REQ7;
end
RX_REQ7: begin
rx_addr[15: 2] <= rx_data[15:2];
if ( rx_end == 1'b0 )
rx_status <= RX_REQ;
end
RX_REQ: begin
end
endcase
end
end
//-----------------------------------------------------------------
// TLP transmit
//-----------------------------------------------------------------
parameter [4:0]
TX_IDLE = 5'h0,
TX_WAIT = 5'h1,
TX1_HEAD0= 5'h2,
TX1_HEAD1= 5'h3,
TX1_COMP2= 5'h4,
TX1_COMP3= 5'h5,
TX1_COMP4= 5'h6,
TX1_COMP5= 5'h7,
TX1_DATA = 5'h8,
TX2_HEAD0= 5'h9,
TX2_HEAD1= 5'hA,
TX2_COMP2= 5'hB,
TX2_COMP3= 5'hC,
TX2_COMP4= 5'hD,
TX2_COMP5= 5'hE,
TX2_COMP6= 5'hF,
TX2_COMP7= 5'h10,
TX2_DATA = 5'h11;
reg [4:0] tx_status = TX_IDLE;
reg tx_lastch = 1'b0;
reg [15:0] tx1_data;
reg tx1_tlph_valid = 1'b0;
reg tx1_tlpd_ready = 1'b0;
reg tx1_tlpd_done = 1'b0;
reg [1:0] tx1_fmt = 2'b00;
reg [4:0] tx1_type = 5'b00000;
reg [2:0] tx1_tc = 2'b00;
reg tx1_td = 1'b0, tx1_ep = 1'b0;
reg [1:0] tx1_attr = 2'b00;
reg [10:0] tx1_length = 11'h0;
reg [2:0] tx1_cplst = 3'h0;
reg tx1_bcm = 1'b0;
reg [11:0] tx1_bcount = 12'h0;
reg [15:0] tx1_reqid = 16'h0;
reg [7:0] tx1_tag = 8'h0;
reg [7:0] tx1_lowaddr = 8'h0;
reg [3:0] tx1_lastbe = 4'h0, tx1_firstbe = 4'h0;
reg [15:0] tx2_data;
reg tx2_tlph_valid = 1'b0;
reg tx2_tlpd_ready = 1'b0;
reg tx2_tlpd_done = 1'b0;
reg [1:0] tx2_fmt = 2'b00;
reg [4:0] tx2_type = 5'b00000;
reg [2:0] tx2_tc = 2'b00;
reg tx2_td = 1'b0, tx2_ep = 1'b0;
reg [1:0] tx2_attr = 2'b00;
reg [10:0] tx2_length = 11'h0;
reg [11:0] tx2_bcount = 12'h0;
reg [15:0] tx2_reqid = 16'h0;
reg [7:0] tx2_tag = 8'h0;
reg [7:0] tx2_lowaddr = 8'h0;
reg [3:0] tx2_lastbe = 4'h0, tx2_firstbe = 4'h0;
reg [47:2] tx2_addr = 46'h0000000000000000;
always @(posedge pcie_clk) begin
if (sys_rst) begin
tx_status <= TX_IDLE;
tx_data[15:0] <= 16'h0;
tx_req <= 1'b0;
tx_st <= 1'b0;
tx1_tlpd_ready <= 1'b0;
tx2_tlpd_ready <= 1'b0;
tx_lastch <= 1'b0;
end else begin
tx_st <= 1'b0;
case ( tx_status )
TX_IDLE: begin
if ( tx1_tlph_valid == 1'b1 || tx2_tlph_valid == 1'b1 ) begin
tx_lastch <= tx2_tlph_valid;
tx_req <= 1'b1;
tx_status <= TX_WAIT;
end
end
TX_WAIT: begin
if ( tx_rdy == 1'b1 ) begin
tx_req <= 1'b0;
if ( tx_lastch == 1'b1 )
tx_status <= TX2_HEAD0;
else
tx_status <= TX1_HEAD0;
end
end
TX1_HEAD0: begin
tx_data[15:0] <= {1'b0, tx1_fmt[1:0], tx1_type[4:0], 1'b0, tx1_tc[2:0], 4'b000};
tx_st <= 1'b1;
tx_status <= TX1_HEAD1;
end
TX1_HEAD1: begin
tx_data[15:0] <= {tx1_td, tx1_ep, tx1_attr[1:0], 2'b00, tx1_length[10:1]};
tx_status <= TX1_COMP2;
end
TX1_COMP2: begin
tx_data[15:0] <= {bus_num, dev_num, func_num}; // CplID
tx1_tlpd_ready <= 1'b1;
tx_status <= TX1_COMP3;
end
TX1_COMP3: begin
tx_data[15:0] <= { tx1_cplst[2:0], tx1_bcm, tx1_bcount[11:0] };
tx_status <= TX1_COMP4;
end
TX1_COMP4: begin
tx_data[15:0] <= tx1_reqid[15:0];
tx_status <= TX1_COMP5;
end
TX1_COMP5: begin
tx_data[15:0] <= { tx1_tag[7:0], 1'b0, tx1_lowaddr[6:0] };
tx_status <= TX1_DATA;
end
TX1_DATA: begin
tx_data[15:0] <= tx1_data[15:0];
if (tx1_tlpd_done == 1'b1) begin
tx_status <= TX_IDLE;
tx1_tlpd_ready <= 1'b0;
end
end
TX2_HEAD0: begin
tx_data[15:0] <= {1'b0, tx2_fmt[1:0], tx2_type[4:0], 1'b0, tx2_tc[2:0], 4'b000};
tx_st <= 1'b1;
tx_status <= TX2_HEAD1;
end
TX2_HEAD1: begin
tx_data[15:0] <= {tx2_td, tx2_ep, tx2_attr[1:0], 2'b00, tx2_length[10:1]};
tx_status <= TX2_COMP2;
end
TX2_COMP2: begin
tx_data[15:0] <= {bus_num, dev_num, func_num}; // Request ID
tx_status <= TX2_COMP3;
end
TX2_COMP3: begin
tx_data[15:0] <= { tx2_tag[7:0], tx2_lastbe[3:0], tx2_firstbe[3:0] };
if ( tx2_fmt[0] == 1'b0 ) begin // 64 or 32bit ??
tx2_tlpd_ready <= 1'b1;
tx_status <= TX2_COMP6;
end else
tx_status <= TX2_COMP4;
end
TX2_COMP4: begin
tx_data[15:0] <= 16'h0000;
tx2_tlpd_ready <= 1'b1;
tx_status <= TX2_COMP5;
end
TX2_COMP5: begin
tx_data[15:0] <= tx2_addr[47:32];
tx_status <= TX2_COMP6;
end
TX2_COMP6: begin
tx_data[15:0] <= tx2_addr[31:16];
tx_status <= TX2_COMP7;
end
TX2_COMP7: begin
tx_data[15:0] <= { tx2_addr[15: 2], 2'b00 };
tx_status <= TX2_DATA;
end
TX2_DATA: begin
tx_data[15:0] <= tx2_data[15:0];
if (tx2_tlpd_done == 1'b1) begin
tx_status <= TX_IDLE;
tx2_tlpd_ready <= 1'b0;
end
end
endcase
end
end
//-----------------------------------------------------------------
// Slave Seaquencer
//-----------------------------------------------------------------
parameter [3:0]
SLV_IDLE = 3'h0,
SLV_MREADH = 3'h1,
SLV_MREADD = 3'h2,
SLV_MWRITEH= 3'h3,
SLV_MWRITED= 3'h4,
SLV_COMP = 3'h7;
reg [3:0] slv_status = SLV_IDLE;
always @(posedge pcie_clk) begin
if (sys_rst) begin
tx1_tlph_valid <= 1'b0;
tx1_tlpd_done <= 1'b0;
slv_status <= SLV_IDLE;
slv_bar_i <= 7'h0;
slv_ce_i <= 1'b0;
slv_we_i <= 1'b0;
slv_adr_i <= 20'h0;
slv_dat_i <= 16'b0;
slv_sel_i <= 2'b00;
end else begin
tx1_tlpd_done <= 1'b0;
slv_ce_i <= 1'b0;
slv_we_i <= 1'b0;
case ( slv_status )
SLV_IDLE: begin
tx1_tlph_valid <= 1'b0;
slv_bar_i <= 7'h0;
if ( rx_tlph_valid == 1'b1 ) begin
case ( rx_comm )
TLP_MR: begin
`ifdef ENABLE_EXPROM
slv_bar_i <= rx_bar_hit == 7'h0 ? 7'b1000000 : rx_bar_hit;
`else
slv_bar_i <= rx_bar_hit;
`endif
if ( rx_fmt[1] == 1'b0 ) begin
slv_status <= SLV_MREADH;
end else begin
slv_status <= SLV_MWRITEH;
end
end
TLP_MRdLk: begin
end
TLP_IO: begin
end
TLP_Cfg0: begin
end
TLP_Cfg1: begin
end
TLP_Msg: begin
end
TLP_Cpl: begin
end
TLP_CplLk: begin
end
endcase
end
end
SLV_MREADH: begin
tx1_fmt[1:0] <= 2'b10; // 3DW with data
tx1_type[4:0] <= 5'b01010; // Cpl with data
tx1_tc[2:0] <= 3'b000;
tx1_td <= 1'b0;
tx1_ep <= 1'b0;
tx1_attr[1:0] <= 2'b00;
tx1_cplst[2:0] <= 3'b000;
tx1_bcm <= 1'b0;
casex( {rx_firstbe[3:0], rx_lastbe[3:0]} )
8'b1xx10000: tx1_bcount[11:0] <= 12'h004;
8'b01x10000: tx1_bcount[11:0] <= 12'h003;
8'b1x100000: tx1_bcount[11:0] <= 12'h003;
8'b00110000: tx1_bcount[11:0] <= 12'h002;
8'b01100000: tx1_bcount[11:0] <= 12'h002;
8'b11000000: tx1_bcount[11:0] <= 12'h002;
8'b00010000: tx1_bcount[11:0] <= 12'h001;
8'b00100000: tx1_bcount[11:0] <= 12'h001;
8'b01000000: tx1_bcount[11:0] <= 12'h001;
8'b10000000: tx1_bcount[11:0] <= 12'h001;
8'b00000000: tx1_bcount[11:0] <= 12'h001;
8'bxxx11xxx: tx1_bcount[11:0] <= (rx_length*4);
8'bxxx101xx: tx1_bcount[11:0] <= (rx_length*4) - 1;
8'bxxx1001x: tx1_bcount[11:0] <= (rx_length*4) - 2;
8'bxxx10001: tx1_bcount[11:0] <= (rx_length*4) - 3;
8'bxx101xxx: tx1_bcount[11:0] <= (rx_length*4) - 1;
8'bxx1001xx: tx1_bcount[11:0] <= (rx_length*4) - 2;
8'bxx10001x: tx1_bcount[11:0] <= (rx_length*4) - 3;
8'bxx100001: tx1_bcount[11:0] <= (rx_length*4) - 4;
8'bx1001xxx: tx1_bcount[11:0] <= (rx_length*4) - 2;
8'bx10001xx: tx1_bcount[11:0] <= (rx_length*4) - 3;
8'bx100001x: tx1_bcount[11:0] <= (rx_length*4) - 4;
8'bx1000001: tx1_bcount[11:0] <= (rx_length*4) - 5;
8'b10001xxx: tx1_bcount[11:0] <= (rx_length*4) - 3;
8'b100001xx: tx1_bcount[11:0] <= (rx_length*4) - 4;
8'b1000001x: tx1_bcount[11:0] <= (rx_length*4) - 5;
8'b10000001: tx1_bcount[11:0] <= (rx_length*4) - 6;
endcase
tx1_reqid[15:0] <= rx_reqid[15:0];
tx1_tag[7:0] <= rx_tag[7:0];
casex (rx_firstbe[3:0])
4'b0000: tx1_lowaddr[7:0] <= {rx_addr[7:2], 2'b00};
4'bxxx1: tx1_lowaddr[7:0] <= {rx_addr[7:2], 2'b00};
4'bxx10: tx1_lowaddr[7:0] <= {rx_addr[7:2], 2'b01};
4'bx100: tx1_lowaddr[7:0] <= {rx_addr[7:2], 2'b10};
4'b1000: tx1_lowaddr[7:0] <= {rx_addr[7:2], 2'b11};
endcase
tx1_length[10:0] <= {rx_length[9:0], 1'b1};
slv_adr_i[19:1] <= ({rx_addr[19:2],1'b0} - 19'h1);
tx1_tlph_valid <= 1'b1;
slv_status <= SLV_MREADD;
end
SLV_MREADD: begin
if ( tx1_tlpd_ready == 1'b1 ) begin
tx1_tlph_valid <= 1'b0;
tx1_length <= tx1_length - 11'h1;
if ( tx1_length[10:1] != 10'h000)
slv_adr_i[19:1] <= slv_adr_i[19:1] + 19'h1;
if ( tx1_length == 11'h7ff ) begin
slv_status <= SLV_IDLE;
tx1_tlpd_done <= 1'b1;
end else
slv_ce_i <= 1'b1;
tx1_data[15:0] <= slv_dat_o[15:0];
end
end
SLV_MWRITEH: begin
tx1_length[10:0] <= 11'h0;
slv_adr_i[19:1] <= ({rx_addr[19:2],1'b0} - 19'h1);
slv_status <= SLV_MWRITED;
end
SLV_MWRITED: begin
tx1_length <= tx1_length + 11'h1;
slv_adr_i[19:1] <= slv_adr_i[19:1] + 19'h1;
slv_ce_i <= 1'b1;
slv_we_i <= 1'b1;
slv_dat_i <= rx_data2[15:0];
if ( tx1_length[10:1] == 10'h0 ) begin
if ( tx1_length[0] == 1'b0 ) begin
slv_sel_i[1:0] <= { rx_firstbe[0], rx_firstbe[1] };
end else begin
slv_sel_i[1:0] <= { rx_firstbe[2], rx_firstbe[3] };
end
end else if ( tx1_length[10:1] == (rx_length[9:0] - 10'h1) )
if ( tx1_length[0] == 1'b0 ) begin
slv_sel_i[1:0] <= { rx_lastbe[0], rx_lastbe[1] };
end else begin
slv_sel_i[1:0] <= { rx_lastbe[2], rx_lastbe[3] };
slv_status <= SLV_IDLE;
end
else begin
slv_sel_i[1:0] <= 2'b11;
end
if ( rx_end2 == 1'b1 )
slv_status <= SLV_IDLE;
end
endcase
end
end
//-----------------------------------------------------------------
// Master Seaquencer
//-----------------------------------------------------------------
parameter [3:0]
MST_IDLE = 3'h0,
MST_MWRITE64= 3'h1,
MST_MWRITE48= 3'h2,
MST_MWRITE32= 3'h3,
MST_MWRITE16= 3'h4,
MST_MWRITED = 3'h5,
MST_COMP = 3'h7;
reg [3:0] mst_status = MST_IDLE;
reg [47:1] mst_adr;
reg mst_rd_wait;
always @(posedge pcie_clk) begin
if (sys_rst) begin
tx2_tlph_valid <= 1'b0;
tx2_tlpd_done <= 1'b0;
mst_status <= MST_IDLE;
mst_rd_en <= 1'b0;
mst_rd_wait <= 1'b0;
end else begin
tx2_tlpd_done <= 1'b0;
mst_rd_en <= ~mst_empty & ~mst_rd_wait;
if ( ( mst_rd_en == 1'b1 && mst_empty == 1'b0 ) || ( mst_status == MST_MWRITED ) ) begin
case ( mst_status )
MST_IDLE: begin
tx2_tlph_valid <= 1'b0;
if ( mst_dout[17] == 1'b1 ) begin
tx2_addr[47:32] <= 14'h0;
tx2_length[10:0] <= {4'b0000, mst_dout[13:8], 1'b0};
{tx2_lastbe[3:0], tx2_firstbe[3:0]} <= mst_dout[7:0];
case ( mst_dout[15:14] )
2'b00: mst_status <= MST_MWRITE32;
2'b01: mst_status <= MST_MWRITE64;
2'b10: mst_status <= MST_MWRITE32;
2'b11: mst_status <= MST_MWRITE64;
endcase
end
end
MST_MWRITE64: begin
mst_status <= MST_MWRITE48;
end
MST_MWRITE48: begin
tx2_addr[47:32] <= mst_dout[15:0];
mst_status <= MST_MWRITE32;
end
MST_MWRITE32: begin
tx2_addr[31:16] <= mst_dout[15:0];
mst_status <= MST_MWRITE16;
end
MST_MWRITE16: begin
tx2_addr[15: 2] <= mst_dout[15:2];
tx2_fmt[1:0] <= 2'b11; // 4DW, with DATA
tx2_type[4:0] <= 5'b00000; // Memory write request
tx2_tc[2:0] <= 3'b000;
tx2_td <= 1'b0;
tx2_ep <= 1'b0;
tx2_attr[1:0] <= 2'b00;
tx2_tag[7:0] <= 8'h01;
mst_adr[47:1] <= {tx2_addr[47:16], mst_dout[15:2], 1'b0};
tx2_tlph_valid <= 1'b1;
mst_rd_en <= 1'b0;
mst_rd_wait <= 1'b1;
mst_status <= MST_MWRITED;
end
MST_MWRITED: begin
if ( tx2_tlpd_ready == 1'b1 ) begin
tx2_tlph_valid <= 1'b0;
tx2_length <= tx2_length - 11'h1;
if ( tx2_length[10:1] != 10'h000)
mst_adr[47:1] <= mst_adr[47:1] + 19'h1;
if ( tx2_length == 11'h7ff || tx2_length == 11'h7fe ) begin
mst_rd_en <= 1'b0;
end
if ( tx2_length == 11'h7fe ) begin
tx2_tlpd_done <= 1'b1;
mst_status <= MST_IDLE;
end
tx2_data[15:0] <= mst_dout[15:0];
mst_rd_wait <= 1'b0;
end
end
`ifdef NO
MST_MWRITEH: begin
tx2_length[10:0] <= 11'h0;
mst_adr[19:1] <= ({rx_addr[19:2],1'b0} - 19'h1);
mst_status <= MST_MWRITED;
end
MST_MWRITED: begin
tx2_length <= tx2_length + 11'h1;
mst_adr[19:1] <= mst_adr[19:1] + 19'h1;
mst_din <= rx_data2[15:0];
if ( tx2_length[10:1] == (rx_length[9:0] - 10'h1) )
if ( tx2_length[0] == 1'b1 ) begin
mst_status <= MST_IDLE;
end
if ( rx_end2 == 1'b1 )
mst_status <= MST_IDLE;
end
`endif
endcase
end
end
end
assign tx_end = tx1_tlpd_done | tx2_tlpd_done;
//assign tx_end = tx1_tlpd_done;
//assign led = 8'b11111111;
//assign led = ~(btn ? rx_addr[31:24] : rx_addr[23:16]);
assign led = ~(btn ? rx_length[7:0] : {rx_lastbe[3:0], rx_firstbe[3:0]} );
//assign segled = ~{12'b000000000000, rx_length[9:8] };
endmodule
`default_nettype wire
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_267x128.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_267x128 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrempty,
wrfull,
wrusedw);
input [266:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [266:0] q;
output rdempty;
output wrempty;
output wrfull;
output [6:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "267"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "267"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "267"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 267 0 INPUT NODEFVAL data[266..0]
// Retrieval info: USED_PORT: q 0 0 267 0 OUTPUT NODEFVAL q[266..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL wrusedw[6..0]
// Retrieval info: CONNECT: @data 0 0 267 0 data 0 0 267 0
// Retrieval info: CONNECT: q 0 0 267 0 @q 0 0 267 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_267x128_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* PL allocator
*
*
*/
module LAG_pl_allocator (req, output_port, // PL request, for which port?
pl_new, pl_new_valid, // newly allocated PL ids
pl_allocated, // which PLs were allocated on this cycle?
pl_alloc_status, // which PLs are free?
clk, rst_n);
parameter buf_len=4;
parameter xs=4;
parameter ys=4;
parameter np=5;
parameter nv=4;
parameter dynamic_priority_pl_alloc = 0;
parameter plalloc_unrestricted = 0;
parameter alloc_stages = 1;
parameter plselect_bydestinationnode = 0;
parameter plselect_leastfullbuffer = 0;
parameter plselect_arbstateupdate = 0;
parameter plselect_usepacketmask = 0;
//-----
input [np-1:0][nv-1:0] req;
input output_port_t output_port [np-1:0][nv-1:0];
output [np-1:0][nv-1:0][nv-1:0] pl_new;
output [np-1:0][nv-1:0] pl_new_valid;
// input pl_priority_t pl_sel_priority [np-1:0][nv-1:0][nv-1:0];
output [np-1:0][nv-1:0] pl_allocated;
input [np-1:0][nv-1:0] pl_alloc_status;
input clk, rst_n;
generate
LAG_pl_unrestricted_allocator
#(.np(np), .nv(nv), .xs(xs), .ys(ys), .buf_len(buf_len),
.alloc_stages(alloc_stages),
.dynamic_priority_pl_alloc(dynamic_priority_pl_alloc),
.plselect_bydestinationnode(plselect_bydestinationnode),
.plselect_leastfullbuffer(plselect_leastfullbuffer),
.plselect_arbstateupdate(plselect_arbstateupdate),
.plselect_usepacketmask(plselect_usepacketmask))
unrestricted
(
.req,
.output_port,
.pl_status(pl_alloc_status),
.pl_new,
.pl_new_valid,
.pl_allocated,
.clk, .rst_n
);
endgenerate
endmodule // LAG_pl_allocator
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altera_syscon_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_syscon_pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=altera_syscon_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altera_syscon_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_syscon_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_syscon_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_syscon_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_syscon_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_syscon_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_syscon_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_syscon_pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_PP_SYMBOL_V
`define SKY130_FD_SC_LP__XOR2_PP_SYMBOL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_PP_SYMBOL_V
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_tl_repeater_5(
input clock,
input reset,
input io_repeat,
output io_full,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [2:0] io_enq_bits_param,
input [2:0] io_enq_bits_size,
input [1:0] io_enq_bits_source,
input [29:0] io_enq_bits_address,
input [3:0] io_enq_bits_mask,
input [31:0] io_enq_bits_data,
input io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output [2:0] io_deq_bits_param,
output [2:0] io_deq_bits_size,
output [1:0] io_deq_bits_source,
output [29:0] io_deq_bits_address,
output [3:0] io_deq_bits_mask,
output [31:0] io_deq_bits_data
);
reg full;
reg [31:0] GEN_9;
reg [2:0] saved_opcode;
reg [31:0] GEN_10;
reg [2:0] saved_param;
reg [31:0] GEN_11;
reg [2:0] saved_size;
reg [31:0] GEN_12;
reg [1:0] saved_source;
reg [31:0] GEN_13;
reg [29:0] saved_address;
reg [31:0] GEN_14;
reg [3:0] saved_mask;
reg [31:0] GEN_15;
reg [31:0] saved_data;
reg [31:0] GEN_16;
wire T_77;
wire T_79;
wire T_80;
wire [2:0] T_81_opcode;
wire [2:0] T_81_param;
wire [2:0] T_81_size;
wire [1:0] T_81_source;
wire [29:0] T_81_address;
wire [3:0] T_81_mask;
wire [31:0] T_81_data;
wire T_89;
wire T_90;
wire GEN_0;
wire [2:0] GEN_1;
wire [2:0] GEN_2;
wire [2:0] GEN_3;
wire [1:0] GEN_4;
wire [29:0] GEN_5;
wire [3:0] GEN_6;
wire [31:0] GEN_7;
wire T_92;
wire T_94;
wire T_95;
wire GEN_8;
assign io_full = full;
assign io_enq_ready = T_80;
assign io_deq_valid = T_77;
assign io_deq_bits_opcode = T_81_opcode;
assign io_deq_bits_param = T_81_param;
assign io_deq_bits_size = T_81_size;
assign io_deq_bits_source = T_81_source;
assign io_deq_bits_address = T_81_address;
assign io_deq_bits_mask = T_81_mask;
assign io_deq_bits_data = T_81_data;
assign T_77 = io_enq_valid | full;
assign T_79 = full == 1'h0;
assign T_80 = io_deq_ready & T_79;
assign T_81_opcode = full ? saved_opcode : io_enq_bits_opcode;
assign T_81_param = full ? saved_param : io_enq_bits_param;
assign T_81_size = full ? saved_size : io_enq_bits_size;
assign T_81_source = full ? saved_source : io_enq_bits_source;
assign T_81_address = full ? saved_address : io_enq_bits_address;
assign T_81_mask = full ? saved_mask : io_enq_bits_mask;
assign T_81_data = full ? saved_data : io_enq_bits_data;
assign T_89 = io_enq_ready & io_enq_valid;
assign T_90 = T_89 & io_repeat;
assign GEN_0 = T_90 ? 1'h1 : full;
assign GEN_1 = T_90 ? io_enq_bits_opcode : saved_opcode;
assign GEN_2 = T_90 ? io_enq_bits_param : saved_param;
assign GEN_3 = T_90 ? io_enq_bits_size : saved_size;
assign GEN_4 = T_90 ? io_enq_bits_source : saved_source;
assign GEN_5 = T_90 ? io_enq_bits_address : saved_address;
assign GEN_6 = T_90 ? io_enq_bits_mask : saved_mask;
assign GEN_7 = T_90 ? io_enq_bits_data : saved_data;
assign T_92 = io_deq_ready & io_deq_valid;
assign T_94 = io_repeat == 1'h0;
assign T_95 = T_92 & T_94;
assign GEN_8 = T_95 ? 1'h0 : GEN_0;
always @(posedge clock or posedge reset)
if (reset) begin
full <= 1'h0;
end else begin
if (T_95) begin
full <= 1'h0;
end else begin
if (T_90) begin
full <= 1'h1;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
saved_opcode <= 3'b0;
saved_param <= 3'b0;
saved_size <= 3'b0;
saved_source <= 2'b0;
saved_address <= 30'b0;
saved_mask <= 4'b0;
saved_data <= 32'b0;
end
else begin
if (T_90) begin
saved_opcode <= io_enq_bits_opcode;
end
if (T_90) begin
saved_param <= io_enq_bits_param;
end
if (T_90) begin
saved_size <= io_enq_bits_size;
end
if (T_90) begin
saved_source <= io_enq_bits_source;
end
if (T_90) begin
saved_address <= io_enq_bits_address;
end
if (T_90) begin
saved_mask <= io_enq_bits_mask;
end
if (T_90) begin
saved_data <= io_enq_bits_data;
end
end
endmodule
|
//Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
//Date : Mon May 15 11:07:48 2017
//Host : DLAB running 64-bit Service Pack 1 (build 7601)
//Command : generate_target image_processing_2d_design.bd
//Design : image_processing_2d_design
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "image_processing_2d_design,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=image_processing_2d_design,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=25,numReposBlks=17,numNonXlnxBlks=0,numHierBlks=8,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=8,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=1,da_board_cnt=1,da_ps7_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "image_processing_2d_design.hwdef" *)
module image_processing_2d_design
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
LINESCANNER0_DATA,
LINESCANNER0_END_ADC,
LINESCANNER0_LOAD_PULSE,
LINESCANNER0_LVAL,
LINESCANNER0_MAIN_CLOCK,
LINESCANNER0_N_RESET,
LINESCANNER0_PIXEL_CLOCK,
LINESCANNER0_RST_CDS,
LINESCANNER0_RST_CVC,
LINESCANNER0_SAMPLE,
LINESCANNER1_DATA,
LINESCANNER1_END_ADC,
LINESCANNER1_LOAD_PULSE,
LINESCANNER1_LVAL,
LINESCANNER1_MAIN_CLOCK,
LINESCANNER1_N_RESET,
LINESCANNER1_PIXEL_CLOCK,
LINESCANNER1_RST_CDS,
LINESCANNER1_RST_CVC,
LINESCANNER1_SAMPLE,
LINESCANNER_CLK,
LINESCANNER_CS,
LINESCANNER_MISO,
LINESCANNER_MOSI);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input [7:0]LINESCANNER0_DATA;
input LINESCANNER0_END_ADC;
output LINESCANNER0_LOAD_PULSE;
input LINESCANNER0_LVAL;
output LINESCANNER0_MAIN_CLOCK;
output [0:0]LINESCANNER0_N_RESET;
input LINESCANNER0_PIXEL_CLOCK;
output LINESCANNER0_RST_CDS;
output LINESCANNER0_RST_CVC;
output LINESCANNER0_SAMPLE;
input [7:0]LINESCANNER1_DATA;
input LINESCANNER1_END_ADC;
output LINESCANNER1_LOAD_PULSE;
input LINESCANNER1_LVAL;
output LINESCANNER1_MAIN_CLOCK;
output [0:0]LINESCANNER1_N_RESET;
input LINESCANNER1_PIXEL_CLOCK;
output LINESCANNER1_RST_CDS;
output LINESCANNER1_RST_CVC;
output LINESCANNER1_SAMPLE;
output LINESCANNER_CLK;
output [1:0]LINESCANNER_CS;
input LINESCANNER_MISO;
output LINESCANNER_MOSI;
wire [7:0]LINESCANNER0_DATA_1;
wire LINESCANNER0_END_ADC_1;
wire LINESCANNER0_LVAL_1;
wire LINESCANNER0_PIXEL_CLOCK_1;
wire [7:0]LINESCANNER1_DATA_1;
wire LINESCANNER1_END_ADC_1;
wire LINESCANNER1_LVAL_1;
wire LINESCANNER1_PIXEL_CLOCK_1;
wire LINESCANNER_MISO_1;
wire [31:0]axi_interconnect_0_M01_AXI_ARADDR;
wire [2:0]axi_interconnect_0_M01_AXI_ARPROT;
wire axi_interconnect_0_M01_AXI_ARREADY;
wire axi_interconnect_0_M01_AXI_ARVALID;
wire [31:0]axi_interconnect_0_M01_AXI_AWADDR;
wire [2:0]axi_interconnect_0_M01_AXI_AWPROT;
wire axi_interconnect_0_M01_AXI_AWREADY;
wire axi_interconnect_0_M01_AXI_AWVALID;
wire axi_interconnect_0_M01_AXI_BREADY;
wire [1:0]axi_interconnect_0_M01_AXI_BRESP;
wire axi_interconnect_0_M01_AXI_BVALID;
wire [31:0]axi_interconnect_0_M01_AXI_RDATA;
wire axi_interconnect_0_M01_AXI_RREADY;
wire [1:0]axi_interconnect_0_M01_AXI_RRESP;
wire axi_interconnect_0_M01_AXI_RVALID;
wire [31:0]axi_interconnect_0_M01_AXI_WDATA;
wire axi_interconnect_0_M01_AXI_WREADY;
wire [3:0]axi_interconnect_0_M01_AXI_WSTRB;
wire axi_interconnect_0_M01_AXI_WVALID;
wire [31:0]axi_interconnect_0_M02_AXI_ARADDR;
wire [2:0]axi_interconnect_0_M02_AXI_ARPROT;
wire axi_interconnect_0_M02_AXI_ARREADY;
wire axi_interconnect_0_M02_AXI_ARVALID;
wire [31:0]axi_interconnect_0_M02_AXI_AWADDR;
wire [2:0]axi_interconnect_0_M02_AXI_AWPROT;
wire axi_interconnect_0_M02_AXI_AWREADY;
wire axi_interconnect_0_M02_AXI_AWVALID;
wire axi_interconnect_0_M02_AXI_BREADY;
wire [1:0]axi_interconnect_0_M02_AXI_BRESP;
wire axi_interconnect_0_M02_AXI_BVALID;
wire [31:0]axi_interconnect_0_M02_AXI_RDATA;
wire axi_interconnect_0_M02_AXI_RREADY;
wire [1:0]axi_interconnect_0_M02_AXI_RRESP;
wire axi_interconnect_0_M02_AXI_RVALID;
wire [31:0]axi_interconnect_0_M02_AXI_WDATA;
wire axi_interconnect_0_M02_AXI_WREADY;
wire [3:0]axi_interconnect_0_M02_AXI_WSTRB;
wire axi_interconnect_0_M02_AXI_WVALID;
wire [31:0]axi_interconnect_0_M03_AXI_ARADDR;
wire [2:0]axi_interconnect_0_M03_AXI_ARPROT;
wire axi_interconnect_0_M03_AXI_ARREADY;
wire axi_interconnect_0_M03_AXI_ARVALID;
wire [31:0]axi_interconnect_0_M03_AXI_AWADDR;
wire [2:0]axi_interconnect_0_M03_AXI_AWPROT;
wire axi_interconnect_0_M03_AXI_AWREADY;
wire axi_interconnect_0_M03_AXI_AWVALID;
wire axi_interconnect_0_M03_AXI_BREADY;
wire [1:0]axi_interconnect_0_M03_AXI_BRESP;
wire axi_interconnect_0_M03_AXI_BVALID;
wire [31:0]axi_interconnect_0_M03_AXI_RDATA;
wire axi_interconnect_0_M03_AXI_RREADY;
wire [1:0]axi_interconnect_0_M03_AXI_RRESP;
wire axi_interconnect_0_M03_AXI_RVALID;
wire [31:0]axi_interconnect_0_M03_AXI_WDATA;
wire axi_interconnect_0_M03_AXI_WREADY;
wire [3:0]axi_interconnect_0_M03_AXI_WSTRB;
wire axi_interconnect_0_M03_AXI_WVALID;
wire [31:0]axi_interconnect_0_M04_AXI_ARADDR;
wire [1:0]axi_interconnect_0_M04_AXI_ARBURST;
wire [3:0]axi_interconnect_0_M04_AXI_ARCACHE;
wire [3:0]axi_interconnect_0_M04_AXI_ARLEN;
wire [1:0]axi_interconnect_0_M04_AXI_ARLOCK;
wire [2:0]axi_interconnect_0_M04_AXI_ARPROT;
wire [3:0]axi_interconnect_0_M04_AXI_ARQOS;
wire axi_interconnect_0_M04_AXI_ARREADY;
wire [2:0]axi_interconnect_0_M04_AXI_ARSIZE;
wire axi_interconnect_0_M04_AXI_ARVALID;
wire [31:0]axi_interconnect_0_M04_AXI_AWADDR;
wire [1:0]axi_interconnect_0_M04_AXI_AWBURST;
wire [3:0]axi_interconnect_0_M04_AXI_AWCACHE;
wire [3:0]axi_interconnect_0_M04_AXI_AWLEN;
wire [1:0]axi_interconnect_0_M04_AXI_AWLOCK;
wire [2:0]axi_interconnect_0_M04_AXI_AWPROT;
wire [3:0]axi_interconnect_0_M04_AXI_AWQOS;
wire axi_interconnect_0_M04_AXI_AWREADY;
wire [2:0]axi_interconnect_0_M04_AXI_AWSIZE;
wire axi_interconnect_0_M04_AXI_AWVALID;
wire axi_interconnect_0_M04_AXI_BREADY;
wire [1:0]axi_interconnect_0_M04_AXI_BRESP;
wire axi_interconnect_0_M04_AXI_BVALID;
wire [31:0]axi_interconnect_0_M04_AXI_RDATA;
wire axi_interconnect_0_M04_AXI_RLAST;
wire axi_interconnect_0_M04_AXI_RREADY;
wire [1:0]axi_interconnect_0_M04_AXI_RRESP;
wire axi_interconnect_0_M04_AXI_RVALID;
wire [31:0]axi_interconnect_0_M04_AXI_WDATA;
wire axi_interconnect_0_M04_AXI_WLAST;
wire axi_interconnect_0_M04_AXI_WREADY;
wire [3:0]axi_interconnect_0_M04_AXI_WSTRB;
wire axi_interconnect_0_M04_AXI_WVALID;
wire dragster_configurator_0_mosi;
wire dragster_configurator_0_sclk;
wire [1:0]dragster_configurator_0_ss_n;
wire frequency_analyzer_manager_0_irq;
wire frequency_analyzer_manager_1_irq;
wire frequency_analyzer_synch_0_start_analyzer_0;
wire frequency_analyzer_synch_0_start_analyzer_1;
wire frequency_analyzer_synch_0_stop_analyzer_0;
wire frequency_analyzer_synch_0_stop_analyzer_1;
wire image_capture_manager_0_clear_memory;
wire image_capture_manager_0_image_capture_enabled;
wire image_capture_manager_0_reset;
wire linescanner_image_capture_unit_0_load_pulse;
wire linescanner_image_capture_unit_0_main_clock;
wire linescanner_image_capture_unit_0_pixel_captured;
(* MARK_DEBUG *) wire [7:0]linescanner_image_capture_unit_0_pixel_data;
wire linescanner_image_capture_unit_0_rst_cds;
wire linescanner_image_capture_unit_0_rst_cvc;
wire linescanner_image_capture_unit_0_sample;
wire linescanner_image_capture_unit_1_load_pulse;
wire linescanner_image_capture_unit_1_main_clock;
wire linescanner_image_capture_unit_1_pixel_captured;
wire [7:0]linescanner_image_capture_unit_1_pixel_data;
wire linescanner_image_capture_unit_1_rst_cds;
wire linescanner_image_capture_unit_1_rst_cvc;
wire linescanner_image_capture_unit_1_sample;
wire proc_sys_reset_0_peripheral_aresetn;
wire [0:0]proc_sys_reset_0_peripheral_reset;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_CLK0;
wire processing_system7_0_FCLK_CLK1;
wire processing_system7_0_FCLK_CLK2;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [1:0]xlconcat_0_dout;
assign LINESCANNER0_DATA_1 = LINESCANNER0_DATA[7:0];
assign LINESCANNER0_END_ADC_1 = LINESCANNER0_END_ADC;
assign LINESCANNER0_LOAD_PULSE = linescanner_image_capture_unit_0_load_pulse;
assign LINESCANNER0_LVAL_1 = LINESCANNER0_LVAL;
assign LINESCANNER0_MAIN_CLOCK = linescanner_image_capture_unit_0_main_clock;
assign LINESCANNER0_N_RESET[0] = proc_sys_reset_0_peripheral_aresetn;
assign LINESCANNER0_PIXEL_CLOCK_1 = LINESCANNER0_PIXEL_CLOCK;
assign LINESCANNER0_RST_CDS = linescanner_image_capture_unit_0_rst_cds;
assign LINESCANNER0_RST_CVC = linescanner_image_capture_unit_0_rst_cvc;
assign LINESCANNER0_SAMPLE = linescanner_image_capture_unit_0_sample;
assign LINESCANNER1_DATA_1 = LINESCANNER1_DATA[7:0];
assign LINESCANNER1_END_ADC_1 = LINESCANNER1_END_ADC;
assign LINESCANNER1_LOAD_PULSE = linescanner_image_capture_unit_1_load_pulse;
assign LINESCANNER1_LVAL_1 = LINESCANNER1_LVAL;
assign LINESCANNER1_MAIN_CLOCK = linescanner_image_capture_unit_1_main_clock;
assign LINESCANNER1_N_RESET[0] = proc_sys_reset_0_peripheral_aresetn;
assign LINESCANNER1_PIXEL_CLOCK_1 = LINESCANNER1_PIXEL_CLOCK;
assign LINESCANNER1_RST_CDS = linescanner_image_capture_unit_1_rst_cds;
assign LINESCANNER1_RST_CVC = linescanner_image_capture_unit_1_rst_cvc;
assign LINESCANNER1_SAMPLE = linescanner_image_capture_unit_1_sample;
assign LINESCANNER_CLK = dragster_configurator_0_sclk;
assign LINESCANNER_CS[1:0] = dragster_configurator_0_ss_n;
assign LINESCANNER_MISO_1 = LINESCANNER_MISO;
assign LINESCANNER_MOSI = dragster_configurator_0_mosi;
image_processing_2d_design_axi_interconnect_0_0 axi_interconnect_0
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(proc_sys_reset_0_peripheral_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(proc_sys_reset_0_peripheral_aresetn),
.M00_AXI_arready(1'b0),
.M00_AXI_awready(1'b0),
.M00_AXI_bresp(1'b0),
.M00_AXI_bvalid(1'b0),
.M00_AXI_rdata(1'b0),
.M00_AXI_rlast(1'b0),
.M00_AXI_rresp(1'b0),
.M00_AXI_rvalid(1'b0),
.M00_AXI_wready(1'b0),
.M01_ACLK(processing_system7_0_FCLK_CLK0),
.M01_ARESETN(proc_sys_reset_0_peripheral_aresetn),
.M01_AXI_araddr(axi_interconnect_0_M01_AXI_ARADDR),
.M01_AXI_arprot(axi_interconnect_0_M01_AXI_ARPROT),
.M01_AXI_arready(axi_interconnect_0_M01_AXI_ARREADY),
.M01_AXI_arvalid(axi_interconnect_0_M01_AXI_ARVALID),
.M01_AXI_awaddr(axi_interconnect_0_M01_AXI_AWADDR),
.M01_AXI_awprot(axi_interconnect_0_M01_AXI_AWPROT),
.M01_AXI_awready(axi_interconnect_0_M01_AXI_AWREADY),
.M01_AXI_awvalid(axi_interconnect_0_M01_AXI_AWVALID),
.M01_AXI_bready(axi_interconnect_0_M01_AXI_BREADY),
.M01_AXI_bresp(axi_interconnect_0_M01_AXI_BRESP),
.M01_AXI_bvalid(axi_interconnect_0_M01_AXI_BVALID),
.M01_AXI_rdata(axi_interconnect_0_M01_AXI_RDATA),
.M01_AXI_rready(axi_interconnect_0_M01_AXI_RREADY),
.M01_AXI_rresp(axi_interconnect_0_M01_AXI_RRESP),
.M01_AXI_rvalid(axi_interconnect_0_M01_AXI_RVALID),
.M01_AXI_wdata(axi_interconnect_0_M01_AXI_WDATA),
.M01_AXI_wready(axi_interconnect_0_M01_AXI_WREADY),
.M01_AXI_wstrb(axi_interconnect_0_M01_AXI_WSTRB),
.M01_AXI_wvalid(axi_interconnect_0_M01_AXI_WVALID),
.M02_ACLK(processing_system7_0_FCLK_CLK0),
.M02_ARESETN(proc_sys_reset_0_peripheral_aresetn),
.M02_AXI_araddr(axi_interconnect_0_M02_AXI_ARADDR),
.M02_AXI_arprot(axi_interconnect_0_M02_AXI_ARPROT),
.M02_AXI_arready(axi_interconnect_0_M02_AXI_ARREADY),
.M02_AXI_arvalid(axi_interconnect_0_M02_AXI_ARVALID),
.M02_AXI_awaddr(axi_interconnect_0_M02_AXI_AWADDR),
.M02_AXI_awprot(axi_interconnect_0_M02_AXI_AWPROT),
.M02_AXI_awready(axi_interconnect_0_M02_AXI_AWREADY),
.M02_AXI_awvalid(axi_interconnect_0_M02_AXI_AWVALID),
.M02_AXI_bready(axi_interconnect_0_M02_AXI_BREADY),
.M02_AXI_bresp(axi_interconnect_0_M02_AXI_BRESP),
.M02_AXI_bvalid(axi_interconnect_0_M02_AXI_BVALID),
.M02_AXI_rdata(axi_interconnect_0_M02_AXI_RDATA),
.M02_AXI_rready(axi_interconnect_0_M02_AXI_RREADY),
.M02_AXI_rresp(axi_interconnect_0_M02_AXI_RRESP),
.M02_AXI_rvalid(axi_interconnect_0_M02_AXI_RVALID),
.M02_AXI_wdata(axi_interconnect_0_M02_AXI_WDATA),
.M02_AXI_wready(axi_interconnect_0_M02_AXI_WREADY),
.M02_AXI_wstrb(axi_interconnect_0_M02_AXI_WSTRB),
.M02_AXI_wvalid(axi_interconnect_0_M02_AXI_WVALID),
.M03_ACLK(processing_system7_0_FCLK_CLK0),
.M03_ARESETN(proc_sys_reset_0_peripheral_aresetn),
.M03_AXI_araddr(axi_interconnect_0_M03_AXI_ARADDR),
.M03_AXI_arprot(axi_interconnect_0_M03_AXI_ARPROT),
.M03_AXI_arready(axi_interconnect_0_M03_AXI_ARREADY),
.M03_AXI_arvalid(axi_interconnect_0_M03_AXI_ARVALID),
.M03_AXI_awaddr(axi_interconnect_0_M03_AXI_AWADDR),
.M03_AXI_awprot(axi_interconnect_0_M03_AXI_AWPROT),
.M03_AXI_awready(axi_interconnect_0_M03_AXI_AWREADY),
.M03_AXI_awvalid(axi_interconnect_0_M03_AXI_AWVALID),
.M03_AXI_bready(axi_interconnect_0_M03_AXI_BREADY),
.M03_AXI_bresp(axi_interconnect_0_M03_AXI_BRESP),
.M03_AXI_bvalid(axi_interconnect_0_M03_AXI_BVALID),
.M03_AXI_rdata(axi_interconnect_0_M03_AXI_RDATA),
.M03_AXI_rready(axi_interconnect_0_M03_AXI_RREADY),
.M03_AXI_rresp(axi_interconnect_0_M03_AXI_RRESP),
.M03_AXI_rvalid(axi_interconnect_0_M03_AXI_RVALID),
.M03_AXI_wdata(axi_interconnect_0_M03_AXI_WDATA),
.M03_AXI_wready(axi_interconnect_0_M03_AXI_WREADY),
.M03_AXI_wstrb(axi_interconnect_0_M03_AXI_WSTRB),
.M03_AXI_wvalid(axi_interconnect_0_M03_AXI_WVALID),
.M04_ACLK(processing_system7_0_FCLK_CLK0),
.M04_ARESETN(proc_sys_reset_0_peripheral_aresetn),
.M04_AXI_araddr(axi_interconnect_0_M04_AXI_ARADDR),
.M04_AXI_arburst(axi_interconnect_0_M04_AXI_ARBURST),
.M04_AXI_arcache(axi_interconnect_0_M04_AXI_ARCACHE),
.M04_AXI_arlen(axi_interconnect_0_M04_AXI_ARLEN),
.M04_AXI_arlock(axi_interconnect_0_M04_AXI_ARLOCK),
.M04_AXI_arprot(axi_interconnect_0_M04_AXI_ARPROT),
.M04_AXI_arqos(axi_interconnect_0_M04_AXI_ARQOS),
.M04_AXI_arready(axi_interconnect_0_M04_AXI_ARREADY),
.M04_AXI_arsize(axi_interconnect_0_M04_AXI_ARSIZE),
.M04_AXI_arvalid(axi_interconnect_0_M04_AXI_ARVALID),
.M04_AXI_awaddr(axi_interconnect_0_M04_AXI_AWADDR),
.M04_AXI_awburst(axi_interconnect_0_M04_AXI_AWBURST),
.M04_AXI_awcache(axi_interconnect_0_M04_AXI_AWCACHE),
.M04_AXI_awlen(axi_interconnect_0_M04_AXI_AWLEN),
.M04_AXI_awlock(axi_interconnect_0_M04_AXI_AWLOCK),
.M04_AXI_awprot(axi_interconnect_0_M04_AXI_AWPROT),
.M04_AXI_awqos(axi_interconnect_0_M04_AXI_AWQOS),
.M04_AXI_awready(axi_interconnect_0_M04_AXI_AWREADY),
.M04_AXI_awsize(axi_interconnect_0_M04_AXI_AWSIZE),
.M04_AXI_awvalid(axi_interconnect_0_M04_AXI_AWVALID),
.M04_AXI_bready(axi_interconnect_0_M04_AXI_BREADY),
.M04_AXI_bresp(axi_interconnect_0_M04_AXI_BRESP),
.M04_AXI_bvalid(axi_interconnect_0_M04_AXI_BVALID),
.M04_AXI_rdata(axi_interconnect_0_M04_AXI_RDATA),
.M04_AXI_rlast(axi_interconnect_0_M04_AXI_RLAST),
.M04_AXI_rready(axi_interconnect_0_M04_AXI_RREADY),
.M04_AXI_rresp(axi_interconnect_0_M04_AXI_RRESP),
.M04_AXI_rvalid(axi_interconnect_0_M04_AXI_RVALID),
.M04_AXI_wdata(axi_interconnect_0_M04_AXI_WDATA),
.M04_AXI_wlast(axi_interconnect_0_M04_AXI_WLAST),
.M04_AXI_wready(axi_interconnect_0_M04_AXI_WREADY),
.M04_AXI_wstrb(axi_interconnect_0_M04_AXI_WSTRB),
.M04_AXI_wvalid(axi_interconnect_0_M04_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(proc_sys_reset_0_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID),
.S01_ACLK(processing_system7_0_FCLK_CLK0),
.S01_ARESETN(proc_sys_reset_0_peripheral_aresetn),
.S01_AXI_araddr(1'b0),
.S01_AXI_arburst(1'b0),
.S01_AXI_arcache(1'b0),
.S01_AXI_arid(1'b0),
.S01_AXI_arlen(1'b0),
.S01_AXI_arlock(1'b0),
.S01_AXI_arprot(1'b0),
.S01_AXI_arqos(1'b0),
.S01_AXI_arsize(1'b0),
.S01_AXI_arvalid(1'b0),
.S01_AXI_awaddr(1'b0),
.S01_AXI_awburst(1'b0),
.S01_AXI_awcache(1'b0),
.S01_AXI_awid(1'b0),
.S01_AXI_awlen(1'b0),
.S01_AXI_awlock(1'b0),
.S01_AXI_awprot(1'b0),
.S01_AXI_awqos(1'b0),
.S01_AXI_awsize(1'b0),
.S01_AXI_awvalid(1'b0),
.S01_AXI_bready(1'b0),
.S01_AXI_rready(1'b0),
.S01_AXI_wdata(1'b0),
.S01_AXI_wlast(1'b0),
.S01_AXI_wstrb(1'b0),
.S01_AXI_wvalid(1'b0));
image_processing_2d_design_dragster_configurator_0_0 dragster_configurator_0
(.clk(processing_system7_0_FCLK_CLK2),
.miso(LINESCANNER_MISO_1),
.mosi(dragster_configurator_0_mosi),
.reset_n(proc_sys_reset_0_peripheral_aresetn),
.sclk(dragster_configurator_0_sclk),
.ss_n(dragster_configurator_0_ss_n));
image_processing_2d_design_frequency_analyzer_manager_0_1 frequency_analyzer_manager_0
(.clear(image_capture_manager_0_clear_memory),
.data(linescanner_image_capture_unit_0_pixel_data),
.irq(frequency_analyzer_manager_1_irq),
.pixel_clock(linescanner_image_capture_unit_0_pixel_captured),
.s00_axi_aclk(processing_system7_0_FCLK_CLK0),
.s00_axi_araddr(axi_interconnect_0_M02_AXI_ARADDR[9:0]),
.s00_axi_aresetn(proc_sys_reset_0_peripheral_aresetn),
.s00_axi_arprot(axi_interconnect_0_M02_AXI_ARPROT),
.s00_axi_arready(axi_interconnect_0_M02_AXI_ARREADY),
.s00_axi_arvalid(axi_interconnect_0_M02_AXI_ARVALID),
.s00_axi_awaddr(axi_interconnect_0_M02_AXI_AWADDR[9:0]),
.s00_axi_awprot(axi_interconnect_0_M02_AXI_AWPROT),
.s00_axi_awready(axi_interconnect_0_M02_AXI_AWREADY),
.s00_axi_awvalid(axi_interconnect_0_M02_AXI_AWVALID),
.s00_axi_bready(axi_interconnect_0_M02_AXI_BREADY),
.s00_axi_bresp(axi_interconnect_0_M02_AXI_BRESP),
.s00_axi_bvalid(axi_interconnect_0_M02_AXI_BVALID),
.s00_axi_rdata(axi_interconnect_0_M02_AXI_RDATA),
.s00_axi_rready(axi_interconnect_0_M02_AXI_RREADY),
.s00_axi_rresp(axi_interconnect_0_M02_AXI_RRESP),
.s00_axi_rvalid(axi_interconnect_0_M02_AXI_RVALID),
.s00_axi_wdata(axi_interconnect_0_M02_AXI_WDATA),
.s00_axi_wready(axi_interconnect_0_M02_AXI_WREADY),
.s00_axi_wstrb(axi_interconnect_0_M02_AXI_WSTRB),
.s00_axi_wvalid(axi_interconnect_0_M02_AXI_WVALID),
.start(frequency_analyzer_synch_0_start_analyzer_0),
.stop(frequency_analyzer_synch_0_stop_analyzer_0));
image_processing_2d_design_frequency_analyzer_manager_1_0 frequency_analyzer_manager_1
(.clear(image_capture_manager_0_clear_memory),
.data(linescanner_image_capture_unit_1_pixel_data),
.irq(frequency_analyzer_manager_0_irq),
.pixel_clock(linescanner_image_capture_unit_1_pixel_captured),
.s00_axi_aclk(processing_system7_0_FCLK_CLK0),
.s00_axi_araddr(axi_interconnect_0_M03_AXI_ARADDR[9:0]),
.s00_axi_aresetn(proc_sys_reset_0_peripheral_aresetn),
.s00_axi_arprot(axi_interconnect_0_M03_AXI_ARPROT),
.s00_axi_arready(axi_interconnect_0_M03_AXI_ARREADY),
.s00_axi_arvalid(axi_interconnect_0_M03_AXI_ARVALID),
.s00_axi_awaddr(axi_interconnect_0_M03_AXI_AWADDR[9:0]),
.s00_axi_awprot(axi_interconnect_0_M03_AXI_AWPROT),
.s00_axi_awready(axi_interconnect_0_M03_AXI_AWREADY),
.s00_axi_awvalid(axi_interconnect_0_M03_AXI_AWVALID),
.s00_axi_bready(axi_interconnect_0_M03_AXI_BREADY),
.s00_axi_bresp(axi_interconnect_0_M03_AXI_BRESP),
.s00_axi_bvalid(axi_interconnect_0_M03_AXI_BVALID),
.s00_axi_rdata(axi_interconnect_0_M03_AXI_RDATA),
.s00_axi_rready(axi_interconnect_0_M03_AXI_RREADY),
.s00_axi_rresp(axi_interconnect_0_M03_AXI_RRESP),
.s00_axi_rvalid(axi_interconnect_0_M03_AXI_RVALID),
.s00_axi_wdata(axi_interconnect_0_M03_AXI_WDATA),
.s00_axi_wready(axi_interconnect_0_M03_AXI_WREADY),
.s00_axi_wstrb(axi_interconnect_0_M03_AXI_WSTRB),
.s00_axi_wvalid(axi_interconnect_0_M03_AXI_WVALID),
.start(frequency_analyzer_synch_0_start_analyzer_1),
.stop(frequency_analyzer_synch_0_stop_analyzer_1));
image_processing_2d_design_frequency_analyzer_synch_0_0 frequency_analyzer_synch_0
(.clock(processing_system7_0_FCLK_CLK0),
.enable(image_capture_manager_0_image_capture_enabled),
.reset(proc_sys_reset_0_peripheral_aresetn),
.start_analyzer_0(frequency_analyzer_synch_0_start_analyzer_0),
.start_analyzer_1(frequency_analyzer_synch_0_start_analyzer_1),
.stop_analyzer_0(frequency_analyzer_synch_0_stop_analyzer_0),
.stop_analyzer_1(frequency_analyzer_synch_0_stop_analyzer_1));
image_processing_2d_design_image_capture_manager_0_0 image_capture_manager_0
(.clear_memory(image_capture_manager_0_clear_memory),
.image_capture_enabled(image_capture_manager_0_image_capture_enabled),
.reset(image_capture_manager_0_reset),
.s00_axi_aclk(processing_system7_0_FCLK_CLK0),
.s00_axi_araddr(axi_interconnect_0_M01_AXI_ARADDR[3:0]),
.s00_axi_aresetn(proc_sys_reset_0_peripheral_aresetn),
.s00_axi_arprot(axi_interconnect_0_M01_AXI_ARPROT),
.s00_axi_arready(axi_interconnect_0_M01_AXI_ARREADY),
.s00_axi_arvalid(axi_interconnect_0_M01_AXI_ARVALID),
.s00_axi_awaddr(axi_interconnect_0_M01_AXI_AWADDR[3:0]),
.s00_axi_awprot(axi_interconnect_0_M01_AXI_AWPROT),
.s00_axi_awready(axi_interconnect_0_M01_AXI_AWREADY),
.s00_axi_awvalid(axi_interconnect_0_M01_AXI_AWVALID),
.s00_axi_bready(axi_interconnect_0_M01_AXI_BREADY),
.s00_axi_bresp(axi_interconnect_0_M01_AXI_BRESP),
.s00_axi_bvalid(axi_interconnect_0_M01_AXI_BVALID),
.s00_axi_rdata(axi_interconnect_0_M01_AXI_RDATA),
.s00_axi_rready(axi_interconnect_0_M01_AXI_RREADY),
.s00_axi_rresp(axi_interconnect_0_M01_AXI_RRESP),
.s00_axi_rvalid(axi_interconnect_0_M01_AXI_RVALID),
.s00_axi_wdata(axi_interconnect_0_M01_AXI_WDATA),
.s00_axi_wready(axi_interconnect_0_M01_AXI_WREADY),
.s00_axi_wstrb(axi_interconnect_0_M01_AXI_WSTRB),
.s00_axi_wvalid(axi_interconnect_0_M01_AXI_WVALID));
image_processing_2d_design_linescanner_image_capture_unit_0_1 linescanner_image_capture_unit_0
(.data(LINESCANNER0_DATA_1),
.enable(image_capture_manager_0_image_capture_enabled),
.end_adc(LINESCANNER0_END_ADC_1),
.load_pulse(linescanner_image_capture_unit_0_load_pulse),
.lval(LINESCANNER0_LVAL_1),
.main_clock(linescanner_image_capture_unit_0_main_clock),
.main_clock_source(processing_system7_0_FCLK_CLK1),
.n_reset(proc_sys_reset_0_peripheral_aresetn),
.pixel_captured(linescanner_image_capture_unit_0_pixel_captured),
.pixel_clock(LINESCANNER0_PIXEL_CLOCK_1),
.pixel_data(linescanner_image_capture_unit_0_pixel_data),
.rst_cds(linescanner_image_capture_unit_0_rst_cds),
.rst_cvc(linescanner_image_capture_unit_0_rst_cvc),
.sample(linescanner_image_capture_unit_0_sample));
image_processing_2d_design_linescanner_image_capture_unit_1_1 linescanner_image_capture_unit_1
(.data(LINESCANNER1_DATA_1),
.enable(image_capture_manager_0_image_capture_enabled),
.end_adc(LINESCANNER1_END_ADC_1),
.load_pulse(linescanner_image_capture_unit_1_load_pulse),
.lval(LINESCANNER1_LVAL_1),
.main_clock(linescanner_image_capture_unit_1_main_clock),
.main_clock_source(processing_system7_0_FCLK_CLK1),
.n_reset(proc_sys_reset_0_peripheral_aresetn),
.pixel_captured(linescanner_image_capture_unit_1_pixel_captured),
.pixel_clock(LINESCANNER1_PIXEL_CLOCK_1),
.pixel_data(linescanner_image_capture_unit_1_pixel_data),
.rst_cds(linescanner_image_capture_unit_1_rst_cds),
.rst_cvc(linescanner_image_capture_unit_1_rst_cvc),
.sample(linescanner_image_capture_unit_1_sample));
image_processing_2d_design_not_1bit_0_0 not_1bit_0
(.inp(proc_sys_reset_0_peripheral_reset),
.outp(proc_sys_reset_0_peripheral_aresetn));
image_processing_2d_design_proc_sys_reset_0_1 proc_sys_reset_0
(.aux_reset_in(image_capture_manager_0_reset),
.dcm_locked(1'b1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.mb_debug_sys_rst(1'b0),
.peripheral_reset(proc_sys_reset_0_peripheral_reset),
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
image_processing_2d_design_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
.FCLK_CLK1(processing_system7_0_FCLK_CLK1),
.FCLK_CLK2(processing_system7_0_FCLK_CLK2),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.GPIO_I({1'b0,1'b0,1'b0,1'b0}),
.IRQ_F2P(xlconcat_0_dout),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.S_AXI_HP0_ACLK(processing_system7_0_FCLK_CLK0),
.S_AXI_HP0_ARADDR(axi_interconnect_0_M04_AXI_ARADDR),
.S_AXI_HP0_ARBURST(axi_interconnect_0_M04_AXI_ARBURST),
.S_AXI_HP0_ARCACHE(axi_interconnect_0_M04_AXI_ARCACHE),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN(axi_interconnect_0_M04_AXI_ARLEN),
.S_AXI_HP0_ARLOCK(axi_interconnect_0_M04_AXI_ARLOCK),
.S_AXI_HP0_ARPROT(axi_interconnect_0_M04_AXI_ARPROT),
.S_AXI_HP0_ARQOS(axi_interconnect_0_M04_AXI_ARQOS),
.S_AXI_HP0_ARREADY(axi_interconnect_0_M04_AXI_ARREADY),
.S_AXI_HP0_ARSIZE(axi_interconnect_0_M04_AXI_ARSIZE),
.S_AXI_HP0_ARVALID(axi_interconnect_0_M04_AXI_ARVALID),
.S_AXI_HP0_AWADDR(axi_interconnect_0_M04_AXI_AWADDR),
.S_AXI_HP0_AWBURST(axi_interconnect_0_M04_AXI_AWBURST),
.S_AXI_HP0_AWCACHE(axi_interconnect_0_M04_AXI_AWCACHE),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN(axi_interconnect_0_M04_AXI_AWLEN),
.S_AXI_HP0_AWLOCK(axi_interconnect_0_M04_AXI_AWLOCK),
.S_AXI_HP0_AWPROT(axi_interconnect_0_M04_AXI_AWPROT),
.S_AXI_HP0_AWQOS(axi_interconnect_0_M04_AXI_AWQOS),
.S_AXI_HP0_AWREADY(axi_interconnect_0_M04_AXI_AWREADY),
.S_AXI_HP0_AWSIZE(axi_interconnect_0_M04_AXI_AWSIZE),
.S_AXI_HP0_AWVALID(axi_interconnect_0_M04_AXI_AWVALID),
.S_AXI_HP0_BREADY(axi_interconnect_0_M04_AXI_BREADY),
.S_AXI_HP0_BRESP(axi_interconnect_0_M04_AXI_BRESP),
.S_AXI_HP0_BVALID(axi_interconnect_0_M04_AXI_BVALID),
.S_AXI_HP0_RDATA(axi_interconnect_0_M04_AXI_RDATA),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RLAST(axi_interconnect_0_M04_AXI_RLAST),
.S_AXI_HP0_RREADY(axi_interconnect_0_M04_AXI_RREADY),
.S_AXI_HP0_RRESP(axi_interconnect_0_M04_AXI_RRESP),
.S_AXI_HP0_RVALID(axi_interconnect_0_M04_AXI_RVALID),
.S_AXI_HP0_WDATA(axi_interconnect_0_M04_AXI_WDATA),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(axi_interconnect_0_M04_AXI_WLAST),
.S_AXI_HP0_WREADY(axi_interconnect_0_M04_AXI_WREADY),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB(axi_interconnect_0_M04_AXI_WSTRB),
.S_AXI_HP0_WVALID(axi_interconnect_0_M04_AXI_WVALID));
image_processing_2d_design_xlconcat_0_0 xlconcat_0
(.In0(frequency_analyzer_manager_1_irq),
.In1(frequency_analyzer_manager_0_irq),
.dout(xlconcat_0_dout));
endmodule
module image_processing_2d_design_axi_interconnect_0_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arqos,
M00_AXI_arready,
M00_AXI_arregion,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awregion,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arprot,
M01_AXI_arready,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awprot,
M01_AXI_awready,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wready,
M01_AXI_wstrb,
M01_AXI_wvalid,
M02_ACLK,
M02_ARESETN,
M02_AXI_araddr,
M02_AXI_arprot,
M02_AXI_arready,
M02_AXI_arvalid,
M02_AXI_awaddr,
M02_AXI_awprot,
M02_AXI_awready,
M02_AXI_awvalid,
M02_AXI_bready,
M02_AXI_bresp,
M02_AXI_bvalid,
M02_AXI_rdata,
M02_AXI_rready,
M02_AXI_rresp,
M02_AXI_rvalid,
M02_AXI_wdata,
M02_AXI_wready,
M02_AXI_wstrb,
M02_AXI_wvalid,
M03_ACLK,
M03_ARESETN,
M03_AXI_araddr,
M03_AXI_arprot,
M03_AXI_arready,
M03_AXI_arvalid,
M03_AXI_awaddr,
M03_AXI_awprot,
M03_AXI_awready,
M03_AXI_awvalid,
M03_AXI_bready,
M03_AXI_bresp,
M03_AXI_bvalid,
M03_AXI_rdata,
M03_AXI_rready,
M03_AXI_rresp,
M03_AXI_rvalid,
M03_AXI_wdata,
M03_AXI_wready,
M03_AXI_wstrb,
M03_AXI_wvalid,
M04_ACLK,
M04_ARESETN,
M04_AXI_araddr,
M04_AXI_arburst,
M04_AXI_arcache,
M04_AXI_arlen,
M04_AXI_arlock,
M04_AXI_arprot,
M04_AXI_arqos,
M04_AXI_arready,
M04_AXI_arsize,
M04_AXI_arvalid,
M04_AXI_awaddr,
M04_AXI_awburst,
M04_AXI_awcache,
M04_AXI_awlen,
M04_AXI_awlock,
M04_AXI_awprot,
M04_AXI_awqos,
M04_AXI_awready,
M04_AXI_awsize,
M04_AXI_awvalid,
M04_AXI_bready,
M04_AXI_bresp,
M04_AXI_bvalid,
M04_AXI_rdata,
M04_AXI_rlast,
M04_AXI_rready,
M04_AXI_rresp,
M04_AXI_rvalid,
M04_AXI_wdata,
M04_AXI_wlast,
M04_AXI_wready,
M04_AXI_wstrb,
M04_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid,
S01_ACLK,
S01_ARESETN,
S01_AXI_araddr,
S01_AXI_arburst,
S01_AXI_arcache,
S01_AXI_arid,
S01_AXI_arlen,
S01_AXI_arlock,
S01_AXI_arprot,
S01_AXI_arqos,
S01_AXI_arready,
S01_AXI_arsize,
S01_AXI_arvalid,
S01_AXI_awaddr,
S01_AXI_awburst,
S01_AXI_awcache,
S01_AXI_awid,
S01_AXI_awlen,
S01_AXI_awlock,
S01_AXI_awprot,
S01_AXI_awqos,
S01_AXI_awready,
S01_AXI_awsize,
S01_AXI_awvalid,
S01_AXI_bid,
S01_AXI_bready,
S01_AXI_bresp,
S01_AXI_bvalid,
S01_AXI_rdata,
S01_AXI_rid,
S01_AXI_rlast,
S01_AXI_rready,
S01_AXI_rresp,
S01_AXI_rvalid,
S01_AXI_wdata,
S01_AXI_wlast,
S01_AXI_wready,
S01_AXI_wstrb,
S01_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output M00_AXI_araddr;
output M00_AXI_arburst;
output M00_AXI_arcache;
output M00_AXI_arlen;
output M00_AXI_arlock;
output M00_AXI_arprot;
output M00_AXI_arqos;
input M00_AXI_arready;
output M00_AXI_arregion;
output M00_AXI_arsize;
output M00_AXI_arvalid;
output M00_AXI_awaddr;
output M00_AXI_awburst;
output M00_AXI_awcache;
output M00_AXI_awlen;
output M00_AXI_awlock;
output M00_AXI_awprot;
output M00_AXI_awqos;
input M00_AXI_awready;
output M00_AXI_awregion;
output M00_AXI_awsize;
output M00_AXI_awvalid;
output M00_AXI_bready;
input M00_AXI_bresp;
input M00_AXI_bvalid;
input M00_AXI_rdata;
input M00_AXI_rlast;
output M00_AXI_rready;
input M00_AXI_rresp;
input M00_AXI_rvalid;
output M00_AXI_wdata;
output M00_AXI_wlast;
input M00_AXI_wready;
output M00_AXI_wstrb;
output M00_AXI_wvalid;
input M01_ACLK;
input [0:0]M01_ARESETN;
output [31:0]M01_AXI_araddr;
output [2:0]M01_AXI_arprot;
input M01_AXI_arready;
output M01_AXI_arvalid;
output [31:0]M01_AXI_awaddr;
output [2:0]M01_AXI_awprot;
input M01_AXI_awready;
output M01_AXI_awvalid;
output M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
output M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
input M01_AXI_wready;
output [3:0]M01_AXI_wstrb;
output M01_AXI_wvalid;
input M02_ACLK;
input [0:0]M02_ARESETN;
output [31:0]M02_AXI_araddr;
output [2:0]M02_AXI_arprot;
input M02_AXI_arready;
output M02_AXI_arvalid;
output [31:0]M02_AXI_awaddr;
output [2:0]M02_AXI_awprot;
input M02_AXI_awready;
output M02_AXI_awvalid;
output M02_AXI_bready;
input [1:0]M02_AXI_bresp;
input M02_AXI_bvalid;
input [31:0]M02_AXI_rdata;
output M02_AXI_rready;
input [1:0]M02_AXI_rresp;
input M02_AXI_rvalid;
output [31:0]M02_AXI_wdata;
input M02_AXI_wready;
output [3:0]M02_AXI_wstrb;
output M02_AXI_wvalid;
input M03_ACLK;
input [0:0]M03_ARESETN;
output [31:0]M03_AXI_araddr;
output [2:0]M03_AXI_arprot;
input M03_AXI_arready;
output M03_AXI_arvalid;
output [31:0]M03_AXI_awaddr;
output [2:0]M03_AXI_awprot;
input M03_AXI_awready;
output M03_AXI_awvalid;
output M03_AXI_bready;
input [1:0]M03_AXI_bresp;
input M03_AXI_bvalid;
input [31:0]M03_AXI_rdata;
output M03_AXI_rready;
input [1:0]M03_AXI_rresp;
input M03_AXI_rvalid;
output [31:0]M03_AXI_wdata;
input M03_AXI_wready;
output [3:0]M03_AXI_wstrb;
output M03_AXI_wvalid;
input M04_ACLK;
input [0:0]M04_ARESETN;
output [31:0]M04_AXI_araddr;
output [1:0]M04_AXI_arburst;
output [3:0]M04_AXI_arcache;
output [3:0]M04_AXI_arlen;
output [1:0]M04_AXI_arlock;
output [2:0]M04_AXI_arprot;
output [3:0]M04_AXI_arqos;
input M04_AXI_arready;
output [2:0]M04_AXI_arsize;
output M04_AXI_arvalid;
output [31:0]M04_AXI_awaddr;
output [1:0]M04_AXI_awburst;
output [3:0]M04_AXI_awcache;
output [3:0]M04_AXI_awlen;
output [1:0]M04_AXI_awlock;
output [2:0]M04_AXI_awprot;
output [3:0]M04_AXI_awqos;
input M04_AXI_awready;
output [2:0]M04_AXI_awsize;
output M04_AXI_awvalid;
output M04_AXI_bready;
input [1:0]M04_AXI_bresp;
input M04_AXI_bvalid;
input [31:0]M04_AXI_rdata;
input M04_AXI_rlast;
output M04_AXI_rready;
input [1:0]M04_AXI_rresp;
input M04_AXI_rvalid;
output [31:0]M04_AXI_wdata;
output M04_AXI_wlast;
input M04_AXI_wready;
output [3:0]M04_AXI_wstrb;
output M04_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
input S01_ACLK;
input [0:0]S01_ARESETN;
input S01_AXI_araddr;
input S01_AXI_arburst;
input S01_AXI_arcache;
input S01_AXI_arid;
input S01_AXI_arlen;
input S01_AXI_arlock;
input S01_AXI_arprot;
input S01_AXI_arqos;
output S01_AXI_arready;
input S01_AXI_arsize;
input S01_AXI_arvalid;
input S01_AXI_awaddr;
input S01_AXI_awburst;
input S01_AXI_awcache;
input S01_AXI_awid;
input S01_AXI_awlen;
input S01_AXI_awlock;
input S01_AXI_awprot;
input S01_AXI_awqos;
output S01_AXI_awready;
input S01_AXI_awsize;
input S01_AXI_awvalid;
output S01_AXI_bid;
input S01_AXI_bready;
output S01_AXI_bresp;
output S01_AXI_bvalid;
output S01_AXI_rdata;
output S01_AXI_rid;
output S01_AXI_rlast;
input S01_AXI_rready;
output S01_AXI_rresp;
output S01_AXI_rvalid;
input S01_AXI_wdata;
input S01_AXI_wlast;
output S01_AXI_wready;
input S01_AXI_wstrb;
input S01_AXI_wvalid;
wire axi_interconnect_0_ACLK_net;
wire [0:0]axi_interconnect_0_ARESETN_net;
wire [31:0]axi_interconnect_0_to_s00_couplers_ARADDR;
wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST;
wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE;
wire [11:0]axi_interconnect_0_to_s00_couplers_ARID;
wire [3:0]axi_interconnect_0_to_s00_couplers_ARLEN;
wire [1:0]axi_interconnect_0_to_s00_couplers_ARLOCK;
wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT;
wire [3:0]axi_interconnect_0_to_s00_couplers_ARQOS;
wire axi_interconnect_0_to_s00_couplers_ARREADY;
wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE;
wire axi_interconnect_0_to_s00_couplers_ARVALID;
wire [31:0]axi_interconnect_0_to_s00_couplers_AWADDR;
wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST;
wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE;
wire [11:0]axi_interconnect_0_to_s00_couplers_AWID;
wire [3:0]axi_interconnect_0_to_s00_couplers_AWLEN;
wire [1:0]axi_interconnect_0_to_s00_couplers_AWLOCK;
wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT;
wire [3:0]axi_interconnect_0_to_s00_couplers_AWQOS;
wire axi_interconnect_0_to_s00_couplers_AWREADY;
wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE;
wire axi_interconnect_0_to_s00_couplers_AWVALID;
wire [11:0]axi_interconnect_0_to_s00_couplers_BID;
wire axi_interconnect_0_to_s00_couplers_BREADY;
wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP;
wire axi_interconnect_0_to_s00_couplers_BVALID;
wire [31:0]axi_interconnect_0_to_s00_couplers_RDATA;
wire [11:0]axi_interconnect_0_to_s00_couplers_RID;
wire axi_interconnect_0_to_s00_couplers_RLAST;
wire axi_interconnect_0_to_s00_couplers_RREADY;
wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP;
wire axi_interconnect_0_to_s00_couplers_RVALID;
wire [31:0]axi_interconnect_0_to_s00_couplers_WDATA;
wire [11:0]axi_interconnect_0_to_s00_couplers_WID;
wire axi_interconnect_0_to_s00_couplers_WLAST;
wire axi_interconnect_0_to_s00_couplers_WREADY;
wire [3:0]axi_interconnect_0_to_s00_couplers_WSTRB;
wire axi_interconnect_0_to_s00_couplers_WVALID;
wire axi_interconnect_0_to_s01_couplers_ARADDR;
wire axi_interconnect_0_to_s01_couplers_ARBURST;
wire axi_interconnect_0_to_s01_couplers_ARCACHE;
wire axi_interconnect_0_to_s01_couplers_ARID;
wire axi_interconnect_0_to_s01_couplers_ARLEN;
wire axi_interconnect_0_to_s01_couplers_ARLOCK;
wire axi_interconnect_0_to_s01_couplers_ARPROT;
wire axi_interconnect_0_to_s01_couplers_ARQOS;
wire axi_interconnect_0_to_s01_couplers_ARREADY;
wire axi_interconnect_0_to_s01_couplers_ARSIZE;
wire axi_interconnect_0_to_s01_couplers_ARVALID;
wire axi_interconnect_0_to_s01_couplers_AWADDR;
wire axi_interconnect_0_to_s01_couplers_AWBURST;
wire axi_interconnect_0_to_s01_couplers_AWCACHE;
wire axi_interconnect_0_to_s01_couplers_AWID;
wire axi_interconnect_0_to_s01_couplers_AWLEN;
wire axi_interconnect_0_to_s01_couplers_AWLOCK;
wire axi_interconnect_0_to_s01_couplers_AWPROT;
wire axi_interconnect_0_to_s01_couplers_AWQOS;
wire axi_interconnect_0_to_s01_couplers_AWREADY;
wire axi_interconnect_0_to_s01_couplers_AWSIZE;
wire axi_interconnect_0_to_s01_couplers_AWVALID;
wire axi_interconnect_0_to_s01_couplers_BID;
wire axi_interconnect_0_to_s01_couplers_BREADY;
wire axi_interconnect_0_to_s01_couplers_BRESP;
wire axi_interconnect_0_to_s01_couplers_BVALID;
wire axi_interconnect_0_to_s01_couplers_RDATA;
wire axi_interconnect_0_to_s01_couplers_RID;
wire axi_interconnect_0_to_s01_couplers_RLAST;
wire axi_interconnect_0_to_s01_couplers_RREADY;
wire axi_interconnect_0_to_s01_couplers_RRESP;
wire axi_interconnect_0_to_s01_couplers_RVALID;
wire axi_interconnect_0_to_s01_couplers_WDATA;
wire axi_interconnect_0_to_s01_couplers_WLAST;
wire axi_interconnect_0_to_s01_couplers_WREADY;
wire axi_interconnect_0_to_s01_couplers_WSTRB;
wire axi_interconnect_0_to_s01_couplers_WVALID;
wire m00_couplers_to_axi_interconnect_0_ARADDR;
wire m00_couplers_to_axi_interconnect_0_ARBURST;
wire m00_couplers_to_axi_interconnect_0_ARCACHE;
wire m00_couplers_to_axi_interconnect_0_ARLEN;
wire m00_couplers_to_axi_interconnect_0_ARLOCK;
wire m00_couplers_to_axi_interconnect_0_ARPROT;
wire m00_couplers_to_axi_interconnect_0_ARQOS;
wire m00_couplers_to_axi_interconnect_0_ARREADY;
wire m00_couplers_to_axi_interconnect_0_ARREGION;
wire m00_couplers_to_axi_interconnect_0_ARSIZE;
wire m00_couplers_to_axi_interconnect_0_ARVALID;
wire m00_couplers_to_axi_interconnect_0_AWADDR;
wire m00_couplers_to_axi_interconnect_0_AWBURST;
wire m00_couplers_to_axi_interconnect_0_AWCACHE;
wire m00_couplers_to_axi_interconnect_0_AWLEN;
wire m00_couplers_to_axi_interconnect_0_AWLOCK;
wire m00_couplers_to_axi_interconnect_0_AWPROT;
wire m00_couplers_to_axi_interconnect_0_AWQOS;
wire m00_couplers_to_axi_interconnect_0_AWREADY;
wire m00_couplers_to_axi_interconnect_0_AWREGION;
wire m00_couplers_to_axi_interconnect_0_AWSIZE;
wire m00_couplers_to_axi_interconnect_0_AWVALID;
wire m00_couplers_to_axi_interconnect_0_BREADY;
wire m00_couplers_to_axi_interconnect_0_BRESP;
wire m00_couplers_to_axi_interconnect_0_BVALID;
wire m00_couplers_to_axi_interconnect_0_RDATA;
wire m00_couplers_to_axi_interconnect_0_RLAST;
wire m00_couplers_to_axi_interconnect_0_RREADY;
wire m00_couplers_to_axi_interconnect_0_RRESP;
wire m00_couplers_to_axi_interconnect_0_RVALID;
wire m00_couplers_to_axi_interconnect_0_WDATA;
wire m00_couplers_to_axi_interconnect_0_WLAST;
wire m00_couplers_to_axi_interconnect_0_WREADY;
wire m00_couplers_to_axi_interconnect_0_WSTRB;
wire m00_couplers_to_axi_interconnect_0_WVALID;
wire [31:0]m01_couplers_to_axi_interconnect_0_ARADDR;
wire [2:0]m01_couplers_to_axi_interconnect_0_ARPROT;
wire m01_couplers_to_axi_interconnect_0_ARREADY;
wire m01_couplers_to_axi_interconnect_0_ARVALID;
wire [31:0]m01_couplers_to_axi_interconnect_0_AWADDR;
wire [2:0]m01_couplers_to_axi_interconnect_0_AWPROT;
wire m01_couplers_to_axi_interconnect_0_AWREADY;
wire m01_couplers_to_axi_interconnect_0_AWVALID;
wire m01_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]m01_couplers_to_axi_interconnect_0_BRESP;
wire m01_couplers_to_axi_interconnect_0_BVALID;
wire [31:0]m01_couplers_to_axi_interconnect_0_RDATA;
wire m01_couplers_to_axi_interconnect_0_RREADY;
wire [1:0]m01_couplers_to_axi_interconnect_0_RRESP;
wire m01_couplers_to_axi_interconnect_0_RVALID;
wire [31:0]m01_couplers_to_axi_interconnect_0_WDATA;
wire m01_couplers_to_axi_interconnect_0_WREADY;
wire [3:0]m01_couplers_to_axi_interconnect_0_WSTRB;
wire m01_couplers_to_axi_interconnect_0_WVALID;
wire [31:0]m02_couplers_to_axi_interconnect_0_ARADDR;
wire [2:0]m02_couplers_to_axi_interconnect_0_ARPROT;
wire m02_couplers_to_axi_interconnect_0_ARREADY;
wire m02_couplers_to_axi_interconnect_0_ARVALID;
wire [31:0]m02_couplers_to_axi_interconnect_0_AWADDR;
wire [2:0]m02_couplers_to_axi_interconnect_0_AWPROT;
wire m02_couplers_to_axi_interconnect_0_AWREADY;
wire m02_couplers_to_axi_interconnect_0_AWVALID;
wire m02_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]m02_couplers_to_axi_interconnect_0_BRESP;
wire m02_couplers_to_axi_interconnect_0_BVALID;
wire [31:0]m02_couplers_to_axi_interconnect_0_RDATA;
wire m02_couplers_to_axi_interconnect_0_RREADY;
wire [1:0]m02_couplers_to_axi_interconnect_0_RRESP;
wire m02_couplers_to_axi_interconnect_0_RVALID;
wire [31:0]m02_couplers_to_axi_interconnect_0_WDATA;
wire m02_couplers_to_axi_interconnect_0_WREADY;
wire [3:0]m02_couplers_to_axi_interconnect_0_WSTRB;
wire m02_couplers_to_axi_interconnect_0_WVALID;
wire [31:0]m03_couplers_to_axi_interconnect_0_ARADDR;
wire [2:0]m03_couplers_to_axi_interconnect_0_ARPROT;
wire m03_couplers_to_axi_interconnect_0_ARREADY;
wire m03_couplers_to_axi_interconnect_0_ARVALID;
wire [31:0]m03_couplers_to_axi_interconnect_0_AWADDR;
wire [2:0]m03_couplers_to_axi_interconnect_0_AWPROT;
wire m03_couplers_to_axi_interconnect_0_AWREADY;
wire m03_couplers_to_axi_interconnect_0_AWVALID;
wire m03_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]m03_couplers_to_axi_interconnect_0_BRESP;
wire m03_couplers_to_axi_interconnect_0_BVALID;
wire [31:0]m03_couplers_to_axi_interconnect_0_RDATA;
wire m03_couplers_to_axi_interconnect_0_RREADY;
wire [1:0]m03_couplers_to_axi_interconnect_0_RRESP;
wire m03_couplers_to_axi_interconnect_0_RVALID;
wire [31:0]m03_couplers_to_axi_interconnect_0_WDATA;
wire m03_couplers_to_axi_interconnect_0_WREADY;
wire [3:0]m03_couplers_to_axi_interconnect_0_WSTRB;
wire m03_couplers_to_axi_interconnect_0_WVALID;
wire [31:0]m04_couplers_to_axi_interconnect_0_ARADDR;
wire [1:0]m04_couplers_to_axi_interconnect_0_ARBURST;
wire [3:0]m04_couplers_to_axi_interconnect_0_ARCACHE;
wire [3:0]m04_couplers_to_axi_interconnect_0_ARLEN;
wire [1:0]m04_couplers_to_axi_interconnect_0_ARLOCK;
wire [2:0]m04_couplers_to_axi_interconnect_0_ARPROT;
wire [3:0]m04_couplers_to_axi_interconnect_0_ARQOS;
wire m04_couplers_to_axi_interconnect_0_ARREADY;
wire [2:0]m04_couplers_to_axi_interconnect_0_ARSIZE;
wire m04_couplers_to_axi_interconnect_0_ARVALID;
wire [31:0]m04_couplers_to_axi_interconnect_0_AWADDR;
wire [1:0]m04_couplers_to_axi_interconnect_0_AWBURST;
wire [3:0]m04_couplers_to_axi_interconnect_0_AWCACHE;
wire [3:0]m04_couplers_to_axi_interconnect_0_AWLEN;
wire [1:0]m04_couplers_to_axi_interconnect_0_AWLOCK;
wire [2:0]m04_couplers_to_axi_interconnect_0_AWPROT;
wire [3:0]m04_couplers_to_axi_interconnect_0_AWQOS;
wire m04_couplers_to_axi_interconnect_0_AWREADY;
wire [2:0]m04_couplers_to_axi_interconnect_0_AWSIZE;
wire m04_couplers_to_axi_interconnect_0_AWVALID;
wire m04_couplers_to_axi_interconnect_0_BREADY;
wire [1:0]m04_couplers_to_axi_interconnect_0_BRESP;
wire m04_couplers_to_axi_interconnect_0_BVALID;
wire [31:0]m04_couplers_to_axi_interconnect_0_RDATA;
wire m04_couplers_to_axi_interconnect_0_RLAST;
wire m04_couplers_to_axi_interconnect_0_RREADY;
wire [1:0]m04_couplers_to_axi_interconnect_0_RRESP;
wire m04_couplers_to_axi_interconnect_0_RVALID;
wire [31:0]m04_couplers_to_axi_interconnect_0_WDATA;
wire m04_couplers_to_axi_interconnect_0_WLAST;
wire m04_couplers_to_axi_interconnect_0_WREADY;
wire [3:0]m04_couplers_to_axi_interconnect_0_WSTRB;
wire m04_couplers_to_axi_interconnect_0_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [1:0]s00_couplers_to_xbar_ARBURST;
wire [3:0]s00_couplers_to_xbar_ARCACHE;
wire [11:0]s00_couplers_to_xbar_ARID;
wire [7:0]s00_couplers_to_xbar_ARLEN;
wire [0:0]s00_couplers_to_xbar_ARLOCK;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [3:0]s00_couplers_to_xbar_ARQOS;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire [2:0]s00_couplers_to_xbar_ARSIZE;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [1:0]s00_couplers_to_xbar_AWBURST;
wire [3:0]s00_couplers_to_xbar_AWCACHE;
wire [11:0]s00_couplers_to_xbar_AWID;
wire [7:0]s00_couplers_to_xbar_AWLEN;
wire [0:0]s00_couplers_to_xbar_AWLOCK;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [3:0]s00_couplers_to_xbar_AWQOS;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire [2:0]s00_couplers_to_xbar_AWSIZE;
wire s00_couplers_to_xbar_AWVALID;
wire [12:0]s00_couplers_to_xbar_BID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [31:0]s00_couplers_to_xbar_RDATA;
wire [12:0]s00_couplers_to_xbar_RID;
wire [0:0]s00_couplers_to_xbar_RLAST;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s00_couplers_to_xbar_WDATA;
wire s00_couplers_to_xbar_WLAST;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [3:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire s01_couplers_to_xbar_ARADDR;
wire s01_couplers_to_xbar_ARBURST;
wire s01_couplers_to_xbar_ARCACHE;
wire s01_couplers_to_xbar_ARID;
wire s01_couplers_to_xbar_ARLEN;
wire s01_couplers_to_xbar_ARLOCK;
wire s01_couplers_to_xbar_ARPROT;
wire s01_couplers_to_xbar_ARQOS;
wire [1:1]s01_couplers_to_xbar_ARREADY;
wire s01_couplers_to_xbar_ARSIZE;
wire s01_couplers_to_xbar_ARVALID;
wire s01_couplers_to_xbar_AWADDR;
wire s01_couplers_to_xbar_AWBURST;
wire s01_couplers_to_xbar_AWCACHE;
wire s01_couplers_to_xbar_AWID;
wire s01_couplers_to_xbar_AWLEN;
wire s01_couplers_to_xbar_AWLOCK;
wire s01_couplers_to_xbar_AWPROT;
wire s01_couplers_to_xbar_AWQOS;
wire [1:1]s01_couplers_to_xbar_AWREADY;
wire s01_couplers_to_xbar_AWSIZE;
wire s01_couplers_to_xbar_AWVALID;
wire [25:13]s01_couplers_to_xbar_BID;
wire s01_couplers_to_xbar_BREADY;
wire [3:2]s01_couplers_to_xbar_BRESP;
wire [1:1]s01_couplers_to_xbar_BVALID;
wire [63:32]s01_couplers_to_xbar_RDATA;
wire [25:13]s01_couplers_to_xbar_RID;
wire [1:1]s01_couplers_to_xbar_RLAST;
wire s01_couplers_to_xbar_RREADY;
wire [3:2]s01_couplers_to_xbar_RRESP;
wire [1:1]s01_couplers_to_xbar_RVALID;
wire s01_couplers_to_xbar_WDATA;
wire s01_couplers_to_xbar_WLAST;
wire [1:1]s01_couplers_to_xbar_WREADY;
wire s01_couplers_to_xbar_WSTRB;
wire s01_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [1:0]xbar_to_m00_couplers_ARBURST;
wire [3:0]xbar_to_m00_couplers_ARCACHE;
wire [7:0]xbar_to_m00_couplers_ARLEN;
wire [0:0]xbar_to_m00_couplers_ARLOCK;
wire [2:0]xbar_to_m00_couplers_ARPROT;
wire [3:0]xbar_to_m00_couplers_ARQOS;
wire xbar_to_m00_couplers_ARREADY;
wire [3:0]xbar_to_m00_couplers_ARREGION;
wire [2:0]xbar_to_m00_couplers_ARSIZE;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [1:0]xbar_to_m00_couplers_AWBURST;
wire [3:0]xbar_to_m00_couplers_AWCACHE;
wire [7:0]xbar_to_m00_couplers_AWLEN;
wire [0:0]xbar_to_m00_couplers_AWLOCK;
wire [2:0]xbar_to_m00_couplers_AWPROT;
wire [3:0]xbar_to_m00_couplers_AWQOS;
wire xbar_to_m00_couplers_AWREADY;
wire [3:0]xbar_to_m00_couplers_AWREGION;
wire [2:0]xbar_to_m00_couplers_AWSIZE;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire xbar_to_m00_couplers_BRESP;
wire xbar_to_m00_couplers_BVALID;
wire xbar_to_m00_couplers_RDATA;
wire xbar_to_m00_couplers_RLAST;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire xbar_to_m00_couplers_RRESP;
wire xbar_to_m00_couplers_RVALID;
wire [31:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WLAST;
wire xbar_to_m00_couplers_WREADY;
wire [3:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire [3:2]xbar_to_m01_couplers_ARBURST;
wire [7:4]xbar_to_m01_couplers_ARCACHE;
wire [15:8]xbar_to_m01_couplers_ARLEN;
wire [1:1]xbar_to_m01_couplers_ARLOCK;
wire [5:3]xbar_to_m01_couplers_ARPROT;
wire [7:4]xbar_to_m01_couplers_ARQOS;
wire xbar_to_m01_couplers_ARREADY;
wire [7:4]xbar_to_m01_couplers_ARREGION;
wire [5:3]xbar_to_m01_couplers_ARSIZE;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire [3:2]xbar_to_m01_couplers_AWBURST;
wire [7:4]xbar_to_m01_couplers_AWCACHE;
wire [15:8]xbar_to_m01_couplers_AWLEN;
wire [1:1]xbar_to_m01_couplers_AWLOCK;
wire [5:3]xbar_to_m01_couplers_AWPROT;
wire [7:4]xbar_to_m01_couplers_AWQOS;
wire xbar_to_m01_couplers_AWREADY;
wire [7:4]xbar_to_m01_couplers_AWREGION;
wire [5:3]xbar_to_m01_couplers_AWSIZE;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire xbar_to_m01_couplers_BVALID;
wire [31:0]xbar_to_m01_couplers_RDATA;
wire xbar_to_m01_couplers_RLAST;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire xbar_to_m01_couplers_RVALID;
wire [63:32]xbar_to_m01_couplers_WDATA;
wire [1:1]xbar_to_m01_couplers_WLAST;
wire xbar_to_m01_couplers_WREADY;
wire [7:4]xbar_to_m01_couplers_WSTRB;
wire [1:1]xbar_to_m01_couplers_WVALID;
wire [95:64]xbar_to_m02_couplers_ARADDR;
wire [5:4]xbar_to_m02_couplers_ARBURST;
wire [11:8]xbar_to_m02_couplers_ARCACHE;
wire [23:16]xbar_to_m02_couplers_ARLEN;
wire [2:2]xbar_to_m02_couplers_ARLOCK;
wire [8:6]xbar_to_m02_couplers_ARPROT;
wire [11:8]xbar_to_m02_couplers_ARQOS;
wire xbar_to_m02_couplers_ARREADY;
wire [11:8]xbar_to_m02_couplers_ARREGION;
wire [8:6]xbar_to_m02_couplers_ARSIZE;
wire [2:2]xbar_to_m02_couplers_ARVALID;
wire [95:64]xbar_to_m02_couplers_AWADDR;
wire [5:4]xbar_to_m02_couplers_AWBURST;
wire [11:8]xbar_to_m02_couplers_AWCACHE;
wire [23:16]xbar_to_m02_couplers_AWLEN;
wire [2:2]xbar_to_m02_couplers_AWLOCK;
wire [8:6]xbar_to_m02_couplers_AWPROT;
wire [11:8]xbar_to_m02_couplers_AWQOS;
wire xbar_to_m02_couplers_AWREADY;
wire [11:8]xbar_to_m02_couplers_AWREGION;
wire [8:6]xbar_to_m02_couplers_AWSIZE;
wire [2:2]xbar_to_m02_couplers_AWVALID;
wire [2:2]xbar_to_m02_couplers_BREADY;
wire [1:0]xbar_to_m02_couplers_BRESP;
wire xbar_to_m02_couplers_BVALID;
wire [31:0]xbar_to_m02_couplers_RDATA;
wire xbar_to_m02_couplers_RLAST;
wire [2:2]xbar_to_m02_couplers_RREADY;
wire [1:0]xbar_to_m02_couplers_RRESP;
wire xbar_to_m02_couplers_RVALID;
wire [95:64]xbar_to_m02_couplers_WDATA;
wire [2:2]xbar_to_m02_couplers_WLAST;
wire xbar_to_m02_couplers_WREADY;
wire [11:8]xbar_to_m02_couplers_WSTRB;
wire [2:2]xbar_to_m02_couplers_WVALID;
wire [127:96]xbar_to_m03_couplers_ARADDR;
wire [7:6]xbar_to_m03_couplers_ARBURST;
wire [15:12]xbar_to_m03_couplers_ARCACHE;
wire [31:24]xbar_to_m03_couplers_ARLEN;
wire [3:3]xbar_to_m03_couplers_ARLOCK;
wire [11:9]xbar_to_m03_couplers_ARPROT;
wire [15:12]xbar_to_m03_couplers_ARQOS;
wire xbar_to_m03_couplers_ARREADY;
wire [15:12]xbar_to_m03_couplers_ARREGION;
wire [11:9]xbar_to_m03_couplers_ARSIZE;
wire [3:3]xbar_to_m03_couplers_ARVALID;
wire [127:96]xbar_to_m03_couplers_AWADDR;
wire [7:6]xbar_to_m03_couplers_AWBURST;
wire [15:12]xbar_to_m03_couplers_AWCACHE;
wire [31:24]xbar_to_m03_couplers_AWLEN;
wire [3:3]xbar_to_m03_couplers_AWLOCK;
wire [11:9]xbar_to_m03_couplers_AWPROT;
wire [15:12]xbar_to_m03_couplers_AWQOS;
wire xbar_to_m03_couplers_AWREADY;
wire [15:12]xbar_to_m03_couplers_AWREGION;
wire [11:9]xbar_to_m03_couplers_AWSIZE;
wire [3:3]xbar_to_m03_couplers_AWVALID;
wire [3:3]xbar_to_m03_couplers_BREADY;
wire [1:0]xbar_to_m03_couplers_BRESP;
wire xbar_to_m03_couplers_BVALID;
wire [31:0]xbar_to_m03_couplers_RDATA;
wire xbar_to_m03_couplers_RLAST;
wire [3:3]xbar_to_m03_couplers_RREADY;
wire [1:0]xbar_to_m03_couplers_RRESP;
wire xbar_to_m03_couplers_RVALID;
wire [127:96]xbar_to_m03_couplers_WDATA;
wire [3:3]xbar_to_m03_couplers_WLAST;
wire xbar_to_m03_couplers_WREADY;
wire [15:12]xbar_to_m03_couplers_WSTRB;
wire [3:3]xbar_to_m03_couplers_WVALID;
wire [159:128]xbar_to_m04_couplers_ARADDR;
wire [9:8]xbar_to_m04_couplers_ARBURST;
wire [19:16]xbar_to_m04_couplers_ARCACHE;
wire [39:32]xbar_to_m04_couplers_ARLEN;
wire [4:4]xbar_to_m04_couplers_ARLOCK;
wire [14:12]xbar_to_m04_couplers_ARPROT;
wire [19:16]xbar_to_m04_couplers_ARQOS;
wire xbar_to_m04_couplers_ARREADY;
wire [19:16]xbar_to_m04_couplers_ARREGION;
wire [14:12]xbar_to_m04_couplers_ARSIZE;
wire [4:4]xbar_to_m04_couplers_ARVALID;
wire [159:128]xbar_to_m04_couplers_AWADDR;
wire [9:8]xbar_to_m04_couplers_AWBURST;
wire [19:16]xbar_to_m04_couplers_AWCACHE;
wire [39:32]xbar_to_m04_couplers_AWLEN;
wire [4:4]xbar_to_m04_couplers_AWLOCK;
wire [14:12]xbar_to_m04_couplers_AWPROT;
wire [19:16]xbar_to_m04_couplers_AWQOS;
wire xbar_to_m04_couplers_AWREADY;
wire [19:16]xbar_to_m04_couplers_AWREGION;
wire [14:12]xbar_to_m04_couplers_AWSIZE;
wire [4:4]xbar_to_m04_couplers_AWVALID;
wire [4:4]xbar_to_m04_couplers_BREADY;
wire [1:0]xbar_to_m04_couplers_BRESP;
wire xbar_to_m04_couplers_BVALID;
wire [31:0]xbar_to_m04_couplers_RDATA;
wire xbar_to_m04_couplers_RLAST;
wire [4:4]xbar_to_m04_couplers_RREADY;
wire [1:0]xbar_to_m04_couplers_RRESP;
wire xbar_to_m04_couplers_RVALID;
wire [159:128]xbar_to_m04_couplers_WDATA;
wire [4:4]xbar_to_m04_couplers_WLAST;
wire xbar_to_m04_couplers_WREADY;
wire [19:16]xbar_to_m04_couplers_WSTRB;
wire [4:4]xbar_to_m04_couplers_WVALID;
assign M00_AXI_araddr = m00_couplers_to_axi_interconnect_0_ARADDR;
assign M00_AXI_arburst = m00_couplers_to_axi_interconnect_0_ARBURST;
assign M00_AXI_arcache = m00_couplers_to_axi_interconnect_0_ARCACHE;
assign M00_AXI_arlen = m00_couplers_to_axi_interconnect_0_ARLEN;
assign M00_AXI_arlock = m00_couplers_to_axi_interconnect_0_ARLOCK;
assign M00_AXI_arprot = m00_couplers_to_axi_interconnect_0_ARPROT;
assign M00_AXI_arqos = m00_couplers_to_axi_interconnect_0_ARQOS;
assign M00_AXI_arregion = m00_couplers_to_axi_interconnect_0_ARREGION;
assign M00_AXI_arsize = m00_couplers_to_axi_interconnect_0_ARSIZE;
assign M00_AXI_arvalid = m00_couplers_to_axi_interconnect_0_ARVALID;
assign M00_AXI_awaddr = m00_couplers_to_axi_interconnect_0_AWADDR;
assign M00_AXI_awburst = m00_couplers_to_axi_interconnect_0_AWBURST;
assign M00_AXI_awcache = m00_couplers_to_axi_interconnect_0_AWCACHE;
assign M00_AXI_awlen = m00_couplers_to_axi_interconnect_0_AWLEN;
assign M00_AXI_awlock = m00_couplers_to_axi_interconnect_0_AWLOCK;
assign M00_AXI_awprot = m00_couplers_to_axi_interconnect_0_AWPROT;
assign M00_AXI_awqos = m00_couplers_to_axi_interconnect_0_AWQOS;
assign M00_AXI_awregion = m00_couplers_to_axi_interconnect_0_AWREGION;
assign M00_AXI_awsize = m00_couplers_to_axi_interconnect_0_AWSIZE;
assign M00_AXI_awvalid = m00_couplers_to_axi_interconnect_0_AWVALID;
assign M00_AXI_bready = m00_couplers_to_axi_interconnect_0_BREADY;
assign M00_AXI_rready = m00_couplers_to_axi_interconnect_0_RREADY;
assign M00_AXI_wdata = m00_couplers_to_axi_interconnect_0_WDATA;
assign M00_AXI_wlast = m00_couplers_to_axi_interconnect_0_WLAST;
assign M00_AXI_wstrb = m00_couplers_to_axi_interconnect_0_WSTRB;
assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_0_WVALID;
assign M01_AXI_araddr[31:0] = m01_couplers_to_axi_interconnect_0_ARADDR;
assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_interconnect_0_ARPROT;
assign M01_AXI_arvalid = m01_couplers_to_axi_interconnect_0_ARVALID;
assign M01_AXI_awaddr[31:0] = m01_couplers_to_axi_interconnect_0_AWADDR;
assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_interconnect_0_AWPROT;
assign M01_AXI_awvalid = m01_couplers_to_axi_interconnect_0_AWVALID;
assign M01_AXI_bready = m01_couplers_to_axi_interconnect_0_BREADY;
assign M01_AXI_rready = m01_couplers_to_axi_interconnect_0_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_axi_interconnect_0_WDATA;
assign M01_AXI_wstrb[3:0] = m01_couplers_to_axi_interconnect_0_WSTRB;
assign M01_AXI_wvalid = m01_couplers_to_axi_interconnect_0_WVALID;
assign M02_AXI_araddr[31:0] = m02_couplers_to_axi_interconnect_0_ARADDR;
assign M02_AXI_arprot[2:0] = m02_couplers_to_axi_interconnect_0_ARPROT;
assign M02_AXI_arvalid = m02_couplers_to_axi_interconnect_0_ARVALID;
assign M02_AXI_awaddr[31:0] = m02_couplers_to_axi_interconnect_0_AWADDR;
assign M02_AXI_awprot[2:0] = m02_couplers_to_axi_interconnect_0_AWPROT;
assign M02_AXI_awvalid = m02_couplers_to_axi_interconnect_0_AWVALID;
assign M02_AXI_bready = m02_couplers_to_axi_interconnect_0_BREADY;
assign M02_AXI_rready = m02_couplers_to_axi_interconnect_0_RREADY;
assign M02_AXI_wdata[31:0] = m02_couplers_to_axi_interconnect_0_WDATA;
assign M02_AXI_wstrb[3:0] = m02_couplers_to_axi_interconnect_0_WSTRB;
assign M02_AXI_wvalid = m02_couplers_to_axi_interconnect_0_WVALID;
assign M03_AXI_araddr[31:0] = m03_couplers_to_axi_interconnect_0_ARADDR;
assign M03_AXI_arprot[2:0] = m03_couplers_to_axi_interconnect_0_ARPROT;
assign M03_AXI_arvalid = m03_couplers_to_axi_interconnect_0_ARVALID;
assign M03_AXI_awaddr[31:0] = m03_couplers_to_axi_interconnect_0_AWADDR;
assign M03_AXI_awprot[2:0] = m03_couplers_to_axi_interconnect_0_AWPROT;
assign M03_AXI_awvalid = m03_couplers_to_axi_interconnect_0_AWVALID;
assign M03_AXI_bready = m03_couplers_to_axi_interconnect_0_BREADY;
assign M03_AXI_rready = m03_couplers_to_axi_interconnect_0_RREADY;
assign M03_AXI_wdata[31:0] = m03_couplers_to_axi_interconnect_0_WDATA;
assign M03_AXI_wstrb[3:0] = m03_couplers_to_axi_interconnect_0_WSTRB;
assign M03_AXI_wvalid = m03_couplers_to_axi_interconnect_0_WVALID;
assign M04_AXI_araddr[31:0] = m04_couplers_to_axi_interconnect_0_ARADDR;
assign M04_AXI_arburst[1:0] = m04_couplers_to_axi_interconnect_0_ARBURST;
assign M04_AXI_arcache[3:0] = m04_couplers_to_axi_interconnect_0_ARCACHE;
assign M04_AXI_arlen[3:0] = m04_couplers_to_axi_interconnect_0_ARLEN;
assign M04_AXI_arlock[1:0] = m04_couplers_to_axi_interconnect_0_ARLOCK;
assign M04_AXI_arprot[2:0] = m04_couplers_to_axi_interconnect_0_ARPROT;
assign M04_AXI_arqos[3:0] = m04_couplers_to_axi_interconnect_0_ARQOS;
assign M04_AXI_arsize[2:0] = m04_couplers_to_axi_interconnect_0_ARSIZE;
assign M04_AXI_arvalid = m04_couplers_to_axi_interconnect_0_ARVALID;
assign M04_AXI_awaddr[31:0] = m04_couplers_to_axi_interconnect_0_AWADDR;
assign M04_AXI_awburst[1:0] = m04_couplers_to_axi_interconnect_0_AWBURST;
assign M04_AXI_awcache[3:0] = m04_couplers_to_axi_interconnect_0_AWCACHE;
assign M04_AXI_awlen[3:0] = m04_couplers_to_axi_interconnect_0_AWLEN;
assign M04_AXI_awlock[1:0] = m04_couplers_to_axi_interconnect_0_AWLOCK;
assign M04_AXI_awprot[2:0] = m04_couplers_to_axi_interconnect_0_AWPROT;
assign M04_AXI_awqos[3:0] = m04_couplers_to_axi_interconnect_0_AWQOS;
assign M04_AXI_awsize[2:0] = m04_couplers_to_axi_interconnect_0_AWSIZE;
assign M04_AXI_awvalid = m04_couplers_to_axi_interconnect_0_AWVALID;
assign M04_AXI_bready = m04_couplers_to_axi_interconnect_0_BREADY;
assign M04_AXI_rready = m04_couplers_to_axi_interconnect_0_RREADY;
assign M04_AXI_wdata[31:0] = m04_couplers_to_axi_interconnect_0_WDATA;
assign M04_AXI_wlast = m04_couplers_to_axi_interconnect_0_WLAST;
assign M04_AXI_wstrb[3:0] = m04_couplers_to_axi_interconnect_0_WSTRB;
assign M04_AXI_wvalid = m04_couplers_to_axi_interconnect_0_WVALID;
assign S00_AXI_arready = axi_interconnect_0_to_s00_couplers_ARREADY;
assign S00_AXI_awready = axi_interconnect_0_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = axi_interconnect_0_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_interconnect_0_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = axi_interconnect_0_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = axi_interconnect_0_to_s00_couplers_RID;
assign S00_AXI_rlast = axi_interconnect_0_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_interconnect_0_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_interconnect_0_to_s00_couplers_RVALID;
assign S00_AXI_wready = axi_interconnect_0_to_s00_couplers_WREADY;
assign S01_AXI_arready = axi_interconnect_0_to_s01_couplers_ARREADY;
assign S01_AXI_awready = axi_interconnect_0_to_s01_couplers_AWREADY;
assign S01_AXI_bid = axi_interconnect_0_to_s01_couplers_BID;
assign S01_AXI_bresp = axi_interconnect_0_to_s01_couplers_BRESP;
assign S01_AXI_bvalid = axi_interconnect_0_to_s01_couplers_BVALID;
assign S01_AXI_rdata = axi_interconnect_0_to_s01_couplers_RDATA;
assign S01_AXI_rid = axi_interconnect_0_to_s01_couplers_RID;
assign S01_AXI_rlast = axi_interconnect_0_to_s01_couplers_RLAST;
assign S01_AXI_rresp = axi_interconnect_0_to_s01_couplers_RRESP;
assign S01_AXI_rvalid = axi_interconnect_0_to_s01_couplers_RVALID;
assign S01_AXI_wready = axi_interconnect_0_to_s01_couplers_WREADY;
assign axi_interconnect_0_ACLK_net = ACLK;
assign axi_interconnect_0_ARESETN_net = ARESETN[0];
assign axi_interconnect_0_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_interconnect_0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_interconnect_0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_interconnect_0_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign axi_interconnect_0_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign axi_interconnect_0_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign axi_interconnect_0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_interconnect_0_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign axi_interconnect_0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_interconnect_0_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_interconnect_0_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign axi_interconnect_0_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_interconnect_0_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_interconnect_0_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_interconnect_0_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign axi_interconnect_0_to_s01_couplers_ARADDR = S01_AXI_araddr;
assign axi_interconnect_0_to_s01_couplers_ARBURST = S01_AXI_arburst;
assign axi_interconnect_0_to_s01_couplers_ARCACHE = S01_AXI_arcache;
assign axi_interconnect_0_to_s01_couplers_ARID = S01_AXI_arid;
assign axi_interconnect_0_to_s01_couplers_ARLEN = S01_AXI_arlen;
assign axi_interconnect_0_to_s01_couplers_ARLOCK = S01_AXI_arlock;
assign axi_interconnect_0_to_s01_couplers_ARPROT = S01_AXI_arprot;
assign axi_interconnect_0_to_s01_couplers_ARQOS = S01_AXI_arqos;
assign axi_interconnect_0_to_s01_couplers_ARSIZE = S01_AXI_arsize;
assign axi_interconnect_0_to_s01_couplers_ARVALID = S01_AXI_arvalid;
assign axi_interconnect_0_to_s01_couplers_AWADDR = S01_AXI_awaddr;
assign axi_interconnect_0_to_s01_couplers_AWBURST = S01_AXI_awburst;
assign axi_interconnect_0_to_s01_couplers_AWCACHE = S01_AXI_awcache;
assign axi_interconnect_0_to_s01_couplers_AWID = S01_AXI_awid;
assign axi_interconnect_0_to_s01_couplers_AWLEN = S01_AXI_awlen;
assign axi_interconnect_0_to_s01_couplers_AWLOCK = S01_AXI_awlock;
assign axi_interconnect_0_to_s01_couplers_AWPROT = S01_AXI_awprot;
assign axi_interconnect_0_to_s01_couplers_AWQOS = S01_AXI_awqos;
assign axi_interconnect_0_to_s01_couplers_AWSIZE = S01_AXI_awsize;
assign axi_interconnect_0_to_s01_couplers_AWVALID = S01_AXI_awvalid;
assign axi_interconnect_0_to_s01_couplers_BREADY = S01_AXI_bready;
assign axi_interconnect_0_to_s01_couplers_RREADY = S01_AXI_rready;
assign axi_interconnect_0_to_s01_couplers_WDATA = S01_AXI_wdata;
assign axi_interconnect_0_to_s01_couplers_WLAST = S01_AXI_wlast;
assign axi_interconnect_0_to_s01_couplers_WSTRB = S01_AXI_wstrb;
assign axi_interconnect_0_to_s01_couplers_WVALID = S01_AXI_wvalid;
assign m00_couplers_to_axi_interconnect_0_ARREADY = M00_AXI_arready;
assign m00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready;
assign m00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp;
assign m00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid;
assign m00_couplers_to_axi_interconnect_0_RDATA = M00_AXI_rdata;
assign m00_couplers_to_axi_interconnect_0_RLAST = M00_AXI_rlast;
assign m00_couplers_to_axi_interconnect_0_RRESP = M00_AXI_rresp;
assign m00_couplers_to_axi_interconnect_0_RVALID = M00_AXI_rvalid;
assign m00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready;
assign m01_couplers_to_axi_interconnect_0_ARREADY = M01_AXI_arready;
assign m01_couplers_to_axi_interconnect_0_AWREADY = M01_AXI_awready;
assign m01_couplers_to_axi_interconnect_0_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_axi_interconnect_0_BVALID = M01_AXI_bvalid;
assign m01_couplers_to_axi_interconnect_0_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_axi_interconnect_0_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_axi_interconnect_0_RVALID = M01_AXI_rvalid;
assign m01_couplers_to_axi_interconnect_0_WREADY = M01_AXI_wready;
assign m02_couplers_to_axi_interconnect_0_ARREADY = M02_AXI_arready;
assign m02_couplers_to_axi_interconnect_0_AWREADY = M02_AXI_awready;
assign m02_couplers_to_axi_interconnect_0_BRESP = M02_AXI_bresp[1:0];
assign m02_couplers_to_axi_interconnect_0_BVALID = M02_AXI_bvalid;
assign m02_couplers_to_axi_interconnect_0_RDATA = M02_AXI_rdata[31:0];
assign m02_couplers_to_axi_interconnect_0_RRESP = M02_AXI_rresp[1:0];
assign m02_couplers_to_axi_interconnect_0_RVALID = M02_AXI_rvalid;
assign m02_couplers_to_axi_interconnect_0_WREADY = M02_AXI_wready;
assign m03_couplers_to_axi_interconnect_0_ARREADY = M03_AXI_arready;
assign m03_couplers_to_axi_interconnect_0_AWREADY = M03_AXI_awready;
assign m03_couplers_to_axi_interconnect_0_BRESP = M03_AXI_bresp[1:0];
assign m03_couplers_to_axi_interconnect_0_BVALID = M03_AXI_bvalid;
assign m03_couplers_to_axi_interconnect_0_RDATA = M03_AXI_rdata[31:0];
assign m03_couplers_to_axi_interconnect_0_RRESP = M03_AXI_rresp[1:0];
assign m03_couplers_to_axi_interconnect_0_RVALID = M03_AXI_rvalid;
assign m03_couplers_to_axi_interconnect_0_WREADY = M03_AXI_wready;
assign m04_couplers_to_axi_interconnect_0_ARREADY = M04_AXI_arready;
assign m04_couplers_to_axi_interconnect_0_AWREADY = M04_AXI_awready;
assign m04_couplers_to_axi_interconnect_0_BRESP = M04_AXI_bresp[1:0];
assign m04_couplers_to_axi_interconnect_0_BVALID = M04_AXI_bvalid;
assign m04_couplers_to_axi_interconnect_0_RDATA = M04_AXI_rdata[31:0];
assign m04_couplers_to_axi_interconnect_0_RLAST = M04_AXI_rlast;
assign m04_couplers_to_axi_interconnect_0_RRESP = M04_AXI_rresp[1:0];
assign m04_couplers_to_axi_interconnect_0_RVALID = M04_AXI_rvalid;
assign m04_couplers_to_axi_interconnect_0_WREADY = M04_AXI_wready;
m00_couplers_imp_J0QEI9 m00_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(m00_couplers_to_axi_interconnect_0_ARADDR),
.M_AXI_arburst(m00_couplers_to_axi_interconnect_0_ARBURST),
.M_AXI_arcache(m00_couplers_to_axi_interconnect_0_ARCACHE),
.M_AXI_arlen(m00_couplers_to_axi_interconnect_0_ARLEN),
.M_AXI_arlock(m00_couplers_to_axi_interconnect_0_ARLOCK),
.M_AXI_arprot(m00_couplers_to_axi_interconnect_0_ARPROT),
.M_AXI_arqos(m00_couplers_to_axi_interconnect_0_ARQOS),
.M_AXI_arready(m00_couplers_to_axi_interconnect_0_ARREADY),
.M_AXI_arregion(m00_couplers_to_axi_interconnect_0_ARREGION),
.M_AXI_arsize(m00_couplers_to_axi_interconnect_0_ARSIZE),
.M_AXI_arvalid(m00_couplers_to_axi_interconnect_0_ARVALID),
.M_AXI_awaddr(m00_couplers_to_axi_interconnect_0_AWADDR),
.M_AXI_awburst(m00_couplers_to_axi_interconnect_0_AWBURST),
.M_AXI_awcache(m00_couplers_to_axi_interconnect_0_AWCACHE),
.M_AXI_awlen(m00_couplers_to_axi_interconnect_0_AWLEN),
.M_AXI_awlock(m00_couplers_to_axi_interconnect_0_AWLOCK),
.M_AXI_awprot(m00_couplers_to_axi_interconnect_0_AWPROT),
.M_AXI_awqos(m00_couplers_to_axi_interconnect_0_AWQOS),
.M_AXI_awready(m00_couplers_to_axi_interconnect_0_AWREADY),
.M_AXI_awregion(m00_couplers_to_axi_interconnect_0_AWREGION),
.M_AXI_awsize(m00_couplers_to_axi_interconnect_0_AWSIZE),
.M_AXI_awvalid(m00_couplers_to_axi_interconnect_0_AWVALID),
.M_AXI_bready(m00_couplers_to_axi_interconnect_0_BREADY),
.M_AXI_bresp(m00_couplers_to_axi_interconnect_0_BRESP),
.M_AXI_bvalid(m00_couplers_to_axi_interconnect_0_BVALID),
.M_AXI_rdata(m00_couplers_to_axi_interconnect_0_RDATA),
.M_AXI_rlast(m00_couplers_to_axi_interconnect_0_RLAST),
.M_AXI_rready(m00_couplers_to_axi_interconnect_0_RREADY),
.M_AXI_rresp(m00_couplers_to_axi_interconnect_0_RRESP),
.M_AXI_rvalid(m00_couplers_to_axi_interconnect_0_RVALID),
.M_AXI_wdata(m00_couplers_to_axi_interconnect_0_WDATA),
.M_AXI_wlast(m00_couplers_to_axi_interconnect_0_WLAST),
.M_AXI_wready(m00_couplers_to_axi_interconnect_0_WREADY),
.M_AXI_wstrb(m00_couplers_to_axi_interconnect_0_WSTRB),
.M_AXI_wvalid(m00_couplers_to_axi_interconnect_0_WVALID),
.S_ACLK(axi_interconnect_0_ACLK_net),
.S_ARESETN(axi_interconnect_0_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR[0]),
.S_AXI_arburst(xbar_to_m00_couplers_ARBURST[0]),
.S_AXI_arcache(xbar_to_m00_couplers_ARCACHE[0]),
.S_AXI_arlen(xbar_to_m00_couplers_ARLEN[0]),
.S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m00_couplers_ARPROT[0]),
.S_AXI_arqos(xbar_to_m00_couplers_ARQOS[0]),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m00_couplers_ARREGION[0]),
.S_AXI_arsize(xbar_to_m00_couplers_ARSIZE[0]),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR[0]),
.S_AXI_awburst(xbar_to_m00_couplers_AWBURST[0]),
.S_AXI_awcache(xbar_to_m00_couplers_AWCACHE[0]),
.S_AXI_awlen(xbar_to_m00_couplers_AWLEN[0]),
.S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m00_couplers_AWPROT[0]),
.S_AXI_awqos(xbar_to_m00_couplers_AWQOS[0]),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m00_couplers_AWREGION[0]),
.S_AXI_awsize(xbar_to_m00_couplers_AWSIZE[0]),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rlast(xbar_to_m00_couplers_RLAST),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA[0]),
.S_AXI_wlast(xbar_to_m00_couplers_WLAST),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB[0]),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_1M9HB38 m01_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(m01_couplers_to_axi_interconnect_0_ARADDR),
.M_AXI_arprot(m01_couplers_to_axi_interconnect_0_ARPROT),
.M_AXI_arready(m01_couplers_to_axi_interconnect_0_ARREADY),
.M_AXI_arvalid(m01_couplers_to_axi_interconnect_0_ARVALID),
.M_AXI_awaddr(m01_couplers_to_axi_interconnect_0_AWADDR),
.M_AXI_awprot(m01_couplers_to_axi_interconnect_0_AWPROT),
.M_AXI_awready(m01_couplers_to_axi_interconnect_0_AWREADY),
.M_AXI_awvalid(m01_couplers_to_axi_interconnect_0_AWVALID),
.M_AXI_bready(m01_couplers_to_axi_interconnect_0_BREADY),
.M_AXI_bresp(m01_couplers_to_axi_interconnect_0_BRESP),
.M_AXI_bvalid(m01_couplers_to_axi_interconnect_0_BVALID),
.M_AXI_rdata(m01_couplers_to_axi_interconnect_0_RDATA),
.M_AXI_rready(m01_couplers_to_axi_interconnect_0_RREADY),
.M_AXI_rresp(m01_couplers_to_axi_interconnect_0_RRESP),
.M_AXI_rvalid(m01_couplers_to_axi_interconnect_0_RVALID),
.M_AXI_wdata(m01_couplers_to_axi_interconnect_0_WDATA),
.M_AXI_wready(m01_couplers_to_axi_interconnect_0_WREADY),
.M_AXI_wstrb(m01_couplers_to_axi_interconnect_0_WSTRB),
.M_AXI_wvalid(m01_couplers_to_axi_interconnect_0_WVALID),
.S_ACLK(axi_interconnect_0_ACLK_net),
.S_ARESETN(axi_interconnect_0_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m01_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m01_couplers_ARCACHE),
.S_AXI_arlen(xbar_to_m01_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m01_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m01_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m01_couplers_ARQOS),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m01_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m01_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m01_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m01_couplers_AWCACHE),
.S_AXI_awlen(xbar_to_m01_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m01_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m01_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m01_couplers_AWQOS),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m01_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m01_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rlast(xbar_to_m01_couplers_RLAST),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wlast(xbar_to_m01_couplers_WLAST),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
m02_couplers_imp_1E92BOA m02_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(m02_couplers_to_axi_interconnect_0_ARADDR),
.M_AXI_arprot(m02_couplers_to_axi_interconnect_0_ARPROT),
.M_AXI_arready(m02_couplers_to_axi_interconnect_0_ARREADY),
.M_AXI_arvalid(m02_couplers_to_axi_interconnect_0_ARVALID),
.M_AXI_awaddr(m02_couplers_to_axi_interconnect_0_AWADDR),
.M_AXI_awprot(m02_couplers_to_axi_interconnect_0_AWPROT),
.M_AXI_awready(m02_couplers_to_axi_interconnect_0_AWREADY),
.M_AXI_awvalid(m02_couplers_to_axi_interconnect_0_AWVALID),
.M_AXI_bready(m02_couplers_to_axi_interconnect_0_BREADY),
.M_AXI_bresp(m02_couplers_to_axi_interconnect_0_BRESP),
.M_AXI_bvalid(m02_couplers_to_axi_interconnect_0_BVALID),
.M_AXI_rdata(m02_couplers_to_axi_interconnect_0_RDATA),
.M_AXI_rready(m02_couplers_to_axi_interconnect_0_RREADY),
.M_AXI_rresp(m02_couplers_to_axi_interconnect_0_RRESP),
.M_AXI_rvalid(m02_couplers_to_axi_interconnect_0_RVALID),
.M_AXI_wdata(m02_couplers_to_axi_interconnect_0_WDATA),
.M_AXI_wready(m02_couplers_to_axi_interconnect_0_WREADY),
.M_AXI_wstrb(m02_couplers_to_axi_interconnect_0_WSTRB),
.M_AXI_wvalid(m02_couplers_to_axi_interconnect_0_WVALID),
.S_ACLK(axi_interconnect_0_ACLK_net),
.S_ARESETN(axi_interconnect_0_ARESETN_net),
.S_AXI_araddr(xbar_to_m02_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m02_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m02_couplers_ARCACHE),
.S_AXI_arlen(xbar_to_m02_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m02_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m02_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m02_couplers_ARQOS),
.S_AXI_arready(xbar_to_m02_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m02_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m02_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m02_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m02_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m02_couplers_AWCACHE),
.S_AXI_awlen(xbar_to_m02_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m02_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m02_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m02_couplers_AWQOS),
.S_AXI_awready(xbar_to_m02_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m02_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m02_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),
.S_AXI_bready(xbar_to_m02_couplers_BREADY),
.S_AXI_bresp(xbar_to_m02_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m02_couplers_BVALID),
.S_AXI_rdata(xbar_to_m02_couplers_RDATA),
.S_AXI_rlast(xbar_to_m02_couplers_RLAST),
.S_AXI_rready(xbar_to_m02_couplers_RREADY),
.S_AXI_rresp(xbar_to_m02_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m02_couplers_RVALID),
.S_AXI_wdata(xbar_to_m02_couplers_WDATA),
.S_AXI_wlast(xbar_to_m02_couplers_WLAST),
.S_AXI_wready(xbar_to_m02_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m02_couplers_WVALID));
m03_couplers_imp_8ZVH8V m03_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(m03_couplers_to_axi_interconnect_0_ARADDR),
.M_AXI_arprot(m03_couplers_to_axi_interconnect_0_ARPROT),
.M_AXI_arready(m03_couplers_to_axi_interconnect_0_ARREADY),
.M_AXI_arvalid(m03_couplers_to_axi_interconnect_0_ARVALID),
.M_AXI_awaddr(m03_couplers_to_axi_interconnect_0_AWADDR),
.M_AXI_awprot(m03_couplers_to_axi_interconnect_0_AWPROT),
.M_AXI_awready(m03_couplers_to_axi_interconnect_0_AWREADY),
.M_AXI_awvalid(m03_couplers_to_axi_interconnect_0_AWVALID),
.M_AXI_bready(m03_couplers_to_axi_interconnect_0_BREADY),
.M_AXI_bresp(m03_couplers_to_axi_interconnect_0_BRESP),
.M_AXI_bvalid(m03_couplers_to_axi_interconnect_0_BVALID),
.M_AXI_rdata(m03_couplers_to_axi_interconnect_0_RDATA),
.M_AXI_rready(m03_couplers_to_axi_interconnect_0_RREADY),
.M_AXI_rresp(m03_couplers_to_axi_interconnect_0_RRESP),
.M_AXI_rvalid(m03_couplers_to_axi_interconnect_0_RVALID),
.M_AXI_wdata(m03_couplers_to_axi_interconnect_0_WDATA),
.M_AXI_wready(m03_couplers_to_axi_interconnect_0_WREADY),
.M_AXI_wstrb(m03_couplers_to_axi_interconnect_0_WSTRB),
.M_AXI_wvalid(m03_couplers_to_axi_interconnect_0_WVALID),
.S_ACLK(axi_interconnect_0_ACLK_net),
.S_ARESETN(axi_interconnect_0_ARESETN_net),
.S_AXI_araddr(xbar_to_m03_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m03_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m03_couplers_ARCACHE),
.S_AXI_arlen(xbar_to_m03_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m03_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m03_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m03_couplers_ARQOS),
.S_AXI_arready(xbar_to_m03_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m03_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m03_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m03_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m03_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m03_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m03_couplers_AWCACHE),
.S_AXI_awlen(xbar_to_m03_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m03_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m03_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m03_couplers_AWQOS),
.S_AXI_awready(xbar_to_m03_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m03_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m03_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m03_couplers_AWVALID),
.S_AXI_bready(xbar_to_m03_couplers_BREADY),
.S_AXI_bresp(xbar_to_m03_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m03_couplers_BVALID),
.S_AXI_rdata(xbar_to_m03_couplers_RDATA),
.S_AXI_rlast(xbar_to_m03_couplers_RLAST),
.S_AXI_rready(xbar_to_m03_couplers_RREADY),
.S_AXI_rresp(xbar_to_m03_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m03_couplers_RVALID),
.S_AXI_wdata(xbar_to_m03_couplers_WDATA),
.S_AXI_wlast(xbar_to_m03_couplers_WLAST),
.S_AXI_wready(xbar_to_m03_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m03_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m03_couplers_WVALID));
m04_couplers_imp_YN7N1I m04_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(m04_couplers_to_axi_interconnect_0_ARADDR),
.M_AXI_arburst(m04_couplers_to_axi_interconnect_0_ARBURST),
.M_AXI_arcache(m04_couplers_to_axi_interconnect_0_ARCACHE),
.M_AXI_arlen(m04_couplers_to_axi_interconnect_0_ARLEN),
.M_AXI_arlock(m04_couplers_to_axi_interconnect_0_ARLOCK),
.M_AXI_arprot(m04_couplers_to_axi_interconnect_0_ARPROT),
.M_AXI_arqos(m04_couplers_to_axi_interconnect_0_ARQOS),
.M_AXI_arready(m04_couplers_to_axi_interconnect_0_ARREADY),
.M_AXI_arsize(m04_couplers_to_axi_interconnect_0_ARSIZE),
.M_AXI_arvalid(m04_couplers_to_axi_interconnect_0_ARVALID),
.M_AXI_awaddr(m04_couplers_to_axi_interconnect_0_AWADDR),
.M_AXI_awburst(m04_couplers_to_axi_interconnect_0_AWBURST),
.M_AXI_awcache(m04_couplers_to_axi_interconnect_0_AWCACHE),
.M_AXI_awlen(m04_couplers_to_axi_interconnect_0_AWLEN),
.M_AXI_awlock(m04_couplers_to_axi_interconnect_0_AWLOCK),
.M_AXI_awprot(m04_couplers_to_axi_interconnect_0_AWPROT),
.M_AXI_awqos(m04_couplers_to_axi_interconnect_0_AWQOS),
.M_AXI_awready(m04_couplers_to_axi_interconnect_0_AWREADY),
.M_AXI_awsize(m04_couplers_to_axi_interconnect_0_AWSIZE),
.M_AXI_awvalid(m04_couplers_to_axi_interconnect_0_AWVALID),
.M_AXI_bready(m04_couplers_to_axi_interconnect_0_BREADY),
.M_AXI_bresp(m04_couplers_to_axi_interconnect_0_BRESP),
.M_AXI_bvalid(m04_couplers_to_axi_interconnect_0_BVALID),
.M_AXI_rdata(m04_couplers_to_axi_interconnect_0_RDATA),
.M_AXI_rlast(m04_couplers_to_axi_interconnect_0_RLAST),
.M_AXI_rready(m04_couplers_to_axi_interconnect_0_RREADY),
.M_AXI_rresp(m04_couplers_to_axi_interconnect_0_RRESP),
.M_AXI_rvalid(m04_couplers_to_axi_interconnect_0_RVALID),
.M_AXI_wdata(m04_couplers_to_axi_interconnect_0_WDATA),
.M_AXI_wlast(m04_couplers_to_axi_interconnect_0_WLAST),
.M_AXI_wready(m04_couplers_to_axi_interconnect_0_WREADY),
.M_AXI_wstrb(m04_couplers_to_axi_interconnect_0_WSTRB),
.M_AXI_wvalid(m04_couplers_to_axi_interconnect_0_WVALID),
.S_ACLK(axi_interconnect_0_ACLK_net),
.S_ARESETN(axi_interconnect_0_ARESETN_net),
.S_AXI_araddr(xbar_to_m04_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m04_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m04_couplers_ARCACHE),
.S_AXI_arlen(xbar_to_m04_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m04_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m04_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m04_couplers_ARQOS),
.S_AXI_arready(xbar_to_m04_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m04_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m04_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m04_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m04_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m04_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m04_couplers_AWCACHE),
.S_AXI_awlen(xbar_to_m04_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m04_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m04_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m04_couplers_AWQOS),
.S_AXI_awready(xbar_to_m04_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m04_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m04_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m04_couplers_AWVALID),
.S_AXI_bready(xbar_to_m04_couplers_BREADY),
.S_AXI_bresp(xbar_to_m04_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m04_couplers_BVALID),
.S_AXI_rdata(xbar_to_m04_couplers_RDATA),
.S_AXI_rlast(xbar_to_m04_couplers_RLAST),
.S_AXI_rready(xbar_to_m04_couplers_RREADY),
.S_AXI_rresp(xbar_to_m04_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m04_couplers_RVALID),
.S_AXI_wdata(xbar_to_m04_couplers_WDATA),
.S_AXI_wlast(xbar_to_m04_couplers_WLAST),
.S_AXI_wready(xbar_to_m04_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m04_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m04_couplers_WVALID));
s00_couplers_imp_1PH4J44 s00_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arburst(s00_couplers_to_xbar_ARBURST),
.M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),
.M_AXI_arid(s00_couplers_to_xbar_ARID),
.M_AXI_arlen(s00_couplers_to_xbar_ARLEN),
.M_AXI_arlock(s00_couplers_to_xbar_ARLOCK),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arqos(s00_couplers_to_xbar_ARQOS),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awburst(s00_couplers_to_xbar_AWBURST),
.M_AXI_awcache(s00_couplers_to_xbar_AWCACHE),
.M_AXI_awid(s00_couplers_to_xbar_AWID),
.M_AXI_awlen(s00_couplers_to_xbar_AWLEN),
.M_AXI_awlock(s00_couplers_to_xbar_AWLOCK),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awqos(s00_couplers_to_xbar_AWQOS),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awsize(s00_couplers_to_xbar_AWSIZE),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bid(s00_couplers_to_xbar_BID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rid(s00_couplers_to_xbar_RID),
.M_AXI_rlast(s00_couplers_to_xbar_RLAST),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wlast(s00_couplers_to_xbar_WLAST),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(axi_interconnect_0_ACLK_net),
.S_ARESETN(axi_interconnect_0_ARESETN_net),
.S_AXI_araddr(axi_interconnect_0_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_interconnect_0_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_interconnect_0_to_s00_couplers_ARCACHE),
.S_AXI_arid(axi_interconnect_0_to_s00_couplers_ARID),
.S_AXI_arlen(axi_interconnect_0_to_s00_couplers_ARLEN),
.S_AXI_arlock(axi_interconnect_0_to_s00_couplers_ARLOCK),
.S_AXI_arprot(axi_interconnect_0_to_s00_couplers_ARPROT),
.S_AXI_arqos(axi_interconnect_0_to_s00_couplers_ARQOS),
.S_AXI_arready(axi_interconnect_0_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_interconnect_0_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_interconnect_0_to_s00_couplers_ARVALID),
.S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE),
.S_AXI_awid(axi_interconnect_0_to_s00_couplers_AWID),
.S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN),
.S_AXI_awlock(axi_interconnect_0_to_s00_couplers_AWLOCK),
.S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT),
.S_AXI_awqos(axi_interconnect_0_to_s00_couplers_AWQOS),
.S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID),
.S_AXI_bid(axi_interconnect_0_to_s00_couplers_BID),
.S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID),
.S_AXI_rdata(axi_interconnect_0_to_s00_couplers_RDATA),
.S_AXI_rid(axi_interconnect_0_to_s00_couplers_RID),
.S_AXI_rlast(axi_interconnect_0_to_s00_couplers_RLAST),
.S_AXI_rready(axi_interconnect_0_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_interconnect_0_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_interconnect_0_to_s00_couplers_RVALID),
.S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA),
.S_AXI_wid(axi_interconnect_0_to_s00_couplers_WID),
.S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST),
.S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID));
s01_couplers_imp_K956Q9 s01_couplers
(.M_ACLK(axi_interconnect_0_ACLK_net),
.M_ARESETN(axi_interconnect_0_ARESETN_net),
.M_AXI_araddr(s01_couplers_to_xbar_ARADDR),
.M_AXI_arburst(s01_couplers_to_xbar_ARBURST),
.M_AXI_arcache(s01_couplers_to_xbar_ARCACHE),
.M_AXI_arid(s01_couplers_to_xbar_ARID),
.M_AXI_arlen(s01_couplers_to_xbar_ARLEN),
.M_AXI_arlock(s01_couplers_to_xbar_ARLOCK),
.M_AXI_arprot(s01_couplers_to_xbar_ARPROT),
.M_AXI_arqos(s01_couplers_to_xbar_ARQOS),
.M_AXI_arready(s01_couplers_to_xbar_ARREADY),
.M_AXI_arsize(s01_couplers_to_xbar_ARSIZE),
.M_AXI_arvalid(s01_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),
.M_AXI_awburst(s01_couplers_to_xbar_AWBURST),
.M_AXI_awcache(s01_couplers_to_xbar_AWCACHE),
.M_AXI_awid(s01_couplers_to_xbar_AWID),
.M_AXI_awlen(s01_couplers_to_xbar_AWLEN),
.M_AXI_awlock(s01_couplers_to_xbar_AWLOCK),
.M_AXI_awprot(s01_couplers_to_xbar_AWPROT),
.M_AXI_awqos(s01_couplers_to_xbar_AWQOS),
.M_AXI_awready(s01_couplers_to_xbar_AWREADY),
.M_AXI_awsize(s01_couplers_to_xbar_AWSIZE),
.M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),
.M_AXI_bid(s01_couplers_to_xbar_BID[13]),
.M_AXI_bready(s01_couplers_to_xbar_BREADY),
.M_AXI_bresp(s01_couplers_to_xbar_BRESP[2]),
.M_AXI_bvalid(s01_couplers_to_xbar_BVALID),
.M_AXI_rdata(s01_couplers_to_xbar_RDATA[32]),
.M_AXI_rid(s01_couplers_to_xbar_RID[13]),
.M_AXI_rlast(s01_couplers_to_xbar_RLAST),
.M_AXI_rready(s01_couplers_to_xbar_RREADY),
.M_AXI_rresp(s01_couplers_to_xbar_RRESP[2]),
.M_AXI_rvalid(s01_couplers_to_xbar_RVALID),
.M_AXI_wdata(s01_couplers_to_xbar_WDATA),
.M_AXI_wlast(s01_couplers_to_xbar_WLAST),
.M_AXI_wready(s01_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s01_couplers_to_xbar_WVALID),
.S_ACLK(axi_interconnect_0_ACLK_net),
.S_ARESETN(axi_interconnect_0_ARESETN_net),
.S_AXI_araddr(axi_interconnect_0_to_s01_couplers_ARADDR),
.S_AXI_arburst(axi_interconnect_0_to_s01_couplers_ARBURST),
.S_AXI_arcache(axi_interconnect_0_to_s01_couplers_ARCACHE),
.S_AXI_arid(axi_interconnect_0_to_s01_couplers_ARID),
.S_AXI_arlen(axi_interconnect_0_to_s01_couplers_ARLEN),
.S_AXI_arlock(axi_interconnect_0_to_s01_couplers_ARLOCK),
.S_AXI_arprot(axi_interconnect_0_to_s01_couplers_ARPROT),
.S_AXI_arqos(axi_interconnect_0_to_s01_couplers_ARQOS),
.S_AXI_arready(axi_interconnect_0_to_s01_couplers_ARREADY),
.S_AXI_arsize(axi_interconnect_0_to_s01_couplers_ARSIZE),
.S_AXI_arvalid(axi_interconnect_0_to_s01_couplers_ARVALID),
.S_AXI_awaddr(axi_interconnect_0_to_s01_couplers_AWADDR),
.S_AXI_awburst(axi_interconnect_0_to_s01_couplers_AWBURST),
.S_AXI_awcache(axi_interconnect_0_to_s01_couplers_AWCACHE),
.S_AXI_awid(axi_interconnect_0_to_s01_couplers_AWID),
.S_AXI_awlen(axi_interconnect_0_to_s01_couplers_AWLEN),
.S_AXI_awlock(axi_interconnect_0_to_s01_couplers_AWLOCK),
.S_AXI_awprot(axi_interconnect_0_to_s01_couplers_AWPROT),
.S_AXI_awqos(axi_interconnect_0_to_s01_couplers_AWQOS),
.S_AXI_awready(axi_interconnect_0_to_s01_couplers_AWREADY),
.S_AXI_awsize(axi_interconnect_0_to_s01_couplers_AWSIZE),
.S_AXI_awvalid(axi_interconnect_0_to_s01_couplers_AWVALID),
.S_AXI_bid(axi_interconnect_0_to_s01_couplers_BID),
.S_AXI_bready(axi_interconnect_0_to_s01_couplers_BREADY),
.S_AXI_bresp(axi_interconnect_0_to_s01_couplers_BRESP),
.S_AXI_bvalid(axi_interconnect_0_to_s01_couplers_BVALID),
.S_AXI_rdata(axi_interconnect_0_to_s01_couplers_RDATA),
.S_AXI_rid(axi_interconnect_0_to_s01_couplers_RID),
.S_AXI_rlast(axi_interconnect_0_to_s01_couplers_RLAST),
.S_AXI_rready(axi_interconnect_0_to_s01_couplers_RREADY),
.S_AXI_rresp(axi_interconnect_0_to_s01_couplers_RRESP),
.S_AXI_rvalid(axi_interconnect_0_to_s01_couplers_RVALID),
.S_AXI_wdata(axi_interconnect_0_to_s01_couplers_WDATA),
.S_AXI_wlast(axi_interconnect_0_to_s01_couplers_WLAST),
.S_AXI_wready(axi_interconnect_0_to_s01_couplers_WREADY),
.S_AXI_wstrb(axi_interconnect_0_to_s01_couplers_WSTRB),
.S_AXI_wvalid(axi_interconnect_0_to_s01_couplers_WVALID));
image_processing_2d_design_xbar_0 xbar
(.aclk(axi_interconnect_0_ACLK_net),
.aresetn(axi_interconnect_0_ARESETN_net),
.m_axi_araddr({xbar_to_m04_couplers_ARADDR,xbar_to_m03_couplers_ARADDR,xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arburst({xbar_to_m04_couplers_ARBURST,xbar_to_m03_couplers_ARBURST,xbar_to_m02_couplers_ARBURST,xbar_to_m01_couplers_ARBURST,xbar_to_m00_couplers_ARBURST}),
.m_axi_arcache({xbar_to_m04_couplers_ARCACHE,xbar_to_m03_couplers_ARCACHE,xbar_to_m02_couplers_ARCACHE,xbar_to_m01_couplers_ARCACHE,xbar_to_m00_couplers_ARCACHE}),
.m_axi_arlen({xbar_to_m04_couplers_ARLEN,xbar_to_m03_couplers_ARLEN,xbar_to_m02_couplers_ARLEN,xbar_to_m01_couplers_ARLEN,xbar_to_m00_couplers_ARLEN}),
.m_axi_arlock({xbar_to_m04_couplers_ARLOCK,xbar_to_m03_couplers_ARLOCK,xbar_to_m02_couplers_ARLOCK,xbar_to_m01_couplers_ARLOCK,xbar_to_m00_couplers_ARLOCK}),
.m_axi_arprot({xbar_to_m04_couplers_ARPROT,xbar_to_m03_couplers_ARPROT,xbar_to_m02_couplers_ARPROT,xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),
.m_axi_arqos({xbar_to_m04_couplers_ARQOS,xbar_to_m03_couplers_ARQOS,xbar_to_m02_couplers_ARQOS,xbar_to_m01_couplers_ARQOS,xbar_to_m00_couplers_ARQOS}),
.m_axi_arready({xbar_to_m04_couplers_ARREADY,xbar_to_m03_couplers_ARREADY,xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arregion({xbar_to_m04_couplers_ARREGION,xbar_to_m03_couplers_ARREGION,xbar_to_m02_couplers_ARREGION,xbar_to_m01_couplers_ARREGION,xbar_to_m00_couplers_ARREGION}),
.m_axi_arsize({xbar_to_m04_couplers_ARSIZE,xbar_to_m03_couplers_ARSIZE,xbar_to_m02_couplers_ARSIZE,xbar_to_m01_couplers_ARSIZE,xbar_to_m00_couplers_ARSIZE}),
.m_axi_arvalid({xbar_to_m04_couplers_ARVALID,xbar_to_m03_couplers_ARVALID,xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m04_couplers_AWADDR,xbar_to_m03_couplers_AWADDR,xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awburst({xbar_to_m04_couplers_AWBURST,xbar_to_m03_couplers_AWBURST,xbar_to_m02_couplers_AWBURST,xbar_to_m01_couplers_AWBURST,xbar_to_m00_couplers_AWBURST}),
.m_axi_awcache({xbar_to_m04_couplers_AWCACHE,xbar_to_m03_couplers_AWCACHE,xbar_to_m02_couplers_AWCACHE,xbar_to_m01_couplers_AWCACHE,xbar_to_m00_couplers_AWCACHE}),
.m_axi_awlen({xbar_to_m04_couplers_AWLEN,xbar_to_m03_couplers_AWLEN,xbar_to_m02_couplers_AWLEN,xbar_to_m01_couplers_AWLEN,xbar_to_m00_couplers_AWLEN}),
.m_axi_awlock({xbar_to_m04_couplers_AWLOCK,xbar_to_m03_couplers_AWLOCK,xbar_to_m02_couplers_AWLOCK,xbar_to_m01_couplers_AWLOCK,xbar_to_m00_couplers_AWLOCK}),
.m_axi_awprot({xbar_to_m04_couplers_AWPROT,xbar_to_m03_couplers_AWPROT,xbar_to_m02_couplers_AWPROT,xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),
.m_axi_awqos({xbar_to_m04_couplers_AWQOS,xbar_to_m03_couplers_AWQOS,xbar_to_m02_couplers_AWQOS,xbar_to_m01_couplers_AWQOS,xbar_to_m00_couplers_AWQOS}),
.m_axi_awready({xbar_to_m04_couplers_AWREADY,xbar_to_m03_couplers_AWREADY,xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awregion({xbar_to_m04_couplers_AWREGION,xbar_to_m03_couplers_AWREGION,xbar_to_m02_couplers_AWREGION,xbar_to_m01_couplers_AWREGION,xbar_to_m00_couplers_AWREGION}),
.m_axi_awsize({xbar_to_m04_couplers_AWSIZE,xbar_to_m03_couplers_AWSIZE,xbar_to_m02_couplers_AWSIZE,xbar_to_m01_couplers_AWSIZE,xbar_to_m00_couplers_AWSIZE}),
.m_axi_awvalid({xbar_to_m04_couplers_AWVALID,xbar_to_m03_couplers_AWVALID,xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m04_couplers_BREADY,xbar_to_m03_couplers_BREADY,xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m04_couplers_BRESP,xbar_to_m03_couplers_BRESP,xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m04_couplers_BVALID,xbar_to_m03_couplers_BVALID,xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m04_couplers_RDATA,xbar_to_m03_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rlast({xbar_to_m04_couplers_RLAST,xbar_to_m03_couplers_RLAST,xbar_to_m02_couplers_RLAST,xbar_to_m01_couplers_RLAST,xbar_to_m00_couplers_RLAST}),
.m_axi_rready({xbar_to_m04_couplers_RREADY,xbar_to_m03_couplers_RREADY,xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m04_couplers_RRESP,xbar_to_m03_couplers_RRESP,xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m04_couplers_RVALID,xbar_to_m03_couplers_RVALID,xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m04_couplers_WDATA,xbar_to_m03_couplers_WDATA,xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wlast({xbar_to_m04_couplers_WLAST,xbar_to_m03_couplers_WLAST,xbar_to_m02_couplers_WLAST,xbar_to_m01_couplers_WLAST,xbar_to_m00_couplers_WLAST}),
.m_axi_wready({xbar_to_m04_couplers_WREADY,xbar_to_m03_couplers_WREADY,xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m04_couplers_WSTRB,xbar_to_m03_couplers_WSTRB,xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),
.m_axi_wvalid({xbar_to_m04_couplers_WVALID,xbar_to_m03_couplers_WVALID,xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr({s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}),
.s_axi_arburst({s01_couplers_to_xbar_ARBURST,s01_couplers_to_xbar_ARBURST,s00_couplers_to_xbar_ARBURST}),
.s_axi_arcache({s01_couplers_to_xbar_ARCACHE,s01_couplers_to_xbar_ARCACHE,s01_couplers_to_xbar_ARCACHE,s01_couplers_to_xbar_ARCACHE,s00_couplers_to_xbar_ARCACHE}),
.s_axi_arid({s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,s01_couplers_to_xbar_ARID,1'b0,s00_couplers_to_xbar_ARID}),
.s_axi_arlen({s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s00_couplers_to_xbar_ARLEN}),
.s_axi_arlock({s01_couplers_to_xbar_ARLOCK,s00_couplers_to_xbar_ARLOCK}),
.s_axi_arprot({s01_couplers_to_xbar_ARPROT,s01_couplers_to_xbar_ARPROT,s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}),
.s_axi_arqos({s01_couplers_to_xbar_ARQOS,s01_couplers_to_xbar_ARQOS,s01_couplers_to_xbar_ARQOS,s01_couplers_to_xbar_ARQOS,s00_couplers_to_xbar_ARQOS}),
.s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}),
.s_axi_arsize({s01_couplers_to_xbar_ARSIZE,s01_couplers_to_xbar_ARSIZE,s01_couplers_to_xbar_ARSIZE,s00_couplers_to_xbar_ARSIZE}),
.s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}),
.s_axi_awaddr({s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s00_couplers_to_xbar_AWADDR}),
.s_axi_awburst({s01_couplers_to_xbar_AWBURST,s01_couplers_to_xbar_AWBURST,s00_couplers_to_xbar_AWBURST}),
.s_axi_awcache({s01_couplers_to_xbar_AWCACHE,s01_couplers_to_xbar_AWCACHE,s01_couplers_to_xbar_AWCACHE,s01_couplers_to_xbar_AWCACHE,s00_couplers_to_xbar_AWCACHE}),
.s_axi_awid({s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,s01_couplers_to_xbar_AWID,1'b0,s00_couplers_to_xbar_AWID}),
.s_axi_awlen({s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s00_couplers_to_xbar_AWLEN}),
.s_axi_awlock({s01_couplers_to_xbar_AWLOCK,s00_couplers_to_xbar_AWLOCK}),
.s_axi_awprot({s01_couplers_to_xbar_AWPROT,s01_couplers_to_xbar_AWPROT,s01_couplers_to_xbar_AWPROT,s00_couplers_to_xbar_AWPROT}),
.s_axi_awqos({s01_couplers_to_xbar_AWQOS,s01_couplers_to_xbar_AWQOS,s01_couplers_to_xbar_AWQOS,s01_couplers_to_xbar_AWQOS,s00_couplers_to_xbar_AWQOS}),
.s_axi_awready({s01_couplers_to_xbar_AWREADY,s00_couplers_to_xbar_AWREADY}),
.s_axi_awsize({s01_couplers_to_xbar_AWSIZE,s01_couplers_to_xbar_AWSIZE,s01_couplers_to_xbar_AWSIZE,s00_couplers_to_xbar_AWSIZE}),
.s_axi_awvalid({s01_couplers_to_xbar_AWVALID,s00_couplers_to_xbar_AWVALID}),
.s_axi_bid({s01_couplers_to_xbar_BID,s00_couplers_to_xbar_BID}),
.s_axi_bready({s01_couplers_to_xbar_BREADY,s00_couplers_to_xbar_BREADY}),
.s_axi_bresp({s01_couplers_to_xbar_BRESP,s00_couplers_to_xbar_BRESP}),
.s_axi_bvalid({s01_couplers_to_xbar_BVALID,s00_couplers_to_xbar_BVALID}),
.s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}),
.s_axi_rid({s01_couplers_to_xbar_RID,s00_couplers_to_xbar_RID}),
.s_axi_rlast({s01_couplers_to_xbar_RLAST,s00_couplers_to_xbar_RLAST}),
.s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}),
.s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}),
.s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}),
.s_axi_wdata({s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s00_couplers_to_xbar_WDATA}),
.s_axi_wlast({s01_couplers_to_xbar_WLAST,s00_couplers_to_xbar_WLAST}),
.s_axi_wready({s01_couplers_to_xbar_WREADY,s00_couplers_to_xbar_WREADY}),
.s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s01_couplers_to_xbar_WSTRB,s01_couplers_to_xbar_WSTRB,s01_couplers_to_xbar_WSTRB,s00_couplers_to_xbar_WSTRB}),
.s_axi_wvalid({s01_couplers_to_xbar_WVALID,s00_couplers_to_xbar_WVALID}));
endmodule
module m00_couplers_imp_J0QEI9
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arregion,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awregion,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output M_AXI_araddr;
output M_AXI_arburst;
output M_AXI_arcache;
output M_AXI_arlen;
output M_AXI_arlock;
output M_AXI_arprot;
output M_AXI_arqos;
input M_AXI_arready;
output M_AXI_arregion;
output M_AXI_arsize;
output M_AXI_arvalid;
output M_AXI_awaddr;
output M_AXI_awburst;
output M_AXI_awcache;
output M_AXI_awlen;
output M_AXI_awlock;
output M_AXI_awprot;
output M_AXI_awqos;
input M_AXI_awready;
output M_AXI_awregion;
output M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input M_AXI_bresp;
input M_AXI_bvalid;
input M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input M_AXI_rresp;
input M_AXI_rvalid;
output M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input S_AXI_araddr;
input S_AXI_arburst;
input S_AXI_arcache;
input S_AXI_arlen;
input S_AXI_arlock;
input S_AXI_arprot;
input S_AXI_arqos;
output S_AXI_arready;
input S_AXI_arregion;
input S_AXI_arsize;
input S_AXI_arvalid;
input S_AXI_awaddr;
input S_AXI_awburst;
input S_AXI_awcache;
input S_AXI_awlen;
input S_AXI_awlock;
input S_AXI_awprot;
input S_AXI_awqos;
output S_AXI_awready;
input S_AXI_awregion;
input S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output S_AXI_bresp;
output S_AXI_bvalid;
output S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output S_AXI_rresp;
output S_AXI_rvalid;
input S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input S_AXI_wstrb;
input S_AXI_wvalid;
wire m00_couplers_to_m00_couplers_ARADDR;
wire m00_couplers_to_m00_couplers_ARBURST;
wire m00_couplers_to_m00_couplers_ARCACHE;
wire m00_couplers_to_m00_couplers_ARLEN;
wire m00_couplers_to_m00_couplers_ARLOCK;
wire m00_couplers_to_m00_couplers_ARPROT;
wire m00_couplers_to_m00_couplers_ARQOS;
wire m00_couplers_to_m00_couplers_ARREADY;
wire m00_couplers_to_m00_couplers_ARREGION;
wire m00_couplers_to_m00_couplers_ARSIZE;
wire m00_couplers_to_m00_couplers_ARVALID;
wire m00_couplers_to_m00_couplers_AWADDR;
wire m00_couplers_to_m00_couplers_AWBURST;
wire m00_couplers_to_m00_couplers_AWCACHE;
wire m00_couplers_to_m00_couplers_AWLEN;
wire m00_couplers_to_m00_couplers_AWLOCK;
wire m00_couplers_to_m00_couplers_AWPROT;
wire m00_couplers_to_m00_couplers_AWQOS;
wire m00_couplers_to_m00_couplers_AWREADY;
wire m00_couplers_to_m00_couplers_AWREGION;
wire m00_couplers_to_m00_couplers_AWSIZE;
wire m00_couplers_to_m00_couplers_AWVALID;
wire m00_couplers_to_m00_couplers_BREADY;
wire m00_couplers_to_m00_couplers_BRESP;
wire m00_couplers_to_m00_couplers_BVALID;
wire m00_couplers_to_m00_couplers_RDATA;
wire m00_couplers_to_m00_couplers_RLAST;
wire m00_couplers_to_m00_couplers_RREADY;
wire m00_couplers_to_m00_couplers_RRESP;
wire m00_couplers_to_m00_couplers_RVALID;
wire m00_couplers_to_m00_couplers_WDATA;
wire m00_couplers_to_m00_couplers_WLAST;
wire m00_couplers_to_m00_couplers_WREADY;
wire m00_couplers_to_m00_couplers_WSTRB;
wire m00_couplers_to_m00_couplers_WVALID;
assign M_AXI_araddr = m00_couplers_to_m00_couplers_ARADDR;
assign M_AXI_arburst = m00_couplers_to_m00_couplers_ARBURST;
assign M_AXI_arcache = m00_couplers_to_m00_couplers_ARCACHE;
assign M_AXI_arlen = m00_couplers_to_m00_couplers_ARLEN;
assign M_AXI_arlock = m00_couplers_to_m00_couplers_ARLOCK;
assign M_AXI_arprot = m00_couplers_to_m00_couplers_ARPROT;
assign M_AXI_arqos = m00_couplers_to_m00_couplers_ARQOS;
assign M_AXI_arregion = m00_couplers_to_m00_couplers_ARREGION;
assign M_AXI_arsize = m00_couplers_to_m00_couplers_ARSIZE;
assign M_AXI_arvalid = m00_couplers_to_m00_couplers_ARVALID;
assign M_AXI_awaddr = m00_couplers_to_m00_couplers_AWADDR;
assign M_AXI_awburst = m00_couplers_to_m00_couplers_AWBURST;
assign M_AXI_awcache = m00_couplers_to_m00_couplers_AWCACHE;
assign M_AXI_awlen = m00_couplers_to_m00_couplers_AWLEN;
assign M_AXI_awlock = m00_couplers_to_m00_couplers_AWLOCK;
assign M_AXI_awprot = m00_couplers_to_m00_couplers_AWPROT;
assign M_AXI_awqos = m00_couplers_to_m00_couplers_AWQOS;
assign M_AXI_awregion = m00_couplers_to_m00_couplers_AWREGION;
assign M_AXI_awsize = m00_couplers_to_m00_couplers_AWSIZE;
assign M_AXI_awvalid = m00_couplers_to_m00_couplers_AWVALID;
assign M_AXI_bready = m00_couplers_to_m00_couplers_BREADY;
assign M_AXI_rready = m00_couplers_to_m00_couplers_RREADY;
assign M_AXI_wdata = m00_couplers_to_m00_couplers_WDATA;
assign M_AXI_wlast = m00_couplers_to_m00_couplers_WLAST;
assign M_AXI_wstrb = m00_couplers_to_m00_couplers_WSTRB;
assign M_AXI_wvalid = m00_couplers_to_m00_couplers_WVALID;
assign S_AXI_arready = m00_couplers_to_m00_couplers_ARREADY;
assign S_AXI_awready = m00_couplers_to_m00_couplers_AWREADY;
assign S_AXI_bresp = m00_couplers_to_m00_couplers_BRESP;
assign S_AXI_bvalid = m00_couplers_to_m00_couplers_BVALID;
assign S_AXI_rdata = m00_couplers_to_m00_couplers_RDATA;
assign S_AXI_rlast = m00_couplers_to_m00_couplers_RLAST;
assign S_AXI_rresp = m00_couplers_to_m00_couplers_RRESP;
assign S_AXI_rvalid = m00_couplers_to_m00_couplers_RVALID;
assign S_AXI_wready = m00_couplers_to_m00_couplers_WREADY;
assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr;
assign m00_couplers_to_m00_couplers_ARBURST = S_AXI_arburst;
assign m00_couplers_to_m00_couplers_ARCACHE = S_AXI_arcache;
assign m00_couplers_to_m00_couplers_ARLEN = S_AXI_arlen;
assign m00_couplers_to_m00_couplers_ARLOCK = S_AXI_arlock;
assign m00_couplers_to_m00_couplers_ARPROT = S_AXI_arprot;
assign m00_couplers_to_m00_couplers_ARQOS = S_AXI_arqos;
assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready;
assign m00_couplers_to_m00_couplers_ARREGION = S_AXI_arregion;
assign m00_couplers_to_m00_couplers_ARSIZE = S_AXI_arsize;
assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid;
assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr;
assign m00_couplers_to_m00_couplers_AWBURST = S_AXI_awburst;
assign m00_couplers_to_m00_couplers_AWCACHE = S_AXI_awcache;
assign m00_couplers_to_m00_couplers_AWLEN = S_AXI_awlen;
assign m00_couplers_to_m00_couplers_AWLOCK = S_AXI_awlock;
assign m00_couplers_to_m00_couplers_AWPROT = S_AXI_awprot;
assign m00_couplers_to_m00_couplers_AWQOS = S_AXI_awqos;
assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready;
assign m00_couplers_to_m00_couplers_AWREGION = S_AXI_awregion;
assign m00_couplers_to_m00_couplers_AWSIZE = S_AXI_awsize;
assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid;
assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready;
assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp;
assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid;
assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata;
assign m00_couplers_to_m00_couplers_RLAST = M_AXI_rlast;
assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready;
assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp;
assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid;
assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata;
assign m00_couplers_to_m00_couplers_WLAST = S_AXI_wlast;
assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready;
assign m00_couplers_to_m00_couplers_WSTRB = S_AXI_wstrb;
assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid;
endmodule
module m01_couplers_imp_1M9HB38
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_m01_couplers_ARADDR;
wire [2:0]auto_pc_to_m01_couplers_ARPROT;
wire auto_pc_to_m01_couplers_ARREADY;
wire auto_pc_to_m01_couplers_ARVALID;
wire [31:0]auto_pc_to_m01_couplers_AWADDR;
wire [2:0]auto_pc_to_m01_couplers_AWPROT;
wire auto_pc_to_m01_couplers_AWREADY;
wire auto_pc_to_m01_couplers_AWVALID;
wire auto_pc_to_m01_couplers_BREADY;
wire [1:0]auto_pc_to_m01_couplers_BRESP;
wire auto_pc_to_m01_couplers_BVALID;
wire [31:0]auto_pc_to_m01_couplers_RDATA;
wire auto_pc_to_m01_couplers_RREADY;
wire [1:0]auto_pc_to_m01_couplers_RRESP;
wire auto_pc_to_m01_couplers_RVALID;
wire [31:0]auto_pc_to_m01_couplers_WDATA;
wire auto_pc_to_m01_couplers_WREADY;
wire [3:0]auto_pc_to_m01_couplers_WSTRB;
wire auto_pc_to_m01_couplers_WVALID;
wire [31:0]m01_couplers_to_auto_pc_ARADDR;
wire [1:0]m01_couplers_to_auto_pc_ARBURST;
wire [3:0]m01_couplers_to_auto_pc_ARCACHE;
wire [7:0]m01_couplers_to_auto_pc_ARLEN;
wire [0:0]m01_couplers_to_auto_pc_ARLOCK;
wire [2:0]m01_couplers_to_auto_pc_ARPROT;
wire [3:0]m01_couplers_to_auto_pc_ARQOS;
wire m01_couplers_to_auto_pc_ARREADY;
wire [3:0]m01_couplers_to_auto_pc_ARREGION;
wire [2:0]m01_couplers_to_auto_pc_ARSIZE;
wire m01_couplers_to_auto_pc_ARVALID;
wire [31:0]m01_couplers_to_auto_pc_AWADDR;
wire [1:0]m01_couplers_to_auto_pc_AWBURST;
wire [3:0]m01_couplers_to_auto_pc_AWCACHE;
wire [7:0]m01_couplers_to_auto_pc_AWLEN;
wire [0:0]m01_couplers_to_auto_pc_AWLOCK;
wire [2:0]m01_couplers_to_auto_pc_AWPROT;
wire [3:0]m01_couplers_to_auto_pc_AWQOS;
wire m01_couplers_to_auto_pc_AWREADY;
wire [3:0]m01_couplers_to_auto_pc_AWREGION;
wire [2:0]m01_couplers_to_auto_pc_AWSIZE;
wire m01_couplers_to_auto_pc_AWVALID;
wire m01_couplers_to_auto_pc_BREADY;
wire [1:0]m01_couplers_to_auto_pc_BRESP;
wire m01_couplers_to_auto_pc_BVALID;
wire [31:0]m01_couplers_to_auto_pc_RDATA;
wire m01_couplers_to_auto_pc_RLAST;
wire m01_couplers_to_auto_pc_RREADY;
wire [1:0]m01_couplers_to_auto_pc_RRESP;
wire m01_couplers_to_auto_pc_RVALID;
wire [31:0]m01_couplers_to_auto_pc_WDATA;
wire m01_couplers_to_auto_pc_WLAST;
wire m01_couplers_to_auto_pc_WREADY;
wire [3:0]m01_couplers_to_auto_pc_WSTRB;
wire m01_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_m01_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_m01_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_m01_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_m01_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_m01_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_m01_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_m01_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_m01_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_m01_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = m01_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = m01_couplers_to_auto_pc_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = m01_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = m01_couplers_to_auto_pc_RDATA;
assign S_AXI_rlast = m01_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = m01_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = m01_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = m01_couplers_to_auto_pc_WREADY;
assign auto_pc_to_m01_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_m01_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_m01_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_m01_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_m01_couplers_WREADY = M_AXI_wready;
assign m01_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign m01_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign m01_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign m01_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign m01_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign m01_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign m01_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign m01_couplers_to_auto_pc_ARREGION = S_AXI_arregion[3:0];
assign m01_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign m01_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign m01_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign m01_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign m01_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign m01_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign m01_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign m01_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign m01_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign m01_couplers_to_auto_pc_AWREGION = S_AXI_awregion[3:0];
assign m01_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign m01_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign m01_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign m01_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign m01_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign m01_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign m01_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign m01_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
image_processing_2d_design_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m01_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_m01_couplers_ARPROT),
.m_axi_arready(auto_pc_to_m01_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_m01_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_m01_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_m01_couplers_AWPROT),
.m_axi_awready(auto_pc_to_m01_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_m01_couplers_AWVALID),
.m_axi_bready(auto_pc_to_m01_couplers_BREADY),
.m_axi_bresp(auto_pc_to_m01_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_m01_couplers_BVALID),
.m_axi_rdata(auto_pc_to_m01_couplers_RDATA),
.m_axi_rready(auto_pc_to_m01_couplers_RREADY),
.m_axi_rresp(auto_pc_to_m01_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_m01_couplers_RVALID),
.m_axi_wdata(auto_pc_to_m01_couplers_WDATA),
.m_axi_wready(auto_pc_to_m01_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_m01_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_m01_couplers_WVALID),
.s_axi_araddr(m01_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(m01_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(m01_couplers_to_auto_pc_ARCACHE),
.s_axi_arlen(m01_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(m01_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(m01_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(m01_couplers_to_auto_pc_ARQOS),
.s_axi_arready(m01_couplers_to_auto_pc_ARREADY),
.s_axi_arregion(m01_couplers_to_auto_pc_ARREGION),
.s_axi_arsize(m01_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(m01_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(m01_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(m01_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(m01_couplers_to_auto_pc_AWCACHE),
.s_axi_awlen(m01_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(m01_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(m01_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(m01_couplers_to_auto_pc_AWQOS),
.s_axi_awready(m01_couplers_to_auto_pc_AWREADY),
.s_axi_awregion(m01_couplers_to_auto_pc_AWREGION),
.s_axi_awsize(m01_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(m01_couplers_to_auto_pc_AWVALID),
.s_axi_bready(m01_couplers_to_auto_pc_BREADY),
.s_axi_bresp(m01_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(m01_couplers_to_auto_pc_BVALID),
.s_axi_rdata(m01_couplers_to_auto_pc_RDATA),
.s_axi_rlast(m01_couplers_to_auto_pc_RLAST),
.s_axi_rready(m01_couplers_to_auto_pc_RREADY),
.s_axi_rresp(m01_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(m01_couplers_to_auto_pc_RVALID),
.s_axi_wdata(m01_couplers_to_auto_pc_WDATA),
.s_axi_wlast(m01_couplers_to_auto_pc_WLAST),
.s_axi_wready(m01_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(m01_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(m01_couplers_to_auto_pc_WVALID));
endmodule
module m02_couplers_imp_1E92BOA
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_m02_couplers_ARADDR;
wire [2:0]auto_pc_to_m02_couplers_ARPROT;
wire auto_pc_to_m02_couplers_ARREADY;
wire auto_pc_to_m02_couplers_ARVALID;
wire [31:0]auto_pc_to_m02_couplers_AWADDR;
wire [2:0]auto_pc_to_m02_couplers_AWPROT;
wire auto_pc_to_m02_couplers_AWREADY;
wire auto_pc_to_m02_couplers_AWVALID;
wire auto_pc_to_m02_couplers_BREADY;
wire [1:0]auto_pc_to_m02_couplers_BRESP;
wire auto_pc_to_m02_couplers_BVALID;
wire [31:0]auto_pc_to_m02_couplers_RDATA;
wire auto_pc_to_m02_couplers_RREADY;
wire [1:0]auto_pc_to_m02_couplers_RRESP;
wire auto_pc_to_m02_couplers_RVALID;
wire [31:0]auto_pc_to_m02_couplers_WDATA;
wire auto_pc_to_m02_couplers_WREADY;
wire [3:0]auto_pc_to_m02_couplers_WSTRB;
wire auto_pc_to_m02_couplers_WVALID;
wire [31:0]m02_couplers_to_auto_pc_ARADDR;
wire [1:0]m02_couplers_to_auto_pc_ARBURST;
wire [3:0]m02_couplers_to_auto_pc_ARCACHE;
wire [7:0]m02_couplers_to_auto_pc_ARLEN;
wire [0:0]m02_couplers_to_auto_pc_ARLOCK;
wire [2:0]m02_couplers_to_auto_pc_ARPROT;
wire [3:0]m02_couplers_to_auto_pc_ARQOS;
wire m02_couplers_to_auto_pc_ARREADY;
wire [3:0]m02_couplers_to_auto_pc_ARREGION;
wire [2:0]m02_couplers_to_auto_pc_ARSIZE;
wire m02_couplers_to_auto_pc_ARVALID;
wire [31:0]m02_couplers_to_auto_pc_AWADDR;
wire [1:0]m02_couplers_to_auto_pc_AWBURST;
wire [3:0]m02_couplers_to_auto_pc_AWCACHE;
wire [7:0]m02_couplers_to_auto_pc_AWLEN;
wire [0:0]m02_couplers_to_auto_pc_AWLOCK;
wire [2:0]m02_couplers_to_auto_pc_AWPROT;
wire [3:0]m02_couplers_to_auto_pc_AWQOS;
wire m02_couplers_to_auto_pc_AWREADY;
wire [3:0]m02_couplers_to_auto_pc_AWREGION;
wire [2:0]m02_couplers_to_auto_pc_AWSIZE;
wire m02_couplers_to_auto_pc_AWVALID;
wire m02_couplers_to_auto_pc_BREADY;
wire [1:0]m02_couplers_to_auto_pc_BRESP;
wire m02_couplers_to_auto_pc_BVALID;
wire [31:0]m02_couplers_to_auto_pc_RDATA;
wire m02_couplers_to_auto_pc_RLAST;
wire m02_couplers_to_auto_pc_RREADY;
wire [1:0]m02_couplers_to_auto_pc_RRESP;
wire m02_couplers_to_auto_pc_RVALID;
wire [31:0]m02_couplers_to_auto_pc_WDATA;
wire m02_couplers_to_auto_pc_WLAST;
wire m02_couplers_to_auto_pc_WREADY;
wire [3:0]m02_couplers_to_auto_pc_WSTRB;
wire m02_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_m02_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_m02_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_m02_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_m02_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_m02_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_m02_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_m02_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_m02_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_m02_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_m02_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_m02_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = m02_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = m02_couplers_to_auto_pc_AWREADY;
assign S_AXI_bresp[1:0] = m02_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = m02_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = m02_couplers_to_auto_pc_RDATA;
assign S_AXI_rlast = m02_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = m02_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = m02_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = m02_couplers_to_auto_pc_WREADY;
assign auto_pc_to_m02_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_m02_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_m02_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_m02_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_m02_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_m02_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_m02_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_m02_couplers_WREADY = M_AXI_wready;
assign m02_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign m02_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign m02_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign m02_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign m02_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign m02_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign m02_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign m02_couplers_to_auto_pc_ARREGION = S_AXI_arregion[3:0];
assign m02_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign m02_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign m02_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign m02_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign m02_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign m02_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign m02_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign m02_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign m02_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign m02_couplers_to_auto_pc_AWREGION = S_AXI_awregion[3:0];
assign m02_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign m02_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign m02_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign m02_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign m02_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign m02_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign m02_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign m02_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
image_processing_2d_design_auto_pc_1 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m02_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_m02_couplers_ARPROT),
.m_axi_arready(auto_pc_to_m02_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_m02_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_m02_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_m02_couplers_AWPROT),
.m_axi_awready(auto_pc_to_m02_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_m02_couplers_AWVALID),
.m_axi_bready(auto_pc_to_m02_couplers_BREADY),
.m_axi_bresp(auto_pc_to_m02_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_m02_couplers_BVALID),
.m_axi_rdata(auto_pc_to_m02_couplers_RDATA),
.m_axi_rready(auto_pc_to_m02_couplers_RREADY),
.m_axi_rresp(auto_pc_to_m02_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_m02_couplers_RVALID),
.m_axi_wdata(auto_pc_to_m02_couplers_WDATA),
.m_axi_wready(auto_pc_to_m02_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_m02_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_m02_couplers_WVALID),
.s_axi_araddr(m02_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(m02_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(m02_couplers_to_auto_pc_ARCACHE),
.s_axi_arlen(m02_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(m02_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(m02_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(m02_couplers_to_auto_pc_ARQOS),
.s_axi_arready(m02_couplers_to_auto_pc_ARREADY),
.s_axi_arregion(m02_couplers_to_auto_pc_ARREGION),
.s_axi_arsize(m02_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(m02_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(m02_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(m02_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(m02_couplers_to_auto_pc_AWCACHE),
.s_axi_awlen(m02_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(m02_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(m02_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(m02_couplers_to_auto_pc_AWQOS),
.s_axi_awready(m02_couplers_to_auto_pc_AWREADY),
.s_axi_awregion(m02_couplers_to_auto_pc_AWREGION),
.s_axi_awsize(m02_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(m02_couplers_to_auto_pc_AWVALID),
.s_axi_bready(m02_couplers_to_auto_pc_BREADY),
.s_axi_bresp(m02_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(m02_couplers_to_auto_pc_BVALID),
.s_axi_rdata(m02_couplers_to_auto_pc_RDATA),
.s_axi_rlast(m02_couplers_to_auto_pc_RLAST),
.s_axi_rready(m02_couplers_to_auto_pc_RREADY),
.s_axi_rresp(m02_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(m02_couplers_to_auto_pc_RVALID),
.s_axi_wdata(m02_couplers_to_auto_pc_WDATA),
.s_axi_wlast(m02_couplers_to_auto_pc_WLAST),
.s_axi_wready(m02_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(m02_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(m02_couplers_to_auto_pc_WVALID));
endmodule
module m03_couplers_imp_8ZVH8V
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_m03_couplers_ARADDR;
wire [2:0]auto_pc_to_m03_couplers_ARPROT;
wire auto_pc_to_m03_couplers_ARREADY;
wire auto_pc_to_m03_couplers_ARVALID;
wire [31:0]auto_pc_to_m03_couplers_AWADDR;
wire [2:0]auto_pc_to_m03_couplers_AWPROT;
wire auto_pc_to_m03_couplers_AWREADY;
wire auto_pc_to_m03_couplers_AWVALID;
wire auto_pc_to_m03_couplers_BREADY;
wire [1:0]auto_pc_to_m03_couplers_BRESP;
wire auto_pc_to_m03_couplers_BVALID;
wire [31:0]auto_pc_to_m03_couplers_RDATA;
wire auto_pc_to_m03_couplers_RREADY;
wire [1:0]auto_pc_to_m03_couplers_RRESP;
wire auto_pc_to_m03_couplers_RVALID;
wire [31:0]auto_pc_to_m03_couplers_WDATA;
wire auto_pc_to_m03_couplers_WREADY;
wire [3:0]auto_pc_to_m03_couplers_WSTRB;
wire auto_pc_to_m03_couplers_WVALID;
wire [31:0]m03_couplers_to_auto_pc_ARADDR;
wire [1:0]m03_couplers_to_auto_pc_ARBURST;
wire [3:0]m03_couplers_to_auto_pc_ARCACHE;
wire [7:0]m03_couplers_to_auto_pc_ARLEN;
wire [0:0]m03_couplers_to_auto_pc_ARLOCK;
wire [2:0]m03_couplers_to_auto_pc_ARPROT;
wire [3:0]m03_couplers_to_auto_pc_ARQOS;
wire m03_couplers_to_auto_pc_ARREADY;
wire [3:0]m03_couplers_to_auto_pc_ARREGION;
wire [2:0]m03_couplers_to_auto_pc_ARSIZE;
wire m03_couplers_to_auto_pc_ARVALID;
wire [31:0]m03_couplers_to_auto_pc_AWADDR;
wire [1:0]m03_couplers_to_auto_pc_AWBURST;
wire [3:0]m03_couplers_to_auto_pc_AWCACHE;
wire [7:0]m03_couplers_to_auto_pc_AWLEN;
wire [0:0]m03_couplers_to_auto_pc_AWLOCK;
wire [2:0]m03_couplers_to_auto_pc_AWPROT;
wire [3:0]m03_couplers_to_auto_pc_AWQOS;
wire m03_couplers_to_auto_pc_AWREADY;
wire [3:0]m03_couplers_to_auto_pc_AWREGION;
wire [2:0]m03_couplers_to_auto_pc_AWSIZE;
wire m03_couplers_to_auto_pc_AWVALID;
wire m03_couplers_to_auto_pc_BREADY;
wire [1:0]m03_couplers_to_auto_pc_BRESP;
wire m03_couplers_to_auto_pc_BVALID;
wire [31:0]m03_couplers_to_auto_pc_RDATA;
wire m03_couplers_to_auto_pc_RLAST;
wire m03_couplers_to_auto_pc_RREADY;
wire [1:0]m03_couplers_to_auto_pc_RRESP;
wire m03_couplers_to_auto_pc_RVALID;
wire [31:0]m03_couplers_to_auto_pc_WDATA;
wire m03_couplers_to_auto_pc_WLAST;
wire m03_couplers_to_auto_pc_WREADY;
wire [3:0]m03_couplers_to_auto_pc_WSTRB;
wire m03_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_m03_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_m03_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_m03_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_m03_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_m03_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_m03_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_m03_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_m03_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_m03_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_m03_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_m03_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = m03_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = m03_couplers_to_auto_pc_AWREADY;
assign S_AXI_bresp[1:0] = m03_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = m03_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = m03_couplers_to_auto_pc_RDATA;
assign S_AXI_rlast = m03_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = m03_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = m03_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = m03_couplers_to_auto_pc_WREADY;
assign auto_pc_to_m03_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_m03_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_m03_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_m03_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_m03_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_m03_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_m03_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_m03_couplers_WREADY = M_AXI_wready;
assign m03_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign m03_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign m03_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign m03_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign m03_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign m03_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign m03_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign m03_couplers_to_auto_pc_ARREGION = S_AXI_arregion[3:0];
assign m03_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign m03_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign m03_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign m03_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign m03_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign m03_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign m03_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign m03_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign m03_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign m03_couplers_to_auto_pc_AWREGION = S_AXI_awregion[3:0];
assign m03_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign m03_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign m03_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign m03_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign m03_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign m03_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign m03_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign m03_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
image_processing_2d_design_auto_pc_2 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m03_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_m03_couplers_ARPROT),
.m_axi_arready(auto_pc_to_m03_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_m03_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_m03_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_m03_couplers_AWPROT),
.m_axi_awready(auto_pc_to_m03_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_m03_couplers_AWVALID),
.m_axi_bready(auto_pc_to_m03_couplers_BREADY),
.m_axi_bresp(auto_pc_to_m03_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_m03_couplers_BVALID),
.m_axi_rdata(auto_pc_to_m03_couplers_RDATA),
.m_axi_rready(auto_pc_to_m03_couplers_RREADY),
.m_axi_rresp(auto_pc_to_m03_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_m03_couplers_RVALID),
.m_axi_wdata(auto_pc_to_m03_couplers_WDATA),
.m_axi_wready(auto_pc_to_m03_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_m03_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_m03_couplers_WVALID),
.s_axi_araddr(m03_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(m03_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(m03_couplers_to_auto_pc_ARCACHE),
.s_axi_arlen(m03_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(m03_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(m03_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(m03_couplers_to_auto_pc_ARQOS),
.s_axi_arready(m03_couplers_to_auto_pc_ARREADY),
.s_axi_arregion(m03_couplers_to_auto_pc_ARREGION),
.s_axi_arsize(m03_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(m03_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(m03_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(m03_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(m03_couplers_to_auto_pc_AWCACHE),
.s_axi_awlen(m03_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(m03_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(m03_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(m03_couplers_to_auto_pc_AWQOS),
.s_axi_awready(m03_couplers_to_auto_pc_AWREADY),
.s_axi_awregion(m03_couplers_to_auto_pc_AWREGION),
.s_axi_awsize(m03_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(m03_couplers_to_auto_pc_AWVALID),
.s_axi_bready(m03_couplers_to_auto_pc_BREADY),
.s_axi_bresp(m03_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(m03_couplers_to_auto_pc_BVALID),
.s_axi_rdata(m03_couplers_to_auto_pc_RDATA),
.s_axi_rlast(m03_couplers_to_auto_pc_RLAST),
.s_axi_rready(m03_couplers_to_auto_pc_RREADY),
.s_axi_rresp(m03_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(m03_couplers_to_auto_pc_RVALID),
.s_axi_wdata(m03_couplers_to_auto_pc_WDATA),
.s_axi_wlast(m03_couplers_to_auto_pc_WLAST),
.s_axi_wready(m03_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(m03_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(m03_couplers_to_auto_pc_WVALID));
endmodule
module m04_couplers_imp_YN7N1I
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [3:0]M_AXI_arlen;
output [1:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [3:0]M_AXI_awlen;
output [1:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_m04_couplers_ARADDR;
wire [1:0]auto_pc_to_m04_couplers_ARBURST;
wire [3:0]auto_pc_to_m04_couplers_ARCACHE;
wire [3:0]auto_pc_to_m04_couplers_ARLEN;
wire [1:0]auto_pc_to_m04_couplers_ARLOCK;
wire [2:0]auto_pc_to_m04_couplers_ARPROT;
wire [3:0]auto_pc_to_m04_couplers_ARQOS;
wire auto_pc_to_m04_couplers_ARREADY;
wire [2:0]auto_pc_to_m04_couplers_ARSIZE;
wire auto_pc_to_m04_couplers_ARVALID;
wire [31:0]auto_pc_to_m04_couplers_AWADDR;
wire [1:0]auto_pc_to_m04_couplers_AWBURST;
wire [3:0]auto_pc_to_m04_couplers_AWCACHE;
wire [3:0]auto_pc_to_m04_couplers_AWLEN;
wire [1:0]auto_pc_to_m04_couplers_AWLOCK;
wire [2:0]auto_pc_to_m04_couplers_AWPROT;
wire [3:0]auto_pc_to_m04_couplers_AWQOS;
wire auto_pc_to_m04_couplers_AWREADY;
wire [2:0]auto_pc_to_m04_couplers_AWSIZE;
wire auto_pc_to_m04_couplers_AWVALID;
wire auto_pc_to_m04_couplers_BREADY;
wire [1:0]auto_pc_to_m04_couplers_BRESP;
wire auto_pc_to_m04_couplers_BVALID;
wire [31:0]auto_pc_to_m04_couplers_RDATA;
wire auto_pc_to_m04_couplers_RLAST;
wire auto_pc_to_m04_couplers_RREADY;
wire [1:0]auto_pc_to_m04_couplers_RRESP;
wire auto_pc_to_m04_couplers_RVALID;
wire [31:0]auto_pc_to_m04_couplers_WDATA;
wire auto_pc_to_m04_couplers_WLAST;
wire auto_pc_to_m04_couplers_WREADY;
wire [3:0]auto_pc_to_m04_couplers_WSTRB;
wire auto_pc_to_m04_couplers_WVALID;
wire [31:0]m04_couplers_to_auto_pc_ARADDR;
wire [1:0]m04_couplers_to_auto_pc_ARBURST;
wire [3:0]m04_couplers_to_auto_pc_ARCACHE;
wire [7:0]m04_couplers_to_auto_pc_ARLEN;
wire [0:0]m04_couplers_to_auto_pc_ARLOCK;
wire [2:0]m04_couplers_to_auto_pc_ARPROT;
wire [3:0]m04_couplers_to_auto_pc_ARQOS;
wire m04_couplers_to_auto_pc_ARREADY;
wire [3:0]m04_couplers_to_auto_pc_ARREGION;
wire [2:0]m04_couplers_to_auto_pc_ARSIZE;
wire m04_couplers_to_auto_pc_ARVALID;
wire [31:0]m04_couplers_to_auto_pc_AWADDR;
wire [1:0]m04_couplers_to_auto_pc_AWBURST;
wire [3:0]m04_couplers_to_auto_pc_AWCACHE;
wire [7:0]m04_couplers_to_auto_pc_AWLEN;
wire [0:0]m04_couplers_to_auto_pc_AWLOCK;
wire [2:0]m04_couplers_to_auto_pc_AWPROT;
wire [3:0]m04_couplers_to_auto_pc_AWQOS;
wire m04_couplers_to_auto_pc_AWREADY;
wire [3:0]m04_couplers_to_auto_pc_AWREGION;
wire [2:0]m04_couplers_to_auto_pc_AWSIZE;
wire m04_couplers_to_auto_pc_AWVALID;
wire m04_couplers_to_auto_pc_BREADY;
wire [1:0]m04_couplers_to_auto_pc_BRESP;
wire m04_couplers_to_auto_pc_BVALID;
wire [31:0]m04_couplers_to_auto_pc_RDATA;
wire m04_couplers_to_auto_pc_RLAST;
wire m04_couplers_to_auto_pc_RREADY;
wire [1:0]m04_couplers_to_auto_pc_RRESP;
wire m04_couplers_to_auto_pc_RVALID;
wire [31:0]m04_couplers_to_auto_pc_WDATA;
wire m04_couplers_to_auto_pc_WLAST;
wire m04_couplers_to_auto_pc_WREADY;
wire [3:0]m04_couplers_to_auto_pc_WSTRB;
wire m04_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_m04_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_pc_to_m04_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_pc_to_m04_couplers_ARCACHE;
assign M_AXI_arlen[3:0] = auto_pc_to_m04_couplers_ARLEN;
assign M_AXI_arlock[1:0] = auto_pc_to_m04_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_pc_to_m04_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_pc_to_m04_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_pc_to_m04_couplers_ARSIZE;
assign M_AXI_arvalid = auto_pc_to_m04_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_m04_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_pc_to_m04_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_pc_to_m04_couplers_AWCACHE;
assign M_AXI_awlen[3:0] = auto_pc_to_m04_couplers_AWLEN;
assign M_AXI_awlock[1:0] = auto_pc_to_m04_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_pc_to_m04_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_pc_to_m04_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_pc_to_m04_couplers_AWSIZE;
assign M_AXI_awvalid = auto_pc_to_m04_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_m04_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_m04_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_m04_couplers_WDATA;
assign M_AXI_wlast = auto_pc_to_m04_couplers_WLAST;
assign M_AXI_wstrb[3:0] = auto_pc_to_m04_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_m04_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = m04_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = m04_couplers_to_auto_pc_AWREADY;
assign S_AXI_bresp[1:0] = m04_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = m04_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = m04_couplers_to_auto_pc_RDATA;
assign S_AXI_rlast = m04_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = m04_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = m04_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = m04_couplers_to_auto_pc_WREADY;
assign auto_pc_to_m04_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_m04_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_m04_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_m04_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_m04_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_m04_couplers_RLAST = M_AXI_rlast;
assign auto_pc_to_m04_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_m04_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_m04_couplers_WREADY = M_AXI_wready;
assign m04_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign m04_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign m04_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign m04_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign m04_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign m04_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign m04_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign m04_couplers_to_auto_pc_ARREGION = S_AXI_arregion[3:0];
assign m04_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign m04_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign m04_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign m04_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign m04_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign m04_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign m04_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign m04_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign m04_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign m04_couplers_to_auto_pc_AWREGION = S_AXI_awregion[3:0];
assign m04_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign m04_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign m04_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign m04_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign m04_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign m04_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign m04_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign m04_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
image_processing_2d_design_auto_pc_3 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m04_couplers_ARADDR),
.m_axi_arburst(auto_pc_to_m04_couplers_ARBURST),
.m_axi_arcache(auto_pc_to_m04_couplers_ARCACHE),
.m_axi_arlen(auto_pc_to_m04_couplers_ARLEN),
.m_axi_arlock(auto_pc_to_m04_couplers_ARLOCK),
.m_axi_arprot(auto_pc_to_m04_couplers_ARPROT),
.m_axi_arqos(auto_pc_to_m04_couplers_ARQOS),
.m_axi_arready(auto_pc_to_m04_couplers_ARREADY),
.m_axi_arsize(auto_pc_to_m04_couplers_ARSIZE),
.m_axi_arvalid(auto_pc_to_m04_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_m04_couplers_AWADDR),
.m_axi_awburst(auto_pc_to_m04_couplers_AWBURST),
.m_axi_awcache(auto_pc_to_m04_couplers_AWCACHE),
.m_axi_awlen(auto_pc_to_m04_couplers_AWLEN),
.m_axi_awlock(auto_pc_to_m04_couplers_AWLOCK),
.m_axi_awprot(auto_pc_to_m04_couplers_AWPROT),
.m_axi_awqos(auto_pc_to_m04_couplers_AWQOS),
.m_axi_awready(auto_pc_to_m04_couplers_AWREADY),
.m_axi_awsize(auto_pc_to_m04_couplers_AWSIZE),
.m_axi_awvalid(auto_pc_to_m04_couplers_AWVALID),
.m_axi_bready(auto_pc_to_m04_couplers_BREADY),
.m_axi_bresp(auto_pc_to_m04_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_m04_couplers_BVALID),
.m_axi_rdata(auto_pc_to_m04_couplers_RDATA),
.m_axi_rlast(auto_pc_to_m04_couplers_RLAST),
.m_axi_rready(auto_pc_to_m04_couplers_RREADY),
.m_axi_rresp(auto_pc_to_m04_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_m04_couplers_RVALID),
.m_axi_wdata(auto_pc_to_m04_couplers_WDATA),
.m_axi_wlast(auto_pc_to_m04_couplers_WLAST),
.m_axi_wready(auto_pc_to_m04_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_m04_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_m04_couplers_WVALID),
.s_axi_araddr(m04_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(m04_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(m04_couplers_to_auto_pc_ARCACHE),
.s_axi_arlen(m04_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(m04_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(m04_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(m04_couplers_to_auto_pc_ARQOS),
.s_axi_arready(m04_couplers_to_auto_pc_ARREADY),
.s_axi_arregion(m04_couplers_to_auto_pc_ARREGION),
.s_axi_arsize(m04_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(m04_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(m04_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(m04_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(m04_couplers_to_auto_pc_AWCACHE),
.s_axi_awlen(m04_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(m04_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(m04_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(m04_couplers_to_auto_pc_AWQOS),
.s_axi_awready(m04_couplers_to_auto_pc_AWREADY),
.s_axi_awregion(m04_couplers_to_auto_pc_AWREGION),
.s_axi_awsize(m04_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(m04_couplers_to_auto_pc_AWVALID),
.s_axi_bready(m04_couplers_to_auto_pc_BREADY),
.s_axi_bresp(m04_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(m04_couplers_to_auto_pc_BVALID),
.s_axi_rdata(m04_couplers_to_auto_pc_RDATA),
.s_axi_rlast(m04_couplers_to_auto_pc_RLAST),
.s_axi_rready(m04_couplers_to_auto_pc_RREADY),
.s_axi_rresp(m04_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(m04_couplers_to_auto_pc_RVALID),
.s_axi_wdata(m04_couplers_to_auto_pc_WDATA),
.s_axi_wlast(m04_couplers_to_auto_pc_WLAST),
.s_axi_wready(m04_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(m04_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(m04_couplers_to_auto_pc_WVALID));
endmodule
module s00_couplers_imp_1PH4J44
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arid,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awid,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rid,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [11:0]M_AXI_arid;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [11:0]M_AXI_awid;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
input [12:0]M_AXI_bid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
input [12:0]M_AXI_rid;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [1:0]auto_pc_to_s00_couplers_ARBURST;
wire [3:0]auto_pc_to_s00_couplers_ARCACHE;
wire [11:0]auto_pc_to_s00_couplers_ARID;
wire [7:0]auto_pc_to_s00_couplers_ARLEN;
wire [0:0]auto_pc_to_s00_couplers_ARLOCK;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire [3:0]auto_pc_to_s00_couplers_ARQOS;
wire auto_pc_to_s00_couplers_ARREADY;
wire [2:0]auto_pc_to_s00_couplers_ARSIZE;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [1:0]auto_pc_to_s00_couplers_AWBURST;
wire [3:0]auto_pc_to_s00_couplers_AWCACHE;
wire [11:0]auto_pc_to_s00_couplers_AWID;
wire [7:0]auto_pc_to_s00_couplers_AWLEN;
wire [0:0]auto_pc_to_s00_couplers_AWLOCK;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire [3:0]auto_pc_to_s00_couplers_AWQOS;
wire auto_pc_to_s00_couplers_AWREADY;
wire [2:0]auto_pc_to_s00_couplers_AWSIZE;
wire auto_pc_to_s00_couplers_AWVALID;
wire [12:0]auto_pc_to_s00_couplers_BID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire [12:0]auto_pc_to_s00_couplers_RID;
wire auto_pc_to_s00_couplers_RLAST;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WLAST;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_pc_to_s00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_pc_to_s00_couplers_ARCACHE;
assign M_AXI_arid[11:0] = auto_pc_to_s00_couplers_ARID;
assign M_AXI_arlen[7:0] = auto_pc_to_s00_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_pc_to_s00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_pc_to_s00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_pc_to_s00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_pc_to_s00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_pc_to_s00_couplers_AWCACHE;
assign M_AXI_awid[11:0] = auto_pc_to_s00_couplers_AWID;
assign M_AXI_awlen[7:0] = auto_pc_to_s00_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_pc_to_s00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_pc_to_s00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_pc_to_s00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wlast = auto_pc_to_s00_couplers_WLAST;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BID = M_AXI_bid[12:0];
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RID = M_AXI_rid[12:0];
assign auto_pc_to_s00_couplers_RLAST = M_AXI_rlast;
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
image_processing_2d_design_auto_pc_4 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arburst(auto_pc_to_s00_couplers_ARBURST),
.m_axi_arcache(auto_pc_to_s00_couplers_ARCACHE),
.m_axi_arid(auto_pc_to_s00_couplers_ARID),
.m_axi_arlen(auto_pc_to_s00_couplers_ARLEN),
.m_axi_arlock(auto_pc_to_s00_couplers_ARLOCK),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arqos(auto_pc_to_s00_couplers_ARQOS),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arsize(auto_pc_to_s00_couplers_ARSIZE),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awburst(auto_pc_to_s00_couplers_AWBURST),
.m_axi_awcache(auto_pc_to_s00_couplers_AWCACHE),
.m_axi_awid(auto_pc_to_s00_couplers_AWID),
.m_axi_awlen(auto_pc_to_s00_couplers_AWLEN),
.m_axi_awlock(auto_pc_to_s00_couplers_AWLOCK),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awqos(auto_pc_to_s00_couplers_AWQOS),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awsize(auto_pc_to_s00_couplers_AWSIZE),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bid(auto_pc_to_s00_couplers_BID[11:0]),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rid(auto_pc_to_s00_couplers_RID[11:0]),
.m_axi_rlast(auto_pc_to_s00_couplers_RLAST),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wlast(auto_pc_to_s00_couplers_WLAST),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
module s01_couplers_imp_K956Q9
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arid,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awid,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rid,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output M_AXI_araddr;
output M_AXI_arburst;
output M_AXI_arcache;
output M_AXI_arid;
output M_AXI_arlen;
output M_AXI_arlock;
output M_AXI_arprot;
output M_AXI_arqos;
input M_AXI_arready;
output M_AXI_arsize;
output M_AXI_arvalid;
output M_AXI_awaddr;
output M_AXI_awburst;
output M_AXI_awcache;
output M_AXI_awid;
output M_AXI_awlen;
output M_AXI_awlock;
output M_AXI_awprot;
output M_AXI_awqos;
input M_AXI_awready;
output M_AXI_awsize;
output M_AXI_awvalid;
input M_AXI_bid;
output M_AXI_bready;
input M_AXI_bresp;
input M_AXI_bvalid;
input M_AXI_rdata;
input M_AXI_rid;
input M_AXI_rlast;
output M_AXI_rready;
input M_AXI_rresp;
input M_AXI_rvalid;
output M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input S_AXI_araddr;
input S_AXI_arburst;
input S_AXI_arcache;
input S_AXI_arid;
input S_AXI_arlen;
input S_AXI_arlock;
input S_AXI_arprot;
input S_AXI_arqos;
output S_AXI_arready;
input S_AXI_arsize;
input S_AXI_arvalid;
input S_AXI_awaddr;
input S_AXI_awburst;
input S_AXI_awcache;
input S_AXI_awid;
input S_AXI_awlen;
input S_AXI_awlock;
input S_AXI_awprot;
input S_AXI_awqos;
output S_AXI_awready;
input S_AXI_awsize;
input S_AXI_awvalid;
output S_AXI_bid;
input S_AXI_bready;
output S_AXI_bresp;
output S_AXI_bvalid;
output S_AXI_rdata;
output S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output S_AXI_rresp;
output S_AXI_rvalid;
input S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input S_AXI_wstrb;
input S_AXI_wvalid;
wire s01_couplers_to_s01_couplers_ARADDR;
wire s01_couplers_to_s01_couplers_ARBURST;
wire s01_couplers_to_s01_couplers_ARCACHE;
wire s01_couplers_to_s01_couplers_ARID;
wire s01_couplers_to_s01_couplers_ARLEN;
wire s01_couplers_to_s01_couplers_ARLOCK;
wire s01_couplers_to_s01_couplers_ARPROT;
wire s01_couplers_to_s01_couplers_ARQOS;
wire s01_couplers_to_s01_couplers_ARREADY;
wire s01_couplers_to_s01_couplers_ARSIZE;
wire s01_couplers_to_s01_couplers_ARVALID;
wire s01_couplers_to_s01_couplers_AWADDR;
wire s01_couplers_to_s01_couplers_AWBURST;
wire s01_couplers_to_s01_couplers_AWCACHE;
wire s01_couplers_to_s01_couplers_AWID;
wire s01_couplers_to_s01_couplers_AWLEN;
wire s01_couplers_to_s01_couplers_AWLOCK;
wire s01_couplers_to_s01_couplers_AWPROT;
wire s01_couplers_to_s01_couplers_AWQOS;
wire s01_couplers_to_s01_couplers_AWREADY;
wire s01_couplers_to_s01_couplers_AWSIZE;
wire s01_couplers_to_s01_couplers_AWVALID;
wire s01_couplers_to_s01_couplers_BID;
wire s01_couplers_to_s01_couplers_BREADY;
wire s01_couplers_to_s01_couplers_BRESP;
wire s01_couplers_to_s01_couplers_BVALID;
wire s01_couplers_to_s01_couplers_RDATA;
wire s01_couplers_to_s01_couplers_RID;
wire s01_couplers_to_s01_couplers_RLAST;
wire s01_couplers_to_s01_couplers_RREADY;
wire s01_couplers_to_s01_couplers_RRESP;
wire s01_couplers_to_s01_couplers_RVALID;
wire s01_couplers_to_s01_couplers_WDATA;
wire s01_couplers_to_s01_couplers_WLAST;
wire s01_couplers_to_s01_couplers_WREADY;
wire s01_couplers_to_s01_couplers_WSTRB;
wire s01_couplers_to_s01_couplers_WVALID;
assign M_AXI_araddr = s01_couplers_to_s01_couplers_ARADDR;
assign M_AXI_arburst = s01_couplers_to_s01_couplers_ARBURST;
assign M_AXI_arcache = s01_couplers_to_s01_couplers_ARCACHE;
assign M_AXI_arid = s01_couplers_to_s01_couplers_ARID;
assign M_AXI_arlen = s01_couplers_to_s01_couplers_ARLEN;
assign M_AXI_arlock = s01_couplers_to_s01_couplers_ARLOCK;
assign M_AXI_arprot = s01_couplers_to_s01_couplers_ARPROT;
assign M_AXI_arqos = s01_couplers_to_s01_couplers_ARQOS;
assign M_AXI_arsize = s01_couplers_to_s01_couplers_ARSIZE;
assign M_AXI_arvalid = s01_couplers_to_s01_couplers_ARVALID;
assign M_AXI_awaddr = s01_couplers_to_s01_couplers_AWADDR;
assign M_AXI_awburst = s01_couplers_to_s01_couplers_AWBURST;
assign M_AXI_awcache = s01_couplers_to_s01_couplers_AWCACHE;
assign M_AXI_awid = s01_couplers_to_s01_couplers_AWID;
assign M_AXI_awlen = s01_couplers_to_s01_couplers_AWLEN;
assign M_AXI_awlock = s01_couplers_to_s01_couplers_AWLOCK;
assign M_AXI_awprot = s01_couplers_to_s01_couplers_AWPROT;
assign M_AXI_awqos = s01_couplers_to_s01_couplers_AWQOS;
assign M_AXI_awsize = s01_couplers_to_s01_couplers_AWSIZE;
assign M_AXI_awvalid = s01_couplers_to_s01_couplers_AWVALID;
assign M_AXI_bready = s01_couplers_to_s01_couplers_BREADY;
assign M_AXI_rready = s01_couplers_to_s01_couplers_RREADY;
assign M_AXI_wdata = s01_couplers_to_s01_couplers_WDATA;
assign M_AXI_wlast = s01_couplers_to_s01_couplers_WLAST;
assign M_AXI_wstrb = s01_couplers_to_s01_couplers_WSTRB;
assign M_AXI_wvalid = s01_couplers_to_s01_couplers_WVALID;
assign S_AXI_arready = s01_couplers_to_s01_couplers_ARREADY;
assign S_AXI_awready = s01_couplers_to_s01_couplers_AWREADY;
assign S_AXI_bid = s01_couplers_to_s01_couplers_BID;
assign S_AXI_bresp = s01_couplers_to_s01_couplers_BRESP;
assign S_AXI_bvalid = s01_couplers_to_s01_couplers_BVALID;
assign S_AXI_rdata = s01_couplers_to_s01_couplers_RDATA;
assign S_AXI_rid = s01_couplers_to_s01_couplers_RID;
assign S_AXI_rlast = s01_couplers_to_s01_couplers_RLAST;
assign S_AXI_rresp = s01_couplers_to_s01_couplers_RRESP;
assign S_AXI_rvalid = s01_couplers_to_s01_couplers_RVALID;
assign S_AXI_wready = s01_couplers_to_s01_couplers_WREADY;
assign s01_couplers_to_s01_couplers_ARADDR = S_AXI_araddr;
assign s01_couplers_to_s01_couplers_ARBURST = S_AXI_arburst;
assign s01_couplers_to_s01_couplers_ARCACHE = S_AXI_arcache;
assign s01_couplers_to_s01_couplers_ARID = S_AXI_arid;
assign s01_couplers_to_s01_couplers_ARLEN = S_AXI_arlen;
assign s01_couplers_to_s01_couplers_ARLOCK = S_AXI_arlock;
assign s01_couplers_to_s01_couplers_ARPROT = S_AXI_arprot;
assign s01_couplers_to_s01_couplers_ARQOS = S_AXI_arqos;
assign s01_couplers_to_s01_couplers_ARREADY = M_AXI_arready;
assign s01_couplers_to_s01_couplers_ARSIZE = S_AXI_arsize;
assign s01_couplers_to_s01_couplers_ARVALID = S_AXI_arvalid;
assign s01_couplers_to_s01_couplers_AWADDR = S_AXI_awaddr;
assign s01_couplers_to_s01_couplers_AWBURST = S_AXI_awburst;
assign s01_couplers_to_s01_couplers_AWCACHE = S_AXI_awcache;
assign s01_couplers_to_s01_couplers_AWID = S_AXI_awid;
assign s01_couplers_to_s01_couplers_AWLEN = S_AXI_awlen;
assign s01_couplers_to_s01_couplers_AWLOCK = S_AXI_awlock;
assign s01_couplers_to_s01_couplers_AWPROT = S_AXI_awprot;
assign s01_couplers_to_s01_couplers_AWQOS = S_AXI_awqos;
assign s01_couplers_to_s01_couplers_AWREADY = M_AXI_awready;
assign s01_couplers_to_s01_couplers_AWSIZE = S_AXI_awsize;
assign s01_couplers_to_s01_couplers_AWVALID = S_AXI_awvalid;
assign s01_couplers_to_s01_couplers_BID = M_AXI_bid;
assign s01_couplers_to_s01_couplers_BREADY = S_AXI_bready;
assign s01_couplers_to_s01_couplers_BRESP = M_AXI_bresp;
assign s01_couplers_to_s01_couplers_BVALID = M_AXI_bvalid;
assign s01_couplers_to_s01_couplers_RDATA = M_AXI_rdata;
assign s01_couplers_to_s01_couplers_RID = M_AXI_rid;
assign s01_couplers_to_s01_couplers_RLAST = M_AXI_rlast;
assign s01_couplers_to_s01_couplers_RREADY = S_AXI_rready;
assign s01_couplers_to_s01_couplers_RRESP = M_AXI_rresp;
assign s01_couplers_to_s01_couplers_RVALID = M_AXI_rvalid;
assign s01_couplers_to_s01_couplers_WDATA = S_AXI_wdata;
assign s01_couplers_to_s01_couplers_WLAST = S_AXI_wlast;
assign s01_couplers_to_s01_couplers_WREADY = M_AXI_wready;
assign s01_couplers_to_s01_couplers_WSTRB = S_AXI_wstrb;
assign s01_couplers_to_s01_couplers_WVALID = S_AXI_wvalid;
endmodule
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: de_PLL.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module de_PLL (
areset,
inclk0,
c0);
input areset;
input inclk0;
output c0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "85.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "20"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "17"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "FAST"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_enable0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_enable1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_sclkout0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_sclkout1 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL de_PLL.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL de_PLL.ppf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL de_PLL.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL de_PLL.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL de_PLL.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL de_PLL_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL de_PLL_bb.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL de_PLL_waveforms.html TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL de_PLL_wave*.jpg FALSE FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2B_TB_V
`define SKY130_FD_SC_HD__OR2B_TB_V
/**
* or2b: 2-input OR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or2b.v"
module top();
// Inputs are registered
reg A;
reg B_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B_N = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B_N = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B_N = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B_N = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B_N = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__or2b dut (.A(A), .B_N(B_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2B_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O2BB2A_FUNCTIONAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_FUNCTIONAL_PP_V |
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module ym2610(
input PHI_M,
input nRESET,
inout [7:0] SDD,
input [1:0] SDA,
output nIRQ,
input nCS,
input nWR_RAW,
input nRD_RAW,
inout [7:0] SDRAD,
output [5:0] SDRA,
output SDRMPX, nSDROE,
inout [7:0] SDPAD,
output [3:0] SDPA,
output SDPMPX, nSDPOE,
output [5:0] ANA, // How many levels ?
output SH1, SH2, OP0, PHI_S // YM3016 output
);
wire nRD, nWR;
wire BUSY_MMR;
wire clr_run_A, set_run_A, clr_run_B, set_run_B;
// nCS gating - Not sure if it's that simple
assign nWR = nCS | nWR_RAW;
assign nRD = nCS | nRD_RAW;
// Internal
reg P1; // Internal clock
reg BUSY;
reg [1:0] BUSY_MMR_SR; // For edge detection
reg nWR_COPY;
reg [1:0] ADDR_COPY;
reg [7:0] DATA_COPY;
reg nWRITE_S;
reg [1:0] ADDR_S;
reg [7:0] DATA_S;
wire [15:0] ADPCM_OUT;
wire FLAG_A, FLAG_B;
reg [7:0] CLK_144_DIV;
wire TICK_144;
// Timer
wire [9:0] YMTIMER_TA_LOAD;
wire [7:0] YMTIMER_TB_LOAD;
wire [5:0] YMTIMER_CONFIG;
reg FLAG_A_S, FLAG_B_S;
// SSG
wire [11:0] SSG_FREQ_A;
wire [11:0] SSG_FREQ_B;
wire [11:0] SSG_FREQ_C;
wire [4:0] SSG_NOISE;
wire [5:0] SSG_EN;
wire [4:0] SSG_VOL_A;
wire [4:0] SSG_VOL_B;
wire [4:0] SSG_VOL_C;
wire [15:0] SSG_ENV_FREQ;
wire [3:0] SSG_ENV;
// FM
wire [3:0] FM_LFO;
wire [7:0] FM_KEYON;
wire [6:0] FM_DTMUL[3:0];
wire [6:0] FM_TL[3:0];
wire [7:0] FM_KSAR[3:0];
wire [7:0] FM_AMDR[3:0];
wire [4:0] FM_SR[3:0];
wire [7:0] FM_SLRR[3:0];
wire [3:0] FM_SSGEG[3:0];
wire [13:0] FM_FNUM13;
wire [13:0] FM_FNUM24;
wire [13:0] FM_2FNUM13;
wire [13:0] FM_2FNUM24;
wire [5:0] FM_FBALGO13;
wire [5:0] FM_FBALGO24;
wire [7:0] FM_PAN13;
wire [7:0] FM_PAN24;
// ADPCM-A
wire [7:0] PCMA_KEYON;
wire [7:0] PCMA_KEYOFF;
wire [5:0] PCMA_MVOL;
wire [7:0] PCMA_VOLPAN_A, PCMA_VOLPAN_B, PCMA_VOLPAN_C, PCMA_VOLPAN_D, PCMA_VOLPAN_E, PCMA_VOLPAN_F;
wire [15:0] PCMA_START_A, PCMA_START_B, PCMA_START_C, PCMA_START_D, PCMA_START_E, PCMA_START_F;
wire [15:0] PCMA_STOP_A, PCMA_STOP_B, PCMA_STOP_C, PCMA_STOP_D, PCMA_STOP_E, PCMA_STOP_F;
// ADPCM-B
wire [1:0] PCMB_PAN;
wire [15:0] PCMB_START_ADDR;
wire [15:0] PCMB_STOP_ADDR;
wire [15:0] PCMB_DELTA;
wire [7:0] PCMB_TL;
wire PCMB_RESET, PCMB_REPEAT, PCMB_START;
wire [7:0] ADPCM_FLAGS;
wire [5:0] PCMA_FLAGMASK;
wire PCMA_FLAGMASK_PCMB;
// Internal clock generation
always @(posedge PHI_M or negedge nRESET)
begin
if (!nRESET)
P1 <= 1'b0;
else
P1 <= ~P1;
end
assign TICK_144 = (CLK_144_DIV == 143) ? 1'b1 : 1'b0; // 143, not 0. Otherwise timers are goofy
// TICK_144 gen (CLK/144)
always @(posedge PHI_M)
begin
if (!nRESET)
CLK_144_DIV <= 0;
else
begin
if (CLK_144_DIV < 143) // / 12 / 12 = / 144
CLK_144_DIV <= CLK_144_DIV + 1'b1;
else
CLK_144_DIV <= 0;
end
end
// CPU interface
always @(posedge PHI_S)
begin
if (!nRESET)
begin
BUSY <= 1'b0;
end
else
begin
BUSY_MMR_SR <= {BUSY_MMR_SR[0], BUSY_MMR};
if (!nWR && !BUSY)
begin
// Do write
BUSY <= 1'b1;
nWR_COPY <= 1'b0;
ADDR_COPY <= SDA;
DATA_COPY <= SDD;
end
else
begin
if (BUSY_MMR) nWR_COPY <= 1'b1;
if (BUSY && BUSY_MMR_SR == 2'b10) BUSY <= 1'b0;
end
end
end
// Read registers
assign SDD = nRD ? 8'bzzzzzzzz : (SDA == 0) ? { BUSY, 5'h0, FLAG_B_S, FLAG_A_S } : // 4: Timer status
(SDA == 1) ? 8'h0 : // 5: SSG register data
(SDA == 2) ? ADPCM_FLAGS : // 6: ADPCM flags
8'h0; // 7: Nothing
always @(posedge PHI_M)
{ FLAG_B_S, FLAG_A_S } <= { FLAG_B, FLAG_A };
always @(posedge P1)
{nWRITE_S, ADDR_S, DATA_S} <= {nWR_COPY, ADDR_COPY, DATA_COPY};
ym_regs YMREGS(PHI_M, nRESET, nWRITE_S, ADDR_S, DATA_S, BUSY_MMR,
SSG_FREQ_A, SSG_FREQ_B, SSG_FREQ_C, SSG_NOISE, SSG_EN, SSG_VOL_A, SSG_VOL_B, SSG_VOL_C,
SSG_ENV_FREQ, SSG_ENV,
YMTIMER_TA_LOAD, YMTIMER_TB_LOAD, YMTIMER_CONFIG,
clr_run_A, set_run_A, clr_run_B, set_run_B,
PCMA_KEYON, PCMA_KEYOFF, PCMA_MVOL,
PCMA_VOLPAN_A, PCMA_VOLPAN_B, PCMA_VOLPAN_C, PCMA_VOLPAN_D, PCMA_VOLPAN_E, PCMA_VOLPAN_F,
PCMA_START_A, PCMA_START_B, PCMA_START_C, PCMA_START_D, PCMA_START_E, PCMA_START_F,
PCMA_STOP_A, PCMA_STOP_B, PCMA_STOP_C, PCMA_STOP_D, PCMA_STOP_E, PCMA_STOP_F,
PCMA_FLAGMASK, PCMA_FLAGMASK_PCMB,
PCMB_RESET, PCMB_REPEAT, PCMB_START,
PCMB_PAN, PCMB_START_ADDR, PCMB_STOP_ADDR, PCMB_DELTA, PCMB_TL
);
ym_timers YMTIMER(PHI_M, TICK_144, nRESET, YMTIMER_TA_LOAD, YMTIMER_TB_LOAD, YMTIMER_CONFIG,
clr_run_A, set_run_A, clr_run_B, set_run_B, FLAG_A, FLAG_B, nIRQ);
ym_ssg YMSSG(PHI_M, ANA, SSG_FREQ_A, SSG_FREQ_B, SSG_FREQ_C, SSG_NOISE, SSG_EN, SSG_VOL_A, SSG_VOL_B, SSG_VOL_C,
SSG_ENV_FREQ, SSG_ENV);
ym_fm YMFM(PHI_M);
ym_pcm YMPCM(PHI_M, TICK_144, nRESET,
PCMA_FLAGMASK, PCMA_FLAGMASK_PCMB,
ADPCM_FLAGS,
PCMA_KEYON, PCMA_KEYOFF,
PCMA_MVOL,
PCMA_VOLPAN_A, PCMA_VOLPAN_B, PCMA_VOLPAN_C, PCMA_VOLPAN_D, PCMA_VOLPAN_E, PCMA_VOLPAN_F,
PCMA_START_A, PCMA_STOP_A, PCMA_START_B, PCMA_STOP_B, PCMA_START_C, PCMA_STOP_C,
PCMA_START_D, PCMA_STOP_D, PCMA_START_E, PCMA_STOP_E, PCMA_START_F, PCMA_STOP_F,
SDRAD, SDRA, SDRMPX, nSDROE,
SDPAD, SDPA, SDPMPX, nSDPOE,
ADPCM_OUT,
PCMB_RESET, PCMB_REPEAT, PCMB_START,
PCMB_PAN, PCMB_START_ADDR, PCMB_STOP_ADDR, PCMB_DELTA, PCMB_TL);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_PP_V
/**
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
* well on input buffer, no taps,
* double-row-height cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire pwrgood0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood0_out_A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DLRBP_FUNCTIONAL_PP_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBP_FUNCTIONAL_PP_V |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*
*
* @reminder December 1, 2007
* Remember to remove wrbyteen and ctrl_ppp from the inputs to
* the ALU and its testbench
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
`include "control.h"
// Behavioral model for the ALU
module alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result,wrbyteen);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Clock signal
//input clock;
// Control signal bits - ppp
input [0:2] ctrl_ppp;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
parameter max_128_bits = 128'hffffffffffffffffffffffffffffffff;
//parameter max_128_bits = 128'hfffffffffffffffffffffffffffffffff;
//parameter max_128_bits = 128'h00112233445566778899aabbccddeeff1;
//parameter max_128_bits = 128'h123415678901234567890123456789012;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
// ===============================================================
always @(reg_A or reg_B or ctrl_ppp or ctrl_ww or alu_op or wrbyteen)
begin
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// ======================================================
// ======================================================
// SRA instruction >> mv to LSB >> bit 127
`aluwsra:
begin
case(ctrl_ww)
`w8: // sra AND `w8
begin
case(reg_B[5:7])
0:
begin
result[0:7]<=reg_A[0:7]>>0;
result[8:15]<=reg_A[8:15]>>0;
result[16:23]<=reg_A[16:23]>>0;
result[24:31]<=reg_A[24:31]>>0;
result[32:39]<=reg_A[32:39]>>0;
result[40:47]<=reg_A[40:47]>>0;
result[48:55]<=reg_A[48:55]>>0;
result[56:63]<=reg_A[56:63]>>0;
result[64:71]<=reg_A[64:71]>>0;
result[72:79]<=reg_A[72:79]>>0;
result[80:87]<=reg_A[80:87]>>0;
result[88:95]<=reg_A[88:95]>>0;
result[96:103]<=reg_A[96:103]>>0;
result[104:111]<=reg_A[104:111]>>0;
result[112:119]<=reg_A[112:119]>>0;
result[120:127]<=reg_A[120:127]>>0;
end
1:
begin
result[0:7]<=reg_A[0:7]>>1;
result[0]<=result[0];
result[8:15]<=reg_A[8:15]>>1;
result[8]<=result[8];
result[16:23]<=reg_A[16:23]>>1;
result[16]<=result[16];
result[24:31]<=reg_A[24:31]>>1;
result[24]<=result[24];
result[32:39]<=reg_A[32:39]>>1;
result[32]<=result[32];
result[40:47]<=reg_A[40:47]>>1;
result[40]<=result[40];
result[48:55]<=reg_A[48:55]>>1;
result[48]<=result[48];
result[56:63]<=reg_A[56:63]>>1;
result[56]<=result[56];
result[64:71]<=reg_A[64:71]>>1;
result[64]<=result[64];
result[72:79]<=reg_A[72:79]>>1;
result[72]<=result[72];
result[80:87]<=reg_A[80:87]>>1;
result[80]<=result[80];
result[88:95]<=reg_A[88:95]>>1;
result[88]<=result[88];
result[96:103]<=reg_A[96:103]>>1;
result[96]<=result[96];
result[104:111]<=reg_A[104:111]>>1;
result[104]<=result[104];
result[112:119]<=reg_A[112:119]>>1;
result[112]<=result[112];
result[120:127]<=reg_A[120:127]>>1;
result[120]<=result[120];
end
2:
begin
result[0:7]<=reg_A[0:7]>>2;
result[0]<=result[0];
result[1]<=result[0];
result[8:15]<=reg_A[8:15]>>2;
result[8]<=result[8];
result[9]<=result[8];
result[16:23]<=reg_A[16:23]>>2;
result[16]<=result[16];
result[17]<=result[16];
result[24:31]<=reg_A[24:31]>>2;
result[24]<=result[24];
result[25]<=result[24];
result[32:39]<=reg_A[32:39]>>2;
result[32]<=result[32];
result[33]<=result[32];
result[40:47]<=reg_A[40:47]>>2;
result[40]<=result[40];
result[41]<=result[40];
result[48:55]<=reg_A[48:55]>>2;
result[48]<=result[48];
result[49]<=result[48];
result[56:63]<=reg_A[56:63]>>2;
result[56]<=result[56];
result[57]<=result[56];
result[64:71]<=reg_A[64:71]>>2;
result[64]<=result[64];
result[65]<=result[64];
result[72:79]<=reg_A[72:79]>>2;
result[72]<=result[72];
result[73]<=result[72];
result[80:87]<=reg_A[80:87]>>2;
result[80]<=result[80];
result[81]<=result[80];
result[88:95]<=reg_A[88:95]>>2;
result[88]<=result[88];
result[89]<=result[88];
result[96:103]<=reg_A[96:103]>>2;
result[96]<=result[96];
result[97]<=result[96];
result[104:111]<=reg_A[104:111]>>2;
result[104]<=result[104];
result[105]<=result[104];
result[112:119]<=reg_A[112:119]>>2;
result[112]<=result[112];
result[113]<=result[112];
result[120:127]<=reg_A[120:127]>>2;
result[120]<=result[120];
result[121]<=result[120];
end
3:
begin
result[0:7]<=reg_A[0:7]>>3;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[8:15]<=reg_A[8:15]>>3;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[16:23]<=reg_A[16:23]>>3;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[24:31]<=reg_A[24:31]>>3;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[32:39]<=reg_A[32:39]>>3;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[40:47]<=reg_A[40:47]>>3;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[48:55]<=reg_A[48:55]>>3;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[56:63]<=reg_A[56:63]>>3;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[64:71]<=reg_A[64:71]>>3;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[72:79]<=reg_A[72:79]>>3;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[80:87]<=reg_A[80:87]>>3;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[88:95]<=reg_A[88:95]>>3;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[96:103]<=reg_A[96:103]>>3;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[104:111]<=reg_A[104:111]>>3;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[112:119]<=reg_A[112:119]>>3;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[120:127]<=reg_A[120:127]>>3;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
end
4:
begin
$display("entered 8 - shift 4");
result[0:7]<=reg_A[0:7]>>4;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[8:15]<=reg_A[8:15]>>4;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[11]<=result[8];
result[16:23]<=reg_A[16:23]>>4;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[24:31]<=reg_A[24:31]>>4;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[27]<=result[24];
result[32:39]<=reg_A[32:39]>>4;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[40:47]<=reg_A[40:47]>>4;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[43]<=result[40];
result[48:55]<=reg_A[48:55]>>4;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[56:63]<=reg_A[56:63]>>4;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[59]<=result[56];
result[64:71]<=reg_A[64:71]>>4;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[72:79]<=reg_A[72:79]>>4;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[75]<=result[72];
result[80:87]<=reg_A[80:87]>>4;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[88:95]<=reg_A[88:95]>>4;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[91]<=result[88];
result[96:103]<=reg_A[96:103]>>4;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[104:111]<=reg_A[104:111]>>4;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[107]<=result[104];
result[112:119]<=reg_A[112:119]>>4;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[120:127]<=reg_A[120:127]>>4;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
result[123]<=result[120];
end
5:
begin
result[0:7]<=reg_A[0:7]>>5;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[8:15]<=reg_A[8:15]>>5;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[11]<=result[8];
result[12]<=result[8];
result[16:23]<=reg_A[16:23]>>5;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[24:31]<=reg_A[24:31]>>5;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[27]<=result[24];
result[28]<=result[24];
result[32:39]<=reg_A[32:39]>>5;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[40:47]<=reg_A[40:47]>>5;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[43]<=result[40];
result[44]<=result[40];
result[48:55]<=reg_A[48:55]>>5;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[56:63]<=reg_A[56:63]>>5;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[59]<=result[56];
result[60]<=result[56];
result[64:71]<=reg_A[64:71]>>5;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[72:79]<=reg_A[72:79]>>5;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[75]<=result[72];
result[76]<=result[72];
result[80:87]<=reg_A[80:87]>>5;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[88:95]<=reg_A[88:95]>>5;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[91]<=result[88];
result[92]<=result[88];
result[96:103]<=reg_A[96:103]>>5;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[104:111]<=reg_A[104:111]>>5;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[107]<=result[104];
result[108]<=result[104];
result[112:119]<=reg_A[112:119]>>5;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[120:127]<=reg_A[120:127]>>5;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
result[123]<=result[120];
result[124]<=result[120];
end
6:
begin
result[0:7]<=reg_A[0:7]>>6;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[8:15]<=reg_A[8:15]>>6;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[11]<=result[8];
result[12]<=result[8];
result[13]<=result[8];
result[16:23]<=reg_A[16:23]>>6;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[24:31]<=reg_A[24:31]>>6;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[27]<=result[24];
result[28]<=result[24];
result[29]<=result[24];
result[32:39]<=reg_A[32:39]>>6;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[40:47]<=reg_A[40:47]>>6;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[43]<=result[40];
result[44]<=result[40];
result[45]<=result[40];
result[48:55]<=reg_A[48:55]>>6;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[56:63]<=reg_A[56:63]>>6;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[59]<=result[56];
result[60]<=result[56];
result[61]<=result[56];
result[64:71]<=reg_A[64:71]>>6;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[72:79]<=reg_A[72:79]>>6;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[75]<=result[72];
result[76]<=result[72];
result[77]<=result[72];
result[80:87]<=reg_A[80:87]>>6;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[88:95]<=reg_A[88:95]>>6;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[91]<=result[88];
result[92]<=result[88];
result[93]<=result[88];
result[96:103]<=reg_A[96:103]>>6;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[104:111]<=reg_A[104:111]>>6;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[107]<=result[104];
result[108]<=result[104];
result[109]<=result[104];
result[112:119]<=reg_A[112:119]>>6;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[120:127]<=reg_A[120:127]>>6;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
result[123]<=result[120];
result[124]<=result[120];
result[125]<=result[120];
end
default: // sra AND `w8 && 7
begin
result[0:7]<=reg_A[0:7]>>7;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[8:15]<=reg_A[8:15]>>7;
result[8]<=result[8];
result[9]<=result[8];
result[10]<=result[8];
result[11]<=result[8];
result[12]<=result[8];
result[13]<=result[8];
result[14]<=result[8];
result[16:23]<=reg_A[16:23]>>7;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[24:31]<=reg_A[24:31]>>7;
result[24]<=result[24];
result[25]<=result[24];
result[26]<=result[24];
result[27]<=result[24];
result[28]<=result[24];
result[29]<=result[24];
result[30]<=result[24];
result[32:39]<=reg_A[32:39]>>7;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[40:47]<=reg_A[40:47]>>7;
result[40]<=result[40];
result[41]<=result[40];
result[42]<=result[40];
result[43]<=result[40];
result[44]<=result[40];
result[45]<=result[40];
result[46]<=result[40];
result[48:55]<=reg_A[48:55]>>7;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[56:63]<=reg_A[56:63]>>7;
result[56]<=result[56];
result[57]<=result[56];
result[58]<=result[56];
result[59]<=result[56];
result[60]<=result[56];
result[61]<=result[56];
result[62]<=result[56];
result[64:71]<=reg_A[64:71]>>7;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[72:79]<=reg_A[72:79]>>7;
result[72]<=result[72];
result[73]<=result[72];
result[74]<=result[72];
result[75]<=result[72];
result[76]<=result[72];
result[77]<=result[72];
result[78]<=result[72];
result[80:87]<=reg_A[80:87]>>7;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[88:95]<=reg_A[88:95]>>7;
result[88]<=result[88];
result[89]<=result[88];
result[90]<=result[88];
result[91]<=result[88];
result[92]<=result[88];
result[93]<=result[88];
result[94]<=result[88];
result[96:103]<=reg_A[96:103]>>7;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[104:111]<=reg_A[104:111]>>7;
result[104]<=result[104];
result[105]<=result[104];
result[106]<=result[104];
result[107]<=result[104];
result[108]<=result[104];
result[109]<=result[104];
result[110]<=result[104];
result[112:119]<=reg_A[112:119]>>7;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[120:127]<=reg_A[120:127]>>7;
result[120]<=result[120];
result[121]<=result[120];
result[122]<=result[120];
result[123]<=result[120];
result[124]<=result[120];
result[125]<=result[120];
result[126]<=result[120];
end
endcase
end
`w16: // sra AND `w16
begin
case(reg_B[4:7])
0:
begin
result[0:15]<=reg_A[0:15]>>0;
result[16:31]<=reg_A[16:31]>>0;
result[32:47]<=reg_A[32:47]>>0;
result[48:63]<=reg_A[48:63]>>0;
result[64:79]<=reg_A[64:79]>>0;
result[80:95]<=reg_A[80:95]>>0;
result[96:111]<=reg_A[96:111]>>0;
result[112:127]<=reg_A[112:127]>>0;
end
1:
begin
result[0:15]<=reg_A[0:15]>>1;
result[0]<=result[0];
result[16:31]<=reg_A[16:31]>>1;
result[16]<=result[16];
result[32:47]<=reg_A[32:47]>>1;
result[32]<=result[32];
result[48:63]<=reg_A[48:63]>>1;
result[48]<=result[48];
result[64:79]<=reg_A[64:79]>>1;
result[64]<=result[64];
result[80:95]<=reg_A[80:95]>>1;
result[80]<=result[80];
result[96:111]<=reg_A[96:111]>>1;
result[96]<=result[96];
result[112:127]<=reg_A[112:127]>>1;
result[112]<=result[112];
end
2:
begin
result[0:15]<=reg_A[0:15]>>2;
result[0]<=result[0];
result[1]<=result[0];
result[16:31]<=reg_A[16:31]>>2;
result[16]<=result[16];
result[17]<=result[16];
result[32:47]<=reg_A[32:47]>>2;
result[32]<=result[32];
result[33]<=result[32];
result[48:63]<=reg_A[48:63]>>2;
result[48]<=result[48];
result[49]<=result[48];
result[64:79]<=reg_A[64:79]>>2;
result[64]<=result[64];
result[65]<=result[64];
result[80:95]<=reg_A[80:95]>>2;
result[80]<=result[80];
result[81]<=result[80];
result[96:111]<=reg_A[96:111]>>2;
result[96]<=result[96];
result[97]<=result[96];
result[112:127]<=reg_A[112:127]>>2;
result[112]<=result[112];
result[113]<=result[112];
end
3:
begin
result[0:15]<=reg_A[0:15]>>3;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[16:31]<=reg_A[16:31]>>3;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[32:47]<=reg_A[32:47]>>3;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[48:63]<=reg_A[48:63]>>3;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[64:79]<=reg_A[64:79]>>3;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[80:95]<=reg_A[80:95]>>3;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[96:111]<=reg_A[96:111]>>3;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[112:127]<=reg_A[112:127]>>3;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
end
4:
begin
$display("entered 16 - shift 4");
result[0:15]<=reg_A[0:15]>>4;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[16:31]<=reg_A[16:31]>>4;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[32:47]<=reg_A[32:47]>>4;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[48:63]<=reg_A[48:63]>>4;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[64:79]<=reg_A[64:79]>>4;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[80:95]<=reg_A[80:95]>>4;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[96:111]<=reg_A[96:111]>>4;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[112:127]<=reg_A[112:127]>>4;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
end
5:
begin
result[0:15]<=reg_A[0:15]>>5;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[16:31]<=reg_A[16:31]>>5;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[32:47]<=reg_A[32:47]>>5;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[48:63]<=reg_A[48:63]>>5;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[64:79]<=reg_A[64:79]>>5;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[80:95]<=reg_A[80:95]>>5;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[96:111]<=reg_A[96:111]>>5;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[112:127]<=reg_A[112:127]>>5;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
end
6:
begin
result[0:15]<=reg_A[0:15]>>6;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[16:31]<=reg_A[16:31]>>6;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[32:47]<=reg_A[32:47]>>6;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[48:63]<=reg_A[48:63]>>6;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[64:79]<=reg_A[64:79]>>6;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[80:95]<=reg_A[80:95]>>6;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[96:111]<=reg_A[96:111]>>6;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[112:127]<=reg_A[112:127]>>6;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
end
7:
begin
result[0:15]<=reg_A[0:15]>>7;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[16:31]<=reg_A[16:31]>>7;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[32:47]<=reg_A[32:47]>>7;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[48:63]<=reg_A[48:63]>>7;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[64:79]<=reg_A[64:79]>>7;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[80:95]<=reg_A[80:95]>>7;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[96:111]<=reg_A[96:111]>>7;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[112:127]<=reg_A[112:127]>>7;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
end
8:
begin
$display("entered 16 - shift 8");
result[0:15]<=reg_A[0:15]>>8;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[16:31]<=reg_A[16:31]>>8;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[32:47]<=reg_A[32:47]>>8;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[48:63]<=reg_A[48:63]>>8;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[64:79]<=reg_A[64:79]>>8;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[80:95]<=reg_A[80:95]>>8;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[96:111]<=reg_A[96:111]>>8;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[112:127]<=reg_A[112:127]>>8;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
end
9:
begin
result[0:15]<=reg_A[0:15]>>9;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[16:31]<=reg_A[16:31]>>9;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[32:47]<=reg_A[32:47]>>9;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[48:63]<=reg_A[48:63]>>9;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[64:79]<=reg_A[64:79]>>9;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[80:95]<=reg_A[80:95]>>9;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[96:111]<=reg_A[96:111]>>9;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[112:127]<=reg_A[112:127]>>9;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
end
10:
begin
result[0:15]<=reg_A[0:15]>>10;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[16:31]<=reg_A[16:31]>>10;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[32:47]<=reg_A[32:47]>>10;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[48:63]<=reg_A[48:63]>>10;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[64:79]<=reg_A[64:79]>>10;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[80:95]<=reg_A[80:95]>>10;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[96:111]<=reg_A[96:111]>>10;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[112:127]<=reg_A[112:127]>>10;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
end
11:
begin
result[0:15]<=reg_A[0:15]>>11;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[16:31]<=reg_A[16:31]>>11;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[32:47]<=reg_A[32:47]>>11;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[48:63]<=reg_A[48:63]>>11;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[64:79]<=reg_A[64:79]>>11;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[80:95]<=reg_A[80:95]>>11;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[96:111]<=reg_A[96:111]>>11;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[112:127]<=reg_A[112:127]>>11;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
end
12:
begin
result[0:15]<=reg_A[0:15]>>12;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[16:31]<=reg_A[16:31]>>12;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[27]<=result[16];
result[32:47]<=reg_A[32:47]>>12;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[48:63]<=reg_A[48:63]>>12;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[59]<=result[48];
result[64:79]<=reg_A[64:79]>>12;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[80:95]<=reg_A[80:95]>>12;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[91]<=result[80];
result[96:111]<=reg_A[96:111]>>12;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[112:127]<=reg_A[112:127]>>12;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
result[123]<=result[112];
end
13:
begin
result[0:15]<=reg_A[0:15]>>13;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[16:31]<=reg_A[16:31]>>13;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[27]<=result[16];
result[28]<=result[16];
result[32:47]<=reg_A[32:47]>>13;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[48:63]<=reg_A[48:63]>>13;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[59]<=result[48];
result[60]<=result[48];
result[64:79]<=reg_A[64:79]>>13;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[80:95]<=reg_A[80:95]>>13;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[91]<=result[80];
result[92]<=result[80];
result[96:111]<=reg_A[96:111]>>13;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[112:127]<=reg_A[112:127]>>13;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
result[123]<=result[112];
result[124]<=result[112];
end
14:
begin
$display("entered 16 - shift 14");
result[0:15]<=reg_A[0:15]>>14;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[16:31]<=reg_A[16:31]>>14;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[27]<=result[16];
result[28]<=result[16];
result[29]<=result[16];
result[32:47]<=reg_A[32:47]>>14;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[48:63]<=reg_A[48:63]>>14;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[59]<=result[48];
result[60]<=result[48];
result[61]<=result[48];
result[64:79]<=reg_A[64:79]>>14;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[80:95]<=reg_A[80:95]>>14;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[91]<=result[80];
result[92]<=result[80];
result[93]<=result[80];
result[96:111]<=reg_A[96:111]>>14;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[112:127]<=reg_A[112:127]>>14;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
result[123]<=result[112];
result[124]<=result[112];
result[125]<=result[112];
end
default: // sra AND `w16 && 15
begin
result[0:15]<=reg_A[0:15]>>15;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[16:31]<=reg_A[16:31]>>15;
result[16]<=result[16];
result[17]<=result[16];
result[18]<=result[16];
result[19]<=result[16];
result[20]<=result[16];
result[21]<=result[16];
result[22]<=result[16];
result[23]<=result[16];
result[24]<=result[16];
result[25]<=result[16];
result[26]<=result[16];
result[27]<=result[16];
result[28]<=result[16];
result[29]<=result[16];
result[30]<=result[16];
result[32:47]<=reg_A[32:47]>>15;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[48:63]<=reg_A[48:63]>>15;
result[48]<=result[48];
result[49]<=result[48];
result[50]<=result[48];
result[51]<=result[48];
result[52]<=result[48];
result[53]<=result[48];
result[54]<=result[48];
result[55]<=result[48];
result[56]<=result[48];
result[57]<=result[48];
result[58]<=result[48];
result[59]<=result[48];
result[60]<=result[48];
result[61]<=result[48];
result[62]<=result[48];
result[64:79]<=reg_A[64:79]>>15;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[80:95]<=reg_A[80:95]>>15;
result[80]<=result[80];
result[81]<=result[80];
result[82]<=result[80];
result[83]<=result[80];
result[84]<=result[80];
result[85]<=result[80];
result[86]<=result[80];
result[87]<=result[80];
result[88]<=result[80];
result[89]<=result[80];
result[90]<=result[80];
result[91]<=result[80];
result[92]<=result[80];
result[93]<=result[80];
result[94]<=result[80];
result[96:111]<=reg_A[96:111]>>15;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[112:127]<=reg_A[112:127]>>15;
result[112]<=result[112];
result[113]<=result[112];
result[114]<=result[112];
result[115]<=result[112];
result[116]<=result[112];
result[117]<=result[112];
result[118]<=result[112];
result[119]<=result[112];
result[120]<=result[112];
result[121]<=result[112];
result[122]<=result[112];
result[123]<=result[112];
result[124]<=result[112];
result[125]<=result[112];
result[126]<=result[112];
end
endcase
end
default: // sra AND `w32:
begin
case(reg_B[5:7])
0:
begin
result[0:31]<=reg_A[0:31]>>0;
result[32:63]<=reg_A[32:63]>>0;
result[64:95]<=reg_A[64:95]>>0;
result[96:127]<=reg_A[96:127]>>0;
end
1:
begin
result[0:31]<=reg_A[0:31]>>1;
result[0]<=result[0];
result[32:63]<=reg_A[32:63]>>1;
result[32]<=result[32];
result[64:95]<=reg_A[64:95]>>1;
result[64]<=result[64];
result[96:127]<=reg_A[96:127]>>1;
result[96]<=result[96];
end
2:
begin
result[0:31]<=reg_A[0:31]>>2;
result[0]<=result[0];
result[1]<=result[0];
result[32:63]<=reg_A[32:63]>>2;
result[32]<=result[32];
result[33]<=result[32];
result[64:95]<=reg_A[64:95]>>2;
result[64]<=result[64];
result[65]<=result[64];
result[96:127]<=reg_A[96:127]>>2;
result[96]<=result[96];
result[97]<=result[96];
end
3:
begin
result[0:31]<=reg_A[0:31]>>3;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[32:63]<=reg_A[32:63]>>3;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[64:95]<=reg_A[64:95]>>3;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[96:127]<=reg_A[96:127]>>3;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
end
4:
begin
result[0:31]<=reg_A[0:31]>>4;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[32:63]<=reg_A[32:63]>>4;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[64:95]<=reg_A[64:95]>>4;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[96:127]<=reg_A[96:127]>>4;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
end
5:
begin
result[0:31]<=reg_A[0:31]>>5;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[32:63]<=reg_A[32:63]>>5;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[64:95]<=reg_A[64:95]>>5;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[96:127]<=reg_A[96:127]>>5;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
end
6:
begin
result[0:31]<=reg_A[0:31]>>6;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[32:63]<=reg_A[32:63]>>6;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[64:95]<=reg_A[64:95]>>6;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[96:127]<=reg_A[96:127]>>6;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
end
7:
begin
result[0:31]<=reg_A[0:31]>>7;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[32:63]<=reg_A[32:63]>>7;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[64:95]<=reg_A[64:95]>>7;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[96:127]<=reg_A[96:127]>>7;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
end
8:
begin
$display("entered 32 - shift 8");
result[0:31]<=reg_A[0:31]>>8;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[32:63]<=reg_A[32:63]>>8;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[64:95]<=reg_A[64:95]>>8;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[96:127]<=reg_A[96:127]>>8;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
end
9:
begin
result[0:31]<=reg_A[0:31]>>9;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[32:63]<=reg_A[32:63]>>9;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[64:95]<=reg_A[64:95]>>9;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[96:127]<=reg_A[96:127]>>9;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
end
10:
begin
result[0:31]<=reg_A[0:31]>>10;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[32:63]<=reg_A[32:63]>>10;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[64:95]<=reg_A[64:95]>>10;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[96:127]<=reg_A[96:127]>>10;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
end
11:
begin
$display("entered 32 - shift 11");
result[0:31]<=reg_A[0:31]>>11;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[32:63]<=reg_A[32:63]>>11;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[64:95]<=reg_A[64:95]>>11;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[96:127]<=reg_A[96:127]>>11;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
end
12:
begin
$display("entered 32 - shift 12");
result[0:31]<=reg_A[0:31]>>12;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[32:63]<=reg_A[32:63]>>12;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[64:95]<=reg_A[64:95]>>12;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[96:127]<=reg_A[96:127]>>12;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
end
13:
begin
result[0:31]<=reg_A[0:31]>>13;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[32:63]<=reg_A[32:63]>>13;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[64:95]<=reg_A[64:95]>>13;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[96:127]<=reg_A[96:127]>>13;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
end
14:
begin
result[0:31]<=reg_A[0:31]>>14;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[32:63]<=reg_A[32:63]>>14;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[64:95]<=reg_A[64:95]>>14;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[96:127]<=reg_A[96:127]>>14;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
end
15:
begin
result[0:31]<=reg_A[0:31]>>15;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[32:63]<=reg_A[32:63]>>15;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[64:95]<=reg_A[64:95]>>15;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[96:127]<=reg_A[96:127]>>15;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
end
16:
begin
$display("entered 32 - shift 16");
result[0:31]<=reg_A[0:31]>>16;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[32:63]<=reg_A[32:63]>>16;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[64:95]<=reg_A[64:95]>>16;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[96:127]<=reg_A[96:127]>>16;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
end
17:
begin
result[0:31]<=reg_A[0:31]>>17;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[32:63]<=reg_A[32:63]>>17;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[64:95]<=reg_A[64:95]>>17;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[96:127]<=reg_A[96:127]>>17;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
end
18:
begin
result[0:31]<=reg_A[0:31]>>18;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[32:63]<=reg_A[32:63]>>18;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[64:95]<=reg_A[64:95]>>18;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[96:127]<=reg_A[96:127]>>18;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
end
19:
begin
result[0:31]<=reg_A[0:31]>>19;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[32:63]<=reg_A[32:63]>>19;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[64:95]<=reg_A[64:95]>>19;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[96:127]<=reg_A[96:127]>>19;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
end
20:
begin
result[0:31]<=reg_A[0:31]>>20;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[32:63]<=reg_A[32:63]>>20;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[64:95]<=reg_A[64:95]>>20;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[96:127]<=reg_A[96:127]>>20;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
end
21:
begin
result[0:31]<=reg_A[0:31]>>21;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[32:63]<=reg_A[32:63]>>21;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[64:95]<=reg_A[64:95]>>21;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[96:127]<=reg_A[96:127]>>21;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
end
22:
begin
result[0:31]<=reg_A[0:31]>>22;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[32:63]<=reg_A[32:63]>>22;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[64:95]<=reg_A[64:95]>>22;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[96:127]<=reg_A[96:127]>>22;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
end
23:
begin
result[0:31]<=reg_A[0:31]>>23;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[32:63]<=reg_A[32:63]>>23;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[64:95]<=reg_A[64:95]>>23;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[96:127]<=reg_A[96:127]>>23;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
end
24:
begin
result[0:31]<=reg_A[0:31]>>24;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[32:63]<=reg_A[32:63]>>24;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[64:95]<=reg_A[64:95]>>24;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[96:127]<=reg_A[96:127]>>24;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
end
25:
begin
result[0:31]<=reg_A[0:31]>>25;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[32:63]<=reg_A[32:63]>>25;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[64:95]<=reg_A[64:95]>>25;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[96:127]<=reg_A[96:127]>>25;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
end
26:
begin
result[0:31]<=reg_A[0:31]>>26;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[32:63]<=reg_A[32:63]>>26;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[64:95]<=reg_A[64:95]>>26;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[96:127]<=reg_A[96:127]>>26;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
end
27:
begin
$display("entered 32 - shift 27");
result[0:31]<=reg_A[0:31]>>27;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[32:63]<=reg_A[32:63]>>27;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[64:95]<=reg_A[64:95]>>27;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[96:127]<=reg_A[96:127]>>27;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
end
28:
begin
result[0:31]<=reg_A[0:31]>>28;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[27]<=result[0];
result[32:63]<=reg_A[32:63]>>28;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[59]<=result[32];
result[64:95]<=reg_A[64:95]>>28;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[91]<=result[64];
result[96:127]<=reg_A[96:127]>>28;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
result[123]<=result[96];
end
29:
begin
result[0:31]<=reg_A[0:31]>>29;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[27]<=result[0];
result[28]<=result[0];
result[32:63]<=reg_A[32:63]>>29;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[59]<=result[32];
result[60]<=result[32];
result[64:95]<=reg_A[64:95]>>29;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[91]<=result[64];
result[92]<=result[64];
result[96:127]<=reg_A[96:127]>>29;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
result[123]<=result[96];
result[124]<=result[96];
end
30:
begin
result[0:31]<=reg_A[0:31]>>30;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[27]<=result[0];
result[28]<=result[0];
result[29]<=result[0];
result[32:63]<=reg_A[32:63]>>30;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[59]<=result[32];
result[60]<=result[32];
result[61]<=result[32];
result[64:95]<=reg_A[64:95]>>30;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[91]<=result[64];
result[92]<=result[64];
result[93]<=result[64];
result[96:127]<=reg_A[96:127]>>30;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
result[123]<=result[96];
result[124]<=result[96];
result[125]<=result[96];
end
default: // sra AND `w32 && 31
begin
result[0:31]<=reg_A[0:31]>>31;
result[0]<=result[0];
result[1]<=result[0];
result[2]<=result[0];
result[3]<=result[0];
result[4]<=result[0];
result[5]<=result[0];
result[6]<=result[0];
result[7]<=result[0];
result[8]<=result[0];
result[9]<=result[0];
result[10]<=result[0];
result[11]<=result[0];
result[12]<=result[0];
result[13]<=result[0];
result[14]<=result[0];
result[15]<=result[0];
result[16]<=result[0];
result[17]<=result[0];
result[18]<=result[0];
result[19]<=result[0];
result[20]<=result[0];
result[21]<=result[0];
result[22]<=result[0];
result[23]<=result[0];
result[24]<=result[0];
result[25]<=result[0];
result[26]<=result[0];
result[27]<=result[0];
result[28]<=result[0];
result[29]<=result[0];
result[30]<=result[0];
result[32:63]<=reg_A[32:63]>>31;
result[32]<=result[32];
result[33]<=result[32];
result[34]<=result[32];
result[35]<=result[32];
result[36]<=result[32];
result[37]<=result[32];
result[38]<=result[32];
result[39]<=result[32];
result[40]<=result[32];
result[41]<=result[32];
result[42]<=result[32];
result[43]<=result[32];
result[44]<=result[32];
result[45]<=result[32];
result[46]<=result[32];
result[47]<=result[32];
result[48]<=result[32];
result[49]<=result[32];
result[50]<=result[32];
result[51]<=result[32];
result[52]<=result[32];
result[53]<=result[32];
result[54]<=result[32];
result[55]<=result[32];
result[56]<=result[32];
result[57]<=result[32];
result[58]<=result[32];
result[59]<=result[32];
result[60]<=result[32];
result[61]<=result[32];
result[62]<=result[32];
result[64:95]<=reg_A[64:95]>>31;
result[64]<=result[64];
result[65]<=result[64];
result[66]<=result[64];
result[67]<=result[64];
result[68]<=result[64];
result[69]<=result[64];
result[70]<=result[64];
result[71]<=result[64];
result[72]<=result[64];
result[73]<=result[64];
result[74]<=result[64];
result[75]<=result[64];
result[76]<=result[64];
result[77]<=result[64];
result[78]<=result[64];
result[79]<=result[64];
result[80]<=result[64];
result[81]<=result[64];
result[82]<=result[64];
result[83]<=result[64];
result[84]<=result[64];
result[85]<=result[64];
result[86]<=result[64];
result[87]<=result[64];
result[88]<=result[64];
result[89]<=result[64];
result[90]<=result[64];
result[91]<=result[64];
result[92]<=result[64];
result[93]<=result[64];
result[94]<=result[64];
result[96:127]<=reg_A[96:127]>>31;
result[96]<=result[96];
result[97]<=result[96];
result[98]<=result[96];
result[99]<=result[96];
result[100]<=result[96];
result[101]<=result[96];
result[102]<=result[96];
result[103]<=result[96];
result[104]<=result[96];
result[105]<=result[96];
result[106]<=result[96];
result[107]<=result[96];
result[108]<=result[96];
result[109]<=result[96];
result[110]<=result[96];
result[111]<=result[96];
result[112]<=result[96];
result[113]<=result[96];
result[114]<=result[96];
result[115]<=result[96];
result[116]<=result[96];
result[117]<=result[96];
result[118]<=result[96];
result[119]<=result[96];
result[120]<=result[96];
result[121]<=result[96];
result[122]<=result[96];
result[123]<=result[96];
result[124]<=result[96];
result[125]<=result[96];
result[126]<=result[96];
end
endcase
end
endcase
end
// ======================================================
// SLL instruction << mv to LSB << bit 127
`aluwsll:
begin
case(ctrl_ww)
`w8: // aluwsll AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]<<reg_B[5:7];
result[8:15]<=reg_A[8:15]<<reg_B[13:15];
result[16:23]<=reg_A[16:23]<<reg_B[21:23];
result[24:31]<=reg_A[24:31]<<reg_B[29:31];
result[32:39]<=reg_A[32:39]<<reg_B[37:39];
result[40:47]<=reg_A[40:47]<<reg_B[45:47];
result[48:55]<=reg_A[48:55]<<reg_B[53:55];
result[56:63]<=reg_A[56:63]<<reg_B[61:63];
result[64:71]<=reg_A[64:71]<<reg_B[69:71];
result[72:79]<=reg_A[72:79]<<reg_B[77:79];
result[80:87]<=reg_A[80:87]<<reg_B[85:87];
result[88:95]<=reg_A[88:95]<<reg_B[93:95];
result[96:103]<=reg_A[96:103]<<reg_B[101:103];
result[104:111]<=reg_A[104:111]<<reg_B[109:111];
result[112:119]<=reg_A[112:119]<<reg_B[117:119];
result[120:127]<=reg_A[120:127]<<reg_B[125:127];
end
`w16: // aluwsll AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]<<reg_B[12:15];
result[16:31]<=reg_A[16:31]<<reg_B[28:31];
result[32:47]<=reg_A[32:47]<<reg_B[44:47];
result[48:63]<=reg_A[48:63]<<reg_B[60:63];
result[64:79]<=reg_A[64:79]<<reg_B[76:79];
result[80:95]<=reg_A[80:95]<<reg_B[92:95];
result[96:111]<=reg_A[96:111]<<reg_B[108:111];
result[112:127]<=reg_A[112:127]<<reg_B[124:127];
end
`w32: // aluwsll AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]<<reg_B[27:31];
result[32:63]<=reg_A[32:63]<<reg_B[59:63];
result[64:95]<=reg_A[64:95]<<reg_B[91:95];
result[96:127]<=reg_A[96:127]<<reg_B[123:127];
end
default: // aluwsll AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
/*
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
*/
// ======================================================
// SRL instruction >> mv to MSB >> bit 0
`aluwsrl:
begin
case(ctrl_ppp)
`aa: // aluwsrl AND `aa
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default: // aluwsrl AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsrl AND `uu
begin
case(ctrl_ww)
`w8: // aluwsrl AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
end
`w16: // aluwsrl AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
end
`w32: // aluwsrl AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsrl AND `dd
begin
case(ctrl_ww)
`w8: // aluwsrl AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsrl AND `ee
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
end
`w16: // aluwsrl AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
end
`w32: // aluwsrl AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
end
default:
begin
// aluwsrl AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsrl AND `oo
begin
case(ctrl_ww)
`w8: // aluwsrl AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsrl AND `mm
begin
case(ctrl_ww)
`w8: // aluwsrl AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
end
`w16: // aluwsrl AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
end
`w32: // aluwsrl AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
end
default:
begin
// aluwsrl AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsrl AND `ll
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsrl AND Default
begin
result<=128'd0;
end
endcase
end
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// ================================================
// ADD instruction
`aluwadd:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// AND instruction
`aluwand:
begin
case(ctrl_ppp)
`aa: // aluwand AND `aa
begin
case(ctrl_ww)
`w8: // aluwand AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default: // aluwand AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwand AND `uu
begin
case(ctrl_ww)
`w8: // aluwand AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
end
`w16: // aluwand AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
end
`w32: // aluwand AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwand AND `dd
begin
case(ctrl_ww)
`w8: // aluwand AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwand AND `ee
begin
case(ctrl_ww)
`w8: // aluwand AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[112:119]<=reg_A[112:119]®_B[112:119];
end
`w16: // aluwand AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[96:111]<=reg_A[96:111]®_B[96:111];
end
`w32: // aluwand AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[64:95]<=reg_A[64:95]®_B[64:95];
end
default:
begin
// aluwand AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwand AND `oo
begin
case(ctrl_ww)
`w8: // aluwand AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]®_B[8:15];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]®_B[16:31];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]®_B[32:63];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwand AND `mm
begin
case(ctrl_ww)
`w8: // aluwand AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
end
`w16: // aluwand AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
end
`w32: // aluwand AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
end
default:
begin
// aluwand AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwand AND `ll
begin
case(ctrl_ww)
`w8: // aluwand AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwand AND Default
begin
result<=128'd0;
end
endcase
end
// ==============================================
// ================================================
// NOT instruction
`aluwnot:
begin
case(ctrl_ppp)
`aa: // aluwnot AND `aa
begin
case(ctrl_ww)
`w8: // aluwnot AND `aa AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `aa AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `aa AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default: // aluwnot AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwnot AND `uu
begin
case(ctrl_ww)
`w8: // aluwnot AND `uu AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
end
`w16: // aluwnot AND `uu AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
end
`w32: // aluwnot AND `uu AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwnot AND `dd
begin
case(ctrl_ww)
`w8: // aluwnot AND `dd AND `w8
begin
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `dd AND `w16
begin
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `dd AND `w32
begin
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwnot AND `ee
begin
case(ctrl_ww)
`w8: // aluwnot AND `ee AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[16:23]<=~reg_A[16:23];
result[32:39]<=~reg_A[32:39];
result[48:55]<=~reg_A[48:55];
result[64:71]<=~reg_A[64:71];
result[80:87]<=~reg_A[80:87];
result[96:103]<=~reg_A[96:103];
result[112:119]<=~reg_A[112:119];
end
`w16: // aluwnot AND `ee AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[32:47]<=~reg_A[32:47];
result[64:79]<=~reg_A[64:79];
result[96:111]<=~reg_A[96:111];
end
`w32: // aluwnot AND `ee AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[64:95]<=~reg_A[64:95];
end
default:
begin
// aluwnot AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwnot AND `oo
begin
case(ctrl_ww)
`w8: // aluwnot AND `oo AND `w8
begin
result[8:15]<=~reg_A[8:15];
result[24:31]<=~reg_A[24:31];
result[40:47]<=~reg_A[40:47];
result[56:63]<=~reg_A[56:63];
result[72:79]<=~reg_A[72:79];
result[88:95]<=~reg_A[88:95];
result[104:111]<=~reg_A[104:111];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `oo AND `w16
begin
result[16:31]<=~reg_A[16:31];
result[48:63]<=~reg_A[48:63];
result[80:95]<=~reg_A[80:95];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `oo AND `w32
begin
result[32:63]<=~reg_A[32:63];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwnot AND `mm
begin
case(ctrl_ww)
`w8: // aluwnot AND `mm AND `w8
begin
result[0:7]<=~reg_A[0:7];
end
`w16: // aluwnot AND `mm AND `w16
begin
result[0:15]<=~reg_A[0:15];
end
`w32: // aluwnot AND `mm AND `w32
begin
result[0:31]<=~reg_A[0:31];
end
default:
begin
// aluwnot AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwnot AND `ll
begin
case(ctrl_ww)
`w8: // aluwnot AND `ll AND `w8
begin
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `ll AND `w16
begin
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `ll AND `w32
begin
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwnot AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// OR instruction
`aluwor:
begin
case(ctrl_ppp)
`aa: // aluwor AND `aa
begin
case(ctrl_ww)
`w8: // aluwor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default: // aluwor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwor AND `uu
begin
case(ctrl_ww)
`w8: // aluwor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
end
`w16: // aluwor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
end
`w32: // aluwor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwor AND `dd
begin
case(ctrl_ww)
`w8: // aluwor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwor AND `ee
begin
case(ctrl_ww)
`w8: // aluwor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
end
`w16: // aluwor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
end
`w32: // aluwor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
end
default:
begin
// aluwor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwor AND `oo
begin
case(ctrl_ww)
`w8: // aluwor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwor AND `mm
begin
case(ctrl_ww)
`w8: // aluwor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
end
`w16: // aluwor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
end
`w32: // aluwor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
end
default:
begin
// aluwor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwor AND `ll
begin
case(ctrl_ww)
`w8: // aluwor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwor AND Default
begin
result<=128'd0;
end
endcase
end
// ========================================================
// XOR instruction
`aluwxor:
begin
case(ctrl_ppp)
`aa: // aluwxor AND `aa
begin
case(ctrl_ww)
`w8: // aluwxor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default: // aluwxor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwxor AND `uu
begin
case(ctrl_ww)
`w8: // aluwxor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
end
`w16: // aluwxor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
end
`w32: // aluwxor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwxor AND `dd
begin
case(ctrl_ww)
`w8: // aluwxor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwxor AND `ee
begin
case(ctrl_ww)
`w8: // aluwxor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
end
`w16: // aluwxor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
end
`w32: // aluwxor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
end
default:
begin
// aluwxor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwxor AND `oo
begin
case(ctrl_ww)
`w8: // aluwxor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwxor AND `mm
begin
case(ctrl_ww)
`w8: // aluwxor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
end
`w16: // aluwxor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
end
`w32: // aluwxor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
end
default:
begin
// aluwxor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwxor AND `ll
begin
case(ctrl_ww)
`w8: // aluwxor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwxor AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// SUB instruction
`aluwsub:
begin
case(ctrl_ppp)
`aa: // aluwsub AND `aa
begin
case(ctrl_ww)
`w8: // aluwsub AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default: // aluwsub AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsub AND `uu
begin
case(ctrl_ww)
`w8: // aluwsub AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
end
`w16: // aluwsub AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
end
`w32: // aluwsub AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsub AND `dd
begin
case(ctrl_ww)
`w8: // aluwsub AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsub AND `ee
begin
case(ctrl_ww)
`w8: // aluwsub AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
end
`w16: // aluwsub AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
end
`w32: // aluwsub AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
end
default:
begin
// aluwsub AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsub AND `oo
begin
case(ctrl_ww)
`w8: // aluwsub AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsub AND `mm
begin
case(ctrl_ww)
`w8: // aluwsub AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
end
`w16: // aluwsub AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
end
`w32: // aluwsub AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
end
default:
begin
// aluwsub AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsub AND `ll
begin
case(ctrl_ww)
`w8: // aluwsub AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsub AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
//================================================================================
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//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ================================================
// PRM instruction
`aluwprm:
begin
case(ctrl_ppp)
`aa: // aluwprm PRM `aa
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`uu: // aluwprm PRM `uu
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
//bytes8-15
result[64:127]<=64'd0;
end
`dd: // aluwprm PRM `dd
begin
//bytes0-7
result[0:63]<=64'd0;
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[0:7];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`ee: // aluwprm PRM `ee
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
//byte1
result[8:15]<=8'd0;
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
//byte3
result[24:31]<=8'd0;
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
//byte5
result[40:47]<=8'd0;
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
//byte7
result[56:63]<=8'd0;
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
//byte9
result[72:79]<=8'd0;
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
//byte11
result[88:95]<=8'd0;
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
//byte13
result[104:111]<=8'd0;
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
//byte15
result[120:127]<=8'd0;
end
`oo: // aluwprm PRM `oo
begin
//byte0
result[0:7]<=8'd0;
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
//byte2
result[16:23]<=8'd0;
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
//byte4
result[32:39]<=8'd0;
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
//byte6
result[48:55]<=8'd0;
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
//byte8
result[64:71]<=8'd0;
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
//byte10
result[80:87]<=8'd0;
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
//byte12
result[96:103]<=8'd0;
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
//byte14
result[112:119]<=8'd0;
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
`mm: // aluwprm PRM `mm
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
//bytes1-14
result[8:127]<=120'd0;
end
`ll: // aluwprm PRM `ll
begin
//bytes0-14
result[0:119]<=120'd0;
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
default: // aluwprm PRM Default
begin
result<=128'd0;
end
endcase
end
/*
* ========================================================
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*=========================================================
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*========================================================
*=======================================================
*========================================================
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*=======================================================
*=========================================================
*========================================================
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*=========================================================
*========================================================
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*=======================================================
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*=======================================================
*=======================================================
*/
// ================================================
// SLLI instruction
`aluwslli:
begin
case(ctrl_ppp)
`aa: // aluwslli SLLI `aa
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
`uu: // aluwslli SLLI `uu
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:127]<=64'd0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:127]<=64'd0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:127]<=64'd0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:127]<=64'd0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:127]<=64'd0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:127]<=64'd0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:127]<=64'd0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:127]<=64'd0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:127]<=64'd0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:127]<=64'd0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:63]<=reg_A[0:63];
result[64:127]<=64'd0;
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:127]<=64'd0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:127]<=64'd0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:127]<=64'd0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:127]<=64'd0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:127]<=64'd0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:127]<=64'd0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:127]<=64'd0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:127]<=64'd0;
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:127]<=64'd0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:127]<=64'd0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:127]<=64'd0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:127]<=64'd0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:127]<=64'd0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:127]<=64'd0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:127]<=64'd0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:127]<=64'd0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:127]<=64'd0;
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:127]<=64'd0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:127]<=64'd0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:127]<=64'd0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:127]<=64'd0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:127]<=64'd0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:127]<=64'd0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:127]<=64'd0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:127]<=64'd0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:127]<=64'd0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:127]<=64'd0;
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:127]<=64'd0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:127]<=64'd0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:127]<=64'd0;
end
endcase
end
endcase
end
`dd: // aluwslli SLLI `dd
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
3'd1:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:63]<=64'd0;
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
4'd1:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:63]<=64'd0;
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:63]<=64'd0;
result[64:127]<=reg_A[64:127];
end
5'd1:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:63]<=64'd0;
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
`ee: // aluwslli SLLI `ee
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:7]<=reg_A[0:7];
result[8:15]<=8'b0;
result[16:23]<=reg_A[16:23];
result[24:31]<=8'b0;
result[32:39]<=reg_A[33:39];
result[40:47]<=8'b0;
result[48:55]<=reg_A[48:55];
result[56:63]<=8'b0;
result[64:71]<=reg_A[64:71];
result[72:79]<=8'b0;
result[80:87]<=reg_A[80:87];
result[88:95]<=8'b0;
result[96:103]<=reg_A[96:103];
result[104:111]<=8'b0;
result[112:119]<=reg_A[112:119];
result[120:127]<=8'b0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<=8'b0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<=8'b0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<=8'b0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<=8'b0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<=8'b0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<=8'b0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<=8'b0;
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<=8'b0;
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<=8'b0;
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<=8'b0;
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<=8'b0;
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<=8'b0;
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<=8'b0;
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<=8'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<=16'b0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<=16'b0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<=16'b0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<=16'b0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<=16'b0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<=16'b0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<=16'b0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<=16'b0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<=16'b0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<=16'b0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<=16'b0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<=16'b0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<=16'b0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<=16'b0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<=16'b0;
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<=16'b0;
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<=16'b0;
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<=16'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<=32'b0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<=32'b0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<=32'b0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<=32'b0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<=32'b0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<=32'b0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<=32'b0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<=32'b0;
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<=32'b0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<=32'b0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<=32'b0;
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<=32'b0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<=32'b0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<=32'b0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<=32'b0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<=32'b0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<=32'b0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<=32'b0;
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<=32'b0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<=32'b0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<=32'b0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<=32'b0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<=32'b0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<=32'b0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<=32'b0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<=32'b0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<=32'b0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<=32'b0;
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<=32'b0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<=32'b0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<=32'b0;
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<=32'b0;
end
endcase
end
endcase
end
`oo: // aluwslli SLLI `oo
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<=8'b0;
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<=8'b0;
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<=8'b0;
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<=8'b0;
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<=8'b0;
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<=8'b0;
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<=8'b0;
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<=8'b0;
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<=16'b0;
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<=16'b0;
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<=16'b0;
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<=16'b0;
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<=32'b0;
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<=32'b0;
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
`mm: // aluwslli SLLI `mm
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:7]<=reg_A[0:7];
result[8:127]<=119'b0;
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:127]<=119'b0;
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:127]<=119'b0;
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:127]<=119'b0;
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:127]<=119'b0;
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:127]<=119'b0;
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:127]<=119'b0;
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:127]<=119'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:15]<=reg_A[0:15];
result[16:127]<=112'b0;
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:127]<=112'b0;
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:127]<=112'b0;
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:127]<=112'b0;
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:127]<=112'b0;
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:127]<=112'b0;
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:127]<=112'b0;
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:127]<=112'b0;
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:127]<=112'b0;
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:127]<=112'b0;
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:127]<=112'b0;
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:127]<=112'b0;
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:127]<=112'b0;
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:127]<=112'b0;
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:127]<=112'b0;
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:127]<=112'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:31]<=reg_A[0:31];
result[32:127]<=96'b0;
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:127]<=96'b0;
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:127]<=96'b0;
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:127]<=96'b0;
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:127]<=96'b0;
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:127]<=96'b0;
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:127]<=96'b0;
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:127]<=96'b0;
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:127]<=96'b0;
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:127]<=96'b0;
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:127]<=96'b0;
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:127]<=96'b0;
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:127]<=96'b0;
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:127]<=96'b0;
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:127]<=96'b0;
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:127]<=96'b0;
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:127]<=96'b0;
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:127]<=96'b0;
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:127]<=96'b0;
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:127]<=96'b0;
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:127]<=96'b0;
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:127]<=96'b0;
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:127]<=96'b0;
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:127]<=96'b0;
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:127]<=96'b0;
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:127]<=96'b0;
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:127]<=96'b0;
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:127]<=96'b0;
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:127]<=96'b0;
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:127]<=96'b0;
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:127]<=96'b0;
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:127]<=96'b0;
end
endcase
end
endcase
end
`ll: // aluwslli SLLI `ll
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:119]<=120'b0;
result[120:127]<=reg_A[120:127];
end
3'd1:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:119]<=120'b0;
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:111]<=112'b0;
result[112:127]<=reg_A[112:127];
end
4'd1:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:111]<=112'b0;
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:95]<=96'b0;
result[96:127]<=reg_A[96:127];
end
5'd1:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:95]<=96'b0;
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
endcase
end
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
`default_nettype none
`timescale 1ns/1ns
module tb_func_level;
`include "../task/task_disp_inst_issue.v"
`include "../task/task_disp_pcr.v"
`include "../task/task_disp_tag_info.v"
`include "../task/task_disp_branch.v"
`include "../task/task_disp_loadstore.v"
`include "../task/task_disp_logic_register.v"
localparam PL_CORE_CYCLE = 20; //It's necessary "Core Clock == Bus Clock". This restriction is removed near future.
localparam PL_BUS_CYCLE = 20; //
localparam PL_DPS_CYCLE = 18;
localparam PL_RESET_TIME = 20;
localparam PL_GCI_SIZE = 32'h0001_0000;
/****************************************
System
****************************************/
reg iCORE_CLOCK;
reg iBUS_CLOCK;
reg iDPS_CLOCK;
reg inRESET;
/****************************************
SCI
****************************************/
wire oSCI_TXD;
reg iSCI_RXD;
/****************************************
Memory BUS
****************************************/
//Req
wire oMEMORY_REQ;
wire iMEMORY_LOCK;
wire [1:0] oMEMORY_ORDER; //00=Byte Order 01=2Byte Order 10= Word Order 11= None
wire [3:0] oMEMORY_MASK;
wire oMEMORY_RW; //1:Write | 0:Read
wire [31:0] oMEMORY_ADDR;
//This -> Data RAM
wire [31:0] oMEMORY_DATA;
//Data RAM -> This
wire iMEMORY_VALID;
wire oMEMORY_BUSY;
wire [63:0] iMEMORY_DATA;
/****************************************
GCI BUS
****************************************/
//Request
wire oGCI_REQ; //Input
reg iGCI_BUSY;
wire oGCI_RW; //0=Read : 1=Write
wire [31:0] oGCI_ADDR;
wire [31:0] oGCI_DATA;
//Return
reg iGCI_REQ; //Output
wire oGCI_BUSY;
reg [31:0] iGCI_DATA;
//Interrupt
reg iGCI_IRQ_REQ;
reg [5:0] iGCI_IRQ_NUM;
wire oGCI_IRQ_ACK;
//Interrupt Controll
wire oIO_IRQ_CONFIG_TABLE_REQ;
wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY;
wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK;
wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID;
wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL;
wire [31:0] oDEBUG_PC;
wire [31:0] oDEBUG0;
/****************************************
Debug
****************************************/
reg iDEBUG_UART_RXD;
wire oDEBUG_UART_TXD;
reg iDEBUG_PARA_REQ;
wire oDEBUG_PARA_BUSY;
reg [7:0] iDEBUG_PARA_CMD;
reg [31:0] iDEBUG_PARA_DATA;
wire oDEBUG_PARA_VALID;
reg iDEBUG_PARA_BUSY;
wire oDEBUG_PARA_ERROR;
wire [31:0] oDEBUG_PARA_DATA;
/******************************************************
Target
******************************************************/
mist1032sa TARGET(
/****************************************
System
****************************************/
.iCORE_CLOCK(iCORE_CLOCK),
.iBUS_CLOCK(iBUS_CLOCK),
.iDPS_CLOCK(iDPS_CLOCK),
.inRESET(inRESET),
/****************************************
SCI
****************************************/
.oSCI_TXD(oSCI_TXD),
.iSCI_RXD(iSCI_RXD),
/****************************************
Memory BUS
****************************************/
//Req
.oMEMORY_REQ(oMEMORY_REQ),
.iMEMORY_LOCK(iMEMORY_LOCK),
.oMEMORY_ORDER(oMEMORY_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oMEMORY_MASK(oMEMORY_MASK),
.oMEMORY_RW(oMEMORY_RW), //1:Write | 0:Read
.oMEMORY_ADDR(oMEMORY_ADDR),
//This -> Data RAM
.oMEMORY_DATA(oMEMORY_DATA),
//Data RAM -> This
.iMEMORY_VALID(iMEMORY_VALID),
.oMEMORY_BUSY(oMEMORY_BUSY),
.iMEMORY_DATA(iMEMORY_DATA),
/****************************************
GCI BUS
****************************************/
//Request
.oGCI_REQ(oGCI_REQ), //Input
.iGCI_BUSY(iGCI_BUSY),
.oGCI_RW(oGCI_RW), //0=Read : 1=Write
.oGCI_ADDR(oGCI_ADDR),
.oGCI_DATA(oGCI_DATA),
//Return
.iGCI_REQ(iGCI_REQ), //Output
.oGCI_BUSY(oGCI_BUSY),
.iGCI_DATA(iGCI_DATA),
//Interrupt
.iGCI_IRQ_REQ(iGCI_IRQ_REQ),
.iGCI_IRQ_NUM(iGCI_IRQ_NUM),
.oGCI_IRQ_ACK(oGCI_IRQ_ACK),
//Interrupt Controll
.oIO_IRQ_CONFIG_TABLE_REQ(oIO_IRQ_CONFIG_TABLE_REQ),
.oIO_IRQ_CONFIG_TABLE_ENTRY(oIO_IRQ_CONFIG_TABLE_ENTRY),
.oIO_IRQ_CONFIG_TABLE_FLAG_MASK(oIO_IRQ_CONFIG_TABLE_FLAG_MASK),
.oIO_IRQ_CONFIG_TABLE_FLAG_VALID(oIO_IRQ_CONFIG_TABLE_FLAG_VALID),
.oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL(oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL),
.oDEBUG_PC(oDEBUG_PC),
.oDEBUG0(oDEBUG0),
/****************************************
Debug
****************************************/
.iDEBUG_UART_RXD(iDEBUG_UART_RXD),
.oDEBUG_UART_TXD(oDEBUG_UART_TXD),
.iDEBUG_PARA_REQ(iDEBUG_PARA_REQ),
.oDEBUG_PARA_BUSY(oDEBUG_PARA_BUSY),
.iDEBUG_PARA_CMD(iDEBUG_PARA_CMD),
.iDEBUG_PARA_DATA(iDEBUG_PARA_DATA),
.oDEBUG_PARA_VALID(oDEBUG_PARA_VALID),
.iDEBUG_PARA_BUSY(iDEBUG_PARA_BUSY),
.oDEBUG_PARA_ERROR(oDEBUG_PARA_ERROR),
.oDEBUG_PARA_DATA(oDEBUG_PARA_DATA)
);
/******************************************************
Clock
******************************************************/
always#(PL_CORE_CYCLE/2)begin
iCORE_CLOCK = !iCORE_CLOCK;
end
always#(PL_BUS_CYCLE/2)begin
iBUS_CLOCK = !iBUS_CLOCK;
end
always#(PL_DPS_CYCLE/2)begin
iDPS_CLOCK = !iDPS_CLOCK;
end
/******************************************************
State
******************************************************/
initial begin
$display("Check Start");
//Initial
iCORE_CLOCK = 1'b0;
iBUS_CLOCK = 1'b0;
iDPS_CLOCK = 1'b0;
inRESET = 1'b0;
iSCI_RXD = 1'b1;
iGCI_BUSY = 1'b0;
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
iGCI_IRQ_REQ = 1'b0;
iGCI_IRQ_NUM = 6'h0;
iDEBUG_UART_RXD = 1'b1;
iDEBUG_PARA_REQ = 1'b0;
iDEBUG_PARA_CMD = 8'h0;
iDEBUG_PARA_DATA = 32'h0;
iDEBUG_PARA_BUSY = 1'b0;
//Reset After
#(PL_RESET_TIME);
inRESET = 1'b1;
//GCI Init
#(PL_BUS_CYCLE*32);
while(oGCI_BUSY) #(PL_BUS_CYCLE);
iGCI_REQ = 1'b1;
iGCI_DATA = PL_GCI_SIZE;
#(PL_BUS_CYCLE);
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
#15000000 begin
$finish;
end
end
/******************************************************
Memory Model
******************************************************/
sim_memory_model #(1, "tb_func_test.hex") MEMORY_MODEL(
.iCLOCK(iCORE_CLOCK),
.inRESET(inRESET),
//Req
.iMEMORY_REQ(oMEMORY_REQ),
.oMEMORY_LOCK(iMEMORY_LOCK),
.iMEMORY_ORDER(oMEMORY_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.iMEMORY_MASK(oMEMORY_MASK),
.iMEMORY_RW(oMEMORY_RW), //1:Write | 0:Read
.iMEMORY_ADDR(oMEMORY_ADDR),
//This -> Data RAM
.iMEMORY_DATA(oMEMORY_DATA),
//Data RAM -> This
.oMEMORY_VALID(iMEMORY_VALID),
.iMEMORY_LOCK(oMEMORY_BUSY),
.oMEMORY_DATA(iMEMORY_DATA)
);
/******************************************************
Display Dump
******************************************************/
always@(posedge iCORE_CLOCK)begin
if(inRESET)begin
//task_disp_inst_issue();
//task_disp_pcr();
//task_disp_tag_info();
task_disp_branch();
task_disp_loadstore();
//task_disp_logic_register_all();
//task_disp_logic_register_single(5'h2);
end
end
/******************************************************
Assertion
******************************************************/
reg assert_check_flag;
reg [31:0] assert_wrong_number;
reg [31:0] assert_wrong_type;
reg [31:0] assert_result;
reg [31:0] assert_expect;
always@(posedge iCORE_CLOCK)begin
if(inRESET && oMEMORY_REQ && !iMEMORY_LOCK && oMEMORY_ORDER == 2'h2 && oMEMORY_RW)begin
//Finish Check
if(oMEMORY_ADDR == 32'h0002_0004)begin
if(!assert_check_flag)begin
$display("[SIM-ERR]Wrong Data.");
$display("[SIM-ERR]Wrong Type : %d", assert_wrong_type);
$display("[SIM-ERR]Index:%d, Expect:%x, Result:%x", assert_wrong_number, assert_expect, assert_result);
$display("[SIM-ERR]Simulation Finished.");
$finish;
end
else begin
$display("[SIM-OK]Simulation Finished.");
$finish;
end
end
//Check Log
else if(oMEMORY_ADDR == 32'h0002_0008)begin
$display("[SIM-LOG]#d", {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]});
end
//Check Flag
else if(oMEMORY_ADDR == 32'h0002_0000)begin
assert_check_flag = oMEMORY_DATA[24];
end
//Error Number
else if(oMEMORY_ADDR == 32'h0002_0010)begin
assert_wrong_number = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Type
else if(oMEMORY_ADDR == 32'h0002_000c)begin
assert_wrong_type = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Result
else if(oMEMORY_ADDR == 32'h0002_0014)begin
assert_result = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Expect
else if(oMEMORY_ADDR == 32'h0002_0018)begin
assert_expect = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
end
end
endmodule
`default_nettype wire
|
/*!
* <b>Module:</b>gtx_8x10enc
* @file gtx_8x10enc.v
* @date 2015-07-11
* @author Alexey
*
* @brief 8x10 encoder implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* gtx_8x10enc.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* gtx_8x10enc.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
module gtx_8x10enc(
input wire rst,
input wire clk,
input wire [1:0] inisk,
input wire [15:0] indata,
output wire [19:0] outdata
);
// addresses to reference an encoding table
wire [8:0] addr0;
wire [8:0] addr1;
assign addr0 = {inisk[0], indata[7:0]};
assign addr1 = {inisk[1], indata[15:8]};
// possible encoded data - both disparities, for both bytes
// due to registered memory output, this values will be valid after 2 clock cycles
// table[i] [9:0] in case of current disparity +, [19:10] in case of -
wire [31:0] table0_out;
wire [31:0] table1_out;
reg [19:0] table0_r;
reg [19:0] table1_r;
wire [19:0] table0;
wire [19:0] table1;
assign table0 = table0_out[19:0];
assign table1 = table1_out[19:0];
always @ (posedge clk)
begin
table0_r <= table0;
table1_r <= table1;
end
// encoded bytes
wire [9:0] enc0;
wire [9:0] enc1;
//reg [9:0] enc0_r;
//reg [9:0] enc1_r;
// running displarity, 0 = -, 1 = +
reg disparity;
// running disparity after encoding 1st byte
wire disparity_interm;
// invert disparity after a byte
// if current encoded word containg an equal amount of 1s and 0s (i.e. 5 x '1'), disp shall stay the same
// if amounts are unequal, there are either 4 or 6 '1's. in either case disp shall be inverted
wire inv_disp0;
wire inv_disp1;
assign inv_disp0 = ~^enc0;
assign inv_disp1 = ~^enc1;
assign disparity_interm = inv_disp0 ? ~disparity : disparity;
always @ (posedge clk)
disparity <= rst ? 1'b0 : inv_disp1 ^ inv_disp0 ? ~disparity : disparity;
// select encoded bytes depending on a previous disparity
assign enc0 = {10{~disparity}} & table0_r[19:10] | {10{disparity}} & table0_r[9:0];
assign enc1 = {10{~disparity_interm}} & table1_r[19:10] | {10{disparity_interm}} & table1_r[9:0];
// latch output data
reg [19:0] outdata_l;
assign outdata = outdata_l;
always @ (posedge clk)
outdata_l <= {enc1, enc0};
ramt_var_w_var_r #(
.REGISTERS_A (1),
.REGISTERS_B (1),
.LOG2WIDTH_A (5),
.LOG2WIDTH_B (5)
`include "gtx_8x10enc_init.v"
)
encoding_table(
.clk_a (clk),
.addr_a ({1'b0, addr0}),
.en_a (1'b1),
.regen_a (1'b1),
.we_a (1'b0),
.data_out_a (table0_out),
.data_in_a (32'h0),
.clk_b (clk),
.addr_b ({1'b0, addr1}),
.en_b (1'b1),
.regen_b (1'b1),
.we_b (1'b0),
.data_out_b (table1_out),
.data_in_b (32'h0)
);
`ifdef CHECKERS_ENABLED
reg [8:0] addr0_r;
reg [8:0] addr1_r;
reg [8:0] addr0_rr;
reg [8:0] addr1_rr;
always @ (posedge clk)
begin
addr0_r <= addr0;
addr1_r <= addr1;
addr0_rr <= addr0_r;
addr1_rr <= addr1_r;
end
always @ (posedge clk)
if (~rst)
if (|table0 | |table1) begin
// all good
end
else begin
// got xxxx or 0000, both cases tell us addresses were bad
$display("Error in %m: bad incoming data: 1) K = %h, Data = %h 2) K = %h, Data = %h", addr0_rr[8], addr0_rr[7:0], addr1_rr[8], addr1_rr[7:0]);
repeat (10) @(posedge clk);
$finish;
end
`endif // CHECKERS_ENABLED
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
// Date : Tue Sep 16 21:34:47 2014
// Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
// Design : clk_wiz_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_wiz_0(clk_in1, clk_out1, reset, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,reset,locked" */;
input clk_in1;
output clk_out1;
input reset;
output locked;
endmodule
|
`define CLOG2(x) \
(x <= 2) ? 1 : \
(x <= 4) ? 2 : \
(x <= 8) ? 3 : \
(x <= 16) ? 4 : \
(x <= 32) ? 5 : \
(x <= 64) ? 6 : \
(x <= 128) ? 7 : \
(x <= 256) ? 8 : \
-1
module sync_fifo #(
parameter DEPTH = 3,
parameter DATA_W = 32,
parameter ASSERT_OVERFLOW = 1,
parameter ASSERT_UNDERFLOW = 1,
parameter ENABLE_BYPASS = 0
)
(
input clk,
input rstn,
input [DATA_W-1:0] fifo_data_in,
input fifo_push,
output [DATA_W-1:0] fifo_data_out,
input fifo_pop,
output fifo_full,
output fifo_empty,
input fifo_flush
);
localparam DEPTH_LOG2 = `CLOG2(DEPTH);
reg [DATA_W-1:0] mem [0:DEPTH-1];
reg [DEPTH_LOG2-1:0] head, n_head;
reg [DEPTH_LOG2-1:0] tail, n_tail;
wire empty;
wire full;
reg push_last;
assign fifo_data_out = mem[tail];
assign fifo_full = full;
assign fifo_empty = empty;
always @ (*) begin
if (head < DEPTH-1) begin
n_head = head + 'h1;
end
else begin
n_head = 'h0;
end
end
always @ (*) begin
if (tail < DEPTH-1) begin
n_tail = tail + 'h1;
end
else begin
n_tail = 'h0;
end
end
generate
if (ENABLE_BYPASS) begin
assign full = (push_last && (head == tail) && !fifo_pop) ? 1'b1 : 1'b0;
assign empty = (!push_last && (head == tail) && !fifo_push) ? 1'b1 : 1'b0;
end
else begin
assign full = (push_last && (head == tail)) ? 1'b1 : 1'b0;
assign empty = (!push_last && (head == tail)) ? 1'b1 : 1'b0;
end
endgenerate
generate
if (ASSERT_OVERFLOW) begin
always @ (posedge clk) begin
if (clk && !fifo_flush && fifo_push && full) begin
$display("ERROR: FIFO OVERFLOW");
$finish;
end
end
end
if (ASSERT_UNDERFLOW) begin
always @ (posedge clk) begin
if (clk && !fifo_flush && fifo_pop && empty) begin
$display("ERROR: FIFO UNDERFLOW");
$finish;
end
end
end
endgenerate
always @ (posedge clk, negedge rstn) begin
if (~rstn) begin
head <= 'h0;
tail <= 'h0;
push_last <= 'h0;
end
else begin
if (fifo_flush) begin
tail <= 'h0;
head <= 'h0;
push_last <= 'h0;
end
else if (!((full && fifo_push) || (empty && fifo_pop))) begin
if (fifo_push) begin
mem[head] <= fifo_data_in;
head <= n_head;
end
if (fifo_pop) begin
tail <= n_tail;
end
if (fifo_push && !fifo_pop) begin
push_last = 'h1;
end
else if (!fifo_push && fifo_pop) begin
push_last = 'h0;
end
end
end
end
endmodule
|
// megafunction wizard: %ALTSYNCRAM%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: altera_dpram_16x32.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 216 03/06/2006 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_dpram_16x32 (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [3:0] rdaddress;
input [3:0] wraddress;
input wren;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.clocken1 (1'b1),
.clocken0 (1'b1),
.q_a (),
.data_b ({32{1'b1}}),
.rden_b (1'b1),
.wren_b (1'b0),
.byteena_b (1'b1),
.addressstall_a (1'b0),
.byteena_a (1'b1),
.addressstall_b (1'b0),
.clock1 (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16,
altsyncram_component.numwords_b = 16,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 4,
altsyncram_component.widthad_b = 4,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL rdaddress[3..0]
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL wraddress[3..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram_16x32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram_16x32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram_16x32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram_16x32.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram_16x32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_dpram_16x32_bb.v TRUE
|
`timescale 1ns / 1ps
module clocks(
input rst,
input clk50,
input divide_more,
input clk_dac_sel,
output clk_cpu,
output locked,
output clk_dac,
output reg rst_clk4,
output E,
output Q
);
wire clk_base; // 4*3.58MHz
reg [1:0] clk4_cnt;
reg Qr, Er;
reg clk_dac_sel2, clk_dac_aux;
always @(negedge clk_base)
clk_dac_sel2 <= clk_dac_sel;
reg dac_cnt;
always @(posedge clk_base or posedge rst)
if( rst )
dac_cnt <= 1'b0;
else begin
if( clk_dac_sel2 )
clk_dac_aux <= ~clk_dac_aux;
else
{ clk_dac_aux, dac_cnt } <= { clk_dac_aux, dac_cnt } + 1'b1;
end
// BUFG dacbuf( .I(clk_dac_aux), .O(clk_dac) );
// assign clk_dac = clk_base;
// assign clk_dac = clk4_cnt[0];
assign clk_dac = Er;
always @(posedge clk_base or posedge rst)
if (rst) begin
clk4_cnt <= 0;
{ Er, Qr } <= 2'b0;
end
else begin
clk4_cnt <= clk4_cnt+2'b01;
case( clk4_cnt )
2'b00: Qr <= 1; // RISING EDGE OF E
2'b01: Er <= 1; // RISING EDGE OF Q
2'b10: Qr <= 0; // FALLING EDGE OF E
2'b11: Er <= 0; // FALLING EDGE OF Q
endcase
end
BUFG ebuf( .I(Er), .O(E) );
BUFG qbuf( .I(Qr), .O(Q) );
reg rst_clk4_aux;
always @(negedge Q)
{ rst_clk4, rst_clk4_aux } <= { rst_clk4_aux, rst };
reg [1:0] clk_cpu_cnt;
always @( posedge clk_base or posedge rst)
if( rst )
clk_cpu_cnt <= 2'b0;
else
clk_cpu_cnt <= clk_cpu_cnt + 1'b1;
reg clk_sel;
always @( negedge clk_base )
clk_sel <= divide_more;
BUFG CLKDV_BUFG_INST(
.I( clk_sel ? clk_cpu_cnt[0] : clk_base ),
.O(clk_cpu)
);
// clk_base = clk50*2/7 = 14.28MHz
clk50div u_clk50div (
.CLKIN_IN(clk50),
.RST_IN(rst),
.CLKFX_OUT(clk_base),
//.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),
//.CLK0_OUT(CLK0_OUT),
.LOCKED_OUT(locked)
);
endmodule
|
/*
-- ============================================================================
-- FILE NAME : alu.v
-- DESCRIPTION : Zp_Zjbg
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** ÂÊwb_t@C **********/
`include "cpu.h"
/********** W
[ **********/
module alu (
input wire [`WordDataBus] in_0, // üÍ 0
input wire [`WordDataBus] in_1, // üÍ 1
input wire [`AluOpBus] op, // Iy[V
output reg [`WordDataBus] out, // oÍ
output reg of // I[ot[
);
/********** t«üoÍM **********/
wire signed [`WordDataBus] s_in_0 = $signed(in_0); // t«üÍ 0
wire signed [`WordDataBus] s_in_1 = $signed(in_1); // t«üÍ 1
wire signed [`WordDataBus] s_out = $signed(out); // t«oÍ
/********** Zp_Z **********/
always @(*) begin
case (op)
`ALU_OP_AND : begin // _ÏiANDj
out = in_0 & in_1;
end
`ALU_OP_OR : begin // _aiORj
out = in_0 | in_1;
end
`ALU_OP_XOR : begin // r¼I_aiXORj
out = in_0 ^ in_1;
end
`ALU_OP_ADDS : begin // t«ÁZ
out = in_0 + in_1;
end
`ALU_OP_ADDU : begin // ȵÁZ
out = in_0 + in_1;
end
`ALU_OP_SUBS : begin // t«¸Z
out = in_0 - in_1;
end
`ALU_OP_SUBU : begin // ȵ¸Z
out = in_0 - in_1;
end
`ALU_OP_SHRL : begin // _EVtg
out = in_0 >> in_1[`ShAmountLoc];
end
`ALU_OP_SHLL : begin // _¶Vtg
out = in_0 << in_1[`ShAmountLoc];
end
default : begin // ftHgl (No Operation)
out = in_0;
end
endcase
end
/********** I[ot[`FbN **********/
always @(*) begin
case (op)
`ALU_OP_ADDS : begin // ÁZI[ot[Ì`FbN
if (((s_in_0 > 0) && (s_in_1 > 0) && (s_out < 0)) ||
((s_in_0 < 0) && (s_in_1 < 0) && (s_out > 0))) begin
of = `ENABLE;
end else begin
of = `DISABLE;
end
end
`ALU_OP_SUBS : begin // ¸ZI[ot[Ì`FbN
if (((s_in_0 < 0) && (s_in_1 > 0) && (s_out > 0)) ||
((s_in_0 > 0) && (s_in_1 < 0) && (s_out < 0))) begin
of = `ENABLE;
end else begin
of = `DISABLE;
end
end
default : begin // ftHgl
of = `DISABLE;
end
endcase
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module tri_intersect_data_array_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk);
parameter DWIDTH = 576;
parameter AWIDTH = 5;
parameter MEM_SIZE = 20;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
input[DWIDTH-1:0] d1;
input we1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
if (we1)
begin
ram[addr1] <= d1;
q1 <= d1;
end
else
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module tri_intersect_data_array(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1);
parameter DataWidth = 32'd576;
parameter AddressRange = 32'd20;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
input we1;
input[DataWidth - 1:0] d1;
output[DataWidth - 1:0] q1;
tri_intersect_data_array_ram tri_intersect_data_array_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.d1( d1 ),
.we1( we1 ),
.q1( q1 ));
endmodule
|
`timescale 1ps / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14.09.2017 09:33:27
// Design Name:
// Module Name: srio_example_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Try to implement SRIO data transfer between FPGA and DSP
// FPGA must be slave
//////////////////////////////////////////////////////////////////////////////////
(* DowngradeIPIdentifiedWarnings = "yes" *)
module srio_example_test(
// Clocks and Resets
input sys_clkp, // MMCM reference clock
input sys_clkn, // MMCM reference clock
// high-speed IO
// Serial Receive Data
input srio_rxn0,
input srio_rxp0,
input srio_rxn1,
input srio_rxp1,
/*input srio_rxn2,
input srio_rxp2,
input srio_rxn3,
input srio_rxp3,*/
// Serial Transmit Data
output srio_txn0,
output srio_txp0,
output srio_txn1,
output srio_txp1
/*output srio_txn2,
output srio_txp2,
output srio_txn3,
output srio_txp3*/
);
// wire declarations
wire log_clk;
wire phy_clk;
wire gt_clk;
wire gt_pcs_clk;
wire drpclk;
wire refclk;
wire log_rst;
wire phy_rst;
wire cfg_rst;
wire buf_rst;
wire sys_rst = 1'b0; // Global reset signal
wire clk_lock; // asserts from the MMCM
// signals into the DUT
// From FPGA to DSP
wire iotx_tvalid; // Indicates that the information on the channel is valid
wire iotx_tready; // Indicates that the data from the source is accepted (if valid)
wire iotx_tlast; // Indicates the last beat of a packet
wire [63:0] iotx_tdata; // Packet header and data
wire [7:0] iotx_tkeep; // Indicates whether the content of the associated byte of data is valid
wire [31:0] iotx_tuser; // Consists of the Source ID and Destination ID
// From DSP to FPGA
wire iorx_tvalid; // Indicates that the information on the channel is valid
wire iorx_tready; // Indicates that the data from the source is accepted (if valid)
wire iorx_tlast; // Indicates the last beat of a packet
wire [63:0] iorx_tdata; // Packet header and data
wire [7:0] iorx_tkeep; // Indicates whether the content of the associated byte of data is valid
wire [31:0] iorx_tuser; // Consists of the Source ID and Destination ID
wire maintr_rst = 1'b0;
wire maintr_awvalid = 1'b0;
wire maintr_awready;
wire [31:0] maintr_awaddr = 32'b0;
wire maintr_wvalid = 1'b0;
wire maintr_wready;
wire [31:0] maintr_wdata = 32'b0;
wire maintr_bvalid;
wire maintr_bready = 1'b0;
wire [1:0] maintr_bresp;
wire maintr_arvalid = 1'b0;
wire maintr_arready;
wire [31:0] maintr_araddr = 32'b0;
wire maintr_rvalid;
wire maintr_rready = 1'b0;
wire [31:0] maintr_rdata;
wire [1:0] maintr_rresp;
//debug
wire [63:0] dbg_s_axis_tdata;
// PHY control signals
wire phy_mce = 1'b0; // Send MCE control symbol == broadcast
wire phy_link_reset = 1'b0; // Send link reset control symbols
wire force_reinit = 1'b0; // Force reinitialization
wire sim_train_en = 1'b0; // Set this only when simulating to reduce the size of counters
wire gt0_qpll_clk_out; // QPLL outputs
wire gt0_qpll_out_refclk_out;
wire gt_pcs_rst;
// debug wires
wire phy_rcvd_mce; // MCE control symbol received
wire phy_rcvd_link_reset; // Received 4 consecutive reset symbols
wire [223:0] phy_debug; // Usefull debug signals
wire gtrx_disperr_or; // GT disparity error (reduce ORed)
wire gtrx_notintable_or; // GT not in table error
wire port_error; // In Port Error State
wire [23:0] port_timeout; // Timeout value from Port Response Timeout CSR
wire srio_host; // Endpoint is the system host
wire port_decode_error; // Received transaction did not match a valid port
wire [15:0] deviceid; // Device ID
wire idle2_selected; // The PHY is operating in IDLE2 mode
wire port_init; // Port is Initialized
wire link_init; // Link is Initialized
wire mode_1x; // Link is trained down to 1x mode
wire idle_selected; // The IDLE sequence has been selected
vio_0 vio_ip(
.clk ( log_clk ),
.probe_in0 ( mode_1x ),
.probe_in1 ( port_init ),
.probe_in2 ( link_init ),
.probe_in3 ( port_error )
);
/*
ila_1 ila_ip(
.clk (log_clk),
.probe0 (iotx_tdata),
.probe1 (iorx_tdata),
.probe2 (iotx_tuser),
.probe3 (iorx_tuser),
.probe4 (iotx_tready),
.probe5 (iorx_tready),
.probe6 (iotx_tvalid),
.probe7 (iorx_tvalid)
);
*/
/*
TODO: This module must to accept SRIO packet from DSP side,
save data (which was in packet) in DDR (on current time in FIFO),
and send response packet with data (if was get NREAD request);
In this part we accept packet by SRIO IP (srio_ip),
transfer data into srio_response, save their in FIFO and
transfer it back
*/
srio_response srio_rx(
.log_clk ( log_clk ),
.log_rst ( log_rst ),
.src_id ( deviceid ),
.id_override ( 1'b0 ),
// Regs with request data (from DSP to FPGA)
.axis_iorx_tvalid ( iorx_tvalid ),
.axis_iorx_tready ( iorx_tready ),
.axis_iorx_tlast ( iorx_tlast ),
.axis_iorx_tdata ( iorx_tdata ),
.axis_iorx_tkeep ( iorx_tkeep ),
.axis_iorx_tuser ( iorx_tuser ),
// Regs with response data (from FPGA to DSP)
.axis_iotx_tvalid ( iotx_tvalid ),
.axis_iotx_tlast ( iotx_tlast ),
.axis_iotx_tdata ( iotx_tdata ),
.axis_iotx_tkeep ( iotx_tkeep ),
.axis_iotx_tuser ( iotx_tuser ),
.axis_iotx_tready ( iotx_tready )
);
srio_gen2_0 srio_ip(
.sys_clkp ( sys_clkp ),
.sys_clkn ( sys_clkn ),
.sys_rst ( sys_rst ),
// all clocks as output in shared logic mode
.log_clk_out ( log_clk ),
.phy_clk_out ( phy_clk ),
.gt_clk_out ( gt_clk ),
.gt_pcs_clk_out ( gt_pcs_clk ),
.drpclk_out ( drpclk ),
.refclk_out ( refclk ),
.clk_lock_out ( clk_lock ),
// all resets as output in shared logic mode
.log_rst_out ( log_rst ),
.phy_rst_out ( phy_rst ),
.buf_rst_out ( buf_rst ),
.cfg_rst_out ( cfg_rst ),
.gt_pcs_rst_out ( gt_pcs_rst ),
.gt0_qpll_clk_out ( gt0_qpll_clk_out ),
.gt0_qpll_out_refclk_out ( gt0_qpll_out_refclk_out ),
// Serial IO Interface
.srio_rxn0 ( srio_rxn0 ),
.srio_rxp0 ( srio_rxp0 ),
.srio_rxn1 ( srio_rxn1 ),
.srio_rxp1 ( srio_rxp1 ),
/*.srio_rxn2 ( srio_rxn2 ),
.srio_rxp2 ( srio_rxp2 ),
.srio_rxn3 ( srio_rxn3 ),
.srio_rxp3 ( srio_rxp3 ),*/
.srio_txn0 ( srio_txn0 ),
.srio_txp0 ( srio_txp0 ),
.srio_txn1 ( srio_txn1 ),
.srio_txp1 ( srio_txp1 ),
/*.srio_txn2 ( srio_txn2 ),
.srio_txp2 ( srio_txp2 ),
.srio_txn3 ( srio_txn3 ),
.srio_txp3 ( srio_txp3 ),*/
// LOG User I/O Interface
.s_axis_iotx_tvalid ( iotx_tvalid ),
.s_axis_iotx_tready ( iotx_tready ), // output
.s_axis_iotx_tlast ( iotx_tlast ),
.s_axis_iotx_tdata ( iotx_tdata ),
.s_axis_iotx_tkeep ( iotx_tkeep ),
.s_axis_iotx_tuser ( iotx_tuser ),
.m_axis_iorx_tvalid ( iorx_tvalid ),
.m_axis_iorx_tready ( iorx_tready ), // input
.m_axis_iorx_tlast ( iorx_tlast ),
.m_axis_iorx_tdata ( iorx_tdata ),
.m_axis_iorx_tkeep ( iorx_tkeep ),
.m_axis_iorx_tuser ( iorx_tuser ),
// Maintenance Port Interface
.s_axi_maintr_rst ( maintr_rst ),
.s_axi_maintr_awvalid ( maintr_awvalid ),
.s_axi_maintr_awready ( maintr_awready ),
.s_axi_maintr_awaddr ( maintr_awaddr ),
.s_axi_maintr_wvalid ( maintr_wvalid ),
.s_axi_maintr_wready ( maintr_wready ),
.s_axi_maintr_wdata ( maintr_wdata ),
.s_axi_maintr_bvalid ( maintr_bvalid ),
.s_axi_maintr_bready ( maintr_bready ),
.s_axi_maintr_bresp ( maintr_bresp ),
.s_axi_maintr_arvalid ( maintr_arvalid ),
.s_axi_maintr_arready ( maintr_arready ),
.s_axi_maintr_araddr ( maintr_araddr ),
.s_axi_maintr_rvalid ( maintr_rvalid ),
.s_axi_maintr_rready ( maintr_rready ),
.s_axi_maintr_rdata ( maintr_rdata ),
.s_axi_maintr_rresp ( maintr_rresp ),
// PHY control signa
.sim_train_en ( sim_train_en ),
.phy_mce ( phy_mce ),
.phy_link_reset ( phy_link_reset ),
.force_reinit ( force_reinit ),
// Core debug signals
.phy_rcvd_mce ( phy_rcvd_mce ),
.phy_rcvd_link_reset ( phy_rcvd_link_reset ),
.phy_debug ( phy_debug ),
.gtrx_disperr_or ( gtrx_disperr_or ),
.gtrx_notintable_or ( gtrx_notintable_or ),
// Side band signals
.port_error ( port_error ),
.port_timeout ( port_timeout ),
.srio_host ( srio_host ),
// LOG Informational signals
.port_decode_error ( port_decode_error ),
.deviceid ( deviceid ),
.idle2_selected ( idle2_selected ),
.phy_lcl_master_enable_out (), // these are side band output only signals
.buf_lcl_response_only_out (),
.buf_lcl_tx_flow_control_out (),
.buf_lcl_phy_buf_stat_out (),
.phy_lcl_phy_next_fm_out (),
.phy_lcl_phy_last_ack_out (),
.phy_lcl_phy_rewind_out (),
.phy_lcl_phy_rcvd_buf_stat_out (),
.phy_lcl_maint_only_out (),
// PHY Informational signals
.port_initialized ( port_init ),
.link_initialized ( link_init ),
.idle_selected ( idle_selected ),
.mode_1x ( mode_1x )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRTN_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DFRTN_PP_SYMBOL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRTN_PP_SYMBOL_V
|
/**
* clk_gen.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:29:34 04/26/2015
// Design Name:
// Module Name: clk_gen
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_gen(
input wire button,
input wire clk,
input wire res,
output wire clk_div
);
reg [3 : 0] ripple;
assign clk_div = &ripple;
always @(posedge clk) begin
if(res)
ripple <= 4'b0;
else begin
ripple[0] <= button;
ripple[1] <= ripple[0];
ripple[2] <= ripple[1];
ripple[3] <= ripple[2];
end
end
endmodule
/* vim: set ts=4 tw=79 syntax=verilog */
|
//Copyright 2014 Zeno Futurista ([email protected])
//
//Licensed under the Apache License, Version 2.0 (the "License");
//you may not use this file except in compliance with the License.
//You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
//Unless required by applicable law or agreed to in writing, software
//distributed under the License is distributed on an "AS IS" BASIS,
//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//See the License for the specific language governing permissions and
//limitations under the License.
//I hope you will like it :)
//Well, I like alteras quartus and its compiler, good piece of work!
module sha256(input clk, input [7:0] in[0:79], input [31:0] job, input doWork, output reg[7:0] resultOut[0:31], output reg[31:0] resultJobOut, output reg[31:0] resultNonceOut, output reg resultAvailable);
//unroll parameter
parameter unroll = 4;
//sha initial digest constant
wire [31:0] H [0:7];
//initial digest (sha state)
assign H = '{32'h6a09e667, 32'hbb67ae85, 32'h3c6ef372, 32'ha54ff53a, 32'h510e527f, 32'h9b05688c, 32'h1f83d9ab, 32'h5be0cd19};
//actual work registers
reg[7:0] workBuffer[0:79];
reg[31:0] currentJob;
reg midstateReady;
reg[31:0] midstate[0:7];
//signals that there is task to be scheduled
reg scheduleTask;
//interconnection wires and regs for first pipeline follow
//task state wire and reg
reg[31:0] stateOut;
wire[31:0] stateIn;
//digest wires and registers
reg[31:0] digestOut[0:7];
reg[31:0] digestOutOriginal[0:7];
wire [31:0] digestIn [0:7];
wire [31:0] digestInOriginal [0:7];
//wires for first phase midstate computation
//second part with 12 header bytes + nonce and padding
wire[7:0] firstStageSecondPart[0:63];
wire[7:0] dataIn[0:63];
//used for words
reg[31:0] wordsOut[0:15];
wire[31:0] wordsIn[0:15];
//nonce vars
reg[31:0] nonceOut;
wire[31:0] nonceIn;
//job vars
reg[31:0] jobOut;
wire[31:0] jobIn;
//pipeline for first part of computation
sha_pipeline #(unroll) shap(clk, stateOut, digestOut, digestOutOriginal, wordsOut, jobOut, nonceOut, digestIn, digestInOriginal, wordsIn, stateIn, jobIn, nonceIn);
//wires and regs for internal connection with second pipeline
reg[31:0] stateOutb;
wire[31:0] stateInb;
reg[31:0] nonceOutb;
wire[31:0] nonceInb;
reg[31:0] digestOutb[0:7];
wire [31:0] digestInb [0:7];
reg[31:0] digestOutOriginalb[0:7];
wire [31:0] digestInOriginalb [0:7];
reg[31:0] wordsOutb[0:15];
wire[31:0] wordsInb[0:15];
reg[31:0] jobOutb;
wire[31:0] jobInb;
//pipeline for second part of computation
sha_pipeline #(unroll) shapb(clk, stateOutb, digestOutb, digestOutOriginalb, wordsOutb, jobOutb, nonceOutb, digestInb, digestInOriginalb, wordsInb, stateInb, jobInb, nonceInb);
//put second part of input data to queue, used only at several initial cycles after job submition (midstate is not known)
shaqueue #(.elementWidth(8), .elementCount(64), .depth(1 + unroll)) fsspq(clk, (firstPipelineReady & scheduleTask & ~midstateReady), midstateStageReady, firstStageSecondPart, dataIn);
//inputs for each stage
wire[7:0] stageTwoPadding[0:31];
//combinationals needed to assemble new data to hash (paddings, nonces...)
reg[31:0] newNonce;
wire [31:0] newDigest[0:7];
always @(*) begin
for(int i =0; i < 8; i++) begin
newDigest[i] = (digestIn[i] + digestInOriginal[i]);
end
//this is maybe not the best way to set this up, but i find it readable and easy to understand
firstStageSecondPart[0:11] = workBuffer[64:75];
//assembly nonce for new sha hashing
firstStageSecondPart[15] = newNonce;
firstStageSecondPart[14] = (newNonce >> 8);
firstStageSecondPart[13] = (newNonce >> 16);
firstStageSecondPart[12] = (newNonce >> 24);
//padding to 128 bytes of 80B input (first stage second sha part)
firstStageSecondPart[16] = 128;
for(int i =1; i < 46; i++) begin
firstStageSecondPart[16+i] = 0;
end
firstStageSecondPart[62] = 2;
firstStageSecondPart[63] = 128;
//padding for second stage input
stageTwoPadding[0] = 128;
for(int i =1; i < 30; i++) begin
stageTwoPadding[i] = 0;
end
stageTwoPadding[30] = 1;
stageTwoPadding[31] = 0;
end
//some states to be easilly readable
wire firstPipelineWorkIn = stateIn[31];
wire firstStageReady = (stateIn[7:0] == 128);
wire firstPipelineReady = ~firstPipelineWorkIn | firstStageReady;
wire firstPipelineResultReady = firstPipelineWorkIn & firstStageReady;
wire secondPipelineWorkIn = stateInb[31];
wire secondPipelineResultReady = secondPipelineWorkIn & (stateInb[7:0] == 64);
wire secondPipelineReady = (~secondPipelineWorkIn | secondPipelineResultReady);
wire midstateStageReady = (stateIn[7:0] == 64);
always@(posedge clk) begin
if(doWork) begin
//set new data
workBuffer <= in;
//set new job
currentJob <= job;
//reset nonce
//concatenation of input bytes in header
newNonce <= {in[76],in[77],in[78],in[79]};
//TODO reset queue... seems like it is not needed - jobstate guarantees drops (must test)
midstateReady <= 0;
scheduleTask <= 1;
end
if(firstPipelineReady) begin
if(scheduleTask) begin
//now we can schedule task, there is something to do! :) as always in life!
if(~midstateReady) begin
//begining of new work - there is no midstate known
//midstate is the same result of first 64 bytes part sha transform (because of nonce, which changes, lies at bytes 76-79 [zero index])
//--> concatenation
for(int i =0; i<16; i++) begin
wordsOut[i] <= (workBuffer[4*i] <<< 24) | (workBuffer[4*i + 1] <<< 16) | (workBuffer[4*i + 2] <<< 8) | (workBuffer[4*i + 3]);
end
//set state variables
stateOut[31] <= 1;
stateOut[7:0] <= 0;
//set up other job infos
jobOut <= currentJob;
nonceOut <= newNonce;
//increment nonce
newNonce <= newNonce + 1;
//we hit end of nonce interval - stop scheduling
if(newNonce == (32'hffffffff)) begin
scheduleTask <= 0;
end
//set initial digest
digestOut <= H;
digestOutOriginal <= H;
end else begin
//new work scheduling is in stage, where midstate is known (first sha done)
stateOut[31] <= 1;
//set digest from midstate
digestOut <= midstate;
digestOutOriginal <= midstate;
//set job info
jobOut <= currentJob;
nonceOut <= newNonce;
//use data out assembly, that generates new second part of first sha (few bytes from header with changing nonce + padding)
//this is in fact some kind of concatenation
for(int i =0; i<16; i++) begin
wordsOut[i] <= (firstStageSecondPart[4*i] <<< 24) | (firstStageSecondPart[4*i + 1] <<< 16) | (firstStageSecondPart[4*i + 2] <<< 8) | (firstStageSecondPart[4*i + 3]);
end
//increment nonce
newNonce <= newNonce + 1;
//if we hit end of nonce interval - stop scheduling
if(newNonce == (32'hffffffff)) begin
scheduleTask <= 0;
end
//we continue from state 64 (midstate known)
stateOut[7:0] <= 64;
end
end else begin
//otherwise fill pipeline with zeros
stateOut <= 0;
jobOut <= 0;
nonceOut <= 0;
for(int i = 0; i < 16; i++) begin
wordsOut[i] <= 0;
end
for(int i = 0; i < 8; i++) begin
digestOut[i] <= 0;
digestOutOriginal[i] <= 0;
end
end
end
if(firstPipelineWorkIn) begin
//this state is possible only at the beginning, when there is no midstate...
if(midstateStageReady) begin
//second part of data mix stored in queue
//concatenate/assemble words variable
for(int i =0; i<16; i++) begin
wordsOut[i] <= (dataIn[4*i] <<< 24) | (dataIn[4*i + 1] <<< 16) | (dataIn[4*i + 2] <<< 8) | (dataIn[4*i + 3]);
end
//complete digest - add original state/digest (H) to new one and set midstate.
digestOut <= newDigest;
midstate <= newDigest;
digestOutOriginal <= newDigest;
//continue with second part (from midstate), set job etc.
stateOut <= stateIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
//mark midstate ready for this job
midstateReady <= 1;
end else if(firstStageReady) begin
//first sha is complete, use its final digest and info as input for second sha pipeline
digestOutb <= H;
digestOutOriginalb <= H;
jobOutb <= jobIn;
nonceOutb <= nonceIn;
//set up initial words.
//concatenate some stages
for(int i =0; i < 8; i++) begin
wordsOutb[i] <= newDigest[i];
wordsOutb[8+i] <= (stageTwoPadding[4*i] <<< 24) | (stageTwoPadding[4*i + 1] <<< 16) | (stageTwoPadding[4*i + 2] <<< 8) | (stageTwoPadding[4*i + 3]);
end
//set state variables
stateOutb[7:0] <= 0;
stateOutb[31] <= 1;
end else begin
//some middle phase, continue mixing
wordsOut <= wordsIn;
digestOut <= digestIn;
digestOutOriginal <= digestInOriginal;
stateOut <= stateIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
end
end
//controls when to clean/discard data in second pipeline
//second pipe is ready and first one has nothing to schedule...
if(secondPipelineReady & ~firstPipelineResultReady) begin
stateOutb <= 0;
nonceOutb <= 0;
for(int i = 0; i < 16; i++) begin
wordsOutb[i] <= 0;
end
for(int i = 0; i < 8; i++) begin
digestOutb[i] <= 0;
digestOutOriginalb[i] <= 0;
end
jobOutb <= 0;
end
//if there is some result from second pipeline, process it
if(secondPipelineResultReady) begin
//end part of computation - we can signal completed work
//deconcatenate digest to bytes
for(int i =0; i < 8; i++) begin
resultOut[i*4 + 3] <= (digestInb[i] + digestInOriginalb[i]);
resultOut[i*4 + 2] <= (digestInb[i] + digestInOriginalb[i]) >>> 8;
resultOut[i*4 + 1] <= (digestInb[i] + digestInOriginalb[i]) >>> 16;
resultOut[i*4] <= (digestInb[i] + digestInOriginalb[i]) >>> 24;
end
resultJobOut <= jobInb;
resultNonceOut <= nonceInb;
resultAvailable <= 1;
end else if(secondPipelineWorkIn) begin
//otherwise continue in computation
wordsOutb <= wordsInb;
nonceOutb <= nonceInb;
jobOutb <= jobInb;
digestOutb <= digestInb;
digestOutOriginalb <= digestInOriginalb;
stateOutb <= stateInb;
resultAvailable <= 0;
end else begin
//realy, there is no result yet :)
resultAvailable <= 0;
end
end
endmodule
extern module parameterized_shift_unpacked #(parameter elementWidth = 8, parameter depth = 8, parameter elementCount = 64) (input clk, input [(elementWidth-1):0] in[0:(elementCount-1)], output [(elementWidth-1):0] out[0:(elementCount-1)]);
//I believe it is readable and easy to understand
module sha_pipeline(input clk, input [31:0] stateIn, input[31:0] digestIn[0:7], input[31:0] digestInOriginal[0:7], input [31:0] wordsIn[0:15], input [31:0] jobIn, input [31:0] nonceIn, output [31:0] digestOutNew[0:7], output [31:0] digestOutOriginal[0:7], output [31:0] wordsOut[0:15], output [31:0] stateOut, output [31:0] jobOut, output [31:0] nonceOut);
//valid values are 64,32,16,8,4,2,1
parameter N = 64;
//unroll assertion (taken from serial interface example)
generate
if(~(N==64 | N==32 | N==16 | N ==8 | N ==4 | N ==2 | N==1)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("SHA unroll parameter is not valid!");
endgenerate
//some interconnects
wire [31:0] stateMid;
wire [15:0] stateMidm;
//we need to shift some values in parallel with actual computation (usually needed in next steps)
parameterized_shift_packed #(.elementWidth(32), .depth(N)) db(clk, stateIn, stateMid);
parameterized_shift_packed #(.elementWidth(32), .depth(N)) db1(clk, jobIn, jobOut);
parameterized_shift_packed #(.elementWidth(32), .depth(N)) db2(clk, nonceIn, nonceOut);
parameterized_shift_unpacked #(.elementWidth(32), .elementCount(8),.depth(N)) db3(clk, digestInOriginal, digestOutOriginal);
//sha unrolled according to the N parameter
sha_mix #(N) mix(clk, stateIn[15:0], wordsIn, digestIn, digestOutNew, wordsOut, stateMidm);
//apply new index to state if needed (ie. there was valid task in pipeline)
assign stateOut = {stateMid[31:6], stateMid[31] ? stateMidm : 16'h0};
endmodule
//work work work, mix mix mix
module sha_mix(input clk,input[15:0] indexIn, input [31:0] wordsIn[0:15], input [31:0] digestIn[0:7], output [31:0] digestOut[0:7],output [31:0] wordsOut[0:15], output[15:0] indexOut);
wire [31:0] K[0:63];
//unroll parameter
parameter N = 4;
//sha constant
assign K = '{
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2};
//generate block which governs how much sha mixer is unrolled
genvar i;
generate
if(N == 1) begin
//really small design, one passtrough core
sha_mix_part C(.clk(clk), .index(indexIn), .words(wordsIn), .digest(digestIn), .K(K[indexIn%64]), .wordsOut(wordsOut), .digestOut(digestOut), .indexOut(indexOut));
end else begin
for(i =0; i < N; i++) begin : cores
wire [31:0] local_words[0:15];
wire [31:0] local_digest[0:7];
wire [15:0] local_index;
//individual cores, cores[index] represents local wires generated for each core (in this case we connect everytime to previous one)
if(i == 0) begin
//first core connects mix input with actual one input and mix output with next core output
sha_mix_part core(.clk(clk), .index(indexIn), .words(wordsIn), .digest(digestIn), .K(K[indexIn%64]), .wordsOut(local_words), .digestOut(local_digest), .indexOut(local_index));
end else if(i < (N-1)) begin
//middle core(s) connect previous core output with actual one input and actual output with next core input
sha_mix_part core(.clk(clk), .index(cores[i-1].local_index), .words(cores[i-1].local_words), .digest(cores[i-1].local_digest), .K(K[cores[i-1].local_index%64]), .wordsOut(local_words), .digestOut(local_digest), .indexOut(local_index));
end else begin
//last core connects previous core output with actual one input and mix output with actual output
sha_mix_part core(clk, cores[i-1].local_index, cores[i-1].local_words, cores[i-1].local_digest, K[cores[i-1].local_index%64], wordsOut, digestOut, indexOut);
end
end
end
endgenerate
endmodule
//this module is based on this java SHA implementation: https://code.google.com/p/a9cipher/source/browse/src/cosc385final/SHA2.java?r=df621cf75f3448903e9393194a1d6aa086b0a92b
//it works and I am happy! :)
module sha_mix_part(input clk, input[15:0] index, input [31:0] words[0:15], input [31:0] digest[0:7], input [31:0] K, output reg[31:0] wordsOut[0:15], output reg[31:0] digestOut[0:7], output reg[15:0] indexOut);
//TODO resolve long combinational path for ch and newWork - too much chained adders
//digest/state computation for next round part
wire [31:0] s0;
wire [31:0] s00;
wire [31:0] s01;
wire [31:0] s02;
wire [31:0] s1;
wire [31:0] s10;
wire [31:0] s11;
wire [31:0] s12;
wire [31:0] maj;
wire [31:0] ch;
wire [31:0] t2;
wire [31:0] t1;
always @(*) begin
s00[31:30] = digest[0][1:0];
s00[29:0] = digest[0][31:2];
s01[31:19] = digest[0][12:0];
s01[18:0] = digest[0][31:13];
s02[31:10] = digest[0][21:0];
s02[9:0] = digest[0][31:22];
s10[31:26] = digest[4][5:0];
s10[25:0] = digest[4][31:6];
s11[31:21] = digest[4][10:0];
s11[20:0] = digest[4][31:11];
s12[31:7] = digest[4][24:0];
s12[6:0] = digest[4][31:25];
maj = (digest[0] & digest[1]) ^ (digest[0] & digest[2]) ^ (digest[1] & digest[2]);
ch = (digest[4] & digest[5]) ^ (~digest[4] & digest[6]);
s0 = s00 ^ s01 ^ s02;
s1 = s10 ^ s11 ^ s12;
t2 = s0+maj;
t1 = digest[7] + s1 + ch + K + words[0];
end
//shift digests (internal states)
always @(posedge clk) begin
digestOut[0] <= t1 + t2;
digestOut[1] <= digest[0];
digestOut[2] <= digest[1];
digestOut[3] <= digest[2];
digestOut[4] <= digest[3] + t1;
digestOut[5] <= digest[4];
digestOut[6] <= digest[5];
digestOut[7] <= digest[6];
end
//words computation for next round
wire [31:0] w00;
wire [31:0] w01;
wire [31:0] w02;
wire [31:0] w10;
wire [31:0] w11;
wire [31:0] w12;
wire [31:0] newWord;
always @(*) begin
w00[31:25] = words[1][6:0];
w00[24:0] = words[1][31:7];
w01[31:14] = words[1][17:0];
w01[13:0] = words[1][31:18];
w02 = words[1] >> 3;
w10[31:15] = words[14][16:0];
w10[14:0] = words[14][31:17];
w11[31:13] = words[14][18:0];
w11[12:0] = words[14][31:19];
w12 = words[14] >> 10;
newWord = words[0] + (w00^ w01^w02) + words[9] + (w10 ^ w11 ^ w12);
end
//words are shifted and last one is updated + index increment
always @(posedge clk) begin
wordsOut[15] <= newWord;
for(int i =0; i< 15; i++) begin
wordsOut[i] <= words[i+1];
end
//increment index
indexOut <= index +1'h1;
end
endmodule
extern module ram #(parameter elementWidth = 32, parameter elementCount = 8, parameter depth = 256, parameter addrWidth = log2(depth)) (input clk, input [(elementWidth-1):0] data[0:(elementCount-1)], input [(addrWidth-1):0] write_addr, input [(addrWidth-1):0] read_addr, input we, output [(elementWidth-1):0] q[0:(elementCount-1)]);
//queue - same as in sha, but different data size
//inspiration taken from altera examples
//this queue now replaces last element if it is full, could be changed, but newer results are ussually better
//anyway it should be never filled, if so we need to change target
module shaqueue(clk, write, read, in, out, available, full);
parameter elementWidth = 8;
parameter elementCount = 128;
parameter depth = 256;
input clk;
input write;
input read;
input [(elementWidth-1):0] in[0:(elementCount-1)];
output [(elementWidth-1):0] out[0:(elementCount-1)];
output available;
output full;
function integer log2(input integer v);
begin log2=0;
while(v>>log2)
log2=log2+1;
end endfunction
localparam addrWidth = log2(depth-1);
reg[(addrWidth-1):0] write_addr, read_addr;
reg[addrWidth:0] count;
ram #(.elementWidth(elementWidth), .elementCount(elementCount), .depth(depth)) ram(clk, in, write_addr, (read & available) ? (read_addr+1) : read_addr, write, out);
initial begin
read_addr = 0;
write_addr = 0;
count = 0;
end
//queue is full
assign full = (count == depth);
//some elements available
assign available = (count > 0);
always@(posedge clk) begin
//put, drop and available case
if(write & read & available) begin
write_addr <= write_addr + 1;
read_addr <= read_addr +1;
//write only case
end else if(write) begin
write_addr <= write_addr + 1;
//this causes rewrite of oldest value
if(~full) begin
count <= count +1;
end
//drop only case
end else if(read & available) begin
read_addr <= read_addr + 1;
count <= count - 1;
end
end
endmodule
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: crc_128_init
*
*/
module crc_128_init (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk ,
input wire res_n ,
//----------------------------------
//----Input
//----------------------------------
input wire [127:0] inData ,
//----------------------------------
//----Output
//----------------------------------
output reg [31:0] crc
);
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if (!res_n) begin
crc <= 32'h0;
end
else begin
crc[31] <= inData[2]^inData[5]^inData[10]^inData[12]^inData[13]^inData[14]^inData[16]^inData[17]^inData[20]^inData[21]^inData[23]^inData[25]^inData[26]^inData[28]^inData[32]^inData[34]^inData[36]^inData[40]^inData[41]^inData[43]^inData[45]^inData[47]^inData[49]^inData[51]^inData[53]^inData[54]^inData[57]^inData[58]^inData[60]^inData[61]^inData[64]^inData[65]^inData[66]^inData[71]^inData[74]^inData[76]^inData[77]^inData[78]^inData[80]^inData[81]^inData[82]^inData[84]^inData[92]^inData[93]^inData[94]^inData[100]^inData[102]^inData[103]^inData[104]^inData[105]^inData[106]^inData[108]^inData[111]^inData[115]^inData[116]^inData[119]^inData[121]^inData[122]^inData[125]^inData[126];
crc[30] <= inData[3]^inData[6]^inData[11]^inData[13]^inData[14]^inData[15]^inData[17]^inData[18]^inData[21]^inData[22]^inData[24]^inData[26]^inData[27]^inData[29]^inData[33]^inData[35]^inData[37]^inData[41]^inData[42]^inData[44]^inData[46]^inData[48]^inData[50]^inData[52]^inData[54]^inData[55]^inData[58]^inData[59]^inData[61]^inData[62]^inData[65]^inData[66]^inData[67]^inData[72]^inData[75]^inData[77]^inData[78]^inData[79]^inData[81]^inData[82]^inData[83]^inData[85]^inData[93]^inData[94]^inData[95]^inData[101]^inData[103]^inData[104]^inData[105]^inData[106]^inData[107]^inData[109]^inData[112]^inData[116]^inData[117]^inData[120]^inData[122]^inData[123]^inData[126]^inData[127];
crc[29] <= inData[2]^inData[4]^inData[5]^inData[7]^inData[10]^inData[13]^inData[15]^inData[17]^inData[18]^inData[19]^inData[20]^inData[21]^inData[22]^inData[26]^inData[27]^inData[30]^inData[32]^inData[38]^inData[40]^inData[41]^inData[42]^inData[54]^inData[55]^inData[56]^inData[57]^inData[58]^inData[59]^inData[61]^inData[62]^inData[63]^inData[64]^inData[65]^inData[67]^inData[68]^inData[71]^inData[73]^inData[74]^inData[77]^inData[79]^inData[81]^inData[83]^inData[86]^inData[92]^inData[93]^inData[95]^inData[96]^inData[100]^inData[103]^inData[107]^inData[110]^inData[111]^inData[113]^inData[115]^inData[116]^inData[117]^inData[118]^inData[119]^inData[122]^inData[123]^inData[124]^inData[125]^inData[126]^inData[127];
crc[28] <= inData[0]^inData[2]^inData[3]^inData[6]^inData[8]^inData[10]^inData[11]^inData[12]^inData[13]^inData[17]^inData[18]^inData[19]^inData[22]^inData[25]^inData[26]^inData[27]^inData[31]^inData[32]^inData[33]^inData[34]^inData[36]^inData[39]^inData[40]^inData[42]^inData[45]^inData[47]^inData[49]^inData[51]^inData[53]^inData[54]^inData[55]^inData[56]^inData[59]^inData[61]^inData[62]^inData[63]^inData[68]^inData[69]^inData[71]^inData[72]^inData[75]^inData[76]^inData[77]^inData[81]^inData[87]^inData[92]^inData[96]^inData[97]^inData[100]^inData[101]^inData[102]^inData[103]^inData[105]^inData[106]^inData[112]^inData[114]^inData[115]^inData[117]^inData[118]^inData[120]^inData[121]^inData[122]^inData[123]^inData[124]^inData[127];
crc[27] <= inData[0]^inData[1]^inData[2]^inData[3]^inData[4]^inData[5]^inData[7]^inData[9]^inData[10]^inData[11]^inData[16]^inData[17]^inData[18]^inData[19]^inData[21]^inData[25]^inData[27]^inData[33]^inData[35]^inData[36]^inData[37]^inData[45]^inData[46]^inData[47]^inData[48]^inData[49]^inData[50]^inData[51]^inData[52]^inData[53]^inData[55]^inData[56]^inData[58]^inData[61]^inData[62]^inData[63]^inData[65]^inData[66]^inData[69]^inData[70]^inData[71]^inData[72]^inData[73]^inData[74]^inData[80]^inData[81]^inData[84]^inData[88]^inData[92]^inData[94]^inData[97]^inData[98]^inData[100]^inData[101]^inData[105]^inData[107]^inData[108]^inData[111]^inData[113]^inData[118]^inData[123]^inData[124]^inData[126];
crc[26] <= inData[0]^inData[1]^inData[2]^inData[3]^inData[4]^inData[5]^inData[6]^inData[8]^inData[10]^inData[11]^inData[12]^inData[17]^inData[18]^inData[19]^inData[20]^inData[22]^inData[26]^inData[28]^inData[34]^inData[36]^inData[37]^inData[38]^inData[46]^inData[47]^inData[48]^inData[49]^inData[50]^inData[51]^inData[52]^inData[53]^inData[54]^inData[56]^inData[57]^inData[59]^inData[62]^inData[63]^inData[64]^inData[66]^inData[67]^inData[70]^inData[71]^inData[72]^inData[73]^inData[74]^inData[75]^inData[81]^inData[82]^inData[85]^inData[89]^inData[93]^inData[95]^inData[98]^inData[99]^inData[101]^inData[102]^inData[106]^inData[108]^inData[109]^inData[112]^inData[114]^inData[119]^inData[124]^inData[125]^inData[127];
crc[25] <= inData[0]^inData[1]^inData[3]^inData[4]^inData[6]^inData[7]^inData[9]^inData[10]^inData[11]^inData[14]^inData[16]^inData[17]^inData[18]^inData[19]^inData[25]^inData[26]^inData[27]^inData[28]^inData[29]^inData[32]^inData[34]^inData[35]^inData[36]^inData[37]^inData[38]^inData[39]^inData[40]^inData[41]^inData[43]^inData[45]^inData[48]^inData[50]^inData[52]^inData[55]^inData[61]^inData[63]^inData[66]^inData[67]^inData[68]^inData[72]^inData[73]^inData[75]^inData[77]^inData[78]^inData[80]^inData[81]^inData[83]^inData[84]^inData[86]^inData[90]^inData[92]^inData[93]^inData[96]^inData[99]^inData[104]^inData[105]^inData[106]^inData[107]^inData[108]^inData[109]^inData[110]^inData[111]^inData[113]^inData[116]^inData[119]^inData[120]^inData[121]^inData[122];
crc[24] <= inData[1]^inData[2]^inData[4]^inData[5]^inData[7]^inData[8]^inData[10]^inData[11]^inData[12]^inData[15]^inData[17]^inData[18]^inData[19]^inData[20]^inData[26]^inData[27]^inData[28]^inData[29]^inData[30]^inData[33]^inData[35]^inData[36]^inData[37]^inData[38]^inData[39]^inData[40]^inData[41]^inData[42]^inData[44]^inData[46]^inData[49]^inData[51]^inData[53]^inData[56]^inData[62]^inData[64]^inData[67]^inData[68]^inData[69]^inData[73]^inData[74]^inData[76]^inData[78]^inData[79]^inData[81]^inData[82]^inData[84]^inData[85]^inData[87]^inData[91]^inData[93]^inData[94]^inData[97]^inData[100]^inData[105]^inData[106]^inData[107]^inData[108]^inData[109]^inData[110]^inData[111]^inData[112]^inData[114]^inData[117]^inData[120]^inData[121]^inData[122]^inData[123];
crc[23] <= inData[2]^inData[3]^inData[5]^inData[6]^inData[8]^inData[9]^inData[11]^inData[12]^inData[13]^inData[16]^inData[18]^inData[19]^inData[20]^inData[21]^inData[27]^inData[28]^inData[29]^inData[30]^inData[31]^inData[34]^inData[36]^inData[37]^inData[38]^inData[39]^inData[40]^inData[41]^inData[42]^inData[43]^inData[45]^inData[47]^inData[50]^inData[52]^inData[54]^inData[57]^inData[63]^inData[65]^inData[68]^inData[69]^inData[70]^inData[74]^inData[75]^inData[77]^inData[79]^inData[80]^inData[82]^inData[83]^inData[85]^inData[86]^inData[88]^inData[92]^inData[94]^inData[95]^inData[98]^inData[101]^inData[106]^inData[107]^inData[108]^inData[109]^inData[110]^inData[111]^inData[112]^inData[113]^inData[115]^inData[118]^inData[121]^inData[122]^inData[123]^inData[124];
crc[22] <= inData[3]^inData[4]^inData[6]^inData[7]^inData[9]^inData[10]^inData[12]^inData[13]^inData[14]^inData[17]^inData[19]^inData[20]^inData[21]^inData[22]^inData[28]^inData[29]^inData[30]^inData[31]^inData[32]^inData[35]^inData[37]^inData[38]^inData[39]^inData[40]^inData[41]^inData[42]^inData[43]^inData[44]^inData[46]^inData[48]^inData[51]^inData[53]^inData[55]^inData[58]^inData[64]^inData[66]^inData[69]^inData[70]^inData[71]^inData[75]^inData[76]^inData[78]^inData[80]^inData[81]^inData[83]^inData[84]^inData[86]^inData[87]^inData[89]^inData[93]^inData[95]^inData[96]^inData[99]^inData[102]^inData[107]^inData[108]^inData[109]^inData[110]^inData[111]^inData[112]^inData[113]^inData[114]^inData[116]^inData[119]^inData[122]^inData[123]^inData[124]^inData[125];
crc[21] <= inData[4]^inData[5]^inData[7]^inData[8]^inData[10]^inData[11]^inData[13]^inData[14]^inData[15]^inData[18]^inData[20]^inData[21]^inData[22]^inData[23]^inData[29]^inData[30]^inData[31]^inData[32]^inData[33]^inData[36]^inData[38]^inData[39]^inData[40]^inData[41]^inData[42]^inData[43]^inData[44]^inData[45]^inData[47]^inData[49]^inData[52]^inData[54]^inData[56]^inData[59]^inData[65]^inData[67]^inData[70]^inData[71]^inData[72]^inData[76]^inData[77]^inData[79]^inData[81]^inData[82]^inData[84]^inData[85]^inData[87]^inData[88]^inData[90]^inData[94]^inData[96]^inData[97]^inData[100]^inData[103]^inData[108]^inData[109]^inData[110]^inData[111]^inData[112]^inData[113]^inData[114]^inData[115]^inData[117]^inData[120]^inData[123]^inData[124]^inData[125]^inData[126];
crc[20] <= inData[0]^inData[5]^inData[6]^inData[8]^inData[9]^inData[11]^inData[12]^inData[14]^inData[15]^inData[16]^inData[19]^inData[21]^inData[22]^inData[23]^inData[24]^inData[30]^inData[31]^inData[32]^inData[33]^inData[34]^inData[37]^inData[39]^inData[40]^inData[41]^inData[42]^inData[43]^inData[44]^inData[45]^inData[46]^inData[48]^inData[50]^inData[53]^inData[55]^inData[57]^inData[60]^inData[66]^inData[68]^inData[71]^inData[72]^inData[73]^inData[77]^inData[78]^inData[80]^inData[82]^inData[83]^inData[85]^inData[86]^inData[88]^inData[89]^inData[91]^inData[95]^inData[97]^inData[98]^inData[101]^inData[104]^inData[109]^inData[110]^inData[111]^inData[112]^inData[113]^inData[114]^inData[115]^inData[116]^inData[118]^inData[121]^inData[124]^inData[125]^inData[126]^inData[127];
crc[19] <= inData[1]^inData[2]^inData[5]^inData[6]^inData[7]^inData[9]^inData[14]^inData[15]^inData[21]^inData[22]^inData[24]^inData[26]^inData[28]^inData[31]^inData[33]^inData[35]^inData[36]^inData[38]^inData[42]^inData[44]^inData[46]^inData[53]^inData[56]^inData[57]^inData[60]^inData[64]^inData[65]^inData[66]^inData[67]^inData[69]^inData[71]^inData[72]^inData[73]^inData[76]^inData[77]^inData[79]^inData[80]^inData[82]^inData[83]^inData[86]^inData[87]^inData[89]^inData[90]^inData[93]^inData[94]^inData[96]^inData[98]^inData[99]^inData[100]^inData[103]^inData[104]^inData[106]^inData[108]^inData[110]^inData[112]^inData[113]^inData[114]^inData[117]^inData[121]^inData[127];
crc[18] <= inData[3]^inData[5]^inData[6]^inData[7]^inData[8]^inData[12]^inData[13]^inData[14]^inData[15]^inData[17]^inData[20]^inData[21]^inData[22]^inData[26]^inData[27]^inData[28]^inData[29]^inData[37]^inData[39]^inData[40]^inData[41]^inData[49]^inData[51]^inData[53]^inData[60]^inData[64]^inData[67]^inData[68]^inData[70]^inData[71]^inData[72]^inData[73]^inData[76]^inData[82]^inData[83]^inData[87]^inData[88]^inData[90]^inData[91]^inData[92]^inData[93]^inData[95]^inData[97]^inData[99]^inData[101]^inData[102]^inData[103]^inData[106]^inData[107]^inData[108]^inData[109]^inData[113]^inData[114]^inData[116]^inData[118]^inData[119]^inData[121]^inData[125]^inData[126];
crc[17] <= inData[0]^inData[4]^inData[6]^inData[7]^inData[8]^inData[9]^inData[13]^inData[14]^inData[15]^inData[16]^inData[18]^inData[21]^inData[22]^inData[23]^inData[27]^inData[28]^inData[29]^inData[30]^inData[38]^inData[40]^inData[41]^inData[42]^inData[50]^inData[52]^inData[54]^inData[61]^inData[65]^inData[68]^inData[69]^inData[71]^inData[72]^inData[73]^inData[74]^inData[77]^inData[83]^inData[84]^inData[88]^inData[89]^inData[91]^inData[92]^inData[93]^inData[94]^inData[96]^inData[98]^inData[100]^inData[102]^inData[103]^inData[104]^inData[107]^inData[108]^inData[109]^inData[110]^inData[114]^inData[115]^inData[117]^inData[119]^inData[120]^inData[122]^inData[126]^inData[127];
crc[16] <= inData[0]^inData[1]^inData[2]^inData[7]^inData[8]^inData[9]^inData[12]^inData[13]^inData[15]^inData[19]^inData[20]^inData[21]^inData[22]^inData[24]^inData[25]^inData[26]^inData[29]^inData[30]^inData[31]^inData[32]^inData[34]^inData[36]^inData[39]^inData[40]^inData[42]^inData[45]^inData[47]^inData[49]^inData[54]^inData[55]^inData[57]^inData[58]^inData[60]^inData[61]^inData[62]^inData[64]^inData[65]^inData[69]^inData[70]^inData[71]^inData[72]^inData[73]^inData[75]^inData[76]^inData[77]^inData[80]^inData[81]^inData[82]^inData[85]^inData[89]^inData[90]^inData[95]^inData[97]^inData[99]^inData[100]^inData[101]^inData[102]^inData[106]^inData[109]^inData[110]^inData[118]^inData[119]^inData[120]^inData[122]^inData[123]^inData[125]^inData[126]^inData[127];
crc[15] <= inData[0]^inData[1]^inData[3]^inData[5]^inData[8]^inData[9]^inData[12]^inData[17]^inData[22]^inData[27]^inData[28]^inData[30]^inData[31]^inData[33]^inData[34]^inData[35]^inData[36]^inData[37]^inData[45]^inData[46]^inData[47]^inData[48]^inData[49]^inData[50]^inData[51]^inData[53]^inData[54]^inData[55]^inData[56]^inData[57]^inData[59]^inData[60]^inData[62]^inData[63]^inData[64]^inData[70]^inData[72]^inData[73]^inData[80]^inData[83]^inData[84]^inData[86]^inData[90]^inData[91]^inData[92]^inData[93]^inData[94]^inData[96]^inData[98]^inData[101]^inData[104]^inData[105]^inData[106]^inData[107]^inData[108]^inData[110]^inData[115]^inData[116]^inData[120]^inData[122]^inData[123]^inData[124]^inData[125]^inData[127];
crc[14] <= inData[0]^inData[1]^inData[4]^inData[5]^inData[6]^inData[9]^inData[12]^inData[14]^inData[16]^inData[17]^inData[18]^inData[20]^inData[21]^inData[25]^inData[26]^inData[29]^inData[31]^inData[35]^inData[37]^inData[38]^inData[40]^inData[41]^inData[43]^inData[45]^inData[46]^inData[48]^inData[50]^inData[52]^inData[53]^inData[55]^inData[56]^inData[63]^inData[66]^inData[73]^inData[76]^inData[77]^inData[78]^inData[80]^inData[82]^inData[85]^inData[87]^inData[91]^inData[95]^inData[97]^inData[99]^inData[100]^inData[103]^inData[104]^inData[107]^inData[109]^inData[115]^inData[117]^inData[119]^inData[122]^inData[123]^inData[124];
crc[13] <= inData[1]^inData[2]^inData[5]^inData[6]^inData[7]^inData[10]^inData[13]^inData[15]^inData[17]^inData[18]^inData[19]^inData[21]^inData[22]^inData[26]^inData[27]^inData[30]^inData[32]^inData[36]^inData[38]^inData[39]^inData[41]^inData[42]^inData[44]^inData[46]^inData[47]^inData[49]^inData[51]^inData[53]^inData[54]^inData[56]^inData[57]^inData[64]^inData[67]^inData[74]^inData[77]^inData[78]^inData[79]^inData[81]^inData[83]^inData[86]^inData[88]^inData[92]^inData[96]^inData[98]^inData[100]^inData[101]^inData[104]^inData[105]^inData[108]^inData[110]^inData[116]^inData[118]^inData[120]^inData[123]^inData[124]^inData[125];
crc[12] <= inData[0]^inData[2]^inData[3]^inData[6]^inData[7]^inData[8]^inData[11]^inData[14]^inData[16]^inData[18]^inData[19]^inData[20]^inData[22]^inData[23]^inData[27]^inData[28]^inData[31]^inData[33]^inData[37]^inData[39]^inData[40]^inData[42]^inData[43]^inData[45]^inData[47]^inData[48]^inData[50]^inData[52]^inData[54]^inData[55]^inData[57]^inData[58]^inData[65]^inData[68]^inData[75]^inData[78]^inData[79]^inData[80]^inData[82]^inData[84]^inData[87]^inData[89]^inData[93]^inData[97]^inData[99]^inData[101]^inData[102]^inData[105]^inData[106]^inData[109]^inData[111]^inData[117]^inData[119]^inData[121]^inData[124]^inData[125]^inData[126];
crc[11] <= inData[1]^inData[3]^inData[4]^inData[7]^inData[8]^inData[9]^inData[12]^inData[15]^inData[17]^inData[19]^inData[20]^inData[21]^inData[23]^inData[24]^inData[28]^inData[29]^inData[32]^inData[34]^inData[38]^inData[40]^inData[41]^inData[43]^inData[44]^inData[46]^inData[48]^inData[49]^inData[51]^inData[53]^inData[55]^inData[56]^inData[58]^inData[59]^inData[66]^inData[69]^inData[76]^inData[79]^inData[80]^inData[81]^inData[83]^inData[85]^inData[88]^inData[90]^inData[94]^inData[98]^inData[100]^inData[102]^inData[103]^inData[106]^inData[107]^inData[110]^inData[112]^inData[118]^inData[120]^inData[122]^inData[125]^inData[126]^inData[127];
crc[10] <= inData[4]^inData[8]^inData[9]^inData[12]^inData[14]^inData[17]^inData[18]^inData[22]^inData[23]^inData[24]^inData[26]^inData[28]^inData[29]^inData[30]^inData[32]^inData[33]^inData[34]^inData[35]^inData[36]^inData[39]^inData[40]^inData[42]^inData[43]^inData[44]^inData[50]^inData[51]^inData[52]^inData[53]^inData[56]^inData[58]^inData[59]^inData[61]^inData[64]^inData[65]^inData[66]^inData[67]^inData[70]^inData[71]^inData[74]^inData[76]^inData[78]^inData[86]^inData[89]^inData[91]^inData[92]^inData[93]^inData[94]^inData[95]^inData[99]^inData[100]^inData[101]^inData[102]^inData[105]^inData[106]^inData[107]^inData[113]^inData[115]^inData[116]^inData[122]^inData[123]^inData[125]^inData[127];
crc[ 9] <= inData[0]^inData[2]^inData[9]^inData[12]^inData[14]^inData[15]^inData[16]^inData[17]^inData[18]^inData[19]^inData[20]^inData[21]^inData[24]^inData[26]^inData[27]^inData[28]^inData[29]^inData[30]^inData[31]^inData[32]^inData[33]^inData[35]^inData[37]^inData[44]^inData[47]^inData[49]^inData[52]^inData[58]^inData[59]^inData[61]^inData[62]^inData[64]^inData[67]^inData[68]^inData[72]^inData[74]^inData[75]^inData[76]^inData[78]^inData[79]^inData[80]^inData[81]^inData[82]^inData[84]^inData[87]^inData[90]^inData[95]^inData[96]^inData[101]^inData[104]^inData[105]^inData[107]^inData[111]^inData[114]^inData[115]^inData[117]^inData[119]^inData[121]^inData[122]^inData[123]^inData[124]^inData[125];
crc[ 8] <= inData[1]^inData[3]^inData[10]^inData[13]^inData[15]^inData[16]^inData[17]^inData[18]^inData[19]^inData[20]^inData[21]^inData[22]^inData[25]^inData[27]^inData[28]^inData[29]^inData[30]^inData[31]^inData[32]^inData[33]^inData[34]^inData[36]^inData[38]^inData[45]^inData[48]^inData[50]^inData[53]^inData[59]^inData[60]^inData[62]^inData[63]^inData[65]^inData[68]^inData[69]^inData[73]^inData[75]^inData[76]^inData[77]^inData[79]^inData[80]^inData[81]^inData[82]^inData[83]^inData[85]^inData[88]^inData[91]^inData[96]^inData[97]^inData[102]^inData[105]^inData[106]^inData[108]^inData[112]^inData[115]^inData[116]^inData[118]^inData[120]^inData[122]^inData[123]^inData[124]^inData[125]^inData[126];
crc[ 7] <= inData[0]^inData[2]^inData[4]^inData[11]^inData[14]^inData[16]^inData[17]^inData[18]^inData[19]^inData[20]^inData[21]^inData[22]^inData[23]^inData[26]^inData[28]^inData[29]^inData[30]^inData[31]^inData[32]^inData[33]^inData[34]^inData[35]^inData[37]^inData[39]^inData[46]^inData[49]^inData[51]^inData[54]^inData[60]^inData[61]^inData[63]^inData[64]^inData[66]^inData[69]^inData[70]^inData[74]^inData[76]^inData[77]^inData[78]^inData[80]^inData[81]^inData[82]^inData[83]^inData[84]^inData[86]^inData[89]^inData[92]^inData[97]^inData[98]^inData[103]^inData[106]^inData[107]^inData[109]^inData[113]^inData[116]^inData[117]^inData[119]^inData[121]^inData[123]^inData[124]^inData[125]^inData[126]^inData[127];
crc[ 6] <= inData[0]^inData[1]^inData[2]^inData[3]^inData[10]^inData[13]^inData[14]^inData[15]^inData[16]^inData[18]^inData[19]^inData[22]^inData[24]^inData[25]^inData[26]^inData[27]^inData[28]^inData[29]^inData[30]^inData[31]^inData[33]^inData[35]^inData[38]^inData[41]^inData[43]^inData[45]^inData[49]^inData[50]^inData[51]^inData[52]^inData[53]^inData[54]^inData[55]^inData[57]^inData[58]^inData[60]^inData[62]^inData[66]^inData[67]^inData[70]^inData[74]^inData[75]^inData[76]^inData[79]^inData[80]^inData[83]^inData[85]^inData[87]^inData[90]^inData[92]^inData[94]^inData[98]^inData[99]^inData[100]^inData[102]^inData[103]^inData[105]^inData[106]^inData[107]^inData[110]^inData[111]^inData[114]^inData[115]^inData[116]^inData[117]^inData[118]^inData[119]^inData[120]^inData[121]^inData[124]^inData[127];
crc[ 5] <= inData[1]^inData[3]^inData[4]^inData[5]^inData[10]^inData[11]^inData[12]^inData[13]^inData[15]^inData[19]^inData[21]^inData[27]^inData[29]^inData[30]^inData[31]^inData[39]^inData[40]^inData[41]^inData[42]^inData[43]^inData[44]^inData[45]^inData[46]^inData[47]^inData[49]^inData[50]^inData[52]^inData[55]^inData[56]^inData[57]^inData[59]^inData[60]^inData[63]^inData[64]^inData[65]^inData[66]^inData[67]^inData[68]^inData[74]^inData[75]^inData[78]^inData[82]^inData[86]^inData[88]^inData[91]^inData[92]^inData[94]^inData[95]^inData[99]^inData[101]^inData[102]^inData[105]^inData[107]^inData[112]^inData[117]^inData[118]^inData[120]^inData[126];
crc[ 4] <= inData[0]^inData[2]^inData[4]^inData[5]^inData[6]^inData[11]^inData[12]^inData[13]^inData[14]^inData[16]^inData[20]^inData[22]^inData[28]^inData[30]^inData[31]^inData[32]^inData[40]^inData[41]^inData[42]^inData[43]^inData[44]^inData[45]^inData[46]^inData[47]^inData[48]^inData[50]^inData[51]^inData[53]^inData[56]^inData[57]^inData[58]^inData[60]^inData[61]^inData[64]^inData[65]^inData[66]^inData[67]^inData[68]^inData[69]^inData[75]^inData[76]^inData[79]^inData[83]^inData[87]^inData[89]^inData[92]^inData[93]^inData[95]^inData[96]^inData[100]^inData[102]^inData[103]^inData[106]^inData[108]^inData[113]^inData[118]^inData[119]^inData[121]^inData[127];
crc[ 3] <= inData[0]^inData[1]^inData[2]^inData[3]^inData[6]^inData[7]^inData[10]^inData[15]^inData[16]^inData[20]^inData[25]^inData[26]^inData[28]^inData[29]^inData[31]^inData[33]^inData[34]^inData[36]^inData[40]^inData[42]^inData[44]^inData[46]^inData[48]^inData[52]^inData[53]^inData[59]^inData[60]^inData[62]^inData[64]^inData[67]^inData[68]^inData[69]^inData[70]^inData[71]^inData[74]^inData[78]^inData[81]^inData[82]^inData[88]^inData[90]^inData[92]^inData[96]^inData[97]^inData[100]^inData[101]^inData[102]^inData[105]^inData[106]^inData[107]^inData[108]^inData[109]^inData[111]^inData[114]^inData[115]^inData[116]^inData[120]^inData[121]^inData[125]^inData[126];
crc[ 2] <= inData[0]^inData[1]^inData[2]^inData[3]^inData[4]^inData[7]^inData[8]^inData[11]^inData[16]^inData[17]^inData[21]^inData[26]^inData[27]^inData[29]^inData[30]^inData[32]^inData[34]^inData[35]^inData[37]^inData[41]^inData[43]^inData[45]^inData[47]^inData[49]^inData[53]^inData[54]^inData[60]^inData[61]^inData[63]^inData[65]^inData[68]^inData[69]^inData[70]^inData[71]^inData[72]^inData[75]^inData[79]^inData[82]^inData[83]^inData[89]^inData[91]^inData[93]^inData[97]^inData[98]^inData[101]^inData[102]^inData[103]^inData[106]^inData[107]^inData[108]^inData[109]^inData[110]^inData[112]^inData[115]^inData[116]^inData[117]^inData[121]^inData[122]^inData[126]^inData[127];
crc[ 1] <= inData[0]^inData[1]^inData[3]^inData[4]^inData[8]^inData[9]^inData[10]^inData[13]^inData[14]^inData[16]^inData[18]^inData[20]^inData[21]^inData[22]^inData[23]^inData[25]^inData[26]^inData[27]^inData[30]^inData[31]^inData[32]^inData[33]^inData[34]^inData[35]^inData[38]^inData[40]^inData[41]^inData[42]^inData[43]^inData[44]^inData[45]^inData[46]^inData[47]^inData[48]^inData[49]^inData[50]^inData[51]^inData[53]^inData[55]^inData[57]^inData[58]^inData[60]^inData[62]^inData[65]^inData[69]^inData[70]^inData[72]^inData[73]^inData[74]^inData[77]^inData[78]^inData[81]^inData[82]^inData[83]^inData[90]^inData[93]^inData[98]^inData[99]^inData[100]^inData[105]^inData[106]^inData[107]^inData[109]^inData[110]^inData[113]^inData[115]^inData[117]^inData[118]^inData[119]^inData[121]^inData[123]^inData[125]^inData[126]^inData[127];
crc[ 0] <= inData[1]^inData[4]^inData[9]^inData[11]^inData[12]^inData[13]^inData[15]^inData[16]^inData[19]^inData[20]^inData[22]^inData[24]^inData[25]^inData[27]^inData[31]^inData[33]^inData[35]^inData[39]^inData[40]^inData[42]^inData[44]^inData[46]^inData[48]^inData[50]^inData[52]^inData[53]^inData[56]^inData[57]^inData[59]^inData[60]^inData[63]^inData[64]^inData[65]^inData[70]^inData[73]^inData[75]^inData[76]^inData[77]^inData[79]^inData[80]^inData[81]^inData[83]^inData[91]^inData[92]^inData[93]^inData[99]^inData[101]^inData[102]^inData[103]^inData[104]^inData[105]^inData[107]^inData[110]^inData[114]^inData[115]^inData[118]^inData[120]^inData[121]^inData[124]^inData[125]^inData[127];
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: c2i_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: c2i_buf (cpu-to-io UCB buffer)
// Description: This is the interface to the UCB modules.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module c2i_buf (/*AUTOARG*/
// Outputs
ucb_buf_acpt, iob_ucb_vld, iob_ucb_data,
// Inputs
rst_l, clk, c2i_packet_vld, ucb_sel, c2i_packet, ucb_iob_stall
);
// synopsys template
parameter REG_WIDTH = 64;
parameter IOB_UCB_WIDTH = 32;
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
// Global interface
input rst_l;
input clk;
// slow control interface
input c2i_packet_vld;
input ucb_sel;
output ucb_buf_acpt;
// slow datapath interface
input [REG_WIDTH+63:0] c2i_packet;
// UCB interface
output iob_ucb_vld;
output [IOB_UCB_WIDTH-1:0] iob_ucb_data;
input ucb_iob_stall;
// Internal signals
wire dbl_buf_wr;
wire dbl_buf_rd;
wire dbl_buf_vld;
wire dbl_buf_full;
wire outdata_buf_wr;
wire [REG_WIDTH+63:0] outdata_buf_in;
wire [(REG_WIDTH+64)/IOB_UCB_WIDTH-1:0] outdata_vec_in;
wire outdata_buf_busy;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
assign dbl_buf_wr = c2i_packet_vld & ucb_sel & ~dbl_buf_full;
assign ucb_buf_acpt = dbl_buf_wr;
assign dbl_buf_rd = dbl_buf_vld & ~outdata_buf_busy;
assign outdata_buf_wr = dbl_buf_rd;
assign outdata_vec_in = {(REG_WIDTH+64)/IOB_UCB_WIDTH{1'b1}};
dbl_buf #(REG_WIDTH+64) dbl_buf (.rst_l(rst_l),
.clk(clk),
.wr(dbl_buf_wr),
.din(c2i_packet),
.rd(dbl_buf_rd),
.dout(outdata_buf_in),
.vld(dbl_buf_vld),
.full(dbl_buf_full));
ucb_bus_out #(IOB_UCB_WIDTH,REG_WIDTH) ucb_bus_out (.rst_l(rst_l),
.clk(clk),
.outdata_buf_wr(outdata_buf_wr),
.outdata_buf_in(outdata_buf_in),
.outdata_vec_in(outdata_vec_in),
.outdata_buf_busy(outdata_buf_busy),
.vld(iob_ucb_vld),
.data(iob_ucb_data),
.stall(ucb_iob_stall));
endmodule // c2i_buf
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04:04:00 04/01/2012
// Design Name:
// Module Name: sigma_delta_dac
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`define MSBI 7 // Most significant Bit of DAC input
//This is a Delta-Sigma Digital to Analog Converter
module dac (DACout, DACin, Clk, Reset);
output DACout; // This is the average output that feeds low pass filter
input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset;
reg DACout; // for optimum performance, ensure that this ff is in IOB
reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [`MSBI+2:0] SigmaLatch = 1'b1 << (`MSBI+1); // Latches output of Sigma adder
reg [`MSBI+2:0] DeltaB; // B input of Delta adder
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk)
begin
if(Reset)
begin
SigmaLatch <= #1 1'b1 << (`MSBI+1);
DACout <= #1 1'b0;
end
else
begin
SigmaLatch <= #1 SigmaAdder;
DACout <= #1 SigmaLatch[`MSBI+2];
end
end
endmodule
module mixer (
input wire clkdac,
input wire reset,
input wire ear,
input wire mic,
input wire spk,
input wire [7:0] ay1,
input wire [7:0] ay2,
output wire audio
);
parameter
SRC_BEEPER = 2'd0,
SRC_AY1 = 2'd1,
SRC_AY2 = 2'd2;
wire [7:0] beeper = ({ear,spk,mic}==3'b000)? 8'd17 :
({ear,spk,mic}==3'b001)? 8'd36 :
({ear,spk,mic}==3'b010)? 8'd184 :
({ear,spk,mic}==3'b011)? 8'd192 :
({ear,spk,mic}==3'b100)? 8'd22 :
({ear,spk,mic}==3'b101)? 8'd48 :
({ear,spk,mic}==3'b110)? 8'd244 : 8'd255;
reg [7:0] mezcla;
reg [1:0] sndsource = 2'd0;
always @(posedge clkdac) begin
case (sndsource)
SRC_BEEPER: mezcla <= beeper;
SRC_AY1 : mezcla <= ay1;
SRC_AY2 : mezcla <= ay2;
endcase
sndsource <= (sndsource == 2'd2)? 2'd0 : sndsource + 2'd1; // en lugar de sumar, multiplexamos en el tiempo las fuentes de sonido
end
dac audio_dac (
.DACout(audio),
.DACin(mezcla),
.Clk(clkdac),
.Reset(reset)
);
endmodule
|
/*******************************************************************
date:2016/3/31
designer:ZhaiShaoMin
module name:tb_m_rep_upload
module function :find out bugs in m_rep_upload
********************************************************************/
`timescale 1ns/1ps
module tb_m_rep_upload();
//input
reg clk;
reg rst;
reg [175:0] m_flits_rep;
reg v_m_flits_rep;
reg [3:0] flits_max;
reg en_flits_max;
reg rep_fifo_rdy;
//output
wire [15:0] m_flit_out;
wire v_m_flit_out;
wire [1:0] m_ctrl_out;
wire m_rep_upload_state;
m_rep_upload uut(//input
.clk(clk),
.rst(rst),
.m_flits_rep(m_flits_rep),
.v_m_flits_rep(v_m_flits_rep),
.flits_max(flits_max),
.en_flits_max(en_flits_max),
.rep_fifo_rdy(rep_fifo_rdy),
//output
.m_flit_out(m_flit_out),
.v_m_flit_out(v_m_flit_out),
.m_ctrl_out(m_ctrl_out),
.m_rep_upload_state(m_rep_upload_state)
);
//initial inputs
initial begin
clk=1'b0;
rst=1'b1;
m_flits_rep=144'h0000_0000_0000_0000_0000_0000_0000_0000_0000;
v_m_flits_rep=1'b0;
en_flits_max=1'b0;
flits_max=1'b1;
rep_fifo_rdy=1'b0;
end
`define clk_step # 14;
always #7 clk=~clk;
/////////////////////////////////////////////////////////////
////////////////////////////BEGIN TEST!//////////////////////
initial begin
`clk_step
rst=1'b0;
`clk_step
/////////////////////////////////////////////////////////////
//////////1st case: a msg which is only one flit long////////
en_flits_max=1'b1;
flits_max=4'b0000;
rep_fifo_rdy=1'b1;
`clk_step
en_flits_max=1'b0;
m_flits_rep=144'hc0de_c1de_c2de_c3de_c4de_c5de_c6de_c7de_c8de;
v_m_flits_rep=1'b1;
`clk_step
//since rey fifo is ready to receive flit ,so the only flit is poped to rep fifo
v_m_flits_rep=1'b0;
`clk_step
//this cycle m_rep_upload is idle
//in the meantime, preparing for next msg
en_flits_max=1'b1;
flits_max=4'b0010;
/////////////////////////////////////////////////////////////
/////////////2nd case: a msg with 3 flits is coming!/////////
`clk_step
v_m_flits_rep=1'b1;
m_flits_rep=144'habc1_abc2_abc3_abc4_abc5_abc6_abc7_abc8_abc9;
`clk_step
///the 1st flit is transfered to rep fifo
`clk_step
///this cycle rep fifo become full ,so 2nd flit still sit in the regs of m_upload
rep_fifo_rdy=1'b0;
`clk_step
//still full
`clk_step
//still full
`clk_step
//rep fifo become not full! And 2nd flit can be transfered to rep fifo
rep_fifo_rdy=1'b1;
`clk_step
///3rd flit also last flit to rep fifo
`clk_step
/// m_rep_upload become idle
//////////////////////////////////////////////////////////////////
//////////// 3rd case: a msg with 9 flits is coming!//////////////
`clk_step
en_flits_max=1'b1;
flits_max=4'b1000;
`clk_step
m_flits_rep=144'h0123_1234_2345_3456_4567_5678_6789_7890_8901;
v_m_flits_rep=1'b1;
`clk_step
//since rep fifo is ready to receive flit, first flit will get out of m_rep_upload!
`clk_step
//2nd flit get out
`clk_step
//3rd flit get out
`clk_step
////rep fifo become full
rep_fifo_rdy=1'b0;
`clk_step
//still full
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
`clk_step
//rep fifo has empty slots now! And 4th flit get to rep fifo
rep_fifo_rdy=1'b1;
`clk_step
//5th flit get out
`clk_step
//full again!
rep_fifo_rdy=1'b0;
`clk_step
//rep fifo has empty slots now! And 6th flit get to rep fifo
rep_fifo_rdy=1'b1;
`clk_step
//7th get out
`clk_step
//8th get out
`clk_step
//9th get out
`clk_step
//////m_rep_upload become idle now !
`clk_step
$stop;
end
endmodule
|
`include "bsg_nonsynth_dramsim3.svh"
`ifndef dram_pkg
`define dram_pkg bsg_nonsynth_dramsim3_hbm2_8gb_x128_pkg
`endif
module testbench ();
// clock
logic clk;
bsg_nonsynth_clock_gen
#(.cycle_time_p(`dram_pkg::tck_ps))
clkgen
(.o(clk));
// reset
logic reset;
bsg_nonsynth_reset_gen
#(.reset_cycles_lo_p(0)
,.reset_cycles_hi_p(20))
resetgen
(.clk_i(clk)
,.async_reset_o(reset));
// dramsim3
import `dram_pkg::*;
parameter int num_dramsim3_p = 2;
logic [num_channels_p-1:0] dramsim3_v_li [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] dramsim3_write_not_read_li [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] [channel_addr_width_p-1:0] dramsim3_ch_addr_li [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] dramsim3_yumi_lo [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] dramsim3_data_v_li [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] [data_width_p-1:0] dramsim3_data_li [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] dramsim3_data_yumi_lo [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] dramsim3_data_v_lo [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] [data_width_p-1:0] dramsim3_data_lo [num_dramsim3_p-1:0];
`dram_pkg::dram_ch_addr_s dramsim3_ch_addr_li_cast [num_dramsim3_p-1:0];
for (genvar dramsim_i = 0; dramsim_i < num_dramsim3_p; dramsim_i++) begin
assign dramsim3_ch_addr_li_cast[dramsim_i] = dramsim3_ch_addr_li[dramsim_i][0];
bsg_nonsynth_dramsim3
#(.channel_addr_width_p(`dram_pkg::channel_addr_width_p)
,.data_width_p(`dram_pkg::data_width_p)
,.num_channels_p(`dram_pkg::num_channels_p)
,.num_columns_p(`dram_pkg::num_columns_p)
,.num_rows_p(`dram_pkg::num_rows_p)
,.num_ba_p(`dram_pkg::num_ba_p)
,.num_bg_p(`dram_pkg::num_bg_p)
,.num_ranks_p(`dram_pkg::num_ranks_p)
,.size_in_bits_p(`dram_pkg::size_in_bits_p)
,.address_mapping_p(`dram_pkg::address_mapping_p)
,.config_p(`dram_pkg::config_p)
,.masked_p(0)
,.trace_file_p(`BSG_STRINGIFY(`trace_file))
,.debug_p(1))
mem
(.clk_i(clk)
,.reset_i(reset)
,.v_i(dramsim3_v_li[dramsim_i])
,.write_not_read_i(dramsim3_write_not_read_li[dramsim_i])
,.ch_addr_i(dramsim3_ch_addr_li[dramsim_i])
,.yumi_o(dramsim3_yumi_lo[dramsim_i])
,.data_v_i(dramsim3_data_v_li[dramsim_i])
,.data_i(dramsim3_data_li[dramsim_i])
,.mask_i('0)
,.data_yumi_o(dramsim3_data_yumi_lo[dramsim_i])
,.data_v_o(dramsim3_data_v_lo[dramsim_i])
,.data_o(dramsim3_data_lo[dramsim_i])
,.read_done_ch_addr_o()
,.write_done_o()
,.write_done_ch_addr_o()
);
end
// trace replay
//
typedef struct packed {
logic write_not_read;
logic [channel_addr_width_p-1:0] ch_addr;
} dramsim3_trace_s;
localparam ring_width_p = $bits(dramsim3_trace_s);
localparam rom_addr_width_p=20;
dramsim3_trace_s [num_channels_p-1:0] tr_data_lo [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] tr_v_lo [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] tr_yumi_li [num_dramsim3_p-1:0];
logic [num_channels_p-1:0][4+ring_width_p-1:0] rom_data [num_dramsim3_p-1:0];
logic [num_channels_p-1:0][rom_addr_width_p-1:0] rom_addr [num_dramsim3_p-1:0];
logic [num_channels_p-1:0] ch_done [num_dramsim3_p-1:0];
for (genvar dramsim_i = 0; dramsim_i < num_dramsim3_p; dramsim_i++) begin
for (genvar i = 0; i < num_channels_p; i++) begin
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
//,.en_i(i == '0)
,.v_i(1'b0)
,.data_i('0)
,.ready_o()
,.v_o(tr_v_lo[dramsim_i][i])
,.data_o(tr_data_lo[dramsim_i][i])
,.yumi_i(tr_yumi_li[dramsim_i][i])
,.rom_addr_o(rom_addr[dramsim_i][i])
,.rom_data_i(rom_data[dramsim_i][i])
,.done_o(ch_done[dramsim_i][i])
,.error_o()
);
assign dramsim3_write_not_read_li[dramsim_i][i] = tr_data_lo[dramsim_i][i].write_not_read;
assign dramsim3_ch_addr_li[dramsim_i][i] = tr_data_lo[dramsim_i][i].ch_addr;
assign dramsim3_v_li[dramsim_i][i] = tr_v_lo[dramsim_i][i];
assign tr_yumi_li[dramsim_i][i] = dramsim3_yumi_lo[dramsim_i][i];
end // for (genvar i = 0; i < num_channels_p; i++)
end // for (genvar dramsim_i = 0; dramsim_i < num_dramsim3_p; dramsim_i++)
for (genvar i = 0; i < num_channels_p; i++) begin
bsg_nonsynth_test_rom #(.data_width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
,.filename_p(`BSG_STRINGIFY(`rom_file))
) rom0 (
.addr_i(rom_addr[0][i])
,.data_o(rom_data[0][i])
);
bsg_nonsynth_test_rom #(.data_width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
,.filename_p(`BSG_STRINGIFY(`rom_file_1))
) rom1 (
.addr_i(rom_addr[1][i])
,.data_o(rom_data[1][i])
);
end // for (genvar i = 0; i < num_channels_p; i++)
initial begin
# 10000000 $finish;
end
// always_ff @(posedge clk) begin
// if (~reset & dramsim3_v_li[0][0]) begin
// if (dramsim3_write_not_read_li[0][0])
// $display("write: 0x%08x {ro: %d, ba: %d, bg: %d, co: %d, byte: %d}",
// dramsim3_ch_addr_li[0][0],
// dramsim3_ch_addr_li_cast[0].ro,
// dramsim3_ch_addr_li_cast[0].ba,
// dramsim3_ch_addr_li_cast[0].bg,
// dramsim3_ch_addr_li_cast[0].co,
// dramsim3_ch_addr_li_cast[0].byte_offset);
// else
// $display("read: 0x%08x {ro: %d, ba: %d, bg: %d, co: %d, byte: %d}",
// dramsim3_ch_addr_li[0][0],
// dramsim3_ch_addr_li_cast[0].ro,
// dramsim3_ch_addr_li_cast[0].ba,
// dramsim3_ch_addr_li_cast[0].bg,
// dramsim3_ch_addr_li_cast[0].co,
// dramsim3_ch_addr_li_cast[0].byte_offset);
// end
// end
endmodule
|
//wb_tx1_pcie.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x800000000000C594
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:wb_tx1_pcie
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0F
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2016/06/21
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:3
*/
`include "project_defines.v"
`define CTRL_BIT_SOURCE_EN 0
`define CTRL_BIT_CANCEL_WRITE 1
`define CTRL_BIT_SINK_EN 2
`define STS_BIT_LINKUP 0
`define STS_BIT_READ_IDLE 1
`define STS_PER_FIFO_SEL 2
`define STS_MEM_FIFO_SEL 3
`define STS_DMA_FIFO_SEL 4
`define STS_WRITE_EN 5
`define STS_READ_EN 6
`define LOCAL_BUFFER_OFFSET 24'h000100
module wb_tx1_pcie #(
parameter DATA_INGRESS_FIFO_DEPTH = 10,
parameter DATA_EGRESS_FIFO_DEPTH = 6,
parameter CONTROL_FIFO_DEPTH = 7
) (
input clk,
input rst,
// output o_sys_rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
output o_pcie_reset,
output o_pcie_per_fifo_sel,
output o_pcie_mem_fifo_sel,
output o_pcie_dma_fifo_sel,
input i_pcie_write_fin,
input i_pcie_read_fin,
output [31:0] o_pcie_data_size,
output [31:0] o_pcie_data_address,
output o_pcie_data_fifo_flg,
output o_pcie_data_read_flg,
output o_pcie_data_write_flg,
input i_pcie_interrupt_stb,
input [31:0] i_pcie_interrupt_value,
input i_pcie_data_clk,
output o_pcie_ingress_fifo_rdy,
input i_pcie_ingress_fifo_act,
output [23:0] o_pcie_ingress_fifo_size,
input i_pcie_ingress_fifo_stb,
output [31:0] o_pcie_ingress_fifo_data,
output o_pcie_ingress_fifo_idle,
output [1:0] o_pcie_egress_fifo_rdy,
input [1:0] i_pcie_egress_fifo_act,
output [23:0] o_pcie_egress_fifo_size,
input i_pcie_egress_fifo_stb,
input [31:0] i_pcie_egress_fifo_data,
//DEBUG
output [3:0] o_sm_state,
// Tx
output o_pcie_exp_tx_p,
output o_pcie_exp_tx_n,
// Rx
input i_pcie_exp_rx_p,
input i_pcie_exp_rx_n,
input i_pcie_clk_p,
input i_pcie_clk_n,
//PCIE Control
input i_pcie_reset_n,
// output o_pcie_wake_n,
input i_pcie_wake_n,
output o_lax_clk,
output [31:0] o_debug,
output o_pcie_clkreq,
output reg o_wbs_int
);
//Local Parameters
localparam CONTROL = 32'h00;
localparam STATUS = 32'h01;
//Local Registers/Wires
wire w_sys_rst;
wire w_user_link_up;
wire w_user_reset_out;
/*
wire [15:0] w_cfg_status;
wire [15:0] w_cfg_command;
wire [15:0] w_cfg_dstatus;
wire [15:0] w_cfg_dcommand;
wire [15:0] w_cfg_lstatus;
wire [15:0] w_cfg_lcommand;
wire [15:0] w_cfg_dcommand2;
wire [2:0] w_cfg_pcie_link_state;
*/
wire [5:0] w_pl_ltssm_state;
wire w_clock_locked;
wire o_clk_in_stopped;
wire [2:0] pipe_rx0_status_gt;
wire pipe_rx0_phy_status_gt;
wire [3:0] w_tx_diff_ctr;
wire w_pl_sel_lnk_rate;
wire [1:0] w_pl_sel_lnk_width;
wire [2:0] w_pl_initial_link_width;
wire [15:0] w_rx_data;
wire [1:0] w_rx_data_k;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
wire w_master_ready;
wire w_in_ready;
wire [31:0] w_in_command;
wire [31:0] w_in_address;
wire [31:0] w_in_data;
wire [27:0] w_in_data_count;
wire w_out_ready;
wire w_ih_reset;
wire [31:0] w_id_value;
wire [31:0] w_command_value;
wire [31:0] w_count_value;
wire [31:0] w_address_value;
wire [63:0] m64_axis_rx_tdata;
wire [7:0] m64_axis_rx_tkeep;
wire m64_axis_rx_tlast;
wire m64_axis_rx_tvalid;
wire m64_axis_rx_tready;
wire [21:0] m_axis_rx_tuser;
wire [31:0] m32_axis_rx_tdata;
wire [3:0] m32_axis_rx_tkeep;
wire m32_axis_rx_tlast;
wire m32_axis_rx_tvalid;
wire m32_axis_rx_tready;
wire s64_axis_tx_tready;
wire [63:0] s64_axis_tx_tdata;
wire [7:0] s64_axis_tx_tkeep;
wire s64_axis_tx_tlast;
wire s64_axis_tx_tvalid;
wire s32_axis_tx_tready;
wire [31:0] s32_axis_tx_tdata;
wire [3:0] s32_axis_tx_tkeep;
wire s32_axis_tx_tlast;
wire s32_axis_tx_tvalid;
wire [3:0] ingress_state;
wire [3:0] controller_state;
//Submodules
tx1_pcie_adapter pcie_adapter (
.clk (clk ),
.rst (rst ),
.o_user_link_up (w_user_link_up ),
.o_sys_rst (w_sys_rst ),
/******************************************
* Debug Interface *
******************************************/
.o_lax_clk (w_lax_clk ),
.o_user_reset_out (w_user_reset_out ),
.o_pl_ltssm_state (w_pl_ltssm_state ),
.pipe_rx0_status_gt (pipe_rx0_status_gt ),
.pipe_rx0_phy_status_gt (pipe_rx0_phy_status_gt ),
.o_clock_locked (w_clock_locked ),
.o_clk_in_stopped (o_clk_in_stopped ),
.i_tx_diff_ctr (w_tx_diff_ctr ),
.o_pl_sel_lnk_rate (w_pl_sel_lnk_rate ),
.o_pl_sel_lnk_width (w_pl_sel_lnk_width ),
.o_pl_initial_link_width (w_pl_initial_link_width ),
/*
.o_cfg_status (w_cfg_status ),
.o_cfg_command (w_cfg_command ),
.o_cfg_dstatus (w_cfg_dstatus ),
.o_cfg_dcommand (w_cfg_dcommand ),
.o_cfg_lstatus (w_cfg_lstatus ),
.o_cfg_lcommand (w_cfg_lcommand ),
.o_cfg_dcommand2 (w_cfg_dcommand2 ),
.o_cfg_pcie_link_state (w_cfg_pcie_link_state ),
*/
.m64_axis_rx_tdata (m64_axis_rx_tdata ),
.m64_axis_rx_tkeep (m64_axis_rx_tkeep ),
.m64_axis_rx_tlast (m64_axis_rx_tlast ),
.m64_axis_rx_tvalid (m64_axis_rx_tvalid ),
.m64_axis_rx_tready (m64_axis_rx_tready ),
.m_axis_rx_tuser (maxis_rx_tuser ),
.m32_axis_rx_tdata (m32_axis_rx_tdata ),
.m32_axis_rx_tkeep (m32_axis_rx_tkeep ),
.m32_axis_rx_tlast (m32_axis_rx_tlast ),
.m32_axis_rx_tvalid (m32_axis_rx_tvalid ),
.m32_axis_rx_tready (m32_axis_rx_tready ),
.s64_axis_tx_tdata (s64_axis_tx_tdata ),
.s64_axis_tx_tkeep (s64_axis_tx_tkeep ),
.s64_axis_tx_tlast (s64_axis_tx_tlast ),
.s64_axis_tx_tvalid (s64_axis_tx_tvalid ),
.s64_axis_tx_tready (s64_axis_tx_tready ),
.s32_axis_tx_tdata (s32_axis_tx_tdata ),
.s32_axis_tx_tkeep (s32_axis_tx_tkeep ),
.s32_axis_tx_tlast (s32_axis_tx_tlast ),
.s32_axis_tx_tvalid (s32_axis_tx_tvalid ),
.s32_axis_tx_tready (s32_axis_tx_tready ),
.o_ingress_state (ingress_state ),
.o_controller_state (controller_state ),
/******************************************
* PCIE Phy Interface *
******************************************/
// Tx
.o_pcie_exp_tx_p (o_pcie_exp_tx_p ),
.o_pcie_exp_tx_n (o_pcie_exp_tx_n ),
// Rx
.i_pcie_exp_rx_p (i_pcie_exp_rx_p ),
.i_pcie_exp_rx_n (i_pcie_exp_rx_n ),
.i_pcie_clk_p (i_pcie_clk_p ),
.i_pcie_clk_n (i_pcie_clk_n ),
.o_rx_data (w_rx_data ),
.o_rx_data_k (w_rx_data_k ),
.o_rx_byte_is_comma (w_rx_byte_is_comma ),
.o_rx_byte_is_aligned (w_rx_byte_is_aligned ),
//PCIE Control control
.i_pcie_reset_n (i_pcie_reset_n ),
.o_pcie_clkreq (o_pcie_clkreq ),
/******************************************
* Host Interface *
******************************************/
.o_per_fifo_sel (o_pcie_per_fifo_sel ),
.o_mem_fifo_sel (o_pcie_mem_fifo_sel ),
.o_dma_fifo_sel (o_pcie_dma_fifo_sel ),
.i_write_fin (i_pcie_write_fin ),
.i_read_fin (i_pcie_read_fin ),
.o_data_size (o_pcie_data_size ),
.o_data_address (o_pcie_data_address ),
.o_data_fifo_flg (o_pcie_data_fifo_flg ),
.o_data_read_flg (o_pcie_data_read_flg ),
.o_data_write_flg (o_pcie_data_write_flg ),
.i_usr_interrupt_stb (i_pcie_interrupt ),
.i_usr_interrupt_value (i_pcie_interrupt_value ),
//Ingress FIFO
.i_data_clk (i_pcie_data_clk ),
.o_ingress_fifo_rdy (o_pcie_ingress_fifo_rdy ),
.i_ingress_fifo_act (i_pcie_ingress_fifo_act ),
.o_ingress_fifo_size (o_pcie_ingress_fifo_size ),
.i_ingress_fifo_stb (i_pcie_ingress_fifo_stb ),
.o_ingress_fifo_data (o_pcie_ingress_fifo_data ),
.o_ingress_fifo_idle (o_pcie_ingress_fifo_idle ),
//Egress FIFO
.o_egress_fifo_rdy (o_pcie_egress_fifo_rdy ),
.i_egress_fifo_act (i_pcie_egress_fifo_act ),
.o_egress_fifo_size (o_pcie_egress_fifo_size ),
.i_egress_fifo_stb (i_pcie_egress_fifo_stb ),
.i_egress_fifo_data (i_pcie_egress_fifo_data )
);
assign o_lax_clk = w_lax_clk;
//Asynchronous Logic
/*
//LINKUP Debug
assign o_debug[15:0] = w_rx_data;
assign o_debug[17:16] = w_rx_data_k;
assign o_debug[20:18] = pipe_rx0_status_gt;
assign o_debug[21] = pipe_rx0_phy_status_gt;
assign o_debug[23:22] = w_rx_byte_is_comma;
assign o_debug[29:24] = w_pl_ltssm_state;
//assign o_debug[31:30] = w_rx_byte_is_aligned;
assign o_debug[30] = w_rx_byte_is_aligned;
assign o_debug[31] = w_clock_locked;
*/
/*
//PCIE Comm Incomming Debug
//assign o_debug[15:0] = m64_axis_rx_tdata[15:0];
assign o_debug[15:0] = m32_axis_rx_tdata[15:0];
assign o_debug[19:16] = m32_axis_rx_tkeep[3:0];
assign o_debug[20] = m32_axis_rx_tvalid;
assign o_debug[21] = m32_axis_rx_tready;
assign o_debug[22] = m32_axis_rx_tlast;
assign o_debug[23] = 1'b0;
assign o_debug[27:24] = ingress_state;
assign o_debug[31:28] = controller_state;
*/
/*
assign o_debug[28] = m32_axis_rx_tvalid;
assign o_debug[29] = m32_axis_rx_tready;
assign o_debug[30] = m32_axis_rx_tlast;
assign o_debug[31] = 1'b0;
*/
assign o_debug[15:0] = s64_axis_tx_tdata[15:0];
//assign o_debug[15:0] = s32_axis_tx_tdata[15:0];
assign o_debug[19:16] = s64_axis_tx_tkeep[3:0];
assign o_debug[20] = s64_axis_tx_tvalid;
assign o_debug[21] = s64_axis_tx_tready;
assign o_debug[22] = s64_axis_tx_tlast;
assign o_debug[23] = 1'b0;
assign o_debug[27:24] = ingress_state;
assign o_debug[31:28] = controller_state;
//assign o_pcie_reset = w_user_reset_out;
assign o_pcie_reset = w_sys_rst;
assign w_tx_diff_ctr = 4'hC;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
CONTROL: begin
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
//add as many ADDR_X you need here
default: begin
end
endcase
o_wbs_ack <= 1;
end
else begin
//read request
case (i_wbs_adr)
CONTROL: begin
o_wbs_dat <= 0;
end
STATUS: begin
o_wbs_dat <= 0;
end
default: begin
end
endcase
o_wbs_ack <= 1;
end
end
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2I_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__MUX2I_FUNCTIONAL_PP_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_lp__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_lp__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2I_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLYMETAL6S2S_PP_BLACKBOX_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlymetal6s2s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0P_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__INPUTISO0P_BEHAVIORAL_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__inputiso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0P_BEHAVIORAL_V |
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : md_ram.v
// Author : Yanheng Lu
// Created : 2014-09-01
// Description : mode decision(pre_intra) 8x8 ram
//------------------------------------------------------------------
module md_ram (
clk ,
wdata ,
waddr ,
we ,
rd ,
raddr ,
rdata
);
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk ;
input [31:0] wdata ;
input [3:0] waddr ;
input we ;
input rd ;
input [3:0] raddr ;
output [31:0] rdata ;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
rf_2p #(.Addr_Width(4), .Word_Width(32))
rf_2p_32x16 (
.clka ( clk ),
.cena_i ( ~rd ),
.addra_i ( raddr ),
.dataa_o ( rdata ),
.clkb ( clk ),
.cenb_i ( ~we ),
.wenb_i ( ~we ),
.addrb_i ( waddr ),
.datab_i ( wdata )
);
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04:39:25 07/25/2015
// Design Name:
// Module Name: tld_sam
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tld_sam (
input wire clk50mhz,
// Audio I/O
input wire ear,
output wire audio_out_left,
output wire audio_out_right,
// Video output
inout wire [2:0] r,
inout wire [2:0] g,
inout wire [2:0] b,
inout wire hsync,
inout wire vsync,
output wire [2:0] dr,
output wire [2:0] dg,
output wire [2:0] db,
output wire dhsync,
output wire dvsync,
output wire stdn,
output wire stdnb,
// SRAM interface
output wire [20:0] sram_addr,
inout wire [7:0] sram_data,
output wire sram_we_n,
// PS/2 keyoard interface
inout wire clkps2,
inout wire dataps2
);
// Interface with RAM
wire [18:0] sram_addr_from_sam;
wire sram_we_n_from_sam;
// Audio and video
wire [1:0] sam_r, sam_g, sam_b;
wire sam_bright;
// scandoubler
wire hsync_pal, vsync_pal;
wire [2:0] ri = {sam_r, sam_bright};
wire [2:0] gi = {sam_g, sam_bright};
wire [2:0] bi = {sam_b, sam_bright};
assign dr = r;
assign dg = g;
assign db = b;
assign dhsync = hsync;
assign dvsync = vsync;
assign stdn = 1'b0; // fijar norma PAL
assign stdnb = 1'b1; // y conectamos reloj PAL
wire clk24, clk12, clk6, clk8;
reg [7:0] poweron_reset = 8'h00;
reg [1:0] scandoubler_ctrl = 2'b00;
always @(posedge clk6) begin
poweron_reset <= {poweron_reset[6:0], 1'b1};
if (poweron_reset[6] == 1'b0)
scandoubler_ctrl <= sram_data[1:0];
end
assign sram_addr = (poweron_reset[7] == 1'b0)? 21'h008FD5 : {2'b00, sram_addr_from_sam};
assign sram_we_n = (poweron_reset[7] == 1'b0)? 1'b1 : sram_we_n_from_sam;
relojes los_relojes (
.CLK_IN1 (clk50mhz), // IN
// Clock out ports
.CLK_OUT1 (clk24), // modulo multiplexor de SRAM
.CLK_OUT2 (clk12), // ASIC
.CLK_OUT3 (clk6), // CPU y teclado PS/2
.CLK_OUT4 (clk8) // SAA1099 y DAC
);
samcoupe maquina (
.clk24(clk24),
.clk12(clk12),
.clk6(clk6),
.clk8(clk8),
.master_reset_n(poweron_reset[7]),
// Video output
.r(sam_r),
.g(sam_g),
.b(sam_b),
.bright(sam_bright),
.hsync_pal(hsync_pal),
.vsync_pal(vsync_pal),
// Audio output
.ear(~ear),
.audio_out_left(audio_out_left),
.audio_out_right(audio_out_right),
// PS/2 keyboard
.clkps2(clkps2),
.dataps2(dataps2),
// SRAM external interface
.sram_addr(sram_addr_from_sam),
.sram_data(sram_data),
.sram_we_n(sram_we_n_from_sam)
);
vga_scandoubler #(.CLKVIDEO(12000)) salida_vga (
.clkvideo(clk12),
.clkvga(clk24),
.enable_scandoubling(scandoubler_ctrl[0]),
.disable_scaneffect(~scandoubler_ctrl[1]),
.ri(ri),
.gi(gi),
.bi(bi),
.hsync_ext_n(hsync_pal),
.vsync_ext_n(vsync_pal),
.ro(r),
.go(g),
.bo(b),
.hsync(hsync),
.vsync(vsync)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NAND4BB_BEHAVIORAL_PP_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4BB_BEHAVIORAL_PP_V |
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: stratix3_pmem.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module stratix3_pmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [11:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0]
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stratix3_pmem_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1 ns / 1 ps
module axis_delay #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer CNTR_WIDTH = 32
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [CNTR_WIDTH-1:0] cfg_data,
input wire [CNTR_WIDTH-1:0] axis_data_count,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
// Slave side
output wire s_axis_fifo_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_fifo_tdata,
input wire s_axis_fifo_tvalid,
// Master side
input wire m_axis_fifo_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_fifo_tdata,
output wire m_axis_fifo_tvalid
);
reg int_enbl_reg, int_enbl_next;
wire int_comp_wire;
assign int_comp_wire = axis_data_count > cfg_data;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_enbl_reg <= 1'b0;
end
else
begin
int_enbl_reg <= int_enbl_next;
end
end
always @*
begin
int_enbl_next = int_enbl_reg;
if( ~int_enbl_reg & int_comp_wire)
begin
int_enbl_next = 1'b1;
end
end
assign m_axis_fifo_tvalid = s_axis_tvalid;
assign s_axis_tready = m_axis_fifo_tready;
assign m_axis_tvalid = int_enbl_reg ? s_axis_fifo_tvalid : s_axis_tvalid;
assign s_axis_fifo_tready = int_enbl_reg ? m_axis_tready : 1'b0;
assign m_axis_fifo_tdata=s_axis_tdata;
assign m_axis_tdata=s_axis_fifo_tdata;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_PP_SYMBOL_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbufhv2hv_hl (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input LOWHVPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_PP_SYMBOL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_fft_win (
clk,
// adc data input
adc_valid,
adc_data,
adc_last,
adc_ready,
// windowed output
win_valid,
win_data,
win_last,
win_ready,
// window phase increment
win_incr,
win_enable);
input clk;
// adc data input
input adc_valid;
input [15:0] adc_data;
input adc_last;
output adc_ready;
// windowed output
output win_valid;
output [15:0] win_data;
output win_last;
input win_ready;
// window phase increment
input [15:0] win_incr;
input win_enable;
// internal registers
reg [15:0] win_angle = 'd0;
reg win_valid_s1 = 'd0;
reg win_last_s1 = 'd0;
reg win_data_sign_s1 = 'd0;
reg [15:0] win_data_s1 = 'd0;
reg win_cos_sign_s1 = 'd0;
reg [15:0] win_cos_data_s1_sub = 'd0;
reg [15:0] win_cos_data_s1_add = 'd0;
reg win_valid_s2 = 'd0;
reg win_last_s2 = 'd0;
reg win_data_sign_s2 = 'd0;
reg [14:0] win_data_s2 = 'd0;
reg [14:0] win_cos_data_s2 = 'd0;
reg win_valid_s3 = 'd0;
reg win_last_s3 = 'd0;
reg [15:0] win_data_s3 = 'd0;
reg mwr = 'd0;
reg [16:0] mwdata = 'd0;
reg [ 5:0] mwaddr = 'd0;
reg [ 5:0] maddrdiff = 'd0;
reg adc_ready = 'd0;
reg [ 5:0] mraddr = 'd0;
reg mrd = 'd0;
reg mrvalid = 'd0;
reg [16:0] mrdata = 'd0;
reg [ 1:0] mwcnt = 'd0;
reg mvalid_0 = 'd0;
reg [16:0] mdata_0 = 'd0;
reg mvalid_1 = 'd0;
reg [16:0] mdata_1 = 'd0;
reg mvalid_2 = 'd0;
reg [16:0] mdata_2 = 'd0;
reg mvalid_3 = 'd0;
reg [16:0] mdata_3 = 'd0;
reg [ 1:0] mrcnt = 'd0;
reg win_valid = 'd0;
reg [15:0] win_data = 'd0;
reg win_last = 'd0;
// internal signals
wire [15:0] win_cos_s1_s;
wire win_valid_s1_s;
wire win_last_s1_s;
wire [15:0] win_data_s1_s;
wire [31:0] win_data_s3_s;
wire win_sign_s3_s;
wire win_valid_s3_s;
wire win_last_s3_s;
wire mrd_s;
wire [ 6:0] maddrdiff_s;
wire mxfer_s;
wire [16:0] mrdata_s;
// the window is generated from a sine function, to get the cos you need to add 90deg == (pi)/4
always @(posedge clk) begin
if (adc_valid == 1'b1) begin
win_angle <= win_angle + win_incr;
end else if (win_enable == 1'b0) begin
win_angle <= 16'h4000;
end
end
// the sine function actually generates cosine (because of the pi/4 addition above)
ad_sine #(.DELAY_DATA_WIDTH(18)) i_cos (
.clk (clk),
.angle (win_angle),
.sine (win_cos_s1_s),
.ddata_in ({adc_valid, adc_last, adc_data}),
.ddata_out ({win_valid_s1_s, win_last_s1_s, win_data_s1_s}));
// get 0.5*(1 - cos(a)), the output is +ve (because mag(cos(a)) is less than 1.
always @(posedge clk) begin
win_valid_s1 <= win_valid_s1_s;
win_last_s1 <= win_last_s1_s;
win_data_sign_s1 <= win_data_s1_s[15];
if (win_data_s1_s[15] == 1'b1) begin
win_data_s1 <= ~win_data_s1_s + 1'b1;
end else begin
win_data_s1 <= win_data_s1_s;
end
win_cos_sign_s1 <= win_cos_s1_s[15];
win_cos_data_s1_sub <= 16'h7fff - win_cos_s1_s[14:0];
win_cos_data_s1_add <= 16'h7fff + win_cos_s1_s[14:0];
win_valid_s2 <= win_valid_s1;
win_last_s2 <= win_last_s1;
win_data_sign_s2 <= win_data_sign_s1;
win_data_s2 <= win_data_s1[14:0];
if (win_cos_sign_s1 == 1'b1) begin
win_cos_data_s2 <= win_cos_data_s1_add[15:1];
end else begin
win_cos_data_s2 <= win_cos_data_s1_sub[15:1];
end
end
// apply the window function
mul_u16 #(.DELAY_DATA_WIDTH(3)) i_mul (
.clk (clk),
.data_a ({1'b0, win_data_s2}),
.data_b ({1'b0, win_cos_data_s2}),
.data_p (win_data_s3_s),
.ddata_in ({win_data_sign_s2, win_valid_s2, win_last_s2}),
.ddata_out ({win_sign_s3_s, win_valid_s3_s, win_last_s3_s}));
// get the 2's compl and pass the data to memory
always @(posedge clk) begin
win_valid_s3 <= win_valid_s3_s;
win_last_s3 <= win_last_s3_s;
if (win_sign_s3_s == 1'b1) begin
win_data_s3 <= ~win_data_s3_s[30:15] + 1'b1;
end else begin
win_data_s3 <= win_data_s3_s[30:15];
end
end
// the memory is used to account for the "back pressure" from the fft module
always @(posedge clk) begin
if (win_enable == 1'b1) begin
mwr <= win_valid_s3;
mwdata <= {win_last_s3, win_data_s3};
end else begin
mwr <= adc_valid;
mwdata <= {adc_last, adc_data};
end
if (mwr == 1'b1) begin
mwaddr <= mwaddr + 1'b1;
end
end
mem #(.ADDR_WIDTH(6), .DATA_WIDTH(17)) i_mem (
.clka (clk),
.wea (mwr),
.addra (mwaddr),
.dina (mwdata),
.clkb (clk),
.addrb (mraddr),
.doutb (mrdata_s));
// read from meory and pass it to the FFT module
assign mrd_s = (mwaddr == mraddr) ? 1'b0 : win_ready;
assign maddrdiff_s = {1'b1, mwaddr} - mraddr;
assign mxfer_s = win_ready | ~win_valid;
always @(posedge clk) begin
maddrdiff <= maddrdiff_s[5:0];
if (maddrdiff >= 32) begin
adc_ready <= 1'b0;
end else if (maddrdiff <= 20) begin
adc_ready <= 1'b1;
end
end
// read and address update
always @(posedge clk) begin
if (mrd_s == 1'b1) begin
mraddr <= mraddr + 1'b1;
end
mrd <= mrd_s;
mrvalid <= mrd;
mrdata <= mrdata_s;
end
// hold data during sudden death (ready de-asserted!)
always @(posedge clk) begin
if (mrvalid == 1'b1) begin
mwcnt <= mwcnt + 1'b1;
end
if ((mwcnt == 2'd0) && (mrvalid == 1'b1)) begin
mvalid_0 <= 1'b1;
mdata_0 <= mrdata;
end else if ((mrcnt == 2'd0) && (mxfer_s == 1'b1)) begin
mvalid_0 <= 1'b0;
mdata_0 <= 17'd0;
end
if ((mwcnt == 2'd1) && (mrvalid == 1'b1)) begin
mvalid_1 <= 1'b1;
mdata_1 <= mrdata;
end else if ((mrcnt == 2'd1) && (mxfer_s == 1'b1)) begin
mvalid_1 <= 1'b0;
mdata_1 <= 17'd0;
end
if ((mwcnt == 2'd2) && (mrvalid == 1'b1)) begin
mvalid_2 <= 1'b1;
mdata_2 <= mrdata;
end else if ((mrcnt == 2'd2) && (mxfer_s == 1'b1)) begin
mvalid_2 <= 1'b0;
mdata_2 <= 17'd0;
end
if ((mwcnt == 2'd3) && (mrvalid == 1'b1)) begin
mvalid_3 <= 1'b1;
mdata_3 <= mrdata;
end else if ((mrcnt == 2'd3) && (mxfer_s == 1'b1)) begin
mvalid_3 <= 1'b0;
mdata_3 <= 17'd0;
end
if ((mrcnt != mwcnt) && (win_ready == 1'b1)) begin
mrcnt <= mrcnt + 1'b1;
end
if ((win_valid == 1'b0) || (win_ready == 1'b1)) begin
case (mrcnt)
2'd3: begin
win_valid <= mvalid_3;
win_data <= mdata_3[15:0];
win_last <= mdata_3[16] & mvalid_3;
end
2'd2: begin
win_valid <= mvalid_2;
win_data <= mdata_2[15:0];
win_last <= mdata_2[16] & mvalid_2;
end
2'd1: begin
win_valid <= mvalid_1;
win_data <= mdata_1[15:0];
win_last <= mdata_1[16] & mvalid_1;
end
default: begin
win_valid <= mvalid_0;
win_data <= mdata_0[15:0];
win_last <= mdata_0[16] & mvalid_0;
end
endcase
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S50KAPWR_SYMBOL_V
`define SKY130_FD_SC_LP__DLYBUF4S50KAPWR_SYMBOL_V
/**
* dlybuf4s50kapwr: Delay Buffer 4-stage 0.50um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s50kapwr (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S50KAPWR_SYMBOL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_128_if.v
// Version : 1.7
`timescale 1ps/1ps
module pcie_128_if #(
parameter TCQ = 100
)(
input rst_n_250,
input rst_n_500,
output [6:0] trn_rbar_hit_n_o,
output [127:0] trn_rd_o,
output trn_recrc_err_n_o,
output trn_rsof_n_o,
output trn_reof_n_o,
output trn_rerrfwd_n_o,
output [1:0] trn_rrem_n_o,
output trn_rsrc_dsc_n_o,
output trn_rsrc_rdy_n_o,
input trn_rdst_rdy_n_i,
input trn_rnpok_n_i,
output [5:0] trn_tbuf_av_o,
output trn_tdst_rdy_n_o,
output trn_terr_drop_n_o,
input [127:0] trn_td_i,
input trn_tecrc_gen_n_i,
input trn_terr_fwd_n_i,
input [1:0] trn_trem_n_i,
input trn_tsof_n_i,
input trn_teof_n_i,
input trn_tsrc_dsc_n_i,
input trn_tsrc_rdy_n_i,
input trn_tstr_n_i,
output [11:0] trn_fc_cpld_o,
output [7:0] trn_fc_cplh_o,
output [11:0] trn_fc_npd_o,
output [7:0] trn_fc_nph_o,
output [11:0] trn_fc_pd_o,
output [7:0] trn_fc_ph_o,
input [2:0] trn_fc_sel_i,
input [6:0] TRNRBARHITN_i,
input [63:0] TRNRD_i,
input TRNRECRCERRN_i,
input TRNRSOFN_i,
input TRNREOFN_i,
input TRNRERRFWDN_i,
input TRNRREMN_i,
input TRNRSRCDSCN_i,
input TRNRSRCRDYN_i,
output TRNRDSTRDYN_o,
output TRNRNPOKN_o,
input [5:0] TRNTBUFAV_i,
input TRNTCFGREQN_i,
input TRNTDSTRDYN_i,
input TRNTERRDROPN_i,
output TRNTCFGGNTN_o,
output [63:0] TRNTD_o,
output TRNTECRCGENN_o,
output TRNTERRFWDN_o,
output TRNTREMN_o,
output TRNTSOFN_o,
output TRNTEOFN_o,
output TRNTSRCDSCN_o,
output TRNTSRCRDYN_o,
output TRNTSTRN_o,
input [11:0] TRNFCCPLD_i,
input [7:0] TRNFCCPLH_i,
input [11:0] TRNFCNPD_i,
input [7:0] TRNFCNPH_i,
input [11:0] TRNFCPD_i,
input [7:0] TRNFCPH_i,
output [2:0] TRNFCSEL_o,
//--------------------------------------
input BLOCKCLK,
input USERCLK,
input CFGCOMMANDBUSMASTERENABLE_i,
input CFGCOMMANDINTERRUPTDISABLE_i,
input CFGCOMMANDIOENABLE_i,
input CFGCOMMANDMEMENABLE_i,
input CFGCOMMANDSERREN_i,
input CFGDEVCONTROLAUXPOWEREN_i,
input CFGDEVCONTROLCORRERRREPORTINGEN_i,
input CFGDEVCONTROLENABLERO_i,
input CFGDEVCONTROLEXTTAGEN_i,
input CFGDEVCONTROLFATALERRREPORTINGEN_i,
input [2:0] CFGDEVCONTROLMAXPAYLOAD_i,
input [2:0] CFGDEVCONTROLMAXREADREQ_i,
input CFGDEVCONTROLNONFATALREPORTINGEN_i,
input CFGDEVCONTROLNOSNOOPEN_i,
input CFGDEVCONTROLPHANTOMEN_i,
input CFGDEVCONTROLURERRREPORTINGEN_i,
input CFGDEVCONTROL2CPLTIMEOUTDIS_i,
input [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL_i,
input CFGDEVSTATUSCORRERRDETECTED_i,
input CFGDEVSTATUSFATALERRDETECTED_i,
input CFGDEVSTATUSNONFATALERRDETECTED_i,
input CFGDEVSTATUSURDETECTED_i,
input [31:0] CFGDO_i,
input CFGERRCPLRDYN_i,
input [7:0] CFGINTERRUPTDO_i,
input [2:0] CFGINTERRUPTMMENABLE_i,
input CFGINTERRUPTMSIENABLE_i,
input CFGINTERRUPTMSIXENABLE_i,
input CFGINTERRUPTMSIXFM_i,
input CFGINTERRUPTRDYN_i,
input CFGLINKCONTROLRCB_i,
input [1:0] CFGLINKCONTROLASPMCONTROL_i,
input CFGLINKCONTROLAUTOBANDWIDTHINTEN_i,
input CFGLINKCONTROLBANDWIDTHINTEN_i,
input CFGLINKCONTROLCLOCKPMEN_i,
input CFGLINKCONTROLCOMMONCLOCK_i,
input CFGLINKCONTROLEXTENDEDSYNC_i,
input CFGLINKCONTROLHWAUTOWIDTHDIS_i,
input CFGLINKCONTROLLINKDISABLE_i,
input CFGLINKCONTROLRETRAINLINK_i,
input CFGLINKSTATUSAUTOBANDWIDTHSTATUS_i,
input CFGLINKSTATUSBANDWITHSTATUS_i,
input [1:0] CFGLINKSTATUSCURRENTSPEED_i,
input CFGLINKSTATUSDLLACTIVE_i,
input CFGLINKSTATUSLINKTRAINING_i,
input [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH_i,
input [15:0] CFGMSGDATA_i,
input CFGMSGRECEIVED_i,
input CFGMSGRECEIVEDPMETO_i,
input [2:0] CFGPCIELINKSTATE_i,
input CFGPMCSRPMEEN_i,
input CFGPMCSRPMESTATUS_i,
input [1:0] CFGPMCSRPOWERSTATE_i,
input CFGRDWRDONEN_i,
input CFGMSGRECEIVEDSETSLOTPOWERLIMIT_i,
input CFGMSGRECEIVEDUNLOCK_i,
input CFGMSGRECEIVEDPMASNAK_i,
input CFGPMRCVREQACKN_i,
input CFGTRANSACTION_i,
input [6:0] CFGTRANSACTIONADDR_i,
input CFGTRANSACTIONTYPE_i,
output [3:0] CFGBYTEENN_o,
output [31:0] CFGDI_o,
output [63:0] CFGDSN_o,
output [9:0] CFGDWADDR_o,
output CFGERRACSN_o,
output CFGERRCORN_o,
output CFGERRCPLABORTN_o,
output CFGERRCPLTIMEOUTN_o,
output CFGERRCPLUNEXPECTN_o,
output CFGERRECRCN_o,
output CFGERRLOCKEDN_o,
output CFGERRPOSTEDN_o,
output [47:0] CFGERRTLPCPLHEADER_o,
output CFGERRURN_o,
output CFGINTERRUPTASSERTN_o,
output [7:0] CFGINTERRUPTDI_o,
output CFGINTERRUPTN_o,
output CFGPMDIRECTASPML1N_o,
output CFGPMSENDPMACKN_o,
output CFGPMSENDPMETON_o,
output CFGPMSENDPMNAKN_o,
output CFGPMTURNOFFOKN_o,
output CFGPMWAKEN_o,
output [7:0] CFGPORTNUMBER_o,
output CFGRDENN_o,
output CFGTRNPENDINGN_o,
output CFGWRENN_o,
output CFGWRREADONLYN_o,
output CFGWRRW1CASRWN_o,
//--------------------------------------------------------
output CFGCOMMANDBUSMASTERENABLE_o,
output CFGCOMMANDINTERRUPTDISABLE_o,
output CFGCOMMANDIOENABLE_o,
output CFGCOMMANDMEMENABLE_o,
output CFGCOMMANDSERREN_o,
output CFGDEVCONTROLAUXPOWEREN_o,
output CFGDEVCONTROLCORRERRREPORTINGEN_o,
output CFGDEVCONTROLENABLERO_o,
output CFGDEVCONTROLEXTTAGEN_o,
output CFGDEVCONTROLFATALERRREPORTINGEN_o,
output [2:0] CFGDEVCONTROLMAXPAYLOAD_o,
output [2:0] CFGDEVCONTROLMAXREADREQ_o,
output CFGDEVCONTROLNONFATALREPORTINGEN_o,
output CFGDEVCONTROLNOSNOOPEN_o,
output CFGDEVCONTROLPHANTOMEN_o,
output CFGDEVCONTROLURERRREPORTINGEN_o,
output CFGDEVCONTROL2CPLTIMEOUTDIS_o,
output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL_o,
output CFGDEVSTATUSCORRERRDETECTED_o,
output CFGDEVSTATUSFATALERRDETECTED_o,
output CFGDEVSTATUSNONFATALERRDETECTED_o,
output CFGDEVSTATUSURDETECTED_o,
output [31:0] CFGDO_o,
output CFGERRCPLRDYN_o,
output [7:0] CFGINTERRUPTDO_o,
output [2:0] CFGINTERRUPTMMENABLE_o,
output CFGINTERRUPTMSIENABLE_o,
output CFGINTERRUPTMSIXENABLE_o,
output CFGINTERRUPTMSIXFM_o,
output CFGINTERRUPTRDYN_o,
output CFGLINKCONTROLRCB_o,
output [1:0] CFGLINKCONTROLASPMCONTROL_o,
output CFGLINKCONTROLAUTOBANDWIDTHINTEN_o,
output CFGLINKCONTROLBANDWIDTHINTEN_o,
output CFGLINKCONTROLCLOCKPMEN_o,
output CFGLINKCONTROLCOMMONCLOCK_o,
output CFGLINKCONTROLEXTENDEDSYNC_o,
output CFGLINKCONTROLHWAUTOWIDTHDIS_o,
output CFGLINKCONTROLLINKDISABLE_o,
output CFGLINKCONTROLRETRAINLINK_o,
output CFGLINKSTATUSAUTOBANDWIDTHSTATUS_o,
output CFGLINKSTATUSBANDWITHSTATUS_o,
output [1:0] CFGLINKSTATUSCURRENTSPEED_o,
output CFGLINKSTATUSDLLACTIVE_o,
output CFGLINKSTATUSLINKTRAINING_o,
output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH_o,
output [15:0] CFGMSGDATA_o,
output CFGMSGRECEIVED_o,
output CFGMSGRECEIVEDPMETO_o,
output [2:0] CFGPCIELINKSTATE_o,
output CFGPMCSRPMEEN_o,
output CFGPMCSRPMESTATUS_o,
output [1:0] CFGPMCSRPOWERSTATE_o,
output CFGRDWRDONEN_o,
output CFGMSGRECEIVEDSETSLOTPOWERLIMIT_o,
output CFGMSGRECEIVEDUNLOCK_o,
output CFGMSGRECEIVEDPMASNAK_o,
output CFGPMRCVREQACKN_o,
output CFGTRANSACTION_o,
output [6:0] CFGTRANSACTIONADDR_o,
output CFGTRANSACTIONTYPE_o,
input [3:0] CFGBYTEENN_i,
input [31:0] CFGDI_i,
input [63:0] CFGDSN_i,
input [9:0] CFGDWADDR_i,
input CFGERRACSN_i,
input CFGERRCORN_i,
input CFGERRCPLABORTN_i,
input CFGERRCPLTIMEOUTN_i,
input CFGERRCPLUNEXPECTN_i,
input CFGERRECRCN_i,
input CFGERRLOCKEDN_i,
input CFGERRPOSTEDN_i,
input [47:0] CFGERRTLPCPLHEADER_i,
input CFGERRURN_i,
input CFGINTERRUPTASSERTN_i,
input [7:0] CFGINTERRUPTDI_i,
input CFGINTERRUPTN_i,
input CFGPMDIRECTASPML1N_i,
input CFGPMSENDPMACKN_i,
input CFGPMSENDPMETON_i,
input CFGPMSENDPMNAKN_i,
input CFGPMTURNOFFOKN_i,
input CFGPMWAKEN_i,
input [7:0] CFGPORTNUMBER_i,
input CFGRDENN_i,
input CFGTRNPENDINGN_i,
input CFGWRENN_i,
input CFGWRREADONLYN_i,
input CFGWRRW1CASRWN_i
);
pcie_trn_128 #(
.TCQ ( TCQ )
) pcie_trn_128_i (
.user_clk ( USERCLK ),
.block_clk ( BLOCKCLK ),
.rst_n_250 ( rst_n_250 ),
.rst_n_500 ( rst_n_500 ),
`ifdef SILICON_1_0
.cfgpmcsrpowerstate ( 2'h0 ),
`else
.cfgpmcsrpowerstate ( CFGPMCSRPOWERSTATE_o ),
`endif
//////////////////
// to/from user //
//////////////////
.trn_rbar_hit_n_o( trn_rbar_hit_n_o ),
.trn_rd_o( trn_rd_o ),
.trn_recrc_err_n_o( trn_recrc_err_n_o ),
.trn_rsof_n_o( trn_rsof_n_o ),
.trn_reof_n_o( trn_reof_n_o ),
.trn_rerrfwd_n_o( trn_rerrfwd_n_o ),
.trn_rrem_n_o( trn_rrem_n_o ),
.trn_rsrc_dsc_n_o( trn_rsrc_dsc_n_o ),
.trn_rsrc_rdy_n_o( trn_rsrc_rdy_n_o ),
.trn_rdst_rdy_n_i( trn_rdst_rdy_n_i ),
.trn_rnpok_n_i( trn_rnpok_n_i ),
.trn_tbuf_av_o( trn_tbuf_av_o ),
.trn_tdst_rdy_n_o( trn_tdst_rdy_n_o ),
.trn_terr_drop_n_o( trn_terr_drop_n_o ),
.trn_td_i( trn_td_i ),
.trn_tecrc_gen_n_i( trn_tecrc_gen_n_i ),
.trn_terr_fwd_n_i( trn_terr_fwd_n_i ),
.trn_trem_n_i( trn_trem_n_i ),
.trn_tsof_n_i( trn_tsof_n_i ),
.trn_teof_n_i( trn_teof_n_i ),
.trn_tsrc_dsc_n_i( trn_tsrc_dsc_n_i ),
.trn_tsrc_rdy_n_i( trn_tsrc_rdy_n_i ),
.trn_tstr_n_i( trn_tstr_n_i ),
.trn_fc_cpld_o( trn_fc_cpld_o ),
.trn_fc_cplh_o( trn_fc_cplh_o ),
.trn_fc_npd_o( trn_fc_npd_o ),
.trn_fc_nph_o( trn_fc_nph_o ),
.trn_fc_pd_o( trn_fc_pd_o ),
.trn_fc_ph_o( trn_fc_ph_o ),
.trn_fc_sel_i( trn_fc_sel_i ),
////////////////
// to/from EP //
////////////////
.TRNRBARHITN_i( TRNRBARHITN_i ),
.TRNRD_i( TRNRD_i ),
.TRNRECRCERRN_i( TRNRECRCERRN_i ),
.TRNRSOFN_i( TRNRSOFN_i ),
.TRNREOFN_i( TRNREOFN_i ),
.TRNRERRFWDN_i( TRNRERRFWDN_i ),
.TRNRREMN_i( TRNRREMN_i ),
.TRNRSRCDSCN_i( TRNRSRCDSCN_i ),
.TRNRSRCRDYN_i( TRNRSRCRDYN_i ),
.TRNRDSTRDYN_o( TRNRDSTRDYN_o ),
.TRNRNPOKN_o( TRNRNPOKN_o ),
.TRNTBUFAV_i( TRNTBUFAV_i ),
.TRNTCFGREQN_i( TRNTCFGREQN_i ),
.TRNTDSTRDYN_i( TRNTDSTRDYN_i ),
.TRNTERRDROPN_i( TRNTERRDROPN_i ),
.TRNTCFGGNTN_o( TRNTCFGGNTN_o ),
.TRNTD_o( TRNTD_o ),
.TRNTECRCGENN_o( TRNTECRCGENN_o ),
.TRNTERRFWDN_o( TRNTERRFWDN_o ),
.TRNTREMN_o( TRNTREMN_o ),
.TRNTSOFN_o( TRNTSOFN_o ),
.TRNTEOFN_o( TRNTEOFN_o ),
.TRNTSRCDSCN_o( TRNTSRCDSCN_o ),
.TRNTSRCRDYN_o( TRNTSRCRDYN_o ),
.TRNTSTRN_o( TRNTSTRN_o ),
.TRNFCCPLD_i( TRNFCCPLD_i ),
.TRNFCCPLH_i( TRNFCCPLH_i ),
.TRNFCNPD_i( TRNFCNPD_i ),
.TRNFCNPH_i( TRNFCNPH_i ),
.TRNFCPD_i( TRNFCPD_i ),
.TRNFCPH_i( TRNFCPH_i ),
.TRNFCSEL_o( TRNFCSEL_o )
);
pcie_cfg_128 #(
.TCQ( TCQ )
) pcie_cfg_128_i (
.user_clk ( USERCLK ),
.block_clk ( BLOCKCLK ),
.rst_n_500 ( rst_n_500 ),
.CFGCOMMANDBUSMASTERENABLE_i( CFGCOMMANDBUSMASTERENABLE_i ),
.CFGCOMMANDINTERRUPTDISABLE_i( CFGCOMMANDINTERRUPTDISABLE_i ),
.CFGCOMMANDIOENABLE_i( CFGCOMMANDIOENABLE_i ),
.CFGCOMMANDMEMENABLE_i( CFGCOMMANDMEMENABLE_i ),
.CFGCOMMANDSERREN_i( CFGCOMMANDSERREN_i ),
.CFGDEVCONTROLAUXPOWEREN_i( CFGDEVCONTROLAUXPOWEREN_i ),
.CFGDEVCONTROLCORRERRREPORTINGEN_i( CFGDEVCONTROLCORRERRREPORTINGEN_i ),
.CFGDEVCONTROLENABLERO_i( CFGDEVCONTROLENABLERO_i ),
.CFGDEVCONTROLEXTTAGEN_i( CFGDEVCONTROLEXTTAGEN_i ),
.CFGDEVCONTROLFATALERRREPORTINGEN_i( CFGDEVCONTROLFATALERRREPORTINGEN_i ),
.CFGDEVCONTROLMAXPAYLOAD_i( CFGDEVCONTROLMAXPAYLOAD_i ),
.CFGDEVCONTROLMAXREADREQ_i( CFGDEVCONTROLMAXREADREQ_i ),
.CFGDEVCONTROLNONFATALREPORTINGEN_i( CFGDEVCONTROLNONFATALREPORTINGEN_i ),
.CFGDEVCONTROLNOSNOOPEN_i( CFGDEVCONTROLNOSNOOPEN_i ),
.CFGDEVCONTROLPHANTOMEN_i( CFGDEVCONTROLPHANTOMEN_i ),
.CFGDEVCONTROLURERRREPORTINGEN_i( CFGDEVCONTROLURERRREPORTINGEN_i ),
.CFGDEVCONTROL2CPLTIMEOUTDIS_i( CFGDEVCONTROL2CPLTIMEOUTDIS_i ),
.CFGDEVCONTROL2CPLTIMEOUTVAL_i( CFGDEVCONTROL2CPLTIMEOUTVAL_i ),
.CFGDEVSTATUSCORRERRDETECTED_i( CFGDEVSTATUSCORRERRDETECTED_i ),
.CFGDEVSTATUSFATALERRDETECTED_i( CFGDEVSTATUSFATALERRDETECTED_i ),
.CFGDEVSTATUSNONFATALERRDETECTED_i( CFGDEVSTATUSNONFATALERRDETECTED_i ),
.CFGDEVSTATUSURDETECTED_i( CFGDEVSTATUSURDETECTED_i ),
.CFGDO_i( CFGDO_i ),
.CFGERRCPLRDYN_i( CFGERRCPLRDYN_i ),
.CFGINTERRUPTDO_i( CFGINTERRUPTDO_i ),
.CFGINTERRUPTMMENABLE_i( CFGINTERRUPTMMENABLE_i ),
.CFGINTERRUPTMSIENABLE_i( CFGINTERRUPTMSIENABLE_i ),
.CFGINTERRUPTMSIXENABLE_i( CFGINTERRUPTMSIXENABLE_i ),
.CFGINTERRUPTMSIXFM_i( CFGINTERRUPTMSIXFM_i ),
.CFGINTERRUPTRDYN_i( CFGINTERRUPTRDYN_i ),
.CFGLINKCONTROLRCB_i( CFGLINKCONTROLRCB_i ),
.CFGLINKCONTROLASPMCONTROL_i( CFGLINKCONTROLASPMCONTROL_i ),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN_i( CFGLINKCONTROLAUTOBANDWIDTHINTEN_i ),
.CFGLINKCONTROLBANDWIDTHINTEN_i( CFGLINKCONTROLBANDWIDTHINTEN_i ),
.CFGLINKCONTROLCLOCKPMEN_i( CFGLINKCONTROLCLOCKPMEN_i ),
.CFGLINKCONTROLCOMMONCLOCK_i( CFGLINKCONTROLCOMMONCLOCK_i ),
.CFGLINKCONTROLEXTENDEDSYNC_i( CFGLINKCONTROLEXTENDEDSYNC_i ),
.CFGLINKCONTROLHWAUTOWIDTHDIS_i( CFGLINKCONTROLHWAUTOWIDTHDIS_i ),
.CFGLINKCONTROLLINKDISABLE_i( CFGLINKCONTROLLINKDISABLE_i ),
.CFGLINKCONTROLRETRAINLINK_i( CFGLINKCONTROLRETRAINLINK_i ),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS_i( CFGLINKSTATUSAUTOBANDWIDTHSTATUS_i ),
.CFGLINKSTATUSBANDWITHSTATUS_i( CFGLINKSTATUSBANDWITHSTATUS_i ),
.CFGLINKSTATUSCURRENTSPEED_i( CFGLINKSTATUSCURRENTSPEED_i ),
.CFGLINKSTATUSDLLACTIVE_i( CFGLINKSTATUSDLLACTIVE_i ),
.CFGLINKSTATUSLINKTRAINING_i( CFGLINKSTATUSLINKTRAINING_i ),
.CFGLINKSTATUSNEGOTIATEDWIDTH_i( CFGLINKSTATUSNEGOTIATEDWIDTH_i ),
.CFGMSGDATA_i( CFGMSGDATA_i ),
.CFGMSGRECEIVED_i( CFGMSGRECEIVED_i ),
.CFGMSGRECEIVEDPMETO_i( CFGMSGRECEIVEDPMETO_i ),
.CFGPCIELINKSTATE_i( CFGPCIELINKSTATE_i ),
.CFGPMCSRPMEEN_i( CFGPMCSRPMEEN_i ),
.CFGPMCSRPMESTATUS_i( CFGPMCSRPMESTATUS_i ),
.CFGPMCSRPOWERSTATE_i( CFGPMCSRPOWERSTATE_i ),
.CFGRDWRDONEN_i( CFGRDWRDONEN_i ),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT_i( CFGMSGRECEIVEDSETSLOTPOWERLIMIT_i ),
.CFGMSGRECEIVEDUNLOCK_i( CFGMSGRECEIVEDUNLOCK_i ),
.CFGMSGRECEIVEDPMASNAK_i( CFGMSGRECEIVEDPMASNAK_i ),
.CFGPMRCVREQACKN_i( CFGPMRCVREQACKN_i ),
.CFGTRANSACTION_i( CFGTRANSACTION_i ),
.CFGTRANSACTIONADDR_i( CFGTRANSACTIONADDR_i ),
.CFGTRANSACTIONTYPE_i( CFGTRANSACTIONTYPE_i ),
.CFGBYTEENN_o( CFGBYTEENN_o ),
.CFGDI_o( CFGDI_o ),
.CFGDSN_o( CFGDSN_o ),
.CFGDWADDR_o( CFGDWADDR_o ),
.CFGERRACSN_o( CFGERRACSN_o ),
.CFGERRCORN_o( CFGERRCORN_o ),
.CFGERRCPLABORTN_o( CFGERRCPLABORTN_o ),
.CFGERRCPLTIMEOUTN_o( CFGERRCPLTIMEOUTN_o ),
.CFGERRCPLUNEXPECTN_o( CFGERRCPLUNEXPECTN_o ),
.CFGERRECRCN_o( CFGERRECRCN_o ),
.CFGERRLOCKEDN_o( CFGERRLOCKEDN_o ),
.CFGERRPOSTEDN_o( CFGERRPOSTEDN_o ),
.CFGERRTLPCPLHEADER_o( CFGERRTLPCPLHEADER_o ),
.CFGERRURN_o( CFGERRURN_o ),
.CFGINTERRUPTASSERTN_o( CFGINTERRUPTASSERTN_o ),
.CFGINTERRUPTDI_o( CFGINTERRUPTDI_o ),
.CFGINTERRUPTN_o( CFGINTERRUPTN_o ),
.CFGPMDIRECTASPML1N_o( CFGPMDIRECTASPML1N_o ),
.CFGPMSENDPMACKN_o( CFGPMSENDPMACKN_o ),
.CFGPMSENDPMETON_o( CFGPMSENDPMETON_o ),
.CFGPMSENDPMNAKN_o( CFGPMSENDPMNAKN_o ),
.CFGPMTURNOFFOKN_o( CFGPMTURNOFFOKN_o ),
.CFGPMWAKEN_o( CFGPMWAKEN_o ),
.CFGPORTNUMBER_o( CFGPORTNUMBER_o ),
.CFGRDENN_o( CFGRDENN_o ),
.CFGTRNPENDINGN_o( CFGTRNPENDINGN_o ),
.CFGWRENN_o( CFGWRENN_o ),
.CFGWRREADONLYN_o( CFGWRREADONLYN_o ),
.CFGWRRW1CASRWN_o( CFGWRRW1CASRWN_o ),
//------------------
.CFGCOMMANDBUSMASTERENABLE_o( CFGCOMMANDBUSMASTERENABLE_o ),
.CFGCOMMANDINTERRUPTDISABLE_o( CFGCOMMANDINTERRUPTDISABLE_o ),
.CFGCOMMANDIOENABLE_o( CFGCOMMANDIOENABLE_o ),
.CFGCOMMANDMEMENABLE_o( CFGCOMMANDMEMENABLE_o ),
.CFGCOMMANDSERREN_o( CFGCOMMANDSERREN_o ),
.CFGDEVCONTROLAUXPOWEREN_o( CFGDEVCONTROLAUXPOWEREN_o ),
.CFGDEVCONTROLCORRERRREPORTINGEN_o( CFGDEVCONTROLCORRERRREPORTINGEN_o ),
.CFGDEVCONTROLENABLERO_o( CFGDEVCONTROLENABLERO_o ),
.CFGDEVCONTROLEXTTAGEN_o( CFGDEVCONTROLEXTTAGEN_o ),
.CFGDEVCONTROLFATALERRREPORTINGEN_o( CFGDEVCONTROLFATALERRREPORTINGEN_o ),
.CFGDEVCONTROLMAXPAYLOAD_o( CFGDEVCONTROLMAXPAYLOAD_o ),
.CFGDEVCONTROLMAXREADREQ_o( CFGDEVCONTROLMAXREADREQ_o ),
.CFGDEVCONTROLNONFATALREPORTINGEN_o( CFGDEVCONTROLNONFATALREPORTINGEN_o ),
.CFGDEVCONTROLNOSNOOPEN_o( CFGDEVCONTROLNOSNOOPEN_o ),
.CFGDEVCONTROLPHANTOMEN_o( CFGDEVCONTROLPHANTOMEN_o ),
.CFGDEVCONTROLURERRREPORTINGEN_o( CFGDEVCONTROLURERRREPORTINGEN_o ),
.CFGDEVCONTROL2CPLTIMEOUTDIS_o( CFGDEVCONTROL2CPLTIMEOUTDIS_o ),
.CFGDEVCONTROL2CPLTIMEOUTVAL_o( CFGDEVCONTROL2CPLTIMEOUTVAL_o ),
.CFGDEVSTATUSCORRERRDETECTED_o( CFGDEVSTATUSCORRERRDETECTED_o ),
.CFGDEVSTATUSFATALERRDETECTED_o( CFGDEVSTATUSFATALERRDETECTED_o ),
.CFGDEVSTATUSNONFATALERRDETECTED_o( CFGDEVSTATUSNONFATALERRDETECTED_o ),
.CFGDEVSTATUSURDETECTED_o( CFGDEVSTATUSURDETECTED_o ),
.CFGDO_o( CFGDO_o ),
.CFGERRCPLRDYN_o( CFGERRCPLRDYN_o ),
.CFGINTERRUPTDO_o( CFGINTERRUPTDO_o ),
.CFGINTERRUPTMMENABLE_o( CFGINTERRUPTMMENABLE_o ),
.CFGINTERRUPTMSIENABLE_o( CFGINTERRUPTMSIENABLE_o ),
.CFGINTERRUPTMSIXENABLE_o( CFGINTERRUPTMSIXENABLE_o ),
.CFGINTERRUPTMSIXFM_o( CFGINTERRUPTMSIXFM_o ),
.CFGINTERRUPTRDYN_o( CFGINTERRUPTRDYN_o ),
.CFGLINKCONTROLRCB_o( CFGLINKCONTROLRCB_o ),
.CFGLINKCONTROLASPMCONTROL_o( CFGLINKCONTROLASPMCONTROL_o ),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN_o( CFGLINKCONTROLAUTOBANDWIDTHINTEN_o ),
.CFGLINKCONTROLBANDWIDTHINTEN_o( CFGLINKCONTROLBANDWIDTHINTEN_o ),
.CFGLINKCONTROLCLOCKPMEN_o( CFGLINKCONTROLCLOCKPMEN_o ),
.CFGLINKCONTROLCOMMONCLOCK_o( CFGLINKCONTROLCOMMONCLOCK_o ),
.CFGLINKCONTROLEXTENDEDSYNC_o( CFGLINKCONTROLEXTENDEDSYNC_o ),
.CFGLINKCONTROLHWAUTOWIDTHDIS_o( CFGLINKCONTROLHWAUTOWIDTHDIS_o ),
.CFGLINKCONTROLLINKDISABLE_o( CFGLINKCONTROLLINKDISABLE_o ),
.CFGLINKCONTROLRETRAINLINK_o( CFGLINKCONTROLRETRAINLINK_o ),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS_o( CFGLINKSTATUSAUTOBANDWIDTHSTATUS_o ),
.CFGLINKSTATUSBANDWITHSTATUS_o( CFGLINKSTATUSBANDWITHSTATUS_o ),
.CFGLINKSTATUSCURRENTSPEED_o( CFGLINKSTATUSCURRENTSPEED_o ),
.CFGLINKSTATUSDLLACTIVE_o( CFGLINKSTATUSDLLACTIVE_o ),
.CFGLINKSTATUSLINKTRAINING_o( CFGLINKSTATUSLINKTRAINING_o ),
.CFGLINKSTATUSNEGOTIATEDWIDTH_o( CFGLINKSTATUSNEGOTIATEDWIDTH_o ),
.CFGMSGDATA_o( CFGMSGDATA_o ),
.CFGMSGRECEIVED_o( CFGMSGRECEIVED_o ),
.CFGMSGRECEIVEDPMETO_o( CFGMSGRECEIVEDPMETO_o ),
.CFGPCIELINKSTATE_o( CFGPCIELINKSTATE_o ),
.CFGPMCSRPMEEN_o( CFGPMCSRPMEEN_o ),
.CFGPMCSRPMESTATUS_o( CFGPMCSRPMESTATUS_o ),
.CFGPMCSRPOWERSTATE_o( CFGPMCSRPOWERSTATE_o ),
.CFGRDWRDONEN_o( CFGRDWRDONEN_o ),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT_o( CFGMSGRECEIVEDSETSLOTPOWERLIMIT_o ),
.CFGMSGRECEIVEDUNLOCK_o( CFGMSGRECEIVEDUNLOCK_o ),
.CFGMSGRECEIVEDPMASNAK_o( CFGMSGRECEIVEDPMASNAK_o ),
.CFGPMRCVREQACKN_o( CFGPMRCVREQACKN_o ),
.CFGTRANSACTION_o( CFGTRANSACTION_o ),
.CFGTRANSACTIONADDR_o( CFGTRANSACTIONADDR_o ),
.CFGTRANSACTIONTYPE_o( CFGTRANSACTIONTYPE_o ),
.CFGBYTEENN_i( CFGBYTEENN_i ),
.CFGDI_i( CFGDI_i ),
.CFGDSN_i( CFGDSN_i ),
.CFGDWADDR_i( CFGDWADDR_i ),
.CFGERRACSN_i( CFGERRACSN_i ),
.CFGERRCORN_i( CFGERRCORN_i ),
.CFGERRCPLABORTN_i( CFGERRCPLABORTN_i ),
.CFGERRCPLTIMEOUTN_i( CFGERRCPLTIMEOUTN_i ),
.CFGERRCPLUNEXPECTN_i( CFGERRCPLUNEXPECTN_i ),
.CFGERRECRCN_i( CFGERRECRCN_i ),
.CFGERRLOCKEDN_i( CFGERRLOCKEDN_i ),
.CFGERRPOSTEDN_i( CFGERRPOSTEDN_i ),
.CFGERRTLPCPLHEADER_i( CFGERRTLPCPLHEADER_i ),
.CFGERRURN_i( CFGERRURN_i ),
.CFGINTERRUPTASSERTN_i( CFGINTERRUPTASSERTN_i ),
.CFGINTERRUPTDI_i( CFGINTERRUPTDI_i ),
.CFGINTERRUPTN_i( CFGINTERRUPTN_i ),
.CFGPMDIRECTASPML1N_i( CFGPMDIRECTASPML1N_i ),
.CFGPMSENDPMACKN_i( CFGPMSENDPMACKN_i ),
.CFGPMSENDPMETON_i( CFGPMSENDPMETON_i ),
.CFGPMSENDPMNAKN_i( CFGPMSENDPMNAKN_i ),
.CFGPMTURNOFFOKN_i( CFGPMTURNOFFOKN_i ),
.CFGPMWAKEN_i( CFGPMWAKEN_i ),
.CFGPORTNUMBER_i( CFGPORTNUMBER_i ),
.CFGRDENN_i( CFGRDENN_i ),
.CFGTRNPENDINGN_i( CFGTRNPENDINGN_i ),
.CFGWRENN_i( CFGWRENN_i ),
.CFGWRREADONLYN_i( CFGWRREADONLYN_i ),
.CFGWRRW1CASRWN_i( CFGWRRW1CASRWN_i )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3_SYMBOL_V
`define SKY130_FD_SC_HDLL__OR3_SYMBOL_V
/**
* or3: 3-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0N_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__INPUTISO0N_PP_BLACKBOX_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputiso0n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0N_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/23/2016 11:26:28 AM
// Design Name:
// Module Name: Sgf_Multiplication
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Sgf_Multiplication
#(parameter SW = 24)
//#(parameter SW = 54)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
//wire [SW-1:0] Data_A_i;
//wire [SW-1:0] Data_B_i;
//wire [2*(SW/2)-1:0] result_left_mult;
//wire [2*(SW/2+1)-1:0] result_right_mult;
wire [SW/2+1:0] result_A_adder;
//wire [SW/2+1:0] Q_result_A_adder;
wire [SW/2+1:0] result_B_adder;
//wire [SW/2+1:0] Q_result_B_adder;
//wire [2*(SW/2+2)-1:0] result_middle_mult;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
case (SW%2)
0:begin : GEN1
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
multiplier #(.W(SW/2)/*,.level(level1)*/) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
multiplier #(.W(SW/2)/*,.level(level1)*/) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right[2*(SW/2)-1:0])
);
// assign Q_left = Data_A_i[SW-1:SW-SW/2]*Data_B_i[SW-1:SW-SW/2];
// assign Q_right[2*(SW/2)-1:0] = Data_A_i[SW-SW/2-1:0]*Data_B_i[SW-SW/2-1:0];
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
//segmentation registers for 64 bits
//multiplication for middle
multiplier #(.W(SW/2+1)/*,.level(level1)*/) middle (
.clk(clk),
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.Data_S_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
//assign Q_middle[2*(SW/2)+1:0] = result_A_adder[SW/2:0]*result_B_adder[SW/2:0];
//segmentation registers array
/*RegisterAdd #(.W(SW+2)) midreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_middle_mult[2*(SW/2)+1:0]),
.Q(Q_middle[2*(SW/2)+1:0])
);//*/
///Subtractors for middle
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A[2*(SW/2)+1:0])
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]}),
.Data_S_o(S_B[2*(SW/2)+1:0])
);
//Final adder
adder #(.W(4*(SW/2))) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right[2*(SW/2)-1:0]}),
.Data_B_i({{(2*SW-(SW+SW/2+2)){1'b0}},S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : GEN2
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
multiplier #(.W(SW/2)/*,.level(level2)*/) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
/*RegisterAdd #(.W(2*(SW/2))) leftreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_left_mult),
.Q(Q_left)
);//*/
multiplier #(.W((SW/2)+1)/*,.level(level2)*/) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(/*result_right_mult*/Q_right)
);
/*RegisterAdd #(.W(2*((SW/2)+1))) rightreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_right_mult),
.Q(Q_right)
);//*/
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//multiplication for middle
multiplier #(.W(SW/2+2)/*,.level(level2)*/) middle (
.clk(clk),
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.Data_S_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
//-- Banco de prueba para setbit
//-- (c) BQ August 2015
//-- Written by Juan Gonzalez (obijuan)
//-- mods by D. Cuartielles for Arduino, 2015 December, GPLv3
//-----------------------------------------------------------------------------
//-- Para la simulacion del componente es necesario hacer un banco de pruebas
//-- que coloque el componente, asigne valor a las entradas y compruebe las
//-- salidas. En el caso del compoente setbit, es muy sencillo. Solo tiene
//-- una salida, así que colocamos un cable a su salida y comprobamos que
//-- efectivamente se encuentra a valor 1
//-----------------------------------------------------------------------------
//-- Modulo para el test bench
module setbit_tb;
//-- Cable para conectar al componente que pone
//-- el bit a uno
wire LED1;
//--Instanciar el componente. Conectado al cable A
setbit SB1 (
.LED1 (LED1)
);
//-- Comenzamos las pruebas
initial begin
//-- Definir el fichero donde volvar los datos
//-- para ver graficamente la salida
$dumpfile("T01-setbit_tb.vcd");
//-- Volcar todos los datos a ese fichero
$dumpvars(0, setbit_tb);
//-- Pasadas 10 unidades de tiempo comprobamos
//-- si el cable esta a 1
//-- En caso de no estar a 1, se informa del problema, pero la
//-- simulacion no se detiene
# 10 if (LED1 != 1)
$display("---->¡ERROR! Salida no esta a 1");
else
$display("Componente ok!");
//-- Terminar la simulacion 10 unidades de tiempo
//-- despues
# 10 $finish;
end
endmodule
|
// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.0 595
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_7"),
.ENUM_MEM_IF_TCWL ("TCWL_7"),
.ENUM_MEM_IF_TFAW ("TFAW_15"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_16"),
.ENUM_MEM_IF_TRC ("TRC_22"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_2"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (2800),
.INTG_MEM_IF_TRFC (30),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
(* abc9_flop, lib_whitebox *)
module sh_dff(
output reg Q,
input D,
(* clkbuf_sink *)
input C
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge C)
Q <= D;
endmodule
(* abc9_box, lib_blackbox *)
module adder_carry(
output sumout,
output cout,
input p,
input g,
input cin
);
assign sumout = p ^ cin;
assign cout = p ? cin : g;
endmodule
(* abc9_box, lib_whitebox *)
module adder_lut5(
output lut5_out,
(* abc9_carry *)
output cout,
input [0:4] in,
(* abc9_carry *)
input cin
);
parameter [0:15] LUT=0;
parameter IN2_IS_CIN = 0;
wire [0:4] li = (IN2_IS_CIN) ? {in[0], in[1], cin, in[3], in[4]} : {in[0], in[1], in[2], in[3],in[4]};
// Output function
wire [0:15] s1 = li[0] ?
{LUT[0], LUT[2], LUT[4], LUT[6], LUT[8], LUT[10], LUT[12], LUT[14], LUT[16], LUT[18], LUT[20], LUT[22], LUT[24], LUT[26], LUT[28], LUT[30]}:
{LUT[1], LUT[3], LUT[5], LUT[7], LUT[9], LUT[11], LUT[13], LUT[15], LUT[17], LUT[19], LUT[21], LUT[23], LUT[25], LUT[27], LUT[29], LUT[31]};
wire [0:7] s2 = li[1] ? {s1[0], s1[2], s1[4], s1[6], s1[8], s1[10], s1[12], s1[14]} :
{s1[1], s1[3], s1[5], s1[7], s1[9], s1[11], s1[13], s1[15]};
wire [0:3] s3 = li[2] ? {s2[0], s2[2], s2[4], s2[6]} : {s2[1], s2[3], s2[5], s2[7]};
wire [0:1] s4 = li[3] ? {s3[0], s3[2]} : {s3[1], s3[3]};
assign lut5_out = li[4] ? s4[0] : s4[1];
// Carry out function
assign cout = (s3[2]) ? cin : s3[3];
endmodule
(* abc9_lut=1, lib_whitebox *)
module frac_lut6(
input [0:5] in,
output [0:3] lut4_out,
output [0:1] lut5_out,
output lut6_out
);
parameter [0:63] LUT = 0;
// Effective LUT input
wire [0:5] li = in;
// Output function
wire [0:31] s1 = li[0] ?
{LUT[0] , LUT[2] , LUT[4] , LUT[6] , LUT[8] , LUT[10], LUT[12], LUT[14],
LUT[16], LUT[18], LUT[20], LUT[22], LUT[24], LUT[26], LUT[28], LUT[30],
LUT[32], LUT[34], LUT[36], LUT[38], LUT[40], LUT[42], LUT[44], LUT[46],
LUT[48], LUT[50], LUT[52], LUT[54], LUT[56], LUT[58], LUT[60], LUT[62]}:
{LUT[1] , LUT[3] , LUT[5] , LUT[7] , LUT[9] , LUT[11], LUT[13], LUT[15],
LUT[17], LUT[19], LUT[21], LUT[23], LUT[25], LUT[27], LUT[29], LUT[31],
LUT[33], LUT[35], LUT[37], LUT[39], LUT[41], LUT[43], LUT[45], LUT[47],
LUT[49], LUT[51], LUT[53], LUT[55], LUT[57], LUT[59], LUT[61], LUT[63]};
wire [0:15] s2 = li[1] ?
{s1[0] , s1[2] , s1[4] , s1[6] , s1[8] , s1[10], s1[12], s1[14],
s1[16], s1[18], s1[20], s1[22], s1[24], s1[26], s1[28], s1[30]}:
{s1[1] , s1[3] , s1[5] , s1[7] , s1[9] , s1[11], s1[13], s1[15],
s1[17], s1[19], s1[21], s1[23], s1[25], s1[27], s1[29], s1[31]};
wire [0:7] s3 = li[2] ?
{s2[0], s2[2], s2[4], s2[6], s2[8], s2[10], s2[12], s2[14]}:
{s2[1], s2[3], s2[5], s2[7], s2[9], s2[11], s2[13], s2[15]};
wire [0:3] s4 = li[3] ? {s3[0], s3[2], s3[4], s3[6]}:
{s3[1], s3[3], s3[5], s3[7]};
wire [0:1] s5 = li[4] ? {s4[0], s4[2]} : {s4[1], s4[3]};
assign lut4_out[0] = s4[0];
assign lut4_out[1] = s4[1];
assign lut4_out[2] = s4[2];
assign lut4_out[3] = s4[3];
assign lut5_out[0] = s0[0];
assign lut5_out[1] = s5[1];
assign lut6_out = li[5] ? s5[0] : s5[1];
endmodule
(* abc9_flop, lib_whitebox *)
module dff(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C)
Q <= D;
1'b1:
always @(negedge C)
Q <= D;
endcase
endmodule
(* abc9_flop, lib_whitebox *)
module dffr(
output reg Q,
input D,
input R,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or posedge R)
if (R)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C or posedge R)
if (R)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
(* abc9_flop, lib_whitebox *)
module dffre(
output reg Q,
input D,
input R,
input E,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or posedge R)
if (R)
Q <= 1'b0;
else if(E)
Q <= D;
1'b1:
always @(negedge C or posedge R)
if (R)
Q <= 1'b0;
else if(E)
Q <= D;
endcase
endmodule
module dffs(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input S
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge S)
if (S)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C or negedge S)
if (S)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule
module dffse(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input S,
input E,
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge S)
if (S)
Q <= 1'b1;
else if(E)
Q <= D;
1'b1:
always @(negedge C or negedge S)
if (S)
Q <= 1'b1;
else if(E)
Q <= D;
endcase
endmodule
module dffsr(
output reg Q,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input R,
input S
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge S or negedge R)
if (S)
Q <= 1'b1;
else if (R)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C or negedge S or negedge R)
if (S)
Q <= 1'b1;
else if (R)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule
module dffsre(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input E,
input R,
input S
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge C or negedge S or negedge R)
if (!R)
Q <= 1'b0;
else if (!S)
Q <= 1'b1;
else if (E)
Q <= D;
endmodule
module dffnsre(
output reg Q,
input D,
(* clkbuf_sink *)
input C,
input E,
input R,
input S
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge C or negedge S or negedge R)
if (!R)
Q <= 1'b0;
else if (!S)
Q <= 1'b1;
else if (E)
Q <= D;
endmodule
(* abc9_flop, lib_whitebox *)
module latchsre (
output reg Q,
input S,
input R,
input D,
input G,
input E
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
begin
if (!R)
Q <= 1'b0;
else if (!S)
Q <= 1'b1;
else if (E && G)
Q <= D;
end
endmodule
(* abc9_flop, lib_whitebox *)
module latchnsre (
output reg Q,
input S,
input R,
input D,
input G,
input E
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @*
begin
if (!R)
Q <= 1'b0;
else if (!S)
Q <= 1'b1;
else if (E && !G)
Q <= D;
end
endmodule
(* abc9_flop, lib_whitebox *)
module scff(
output reg Q,
input D,
input clk
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge clk)
Q <= D;
endmodule
module TDP_BRAM18 (
(* clkbuf_sink *)
input CLOCKA,
(* clkbuf_sink *)
input CLOCKB,
input READENABLEA,
input READENABLEB,
input [13:0] ADDRA,
input [13:0] ADDRB,
input [15:0] WRITEDATAA,
input [15:0] WRITEDATAB,
input [1:0] WRITEDATAAP,
input [1:0] WRITEDATABP,
input WRITEENABLEA,
input WRITEENABLEB,
input [1:0] BYTEENABLEA,
input [1:0] BYTEENABLEB,
//input [2:0] WRITEDATAWIDTHA,
//input [2:0] WRITEDATAWIDTHB,
//input [2:0] READDATAWIDTHA,
//input [2:0] READDATAWIDTHB,
output [15:0] READDATAA,
output [15:0] READDATAB,
output [1:0] READDATAAP,
output [1:0] READDATABP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
endmodule
module TDP_BRAM36 (
(* clkbuf_sink *)
input CLOCKA,
(* clkbuf_sink *)
input CLOCKB,
input READENABLEA,
input READENABLEB,
input [14:0] ADDRA,
input [14:0] ADDRB,
input [31:0] WRITEDATAA,
input [31:0] WRITEDATAB,
input [3:0] WRITEDATAAP,
input [3:0] WRITEDATABP,
input WRITEENABLEA,
input WRITEENABLEB,
input [3:0] BYTEENABLEA,
input [3:0] BYTEENABLEB,
//input [2:0] WRITEDATAWIDTHA,
//input [2:0] WRITEDATAWIDTHB,
//input [2:0] READDATAWIDTHA,
//input [2:0] READDATAWIDTHB,
output [31:0] READDATAA,
output [31:0] READDATAB,
output [3:0] READDATAAP,
output [3:0] READDATABP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
endmodule
(* blackbox *)
module QL_DSP1 (
input [19:0] a,
input [17:0] b,
input clk0,
(* clkbuf_sink *)
input clk1,
(* clkbuf_sink *)
input [ 1:0] feedback0,
input [ 1:0] feedback1,
input load_acc0,
input load_acc1,
input reset0,
input reset1,
output reg [37:0] z
);
parameter MODE_BITS = 27'b00000000000000000000000000;
endmodule /* QL_DSP1 */
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3B_BLACKBOX_V
`define SKY130_FD_SC_LS__NAND3B_BLACKBOX_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand3b (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3B_BLACKBOX_V
|
\begin{codeblock}
module Lpm (input wire CLK, input wire nRST,
input wire request$enter__ENA,
input wire [31:0]request$enter$x,
output wire request$enter__RDY,
output wire outQ$enq__ENA,
output wire [31:0]outQ$enq$v,
input wire outQ$enq__RDY);
wire [2:0]RULE$recirc__ENA$agg_2e_tmp$state;
wire [15:0]RULE$recirc__ENA$y$IPA;
wire compBuf$tickIfc$allocateTicket__ENA;
wire compBuf$tickIfc$allocateTicket__RDY;
wire [3:0]compBuf$tickIfc$getTicket;
wire compBuf$tickIfc$getTicket__RDY;
wire [22:0]fifo$in$enq$v;
wire fifo$in$enq__ENA;
wire fifo$in$enq__RDY;
wire fifo$out$deq__ENA;
wire fifo$out$deq__RDY;
wire [22:0]fifo$out$first;
wire fifo$out$first__RDY;
wire inQ$in$enq__RDY;
wire inQ$out$deq__ENA;
wire inQ$out$deq__RDY;
wire [31:0]inQ$out$first;
wire inQ$out$first__RDY;
wire [31:0]mem$ifc$req$v;
wire mem$ifc$req__ENA;
wire mem$ifc$req__RDY;
wire mem$ifc$resAccept__ENA;
wire mem$ifc$resAccept__RDY;
wire [31:0]mem$ifc$resValue;
wire mem$ifc$resValue__RDY;
BufTicket compBuf (.CLK(CLK), .nRST(nRST),
.tickIfc$allocateTicket__ENA(compBuf$tickIfc$allocateTicket__ENA),
.tickIfc$allocateTicket__RDY(compBuf$tickIfc$allocateTicket__RDY),
.tickIfc$getTicket(compBuf$tickIfc$getTicket),
.tickIfc$getTicket__RDY(compBuf$tickIfc$getTicket__RDY));
Fifo1Base#(32) inQ (.CLK(CLK), .nRST(nRST),
.in$enq__ENA(request$enter__ENA),
.in$enq$v(request$enter$x),
.in$enq__RDY(inQ$in$enq__RDY),
.out$deq__ENA(inQ$out$deq__ENA),
.out$deq__RDY(inQ$out$deq__RDY),
.out$first(inQ$out$first),
.out$first__RDY(inQ$out$first__RDY));
FifoB1Base#(23) fifo (.CLK(CLK), .nRST(nRST),
.in$enq__ENA(fifo$in$enq__ENA),
.in$enq$v(fifo$in$enq$v),
.in$enq__RDY(fifo$in$enq__RDY),
.out$deq__ENA(fifo$out$deq__ENA),
.out$deq__RDY(fifo$out$deq__RDY),
.out$first(fifo$out$first),
.out$first__RDY(fifo$out$first__RDY));
LpmMemory mem (.CLK(CLK), .nRST(nRST),
.ifc$req__ENA(mem$ifc$req__ENA),
.ifc$req$v(mem$ifc$req$v),
.ifc$req__RDY(mem$ifc$req__RDY),
.ifc$resAccept__ENA(mem$ifc$resAccept__ENA),
.ifc$resAccept__RDY(mem$ifc$resAccept__RDY),
.ifc$resValue(mem$ifc$resValue),
.ifc$resValue__RDY(mem$ifc$resValue__RDY));
// There are still ERRORs in some of these conditions
assign compBuf$tickIfc$allocateTicket__ENA = ( !( ( mem$ifc$resValue != 32'd1 )
& mem$ifc$resValue__RDY & fifo$out$first__RDY & mem$ifc$resAccept__RDY
& mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY ) )
& inQ$out$first__RDY & compBuf$tickIfc$getTicket__RDY & inQ$out$deq__RDY & fifo$in$enq__RDY & mem$ifc$req__RDY;
assign fifo$in$enq$v = ( ( ( !( ( mem$ifc$resValue != 32'd1 )
& mem$ifc$resValue__RDY & fifo$out$first__RDY
& mem$ifc$resAccept__RDY & mem$ifc$req__RDY
& fifo$out$deq__RDY & fifo$in$enq__RDY ) )
& inQ$out$first__RDY & compBuf$tickIfc$getTicket__RDY
& compBuf$tickIfc$allocateTicket__RDY
& inQ$out$deq__RDY & fifo$in$enq__RDY & mem$ifc$req__RDY )
? { 3'd0 , inQ$out$first[ 15 : 0 ] , compBuf$tickIfc$getTicket } : 23'd0 )
| ( ( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY
& fifo$out$first__RDY & mem$ifc$resAccept__RDY
& mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY )
? { RULE$recirc__ENA$agg_2e_tmp$state , fifo$out$first[ 19 : 4 ] , fifo$out$first[ 3 : 0 ] } : 23'd0 );
assign fifo$in$enq__ENA = ( ( !( ( mem$ifc$resValue != 32'd1 )
& mem$ifc$resValue__RDY & fifo$out$first__RDY
& mem$ifc$resAccept__RDY & mem$ifc$req__RDY & fifo$out$deq__RDY ) )
& inQ$out$first__RDY & compBuf$tickIfc$getTicket__RDY
& compBuf$tickIfc$allocateTicket__RDY & inQ$out$deq__RDY & mem$ifc$req__RDY )
| ( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY
& fifo$out$first__RDY & mem$ifc$resAccept__RDY & mem$ifc$req__RDY & fifo$out$deq__RDY );
assign fifo$out$deq__ENA = ( ( mem$ifc$resValue == 32'd1 )
& ( !( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY
& fifo$out$first__RDY & mem$ifc$resAccept__RDY
& mem$ifc$req__RDY & fifo$in$enq__RDY ) )
& mem$ifc$resValue__RDY & fifo$out$first__RDY & mem$ifc$resAccept__RDY & outQ$enq__RDY )
| ( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY
& fifo$out$first__RDY & mem$ifc$resAccept__RDY & mem$ifc$req__RDY & fifo$in$enq__RDY );
assign inQ$out$deq__ENA = ( !( ( mem$ifc$resValue != 32'd1 )
& mem$ifc$resValue__RDY & fifo$out$first__RDY &
mem$ifc$resAccept__RDY & mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY ) )
& inQ$out$first__RDY & compBuf$tickIfc$getTicket__RDY
& compBuf$tickIfc$allocateTicket__RDY & fifo$in$enq__RDY & mem$ifc$req__RDY;
assign mem$ifc$req$v = ( ( ( !( ( mem$ifc$resValue != 32'd1 )
& mem$ifc$resValue__RDY & fifo$out$first__RDY
& mem$ifc$resAccept__RDY & mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY ) )
& inQ$out$first__RDY & compBuf$tickIfc$getTicket__RDY
& compBuf$tickIfc$allocateTicket__RDY & inQ$out$deq__RDY
& fifo$in$enq__RDY & mem$ifc$req__RDY )
? ( 32'd0 + inQ$out$first[ 31 : 16 ] inQ$out$first [ 18446744073709551615 ] ) : 32'd0 )
| ( ( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY &
fifo$out$first__RDY & mem$ifc$resAccept__RDY
& mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY )
? ( ( ( mem$ifc$resValue + fifo$out$first[ 22 : 20 ] ) == 1 )
? RULE$recirc__ENA$y$IPA[ 15 : 8 ]
: RULE$recirc__ENA$y$IPA[ 7 : 0 ] )
: 8'd0 );
assign mem$ifc$req__ENA = ( ( ( !( ( mem$ifc$resValue != 32'd1 )
& mem$ifc$resValue__RDY & fifo$out$first__RDY
& mem$ifc$resAccept__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY ) )
& inQ$out$first__RDY & compBuf$tickIfc$getTicket__RDY
& compBuf$tickIfc$allocateTicket__RDY & inQ$out$deq__RDY )
| ( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY
& fifo$out$first__RDY & mem$ifc$resAccept__RDY & fifo$out$deq__RDY ) )
& fifo$in$enq__RDY;
assign mem$ifc$resAccept__ENA = ( ( mem$ifc$resValue == 32'd1 )
& ( !( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY
& fifo$out$first__RDY & mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY ) )
& mem$ifc$resValue__RDY & fifo$out$first__RDY & fifo$out$deq__RDY & outQ$enq__RDY )
| ( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY & fifo$out$first__RDY
& mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY );
assign outQ$enq$v = mem$ifc$resValue;
assign outQ$enq__ENA = ( mem$ifc$resValue == 32'd1 )
& ( !( ( mem$ifc$resValue != 32'd1 ) & mem$ifc$resValue__RDY & fifo$out$first__RDY
& mem$ifc$resAccept__RDY & mem$ifc$req__RDY & fifo$out$deq__RDY & fifo$in$enq__RDY ) )
& mem$ifc$resValue__RDY & fifo$out$first__RDY & mem$ifc$resAccept__RDY & fifo$out$deq__RDY;
assign request$enter__RDY = inQ$in$enq__RDY;
// Extra assigments, not to output wires
assign RULE$recirc__ENA$agg_2e_tmp$state = fifo$out$first[ 22 : 20 ] + 3'd1;
assign RULE$recirc__ENA$y$IPA = fifo$out$first[ 19 : 4 ];
endmodule
\end{codeblock}
|
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTN_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLXTN_FUNCTIONAL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxtn (
VPWR ,
VGND ,
Q ,
D ,
GATE_N
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input D ;
input GATE_N;
// Local signals
wire gate buf_Q ;
wire gate GATE_N_delayed;
wire gate D_delayed ;
wire GATE ;
// Name Output Other arguments
not not0 (GATE , GATE_N );
sky130_fd_sc_hs__u_dl_p_pg u_dl_p_pg0 (buf_Q , D, GATE, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTN_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVP_BLACKBOX_V
`define SKY130_FD_SC_HS__EINVP_BLACKBOX_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__einvp (
A ,
TE,
Z
);
input A ;
input TE;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVP_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Top level stimulus file for ImaginePC family of chips
// File : borealis_stim.v
// Author : Frank Bruno
// Created : 12-29-2005
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description : This file is the top level stimulus file for Borealis
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module graph_core_stim;
`define DISPLAY_MODE 32'H0104_0101
`define BLOCK_MODE 32'h0
`include "../../stim/includes/stim_params_sh.h"
parameter
`ifdef BYTE4
BYTES = 4,
BYTE_BASE = 2,
`elsif BYTE8
BYTES = 8,
BYTE_BASE = 3,
`elsif BYTE16
BYTES = 16,
BYTE_BASE = 4,
`else
BYTES = 32,
BYTE_BASE = 5,
`endif
DE_ADDR = 32'h800,
`ifdef WIN_TEST XYW_ADDR = 32'h4000_0000,
`else XYW_ADDR = 32'h1000_0000,
`endif
id_width = 4,
addr_width = 29,
aresp_width = 2,
alen_width = 4,
asize_width = 3,
aburst_width = 2,
alock_width = 2,
acache_width = 4,
aprot_width = 3;
reg start_of_test = 0;
// Clock and reset signals
reg pclk; // host clock reg port
reg de_clk; // Drawing engine clock
reg pll_ref_clk; // 25Mhz Board clock
wire mclock; // Memory controller clock
reg bb_rstn; // Global soft reset
// Dual port ram interface for ded_ca_top.v
`ifdef BYTE16
wire [3:0] ca_enable;
`elsif BYTE8
wire [1:0] ca_enable;
`else
wire ca_enable;
`endif
wire de_push;
wire [(BYTES*8)-1:0] mc_read_data;
wire [4:0] ca_ram_addr0;
wire [4:0] ca_ram_addr1;
wire [(BYTES*8)-1:0] hb_dout_ram, hb_din;
reg [(BYTES*8)-1:0] hb_dout_ramc;
wire [(BYTES<<3)-1:0] ca_dout0;
wire [(BYTES<<3)-1:0] ca_dout1;
// Host interface signals
reg [31:2] paddr; // APB address.
reg [31:0] pwdata; // APA data.
reg pwrite; // Host write enable
reg psel; // Chip Select
reg penable; // Chip Select
wire [31:0] prdata; // host bus read back data
reg [31:0] pwcdata; // Cache swizzel data.
wire interrupt; // host interrupt active high.
// DLP signals
reg vb_int_tog; // Vertical interrupt
// DDR3 signals
tri [ 63: 0] mem_dq;
tri [ 7: 0] mem_dqs;
tri [ 7: 0] mem_dqsn;
wire [ 13: 0] mem_addr;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire mem_cke;
wire mem_clk;
wire mem_clk_n;
wire mem_cs_n;
wire [ 7: 0] mem_dm;
wire mem_odt;
wire mem_ras_n;
wire mem_rst_n;
wire mem_we_n;
// SIMULATION ENVIRONMENT REGISTERS.
reg enable_64;
reg [19:0] aw_mask;
reg [3:0] aw_size;
reg [31:0] config_reg;
reg [31:0] temp_config;
reg config_en;
reg [31:0] rbase_io;
reg [31:0] rbase_g; // holding register for the global base address.
reg [31:0] rbase_w; // holding register for the memory windows base addr
reg [31:0] rbase_a; // holding register for drawing engine A base addr
reg [31:0] rbase_aw; // holding reg for drawing engine A cache base addr
reg [31:0] rbase_b; // holding register for drawing engine B base addr
reg [31:0] rbase_bw; // holding reg for drawing engine B cache base addr
reg [31:0] rbase_i; // holding register for interrupt register address.
reg [31:0] rbase_e; // holding register for EPROM base address.
reg [31:0] rbase_mw0;
reg [31:0] rbase_mw1;
reg [31:0] test_reg; // holding register for read.
reg [15:0] h;
reg [15:0] i;
reg [15:0] j;
reg [15:0] k;
reg [15:0] l;
reg [15:0] m;
reg [15:0] n;
reg [15:0] o;
reg [15:0] p;
reg [15:0] w;
reg [15:0] xs;
reg [15:0] ys;
reg [15:0] xd;
reg [15:0] yd;
reg [15:0] xe;
reg [15:0] ye;
reg [15:0] xs_inc;
reg [15:0] ys_inc;
reg [15:0] xe_inc;
reg [15:0] ye_inc;
reg [15:0] zx;
reg [15:0] zy;
reg [14:0] mw0_mask;
reg [14:0] mw1_mask;
reg [31:12] mw0_ad_dout;
reg [31:12] mw1_ad_dout;
reg [3:0] mw0_sz_dout;
reg [3:0] mw1_sz_dout;
reg [31:0] mw0_org_dout;
reg [31:0] mw1_org_dout;
reg [31:0] mem_address;
reg [31:0] old_mem;
// hb port to the cache for sims
wire [4:0] hb_ram_addr;
reg [31:12] xyw_a_dout;
graph_core
#(
.BYTES (BYTES),
.DE_ADDR (DE_ADDR),
.XYW_ADDR (XYW_ADDR)
)
u_core
(
// Clock and reset signals
.de_clk (de_clk),
.mclock (mclock),
.pll_ref_clk (pll_ref_clk),
.bb_rstn (bb_rstn),
// Host interface signals
.pclk (pclk),
.paddr (paddr),
.pwdata (pwdata),
.pwrite (pwrite),
.psel (psel),
.penable (penable),
.prdata (prdata),
.pready (pready),
.pslverr (pslverr),
.interrupt (interrupt),
// Memory Window Flush in progress.
// Tie to zero if frame buffer is not cached.
.mw_de_fip (1'b0),
.mw_dlp_fip (1'b0),
// Dual port ram interface for ded_ca_top.v
.ca_enable (ca_enable),
.hb_ram_addr (hb_ram_addr),
.de_push (de_push),
.mc_read_data (mc_read_data),
.ca_ram_addr0 (ca_ram_addr0),
.ca_ram_addr1 (ca_ram_addr1),
.hb_dout_ram (hb_dout_ramc),
.ca_dout0 (ca_dout0),
.ca_dout1 (ca_dout1),
// DLP signals
.vb_int_tog (vb_int_tog),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (mem_cs_n),
.mem_dm (mem_dm),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_rst_n (mem_rst_n),
.mem_we_n (mem_we_n),
// outputs:
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqsn (mem_dqsn)
);
// Write swizzle.
always @* begin
case(u_core.U_DE.hdf_1)
3'b000: pwcdata = pwdata;
3'b001: pwcdata = {hdf_rot(pwdata[31:24]), hdf_rot(pwdata[23:16]), hdf_rot(pwdata[15:8]), hdf_rot(pwdata[7:0])};
3'b010: pwcdata = {pwdata[23:16], pwdata[31:24], pwdata[7:0], pwdata[15:8]};
3'b011: pwcdata = {hdf_rot(pwdata[23:16]), hdf_rot(pwdata[31:24]), hdf_rot(pwdata[7:0]), hdf_rot(pwdata[15:8])};
3'b100: pwcdata = {pwdata[15:8], pwdata[7:0], pwdata[31:24], pwdata[23:16]};
3'b101: pwcdata = {hdf_rot(pwdata[15:8]), hdf_rot(pwdata[7:0]), hdf_rot(pwdata[31:24]), hdf_rot(pwdata[23:16])};
3'b110: pwcdata = {pwdata[7:0], pwdata[15:8], pwdata[23:16], pwdata[31:24]};
3'b111: pwcdata = {hdf_rot(pwdata[7:0]), hdf_rot(pwdata[15:8]), hdf_rot(pwdata[23:16]), hdf_rot(pwdata[31:24])};
endcase
end
// Read swizzle.
always @* begin
if (BYTES == 16) begin
case(u_core.U_DE.hdf_1)
3'b000: hb_dout_ramc[127:64] = hb_dout_ram[127:64];
3'b001: hb_dout_ramc[127:64] =
{
hdf_rot(hb_dout_ram[127:120]),
hdf_rot(hb_dout_ram[119:112]),
hdf_rot(hb_dout_ram[111:104]),
hdf_rot(hb_dout_ram[103:96]),
hdf_rot(hb_dout_ram[95:88]),
hdf_rot(hb_dout_ram[87:80]),
hdf_rot(hb_dout_ram[79:72]),
hdf_rot(hb_dout_ram[71:64])
};
3'b010: hb_dout_ramc[127:64] =
{
hb_dout_ram[119:112],
hb_dout_ram[127:120],
hb_dout_ram[103:96],
hb_dout_ram[111:104],
hb_dout_ram[87:80],
hb_dout_ram[95:88],
hb_dout_ram[71:64],
hb_dout_ram[79:72]
};
3'b011: hb_dout_ramc[127:64] =
{
hdf_rot(hb_dout_ram[119:112]),
hdf_rot(hb_dout_ram[127:120]),
hdf_rot(hb_dout_ram[103:96]),
hdf_rot(hb_dout_ram[111:104]),
hdf_rot(hb_dout_ram[87:80]),
hdf_rot(hb_dout_ram[95:88]),
hdf_rot(hb_dout_ram[71:64]),
hdf_rot(hb_dout_ram[79:72])
};
3'b100: hb_dout_ramc[127:64] =
{
hb_dout_ram[111:104],
hb_dout_ram[103:96],
hb_dout_ram[127:120],
hb_dout_ram[119:112],
hb_dout_ram[79:72],
hb_dout_ram[71:64],
hb_dout_ram[95:88],
hb_dout_ram[87:80]
};
3'b101: hb_dout_ramc[127:64] =
{
hdf_rot(hb_dout_ram[111:104]),
hdf_rot(hb_dout_ram[103:96]),
hdf_rot(hb_dout_ram[127:120]),
hdf_rot(hb_dout_ram[119:112]),
hdf_rot(hb_dout_ram[79:72]),
hdf_rot(hb_dout_ram[71:64]),
hdf_rot(hb_dout_ram[95:88]),
hdf_rot(hb_dout_ram[87:80])
};
3'b110: hb_dout_ramc[127:64] =
{
hb_dout_ram[103:96],
hb_dout_ram[111:104],
hb_dout_ram[119:112],
hb_dout_ram[127:120],
hb_dout_ram[71:64],
hb_dout_ram[79:72],
hb_dout_ram[87:80],
hb_dout_ram[95:88]
};
3'b111: hb_dout_ramc[127:64] =
{
hdf_rot(hb_dout_ram[103:96]),
hdf_rot(hb_dout_ram[111:104]),
hdf_rot(hb_dout_ram[119:112]),
hdf_rot(hb_dout_ram[127:120]),
hdf_rot(hb_dout_ram[71:64]),
hdf_rot(hb_dout_ram[79:72]),
hdf_rot(hb_dout_ram[87:80]),
hdf_rot(hb_dout_ram[95:88])
};
endcase
end
if (BYTES == 16 || BYTES == 8) begin
case(u_core.U_DE.hdf_1)
3'b000: hb_dout_ramc[63:32] = hb_dout_ram[63:32];
3'b001: hb_dout_ramc[63:32] =
{
hdf_rot(hb_dout_ram[63:56]),
hdf_rot(hb_dout_ram[55:48]),
hdf_rot(hb_dout_ram[47:40]),
hdf_rot(hb_dout_ram[39:32])
};
3'b010: hb_dout_ramc[63:32] =
{
hb_dout_ram[55:48],
hb_dout_ram[63:56],
hb_dout_ram[39:32],
hb_dout_ram[47:40]
};
3'b011: hb_dout_ramc[63:32] =
{
hdf_rot(hb_dout_ram[55:48]),
hdf_rot(hb_dout_ram[63:56]),
hdf_rot(hb_dout_ram[39:32]),
hdf_rot(hb_dout_ram[47:40])
};
3'b100: hb_dout_ramc[63:32] =
{
hb_dout_ram[47:40],
hb_dout_ram[39:32],
hb_dout_ram[63:56],
hb_dout_ram[55:48]
};
3'b101: hb_dout_ramc[63:32] =
{
hdf_rot(hb_dout_ram[47:40]),
hdf_rot(hb_dout_ram[39:32]),
hdf_rot(hb_dout_ram[63:56]),
hdf_rot(hb_dout_ram[55:48])
};
3'b110: hb_dout_ramc[63:32] =
{
hb_dout_ram[39:32],
hb_dout_ram[47:40],
hb_dout_ram[55:48],
hb_dout_ram[63:56]
};
3'b111: hb_dout_ramc[63:32] =
{
hdf_rot(hb_dout_ram[39:32]),
hdf_rot(hb_dout_ram[47:40]),
hdf_rot(hb_dout_ram[55:48]),
hdf_rot(hb_dout_ram[63:56])
};
endcase
end
case(u_core.U_DE.hdf_1)
3'b000: hb_dout_ramc[31:0] = hb_dout_ram[31:0];
3'b001: hb_dout_ramc[31:0] =
{
hdf_rot(hb_dout_ram[31:24]),
hdf_rot(hb_dout_ram[23:16]),
hdf_rot(hb_dout_ram[15:8]),
hdf_rot(hb_dout_ram[7:0])
};
3'b010: hb_dout_ramc[31:0] =
{
hb_dout_ram[23:16],
hb_dout_ram[31:24],
hb_dout_ram[7:0],
hb_dout_ram[15:8]
};
3'b011: hb_dout_ramc[31:0] =
{
hdf_rot(hb_dout_ram[23:16]),
hdf_rot(hb_dout_ram[31:24]),
hdf_rot(hb_dout_ram[7:0]),
hdf_rot(hb_dout_ram[15:8])
};
3'b100: hb_dout_ramc[31:0] =
{
hb_dout_ram[15:8],
hb_dout_ram[7:0],
hb_dout_ram[31:24],
hb_dout_ram[23:16]
};
3'b101: hb_dout_ramc[31:0] =
{
hdf_rot(hb_dout_ram[15:8]),
hdf_rot(hb_dout_ram[7:0]),
hdf_rot(hb_dout_ram[31:24]),
hdf_rot(hb_dout_ram[23:16])
};
3'b110: hb_dout_ramc[31:0] =
{
hb_dout_ram[7:0],
hb_dout_ram[15:8],
hb_dout_ram[23:16],
hb_dout_ram[31:24]
};
3'b111: hb_dout_ramc[31:0] =
{
hdf_rot(hb_dout_ram[7:0]),
hdf_rot(hb_dout_ram[15:8]),
hdf_rot(hb_dout_ram[23:16]),
hdf_rot(hb_dout_ram[31:24])
};
endcase
end
// DE cache RAMs
// ram_32x32_dp_be u_ram0[`BYTES/4-1:0]
dual_port_sim u_ram0[BYTES/4-1:0]
(
.clock_a (pclk),
.data_a (pwcdata),
.wren_a (ca_enable),
.address_a (hb_ram_addr),
.clock_b (mclock),
.data_b (mc_read_data),
.address_b (ca_ram_addr0),
.wren_b (de_push),
.q_a (hb_dout_ram),
.q_b (ca_dout0)
);
// ram_32x32_dp_be u_ram4[`BYTES/4-1:0]
dual_port_sim u_ram4[BYTES/4-1:0]
(
.clock_a (pclk),
.data_a (pwcdata),
.wren_a (ca_enable),
.address_a (hb_ram_addr),
.clock_b (mclock),
.data_b (mc_read_data),
.address_b (ca_ram_addr1),
.wren_b (de_push),
.q_a (),
.q_b (ca_dout1)
);
ddr3_int_full_mem_model VR
(
// inputs:
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (mem_cs_n),
.mem_dm (mem_dm),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_rst_n (mem_rst_n),
.mem_we_n (mem_we_n),
// outputs:
.global_reset_n (),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqsn)
);
// CREATE CLOCKS.
always begin
#5 pclk = 0;
#5 pclk = 1;
end
always begin
#3 de_clk=0;
#3 de_clk=1;
end
always begin
#20 pll_ref_clk=0;
#20 pll_ref_clk=1;
end
task pci_burst_data;
input [31:0] address;
input [3:0] byte_enables;
input [31:0] data;
begin
// All APB Cycles are at least two cycles long.
if ((address[31:9] == rbase_a[31:9]) && (address[8:2] == 7'h04)) begin
xyw_a_dout[31:12] <= data[31:12];
end else if (address[31:9] == rbase_a[31:9]) begin
// Drawing engine register accesses
psel = 1'b1;
pwrite = 1'b1;
penable = 1'b0;
paddr = address[31:2];
pwdata = data;
@(posedge pclk);
#1;
penable = 1'b1;
#1;
while(pslverr | ~pready) begin
@(posedge pclk);
#1;
psel = 1'b1;
end
@(posedge pclk);
#1;
psel = 1'b0;
pwrite = 1'b0;
penable = 1'b0;
end else if (address[31:12] == xyw_a_dout) begin // if (address[31:9] == rbase_a[31:9])
// Drawing engine cache access
psel = 1'b1;
pwrite = 1'b1;
penable = 1'b0;
paddr = address[31:2];
pwdata = data;
@(posedge pclk);
#1;
penable = 1'b1;
@(posedge pclk);
#1;
psel = 1'b0;
pwrite = 1'b0;
penable = 1'b0;
end else if (address[31:8] == rbase_w[31:8]) begin // if (address[31:9] == rbase_a[31:9])
case (address[7:2])
// MW0_CTRL register (addr= {RBASE_W,x0000})
//6'h00: begin
//if (!byte_enables[0]) mw0_ctrl_dout_0 <= data[7:0];
//if (!byte_enables[2]) mw0_ctrl_dout_2 <= data[23:16];
//if (!byte_enables[3]) mw0_ctrl_dout_3 <= data[31:24];
//end
// MW0_AD register (addr= {RBASE_W,x0004})
6'h01: begin
if (!byte_enables[1]) mw0_ad_dout[15:12] <= data[15:12];
if (!byte_enables[2]) mw0_ad_dout[23:16] <= data[23:16];
if (!byte_enables[3]) mw0_ad_dout[31:24] <= data[31:24];
end
// MW0_SZ register (addr= {RBASE_W,x0008})
6'h02: begin
if (!byte_enables[0]) mw0_sz_dout <= data[3:0];
end //
// MW0_ORG register (addr= {RBASE_W,x0010 OR RBASE_W,x0014})
6'h04: begin
if (!byte_enables[1]) mw0_org_dout[15:12] <= data[15:12];
if (!byte_enables[2]) mw0_org_dout[23:16] <= data[23:16];
if (!byte_enables[3]) mw0_org_dout[26:24] <= data[26:24];
end
// MW1_CTRL register (addr= {RBASE_W,x0028})
//6'h0a: begin
//if (!byte_enables[0]) mw1_ctrl_dout_0 <= data[7:0];
//if (!byte_enables[2]) mw1_ctrl_dout_2 <= data[23:16];
//if (!byte_enables[3]) mw1_ctrl_dout_3 <= data[31:24];
//end
// MW1_AD register (addr= {RBASE_W,x002C})
6'h0b: begin
if (!byte_enables[1]) mw1_ad_dout[15:12] <= data[15:12];
if (!byte_enables[2]) mw1_ad_dout[23:16] <= data[23:16];
if (!byte_enables[3]) mw1_ad_dout[31:24] <= data[31:24];
end
// MW1_SZ register (addr= {RBASE_W,x0030})
6'h0c: begin
if (!byte_enables[0]) mw1_sz_dout <= data[3:0];
end //
// MW1_ORG register (addr= {RBASE_W,x0010 OR RBASE_W,x003C})
6'h0e: begin
if (!byte_enables[1]) mw1_org_dout[15:12] <= data[15:12];
if (!byte_enables[2]) mw1_org_dout[23:16] <= data[23:16];
if (!byte_enables[3]) mw1_org_dout[26:24] <= data[26:24];
end
endcase // case(hbi_addr_in[7:2])
case (mw0_sz_dout)
4'h0: mw0_mask = 15'b000000000000000; // 4K
4'h1: mw0_mask = 15'b000000000000001; // 8K
4'h2: mw0_mask = 15'b000000000000011; // 16K
4'h3: mw0_mask = 15'b000000000000111; // 32K
4'h4: mw0_mask = 15'b000000000001111; // 64K
4'h5: mw0_mask = 15'b000000000011111; // 128K
4'h6: mw0_mask = 15'b000000000111111; // 256K
4'h7: mw0_mask = 15'b000000001111111; // 512K
4'h8: mw0_mask = 15'b000000011111111; // 1M
4'h9: mw0_mask = 15'b000000111111111; // 2M
4'ha: mw0_mask = 15'b000001111111111; // 4M
4'hb: mw0_mask = 15'b000011111111111; // 8M
4'hc: mw0_mask = 15'b000111111111111; // 16M
4'hd: mw0_mask = 15'b001111111111111; // 32M
4'he: mw0_mask = 15'b011111111111111; // 64M
4'hf: mw0_mask = 15'b111111111111111; // 128M
endcase // case (mw0_sz_dout)
case (mw1_sz_dout)
4'h0: mw1_mask = 15'b000000000000000; // 4K
4'h1: mw1_mask = 15'b000000000000001; // 8K
4'h2: mw1_mask = 15'b000000000000011; // 16K
4'h3: mw1_mask = 15'b000000000000111; // 32K
4'h4: mw1_mask = 15'b000000000001111; // 64K
4'h5: mw1_mask = 15'b000000000011111; // 128K
4'h6: mw1_mask = 15'b000000000111111; // 256K
4'h7: mw1_mask = 15'b000000001111111; // 512K
4'h8: mw1_mask = 15'b000000011111111; // 1M
4'h9: mw1_mask = 15'b000000111111111; // 2M
4'ha: mw1_mask = 15'b000001111111111; // 4M
4'hb: mw1_mask = 15'b000011111111111; // 8M
4'hc: mw1_mask = 15'b000111111111111; // 16M
4'hd: mw1_mask = 15'b001111111111111; // 32M
4'he: mw1_mask = 15'b011111111111111; // 64M
4'hf: mw1_mask = 15'b111111111111111; // 128M
endcase // case (mw1_sz_dout)
@(posedge pclk);
end else if ((address[31:12] ~^ mw0_ad_dout[31:12] |
{7'h0,mw0_mask})==22'h3fffff) begin
// Direct memory access
$display("Write %h to %h ", data, mem_address);
mem_address = mw0_org_dout + {(address[26:12] & mw0_mask), address[11:0]};
if (BYTES == 4) begin
old_mem = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>2];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][31:24] = byte_enables[3] ? old_mem[31:24] :
data[31:24];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][23:16] = byte_enables[2] ? old_mem[23:16] :
data[23:16];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][15:8] = byte_enables[1] ? old_mem[15:8] :
data[15:8];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][7:0] = byte_enables[0] ? old_mem[7:0] :
data[7:0];
end else if (BYTES == 8) begin // if (BYTES == 4)
if (mem_address[2]) begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][63:56] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][55:48] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][47:40] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][39:32] = data[7:0];
end else begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][31:24] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][23:16] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][15:8] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][7:0] = data[7:0];
end
end else begin
old_mem = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>4];
case (mem_address[3:2])
2'h0: begin
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][31:24] = byte_enables[3] ? old_mem[31:24] :
data[31:24];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][23:16] = byte_enables[2] ? old_mem[23:16] :
data[23:16];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][15:8] = byte_enables[1] ? old_mem[15:8] :
data[15:8];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][7:0] = byte_enables[0] ? old_mem[7:0] :
data[7:0];
end // case: begin...
2'h1: begin
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][63:56] = byte_enables[3] ? old_mem[31:24] :
data[31:24];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][55:48] = byte_enables[2] ? old_mem[23:16] :
data[23:16];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][47:40] = byte_enables[1] ? old_mem[15:8] :
data[15:8];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][39:32] = byte_enables[0] ? old_mem[7:0] :
data[7:0];
end // case: begin...
2'h2: begin
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][95:88] = byte_enables[3] ? old_mem[31:24] :
data[31:24];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][87:80] = byte_enables[2] ? old_mem[23:16] :
data[23:16];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][79:72] = byte_enables[1] ? old_mem[15:8] :
data[15:8];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][71:64] = byte_enables[0] ? old_mem[7:0] :
data[7:0];
end // case: begin...
2'h3: begin
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][127:120] = byte_enables[3] ? old_mem[31:24] :
data[31:24];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][119:112] = byte_enables[2] ? old_mem[23:16] :
data[23:16];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][111:104] = byte_enables[1] ? old_mem[15:8] :
data[15:8];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][103:96] = byte_enables[0] ? old_mem[7:0] :
data[7:0];
end // case: begin...
endcase // case (mem_address[3:2])
end
$display("MW0 Access to %h", mem_address);
@(posedge pclk);
end else if ((address[31:12] ~^ mw1_ad_dout[31:12] |
{7'h0,mw1_mask})==22'h3fffff) begin
// Direct memory access
mem_address = mw1_org_dout + {(address[26:12] & mw1_mask), address[11:0]};
$display("Write %h to %h ", data, mem_address);
if (BYTES == 4) begin
old_mem = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>2];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][31:24] = byte_enables[3] ? old_mem[31:24] :
data[31:24];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][23:16] = byte_enables[2] ? old_mem[23:16] :
data[23:16];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][15:8] = byte_enables[1] ? old_mem[15:8] :
data[15:8];
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:2]][7:0] = byte_enables[0] ? old_mem[7:0] :
data[7:0];
end else if (BYTES == 8) begin // if (BYTES == 4)
if (mem_address[2]) begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][63:56] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][55:48] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][47:40] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][39:32] = data[7:0];
end else begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][31:24] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][23:16] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][15:8] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:3]][7:0] = data[7:0];
end
end else begin
old_mem = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>4];
case (mem_address[3:2])
2'h0: begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][31:24] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][23:16] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][15:8] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][7:0] = data[7:0];
end // case: begin...
2'h1: begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][63:56] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][55:48] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][47:40] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][39:32] = data[7:0];
end // case: begin...
2'h2: begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][95:88] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][87:80] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][79:72] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][71:64] = data[7:0];
end // case: begin...
2'h3: begin
if (~byte_enables[3])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][127:120] = data[31:24];
if (~byte_enables[2])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][119:112] = data[23:16];
if (~byte_enables[1])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][111:104] = data[15:8];
if (~byte_enables[0])
VR.ddr3_int_full_mem_model_ram.mem_array[mem_address[31:4]][103:96] = data[7:0];
end // case: begin...
endcase // case (mem_address[3:2])
end
$display("MW1 Access to %h", mem_address);
@(posedge pclk);
end else // if ((address[31:12] ~^ mw1_ad_dout[31:12] |...
@(posedge pclk);
end
endtask // pci_burst_data
task mov_dw;
input [3:0] host_cycle_type;
input [31:0] address;
input [31:0] data;
input [3:0] byte_enables;
input [29:0] NO_OF_BEATS;
begin
if (host_cycle_type == MEM_WR ||
host_cycle_type == CONFIG_WR ||
host_cycle_type == IO_WR)
pci_burst_data(address, byte_enables, data);
end
endtask // mov_dw
task mov_burst;
input [3:0] host_cycle_type;
input [31:0] address;
input [3:0] byte_enables;
input [3:0] NO_OF_BEATS;
input [31:0] data1;
input [31:0] data2;
input [31:0] data3;
input [31:0] data4;
input [31:0] data5;
input [31:0] data6;
input [31:0] data7;
input [31:0] data8;
begin
if (NO_OF_BEATS >= 1) pci_burst_data(address, byte_enables, data1);
if (NO_OF_BEATS >= 2) pci_burst_data(address + 4, byte_enables, data2);
if (NO_OF_BEATS >= 3) pci_burst_data(address + 8, byte_enables, data3);
if (NO_OF_BEATS >= 4) pci_burst_data(address + 12, byte_enables, data4);
if (NO_OF_BEATS >= 5) pci_burst_data(address + 16, byte_enables, data5);
if (NO_OF_BEATS >= 6) pci_burst_data(address + 20, byte_enables, data6);
if (NO_OF_BEATS >= 7) pci_burst_data(address + 24, byte_enables, data7);
if (NO_OF_BEATS == 8) pci_burst_data(address + 28, byte_enables, data8);
end
endtask // mov_burst
task rd;
input [3:0] host_cycle_type;
input [31:0] address;
input [29:0] count; //number of beats in one burst cycle (max= 1G beats)
integer int_count, int_address;
begin
int_count = count; // Load a local copy of the counter
int_address= address;
psel = 1'b0;
while (int_count != 0) begin
if (int_address[31:9] == rbase_a[31:9]) begin
psel = 1'b1;
pwrite = 1'b0;
penable = 1'b0;
paddr = address[31:2];
@(posedge pclk);
#1;
penable = 1'b1;
@(posedge pclk);
test_reg = prdata;
#1;
psel = 1'b0;
penable = 1'b0;
end else if (address[31:12] == xyw_a_dout) begin
psel = 1'b1;
pwrite = 1'b0;
penable = 1'b0;
paddr = address[31:2];
@(posedge pclk);
#1;
penable = 1'b1;
@(posedge pclk);
@(posedge pclk);
test_reg = prdata;
#1;
psel = 1'b0;
penable = 1'b0;
end else if (int_address[31:8] == rbase_g[31:8]) begin
end else if (int_address[31:8] == rbase_i[31:8]) begin
end else if ((address[31:12] ~^ mw0_ad_dout[31:12] |
{7'h0,mw0_mask})==22'h3fffff) begin
// Direct memory access
mem_address = mw0_org_dout + (address[31:12] - mw0_ad_dout[31:12]);
if (BYTES == 4)
test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>2];
else if (BYTES == 8)
case (mem_address[2])
1'b0: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][31:0];
1'b1: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][63:32];
endcase
else
case (mem_address[2])
2'h0: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][31:0];
2'h1: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][63:32];
2'h2: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][95:64];
2'h3: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][127:96];
endcase
end else if ((address[31:12] ~^ mw1_ad_dout[31:12] |
{7'h0,mw1_mask})==22'h3fffff) begin
// Direct memory access
mem_address = mw1_org_dout + (address[31:12] - mw1_ad_dout[31:12]);
if (BYTES == 4)
test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>2];
else if (BYTES == 8)
case (mem_address[2])
1'b0: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][31:0];
1'b1: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][63:32];
endcase
else
case (mem_address[2])
2'h0: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][31:0];
2'h1: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][63:32];
2'h2: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][95:64];
2'h3: test_reg = VR.ddr3_int_full_mem_model_ram.mem_array[mem_address>>3][127:96];
endcase
end
int_address = int_address + 4;
int_count = int_count - 1;
end // while (int_count != 0)
end
endtask // rd
task cpu_mov_dw;
input[3:0] Access;
input[31:0] Address;
input[31:0] Data;
reg[31:0] shift_back, shift_forward;
reg[31:0] Address1, Address2;
reg[31:0] Data1, Data2;
reg[3:0] Mask1, Mask2;
reg[3:0] Strobe1, Strobe2;
reg[3:0] StandardMask ;
reg[3:0] Strobe;
begin
StandardMask = 4'b1111;
shift_back = (Address & 32'h0000_0003);
if (shift_back > 0)
begin
shift_forward = 4 - shift_back;
Address1 = Address - shift_back;
Data1 = Data << (shift_back * 8);
Mask1 = StandardMask << shift_back;
Strobe1 = ~Mask1;
Address2 = Address + shift_forward;
Data2 = Data >> (shift_forward * 8);
Mask2 = StandardMask >> shift_forward;
Strobe2 = ~Mask2;
mov_dw(Access, Address1, Data1, Strobe1, 1);
mov_dw(Access, Address2, Data2, Strobe2, 1);
end
else /* There is no need to shift data. */
begin
Strobe = ~StandardMask;
mov_dw(Access, Address, Data, Strobe, 1);
end
end
endtask // cpu_mov_dw
task cpu_mov_w;
input[3:0] Access;
input[31:0] Address;
input[15:0] Data;
reg[31:0] shift_back;
reg[31:0] Data2;
reg[3:0] StandardMask ;
reg[3:0] Strobe;
begin
StandardMask = 4'b0011;
shift_back = (Address & 32'h0000_0003);
if (shift_back > 2)
begin
mov_dw(Access, Address - 3, Data << 24, 4'b1000, 1);
mov_dw(Access, Address + 1, Data, 4'b0001, 1);
end
else /* Shift the data in the word */
begin
Strobe = ~(StandardMask << shift_back);
Data2 = Data << (shift_back << 3);
mov_dw(Access, Address - shift_back, Data2, Strobe, 1);
end
end
endtask // cpu_mov_w
task cpu_mov_b;
input[3:0] Access;
input[31:0] Address;
input[7:0] Data;
reg[31:0] shift_back, shift_forward;
reg[31:0] NewAddress;
reg[31:0] LongData;
reg[3:0] Mask;
reg[3:0] StandardMask;
reg[3:0] Strobe;
reg[31:0] Long_tmp;
reg[31:0] test_tmp;
begin
LongData = Data;
StandardMask = 4'b0001;
shift_back = (Address & 32'h0000_0003);
if (shift_back > 0)
begin
shift_forward = 4 - shift_back;
NewAddress = Address - shift_back;
LongData = LongData << (shift_back * 8);
Mask = StandardMask << shift_back;
Strobe = ~Mask;
rd(MEM_RD, NewAddress,1);
test_tmp = {test_reg[31:24] & {8{Strobe[3]}},
test_reg[23:16] & {8{Strobe[2]}},
test_reg[15:8] & {8{Strobe[1]}},
test_reg[7:0] & {8{Strobe[0]}}};
Long_tmp = {LongData[31:24] & {8{~Strobe[3]}},
LongData[23:16] & {8{~Strobe[2]}},
LongData[15:8] & {8{~Strobe[1]}},
LongData[7:0] & {8{~Strobe[0]}}};
mov_dw(Access, NewAddress, (Long_tmp | test_tmp), Strobe, 1);
end
else /* There is no need to shift data. */
begin
NewAddress = Address;
Strobe = ~StandardMask;
rd(MEM_RD, NewAddress,1);
test_tmp = {test_reg[31:24] & {8{Strobe[3]}},
test_reg[23:16] & {8{Strobe[2]}},
test_reg[15:8] & {8{Strobe[1]}},
test_reg[7:0] & {8{Strobe[0]}}};
Long_tmp = {LongData[31:24] & {8{~Strobe[3]}},
LongData[23:16] & {8{~Strobe[2]}},
LongData[15:8] & {8{~Strobe[1]}},
LongData[7:0] & {8{~Strobe[0]}}};
mov_dw(Access, NewAddress, (Long_tmp | test_tmp), Strobe, 1);
end
end
endtask // cpu_mov_b
task Verify;
input [31:0] address;
input [7:0] size;
input [31:0] data;
begin
$display("VERIFY ADDRESS %h Size %h", address, size);
$display("VERIFY EXPECTED %h", data);
rd(MEM_RD, address, 1);
$display("VERIFY DATA %h", test_reg);
end
endtask
task Verify_Io;
input [31:0] address;
input [7:0] size;
input [31:0] data;
integer long_addr;
integer byte_enables;
begin
long_addr = address & 32'hFFFFFFFC;
byte_enables = (1 << size) - 1;
byte_enables = byte_enables << (address & 3);
$display("VERIFY ADDRESS %h Size %h", address, size);
$display("VERIFY EXPECTED %h", data);
rd_byte(IO_RD, address, ~byte_enables, 1);
data = (test_reg >> (address & 3)) & ((1 << size) - 1);
$display("VERIFY DATA %h", data);
end
endtask
task initialize;
begin
@(posedge pclk);
bb_rstn = 0;
rbase_io = 32'h9000;
config_en = 1'b1;
repeat (12) @(posedge pclk);
config_en = 1'b0;
repeat (12) @(posedge pclk);
bb_rstn = 1;
// Enable all address decoding
load_base("G",32'h100);
load_base("W",32'h200);
load_base("A",32'h800);
load_base("B",32'h400);
load_base("I",32'h500);
load_base("E",32'h600);
end
endtask // initialize
/***************************************************************************/
/* TASK TO LOAD THE BASE ADDRESSES. */
/***************************************************************************/
task load_base;
input [7:0] reg_string;
input [31:0] reg_address;
begin
if(reg_string=="G") rbase_g = {reg_address[31:8],8'h0};
if(reg_string=="W") rbase_w = {reg_address[31:8],8'h0};
if(reg_string=="A") rbase_a = {reg_address[31:8],8'h0};
if(reg_string=="B") rbase_b = {reg_address[31:8],8'h0};
if(reg_string=="I") rbase_i = {reg_address[31:8],8'h0};
if(reg_string=="E") rbase_e = {reg_address[31:8],8'h0};
end
endtask
/**************************************************************************/
task redhat_wait;
begin
rd(MEM_RD, rbase_a+FLOW,1);
while (test_reg[3] || test_reg[1] || test_reg[0]) rd(MEM_RD, rbase_a+FLOW,1);
end
endtask
/**************************************************************************/
task wait_for_pipe_a;
begin
@(posedge pclk);
rd(MEM_RD, rbase_a+BUSY,1);
while (test_reg[0]) rd(MEM_RD, rbase_a+BUSY,1);
end
endtask
/**************************************************************************/
task wait_for_de_a;
begin
@(posedge pclk);
rd(MEM_RD, rbase_a+FLOW,1);
while (test_reg[0]) rd(MEM_RD, rbase_a+FLOW,1);
end
endtask
/**************************************************************************/
task wait_for_mc_a;
begin
@(posedge pclk);
rd(MEM_RD, rbase_a+FLOW,1);
while (test_reg[1]) rd(MEM_RD, rbase_a+FLOW,1);
repeat (6000) @(posedge pclk);
end
endtask
/**************************************************************************/
task wait_for_prev_a;
begin
@(posedge pclk);
rd(MEM_RD, rbase_a+FLOW,1);
while (test_reg[3]) rd(MEM_RD, rbase_a+FLOW,1);
end
endtask
/**************************************************************************/
task wait_for_crdy_a;
begin
@(posedge pclk);
rd(MEM_RD, rbase_a+BUF_CTRL,1);
while (test_reg[31]) rd(MEM_RD, rbase_a+BUF_CTRL,1);
end
endtask
task wait_for_dlp;
begin
@(posedge pclk);
rd(MEM_RD, rbase_a+32'hFC,1);
while (~test_reg[31]) rd(MEM_RD, rbase_a+32'hFC,1);
end
endtask
/*
task wait_for_eq;
input [31:0] address;
input [4:0] bit_select;
input value;
begin
rd(MEM_RD, address,1);
while ((test_reg[bit_select]) != value) rd(MEM_RD, address,1);
end
endtask
*/
/* Empty tasks to not break tests */
task wait_for_mw0;
begin
@(posedge pclk);
end
endtask
task wait_for_mw1;
begin
@(posedge pclk);
end
endtask
// Main task
initial begin
mw0_org_dout = 32'b0;
mw1_org_dout = 32'b0;
vb_int_tog = 1'b0;
paddr = 30'h0;
pwdata = 0;
pwrite = 1'b0;
psel = 1'b0;
penable = 1'b0;
initialize;
//set up the memory window addresses
pci_burst_data(rbase_a + XYC_AD, 4'h0, 32'h1000_0000); // 4 KBytes
mov_dw(MEM_WR, rbase_w + MW0_AD, 32'h4000_0000, 4'h0, 1);
mov_dw(MEM_WR, rbase_w + MW0_SZ, 32'h0000_000A, 4'h0, 1); // 4 MBytes
mov_dw(MEM_WR, rbase_w + MW1_AD, 32'hA000_0000, 4'h0, 1);
mov_dw(MEM_WR, rbase_w + MW1_SZ, 32'h0000_000A, 4'h0, 1); // 4 MBytes
/* clear interrupt register. */
pci_burst_data(rbase_a+INTP, 4'h0, 32'h0000_0000);
/* clear interrupt mask register. */
pci_burst_data(rbase_a+INTM, 4'h0, 32'h0000_0000);
/* set the buffer control register. */
pci_burst_data(rbase_a+BUF_CTRL, 4'h0, 32'h0000_0000);
/* set the buffer control register. */
pci_burst_data(rbase_a+XYW_AD, 4'h0, 32'h1000_0000);
/* Set the Drawing engine source origins equals zero. */
pci_burst_data(rbase_a+DE_SORG,4'h0,32'h0000_0000);
pci_burst_data(rbase_a+DE_DORG,4'h0,32'h0000_0000);
/* Drawing engine KEY equals zero. */
pci_burst_data(rbase_a+DE_KEY,4'h0,32'h0000_0000);
/* Set the Drawing engine pitches = 40h (64x16bytes=1024). */
pci_burst_data(rbase_a+DE_SPTCH,4'h0,32'h0000_0400);
pci_burst_data(rbase_a+DE_DPTCH,4'h0,32'h0000_0400);
/* Drawing engine foreground = ffff. */
pci_burst_data(rbase_a+FORE,4'h0,32'h9999_9999);
/* Drawing engine background = bbbb. */
pci_burst_data(rbase_a+BACK,4'h0,32'hbbbb_bbbb);
/* Drawing engine plane mask = ffffffff. */
pci_burst_data(rbase_a+MASK,4'h0,32'hffff_ffff);
/* Drawing engine line pattern register = ffffffff. */
pci_burst_data(rbase_a+LPAT,4'h0,32'hffff_ffff);
/* Drawing engine line pattern control register = 0. */
pci_burst_data(rbase_a+PCTRL,4'h0,32'h0000_0000);
/* Drawing engine clipping top left corner (0,0). */
pci_burst_data(rbase_a+CLPTL,4'h0,32'h0000_0000);
/* Drawing engine clipping bottom right corner (1024,1024). */
pci_burst_data(rbase_a+CLPBR,4'h0, 32'h03ff_03ff);
pci_burst_data(rbase_a + XYC_AD, 4'h0, 32'h1000_0400); // 4 KBytes
// Wait for the DDR2 Controller to come up
wait (u_core.init_done);
$display("DDR3 Contoller now up.");
`include "the_test.h"
$stop;
end
function [7:0] hdf_rot;
input [7:0] din;
hdf_rot = {din[0], din[1], din[2], din[3], din[4], din[5], din[6], din[7]};
endfunction //
endmodule
|
module fpga_top
(
input wire RSTN,
input wire clk_sys,
input wire clk,
input wire SW4N,
input wire SW5N,
output wire [7:0] SEG_A,
output wire [7:0] SEG_B,
output wire [7:0] SEG_C,
output wire [7:0] SEG_D,
output wire [7:0] SEG_E,
output wire [7:0] SEG_F,
output wire [7:0] SEG_G,
output wire [7:0] SEG_H,
output wire [8:0] SEG_SEL_IK
);
parameter
N_IN = 7,
N_OUT = 90;
reg req;
reg [N_IN-1:0] n;
wire ack;
wire [N_OUT-1:0] result;
// detect falling edge
reg [1:0] ff_sw4 = 0;
reg [1:0] ff_sw5 = 0;
always @(posedge clk) begin
ff_sw4 <= {ff_sw4[0], SW4N};
ff_sw5 <= {ff_sw5[0], SW5N};
end
wire tri_sw4 = (ff_sw4 == 2'b10);
wire tri_sw5 = (ff_sw5 == 2'b10);
always @(posedge clk or negedge RSTN) begin
if(~RSTN)
req <= 0;
else if(tri_sw4) begin
req <= 1;
n <= 60;
end
else if(tri_sw5)
req <= 0;
end
fib
#(
.N_IN ( N_IN ) ,
.N_OUT ( N_OUT )
) fib_1
(
.rst_n ( RSTN ) ,
.clk ( clk ) ,
.req ( req ) ,
.n ( n ) ,
.ack ( ack ) ,
.result ( result )
);
/* 7SEG LED
+--------+--------+--------+--------+
| data0 | data1 | data2 | data3 |
+--------+--------+--------+--------+
| data4 | data5 | data6 | data7 |
+--------+--------+--------+--------+
| data8 | data9 | data10 | data11 |
+--------+--------+--------+--------+
| data12 | data13 | data14 | data15 |
+--------+--------+--------+--------+
*/
displayIK_7seg_16
_displayIK_7seg_16
(
.RSTN ( RSTN ),
.CLK ( clk_sys ),
.data0 ( {3'h0, clk, 3'h0, RSTN, 8'h00} ),
.data1 ( {3'h0, SW4N, 3'h0, SW5N, 3'h0, req, 3'h0, ack} ),
.data2 ( 0 ) ,
.data3 ( n ) ,
.data4 ( result[89:64] ) ,
.data5 ( result[63:48] ) ,
.data6 ( result[47:32] ) ,
.data7 ( result[31:16] ) ,
.data8 ( result[15: 0] ) ,
.data9 ( 0 ) ,
.data10 ( 0 ) ,
.data11 ( 0 ) ,
.data12 ( 0 ) ,
.data13 ( 0 ) ,
.data14 ( 0 ) ,
.data15 ( 0 ) ,
.SEG_A ( SEG_A ) ,
.SEG_B ( SEG_B ) ,
.SEG_C ( SEG_C ) ,
.SEG_D ( SEG_D ) ,
.SEG_E ( SEG_E ) ,
.SEG_F ( SEG_F ) ,
.SEG_G ( SEG_G ) ,
.SEG_H ( SEG_H ) ,
.SEG_SEL ( SEG_SEL_IK )
);
endmodule
|
Require Import Coq.Strings.String.
Require Import Coq.Lists.List.
Require Import Coq.micromega.Lia.
Require Import Coq.ZArith.ZArith.
Require Import bedrock2.Array.
Require Import bedrock2.Map.Separation.
Require Import bedrock2.Map.SeparationLogic.
Require Import bedrock2.ProgramLogic.
Require Import bedrock2.Scalars.
Require Import bedrock2.Semantics.
Require Import bedrock2.Syntax.
Require Import bedrock2.Loops.
Require Import bedrock2.WeakestPrecondition.
Require Import bedrock2.WeakestPreconditionProperties.
Require Import coqutil.Word.Interface.
Require Import coqutil.Word.Properties.
Require Import coqutil.Map.Interface.
Require Import coqutil.Map.Properties.
Require Import coqutil.Tactics.Tactics.
Require Import coqutil.Tactics.syntactic_unify.
Require Import coqutil.Tactics.letexists.
Require Import coqutil.Z.Lia.
Require Import Cava.Util.Nat.
Require Import Cava.Util.List.
Require Import Cava.Util.Tactics.
Require Import Bedrock2Experiments.LibBase.MMIOLabels.
Require Import Bedrock2Experiments.ProgramSemantics32.
Require Import Bedrock2Experiments.StateMachineSemantics.
Require Import Bedrock2Experiments.StateMachineProperties.
Require Import Bedrock2Experiments.Tactics.
Require Import Bedrock2Experiments.WhileProperties.
Require Import Bedrock2Experiments.Word.
Require Import Bedrock2Experiments.WordProperties.
Require Import Bedrock2Experiments.Aes.AesSemantics.
Require Import Bedrock2Experiments.Aes.Aes.
Require Import Bedrock2Experiments.Aes.Constants.
Require Import Bedrock2Experiments.LibBase.AbsMMIOProperties.
Import Syntax.Coercions List.ListNotations.
Local Open Scope string_scope.
Local Open Scope list_scope.
Local Open Scope Z_scope.
(* bedrock2.ProgramLogic does cbv, which unfolds the getters of aes_constants,
resulting in large ugly ASTs *)
Ltac normalize_body_of_function f ::= Tactics.rdelta.rdelta f.
Section Proofs.
Context {word: word.word 32} {mem: map.map word Byte.byte}
{word_ok: word.ok word} {mem_ok: map.ok mem}
{ASpec: AesSpec}
{consts : aes_constants Z} {timing : timing}
{consts_ok : aes_constants_ok consts}.
(* Plug in the right state machine parameters; typeclass inference struggles here *)
Local Notation execution := (execution (M := aes_state_machine)).
(***** General-purpose lemmas/tactics and setup *****)
Add Ring wring : (Properties.word.ring_theory (word := word))
(preprocess [autorewrite with rew_word_morphism],
morphism (Properties.word.ring_morph (word := word)),
constants [Properties.word_cst]).
Existing Instance constant_literals | 10.
(* tactic to simplify side conditions in terms of [dexpr] *)
Local Ltac dexpr_hammer :=
subst_lets;
repeat first [ progress push_unsigned
| rewrite word.unsigned_of_Z in *
| rewrite word.wrap_small in * by lia
| destruct_one_match
| lia
| progress ring_simplify
| reflexivity ].
Lemma execution_unique (t : trace) s1 s2 :
execution t s1 ->
execution t s2 ->
s1 = s2.
Proof.
eapply StateMachineProperties.execution_unique; intros;
cbn [state_machine.is_initial_state state_machine.read_step state_machine.write_step
aes_state_machine] in *;
subst; try reflexivity.
all:logical_simplify; subst.
all:cbv [write_step read_step] in *; subst.
all:repeat destruct_one_match_hyp; try congruence.
all:logical_simplify; subst.
all:lazymatch goal with
| H : False |- _ => contradiction H
| H1 : ?x = Some ?a, H2 : ?x = Some ?b |- _ =>
rewrite H1 in H2; inversion H2; clear H2; subst
| _ => idtac
end.
all:reflexivity.
Qed.
Local Ltac infer_states_equal :=
repeat lazymatch goal with
| H1 : execution ?t _, H2 : execution ?t _ |- _ =>
pose proof execution_unique _ _ _ H1 H2; subst;
clear H2; one_goal_or_solved ltac:(try congruence)
end.
Local Ltac infer_state_data_equal :=
repeat lazymatch goal with
| H : IDLE _ = IDLE _ |- _ => inversion H; clear H; subst
| H : BUSY _ _ _ = BUSY _ _ _ |- _ => inversion H; clear H; subst
| H : DONE _ = DONE _ |- _ => inversion H; clear H; subst
end.
Local Ltac infer :=
repeat first [ progress infer_states_equal
| progress infer_state_data_equal
| match goal with
| H: state_machine.read_step _ _ _ _ _ |- _ => apply proj2 in H
| H: state_machine.write_step _ _ _ _ _ |- _ => apply proj2 in H
end ].
(* TODO: lots of annoying bit arithmetic here, maybe try to clean it up *)
Lemma status_read_always_ok s :
exists val s', read_step s STATUS val s'.
Proof.
assert (forall x y : word,
word.slu (word.of_Z 1) x <> word.slu (word.of_Z 1) y -> x <> y)
as Hshift_neq by (intros; subst; congruence).
pose proof status_flags_unique_and_nonzero as Hflags.
simplify_unique_words_in Hflags.
repeat match goal with
| H : _ |- _ => apply Hshift_neq in H
end.
pose proof status_flags_inbounds as Hbounds.
repeat lazymatch goal with
| H : Forall _ (_ :: _) |- _ =>
pose proof (Forall_inv H);
apply Forall_inv_tail in H
| H : Forall _ [] |- _ => clear H
end.
cbv beta in *.
destruct s; unfold read_step; cbn [read_step reg_category status_matches_state].
{ exists (word.of_Z 0). eexists; ssplit; try reflexivity; [].
cbv [is_flag_set]. boolsimpl.
rewrite !word.eqb_eq; [ reflexivity | apply word.unsigned_inj .. ].
all:push_unsigned; rewrite Z.land_0_l; reflexivity. }
{ exists (word.or (word.slu (word.of_Z 1) (word.of_Z AES_STATUS_IDLE))
(word.slu (word.of_Z 1) (word.of_Z AES_STATUS_INPUT_READY))).
eexists; ssplit; try reflexivity; [].
cbv [is_flag_set]. boolsimpl.
repeat lazymatch goal with
| |- (_ && _)%bool = true => apply Bool.andb_true_iff; split
| |- negb _ = true => apply Bool.negb_true_iff
end.
all:rewrite word.unsigned_eqb.
all:first [ apply Z.eqb_eq | apply Z.eqb_neq ].
all:try lazymatch goal with
| |- word.unsigned (word.and ?x ?y) <> _ =>
let H := fresh in
assert (word.unsigned (word.and x y) = word.unsigned y)
as H;
[ | rewrite H; intro Heq; apply word.unsigned_inj in Heq;
cbn in *; congruence ]
end.
all:push_unsigned; cbv [word.wrap]; rewrite <-!Z.land_ones by lia;
bitblast.Z.bitblast.
all:rewrite !Z_testbit_1_l;
repeat lazymatch goal with
| |- context [?x =? ?y] =>
destr (x =? y)
end.
all:boolsimpl; try reflexivity.
all:subst.
all:lazymatch goal with
| H1 : ?i - ?x = 0,
H2 : ?i - ?y = 0 |- _ =>
assert (word.of_Z x = word.of_Z y) by (f_equal; lia)
end.
all:cbn in *; congruence. }
{ exists (word.slu (word.of_Z 1) (word.of_Z AES_STATUS_OUTPUT_VALID)).
destruct data. rewrite is_flag_set_shift by (cbv [boolean]; tauto || lia).
rewrite word.eqb_ne by
(intro Heq; apply word.of_Z_inj_small in Heq; lia).
cbn [negb]. eauto. }
{ exists (word.slu (word.of_Z 1) (word.of_Z AES_STATUS_OUTPUT_VALID)).
eexists; ssplit; try reflexivity; [].
rewrite is_flag_set_shift by (cbv [boolean]; tauto || lia).
rewrite word.eqb_ne by
(intro Heq; apply word.of_Z_inj_small in Heq; lia).
rewrite !is_flag_set_shift_neq by
(cbv [boolean];
first [ tauto | lia
| intro; cbn in *; congruence ]).
reflexivity. }
Qed.
(* solve common side conditions from interactions *)
Local Ltac post_interaction :=
lazymatch goal with
| |- dexprs _ _ _ _ => repeat straightline_with_map_lookup; reflexivity
| |- reg_addr _ = _ => reflexivity
| |- execution _ _ => eassumption
| |- ?G => tryif is_lia G then lia else eauto
end.
Lemma interact_read_status s call bind addre t m l
(post : trace -> mem -> locals -> Prop) addr :
dexprs m l [addre] [addr] ->
reg_addr STATUS = addr ->
execution t s ->
(forall s' val,
read_step s STATUS val s' ->
(* implied by other preconditions but convenient to have separately *)
execution ((map.empty, READ32, [addr], (map.empty, [val])) :: t) s' ->
post ((map.empty, READ32, [addr], (map.empty, [val])) :: t)
m (map.put l bind val)) ->
cmd call (cmd.interact [bind] READ32 [addre]) t m l post.
Proof.
intros; eapply (interact_read 4); intros; infer;
cbv [state_machine.read_step aes_state_machine] in *;
eauto.
pose proof status_read_always_ok s. logical_simplify.
do 3 eexists; eauto.
Qed.
Lemma reg_is_status :
forall r,
reg_addr r = word.of_Z AES_STATUS0 ->
r = STATUS.
Proof.
intros.
destruct r; apply reg_addr_unique; eauto.
Qed.
Lemma reg_is_ctrl :
forall r,
reg_addr r = word.of_Z AES_CTRL0 ->
r = CTRL.
Proof.
intros.
destruct r; apply reg_addr_unique; eauto.
Qed.
Local Ltac infer_reg_using_addr :=
lazymatch goal with
| H: reg_addr _ = word.of_Z AES_STATUS0 |- _ => apply reg_is_status in H; subst
| H: reg_addr _ = word.of_Z AES_CTRL0 |- _ => apply reg_is_ctrl in H; subst
end.
Lemma read_flag_from_status
(functions : list (string * (list string * list string * Syntax.cmd)))
(H : spec_of_abs_mmio_read32 functions)
(tr : trace)
(m : mem)
(R : mem -> Prop)
(s : state)
(H0 : R m)
(H1 : execution tr s)
(i : Z)
(* Hi below needs to go away once the issue #854 is fixed *)
(Hi : i <= i) :
call functions AbsMMIO.abs_mmio_read32 tr m [word.of_Z AES_STATUS0]
(fun (t : trace) (m0 : mem) (rets : list word) =>
exists l : locals,
map.putmany_of_list_zip ["status"] rets map.empty = Some l /\
cmd (call functions)
(cmd.set "out"
(expr.op bopname.and "status"
(expr.op bopname.slu 1 i))) t m0 l
(fun (t0 : trace) (m1 : mem) (l0 : locals) =>
list_map (get l0) ["out"]
(fun rets0 : list word =>
exists (status out : word) (s' : state),
execution t0 s' /\
read_step s STATUS status s' /\
R m1 /\
rets0 = [out] /\
word.eqb out (word.of_Z 0) =
negb (is_flag_set status i)))).
Proof.
(* call function abs_mmio_read32 *)
pose proof status_read_always_ok s as Hstat.
destruct Hstat as (x & s' & Hstat).
straightline_call; ssplit.
(* specialize abs_mmio to AES STATUS *)
{ instantiate ( 1 := STATUS ). reflexivity. }
{ cbv [state_machine.read_step aes_state_machine] in *. eauto. }
{ eauto. }
{ repeat straightline.
(* keep "execution a x" for later eassumption *)
repeat lazymatch goal with
| H0 : execution tr _, H1: execution ?a _ |- context [?tr] => rename H0 into Hexec; rename H1 into Hexec'
end.
pose proof Hexec' as HH.
simpl in Hexec'.
destruct Hexec'.
lazymatch goal with
| H: execution tr ?x /\ step _ _ _ _ _ |- _ => destruct H; replace s with x in *
end.
2:{ eapply execution_unique; eauto. }
lazymatch goal with
| H: step _ _ _ _ _ |- _ => unfold step in H; simpl in H
end.
logical_simplify.
infer_reg_using_addr.
do 3 eexists; ssplit; eauto.
lazymatch goal with
| H: [_] = [_] |- _ => inversion H; subst
end.
subst_lets. cbv [is_flag_set]. boolsimpl. reflexivity.
}
Qed.
Lemma interact_write_control s call addre vale t m l
(post : trace -> mem -> locals -> Prop) addr val :
dexprs m l [addre; vale] [addr; val] ->
reg_addr CTRL = addr ->
execution t s ->
match s with
| IDLE _ => True
| UNINITIALIZED => True
| _ => False
end ->
(forall s',
write_step s CTRL val s' ->
(* implied by other preconditions but convenient to have separately *)
execution ((map.empty, WRITE32, [addr;val], (map.empty, [])) :: t) s' ->
post ((map.empty, WRITE32, [addr;val], (map.empty, [])) :: t) m l) ->
cmd call (cmd.interact [] WRITE32 [addre;vale]) t m l post.
Proof.
intros; eapply (interact_write 4); intros; infer;
cbv [state_machine.write_step aes_state_machine] in *;
eauto.
cbv [write_step]. cbn [reg_category].
exists s; destruct s; try contradiction;
repeat destruct_one_match;
eexists; ssplit; (assumption || reflexivity).
Qed.
Definition key_from_index (i : nat) : Register :=
nth i [KEY0;KEY1;KEY2;KEY3;KEY4;KEY5;KEY6;KEY7] CTRL.
Lemma key_from_index_category i :
(i < 8)%nat -> reg_category (key_from_index i) = KeyReg.
Proof.
intros. cbv [key_from_index].
apply Forall_nth; [ | length_hammer ].
repeat constructor.
Qed.
Lemma interact_write_key i call addre vale t m l
(post : trace -> mem -> locals -> Prop) rs (addr val: word) :
dexprs m l [addre; vale] [addr; val] ->
addr = word.add (word.of_Z AES_KEY00) (word.mul (word.of_Z (Z.of_nat i)) (word.of_Z 4)) ->
(i < 8)%nat ->
execution t (IDLE rs) ->
(forall s',
write_step (IDLE rs) (key_from_index i) val s' ->
(* implied by other preconditions but convenient to have separately *)
execution ((map.empty, WRITE32, [addr;val], (map.empty, [])) :: t) s' ->
post ((map.empty, WRITE32, [addr;val], (map.empty, [])) :: t) m l) ->
cmd call (cmd.interact [] WRITE32 [addre;vale]) t m l post.
Proof.
intros; eapply (interact_write 4); intros; infer;
cbv [state_machine.write_step aes_state_machine] in *;
eauto.
{ repeat (destruct i; try lia); subst; cbn; ring. }
{ cbv [write_step]. rewrite key_from_index_category by lia.
exists (IDLE rs). eexists; ssplit; eauto. }
Qed.
Definition iv_from_index (i : nat) : Register :=
nth i [IV0;IV1;IV2;IV3] CTRL.
Lemma iv_from_index_category i :
(i < 4)%nat -> reg_category (iv_from_index i) = IVReg.
Proof.
intros. cbv [iv_from_index].
apply Forall_nth; [ | length_hammer ].
repeat constructor.
Qed.
Lemma interact_write_iv i call addre vale t m l
(post : trace -> mem -> locals -> Prop) rs addr val :
dexprs m l [addre; vale] [addr; val] ->
addr = word.add (word.of_Z AES_IV00) (word.mul (word.of_Z (Z.of_nat i)) (word.of_Z 4)) ->
(i < 4)%nat ->
execution t (IDLE rs) ->
(forall s',
write_step (IDLE rs) (iv_from_index i) val s' ->
(* implied by other preconditions but convenient to have separately *)
execution ((map.empty, WRITE32, [addr;val], (map.empty, [])) :: t) s' ->
post ((map.empty, WRITE32, [addr;val], (map.empty, [])) :: t) m l) ->
cmd call (cmd.interact [] WRITE32 [addre;vale]) t m l post.
Proof.
intros; eapply (interact_write 4); intros; infer;
cbv [state_machine.write_step aes_state_machine] in *;
eauto.
{ repeat (destruct i; try lia); subst; cbn; ring. }
{ cbv [write_step]. rewrite iv_from_index_category by lia.
exists (IDLE rs). eexists; ssplit; eauto. }
Qed.
Definition data_in_from_index (i : nat) : Register :=
nth i [DATA_IN0;DATA_IN1;DATA_IN2;DATA_IN3] CTRL.
Lemma data_in_from_index_category i :
(i < 4)%nat -> reg_category (data_in_from_index i) = DataInReg.
Proof.
intros. cbv [data_in_from_index].
apply Forall_nth; [ | length_hammer ].
repeat constructor.
Qed.
Lemma interact_write_data_in i call addre vale t m l
(post : trace -> mem -> locals -> Prop) rs addr val :
dexprs m l [addre; vale] [addr; val] ->
addr = word.add (word.of_Z AES_DATA_IN00) (word.mul (word.of_Z (Z.of_nat i)) (word.of_Z 4)) ->
(i < 4)%nat ->
execution t (IDLE rs) ->
(forall s',
write_step (IDLE rs) (data_in_from_index i) val s' ->
(* implied by other preconditions but convenient to have separately *)
execution ((map.empty, WRITE32, [addr;val], (map.empty, [])) :: t) s' ->
post ((map.empty, WRITE32, [addr;val], (map.empty, [])) :: t) m l) ->
cmd call (cmd.interact [] WRITE32 [addre;vale]) t m l post.
Proof.
intros; eapply (interact_write 4); intros; infer;
cbv [state_machine.write_step aes_state_machine] in *;
eauto.
{ repeat (destruct i; try lia); subst; cbn; ring. }
{ cbv [write_step]. rewrite data_in_from_index_category by lia.
exists (IDLE rs). destruct_one_match; eexists; ssplit; eauto. }
Qed.
Definition data_out_from_index (i : nat) : Register :=
nth i [DATA_OUT0;DATA_OUT1;DATA_OUT2;DATA_OUT3] CTRL.
Lemma data_out_from_index_category i :
(i < 4)%nat -> reg_category (data_out_from_index i) = DataOutReg.
Proof.
intros. cbv [data_out_from_index].
apply Forall_nth; [ | length_hammer ].
repeat constructor.
Qed.
Lemma interact_read_data_out i call addre bind (t : trace) m l
(post : trace -> mem -> locals -> Prop) data addr val :
dexprs m l [addre] [addr] ->
addr = word.add (word.of_Z AES_DATA_OUT00) (word.mul (word.of_Z (Z.of_nat i)) (word.of_Z 4)) ->
(i < 4)%nat ->
match data_out_from_index i with
| DATA_OUT0 => done_data_out0 data
| DATA_OUT1 => done_data_out1 data
| DATA_OUT2 => done_data_out2 data
| DATA_OUT3 => done_data_out3 data
| _ => None
end = Some val ->
execution t (DONE data) ->
(forall s' val,
read_step (DONE data) (data_out_from_index i) val s' ->
(* implied by other preconditions but convenient to have separately *)
execution ((map.empty, READ32, [addr], (map.empty, [val])) :: t) s' ->
post ((map.empty, READ32, [addr], (map.empty, [val])) :: t)
m (map.put l bind val)) ->
cmd call (cmd.interact [bind] READ32 [addre]) t m l post.
Proof.
intros; eapply (interact_read 4) with (r:=data_out_from_index i);
intros; infer;
cbv [state_machine.read_step aes_state_machine] in *;
eauto.
{ repeat (destruct i; try lia); subst; cbn; ring. }
{ cbv [read_step]. rewrite data_out_from_index_category by lia.
exists (DONE data). repeat (destruct i; try lia); subst.
all:cbn [data_out_from_index nth read_output_reg] in *.
all:match goal with H : _ = Some _ |- _ => rewrite H end.
all:do 2 eexists; ssplit; eauto. }
Qed.
Lemma get_aes_input_none data :
(idle_data_in0 data = None
\/ idle_data_in1 data = None
\/ idle_data_in2 data = None
\/ idle_data_in3 data = None) ->
get_aes_input data = None.
Proof.
cbv [get_aes_input]. destruct data; cbn; intros.
repeat lazymatch goal with
| H : _ \/ _ |- _ => destruct H
| H : ?x = None |- _ => rewrite H
end.
all:repeat destruct_one_match; reflexivity.
Qed.
(* apply interact_read_status and do some post-processing *)
Local Ltac read_status :=
eapply interact_read_status; [ try post_interaction .. | ].
(* apply interact_write_status and do some post-processing *)
Local Ltac write_control :=
eapply interact_write_control; [ try post_interaction .. | ].
(* apply interact_write_key and do some post-processing *)
Local Ltac write_key :=
eapply interact_write_key;
[ try post_interaction ..
| intros;
try lazymatch goal with
| H : write_step _ _ _ _ |- _ =>
cbv [write_step] in H;
rewrite key_from_index_category in H by lia; subst
end ].
(* apply interact_write_iv for the nth IV register, and do some
post-processing *)
Local Ltac write_iv_n n :=
eapply interact_write_iv with (i:=n);
[ try post_interaction ..
| intros;
try lazymatch goal with
| H : write_step _ _ _ _ |- _ =>
cbv [write_step] in H;
rewrite iv_from_index_category in H by lia; subst
end ].
(* apply interact_write_data_in for the nth DATA_IN register, and do some
post-processing *)
Local Ltac write_data_in_n n :=
eapply interact_write_data_in with (i:=n);
[ lazymatch goal with
| |- _ = word.add _ _ =>
subst_lets;
cbn [Z.of_nat Pos.of_succ_nat Pos.succ]; ring
| _ => idtac
end;
try post_interaction ..
| intros;
try lazymatch goal with
| H : write_step _ _ _ _ |- _ =>
cbv [write_step] in H;
rewrite data_in_from_index_category in H by lia; subst
end
].
(* same as write_data_in_n but with extra processing to prove we didn't
transition to the BUSY state after the write because there are still
unwritten input registers *)
Local Ltac write_data_in_nonlast_n n :=
write_data_in_n n;
[ ..
| lazymatch goal with
| H : context [match get_aes_input ?d with _ => _ end] |- _ =>
cbn [data_in_from_index nth] in H;
rewrite get_aes_input_none in H
by (cbv [write_input_reg];
repeat match goal with H : ?x = None |- _ => rewrite H end;
tauto)
end
].
(* apply interact_read_data_out for the nth DATA_OUT register, and do some
post-processing *)
Local Ltac read_data_out_n n :=
eapply interact_read_data_out with (i:=n);
[lazymatch goal with
| |- _ = word.add _ _ =>
subst_lets;
cbn [Z.of_nat Pos.of_succ_nat Pos.succ]; ring
| _ => idtac
end;
try post_interaction ..
| intros;
try lazymatch goal with
| H : read_step _ _ _ _ |- _ =>
cbv [read_step] in H;
rewrite data_out_from_index_category in H by lia;
cbn [read_step read_output_reg data_out_from_index nth] in H;
cbn [done_data_out0 done_data_out1 done_data_out2 done_data_out3] in H;
destruct H as [? [H ?]];
inversion H; clear H; subst
end
];
(* try eauto on leftover side conditions now that evars have been filled
in *)
[
cbn [data_out_from_index nth done_data_out0 done_data_out1
done_data_out2 done_data_out3];
eauto .. | ].
Local Notation aes_op_t := (enum_member (aes_op (aes_constants_ok := consts_ok))) (only parsing).
Local Notation aes_mode_t := (enum_member (aes_mode (aes_constants_ok := consts_ok))) (only parsing).
Local Notation aes_key_len_t := (enum_member (aes_key_len (aes_constants_ok := consts_ok))) (only parsing).
Definition ctrl_operation (ctrl : word) : bool :=
is_flag_set ctrl AES_CTRL_OPERATION.
Definition ctrl_mode (ctrl : word) : word :=
select_bits ctrl (word.of_Z AES_CTRL_MODE_OFFSET) (word.of_Z AES_CTRL_MODE_MASK).
Definition ctrl_key_len (ctrl : word) : word :=
select_bits ctrl (word.of_Z AES_CTRL_KEY_LEN_OFFSET) (word.of_Z AES_CTRL_KEY_LEN_MASK).
Definition ctrl_manual_operation (ctrl : word) : bool :=
is_flag_set ctrl AES_CTRL_MANUAL_OPERATION.
(***** Proofs for specific functions *****)
Global Instance spec_of_aes_data_ready : spec_of "b2_data_ready" :=
fun function_env =>
forall (tr : trace) (m : mem) (R : _ -> Prop) (s : state),
(* no special requirements of the memory *)
R m ->
(* no constraints on current state *)
execution tr s ->
call function_env aes_data_ready tr m []
(fun tr' m' rets =>
exists (status out : word) (s' : state),
(* the new state matches the new trace *)
execution tr' s'
(* ...and there exists a single valid status-read step between
the old and new state, and the read result was [status] *)
/\ read_step s STATUS status s'
(* ...and all the same properties as before hold on the memory *)
/\ R m'
(* ...and there is one output value *)
/\ rets = [out]
(* ...and the output value is zero if and only if the
input_ready flag is unset *)
/\ word.eqb out (word.of_Z 0)
= negb (is_flag_set status AES_STATUS_INPUT_READY)).
Lemma aes_data_ready_correct :
program_logic_goal_for_function! aes_data_ready.
Proof.
repeat straightline.
subst l. subst args.
apply read_flag_from_status; eauto.
lia.
Qed.
Global Instance spec_of_aes_data_valid : spec_of "b2_data_valid" :=
fun function_env =>
forall (tr : trace) (m : mem) (R : _ -> Prop) (s : state),
(* no special requirements of the memory *)
R m ->
(* no constraints on current state *)
execution tr s ->
call function_env aes_data_valid tr m []
(fun tr' m' rets =>
exists (status out : word) (s' : state),
(* the new state matches the new trace *)
execution tr' s'
(* ...and there exists a single valid status-read step between
the old and new state, and the read result was [status] *)
/\ read_step s STATUS status s'
(* ...and all the same properties as before hold on the memory *)
/\ R m'
(* ...and there is one output value *)
/\ rets = [out]
(* ...and the output value is zero if and only if the
output_valid flag is unset *)
/\ word.eqb out (word.of_Z 0)
= negb (is_flag_set status AES_STATUS_OUTPUT_VALID)).
Lemma aes_data_valid_correct :
program_logic_goal_for_function! aes_data_valid.
Proof.
repeat straightline.
subst l. subst args.
apply read_flag_from_status; eauto.
lia.
Qed.
Global Instance spec_of_aes_idle : spec_of "b2_idle" :=
fun function_env =>
forall (tr : trace) (m : mem) (R : _ -> Prop) (s : state),
(* no special requirements of the memory *)
R m ->
(* no constraints on current state *)
execution tr s ->
call function_env aes_idle tr m []
(fun tr' m' rets =>
exists (status out : word) (s' : state),
(* the new state matches the new trace *)
execution tr' s'
(* ...and there exists a single valid status-read step between
the old and new state, and the read result was [status] *)
/\ read_step s STATUS status s'
(* ...and all the same properties as before hold on the memory *)
/\ R m'
(* ...and there is one output value *)
/\ rets = [out]
(* ...and the output value is zero if and only if the idle
flag is unset *)
/\ word.eqb out (word.of_Z 0)
= negb (is_flag_set status AES_STATUS_IDLE)).
Lemma aes_idle_correct :
program_logic_goal_for_function! aes_idle.
Proof.
repeat straightline.
subst l. subst args.
apply read_flag_from_status; eauto.
lia.
Qed.
Global Instance spec_of_aes_init : spec_of "b2_aes_init" :=
fun function_env =>
forall (tr : trace) (m : mem) (R : _ -> Prop)
aes_cfg_operation aes_cfg_mode aes_cfg_key_len
aes_cfg_manual_operation,
(* no special requirements of the memory *)
R m ->
(* circuit must start in UNINITIALIZED state *)
execution tr UNINITIALIZED ->
(* operation must be in the aes_op enum *)
aes_op_t aes_cfg_operation ->
(* mode must be in the aes_mode enum *)
aes_mode_t aes_cfg_mode ->
(* key length must be in the aes_key_len enum *)
aes_key_len_t aes_cfg_key_len ->
(* manual_operation is a boolean *)
boolean aes_cfg_manual_operation ->
let args := [aes_cfg_operation; aes_cfg_mode; aes_cfg_key_len;
aes_cfg_manual_operation] in
call function_env aes_init tr m args
(fun tr' m' rets =>
(* the circuit is in IDLE state with the correct control
register value and no other known register values *)
(exists ctrl,
execution tr' (IDLE (Build_idle_data ctrl None None None None
None None None None
None None None None
None None None None))
/\ ctrl_operation ctrl = negb (word.eqb aes_cfg_operation (word.of_Z 0))
/\ ctrl_mode ctrl = aes_cfg_mode
/\ ctrl_key_len ctrl = aes_cfg_key_len
/\ ctrl_manual_operation ctrl
= negb (word.eqb aes_cfg_manual_operation (word.of_Z 0)))
(* ...and the same properties as before hold on the memory *)
/\ R m'
(* ...and there is no output *)
/\ rets = []).
Lemma aes_init_correct :
program_logic_goal_for_function! aes_init.
Proof.
(* initial processing *)
repeat straightline.
straightline_call; ssplit.
{ instantiate ( 1 := CTRL ). reflexivity. }
{ cbv [state_machine.write_step aes_state_machine] in *;
ssplit; eauto.
instantiate ( 2 := UNINITIALIZED ). reflexivity. }
{ eauto. }
repeat straightline.
pose proof H8 as HH.
destruct H8. destruct H6.
replace x0 with UNINITIALIZED in *.
2:{ eapply execution_unique; eauto. }
unfold step in H7. simpl in H7.
logical_simplify.
ssplit; eauto.
unfold write_step in H11.
infer_reg_using_addr. simpl in H11.
(* pose all the control-register formatting proofs *)
pose proof operation_eq.
pose proof mode_mask_eq.
pose proof mode_offset_ok.
pose proof key_len_mask_eq.
pose proof key_len_offset_ok.
pose proof manual_operation_ok.
cbv [op_size] in *.
repeat lazymatch goal with
| H : enum_member _ _ |- _ =>
apply enum_member_size in H;
pose proof has_size_nonneg _ _ H
end.
assert (0 <= AES_CTRL_MODE_MASK < 2 ^ 32). {
rewrite mode_mask_eq.
rewrite Z.ones_equiv.
pose proof Z.pow_lt_mono_r 2 mode_size 32.
pose proof Z.pow_pos_nonneg 2 mode_size.
cbn in *. lia.
}
assert (0 <= AES_CTRL_KEY_LEN_MASK < 2 ^ 32). {
rewrite key_len_mask_eq.
rewrite Z.ones_equiv.
pose proof Z.pow_lt_mono_r 2 key_len_size 32.
pose proof Z.pow_pos_nonneg 2 key_len_size.
cbn in *. lia.
}
eexists. ssplit.
{ subst x. exact HH. }
(* TODO automate in a *robust* way... *)
{ subst x. cbv [ctrl_operation].
rewrite !is_flag_set_or_shiftl_low by lia.
apply is_flag_set_shift; eauto using size1_boolean.
lia.
}
{ subst x. cbv [ctrl_mode].
etransitivity. {
eapply select_bits_or_shiftl_low.
all: rewrite ?word.unsigned_of_Z_nowrap.
1: eassumption.
all: try lia.
}
etransitivity. {
eapply select_bits_or_shiftl_low.
all: rewrite ?word.unsigned_of_Z_nowrap.
1: eassumption.
all: try lia.
}
etransitivity. {
rewrite mode_mask_eq in *.
eapply select_bits_or_shiftl_high.
all: rewrite ?word.unsigned_of_Z_nowrap.
3: {
eapply has_size_ones.
rewrite word.unsigned_of_Z_nowrap; trivial.
}
all: try (cbn in *; lia).
eapply has_size_weaken.
1: eapply has_size_slu.
1: eassumption.
all: rewrite ?word.unsigned_of_Z_nowrap.
all: try (cbn -[Z.add] in *; lia).
}
etransitivity. {
eapply select_bits_id.
1: eassumption.
all: rewrite ?word.unsigned_of_Z_nowrap.
all: try (cbn in *; lia).
}
reflexivity.
}
{ cbv [ctrl_key_len].
etransitivity. {
eapply select_bits_or_shiftl_low.
all: rewrite ?word.unsigned_of_Z_nowrap.
1: eassumption.
all: try lia.
}
etransitivity. {
rewrite key_len_mask_eq in *.
eapply select_bits_or_shiftl_high.
all: rewrite ?word.unsigned_of_Z_nowrap.
3: {
eapply has_size_ones.
rewrite word.unsigned_of_Z_nowrap; trivial.
}
all: try (cbn in *; lia).
eapply has_size_weaken.
{ eapply has_size_or.
{ eapply has_size_slu. 1: eassumption.
rewrite word.unsigned_of_Z_nowrap.
all: try (cbn -[Z.add] in *; lia). }
{ eapply has_size_slu.
{ eapply has_size_and. 1: eassumption.
rewrite mode_mask_eq. eapply has_size_ones.
rewrite word.unsigned_of_Z_nowrap. 1: reflexivity.
cbn in *; lia.
all: try (cbn -[Z.add] in *; lia). }
rewrite word.unsigned_of_Z_nowrap; lia. }
}
rewrite ?word.unsigned_of_Z_nowrap.
all: cbn -[Z.add] in *; try lia.
}
eapply select_bits_id.
1: eassumption.
all: rewrite ?word.unsigned_of_Z_nowrap.
all: try (cbn in *; lia).
}
{ cbv [ctrl_manual_operation].
apply is_flag_set_or_shiftl_high.
1: eassumption.
1: cbn in *; lia.
eapply has_size_weaken.
{ eapply has_size_or.
{ eapply has_size_or.
{ eapply has_size_slu. 1: eassumption.
rewrite word.unsigned_of_Z_nowrap.
all: try (cbn -[Z.add] in *; lia). }
{ eapply has_size_slu.
{ eapply has_size_and. 1: eassumption.
rewrite mode_mask_eq. eapply has_size_ones.
rewrite word.unsigned_of_Z_nowrap. 1: reflexivity.
cbn in *; lia.
all: try (cbn -[Z.add] in *; lia). }
rewrite word.unsigned_of_Z_nowrap; lia. }
}
eapply has_size_slu.
{ eapply has_size_and. 1: eassumption. rewrite key_len_mask_eq.
eapply has_size_ones.
rewrite ?word.unsigned_of_Z_nowrap. 1: reflexivity.
all: cbn -[Z.add] in *; try lia.
}
rewrite ?word.unsigned_of_Z_nowrap.
all: try (cbn in *; lia).
}
rewrite ?word.unsigned_of_Z_nowrap.
all: cbn -[Z.add] in *; try lia.
}
Qed.
Global Instance spec_of_aes_key_put : spec_of "b2_key_put" :=
fun function_env =>
forall (tr : trace) (m : mem) R (data : idle_data)
(key_len key_arr_ptr : word) (key_arr : list word),
(* key_len is a member of the aes_key_len enum *)
aes_key_len_t key_len ->
(* key array is in memory *)
(array scalar32 (word.of_Z 4) key_arr_ptr key_arr * R)%sep m ->
(* key array length matches the key_len argument *)
length key_arr = (if word.eqb key_len (word.of_Z kAes128)
then 4%nat else if word.eqb key_len (word.of_Z kAes192)
then 6%nat else 8%nat) ->
(* circuit must be in IDLE state *)
execution tr (IDLE data) ->
let args := [key_arr_ptr; key_len] in
call function_env aes_key_put tr m args
(fun tr' m' rets =>
(* the circuit is in IDLE state with the key registers updated *)
execution tr'
(IDLE (fold_left
(fun data i =>
write_input_reg (key_from_index i) data (nth i key_arr (word.of_Z 0)))
(seq 0 8) data))
(* ...and the same properties as before hold on the memory *)
/\ (array scalar32 (word.of_Z 4) key_arr_ptr key_arr * R)%sep m'
(* ...and there is no output *)
/\ rets = []).
Lemma aes_key_put_correct :
program_logic_goal_for_function! aes_key_put.
Proof.
(* we want to avoid letting [straightline] go too far here, so we can apply
[cond_nobreak], which requires a [seq] in front of [cond] *)
do 2 straightline. repeat straightline_cleanup.
(* setup: assert useful facts and simplify hypotheses *)
(* assert that key length enum members are unique *)
pose proof enum_unique aes_key_len as key_len_unique.
simplify_unique_words_in key_len_unique.
(* key_len must be one of the members of the aes_key_len enum *)
move H at bottom.
lazymatch goal with
| H : enum_member aes_key_len ?len |- _ =>
cbn in H
end.
(* this assertion helps prove that i does not get truncated *)
assert (9 < 2 ^ 32) by (cbn; lia).
pose proof nregs_key_eq.
(* upper bound key_len *)
assert (4 <= length key_arr <= 8)%nat.
{ lazymatch goal with H : length key_arr = _ |- _ => rewrite H end.
repeat destruct_one_match; lia. }
(* setup done; now we can proceed with the program logic *)
(* after the conditional, num_regs_key_used is set *)
apply cond_nosplit with
(post_cond :=
fun tr' m' l' =>
tr' = tr /\ m' = m
/\ l' = map.put l "num_regs_key_used"
(word.of_Z (Z.of_nat (length key_arr)))).
{ (* prove that the conditional statement fulfills its postcondition *)
(* destruct branches *)
split_if; [ | intros; split_if ]; intros;
repeat lazymatch goal with
| H : word.unsigned _ <> 0 |- _ =>
apply word.if_nonzero, word.eqb_true in H
| H : word.unsigned _ = 0 |- _ =>
apply word.if_zero, word.eqb_false in H
end; subst.
(* destruct nonsensical cases *)
all:repeat (destruct_one_match_hyp_of_type bool;
(* TODO don't use cbn so aggressively *)
cbn -[map.put map.empty] in *; try congruence);
repeat lazymatch goal with
| H : _ \/ _ |- _ => destruct H; try congruence
end; [ ].
all:repeat straightline.
all:ssplit; [ reflexivity .. | ].
all:apply f_equal; subst_lets; apply f_equal.
all:lia. }
repeat straightline.
(* begin first while loop *)
let l := lazymatch goal with |- cmd _ _ _ _ ?l _ => l end in
apply atleastonce_localsmap
with (v0:=length key_arr)
(lt:=lt)
(invariant:=
fun v tr' m' l' =>
(* the new state is the old one plus the first i keys *)
execution
tr'
(IDLE
(fold_left
(fun data i =>
write_input_reg
(key_from_index i) data
(nth i key_arr (word.of_Z 0)))
(seq 0 (length key_arr - v))
data))
(* array accesses in bounds *)
/\ (0 < v <= length key_arr)%nat
(* locals are unaffected except for i *)
/\ l' = map.put l "i" (word.of_Z (Z.of_nat (length key_arr - v)))
(* memory is unaffected *)
/\ (array scalar32 (word.of_Z 4) key_arr_ptr key_arr ⋆ R)%sep m').
{ apply lt_wf. }
{ (* case in which the loop breaks immediately (cannot happen) *)
repeat straightline.
exfalso.
repeat lazymatch goal with
| br := if word.ltu _ _ then _ else _,
H : word.unsigned br = 0 |- _ =>
assert (word.unsigned br <> 0);
[ subst br | congruence ]
| H : length key_arr = _ |- context [length key_arr] =>
rewrite H
| |- context [word.eqb ?x ?y] => destr (word.eqb x y)
| _ => progress push_unsigned
end.
all:destruct_one_match; lia. }
{ (* invariant holds at start of loop *)
rewrite Nat.sub_diag.
ssplit;
lazymatch goal with
| |- ?m = map.put ?m _ _ =>
subst1_map m; rewrite map.put_put_same; reflexivity
| |- sep _ _ _ => ecancel_assumption
| |- (_ < _)%nat => lia
| |- (_ <= _)%nat => lia
| _ => idtac
end.
cbn [firstn fold_left]. eassumption. }
{ (* the body of the loop proves the invariant if it continues and the
postcondition if it breaks *)
repeat straightline.
(* first, we need to find the separation-logic condition and isolate the
key we will be loading *)
(* assertion that matches one of the array_address_inbounds side
conditions *)
let i := lazymatch goal with
| _ := map.put _ "i" (word.of_Z (Z.of_nat ?i)) |- _ => i end in
let a := constr:(word.add key_arr_ptr (word.mul (word.of_Z (Z.of_nat i)) (word.of_Z 4))) in
let offset := constr:(word.sub a key_arr_ptr) in
assert (i = Z.to_nat (word.unsigned offset / word.unsigned (word.of_Z 4))) as Hindex;
[ ring_simplify offset | ].
{ push_unsigned. rewrite (Z.mul_comm 4), Z.div_mul by lia. lia. }
(* rearrangement of Hindex for other side conditions *)
lazymatch type of Hindex with
| ?i = Z.to_nat (word.unsigned ?offset / ?size) =>
assert (word.unsigned offset = Z.of_nat i * size) as Hoffset;
[ ring_simplify offset; push_unsigned; lia | ]
end.
let Hsep :=
lazymatch goal with H : sep _ _ ?m |- cmd _ _ _ ?m _ _ => H end in
pose proof Hsep;
seprewrite_in @array_address_inbounds Hsep; [ | | exact Hindex | ];
[ rewrite Hoffset; push_unsigned; lia
| rewrite Hoffset; push_unsigned; apply Z.mod_mul; lia
| ].
(* seprewrite leaves an evar for a default key; fill it in *)
match goal with
| H : context [List.hd ?d ?l] |- _ =>
is_evar d; unify (List.hd d l) (List.hd (word.of_Z 0) l)
end.
(* now, finally, we can process the loop body *)
(* set key register *)
write_key.
(* rest of loop body *)
repeat straightline.
{ (* "continue" case; prove invariant still holds *)
cbv [Markers.split].
lazymatch goal with
| |- exists v, _ /\ (v < ?oldv)%nat => exists (oldv - 1)%nat; split; [ | lia ]
end.
(* simplify the loop-continue condition (i < length key_arr) *)
match goal with
| H : word.unsigned _ <> 0 |- _ =>
apply word.if_nonzero in H;
rewrite word.unsigned_ltu in H;
apply Z.ltb_lt in H;
rewrite word.unsigned_of_Z, word.wrap_small in H by lia
end.
lazymatch goal with
| l := map.put _ "i" ?i,
H : word.unsigned ?i < _ |- _ =>
subst i;
rewrite word.unsigned_add, word.unsigned_of_Z_1 in H;
rewrite ?word.unsigned_of_Z, ?word.wrap_small in H
by (rewrite ?word.wrap_small; lia)
end.
ssplit;
lazymatch goal with
| |- ?l' = map.put ?l _ _ =>
subst1_map l';
lazymatch goal with
| |- map.put ?l' _ _ = _ =>
subst1_map l'
end;
rewrite map.put_put_same;
f_equal; apply word.unsigned_inj;
push_unsigned; lia
| |- sep _ _ _ => ecancel_assumption
| |- (_ < _)%nat => lia
| |- (_ <= _)%nat => lia
| _ => idtac
end.
lazymatch goal with
| |- context [(length key_arr - (?v - 1))%nat] =>
replace (length key_arr - (v - 1))%nat
with (S (length key_arr - v))%nat by lia
end.
pull_snoc; natsimpl.
rewrite <-!hd_skipn.
eassumption. }
{ (* "break" case; prove postcondition holds after the rest of the function *)
(* simplify the loop-break condition (length key_arr <= i) *)
match goal with
| H : word.unsigned _ = 0 |- _ =>
apply word.if_zero in H;
rewrite word.unsigned_ltu in H;
apply Z.ltb_ge in H;
rewrite word.unsigned_of_Z, word.wrap_small in H by lia
end.
lazymatch goal with
| H : Z.of_nat (length key_arr) <= word.unsigned ?i |- _ =>
subst i; rewrite word.unsigned_add in H;
autorewrite with push_unsigned in H;
rewrite word.wrap_small in H by lia
end.
(* begin second while loop *)
let l := lazymatch goal with |- cmd _ _ _ _ ?l _ => l end in
unfold1_cmd_goal; cbn [cmd_body]; exists nat, lt;
(* invariant *)
exists (fun v tr' m' l' =>
(* the new state is the old one plus the first i keys *)
execution
tr'
(IDLE
(fold_left
(fun data i =>
write_input_reg
(key_from_index i) data
(nth i key_arr (word.of_Z 0)))
(seq 0 (8 - v))
data))
(* bounds for # iterations *)
/\ (v <= 8 - length key_arr)%nat
(* locals are unaffected except for i *)
/\ l' = map.put l "i" (word.of_Z (Z.of_nat (8 - v)))
(* memory is unaffected *)
/\ (array scalar32 (word.of_Z 4) key_arr_ptr key_arr ⋆ R)%sep m').
ssplit.
{ apply lt_wf. }
{ (* invariant holds at loop start *)
exists (8 - length key_arr)%nat. (* total # iterations *)
replace (8 - (8 - length key_arr))%nat with (length key_arr) by lia.
(*
rewrite Nat.sub_diag. cbn [repeat]. rewrite app_nil_r.*)
ssplit;
lazymatch goal with
| |- ?m = map.put ?m _ _ =>
subst1_map m; rewrite map.put_put_same; reflexivity
| |- sep _ _ _ => ecancel_assumption
| |- (_ < _)%nat => lia
| |- (_ <= _)%nat => lia
| _ => idtac
end.
lazymatch goal with
| H : context [write_input_reg _ (fold_left _ (seq 0 ?n) _)]
|- context [fold_left _ (seq 0 ?m)] =>
replace (seq 0 m) with (seq 0 (S n)) by (f_equal; lia)
end.
pull_snoc; natsimpl.
rewrite <-!hd_skipn.
eassumption. }
{ (* the body of the loop proves the invariant if it continues and the
postcondition if it breaks *)
repeat straightline.
split; intros.
{ (* prove that the invariant holds after the loop body *)
(* simplify the loop-continue condition (i < 8) *)
match goal with
| H : word.unsigned _ <> 0 |- _ =>
apply word.if_nonzero in H;
rewrite word.unsigned_ltu in H;
apply Z.ltb_lt in H;
rewrite nregs_key_eq in H;
autorewrite with push_unsigned in H
end.
repeat straightline.
(* set key register *)
write_key.
(* rest of loop body *)
repeat straightline.
(* loop body done; prove invariant still holds *)
(* provide new measure *)
lazymatch goal with
| |- exists v, _ /\ (v < ?oldv)%nat => exists (oldv - 1)%nat; split; [ | lia ]
end.
(* handle most invariant cases *)
ssplit;
lazymatch goal with
| |- ?l' = map.put ?l _ _ =>
subst1_map l';
lazymatch goal with
| |- map.put ?l' _ _ = _ =>
subst1_map l'
end;
rewrite map.put_put_same;
f_equal; apply word.unsigned_inj;
subst_lets; push_unsigned; lia
| |- sep _ _ _ => ecancel_assumption
| |- ?G => tryif is_lia G then lia else idtac
end.
(* final invariant case: new register state *)
(* arithmetic simplification *)
lazymatch goal with
| |- context [(8 - (?v - 1))%nat] =>
replace (8 - (v - 1))%nat
with (S (8 - v))%nat by lia
end.
(* list simplifications *)
pull_snoc; natsimpl; push_nth.
(* solve *)
eassumption. }
{ (* post-loop; given invariant and loop-break condition, prove
postcondition holds after the rest of the function *)
repeat straightline.
(* simplify the loop-break condition (8 <= i) *)
match goal with
| H : word.unsigned _ = 0 |- _ =>
apply word.if_zero in H;
rewrite word.unsigned_ltu in H;
apply Z.ltb_ge in H;
rewrite nregs_key_eq in H;
autorewrite with push_unsigned in H
end.
eexists; ssplit; eauto; [ ].
lazymatch goal with
| H : context [fold_left _ (seq 0 (8 - ?v))] |- _ =>
replace (8 - v)%nat with 8%nat in H by lia
end.
eassumption. } } } }
Qed.
Global Instance spec_of_aes_iv_put : spec_of "b2_iv_put" :=
fun function_env =>
forall (tr : trace) (m : mem) R (data : idle_data)
(iv_ptr : word) (iv_arr : list word),
(* iv array is in memory *)
(array scalar32 (word.of_Z 4) iv_ptr iv_arr * R)%sep m ->
(* iv array has 4 elements *)
length iv_arr = 4%nat ->
(* circuit must be in IDLE state *)
execution tr (IDLE data) ->
call function_env aes_iv_put tr m [iv_ptr]
(fun tr' m' rets =>
(* the circuit is in IDLE state with the iv registers updated *)
execution tr'
(IDLE (fold_left
(fun data i =>
write_input_reg (iv_from_index i) data
(nth i iv_arr (word.of_Z 0)))
(seq 0 4) data))
(* ...and the same properties as before hold on the memory *)
/\ (array scalar32 (word.of_Z 4) iv_ptr iv_arr * R)%sep m'
(* ...and there is no output *)
/\ rets = []).
Lemma aes_iv_put_correct :
program_logic_goal_for_function! aes_iv_put.
Proof.
(* initial processing *)
repeat straightline.
(* simplify array predicate *)
destruct_lists_by_length.
cbn [array] in *.
repeat match goal with
| H : context [scalar32 ?addr] |- _ =>
progress ring_simplify addr in H
end.
pose proof nregs_iv_eq.
(* unroll while loop *)
eapply unroll_while with (iterations:=4%nat). cbn [repeat_logic_step].
repeat straightline.
(* process each iteration of the while loop *)
(* i = 0 *)
split; repeat straightline; [ dexpr_hammer | ].
write_iv_n 0%nat. repeat straightline.
(* i = 1 *)
split; repeat straightline; [ dexpr_hammer | ].
write_iv_n 1%nat; [ subst_lets; ring | ].
repeat straightline.
(* i = 2 *)
split; repeat straightline; [ dexpr_hammer | ].
write_iv_n 2%nat; [ subst_lets; ring | ].
repeat straightline.
(* i = 3 *)
split; repeat straightline; [ dexpr_hammer | ].
write_iv_n 3%nat; [ subst_lets; ring | ].
repeat straightline.
(* i = 4; loop done *)
ssplit; repeat straightline; [ dexpr_hammer | ].
(* done; prove postcondition *)
cbn [array].
repeat match goal with
| |- context [scalar32 ?addr] =>
progress ring_simplify addr
end.
ssplit; eauto.
Qed.
Global Instance spec_of_aes_data_put : spec_of "b2_data_put" :=
fun function_env =>
forall (tr : trace) (m : mem) R (data : idle_data) all_aes_input
(input_ptr : word) (input_arr : list word),
(* input array is in memory *)
(array scalar32 (word.of_Z 4) input_ptr input_arr * R)%sep m ->
(* input array has 4 elements *)
length input_arr = 4%nat ->
(* circuit must be in IDLE state *)
execution tr (IDLE data) ->
(* input-data registers must not be currently set *)
data.(idle_data_in0) = None ->
data.(idle_data_in1) = None ->
data.(idle_data_in2) = None ->
data.(idle_data_in3) = None ->
(* adding input-data registers must result in a full set of data
(i.e. key and iv registers are already set) *)
get_aes_input
(fold_left
(fun data i =>
write_input_reg (data_in_from_index i) data
(nth i input_arr (word.of_Z 0)))
(seq 0 4) data) = Some all_aes_input ->
call function_env aes_data_put tr m [input_ptr]
(fun tr' m' rets =>
(* the circuit is now in the BUSY state *)
execution tr' (BUSY (Build_busy_data
(idle_ctrl data)
(aes_expected_output all_aes_input)
ndelays_core))
(* ...and the same properties as before hold on the memory *)
/\ (array scalar32 (word.of_Z 4) input_ptr input_arr * R)%sep m'
(* ...and there is no output *)
/\ rets = []).
Lemma aes_data_put_correct :
program_logic_goal_for_function! aes_data_put.
Proof.
(* initial processing *)
repeat straightline.
(* simplify array predicate *)
destruct_lists_by_length.
cbn [array] in *.
repeat match goal with
| H : context [scalar32 ?addr] |- _ =>
progress ring_simplify addr in H
end.
pose proof nregs_data_eq.
(* unroll while loop *)
eapply unroll_while with (iterations:=4%nat). cbn [repeat_logic_step].
repeat straightline.
(* process each iteration of the while loop *)
(* i = 0 *)
split; repeat straightline; [ dexpr_hammer | ].
write_data_in_nonlast_n 0%nat. repeat straightline.
(* i = 1 *)
split; repeat straightline; [ dexpr_hammer | ].
write_data_in_nonlast_n 1%nat. repeat straightline.
(* i = 2 *)
split; repeat straightline; [ dexpr_hammer | ].
write_data_in_nonlast_n 2%nat. repeat straightline.
(* i = 3 *)
split; repeat straightline; [ dexpr_hammer | ].
write_data_in_n 3%nat. repeat straightline.
lazymatch goal with
| H1 : get_aes_input (fold_left _ _ _) = Some _,
H2 : context [match get_aes_input _ with _ => _ end] |- _ =>
cbn [fold_left seq nth data_in_from_index] in H1, H2;
rewrite H1 in H2
end.
(* i = 4; loop done *)
ssplit; repeat straightline; [ dexpr_hammer | ].
(* done; prove postcondition *)
cbn [array].
repeat match goal with
| |- context [scalar32 ?addr] =>
progress ring_simplify addr
end.
ssplit; eauto.
Qed.
(* TODO: the real state machine is slightly more complex; AES block can get
input while BUSY and stalls in BUSY state until output is read. The spec
should be modified to account for this behavior. For now, this spec is
exactly the same as aes_data_put. *)
Global Instance spec_of_aes_data_put_wait : spec_of "b2_data_put_wait" :=
fun function_env =>
forall (tr : trace) (m : mem) R (data : idle_data) all_aes_input
(input_ptr : word) (input_arr : list word),
(* input array is in memory *)
(array scalar32 (word.of_Z 4) input_ptr input_arr * R)%sep m ->
(* input array has 4 elements *)
length input_arr = 4%nat ->
(* circuit must be in IDLE state *)
execution tr (IDLE data) ->
(* input-data registers must not be currently set *)
data.(idle_data_in0) = None ->
data.(idle_data_in1) = None ->
data.(idle_data_in2) = None ->
data.(idle_data_in3) = None ->
(* adding input-data registers must result in a full set of data
(i.e. key and iv registers are already set) *)
get_aes_input
(fold_left
(fun data i =>
write_input_reg (data_in_from_index i) data
(nth i input_arr (word.of_Z 0)))
(seq 0 4) data) = Some all_aes_input ->
call function_env aes_data_put_wait tr m [input_ptr]
(fun tr' m' rets =>
(* the circuit is now in the BUSY state *)
execution tr' (BUSY (Build_busy_data
(idle_ctrl data)
(aes_expected_output all_aes_input)
ndelays_core))
(* ...and the same properties as before hold on the memory *)
/\ (array scalar32 (word.of_Z 4) input_ptr input_arr * R)%sep m'
(* ...and there is no output *)
/\ rets = []).
Lemma aes_data_put_wait_correct :
program_logic_goal_for_function! aes_data_put_wait.
Proof.
(* initial processing *)
repeat straightline.
(* we know the circuit is in IDLE state, so loop has exactly 1 iteration *)
eapply unroll_while with (iterations:=1%nat). cbn [repeat_logic_step].
repeat straightline.
split; repeat straightline; [ dexpr_hammer; congruence | ].
(* Call aes_data_ready *)
straightline_call; eauto; [ ].
(* simplify guarantees *)
logical_simplify; subst.
cbn [read_step reg_category] in *.
cbv [status_matches_state] in *.
logical_simplify.
repeat match goal with
| H : (_ && _)%bool = true |- _ => apply Bool.andb_true_iff in H; destruct H
| H : word.eqb _ _ = _ |- _ => apply word.eqb_false in H
| H : is_flag_set _ _ = _ |- _ => progress rewrite H in *
end.
subst.
(* loop done *)
repeat straightline.
split; repeat straightline; [ dexpr_hammer; congruence | ].
(* call aes_data_put *)
straightline_call; eauto; [ ].
(* simplify guarantees *)
logical_simplify; subst.
(* done; prove postcondition *)
repeat straightline. eauto.
Qed.
Global Instance spec_of_aes_data_get : spec_of "b2_data_get" :=
fun function_env =>
forall (tr : trace) (m : mem) R (data : done_data)
(data_ptr out0 out1 out2 out3 : word)
(data_arr : list word),
(* data array is in memory, with arbitrary initital values *)
(array scalar32 (word.of_Z 4) data_ptr data_arr * R)%sep m ->
length data_arr = 4%nat ->
(* circuit must be in the DONE state *)
execution tr (DONE data) ->
(* the output registers must all be populated *)
data.(done_data_out0) = Some out0 ->
data.(done_data_out1) = Some out1 ->
data.(done_data_out2) = Some out2 ->
data.(done_data_out3) = Some out3 ->
call function_env aes_data_get tr m [data_ptr]
(fun tr' m' rets =>
(* the circuit is now in the IDLE state with output registers unset *)
execution tr' (IDLE (Build_idle_data
(done_ctrl data) None None None None None None None None
None None None None None None None None))
(* ...and the array now holds the values from the output registers *)
/\ (array scalar32 (word.of_Z 4) data_ptr [out0;out1;out2;out3] * R)%sep m'
(* ...and there are no return values *)
/\ rets = []).
Lemma aes_data_get_correct :
program_logic_goal_for_function! aes_data_get.
Proof.
(* initial processing *)
repeat straightline.
(* simplify array predicate *)
destruct_lists_by_length.
cbn [array] in *.
repeat match goal with
| H : context [scalar32 ?addr] |- _ =>
progress ring_simplify addr in H
end.
pose proof nregs_data_eq.
(* unroll while loop *)
eapply unroll_while with (iterations:=4%nat). cbn [repeat_logic_step].
repeat straightline.
(* process each iteration of the while loop *)
destruct data;
cbn [AesSemantics.done_ctrl
AesSemantics.done_data_out0
AesSemantics.done_data_out1
AesSemantics.done_data_out2
AesSemantics.done_data_out3] in *; subst.
(* i = 0 *)
split; repeat straightline; [ dexpr_hammer | ].
(* read register *)
read_data_out_n 0%nat. repeat straightline.
(* store result in memory *)
ring_simplify_store_addr.
repeat straightline.
(* i = 1 *)
split; repeat straightline; [ dexpr_hammer | ].
(* read register *)
read_data_out_n 1%nat. repeat straightline.
(* store result in memory *)
ring_simplify_store_addr.
repeat straightline.
(* i = 3 *)
split; repeat straightline; [ dexpr_hammer | ].
(* read register *)
read_data_out_n 2%nat. repeat straightline.
(* store result in memory *)
ring_simplify_store_addr.
repeat straightline.
(* i = 3 *)
split; repeat straightline; [ dexpr_hammer | ].
(* read register *)
read_data_out_n 3%nat. repeat straightline.
(* store result in memory *)
ring_simplify_store_addr.
repeat straightline.
(* i = 4; loop done *)
ssplit; repeat straightline; [ dexpr_hammer | ].
(* done; prove postcondition *)
cbn [array].
repeat match goal with
| |- context [scalar32 ?addr] =>
progress ring_simplify addr
end.
ssplit; eauto; [ ].
ecancel_assumption.
Qed.
Definition output_matches_state (out : aes_output) (s : state) : Prop :=
match s with
| BUSY data => busy_exp_output data = out
| DONE data =>
data = done_data_from_output (done_ctrl data) out
| _ => False
end.
Definition get_ctrl (s : state) : word :=
match s with
| UNINITIALIZED => word.of_Z 0 (* dummy value *)
| IDLE data => idle_ctrl data
| BUSY data => busy_ctrl data
| DONE data => done_ctrl data
end.
Global Instance spec_of_aes_data_get_wait : spec_of "b2_data_get_wait" :=
fun function_env =>
forall (tr : trace) (m : mem) R (out : aes_output)
(data_ptr : word) (data_arr : list word) (s : state),
(* data array is in memory, with arbitrary initital values *)
(array scalar32 (word.of_Z 4) data_ptr data_arr * R)%sep m ->
length data_arr = 4%nat ->
(* circuit must be in the DONE or BUSY state (otherwise we can't prove
termination) and expected or already-written output matches out *)
execution tr s ->
output_matches_state out s ->
call function_env aes_data_get_wait tr m [data_ptr]
(fun tr' m' rets =>
(* the circuit is now in the IDLE state with output registers unset *)
execution tr' (IDLE (Build_idle_data (get_ctrl s) None None None None
None None None None None None None None
None None None None))
(* ...and the array now holds the values from the expected output *)
/\ (array scalar32 (word.of_Z 4) data_ptr
[out.(data_out0)
; out.(data_out1)
; out.(data_out2)
; out.(data_out3)] * R)%sep m'
(* ...and there are no return values *)
/\ rets = []).
Lemma aes_data_get_wait_correct :
program_logic_goal_for_function! aes_data_get_wait.
Proof.
(* initial processing *)
repeat straightline.
(* separate out cases where s is initially BUSY or DONE *)
cbv [output_matches_state] in *.
destruct s; try contradiction; [ | ].
{ (* case in which the initial state is BUSY *)
lazymatch goal with
H : execution tr (BUSY data) |- _ =>
destruct data as [ctrl exp_output max_cycles];
cbn [get_ctrl] in *;
cbn [busy_ctrl busy_exp_output busy_max_cycles_until_done] in *
end.
subst.
(* begin while loop *)
let l := lazymatch goal with |- cmd _ _ _ _ ?l _ => l end in
apply atleastonce_localsmap
with (v0:=max_cycles)
(lt:=lt)
(invariant:=
fun i tr' m' l' =>
exists (s' : state) is_valid,
(* s' is the state for the new trace *)
execution tr' s'
(* as long as the loop continues, we keep setting is_valid to
0, so locals are unchanged until the loop breaks *)
/\ l' = map.put l "is_valid" is_valid
/\ (exists n',
(* current state has the same control and expected
output as the initial state, but a possibly different
counter *)
s' = BUSY (Build_busy_data ctrl out n')
(* the counter matches the "measure" i *)
/\ n' = i)
(* memory is unaffected *)
/\ (array scalar32 (word.of_Z 4) data_ptr data_arr ⋆ R)%sep m').
{ apply lt_wf. }
{ (* case in which the loop breaks immediately (cannot happen) *)
repeat straightline.
exfalso. (* proof by contradiction *)
repeat lazymatch goal with
| v := word.of_Z 0 |- _ => subst v
| br := if word.eqb _ (word.of_Z 0) then _ else _ |- _ => subst br
end.
rewrite @word.unsigned_eqb in * by typeclasses eauto.
autorewrite with push_unsigned in *.
destruct_one_match_hyp_of_type bool; congruence. }
{ (* proof that invariant holds at loop start *)
do 2 eexists; ssplit;
lazymatch goal with
| |- execution _ _ => eassumption
| |- (?x <= ?x)%nat => reflexivity
| |- ?x = ?x => reflexivity
| |- sep _ _ _ => eassumption
| |- _ = map.put _ _ _ => symmetry; solve [apply map.put_put_same]
| |- output_matches_state _ _ =>
cbv [output_matches_state] in *;
destruct_one_match; solve [eauto]
| _ => idtac
end; [ ].
eauto. }
{ (* invariant holds through loop (or postcondition holds, if loop breaks) *)
intros; logical_simplify; subst.
repeat straightline.
(* Call aes_data_valid *)
straightline_call; eauto; [ ].
(* simplify guarantees *)
logical_simplify; subst.
cbn [read_step reg_category] in *.
destruct_one_match_hyp.
{ (* case in which the status is now DONE; break *)
repeat straightline.
{ (* continuation case -- contradiction *)
exfalso.
cbv [status_matches_state] in *.
repeat invert_bool.
lazymatch goal with
| br := if word.eqb _ (word.of_Z 0) then _ else _,
H : word.unsigned br <> 0 |- _ =>
subst br; apply H
end.
push_unsigned.
destruct_one_match; subst; try reflexivity; [ ].
(* TODO: add to invert_bool *)
lazymatch goal with
| H:true = negb _ |- _ => symmetry in H; apply Bool.negb_true_iff in H
end.
congruence. }
{ (* break case *)
(* Call aes_data_get *)
straightline_call; eauto; try reflexivity; [ ].
(* simplify guarantees *)
logical_simplify; subst.
(* postcondition *)
repeat straightline.
ssplit; eauto. } }
{ (* case in which the state is still BUSY *)
intros; logical_simplify.
destruct_one_match_hyp; [ contradiction | subst ].
repeat straightline.
{ (* continuation case *)
cbv [Markers.split].
match goal with |- exists v, _ /\ (v < S ?n)%nat => exists n end.
split; [ | lia ].
(* invariant still holds *)
do 2 eexists; ssplit;
lazymatch goal with
| |- execution _ _ => eassumption
| |- sep _ _ _ => eassumption
| |- @eq map.rep ?l1 ?l2 =>
subst1_map l1;
lazymatch goal with
| |- @eq map.rep ?l1 ?l2 =>
subst1_map l1
end;
apply map.put_put_same
| _ => eauto
end. }
{ (* break case -- contradiction *)
exfalso.
cbv [status_matches_state] in *.
repeat invert_bool; try congruence; [ ].
lazymatch goal with
| br := if word.eqb ?x (word.of_Z 0) then _ else _,
Heq : word.eqb ?x (word.of_Z 0) = _,
Hz : word.unsigned br = 0 |- _ =>
subst br; rewrite Heq in Hz;
autorewrite with push_unsigned in Hz
end.
discriminate. } } } }
{ (* case in which the initial state is DONE *)
(* use output_matches_state precondition *)
lazymatch goal with
| H : ?data = done_data_from_output (done_ctrl ?data) out |- _ =>
cbv [done_data_from_output] in H; destruct data;
cbn [AesSemantics.done_ctrl
AesSemantics.done_data_out0
AesSemantics.done_data_out1
AesSemantics.done_data_out2
AesSemantics.done_data_out3] in *;
inversion H; clear H; subst
end.
(* while loop will run exactly once *)
eapply unroll_while with (iterations:=1%nat). cbn [repeat_logic_step].
repeat straightline.
(* prove that we do enter the while loop *)
ssplit;
[ subst_lets; rewrite word.eqb_eq by reflexivity;
push_unsigned; congruence | ].
repeat straightline.
(* Call aes_data_valid *)
straightline_call; eauto; [ ].
(* simplify guarantees *)
logical_simplify; subst.
cbn [read_step reg_category] in *.
cbv [status_matches_state] in *.
logical_simplify; subst.
repeat invert_bool; try congruence; [ ].
lazymatch goal with
| H : word.eqb _ _ = negb (is_flag_set ?x ?flag),
H' : is_flag_set ?x ?flag = _ |- _ =>
rewrite H' in H; cbn [negb] in H;
apply word.eqb_false in H
end.
repeat straightline.
(* prove the loop breaks *)
ssplit;
[ subst_lets;
destruct_one_match; push_unsigned; congruence | ].
repeat straightline.
(* Call aes_data_get *)
straightline_call; eauto; try reflexivity; [ ].
(* simplify guarantees *)
logical_simplify; subst.
(* postcondition *)
repeat straightline.
ssplit; eauto. }
Qed.
End Proofs.
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_arbiter_rr;
// parameters
localparam PORTS = 32;
localparam TYPE = "ROUND_ROBIN";
localparam BLOCK = "REQUEST";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [PORTS-1:0] request = 0;
reg [PORTS-1:0] acknowledge = 0;
// Outputs
wire [PORTS-1:0] grant;
wire grant_valid;
wire [$clog2(PORTS)-1:0] grant_encoded;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
request,
acknowledge);
$to_myhdl(grant,
grant_valid,
grant_encoded);
// dump file
$dumpfile("test_arbiter_rr.lxt");
$dumpvars(0, test_arbiter_rr);
end
arbiter #(
.PORTS(PORTS),
.TYPE(TYPE),
.BLOCK(BLOCK)
)
UUT (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 24.06.2017 01:23:43
// Design Name:
// Module Name: funciones_cursor
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module reconocedor_cursor(
input [2:0] visor_x,
input [1:0] visor_y,
output reg [7:0] valor,
output reg is_number
);
always @(*) begin
case ({visor_x,visor_y})
{3'd0 ,2'd0}: {valor,is_number}={8'b0,1'b1};
{3'd1 ,2'd0}: {valor,is_number}={8'b1,1'b1};
{3'd2 ,2'd0}: {valor,is_number}={8'd2,1'b1};
{3'd3 ,2'd0}: {valor,is_number}={8'd3,1'b1};
{3'd4 ,2'd0}: {valor,is_number}={8'd16,1'b0}; //suma
{3'd5 ,2'd0}: {valor,is_number}={8'd17,1'b0}; //resta
{3'd0 ,2'd1}: {valor,is_number}={8'd4,1'b1};
{3'd1 ,2'd1}: {valor,is_number}={8'd5,1'b1};
{3'd2 ,2'd1}: {valor,is_number}={8'd6,1'b1};
{3'd3 ,2'd1}: {valor,is_number}={8'd7,1'b1};
{3'd4 ,2'd1}: {valor,is_number}={8'd18,1'b0}; //mul
{3'd5 ,2'd1}: {valor,is_number}={8'd19,1'b0}; //or
{3'd0 ,2'd2}: {valor,is_number}={8'd8,1'b1};
{3'd1 ,2'd2}: {valor,is_number}={8'd9,1'b1};
{3'd2 ,2'd2}: {valor,is_number}={8'h0a,1'b1};
{3'd3 ,2'd2}: {valor,is_number}={8'h0b,1'b1};
{3'd4 ,2'd2}: {valor,is_number}={8'd20,1'b0}; //and
{3'd5 ,2'd2}: {valor,is_number}={8'd21,1'b0}; //CE
{3'd0 ,2'd3}: {valor,is_number}={8'h0c,1'b1};
{3'd1 ,2'd3}: {valor,is_number}={8'h0d,1'b1};
{3'd2 ,2'd3}: {valor,is_number}={8'h0e,1'b1};
{3'd3 ,2'd3}: {valor,is_number}={8'h0f,1'b1};
{3'd4 ,2'd3}: {valor,is_number}={8'd22,1'b0}; //EXE
default: {valor,is_number}={8'd28,1'b0};
endcase
end
endmodule
|
// This file is part of Verilog-65c816.
//
// Copyright 2017 by FPGApeeps
//
// Verilog-65c816 is free software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// Verilog-65c816 is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with Verilog-65c816. If not, see <http://www.gnu.org/licenses/>.
`include "src/inc/misc_defines.v"
`include "src/inc/test_ram_defines.v"
// Block RAM test module
module _InternalTestRam(input wire clk,
// Write enable
input wire we,
// Address
input wire [`TR_ADDR_MSB_POS:0] addr,
// Data in
input wire [`TR_DATA_MSB_POS:0] data_in,
// Data out
output reg [`TR_DATA_MSB_POS:0] data_out);
`include "src/inc/cpu_debug_params.v"
reg [`TR_DATA_MSB_POS:0] __mem[0:`_ARR_SIZE_THING(`_TR_ADDR_WIDTH)];
initial $readmemh("readmemh_input.txt.ignore", __mem);
always @ (posedge clk)
begin
//$display("In _InternalTestRam: %h\t\t%h\t\t%h, %h",
// we,
// addr,
// data_in, data_out);
$display("In _InternalTestRam: %h\t\t%h, %h, %h\t\t%h",
we,
__mem[__debug_addr_0], __mem[__debug_addr_1],
__mem[__debug_addr_2],
data_out);
if (we)
begin
__mem[addr] <= data_in;
end
data_out <= __mem[addr];
end
endmodule
module TestRam(input wire clk,
input wire req_rdwr,
// Write enable
input wire we,
// Address
input wire [`TR_ADDR_MSB_POS:0] addr,
// Data in
input wire [`TR_DATA_MSB_POS:0] data_in,
// Data out
output wire [`TR_DATA_MSB_POS:0] data_out,
// data_ready goes high when data is ready
output reg data_ready);
`include "src/inc/generic_params.v"
reg __can_rdwr;
//reg [1:0] __can_rdwr;
// "pt" is short for "passthrough"
wire __pt_we;
wire [`TR_ADDR_MSB_POS:0] __pt_addr;
wire [`TR_DATA_MSB_POS:0] __pt_data_in, __pt_data_out;
// Inputs to internal_test_ram
assign __pt_we = we;
assign __pt_addr = addr;
assign __pt_data_in = data_in;
// Outputs from internal_test_ram
assign data_out = __pt_data_out;
_InternalTestRam internal_test_ram(.clk(clk), .we(__pt_we),
.addr(__pt_addr), .data_in(__pt_data_in),
.data_out(__pt_data_out));
initial data_ready = __false;
initial __can_rdwr = __false;
always @ (posedge clk)
begin
//__can_rdwr <= !__can_rdwr;
if (!req_rdwr)
begin
data_ready <= __false;
__can_rdwr <= __false;
end
else // if (req_rdwr)
begin
__can_rdwr <= !__can_rdwr;
data_ready <= __can_rdwr;
end
end
endmodule
|
module Hydra ( ready , data_out ,
clk , rst_n ,
inst_cur , inst_nxt ,
data_in_1 , data_in_2 ,
hy_exe
);
//====parameter Declaration====//
parameter inst_num = 31;
parameter nop = 5'h0;
parameter setrn = 5'h1;
parameter mul = 5'h2;
parameter add = 5'h3;
parameter sub = 5'h4;
parameter mod = 5'h5;
parameter pol_add = 5'h6;
parameter mov = 5'h7;
parameter shuffle = 5'h8;
parameter stall = 3'h7;
parameter mode_i = 1'b0;
parameter mode_q = 1'b1;
parameter state_idle = 4'h0 ;
parameter state_load_N = 4'h1 ;
parameter state_p_m_0 = 4'h2 ;
parameter state_p_m_1 = 4'h3 ;
parameter state_p_m_2 = 4'h4 ;
parameter state_p_m_3 = 4'h5 ;
parameter state_p_a_1 = 4'h6 ;
parameter state_p_s_N = 4'h7 ;
parameter state_p_s_1 = 4'h8 ;
parameter state_p_a_N = 4'h9 ;
parameter state_write = 4'hf ;
integer i;
//====I/O Declaration====//
output ready ;
reg ready ;
output [255:0] data_out;
reg [255:0] data_out;
input clk , hy_exe , rst_n;
input [255:0] data_in_1 , data_in_2;
input [inst_num-1:0] inst_cur , inst_nxt;
//====Register Declaration====//
reg [15:0] A [15:0];
reg [15:0] A_next [15:0];
reg [15:0] X [15:0];
reg [15:0] X_next [15:0];
reg [15:0] N [15:0];
reg [15:0] N_next [15:0];
reg [18:0] Y [16:0];
reg [18:0] Y_next [16:0];
reg [15:0] temp , temp_next , np , np_next;
reg [3: 0] curstate , nextstate;
reg [4: 0] counter , counter_next;
//====Wire Declaration====//
reg [15:0] mul_in1 [15:0];
reg [15:0] mul_in2 [15:0];
reg [31:0] mul_o [15:0];
reg [17:0] add1_in1 [15:0];
reg [17:0] add1_in2 [15:0];
reg [18:0] add1_o [15:0];
reg [17:0] add2_in1 [15:0];
reg [17:0] add2_in2 [15:0];
reg [18:0] add2_o [15:0];
//====Connection Wire====//
reg [15:0] buf_44 [43:0];
reg [15:0] vec_inA [15:0];
reg [15:0] vec_inX [15:0];
reg [15:0] vec_out [15:0];
//====Define Wire====//
wire [4:0] comp_type_nxt = inst_nxt[30:26];
wire [4:0] comp_type = inst_cur[30:26];
wire [1:0] shift = inst_cur[17:16];
wire mode = inst_cur[9];
wire rstY = inst_cur[8];
wire accuY = inst_cur[7];
wire WB = inst_cur[6];
wire expand = inst_cur[18];
wire load_A = inst_nxt[24];
wire load_X = inst_nxt[15];
wire [31:0] pol_det = { N[1] , N[0] };
//====Vector Connection====//
always @ (*) begin
data_out = { vec_out[15], vec_out[14], vec_out[13], vec_out[12], vec_out[11], vec_out[10], vec_out[9], vec_out[8],
vec_out[ 7], vec_out[ 6], vec_out[ 5], vec_out[ 4], vec_out[ 3], vec_out[ 2], vec_out[1], vec_out[0] };
{ vec_inA[15], vec_inA[14], vec_inA[13], vec_inA[12], vec_inA[11], vec_inA[10], vec_inA[9], vec_inA[8],
vec_inA[ 7], vec_inA[ 6], vec_inA[ 5], vec_inA[ 4], vec_inA[ 3], vec_inA[ 2], vec_inA[1], vec_inA[0] } = data_in_1;
{ vec_inX[15], vec_inX[14], vec_inX[13], vec_inX[12], vec_inX[11], vec_inX[10], vec_inX[9], vec_inX[8],
vec_inX[ 7], vec_inX[ 6], vec_inX[ 5], vec_inX[ 4], vec_inX[ 3], vec_inX[ 2], vec_inX[1], vec_inX[0] } = data_in_2;
buf_44[ 0] = N[ 0];buf_44[ 1] = N[ 1];buf_44[ 2] = N[ 2];buf_44[ 3] = N[ 3];buf_44[ 4] = N[ 4];buf_44[ 5] = N[ 5];
buf_44[ 6] = N[ 6];buf_44[ 7] = N[ 7];buf_44[ 8] = N[ 8];buf_44[ 9] = N[ 9];buf_44[10] = N[10];buf_44[11] = N[11];
buf_44[12] = N[12];buf_44[13] = N[13];buf_44[14] = N[14];buf_44[15] = N[15];buf_44[16] = X[ 0];buf_44[17] = X[ 1];
buf_44[18] = X[ 2];buf_44[19] = X[ 3];buf_44[20] = X[ 4];buf_44[21] = X[ 5];buf_44[22] = X[ 6];buf_44[23] = X[ 7];
buf_44[24] = X[ 8];buf_44[25] = X[ 9];buf_44[26] = X[10];buf_44[27] = X[11];buf_44[28] = X[12];buf_44[29] = X[13];
buf_44[30] = X[14];buf_44[31] = X[15];buf_44[32] = Y[ 0];buf_44[33] = Y[ 1];buf_44[34] = Y[ 2];buf_44[35] = Y[ 3];
buf_44[36] = Y[ 4];buf_44[37] = Y[ 5];buf_44[38] = Y[ 6];buf_44[39] = Y[ 7];buf_44[40] = Y[ 8];buf_44[41] = Y[ 9];
buf_44[42] = Y[10];buf_44[43] = Y[11];
end
//===============================Sequential Logic===============================//
always @ ( posedge clk or negedge rst_n ) begin
if ( rst_n == 1'b0 ) begin
curstate <= 4'd0;
counter <= 5'd0;
temp <=16'd0;
np <=16'd0;
for ( i=0 ; i!=16 ; i=i+1 ) begin
A[i] <= 16'd0;
X[i] <= 16'd0;
N[i] <= 16'd0;
Y[i] <= 19'd0;
end
Y[16] <= 19'd0;
end
else begin
curstate <= nextstate;
counter <= counter_next;
temp <= temp_next;
np <= np_next;
for ( i=0 ; i!=16 ; i=i+1 ) begin
A[i] <= A_next[i];
X[i] <= X_next[i];
N[i] <= N_next[i];
Y[i] <= Y_next[i];
end
Y[16] <= Y_next[16];
end
end
//===============================NextState Logic===============================//
always @ (*)
begin
case (curstate)
state_idle :
case (comp_type)
mul :
nextstate = state_p_m_0;
add :
nextstate = state_p_a_1;
sub :
nextstate = state_p_s_1;
default :
nextstate = state_idle;
endcase
state_p_m_0 :
nextstate = state_p_m_1;
state_p_m_1 :
nextstate = state_p_m_2;
state_p_m_2 :
nextstate = state_p_m_3;
state_p_m_3 :
if ( counter==5'd17 )
nextstate = state_write;
else
nextstate = state_p_m_1;
state_p_a_1 :
if ( add2_o[15]<N[15] && add2_o[15][16]==1'b0 )
nextstate = state_write;
else
nextstate = state_p_s_N;
state_p_s_N :
nextstate = state_write;
state_p_s_1 :
if (add2_o[15][16]==1'b0 )
nextstate = state_write;
else
nextstate = state_p_a_N;
state_p_a_N :
nextstate = state_write;
state_write :
nextstate = state_idle;
default :
nextstate = state_idle;
endcase
end
//===============================Output Logic===============================//
always @ ( * ) begin
temp_next = temp;
//-------------------------------------------
//--********Write back strategy************--
//-------------------------------------------
for ( i=0 ; i!=16 ; i=i+1 ) begin //vec_out
if (WB)
vec_out[i] = add2_o[i];
else
vec_out[i] = 16'd0;
end
//----------------------------------------
//--********Loading strategy************--
//----------------------------------------
if (ready==1'b1) begin //A & X
if (load_A==1'b1) begin
if (expand==1'b1) begin
for ( i=0 ; i!=16 ; i=i+1 )
A_next[i] = vec_inA[0];
end // end expand
else if (shift==2'd1) begin
for ( i=0 ; i!=15 ; i=i+1 )
A_next[i] = vec_inA[i+1];
A_next[15] = 16'd0;
end // end shift 1
else if (shift==2'd2) begin
for ( i=0 ; i!=14 ; i=i+1 )
A_next[i] = vec_inA[i+2];
A_next[14] = 16'd0;
A_next[15] = 16'd0;
end // end shift 2
else begin
for ( i=0 ; i!=16 ; i=i+1 )
A_next[i] = vec_inA[i];
end // end normal load
end // end load_A == 1
else if (shift==2'd1) begin
for ( i=0 ; i!=15 ; i=i+1 )
A_next[i] = A[i+1];
A_next[15] = 16'd0;
end // end shift 1
else if (shift==2'd2) begin
for ( i=0 ; i!=14 ; i=i+1 )
A_next[i] = A[i+2];
A_next[14] = 16'd0;
A_next[15] = 16'd0;
end // end shift 2
else begin
for ( i=0 ; i!=16 ; i=i+1 )
A_next[i] = A[i];
end
end
else begin
for ( i=0 ; i!=16 ; i=i+1 )
A_next[i] = A[i];
end
for ( i=0 ; i!=16 ; i=i+1 ) begin
if ( ready==1'b1 && load_X==1'b1 )
X_next[i] = vec_inX[i];
else
X_next[i] = X[i];
end
//---------------------------------------------
//--********Accumulation strategy************--
//---------------------------------------------
for ( i=0 ; i!=16 ; i=i+1 ) begin //Y
if (accuY==1'b1)
Y_next[i] = add2_o[i];
else if (rstY==1'b1)
Y_next[i] = 19'd0;
else
Y_next[i] = Y[i];
end
if (rstY==1'b1)
Y_next[16] = 19'd0;
else
Y_next[16] = Y[16];
//----------------------------------------
//--********Default strategy************--
//----------------------------------------
np_next = (comp_type==setrn) ? 16'h15c1/*A[0]*/ : np;
// for ( i=0 ; i!=16 ; i=i+1 ) begin
// N_next[i] = (comp_type==setrn) ? X[i] : N[i];
// end
ready = hy_exe;
for ( i=0 ; i!=16 ; i=i+1 ) begin
mul_in1[i] = 16'd0;
mul_in2[i] = 16'd0;
add1_in1[i] = 18'd0;
add1_in2[i] = 18'd0;
add2_in1[i] = 18'd0;
add2_in2[i] = 18'd0;
N_next[i] = N[i];
end
counter_next = 5'd0;
//--------------------------------------------
//--********Instruction strategy************--
//--------------------------------------------
if (hy_exe==1'b0) begin
counter_next = counter;
for ( i=0 ; i!=16 ; i=i+1 ) begin
N_next[i] = N[i];
X_next[i] = X[i];
A_next[i] = A[i];
Y_next[i] = Y[i];
end
Y_next[16] = Y[16];
end
else if (mode==mode_q) begin
case (comp_type)
nop : begin
counter_next = 5'd0;
for ( i=0 ; i!=16 ; i=i+1 ) begin
mul_in1[i] = 16'd0;
mul_in2[i] = 16'd0;
add1_in1[i] = A[i];
add1_in2[i] = mul_o[i];
add2_in1[i] = (accuY) ? Y[i] : 16'd0;
add2_in2[i] = add1_o[i];
end
end
setrn : begin
if (comp_type_nxt==pol_add)
counter_next = 5'd0;
else
counter_next = 5'd0;
//XXXXXXXXXXXXXXXXXXXXXXXXXX TO BE CONFIRMED XXXXXXXXXXXXXXXXXXXXXXXXXX
for ( i=0 ; i!=16 ; i=i+1 ) begin
mul_in1[i] = 16'd0;
mul_in2[i] = 16'd0;
add1_in1[i] = A[i];
add1_in2[i] = mul_o[i];
add2_in1[i] = (accuY) ? Y[i] : 18'd0;
add2_in2[i] = add1_o[i];
// X_next [i] = vec_inX[i];
N_next [i] = A[i];
end
// ready = (counter==5'd1) ? 1'b1 : 1'b0;
//XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
end
pol_add : begin
counter_next = (counter>5'd6) ? 5'd0 : counter +5'd1;
ready = (counter==5'd7) ? 1'b1 : 1'b0;
//computation part
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = (N[0][i]==1'b1 && counter<5'd8 ) ? A[0] : 18'd0 ;
add2_in1[i] = (accuY) ? Y[i] : 18'd0;
add2_in2[i] = add1_o[i];
end
for ( i=0 ; i!=15 ; i=i+1 ) begin
add1_in2[i] = (N[0][i+1]==1'b1 && counter<5'd8 ) ? A[1] : 18'd0 ;
end
add1_in2[15] = (N[1][0]==1'b1 && counter<5'd8 ) ? A[1] : 18'd0 ;
if ( counter < 5'd8 ) begin
for ( i=0 ; i!=15 ; i=i+1 )
N_next[i] = { N[i+1][1:0] , N[i][15:2] };
N_next[15] = { X[0][1:0] , N[15][15:2] };
for ( i=0 ; i!=8 ; i=i+1 )
X_next[i] = { X[i+1][1:0] , X[i][15:2] };
X_next[8] = { 3'd0 , N[0][1:0] , X[8][12:2] };
for ( i=9 ; i!=16 ; i=i+1 )
X_next[i] = X[i] ;
end
else begin
for ( i=0 ; i!=16 ; i=i+1 ) begin
N_next[i] = N[i];
X_next[i] = X[i];
end
end
if ( counter>5'd6 ) begin
for ( i=0 ; i!=16 ; i=i+1 )
A_next[i] = vec_inA[i];
end
else begin
for ( i=0 ; i!=14 ; i=i+1 )
A_next[i] = A[i+2];
A_next[14] = 16'd0;
A_next[15] = 16'd0;
end
end
mul : begin
counter_next = 5'd0;
ready = 1'b1;
for ( i=0 ; i!=16 ; i=i+1 ) begin
if (expand==1'b1)
mul_in1[i] = A[0];
else
mul_in1[i] = A[i];
mul_in2[i] = X[i];
add1_in1[i] = 16'd0;
add1_in2[i] = mul_o[i];
add2_in1[i] = (accuY) ? Y[i][17:0] : 18'd0;
add2_in2[i] = add1_o[i][17:0];
end
end
add : begin
counter_next = 5'd0;
ready = 1'b1;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = A[i];
add1_in2[i] = X[i];
add2_in1[i] = (accuY) ? Y[i][17:0] : 18'd0;
add2_in2[i] = add1_o[i];
end
end
sub : begin //Should be modified
counter_next = 5'd0;
ready = 1'b1;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = A[i];
add1_in2[i] = ~X[i]+16'd1;
add2_in1[i] = (accuY) ? Y[i][17:0] : 18'd0;
add2_in2[i] = add1_o[i];
end
end
mod : begin
counter_next = 5'd0;
ready = 1'b1;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = 18'd0;
add1_in2[i] = 18'd0;
add2_in1[i] = Y[i] % {inst_cur[23:19] , inst_cur[14:10]};
add2_in2[i] = add1_o[i];
end
//rotation control
for ( i=0 ; i!=15 ; i=i+1 )
N_next[i] = { N[i+1][12:0] , N[i][15:13] };
N_next[15] = { X[0][12:0] , N[15][15:13] };
for ( i=0 ; i!=7 ; i=i+1 )
X_next[i] = { X[i+1][12:0] , X[i][15:13] };
X_next[7] = { X[8][12:0] , X[7][15:13]};
X_next[8] = { 3'd0 , N[0][12:0] } ;
for ( i=9 ; i!=16 ; i=i+1 )
X_next[i] = X[i] ;
end
shuffle : begin
counter_next = 5'd0;
ready = 1'b1;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = buf_44[A[i]];
add1_in2[i] = 18'd0;
add2_in1[i] = 18'd0;
add2_in2[i] = add1_o[i];
end
end
endcase
end
else begin
if ( comp_type==nop || comp_type==mov || comp_type[4:2]==stall ) begin
ready = hy_exe;
end
else begin
case (curstate)
state_p_a_1 : begin
counter_next = 5'd1;
ready = 1'b0;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = A[i];
add1_in2[i] = X[i];
add2_in1[i] = add1_o[i][15:0];
Y_next[i] = add2_o[i][16:0];
end
for ( i=1 ; i!=16 ; i=i+1 )
add2_in2[i] = add1_o[i-1][16];
add2_in2[0] = 18'd0;
end
state_p_s_N : begin
counter_next = 5'd1;
ready = 1'b0;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = Y[i][17:0];
add1_in2[i] = { 2'b11 , ~N[i] };
Y_next[i] = add2_o[i][15:0];
end
for ( i=1 ; i!=16 ; i=i+1 ) begin
add2_in1[i] = add1_o[i][17:0];
if (add1_o[i-1][17]==1'b1 && add1_o[i-1]!=-18'd1 )
add2_in2[i] = 18'd0;
else
add2_in2[i] = 18'd1;
end
add2_in1[0] = add1_o[0][17:0];
add2_in2[0] = 18'd1;
end
state_p_s_1 : begin
counter_next = 5'd1;
ready = 1'b0;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = A[i];
add1_in2[i] = { 2'b11 , ~X[i] };
Y_next[i] = add2_o[i][15:0];
end
for ( i=1 ; i!=16 ; i=i+1 ) begin
add2_in1[i] = add1_o[i][17:0];
if (add1_o[i-1][17]==1'b1 && add1_o[i-1][17:0]!=-18'd1 )
add2_in2[i] = 18'd0;
else
add2_in2[i] = 18'd1;
end
add2_in1[0] = add1_o[0][17:0];
add2_in2[0] = 18'd1;
end
state_p_a_N : begin
counter_next = 5'd1;
ready = 1'b0;
for ( i=0 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = Y[i][17:0];
add1_in2[i] = N[i];
add2_in1[i] = add1_o[i][15:0];
Y_next[i] = add2_o[i][16:0];
end
for ( i=1 ; i!=16 ; i=i+1 )
add2_in2[i] = add1_o[i-1][16];
add2_in2[0] = 18'd0;
end
state_p_m_0 : begin
counter_next = counter;
ready = 1'b0;
mul_in1[0] = A[0];
mul_in2[0] = X[0];
temp_next = mul_o[0][15:0];
Y_next[0] = { 1'b0 , mul_o[0][15:0] };
Y_next[1] = { 1'b0 , mul_o[0][31:16]};
end
state_p_m_1 : begin
counter_next = counter + 5'd1;
ready = 1'b0;
mul_in1[0] = temp;
mul_in2[0] = np;
for ( i=1 ; i!=16 ; i=i+1 ) begin
mul_in1[i] = A[0];
mul_in2[i] = X[i];
add1_in1[i] = { 1'b0 , Y[i][16:0] };
add1_in2[i] = { 2'd0 , mul_o[i][15:0] };
add2_in1[i] = add1_o[i][17:0];
end
for ( i=2 ; i!=16 ; i=i+1 )
add2_in2[i] = { 2'd0 , mul_o[i-1][31:16] };
add2_in2[1] = 18'd0;
for ( i=1 ; i!=16 ; i=i+1 ) begin
Y_next[i] = add2_o[i];
end
Y_next[ 0] = Y[0];
Y_next[16] = mul_o[15][31:16];
temp_next = mul_o[0][15:0];
end
state_p_m_2 : begin
counter_next = counter;
ready = 1'b0;
for ( i=0 ; i!=16 ; i=i+1 ) begin
mul_in1[i] = temp;
mul_in2[i] = N[i];
add1_in1[i] = Y[i][17:0];
add1_in2[i] = { 2'd0 , mul_o[i][15:0] };
end
add2_in1[0] = Y[16][17:0];
add2_in2[0] = { 2'd0 , mul_o[15][31:16] };
for ( i=1 ; i!=16 ; i=i+1 ) begin
add2_in1[i] = add1_o[i][17:0];
add2_in2[i] = { 2'd0 , mul_o[i-1][31:16] };
Y_next[i] = add2_o[i];
end
Y_next[ 0] = add1_o[0];
Y_next[16] = add2_o[0];
for( i=0 ; i!=15 ; i=i+1 )
A_next[i] = A[i+1];
A_next[15] = 16'd0;
end
state_p_m_3 : begin
counter_next = counter;
ready = 1'b0;
mul_in1[0] = A[0];
mul_in2[0] = X[0];
for ( i=1 ; i!=16 ; i=i+1 ) begin
add1_in1[i] = { 2'd0 , Y[i][15:0]};
add1_in2[i] = { 15'd0 , Y[i-1][18:16]};
end
add1_in1[0] = { 2'd0 , Y[16][15:0]};
add1_in2[0] = { 15'd0 , Y[15][18:16]};
add2_in1[1] = add1_o[1][17:0];
add2_in2[1] = { 2'd0 , mul_o[0][15:0] };
add2_in1[2] = add1_o[2][17:0];
add2_in2[2] = { 2'd0 , mul_o[0][31:16] };
//should be mpdified to Y_next[i] = add2_o[i] for regular
for ( i=2 ; i!=15 ; i=i+1 )
Y_next[i] = add1_o[i+1];
Y_next[ 0] = add2_o[1];
Y_next[ 1] = add2_o[2];
Y_next[15] = add1_o[0];
Y_next[16] = 19'd0;
temp_next = add2_o[1][15:0];
end
state_write : begin
counter_next = 5'd0 ;
ready = 1'b1;
for ( i=0 ; i!=16 ; i=i+1) begin
vec_out[i] = Y[i][15:0];
Y_next[i] = (accuY) ? Y[i] : 19'd0;
// A_next[i] = vec_inA[i];
// X_next[i] = vec_inX[i];
end
end
default : begin
counter_next = 5'd0;
ready = 1'b0;
// ready = hy_exe;
for ( i=0 ; i!=16 ; i=i+1) begin
vec_out[i] = 16'd0;
// Y_next[i] = 19'd0;
// A_next[i] = 16'd0;
// X_next[i] = 16'd0;
end
end
endcase
end
end
end
//===============================Combinational Logic===============================//
always @ (*) begin
for (i=0 ; i<=15 ; i=i+1) begin
mul_o[i] = mul_in1[i] * mul_in2[i] ;
add1_o[i] = add1_in1[i] + add1_in2[i] ;
add2_o[i] = add2_in1[i] + add2_in2[i] ;
end
end
endmodule
|
module QcmMasterControllerMain(clk, sig, codeSer, codePar, enableSer, enablePar, ioPowerEnable, clkEnable, serCodeOutput, parCodeOutput, nclkOutput);
/*
This is the master controller module which instantiates the sub-modules responsible for master controller operation:
counter=frequency counter (really, a period counter with inversion) for
determining the RF frequency from the square-wave input on "sig"
lut=look-up-table for mapping from a frequency to a capacitor state.
Currently, the same state number is assigned to both the series and parallel outputs
driver=responsible for mapping from look-up-table output to encoded
signal for decoder boards (in present implementation, no adjustment
needs to be made to lut output), and also determines whether the state
has settled and the cap boards may act on the change.
PIN ASSIGNMENT FOR EPM2210F256C5N (MANY MACROCELL CPLD)
To arrive at this pin assignment,
(1) consult pin assignment for CapBoardDecoder (for tuning code pins) OR "BurkeCPLDBoardConfigurationTemplate.doc" (for signal input)
(2) map to pins on standard 84-pin CPLD
(3) consult Bill Parkin's 84-256-pin adapter schematic to map to 256-pin pin values.
Ok clk Location PIN_H5 Yes
Ok sig Location PIN_K1 Yes (PIN_04 on socket - see Willy Burke's doc and note we are using Slot 1 for sync input on board front panel)
Ok enableSer Location PIN_F1 Yes AC24 on backplane
Ok enablePar Location PIN_G1 Yes AC25
Ok codeSer[0] Location PIN_R16 Yes AC3
Ok codeSer[1] Location PIN_L16 Yes AC6
Ok codeSer[2] Location PIN_E16 Yes AC9
Ok codeSer[3] Location PIN_A13 Yes AC12
Ok codeSer[4] Location PIN_A8 Yes AC15
Ok codeSer[5] Location PIN_A5 Yes AC18
Ok codeSer[6] Location PIN_B1 Yes AC21
Ok codePar[0] Location PIN_N16 Yes AC4
Ok codePar[1] Location PIN_G16 Yes AC7
Ok codePar[2] Location PIN_D16 Yes AC10
Ok codePar[3] Location PIN_A12 Yes AC13
Ok codePar[4] Location PIN_A7 Yes AC16
Ok codePar[5] Location PIN_A4 Yes AC19
Ok codePar[6] Location PIN_D1 Yes AC22
Ok ioPowerEnable Location PIN_T12 Yes Connects to I/O 27. This needs a signal - e.g. clock divided down - to demonstrate CPLD is working. But really should go to Pin56 out of CPLD - this is not connected to 256-pin CPLD, so need to make a jumper wire on board.
Ok clkEnable Location PIN_T15 Yes Connects to I/O 28. The clock needs Pin73 out of CPLD to be high to work, but Pin73 is not connected to 256-pin CPLD, so need to make a hardware jumper on the board.
Ok serCodeOutput Location PIN_N1 Yes Encodes the logic state for the series capacitors into a time series going out on LEMO I/O 4
Ok parCodeOutput Location PIN_T2 Yes Encodes the logic state for the series capacitors into a time series going out on LEMO I/O 4
Ok nclkOutput Location PIN_T4 Yes Encodes n_clk - the number of clock counts in a signal count period. Goes out on I/O #6 - J16 on 84-pin footprint, and connected to PIN_T4 on 256 pin adapter.
Ted Golfinopoulos, pin assignment made on 24 Oct 2011
Revised 9 January 2012
*/
input clk, sig; //1 bit inputs corresponding to clk and RF signal.
output wire [6:0] codeSer, codePar; //Capacitor state encoded in a number which is interpreted by CapBoardDecoder to determine which caps to turn on.
output enableSer, enablePar; //"Ready" bits indicating codes are ready for decoding.
output ioPowerEnable; //Bit which receives clock-like signal and allows IO circuitry to receive power on LH timing board.
output clkEnable; //Bit which, when high, enables clock.
output serCodeOutput; //Bit containing encoded version of serial cap code.
output parCodeOutput; //Bit containing encoded version of parallel cap code.
output nclkOutput; //Bit containing (time)-encoded version of clock counts per M signal count period.
//wire [13:0] f; //Frequency of sig IN HUNDREDS OF Hz, need 4 significant decimal figures.
wire [13:0] n_clk; //Frequency of sig IN HUNDREDS OF Hz, need 4 significant decimal figures.
wire [6:0] stateSer; //Intermediate variable to hold lut output for series levels.
wire [6:0] statePar; //Intermediate variable to hold lut output for parallel levels.
reg [4:0] clkCntr; //Divide clock signal down.
initial begin
#0
clkCntr=4'b0; //Initialize clock counter.
end
//Instantiate frequency counter object.
//counter c(clk, sig, f); //Use period counter instead of frequency counter.
//fcounter c(clk, sig, f); //Use frequency counter instead of period counter.
counter_n c(clk, sig, n_clk); //Use period counter, but don't use division step. Instead, pass number of clock counts.
//10 August 2012 double clock speed and halve number of signal edges so that matching
//network can respond faster to frequency chances.
defparam c.M=25; //Number of signal edges counted inside period counter.
defparam c.F_CLK=80000; //Clock frequency in hundreds of Hz.
//79 corner frequencies in HUNDREDS OF Hz,
//from about 50 kHz (500 hundred Hz) to 300 kHz (3000 hundred Hz)
//Instantiate look-up table which determines state from frequency.
//lut tab(clk,f,state);
lut_n tabSer(clk,n_clk,stateSer); //Tell series lut to use table 1
lut_n tabPar(clk,n_clk,statePar); //Tell parallel lut to use table 2
defparam tabSer.LOOKUP_ID=1; //Tell series lut to use table 1
defparam tabPar.LOOKUP_ID=2; //Tell parallel lut to use table 2
//defparam tabSer.OFFSET=4'b1000;
//defparam tabPar.OFFSET=4'b0111;
//lut_n tabSer(clk,n_clk,stateSer);
//lut_n tabPar(clk,n_clk,statePar);
//At this point, the look-up table outputs a state in the same format required for the encoded cap states, and
//the cap index for the series board is the same as for the parallel board.
assign codeSer=stateSer;
assign codePar=statePar;
//Instantiate drivers for serial and parallel states - primarily, this determines when the states are ready for decoding by CapBoardDecoder.
driver dSer(clk, codeSer, enableSer);
driver dPar(clk, codePar, enablePar);
//Instantiate encoders to put out the series and parallel codes in a pulse sequence on the LEMO outputs.
//Give a slower version of clock so that the digitizer, with 2.5 MHz sample rate, can resolve the pulses.
stateEncoder seriesStateEncoder(clkCntr[4], codeSer, enableSer, serCodeOutput);
stateEncoder parallelStateEncoder(clkCntr[4], codePar, enablePar, parCodeOutput);
defparam nclkEncoder.STATE_LENGTH=4'b1110; //Need to redefine the parameter dictating the size of the bit pattern to encode.
stateEncoder nclkEncoder(clkCntr[4], n_clk, enableSer, nclkOutput); //Instantiate encoder for n_clk
always @(posedge clk) begin
clkCntr=clkCntr+4'b1; //Increment clock counter.
end
//Give ioPowerEnable bit a divided version of the clock. The rationale behind this is
//that (a) the ioPowerEnable bit needs a clock-like signal and (b) you should do an operation
//on the clock to prove that the CPLD is working (otherwise synthesis can just connect a wire,
//and so passing the clock to the ioPowerEnable bit may not demonstrate functionality). This
//is in accordance with the new version of the LH Timing Board. Pin 56 on the CPLD must receive
//the ioPowerEnable bit.
assign ioPowerEnable=clkCntr[1];
assign clkEnable=1'b1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_TB_V
`define SKY130_FD_SC_HVL__DFXBP_TB_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dfxbp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__dfxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__OR4BB_BEHAVIORAL_PP_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4BB_BEHAVIORAL_PP_V |
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
//
// Avalon-MM slave bridge to the DPRIO HIP serial input
//
// Address Translation
//
// ----------------------------------------------------------
// Addr[15:8] |
// -----------------------------------------------------------
// 0x00 | Control register
// 0x01 | HIP DPRIO PCIe config register
// 0x00 | HIP DPRIO Extended register
// Other | Reserved
// |
//
// Control Register
// ----------------------------------------------------------
// Addr[7:0] | Data
// -----------------------------------------------------------
// 0x00 | Data[0] (R/W): 0 enable dprio
// | 1 Disable dprio use csr
// | (--> original configuration)
// |
// | Data[1] (R/W): RESERVED
// | Data[2] (R/W): Indicate error : Unsupported write address
// | Data[3] (R/W): Indicate error : Unsupported read address
// | Data[4] (R/W): Enable extended dprio access
// | in addition to PCIe address
// | Data[15:1] (R/W): RESERVED
// 0x01 | Data[4:0] (R/W): Device address
// | Data[9:5] (R/W): port address
// 0x02 | Data[8:0] (R/W): bases address
// 0x03 | Data[15:0] (R/W): when 16'hED10 enable dprio accross all register
// HIP DPRIO Register
// -----------------------------------------------------------
// Addr[7:0] | Data
// -----------------------------------------------------------
// 0x00 0x08 | reserved
// 0x09 0x20 | k_conf
// 0x21 0x2F | k_bar
// 0x30 0x37 | k_cnt
// 0x38 0x3B | k_vc0
// 0x3C 0x3F | k_vc1
// 0x40 0x58 | reserved
// 0x59 0x5B | k_ptr0
// 0x5C 0x5E | k_ptr1
// 0x5F 0xFF | reserved
`timescale 1ns / 1ps
module altpcie_pcie_reconfig_bridge (
input [ 7: 0] avs_pcie_reconfig_address,
input avs_pcie_reconfig_chipselect,
input avs_pcie_reconfig_write,
input [ 15: 0] avs_pcie_reconfig_writedata,
output reg avs_pcie_reconfig_waitrequest,
input avs_pcie_reconfig_read,
output reg [15: 0] avs_pcie_reconfig_readdata,
output reg avs_pcie_reconfig_readdatavalid,
input avs_pcie_reconfig_clk, // 50 MHz
input avs_pcie_reconfig_rstn,
// DPRIO Interface
output reg dpriodisable,
output reg dprioin,
output reg dprioload,
output dpclk,
input dprioout
);
parameter device_address=0;
parameter port_address =0;
parameter base_address =0;
parameter implement_address_checking =1;
localparam IDLE_ST =0,
CHECK_ADDR_ST =1,
MDIO_START_ST =2,
CTRL_WR_ST =3,
CTRL_RD_ST =4,
ERR_ST =5,
MDIO_CLR_ST =6,
MDIO_PRE_ST =7,
MDIO_FRAME_ST =8,
CLEAR_WAITREQ_ST =9;
localparam MDIO_ADDR =2'b00,
MDIO_WRITE =2'b01,
MDIO_READ =2'b10,
MDIO_END =2'b11;
reg [3:0] cstate;
reg [3:0] nstate;
reg [1:0] error_status;
reg [4:0] hip_dev_addr;
reg [4:0] hip_port_addr;
reg [7:0] hip_base_addr;
reg [31:0] shift_dprioin;
reg [15:0] shift_dprioout;
reg [6:0] count_mdio_st;
reg [1:0] mdio_cycle;
reg read_cycle;
reg write_cycle;
wire valid_address;
reg valid_addrreg;
reg extended_dprio_access;
assign dpclk = avs_pcie_reconfig_clk;
// state machine
always @*
case (cstate)
//TODO : Confirm that Avalon-MM read and write at the same time is illegal
//TODO : Confirm that read or write, chipselect can not be de-asserted until
// waitrequest is de-asserted
IDLE_ST: begin
if ((avs_pcie_reconfig_readdatavalid==1'b0)&&(avs_pcie_reconfig_chipselect==1'b1))
nstate <= CHECK_ADDR_ST;
else
nstate <= IDLE_ST;
end
CHECK_ADDR_ST:
begin
if (valid_address==1'b0)
nstate <= ERR_ST;
else if (avs_pcie_reconfig_address[7] == 1'b1)
nstate <= MDIO_START_ST;
else if (write_cycle==1'b1)
nstate <= CTRL_WR_ST;
else if (read_cycle==1'b1)
nstate <= CTRL_RD_ST;
else
nstate <= IDLE_ST;
end
MDIO_START_ST:
nstate <= MDIO_CLR_ST;
CTRL_WR_ST:
nstate <= CLEAR_WAITREQ_ST;
CTRL_RD_ST:
nstate <= CLEAR_WAITREQ_ST;
ERR_ST:
nstate <= CLEAR_WAITREQ_ST;
MDIO_CLR_ST:
//send 16 zero's to clear the MDIO state machine
//TODO : Check if it's necessary for every read/write transaction or if it's only
// necessary after the first reset
if (count_mdio_st==0) begin
if (mdio_cycle==MDIO_END)
nstate <= CLEAR_WAITREQ_ST;
else
nstate <= MDIO_PRE_ST;
end
else
nstate <= MDIO_CLR_ST;
MDIO_PRE_ST:
// Preamble 32-bit 1's
if (count_mdio_st==0)
nstate <= MDIO_FRAME_ST;
else
nstate <= MDIO_PRE_ST;
MDIO_FRAME_ST:
if (count_mdio_st==0) begin
if (mdio_cycle==MDIO_END)
nstate <= MDIO_CLR_ST;
else
nstate <= MDIO_PRE_ST;
end
else
nstate <= MDIO_FRAME_ST;
CLEAR_WAITREQ_ST:
nstate <= IDLE_ST;
default:
nstate <= IDLE_ST;
endcase
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
cstate <= IDLE_ST;
else
cstate <= nstate;
end
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
mdio_cycle <= MDIO_ADDR;
else if (cstate==MDIO_START_ST)
mdio_cycle <= MDIO_ADDR;
else if ((cstate==MDIO_FRAME_ST) && (count_mdio_st==6'h1F)) begin
if ((mdio_cycle==MDIO_ADDR) && (write_cycle==1'b1))
mdio_cycle <= MDIO_WRITE;
else if ((mdio_cycle==MDIO_ADDR) && (read_cycle==1'b1))
mdio_cycle <= MDIO_READ;
else if ((mdio_cycle==MDIO_WRITE) || (mdio_cycle==MDIO_READ))
mdio_cycle <= MDIO_END;
end
end
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
//TODO Use multiple counter if speed is an issue
if (avs_pcie_reconfig_rstn==1'b0)
count_mdio_st <= 0;
else if (cstate==MDIO_START_ST)
count_mdio_st <= 6'hF;
else if (cstate==MDIO_CLR_ST) begin
if (count_mdio_st>0)
count_mdio_st<=count_mdio_st-1;
else
count_mdio_st<=6'h1F;
end
else if ((cstate==MDIO_PRE_ST)||(cstate==MDIO_FRAME_ST)) begin
if (count_mdio_st>0)
count_mdio_st<=count_mdio_st-1;
else if (mdio_cycle==MDIO_END)
count_mdio_st <= 6'hF;
else
count_mdio_st<=6'h1F;
end
else
count_mdio_st <= 0;
end
// MDIO dprioin, dprioload
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
shift_dprioin <= 32'h0;
else if (cstate==MDIO_PRE_ST) begin
// ST bits - Start of frame
shift_dprioin[31:30]<=2'b00;
// OP bits - Op Codes
if (mdio_cycle==MDIO_ADDR)
shift_dprioin[29:28]<=2'b00;
else if (mdio_cycle == MDIO_WRITE)
shift_dprioin[29:28]<=2'b01;
else // READ
shift_dprioin[29:28]=2'b11;
// Port, Device address
shift_dprioin[27:18] <= {port_address[4:0], device_address[4:0]};
// TA Bits Turnaround
// TODO : Check TA bit 0 which supposed to be Z for read?
shift_dprioin[17:16] <= 2'b10;
if (mdio_cycle==MDIO_ADDR)
// 0x80 is the range for vendor specific (altera) registers according to XAUI spec
shift_dprioin[15:0] = {8'h80,1'b0,avs_pcie_reconfig_address[6:0]};
else if (mdio_cycle==MDIO_WRITE)
shift_dprioin[15:0] = avs_pcie_reconfig_writedata[15:0];
else if (mdio_cycle==MDIO_READ)
shift_dprioin[15:0] = avs_pcie_reconfig_writedata[15:0];
end
else if (cstate==MDIO_FRAME_ST)
shift_dprioin[31:0] <= {shift_dprioin[30:0],1'b0};
end
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0) begin
dprioin <= 1'b0;
end
else if (cstate==MDIO_CLR_ST) begin
if (count_mdio_st>0)
dprioin <= 1'b0;
else if (mdio_cycle==MDIO_END)
dprioin <= 1'b0;
else
dprioin <= 1'b1;
end
else if (cstate==MDIO_PRE_ST) begin
if (count_mdio_st>0)
dprioin <= 1'b1;
else
dprioin <= shift_dprioin[31];
end
else if (cstate==MDIO_FRAME_ST) begin
// MDIO : MSB first
if (count_mdio_st>0)
dprioin <= shift_dprioin[30];
else if (mdio_cycle==MDIO_END)
dprioin <=1'b0;
else
dprioin <=1'b1;
end
else
dprioin <= 1'b0;
end
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
shift_dprioout <= 16'h0;
else
shift_dprioout[15:0] <= {shift_dprioout[14:0],dprioout};
end
// MDIO and status registers dpriodisable , dprioload
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0) begin
dpriodisable <= 1'b1;
dprioload <= 1'b0;
extended_dprio_access <=1'b0;
end
else if ((cstate==CTRL_WR_ST) &&
(avs_pcie_reconfig_address[6:0] == 7'h00 )) begin
dpriodisable <= avs_pcie_reconfig_writedata[0];
dprioload <= ~avs_pcie_reconfig_writedata[0];
end
else if ((cstate==CTRL_WR_ST) &&
(avs_pcie_reconfig_address[6:0] == 7'h03 )) begin
extended_dprio_access <= (avs_pcie_reconfig_writedata==16'hED10)?1'b1:1'b0;
end
end
// Avalon-MM Wait request
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
avs_pcie_reconfig_waitrequest <= 1'b1;
else if (nstate == CLEAR_WAITREQ_ST)
avs_pcie_reconfig_waitrequest <= 1'b0;
else
avs_pcie_reconfig_waitrequest <= 1'b1;
end
// Error Status registers
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
error_status[1:0] <= 2'b00;
else if (cstate==ERR_ST) begin
if (write_cycle==1'b1)
error_status[0] <= 1'b1;
if (read_cycle==1'b1)
error_status[1] <= 1'b1;
end
else if ((cstate == CTRL_WR_ST) &&
(avs_pcie_reconfig_address[6:0] == 7'h00))
// Clear error status registers
error_status[1:0] <= avs_pcie_reconfig_writedata[3:2];
end
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0) begin
// Default parameter
hip_dev_addr <= device_address;
hip_port_addr <= port_address;
end
else if ((cstate==CTRL_WR_ST) &&
(avs_pcie_reconfig_address[6:0] == 7'h01 )) begin
hip_dev_addr <= avs_pcie_reconfig_writedata[4:0];
hip_port_addr <= avs_pcie_reconfig_writedata[9:5];
end
end
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
// Default parameter
hip_base_addr <= base_address;
else if ((cstate==CTRL_WR_ST) &&
(avs_pcie_reconfig_address[6:0] == 7'h02 ))
hip_base_addr <= avs_pcie_reconfig_writedata[7:0];
end
always @ (posedge avs_pcie_reconfig_clk) begin
if (cstate==IDLE_ST)
avs_pcie_reconfig_readdata <= 16'hFFFF;
else if (cstate==CTRL_RD_ST)
case (avs_pcie_reconfig_address[6:0])
7'h0 : avs_pcie_reconfig_readdata <= {12'h0,error_status[1:0], 1'b0, dpriodisable};
7'h1 : avs_pcie_reconfig_readdata <= {6'h0,hip_dev_addr[4:0], hip_port_addr[4:0]};
7'h2 : avs_pcie_reconfig_readdata <= {8'h0,hip_base_addr[7:0]};
7'h3 : avs_pcie_reconfig_readdata <= 16'hFADE;
default : avs_pcie_reconfig_readdata <= 16'hFFFF;
endcase
else if ((cstate==MDIO_CLR_ST)&&(count_mdio_st==6'hF))
avs_pcie_reconfig_readdata <= shift_dprioout;
end
always @ (posedge avs_pcie_reconfig_clk) begin
if ((cstate==CLEAR_WAITREQ_ST)&&(read_cycle==1'b1))
avs_pcie_reconfig_readdatavalid <=1'b1;
else
avs_pcie_reconfig_readdatavalid <=1'b0;
end
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0) begin
read_cycle <= 1'b0;
write_cycle <= 1'b0;
end
else if ((cstate==IDLE_ST) && (avs_pcie_reconfig_chipselect==1'b1)) begin
read_cycle <= avs_pcie_reconfig_read;
write_cycle <= avs_pcie_reconfig_write;
end
end
assign valid_address = (implement_address_checking==0)?1'b1:valid_addrreg;
always @ (negedge avs_pcie_reconfig_rstn or posedge avs_pcie_reconfig_clk) begin
if (avs_pcie_reconfig_rstn==1'b0)
valid_addrreg <= 1'b1;
else if (cstate==IDLE_ST) begin
if (avs_pcie_reconfig_address[7]==1'b0) begin
// Control register address space
if (avs_pcie_reconfig_address[6:0] > 7'h4)
valid_addrreg <=1'b0;
else
valid_addrreg <=1'b1;
end
else begin
// MDIO register HIP address space
if ((avs_pcie_reconfig_address[6:0] < 7'h9) && (extended_dprio_access==1'b0))
valid_addrreg <=1'b0;
else if ((avs_pcie_reconfig_address[6:0] > 7'h5E) && (extended_dprio_access==1'b0))
valid_addrreg <=1'b0;
else if ((avs_pcie_reconfig_address[6:0]>7'h40)&&(avs_pcie_reconfig_address[6:0]<7'h59) && (extended_dprio_access==1'b0))
valid_addrreg <=1'b0;
else
valid_addrreg <=1'b1;
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:28:56 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_stub.v
// Design : system_vga_pll_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_pll,Vivado 2016.4" *)
module system_vga_pll_0_0(clk_100, clk_50, clk_25, clk_12_5, clk_6_25)
/* synthesis syn_black_box black_box_pad_pin="clk_100,clk_50,clk_25,clk_12_5,clk_6_25" */;
input clk_100;
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2B_4_V
`define SKY130_FD_SC_HS__NAND2B_4_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand2b_4 (
Y ,
A_N ,
B ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand2b_4 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2B_4_V
|
/* Copyright 2005-2006, Technologic Systems
* All Rights Reserved.
*
* Author(s): Jesse Off <joff@...>
*
* Boilerplate Verilog for use in Technologic Systems TS-7300 FPGA computer
* at http://www.embeddedarm.com/epc/ts7300-spec-h.htm. Implements bus cycle
* demultiplexing to an internal 16 and 32 bit WISHBONE bus, and 10/100
* ethernet interfrootace.
*
* Full-featured FPGA bitstream from Technologic Systems includes "TS-SDCORE"
* SD card core, 8 "TS-UART" serial ports, "TS-VIDCORE" VGA video framebuffer and
* accelerator, and 2 PWM/Timer/Counter "TS-XDIO" cores for the various GPIO
* pins. Binary bitstream comes with board. Contact Technologic Systems
* for custom FPGA development on the TS-7300 or for non-GPL licensing of this
* or any of the above (not-included-here) TS-cores and OS drivers.
*
* To load the bitstream to the FPGA on the TS-7300, Technologic Systems provides
* a Linux program "load_ts7300" that takes the ts7300_top.rbf file generated
* by Altera's Quartus II on the Linux flash filesystem (yaffs, ext2,
* jffs2, etc..) and loads the FPGA. Loading the FPGA takes approx 0.2 seconds
* this way and can be done (and re-done) at any time during power-up without
* any special JTAG/ISP cables.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License v2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This module is a sample dummy stub that can be filled in by the user. Any access's on
* the TS-7300 CPU for address 0x72a00000 to 0x72fffffc arrive here. Keep in mind
* the address is a word address not the byte address and address 0x0 is 0x72000000.
* The interface used here is the WISHBONE bus, described in detail on
* http://www.opencores.org
*
* There is a 40-pin header next to the FPGA. It is broken up into 2 20 pin
* connectors. One is labeled DIO2 and contains the 18 dedicated GPIO pins. The
* other contains 17 signals that are used by the TS-VIDCORE but can also be used
* as GPIO if video is not used. DO NOT DRIVE THESE SIGNALS OVER 3.3V!!! They
* go straight into the FPGA pads unbuffered.
* ___________________________________________________________
* | 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40|
* | 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39|
* \-----------------------------------------------------------/
* * | * DIO2
*
* pins #2 and #22 are grounds
* pin #20 is fused 5V (polyfuse)
* pin #40 is regulated 3.3V
* pin #18 can be externally driven high to disable DB15 VGA connector DACs
* pin #36 and #38 also go to the red and green LEDs (active low)
* pin #39 is a dedicated clock input and cannot be programmed for output
*
*/
/***********************************
*
* UserCore modified version. Modification author
* [email protected] January 2008, April 2009.
*
* Modified to provide bi-directional data on the header pins by the activation
* of the oe register and alteration of the usercore into vga, dio and misc
* registers.
*
*/
/******************************************************************
* Stub module removed and substituted with ts_7300_usercore.vhd
* which is easier if you are more familiar with vhdl. The mapping
* (component/instance) is near the bottom of this file.
* Also dummyreg was undeclared anywhere so needed to be added to usercore.
*
*
* ***************************************************************/
/* Now begins the real guts of the TS-7300 Cyclone2 EP2C8 FPGA
* boilerplate. You should only have to look below here if the above
* stub module isn't enough for you.
*/
module ts7300_top(
fl_d_pad,
bd_pad,
isa_add11_pad,
isa_add12_pad,
isa_add14_pad,
isa_add15_pad,
isa_add1_pad,
add_pad,
start_cycle_pad,
bd_oe_pad,
dio0to8_pad,
dio9_pad,
dio10to17_pad,
sdram_data_pad,
clk_25mhz_pad,
clk_75mhz_pad,
isa_wait_pad,
dma_req_pad,
irq7_pad,
sd_soft_power_pad,
sd_hard_power_pad,
sd_wprot_pad,
sd_present_pad,
sd_dat_pad,
sd_clk_pad,
sd_cmd_pad,
eth_mdio_pad,
eth_mdc_pad,
eth_rxdat_pad,
eth_rxdv_pad,
eth_rxclk_pad,
eth_rxerr_pad,
eth_txdat_pad,
eth_txclk_pad,
eth_txen_pad,
eth_txerr_pad,
eth_col_pad,
eth_crs_pad,
eth_pd_pad,
sdram_add_pad,
sdram_ras_pad,
sdram_cas_pad,
sdram_we_pad,
sdram_ba_pad,
sdram_clk_pad,
wr_232_pad,
rd_mux_pad,
mux_cntrl_pad,
mux_pad,
blue_pad,
red_pad,
green_pad,
hsync_pad,
vsync_pad
);
inout [7:0] fl_d_pad; /* to/from max2 */
inout [7:0] bd_pad; /* to/from arm sdram */
input isa_add11_pad; /* buffered/muxed from add11 */
input isa_add12_pad; /* ditto add12*/
input isa_add14_pad; /* ditto add14*/
input isa_add15_pad; /* ditto add15*/
input isa_add1_pad; /* is this misnamed? isa_add01 ? from max2? check in pin file*/
input [3:0] add_pad; /* add17, add18, add19, add20 from arm9*/
input start_cycle_pad; /* bus cycle start from max2 (equ wb_cyc) */
input bd_oe_pad;
inout [8:0] dio0to8_pad;
input dio9_pad;
inout [7:0] dio10to17_pad;
inout [15:0] sdram_data_pad;
input clk_25mhz_pad;
output clk_75mhz_pad;
inout isa_wait_pad;
inout dma_req_pad;
inout irq7_pad;
output sd_soft_power_pad;
output sd_hard_power_pad;
input sd_wprot_pad;
input sd_present_pad;
inout [3:0] sd_dat_pad;
output sd_clk_pad;
inout sd_cmd_pad;
inout eth_mdio_pad;
output eth_mdc_pad;
input [3:0] eth_rxdat_pad;
input eth_rxdv_pad;
input eth_rxclk_pad;
input eth_rxerr_pad;
output [3:0] eth_txdat_pad;
input eth_txclk_pad;
output eth_txen_pad;
output eth_txerr_pad;
input eth_col_pad;
input eth_crs_pad;
output eth_pd_pad;
output [12:0] sdram_add_pad;
output sdram_ras_pad;
output sdram_cas_pad;
output sdram_we_pad;
output [1:0] sdram_ba_pad;
output wr_232_pad;
output rd_mux_pad;
output mux_cntrl_pad;
inout [3:0] mux_pad;
inout [4:0] blue_pad;
inout [4:0] red_pad;
inout [4:0] green_pad;
inout hsync_pad;
inout vsync_pad;
output sdram_clk_pad;
/* Set to 1'b0 to disable ethernet. If you disable this, don't
* attempt to load the ethernet driver module! */
parameter ethernet = 1'b0;
/* Bus cycles from the ep9302 processor come in to the FPGA multiplexed by
* the MAX2 CPLD on the TS-7300. Any access on the ep9302 for addresses
* 0x72000000 - 0x72ffffff are routed to the FPGA. The ep9302 CS7 SMCBCR register
* at 0x8008001c physical should be set to 0x10004508 -- 16-bit,
* ~120 nS bus cycle. The FPGA must be loaded and sending 75Mhz to the MAX2
* on clk_75mhz_pad before any bus cycles are attempted.
*
* Since the native multiplexed bus is a little unfriendly to deal with
* and non-standard, as our first order of business we translate it into
* something more easily understood and better documented: a 16 bit WISHBONE bus.
*/
reg epwbm_done, epwbm_done32;
reg isa_add1_pad_q;
reg [23:0] ep93xx_address;
reg epwbm_we_o, epwbm_stb_o;
wire [23:0] epwbm_adr_o;
reg [15:0] epwbm_dat_o;
reg [15:0] epwbm_dat_i;
reg [15:0] ep93xx_dat_latch;
reg epwbm_ack_i;
wire epwbm_clk_o = clk_75mhz_pad;
wire epwbm_cyc_o = start_cycle_posedge_q;
wire ep93xx_databus_oe = !epwbm_we_o && start_cycle_posedge && !bd_oe_pad;
wire pll_locked, clk_150mhz;
wire epwbm_rst_o = !pll_locked;
assign fl_d_pad[7:0] = ep93xx_databus_oe ?ep93xx_dat_latch[7:0] : 8'hzz;
assign bd_pad[7:0] = ep93xx_databus_oe ?ep93xx_dat_latch[15:8] : 8'hzz;
assign isa_wait_pad = start_cycle_negedge ? epwbm_done : 1'bz;
assign epwbm_adr_o[23:2] = ep93xx_address[23:2];
reg ep93xx_address1_q;
assign epwbm_adr_o[0] = ep93xx_address[0];
assign epwbm_adr_o[1] = ep93xx_address1_q;
/* Use Altera's PLL to multiply 25Mhz from the ethernet PHY to 75Mhz */
pll clkgencore(
.inclk0(clk_25mhz_pad),
.c0(clk_150mhz),
.c1(clk_75mhz_pad),
.locked(pll_locked)
);
reg ep93xx_end, ep93xx_end_q;
reg start_cycle_negedge, start_cycle_posedge, bd_oe_negedge,
bd_oe_posedge;
reg start_cycle_negedge_q, start_cycle_posedge_q;
reg bd_oe_negedge_q, bd_oe_posedge_q;
always @(posedge clk_75mhz_pad)
begin
start_cycle_negedge_q <= start_cycle_negedge;
start_cycle_posedge_q <= start_cycle_posedge;
bd_oe_negedge_q <= bd_oe_negedge;
bd_oe_posedge_q <= bd_oe_posedge;
isa_add1_pad_q <= isa_add1_pad;
if ((bd_oe_negedge_q && epwbm_we_o) ||
(start_cycle_posedge_q && !epwbm_we_o) && !epwbm_done)
begin
epwbm_stb_o <= 1'b1;
ep93xx_address1_q <= isa_add1_pad_q;
epwbm_dat_o <= {bd_pad[7:0], fl_d_pad[7:0]};
end
if (epwbm_stb_o && epwbm_ack_i)
begin
epwbm_stb_o <= 1'b0;
epwbm_done <= 1'b1;
ep93xx_dat_latch <= epwbm_dat_i;
end
if (epwbm_done && !epwbm_done32 &&
(ep93xx_address[1] !=isa_add1_pad_q))
begin
epwbm_done <= 1'b0;
epwbm_done32 <= 1'b1;
end
ep93xx_end_q <= 1'b0;
if ((start_cycle_negedge_q && start_cycle_posedge_q &&
bd_oe_negedge_q && bd_oe_posedge) || !pll_locked)
begin
ep93xx_end <= 1'b1;
ep93xx_end_q <= 1'b0;
end
if (ep93xx_end)
begin
ep93xx_end <= 1'b0;
ep93xx_end_q <= 1'b1;
epwbm_done32 <= 1'b0;
epwbm_stb_o <= 1'b0;
epwbm_done <= 1'b0;
start_cycle_negedge_q <= 1'b0;
start_cycle_posedge_q <= 1'b0;
bd_oe_negedge_q <= 1'b0;
bd_oe_posedge_q <= 1'b0;
end
end
wire start_cycle_negedge_aset = !start_cycle_pad && pll_locked;
always @(posedge ep93xx_end_q or posedge start_cycle_negedge_aset)
begin
if (start_cycle_negedge_aset)
start_cycle_negedge <= 1'b1;
else start_cycle_negedge <= 1'b0;
end
always @(posedge start_cycle_pad or posedge ep93xx_end_q)
begin
if (ep93xx_end_q)
start_cycle_posedge <= 1'b0;
else
if (start_cycle_negedge)
start_cycle_posedge <= 1'b1;
end
always @(posedge start_cycle_pad)
begin
epwbm_we_o <= fl_d_pad[7];
ep93xx_address[23] <= fl_d_pad[0];
ep93xx_address[22] <= fl_d_pad[1];
ep93xx_address[21] <= fl_d_pad[2];
ep93xx_address[20:17] <= add_pad[3:0];
ep93xx_address[16] <= fl_d_pad[3];
ep93xx_address[15] <= isa_add15_pad;
ep93xx_address[14] <= isa_add14_pad;
ep93xx_address[13] <= fl_d_pad[4];
ep93xx_address[12] <= isa_add12_pad;
ep93xx_address[11] <= isa_add11_pad;
ep93xx_address[10] <= bd_pad[0];
ep93xx_address[9] <= bd_pad[1];
ep93xx_address[8] <= bd_pad[2];
ep93xx_address[7] <= bd_pad[3];
ep93xx_address[6] <= bd_pad[4];
ep93xx_address[5] <= bd_pad[5];
ep93xx_address[4] <= bd_pad[6];
ep93xx_address[3] <= bd_pad[7];
ep93xx_address[2] <= fl_d_pad[5];
ep93xx_address[1] <= isa_add1_pad;
ep93xx_address[0] <= fl_d_pad[6];
end
always @(negedge bd_oe_pad or posedge ep93xx_end_q)
begin
if (ep93xx_end_q)
bd_oe_negedge <= 1'b0;
else
if (start_cycle_posedge)
bd_oe_negedge <= 1'b1;
end
always @(posedge bd_oe_pad or posedge ep93xx_end_q)
begin
if (ep93xx_end_q)
bd_oe_posedge <= 1'b0;
else
if (bd_oe_negedge)
bd_oe_posedge <= 1'b1;
end
wire [15:0] epwbm_wb32m_bridgecore_dat;
wire epwbm_wb32m_bridgecore_ack;
wire [31:0] wb32m_dat_o;
reg [31:0] wb32m_dat_i;
wire [21:0] wb32m_adr_o;
wire [3:0] wb32m_sel_o;
wire wb32m_cyc_o, wb32m_stb_o, wb32m_we_o;
reg wb32m_ack_i;
wire wb32m_clk_o = epwbm_clk_o;
wire wb32m_rst_o = epwbm_rst_o;
wb32_bridge epwbm_wb32m_bridgecore
(
.wb_clk_i(epwbm_clk_o),
.wb_rst_i(epwbm_rst_o),
.wb16_adr_i(epwbm_adr_o[23:1]),
.wb16_dat_i(epwbm_dat_o),
.wb16_dat_o(epwbm_wb32m_bridgecore_dat),
.wb16_cyc_i(epwbm_cyc_o),
.wb16_stb_i(epwbm_stb_o),
.wb16_we_i(epwbm_we_o),
.wb16_ack_o(epwbm_wb32m_bridgecore_ack),
.wbm_adr_o(wb32m_adr_o),
.wbm_dat_o(wb32m_dat_o),
.wbm_dat_i(wb32m_dat_i),
.wbm_cyc_o(wb32m_cyc_o),
.wbm_stb_o(wb32m_stb_o),
.wbm_we_o(wb32m_we_o),
.wbm_ack_i(wb32m_ack_i),
.wbm_sel_o(wb32m_sel_o)
);
/* At this point we have turned the multiplexed ep93xx bus cycle into a
* WISHBONE master bus cycle with the local regs/wires:
*
* [15:0] epwbm_dat_i -- WISHBONE master 16-bit databus input
* [15:0] epwbm_dat_o -- WISHBONE master 16-bit databus output
* epwbm_clk_o -- WISHBONE master clock output (75 Mhz)
* epwbm_rst_o -- WISHBONE master reset output
* [23:0] epwbm_adr_o -- WISHBONE byte address output
* epwbm_we_o -- WISHBONE master write enable output
* epwbm_stb_o -- WISHBONE master strobe output
* epwbm_cyc_o -- WISHBONE master cycle output
* epwbm_ack_i -- WISHBONE master ack input
*
* The WISHBONE slave or WISHBONE interconnect can withhold the bus cycle ack
* as long as necessary as the above logic will ensure the processor will be
* halted until the cycle is complete. In that regard, it is possible
* to lock up the processor if nothing acks the WISHBONE bus cycle. (!)
*
* Note that the above is only a 16-bit WISHBONE bus. A special WISHBONE
* to WISHBONE bridge is used to combine two back-to-back 16 bit reads or
* writes into a single atomic 32-bit WISHBONE bus cycle. Care should be
* taken to never issue a byte or halfword ARM insn (ldrh, strh, ldrb, strb) to
* address space handled here. This bridge is presented as a secondary
* WISHBONE master bus prefixed with wb32m_:
*
* [31:0] wb32m_dat_i -- WISHBONE master 32-bit databus input
* [31:0] wb32m_dat_o -- WISHBONE master 32-bit databus output
* wb32m_clk_o -- WISHBONE master clock output (75 Mhz)
* wb32m_rst_o -- WISHBONE master reset output
* [21:0] wb32m_adr_o -- WISHBONE master word address
* wb32m_we_o -- WISHBONE master write enable output
* wb32m_stb_o -- WISHBONE master strobe output
* wb32m_cyc_o -- WISHBONE master cycle output
* wb32m_ack_i -- WISHBONE master ack input
* wb32m_sel_o -- WISHBONE master select output -- always 4'b1111
*/
/******************************************************************
* blue_pad, green_pad etc, etc are the physical pin I/Os.
* headerpin_o is the data to be output.
* headerpin_oe should be the tristate control.
* headerpin_i should be the incoming data
* This is a hacked version to try and get the I/O tristate
* control to synthesise properly :(
*******************************************************/
wire [31:0] usercore_dat;
wire usercore_ack;
reg usercore_stb;
wire [40:1] headerpin_i;
reg [40:1] temp_reg;
wire [40:1] headerpin_oe, headerpin_o;
integer i;
// grab the current inputs
assign headerpin_i[1] = blue_pad[0];
assign headerpin_i[3] = blue_pad[1];
assign headerpin_i[5] = blue_pad[2];
assign headerpin_i[7] = blue_pad[3];
assign headerpin_i[9] = blue_pad[4];
assign headerpin_i[11] = green_pad[0];
assign headerpin_i[13] = green_pad[1];
assign headerpin_i[15] = green_pad[2];
assign headerpin_i[17] = green_pad[3];
assign headerpin_i[19] = green_pad[4];
assign headerpin_i[4] = red_pad[0];
assign headerpin_i[6] = red_pad[1];
assign headerpin_i[8] = red_pad[2];
assign headerpin_i[10] = red_pad[3];
assign headerpin_i[12] = red_pad[4];
assign headerpin_i[21] = dio0to8_pad[0];
assign headerpin_i[23] = dio0to8_pad[1];
assign headerpin_i[25] = dio0to8_pad[2];
assign headerpin_i[27] = dio0to8_pad[3];
assign headerpin_i[29] = dio0to8_pad[4];
assign headerpin_i[31] = dio0to8_pad[5];
assign headerpin_i[33] = dio0to8_pad[6];
assign headerpin_i[35] = dio0to8_pad[7];
assign headerpin_i[37] = dio0to8_pad[8];
assign headerpin_i[24] = dio10to17_pad[0];
assign headerpin_i[26] = dio10to17_pad[1];
assign headerpin_i[28] = dio10to17_pad[2];
assign headerpin_i[30] = dio10to17_pad[3];
assign headerpin_i[32] = dio10to17_pad[4];
assign headerpin_i[34] = dio10to17_pad[5];
assign headerpin_i[36] = dio10to17_pad[6];
assign headerpin_i[38] = dio10to17_pad[7];
assign headerpin_i[39] = dio9_pad;
assign headerpin_i[14] = hsync_pad;
assign headerpin_i[16] = vsync_pad;
// misc fixed values
assign headerpin_i[22] = 1'b0;
assign headerpin_i[40] = 1'b1;
assign headerpin_i[2] = 1'b0;
assign headerpin_i[20] = 1'b1;
assign headerpin_i[18] = 1'b0;
// assign outputs or tristates
assign blue_pad[0] = temp_reg[1];
assign blue_pad[1] = temp_reg[3];
assign blue_pad[2] = temp_reg[5];
assign blue_pad[3] = temp_reg[7];
assign blue_pad[4] = temp_reg[9];
assign green_pad[0] = temp_reg[11];
assign green_pad[1] = temp_reg[13];
assign green_pad[2] = temp_reg[15];
assign green_pad[3] = temp_reg[17];
assign green_pad[4] = temp_reg[19];
assign red_pad[0] = temp_reg[4];
assign red_pad[1] = temp_reg[6];
assign red_pad[2] = temp_reg[8];
assign red_pad[3] = temp_reg[10];
assign red_pad[4] = temp_reg[12];
assign vsync_pad = temp_reg[16];
assign hsync_pad = temp_reg[14];
assign dio0to8_pad[0] = temp_reg[21];
assign dio0to8_pad[1] = temp_reg[23];
assign dio0to8_pad[2] = temp_reg[25];
assign dio0to8_pad[3] = temp_reg[27];
assign dio0to8_pad[4] = temp_reg[29];
assign dio0to8_pad[5] = temp_reg[31];
assign dio0to8_pad[6] = temp_reg[33];
assign dio0to8_pad[7] = temp_reg[35];
assign dio0to8_pad[8] = temp_reg[37];
assign dio10to17_pad[0] = temp_reg[24];
assign dio10to17_pad[1] = temp_reg[26];
assign dio10to17_pad[2] = temp_reg[28];
assign dio10to17_pad[3] = temp_reg[30];
assign dio10to17_pad[4] = temp_reg[32];
assign dio10to17_pad[5] = temp_reg[34];
assign dio10to17_pad[6] = temp_reg[36];
assign dio10to17_pad[7] = temp_reg[38];
always @( headerpin_o or headerpin_oe )
begin
for (i = 0; i < 5; i = i + 1)
begin
if (headerpin_oe[1 + (i * 2)])
temp_reg[1+(i*2)] =headerpin_o[1 + (i * 2)];
else
temp_reg[1 + (i * 2)] = 1'bz;
if (headerpin_oe[11 + (i * 2)])
temp_reg[11 + (i * 2)] = headerpin_o[11 + (i * 2)];
else
temp_reg[11 + (i * 2)] = 1'bz;
if (headerpin_oe[4 + (i * 2)])
temp_reg[4 + (i * 2)] = headerpin_o[4 + (i * 2)];
else
temp_reg[4 + (i * 2)] = 1'bz;
end
for (i = 0; i < 8; i = i + 1)
begin
if (headerpin_oe[24 + (i * 2)])
temp_reg[24 + (i * 2)] = headerpin_o[24 + (i * 2)];
else
temp_reg[24 + (i * 2)] = 1'bz;
if (headerpin_oe[21 + (i * 2)])
temp_reg[21 + (i * 2)] = headerpin_o[21 + (i * 2)];
else
temp_reg[21 + (i * 2)] = 1'bz;
end
if (headerpin_oe[14])
temp_reg[14] = headerpin_o[14];
else
temp_reg[14] = 1'bz;
if (headerpin_oe[16])
temp_reg[16] = headerpin_o[16];
else
temp_reg[16] = 1'bz;
if (headerpin_oe[37])
temp_reg[37] = headerpin_o[37];
else
temp_reg[37] = 1'bz;
end
wire usercore_drq, usercore_irq;
// SDRAM
wire [12:0] uc_sdram_add_pad;
wire uc_sdram_ras_pad;
wire uc_sdram_cas_pad;
wire uc_sdram_we_pad;
wire [1:0] uc_sdram_ba_pad;
wire [15:0] uc_sdram_data_pad_i;
wire [15:0] uc_sdram_data_pad_o;
reg uc_sdram_data_pad_oe;
////////////////////////////////////////////////////////////////////////
// this is the interface to your component. It shouldn't need changing//
////////////////////////////////////////////////////////////////////////
ts7300_usercore usercore
(
.wb_clk_i(wb32m_clk_o),
.wb_rst_i(wb32m_rst_o),
.wb_cyc_i(wb32m_cyc_o),
.wb_stb_i(usercore_stb),
.wb_we_i(wb32m_we_o),
.wb_ack_o(usercore_ack),
.wb_dat_o(usercore_dat),
.wb_dat_i(wb32m_dat_o),
.wb_adr_i(wb32m_adr_o),
.headerpin_i(headerpin_i[40:1]),
.headerpin_o(headerpin_o[40:1]),
.headerpin_oe_o(headerpin_oe[40:1]),
.irq_o(usercore_irq),
.sdram_ras_o( sdram_ras_pad ),
.sdram_cas_o( sdram_cas_pad ),
.sdram_we_n_o( sdram_we_pad ),
.sdram_ba_o( sdram_ba_pad ),
.sdram_saddr_o( sdram_add_pad ),
.sdram_sdata_i( uc_sdram_data_pad_i ),
.sdram_sdata_o( uc_sdram_data_pad_o ),
.sdram_sdata_oe( uc_sdram_data_pad_oe )
);
/* IRQ7 is actually ep9302 VIC IRQ #40 */
assign irq7_pad = ( usercore_irq ) ? 1'b1 : 1'bz;
//assign sdram_add_pad = uc_sdram_add_pad;
//assign sdram_ba_pad = uc_sdram_ba_pad;
//assign sdram_cas_pad = uc_sdram_cas_pad;
//assign sdram_ras_pad = uc_sdram_ras_pad;
//assign sdram_we_pad = uc_sdram_we_pad;
assign sdram_clk_pad = clk_75mhz_pad & pll_locked;
assign sdram_data_pad = uc_sdram_data_pad_oe ? uc_sdram_data_pad_o :
16'bz;
assign uc_sdram_data_pad_i = uc_sdram_data_pad_oe ?
uc_sdram_data_pad_i : sdram_data_pad;
/* Now we set up the address decode and the return WISHBONE master
* databus and ack signal multiplexors. This is very simple, on the native
* WISHBONE bus (epwbm_*) if the address is >= 0x72100000, the 16 to 32 bit
* bridge is selected. The 32 bit wishbone bus contains 3 wishbone
* slaves: the ethernet core, the ethernet packet RAM, and the usercore. If the
* address >= 0x72a00000 the usercore is strobed and expected to ack, for
* address >= 0x72102000 the ethernet core is strobed and expected to ack
* otherwise the bus cycle goes to the ethernet RAM core.
*/
always @(epwbm_adr_o or epwbm_wb32m_bridgecore_dat or
epwbm_wb32m_bridgecore_ack or usercore_dat or usercore_ack or
wb32m_adr_o or wb32m_stb_o)
begin
epwbm_dat_i = 16'hxxxx;
epwbm_ack_i = 1'bx;
if (epwbm_adr_o >= 24'h100000)
begin
epwbm_dat_i = epwbm_wb32m_bridgecore_dat;
epwbm_ack_i = epwbm_wb32m_bridgecore_ack;
end
usercore_stb = 1'b0;
// ethcore_stb = 1'b0;
// ethramcore_stb = 1'b0;
// if (wb32m_adr_o >= 22'h280000) begin
usercore_stb = wb32m_stb_o;
wb32m_dat_i = usercore_dat;
wb32m_ack_i = usercore_ack;
// end
end
/* Various defaults for signals not used in this boilerplate project: */
/* No use for DMA -- used by TS-SDCORE on shipped bitstream */
assign dma_req_pad = 1'bz;
/* PHY always on */
assign eth_pd_pad = 1'b1;
/* SDRAM signals outputing 0's -- used by TS-VIDCORE in shipped
bitstream */
/*
assign sdram_add_pad = 12'd0;
assign sdram_ba_pad = 2'd0;
assign sdram_cas_pad = 1'b0;
assign sdram_ras_pad = 1'b0;
assign sdram_we_pad = 1'b0;
assign sdram_clk_pad = 1'b0;
assign sdram_data_pad = 16'd0;
*/
/* serial (RS232) mux signals safely "parked" -- used by TS-UART */
assign rd_mux_pad = 1'b1;
assign mux_cntrl_pad = 1'b0;
assign wr_232_pad = 1'b1;
assign mux_pad = 4'hz;
/* SD flash card signals "parked" -- used by TS-SDCORE */
assign sd_soft_power_pad = 1'b0;
assign sd_hard_power_pad = 1'b1;
assign sd_dat_pad = 4'hz;
assign sd_clk_pad = 1'b0;
assign sd_cmd_pad = 1'bz;
endmodule
|
`timescale 1ns / 1ps
/* All files are owned by Kris Kalavantavanich.
* Feel free to use/modify/distribute in the condition that this copyright header is kept unmodified.
* Github: https://github.com/kkalavantavanich/SD2017 */
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 05/18/2017 11:17:30 PM
// Design Name: Main SD Module
// Module Name: main
// Project Name: SD2017
// Target Devices: Basys3
// Revision: 1.21
// Revisiom 1.21 - Complete CRCD (CRC-16 Data In)
// Revision 1.20 - Added UBADDR + (partial CRCD)
// Revision 1.10 - Branched from Revision 1.07 (remove v1.08)
// Revision 1.07 - Replaced RD Communication State Logic with main state logic
// Revision 1.06 - Debug
// Revision 1.05 - Debug
// Revision 1.04 - Debug
// Revision 1.03 - Debug
// Revision 1.02 - Debug
// Revision 1.01 - Removed led[3:0] output due to synthesis error
// Revision 1.00 - Finished Read Operation
// Revision 0.01 - File Created
// Additional Comments:
//
// KNOWN BUGS //
//
// F_CPU = 100000000 (100 MHz)
// F_SPI = 390625 (390.6 kHz)
//////////////////////////////////////////////////////////////////////////////////
// SPI Connection:
// PIN1 = Data[0] = JA[0] = 7 = MISO
// PIN2 = Data[1] = JA[1] = 8
// PIN3 = Data[2] = JA[2] = 9
// PIN4 = Data[3] = JA[3] = 1 = CS (active low)
// PIN7 = CLK = JA[4] = 5 = CLK
// PIN8 = CMD = JA[5] = 2 = MOSI
// PIN9 = CD = JA[6]
// PIN10 = WP = JA[7]
module main(
input _cpuClock,
input [15:0] sw,
input btnC,
input btnU,
input btnD,
input btnL,
input btnR,
output [15:0] led,
output [6:0] seg,
output dp,
output [3:0] an,
input SD_MISO, SD_CD, SD_WP,
output SD_CLK, SD_MOSI, SD_CS
,
input [31:0] UBDI, // Data In from MB
output [31:0] UBDO, // Data Out to MB
output UBEO, // Error Out to MB (Active HIGH)
output UBRRI, // ReadReadyInterrupt to MB (Active HIGH)
input UBRRA, // ReadReadyAcknowledge from MB (Active HIGH)
input UBRM, // read mode
input UBWM, // write mode
input [31:0] UBADDR // Block Address
);
// CPU CLOCK PRESCALER //
localparam PRESCALE = 8; // Use to slowdown CPU CLOCK
wire cpuClock;
//clockDiv #(PRESCALE) c00 (_cpuClock, cpuClock); // Slowed (Debugging)
assign cpuClock = _cpuClock; // Not Slowed (Normal Operation)
// RESET BUTTON //
wire globalReset;
assign globalReset = btnU || btnC;
// ERROR REGISTER //
reg [7:0] _errorState = 0; // Last state before error occured
wire _errorNoti;
// COMMANDS //
reg [5:0] CMD_INDEX; // Command Index (CMD0 - CMD63)
reg [31:0] CMD_ARG; // 32-bit Command Argument
reg CMD_TRANSMIT; // 0 => Receiver, 1 => Transmitter
// Communication Master (CM) //
reg CM_EN = 0; // Enable
reg CM_RST = 1; // Reset
reg cmSpiClkEn = 1; // Enable SPI Clock Output
reg CMClkBS = 0; // 0 = not activate, 1 = activate byte sync mode
wire CM_EINT; // Error Interrupt
wire [3:0] CM_ETYPE; // Error Type
wire [3:0] CM_EST; // Errored State
reg [1:0] CM_RM = 2'b00; // Read Mode
wire [39:0] CM_RR; // Read Response (Read Data Buffer)
reg CM_STA = 0; // Start
wire CM_FIN; // Finished
wire CM_MISO, CM_CD, CM_WP; // => From SD
wire CM_SCLK, CM_MOSI, CM_CS; // <= To SD
spiCommMaster CMM (cpuClock, CM_EN, CM_RST, cmSpiClkEn, CMClkBS,
CM_EINT, CM_ETYPE, CM_EST,
CMD_TRANSMIT, CMD_INDEX, CMD_ARG,
CM_RM, CM_RR,
CM_STA, CM_FIN,
CM_MISO, CM_CD, CM_WP, CM_SCLK, CM_MOSI, CM_CS);
// INTERNAL //
reg spiClockEn = 0;
reg INTL_MOSI = 1, INTL_CS = 1;
reg INTLTM_RST = 1; // Internal Timer Reset
wire [9:0] INTLTM_OUT;
wire INTLTM_OV; // Internal Timer Overflow
counter #(10) INTLTM (CM_SCLK, INTLTM_RST, INTLTM_OUT, INTLTM_OV);
reg [39:0] INTL_RR = 0; // Internal Read Response
reg trySDv1 = 1;
// SPI PROTOCOL PORT CONNECTION //
assign CM_MISO = SD_MISO;
assign CM_CD = SD_CD;
assign CM_WP = SD_WP;
assign SD_CLK = (spiClockEn ? CM_SCLK : 1'b1) ; // also controlled by cmSpiClkEn
assign SD_MOSI = (CM_EN ? CM_MOSI : INTL_MOSI);
assign SD_CS = (CM_EN ? CM_CS : INTL_CS);
//// Outsize Communication Ports (UB - MicroBlaze)
//wire [31:0] UBDI; // Data In from MB
//wire [31:0] UBDO; // Data Out to MB
//wire UBEO; // Error Out to MB (Active HIGH)
//wire UBRRI; // ReadReadyInterrupt to MB (Active HIGH)
//wire UBRRA; // ReadReadyAcknowledge from MB (Active HIGH)
//wire UBRM; // read mode
//wire UBWM; // write mode
//wire UBADDR;
//assign UBRM = btnR;
//assign UBWM = btnL;
//assign UBRRA = btnD;
//assign UBADDR = 32'h0;
// Data Read //
reg [6:0] _yb = 0; // vertical SD reading (128)
// Single Read (8-bit)
reg INTLRS_ST = 0;
wire INTLRS_FIN;
reg [7:0] INTLRS_BUFF;
wire [7:0] INTLRS_OUT;
reg INTLRS_WFBI = 1;
spiRead #(1) INTLRSM (CM_SCLK, INTLRS_ST, SD_MISO, INTLRS_FIN, INTLRS_OUT, INTLRS_WFBI);
// Double Read (16-bit)
reg INTLRD_ST = 0;
wire INTLRD_FIN;
reg [15:0] INTLRD_BUFF;
wire [15:0] INTLRD_OUT;
reg INTLRD_WFBI = 0;
spiRead #(2) INTLRDM (CM_SCLK, INTLRD_ST, SD_MISO, INTLRD_FIN, INTLRD_OUT, INTLRD_WFBI);
// Quad read (32-bit)
reg INTLRQ_ST = 0;
wire INTLRQ_FIN;
reg [31:0] INTLRQ_BUFF;
wire [31:0] INTLRQ_OUT;
reg INTLRQ_WFBI = 0;
spiRead #(4) INTLRQM (CM_SCLK, INTLRQ_ST, SD_MISO, INTLRQ_FIN, INTLRQ_OUT, INTLRQ_WFBI);
// CRC-16 For Data (CRCD) //
// uses CPU CLOCK
wire CRCD_IN;
reg CRCD_CLR = 1;
reg CRCD_EN = 0;
wire [15:0] CRCD_OUT;
reg [15:0] CRCD_OUT_BUFF;
crcGenerator #(.LEN(16)) CRCDM (CRCD_IN, CM_SCLK, CRCD_CLR, CRCD_EN, 17'b1_00010000_00100001, CRCD_OUT);
assign CRCD_IN = SD_MISO;
// Data Reader (DR) //
reg DR_DRI = 0; // <= Data Ready Interrupt
wire DR_DACK; // => Data Ready Acknowledge
reg DREO = 0; // <= Data Reader Error Out
wire [31:0] DR_OUT; // Data Read output
assign DR_OUT = (DR_DRI) ? INTLRQ_BUFF : 32'bZ;
assign UBDO = DR_OUT; // Data Out to MB
assign UBEO = DREO;
assign UBRRI = DR_DRI; // ReadReadyInterrupt to MB (Active HIGH)
assign DR_DACK = UBRRA; // ReadReadyAcknowledge from MB (Active HIGH)
// STATES //
// 0x0- : error states
// 0x1- : power sequence states
// 0x2- : initialization states (1)
// 0x3- : initialization states (2)
// 0x40 : data transfer standby
// 0x6- : read
// 0xA- : write
reg [7:0] state = 8'h10;
reg [7:0] nstate = 8'h10;
assign _errorNoti = state[7:4] == 4'b0;
// main loop //
always @ (negedge cpuClock) begin
if(globalReset) begin
_errorState <= 8'h0;
nstate <= 8'h10;
INTLTM_RST <= 1; // Stop Internal Timer
CM_RST <= 1; // Reset Communication Master
DREO <= 0;
end else begin
case (state)
8'h07: begin // card locked error
if (SD_WP) begin
nstate <= 8'h10;
end
end
8'h10: begin // wait for card
CM_RST <= 0; // Start Communication Master (Use CM_CLK)
CM_EN <= 0; // Disable Communication Master (Use Internal CS and Timer)
if (!SD_CD) begin
INTLTM_RST <= 0; // Start Internal Timer With SPI Clock from CMM
nstate <= 8'h11;
end
end
8'h11: begin // wait >= 1ms
if (INTLTM_OUT > 200) begin
spiClockEn <= 1; // Main Enable SPI Clock Set for the rest of operation
INTL_CS <= 1; // Set CS HIGH per SD specification
INTLTM_RST <= 1; // Stop Internal Timer
nstate <= 8'h12;
end
end
8'h12: begin // ctrReset sync
if (INTLTM_OUT == 0) begin // wait until counter is set to 0 at SPI Clock
INTLTM_RST <= 0; // Start Inter Internal Timer With SPI Clock from CMM
nstate <= 8'h13;
end
end
8'h13: begin // wait for at least 74 SPI clocks
if (INTLTM_OUT > 74) begin
CM_EN <= 1;
nstate <= 8'h14;
end
end
8'h14: begin // [CMD0] Set CMD
INTLTM_RST <= 1; // reset Internal Timer
CMD_INDEX <= 0; // CMD 0
CMD_ARG <= 0;
CMD_TRANSMIT <= 1;
CM_STA <= 1; // Start Communication Master
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h15;
end
8'h15: begin // [CMD0] wait for CM
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05; // CM Error
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR = CM_RR;
nstate <= 8'h16;
end
end
8'h16: begin // [CMD0] check response
if (INTL_RR[7:0] == 8'b1) nstate <= 8'h20;
else begin // init response error (unknown device)
_errorState <= state;
nstate <= 8'h02; // response error
end
end
8'h20: begin // standby (card idle state)
//if (check?)
nstate <= 8'h24; // Check Voltage range
end
8'h24: begin // [CMD8] Set CMD
CMD_INDEX <= 6'h08; // CMD8: Send Interface Condition Command
CMD_ARG <= {24'h000001, 8'hAA}; // AA = 8-bit check pattern
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 2;
nstate <= 8'h25;
end
8'h25: begin // [CMD8] wait for CM
if (CM_EINT) begin
if(CM_ETYPE == 4'b0010) begin // timeout => Might be SDv1
trySDv1 <= 0;
CM_RST <= 1;
nstate <= 8'h28; // goto 'set CMD55' state
end else begin
nstate <= 8'h05; // CM Error
end
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h26;
end
end
8'h26: begin // [CMD8] check response
if (INTL_RR[11:0] == 12'h1AA) begin
nstate <= 8'h28; // SDv2
end else if(INTL_RR[39:32] == 8'h05) begin
trySDv1 <= 0;
nstate <= 8'h28; // SDv1? => try SDv1
end else begin
_errorState = state;
nstate <= 8'h03; // Unknown Card Error
end
end
8'h28: begin // [CMD55] set CMD (SDv1 & SDv2)
CMD_INDEX <= 55; // CMD55: Application Specific Command (APP_CMD)
CMD_ARG <= 0;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h29;
end
8'h29: begin // [CMD55] wait for CM (SDv1 & SDv2)
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05; // CM Error
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h2A; // delay check response to next clock for safety
end
end
8'h2A: begin // [CMD55] check response (SDv1 & SDv2)
if (INTL_RR[7:0] == 8'h01) begin // Definitely SDv2
nstate <= 8'h2C;
end else if (INTL_RR[7:0] == 8'h05) begin // Is it SD v1?
if (trySDv1) begin // Have we tried SD v1?
trySDv1 <= 0;
nstate <= 8'h28; // goto 'Set CMD55' State
end else begin // Not SD v1 and SD v2
nstate <= 8'h03; // Unknown Card Error
end
end else begin
_errorState <= state;
nstate <= 8'h03; // Unknown Card Error
end
end
8'h2C: begin // [ACMD41] Set CMD (SDv1 & SDv2 -- different in ACMD41_ARG)
CMD_INDEX <= 41; // ACMD41
CMD_ARG <= {(trySDv1 ? 4'h4 : 4'h0), 28'h0};
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h2D;
end
8'h2D: begin // [ACMD41] wait for reading (SDv1 & SDv2)
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05; // CM Error
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h2E;
end
end
8'h2E: begin // [ACMD41] check response (SDv1 & SDv2)
if (INTL_RR[7:0] == 8'h01) begin // Not finished
nstate <= 8'h28; // Set CMD 58
end else if (INTL_RR[7:0] == 8'h00) begin // finished
if (trySDv1) begin // SDv2
nstate <= 8'h30; // goto `Set CMD58` State
end else begin // SDv1
nstate <= 8'h38; // goto `Set CMD16` State
end
end else if (INTL_RR[7:0] == 8'h05) begin // 'invalid command'
if (trySDv1) begin // Have we tried SD v1?
trySDv1 <= 0;
nstate <= 8'h28; // goto 'Set CMD55' State
end else begin // Not SD v1 and SD v2
_errorState = state;
nstate <= 8'h03; // Unknown Card Error
end
end else begin
_errorState = state;
nstate <= 8'h03; // Unknown Card Error
end
end
8'h30: begin // [CMD58] set CMD
CMD_INDEX <= 58; // CMD58 - gen_crc
CMD_ARG <= 32'h0;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 2;
nstate <= 8'h31;
end
8'h31: begin // [CMD58] wait for CM
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05; // CM Error
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h32; // delay check response to next clock for safety
end
end
8'h32: begin // [CMD58] check response
if (INTL_RR[30] == 1) begin // CSS bit: determines whether High Capacity (HC) Card or not
// HC => Finish Initialize
nstate <= 8'h40;
end else begin
// Standard Capacity => force block size
nstate <= 8'h34;
end
end
8'h34: begin // [CMD16] Set CMD
CMD_INDEX <= 16; // CMD16
CMD_ARG <= 32'h00000200; // Force Block Size = 512 bytes for FAT filesystem
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h35;
end
8'h35: begin // [CMD16] wait for CM
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05; // CM Error
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h36;
end
end
8'h36: begin // [CMD16] Check response
if (INTL_RR[7:0] == 8'h01) begin
nstate <= 8'h40;
end else begin
nstate <= 8'h02;
_errorState <= state;
end
end
8'h40: begin
// finished initialization
if (SD_CD) begin
nstate <= 8'h10;
end
if (UBRM) begin
nstate <= 8'h60;
end else if (UBWM) begin
nstate <= 8'hA0;
end
end
8'h60: begin // [CMD17] Set CMD
CMD_INDEX <= 17; // CMD17 (Read Single Block)
CMD_ARG <= UBADDR; // Address = 0
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h61;
end
8'h61: begin // [CMD17] Wait for CM
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h62;
end
end
8'h62: begin // [CMD17] Check Response
if (INTL_RR[7:0] == 8'h00) begin
CM_EN <= 0; // Disable CM
INTL_MOSI <= 1;
INTL_CS <= 0;
INTLTM_RST <= 0;
spiClockEn <= 0;
nstate <= 8'h64; // goto ' wait for reading //
end else begin
_errorState <= state;
nstate <= 8'h02; // Response Error
end
end
8'h64: begin // Start Reading into INTLRS (Data Token Receive)
if (INTLRS_FIN == 0) begin // check whether previous reading `stop` has been acknowledged
INTLRS_ST <= 1; // start reading
INTLRS_WFBI <= 0;
spiClockEn <= 1;
nstate <= 8'h65;
end
end
8'h65: begin // wait for INTLRS reading
if (INTLRS_FIN) begin
nstate <= 8'h66;
INTLRS_ST <= 0;
INTLRS_WFBI <= 1;
INTLRS_BUFF <= INTLRS_OUT;
end
end
8'h66: begin // check response of INTLRS (Data Token)
if (INTLRS_BUFF == 8'hFE) begin // received data token for CMD17/18/24
INTLTM_RST <= 1;
nstate <= 8'h67;
end else if (INTLRS_BUFF == 8'hFC) begin // received data token for CMD25
_errorState <= state;
nstate <= 8'h02;
end else if (INTLRS_BUFF == 8'hFD) begin // Stop trans token for CMD25
_errorState <= state;
nstate <= 8'h02;
end else if (INTLRS_BUFF == 8'hFF) begin
if (INTLTM_OUT > 200) begin
INTLTM_RST <= 1;
_errorState <= state;
nstate <= 8'h01;
end else begin
spiClockEn <= 0;
nstate <= 8'h64; // go back
end
end else begin
_errorState <= state;
nstate <= 8'h02; // illegal response
end
end
8'h67: begin // Start Reading Loop (y) - 32 bit
_yb <= 0;
CRCD_CLR <= 0;
nstate <= 8'h68;
end
8'h68: begin // Read Data Loop body (1)
INTLRQ_ST <= 1;
spiClockEn <= 1;
DR_DRI <= 0;
CRCD_EN <= 1;
nstate <= 8'h69;
end
8'h69: begin // Wait for Reading
if (INTLRQ_FIN) begin
spiClockEn <= 0;
INTLRQ_BUFF <= INTLRQ_OUT;
INTLRQ_ST <= 0;
DR_DRI <= 1;
CRCD_OUT_BUFF <= CRCD_OUT;
CRCD_EN <= 0;
nstate <= 8'h6A;
end else begin
spiClockEn <= 1;
end
end
8'h6A: begin // Check data
if (!INTLRQ_FIN && DR_DACK) begin
if (_yb == 7'h7F) begin // loop condition
_yb <= 0;
nstate <= 8'h70;
end else begin
_yb <= _yb + 1; // loop increment
nstate <= 8'h68;
end
end
end
8'h70: begin // Finish Reading Data => read CRC-16
INTLRD_ST <= 1;
spiClockEn <= 1;
nstate <= 8'h71;
end
8'h71: begin
if (INTLRD_FIN) begin
INTLRD_BUFF <= INTLRD_OUT;
INTLRD_ST <= 0;
nstate <= 8'h72;
end
end
8'h72: begin
if (INTLRD_BUFF == CRCD_OUT_BUFF) begin
DREO <= 0;
nstate <= 8'h74;
end else begin
DREO <= 1;
nstate <= 8'h08; // crc error
end
end
8'h74: begin //wait for data transfer to UB (Microblaze) complete.
CM_EN <= 1; // Enable CM
nstate <= 8'h40; // go back
end
8'h80: begin // [CMD18] Set CMD
CMD_INDEX <= 18; // CMD17 (Read Multi Block)
CMD_ARG <= UBADDR; // Address
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h81;
end
8'h81: begin // [CMD18] Wait for CM
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h82;
end
end
8'h82: begin // [CMD18] Check Response
if (INTL_RR[7:0] == 8'h00) begin
CM_EN <= 0; // Disable CM
INTL_MOSI <= 1;
INTL_CS <= 0;
INTLTM_RST <= 0;
spiClockEn <= 0;
nstate <= 8'h84; // goto ' wait for reading //
end else begin
_errorState <= state;
nstate <= 8'h02; // Response Error
end
end
8'h84: begin
end
8'hA0: begin // <single write>
end
default: begin
if(state[7:4] != 4'b0) begin
_errorState = state;
nstate = 8'h04;
end
end
endcase
end
end
always @ (posedge cpuClock) begin
if (nstate != state && nstate != state + 1 && nstate[1:0] != 2'b00 && nstate[7:4] != 4'h0) begin
state <= 8'h06; //Invalid state sequence
end else begin
state <= nstate;
end
end
// History of states //
// LSB = newest, MSB = oldest
reg [63:0] history = 0;
always @ (posedge cpuClock) begin
if (globalReset)begin
history = 0;
end else if (nstate != state) begin
history = {history[55:0], nstate};
end
end
// Seven Segment //
wire [2:0] historySel;
assign historySel = sw[10:8];
wire [15:0] numSegment;
wire segClock;
wire [3:0] aen;
assign numSegment = sw[11] ? {CM_EST, CM_ETYPE} : historySel == 0 ? {_errorState, state} : history[historySel * 8 +:7];
assign aen = ~sw[15:12];
clockDiv #(10) seg0 (cpuClock, segClock);
segMaster seg1 (segClock, numSegment, aen, seg, an, dp);
// debug
reg [255:0] historyBuff = 0;
always @ (posedge cpuClock) begin
if (globalReset)begin
historyBuff = 0;
end else if (INTLRQ_BUFF != historyBuff[31:0]) begin
historyBuff = {historyBuff[223:0], INTLRQ_BUFF};
end
end
wire [1:0] layer;
assign layer = sw[1:0];
wire cl0, cl1, cl2;
clockDiv #(12) d0 (cpuClock, cl0);
assign led = (sw[1] ? historyBuff[historySel * 32 + 16 +:15] : historyBuff[historySel * 32 +:15]);
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: asyn_256_139.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module asyn_256_139 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw);
input aclr;
input [138:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [138:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "139"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "139"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "139"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 139 0 INPUT NODEFVAL "data[138..0]"
// Retrieval info: USED_PORT: q 0 0 139 0 OUTPUT NODEFVAL "q[138..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL "wrusedw[7..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 139 0 data 0 0 139 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 139 0 @q 0 0 139 0
// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_139_wave*.jpg FALSE
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk_125mhz,
input wire clk90_125mhz,
input wire rst_125mhz,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire ledu,
output wire ledl,
output wire ledd,
output wire ledr,
output wire ledc,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
/*
* Silicon Labs CP2103 USB UART
*/
output wire uart_rxd,
input wire uart_txd,
input wire uart_rts,
output wire uart_cts
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk_125mhz) begin
if (rst_125mhz) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk_125mhz) begin
if (rst_125mhz) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign ledu = 0;
assign ledl = 0;
assign ledd = 0;
assign ledr = 0;
assign ledc = 0;
assign led = led_reg;
assign phy_reset_n = !rst_125mhz;
assign uart_rxd = 0;
assign uart_cts = 0;
eth_mac_1g_rgmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR"),
.CLOCK_INPUT_STYLE("BUFR"),
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk_125mhz),
.gtx_clk90(clk90_125mhz),
.gtx_rst(rst_125mhz),
.logic_clk(clk_125mhz),
.logic_rst(rst_125mhz),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(phy_rx_clk),
.rgmii_rxd(phy_rxd),
.rgmii_rx_ctl(phy_rx_ctl),
.rgmii_tx_clk(phy_tx_clk),
.rgmii_txd(phy_txd),
.rgmii_tx_ctl(phy_tx_ctl),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk_125mhz),
.rst(rst_125mhz),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:31:20 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/shadow_pixel_1/shadow_pixel_sim_netlist.v
// Design : shadow_pixel
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "shadow_pixel,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module shadow_pixel
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [10:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [10:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [10:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "11" *)
(* C_ADDRB_WIDTH = "11" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.5913 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "shadow_pixel.mem" *)
(* C_INIT_FILE_NAME = "shadow_pixel.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1080" *)
(* C_READ_DEPTH_B = "1080" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1080" *)
(* C_WRITE_DEPTH_B = "1080" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
shadow_pixel_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[10:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[10:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module shadow_pixel_blk_mem_gen_generic_cstr
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
shadow_pixel_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module shadow_pixel_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
shadow_pixel_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module shadow_pixel_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h1330133013301330133013301330133013301330133013301330133013301330),
.INIT_01(256'h1330000013300000133000001330000013301330133013301330133013301330),
.INIT_02(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_03(256'h1330133013301330133013301330133013301330133013301330133013300000),
.INIT_04(256'h1330133013301330133013301330133013301330133013301330133013301330),
.INIT_05(256'h0000133000001330000013300000133000001330133013301330133013301330),
.INIT_06(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_07(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_08(256'h1330133013301330133013301330133013301330133013301330133000001330),
.INIT_09(256'h1330000013300000133000001330133013301330133013301330133013301330),
.INIT_0A(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_0B(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_0C(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_0D(256'h0000133013301330133013301330133013301330133013301330133013301330),
.INIT_0E(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_0F(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_10(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_11(256'h1330133013301330133013300000133000001330000013300000133000001330),
.INIT_12(256'h1330000013300000133000001330000013300000133000001330133013301330),
.INIT_13(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_14(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_15(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_16(256'h0000133000001330000013300000133013301330133000001330000013300000),
.INIT_17(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_18(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_19(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_1A(256'h1330133000001330000013300000133000001330000013300000133000001330),
.INIT_1B(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_1C(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_1D(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_1E(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_1F(256'h0000133000001330000013300000133013300000133000001330000013300000),
.INIT_20(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_21(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_22(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_23(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_24(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_25(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_26(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_27(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_28(256'h0000133000001330000013300000133013300000133000001330000013300000),
.INIT_29(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_2A(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_2B(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_2C(256'h1330133000001330000013300000133000001330000013300000133000001330),
.INIT_2D(256'h1330000013300000133000001330000013300000133000001330133013301330),
.INIT_2E(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_2F(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_30(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_31(256'h0000133000001330133013301330133013301330133000001330000013300000),
.INIT_32(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_33(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_34(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_35(256'h1330133013301330133013300000133000001330000013300000133000001330),
.INIT_36(256'h1330000013300000133000001330133013301330133013301330133013301330),
.INIT_37(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_38(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_39(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_3A(256'h1330133013301330133013301330133013301330133013301330133013301330),
.INIT_3B(256'h0000133000001330000013300000133000001330133013301330133013301330),
.INIT_3C(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_3D(256'h0000133000001330000013300000133000001330000013300000133000001330),
.INIT_3E(256'h1330133013301330133013301330133013301330133013301330133000001330),
.INIT_3F(256'h1330133013301330133013301330133013301330133013301330133013301330),
.INIT_40(256'h1330000013300000133000001330000013301330133013301330133013301330),
.INIT_41(256'h1330000013300000133000001330000013300000133000001330000013300000),
.INIT_42(256'h1330133013301330133013301330133013301330133013301330133013300000),
.INIT_43(256'h0000000000000000000000000000000013301330133013301330133013301330),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[11:6],1'b0,1'b0,dina[5:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:16],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ,douta[11:6],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ,douta[5:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:2],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module shadow_pixel_blk_mem_gen_top
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
shadow_pixel_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "11" *) (* C_ADDRB_WIDTH = "11" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.5913 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "shadow_pixel.mem" *)
(* C_INIT_FILE_NAME = "shadow_pixel.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1080" *) (* C_READ_DEPTH_B = "1080" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1080" *) (* C_WRITE_DEPTH_B = "1080" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module shadow_pixel_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [10:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [10:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [10:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [10:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
shadow_pixel_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module shadow_pixel_blk_mem_gen_v8_3_5_synth
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
shadow_pixel_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2015 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2015.4
// \ \ Description : Xilinx Unified Simulation Library Component
// / / _no_description_
// /___/ /\ Filename : OBUFDS_DPHY.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OBUFDS_DPHY #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter IOSTANDARD = "DEFAULT"
)(
output O,
output OB,
input HSTX_I,
input HSTX_T,
input LPTX_I_N,
input LPTX_I_P,
input LPTX_T
);
// define constants
localparam MODULE_NAME = "OBUFDS_DPHY";
// Parameter encodings and registers
localparam IOSTANDARD_DEFAULT = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFDS_DPHY_dr.v"
`else
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
`endif
wire IOSTANDARD_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
reg OB_out;
reg O_out;
wire HSTX_I_in;
wire HSTX_T_in;
wire LPTX_I_N_in;
wire LPTX_I_P_in;
wire LPTX_T_in;
reg hs_mode = 1'b1;
assign (strong1,strong0) O = (hs_mode === 1'b0) ? O_out : 1'bz;
assign (strong1, strong0) OB = (hs_mode === 1'b0) ? OB_out : 1'bz;
assign (supply1,supply0) O = (hs_mode === 1'b1) ? O_out : 1'bz;
assign (supply1,supply0) OB = (hs_mode === 1'b1) ? OB_out : 1'bz;
assign HSTX_I_in = HSTX_I;
assign HSTX_T_in = HSTX_T;
assign LPTX_I_N_in = LPTX_I_N;
assign LPTX_I_P_in = LPTX_I_P;
assign LPTX_T_in = LPTX_T;
assign IOSTANDARD_BIN =
(IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT :
IOSTANDARD_DEFAULT;
//Commenting out the DRC check for IOSTANDARD attribute as it is not required as per IOTST.
/* initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((IOSTANDARD_REG != "DEFAULT"))) begin
$display("Error: [Unisim %s-101] IOSTANDARD attribute is set to %s. Legal values for this attribute are DEFAULT. Instance: %m", MODULE_NAME, IOSTANDARD_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
*/
always @ (LPTX_T_in or HSTX_T_in or LPTX_I_P_in or LPTX_I_N_in or HSTX_I_in) begin
if (LPTX_T_in === 1'b0) begin
O_out <= LPTX_I_P_in;
OB_out <= LPTX_I_N_in;
hs_mode <= 1'b0;
end else if (LPTX_T_in === 1'b1 && HSTX_T_in === 1'b0) begin
O_out <= HSTX_I_in;
OB_out <= ~HSTX_I_in;
hs_mode <= 1'b1;
end else begin
O_out <= 1'bz;
OB_out <= 1'bz;
hs_mode <= 1'bx;
end
end
specify
(HSTX_I => O) = (0:0:0, 0:0:0);
(HSTX_I => OB) = (0:0:0, 0:0:0);
(HSTX_T => O) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
(HSTX_T => OB) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
(LPTX_I_N => OB) = (0:0:0, 0:0:0);
(LPTX_I_P => O) = (0:0:0, 0:0:0);
(LPTX_T => O) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
(LPTX_T => OB) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_PP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire buf0_out_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Chrisky HU
//
// Create Date: 21:35:40 10/01/2015
// Design Name:
// Module Name: ElbertV2_FPGA_Board
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ElbertV2_FPGA_Board(
input[5:0] BTN,
input clk,
output[7:0] LED,
output [7:0] SevenSegment,
output [2:0] SevenSegment_Enable,
output IO_P1_1,
output IO_P1_3,
inout IO_P1_5
);
wire rst_n;
wire inc_n_btn;
wire btn2_n;
wire dht11_dat;
reg [1:0] state_func;
wire inc_n_debounced;
wire btn2_n_debounced;
wire btn6_debounced;
wire select_onehot;
wire rst_debounced;
wire clk_div_1Hz;
wire clk_div_1MHZ;
wire clk_div_1kHZ;
wire [9:0] counter_4bit_out;
wire [9:0] counter_10bit_out;
wire dummy;
wire [9:0]humid;
wire [9:0]temp;
wire [3:0]status;
wire [3:0] HUNDREDS;
wire [3:0] TENS;
wire [3:0] ONES;
wire start_dht11_capture;
reg auto_capture;
reg [3:0] auto_capture_counter;
reg auto_capture_start;
reg auto_capture_rst_n;
wire [3:0] data0a;
wire [3:0] data1a;
wire [3:0] data2a;
wire [3:0] data0b;
wire [3:0] data1b;
wire [3:0] data2b;
reg [3:0] LCD_3;
reg [3:0] LCD_2;
reg [3:0] LCD_1;
wire dht11_start;
wire rst_n_dht11;
assign rst_n = BTN[4];
assign inc_n_btn = ~BTN[0];
assign btn2_n = ~BTN[1];
assign LED[7] = counter_4bit_out[0];
assign LED[6] = counter_4bit_out[1];
assign LED[5] = btn2_n_debounced;
assign LED[4] = inc_n_debounced;
assign LED[3] = status[0];
assign LED[2] = status[1];
assign LED[1] = status[2];
assign LED[0] = status[3];
assign SevenSegment[0] = ~clk_div_1Hz;
assign IO_P1_1 = 1'b0;
assign IO_P1_3 = 1'b1;
assign IO_P1_5 = dht11_dat;
assign start_dht11_capture = auto_capture? auto_capture_start:btn2_n_debounced;
assign rst_n_dht11 = btn6_debounced;//auto_capture? auto_capture_rst_n:btn6_debounced;
assign humid[9:8] = 2'b0;
assign temp[9:8] = 2'b0;
//assign SevenSegment = counter_10bit_out[7:0];
always@(posedge clk or negedge rst_debounced)
begin
if(~rst_debounced)
begin
state_func <=2'b0;
auto_capture<=1'b0;
end
else
begin
if(select_onehot==1'b1)
state_func <=state_func +1;
case(counter_4bit_out[1:0])
2'b0:
begin
LCD_1 <= ONES;
LCD_2 <= TENS;
LCD_3 <= HUNDREDS;
auto_capture<=1'b0;
end
2'b1:
begin
LCD_1 <= data0a;
LCD_2 <= data1a;
LCD_3 <= data2a;
auto_capture<=1'b0;
end
2'b10:
begin
LCD_1 <= data0b;
LCD_2 <= data1b;
LCD_3 <= data2b;
auto_capture<=1'b0;
end
2'b11:
begin
LCD_1 <= data0a;
LCD_2 <= data1a;
LCD_3 <= data2a;
auto_capture<=1'b1;
end
endcase
end
end
/*
always@(posedge clk_div_1Hz or negedge rst_n)
begin
if(~rst_n)
auto_capture_counter<=4'b0;
else
begin
auto_capture_counter<=auto_capture_counter+1;
if (auto_capture_counter == 4'b1101)
begin
auto_capture_rst_n <=1'b0;
end
else
begin
auto_capture_rst_n <=1'b1;
if(auto_capture_counter[2:0] == 3'b111)
begin
auto_capture_start<=1'b1;
end
else
begin
auto_capture_start<=1'b0;
end
end
end
end
*/
always@(posedge clk_div_1Hz or negedge rst_n)
begin
if(~rst_n)
begin
auto_capture_counter<=4'b0;
auto_capture_start<=1'b0;
end
else
begin
auto_capture_counter<=auto_capture_counter+1;
if(auto_capture_counter[2:0] == 3'b111)
auto_capture_start<=1'b1;
else
auto_capture_start<=1'b0;
end
end
freqdiv freqdiv1(clk,rst_n,clk_div_1Hz,2'b01);
freqdiv freqdiv2(clk,rst_n,clk_div_1MHZ,2'b00);
freqdiv freqdiv3(clk,rst_n,clk_div_1kHZ,2'b10);
debounce debounce_inc(clk_div_1kHZ,inc_n_btn,inc_n_debounced);
debounce debounce_start(clk_div_1kHZ,btn2_n,btn2_n_debounced);
debounce debounce_dht11_rst(clk_div_1kHZ,BTN[5],btn6_debounced);
debounce debounce_rst(clk_div_1kHZ,rst_n,rst_debounced);
new_counter theNewCounter(rst_n,inc_n_debounced,counter_4bit_out);
new_counter the10bitCounter(rst_n,clk_div_1Hz,counter_10bit_out);
mySevenSegment sevenSegementDec(clk,rst_debounced,LCD_1,LCD_2,LCD_3,SevenSegment[7:1],SevenSegment_Enable);
BINARY_TO_BCD theBinary2BCD(counter_10bit_out, HUNDREDS,TENS,ONES);
BINARY_TO_BCD theBinary2BCDhumid(humid, data2a,data1a,data0a);
BINARY_TO_BCD theBinary2BCDtemp(temp, data2b,data1b,data0b);
dht11_driver dht11_driver(clk_div_1MHZ,rst_n_dht11,start_dht11_capture,dht11_dat,humid[7:0],temp[7:0],status);
endmodule
|
/* Copyright (C) 2015-2016 by John Cronin
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module debounce(
clk,
PB,
PB_state
);
input clk;
input PB;
output PB_state;
reg init_state = 1'b0;
reg PB_state = 1'b0;
// Next declare a 16-bits counter
reg [11:0] PB_cnt = 12'd0;
wire PB_cnt_max = &PB_cnt;
wire PB_idle = (PB_cnt == 12'd0);
wire PB_changed = (PB != init_state);
always @(posedge clk)
if(PB_idle & PB_changed)
begin
init_state = PB;
PB_cnt = 12'd1;
end
else if(PB_cnt_max)
begin
PB_state = init_state;
PB_cnt = 12'd0;
end
else if(~PB_idle)
PB_cnt = PB_cnt + 12'd1;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_BLACKBOX_V
`define SKY130_FD_SC_HS__TAPMET1_BLACKBOX_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapmet1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__SDFRTP_BEHAVIORAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_r_no_pg/sky130_fd_sc_hs__u_df_p_r_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfrtp (
VPWR ,
VGND ,
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_r_no_pg u_df_p_r_no_pg0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_BEHAVIORAL_PP_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_mout.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// jbi_mout -- Process outbound JBus transaction requests.
// _____________________________________________________________________________
//
`include "sys.h"
`include "jbi.h"
module jbi_mout (/*AUTOARG*/
// Outputs
mout_pio_req_adv, mout_pio_pop, mout_mondo_pop, jbi_io_j_adtype,
jbi_io_j_adtype_en, jbi_io_j_ad, jbi_io_j_ad_en, jbi_io_j_adp,
jbi_io_j_adp_en, jbi_io_j_req0_out_l, jbi_io_j_req0_out_en, jbi_io_j_pack0,
jbi_io_j_pack0_en, jbi_io_j_pack1, jbi_io_j_pack1_en,
mout_dsbl_sampling, mout_trans_yid, mout_trans_valid,
mout_scb0_jbus_wr_ack, mout_scb1_jbus_wr_ack, mout_scb2_jbus_wr_ack,
mout_scb3_jbus_wr_ack, mout_scb0_jbus_rd_ack, mout_scb1_jbus_rd_ack,
mout_scb2_jbus_rd_ack, mout_scb3_jbus_rd_ack, mout_nack, mout_nack_buf_id,
mout_nack_thr_id, mout_min_inject_err_done, mout_csr_inject_output_done, mout_min_jbus_owner,
mout_port_4_present, mout_port_5_present, mout_csr_err_cpar, mout_csr_jbi_log_par_jpar,
mout_csr_jbi_log_par_jpack0, mout_csr_jbi_log_par_jpack1, mout_csr_jbi_log_par_jpack4,
mout_csr_jbi_log_par_jpack5, mout_csr_jbi_log_par_jreq, mout_csr_err_arb_to,
jbi_log_arb_myreq, jbi_log_arb_reqtype, jbi_log_arb_aok, jbi_log_arb_dok, jbi_log_arb_jreq,
mout_csr_err_fatal, mout_csr_err_read_to,
mout_perf_aok_off, mout_perf_dok_off, mout_dbg_pop,
// Inputs
scbuf0_jbi_data, scbuf0_jbi_ctag_vld, scbuf0_jbi_ue_err,
sctag0_jbi_por_req_buf, scbuf1_jbi_data, scbuf1_jbi_ctag_vld,
scbuf1_jbi_ue_err, sctag1_jbi_por_req_buf, scbuf2_jbi_data,
scbuf2_jbi_ctag_vld, scbuf2_jbi_ue_err, sctag2_jbi_por_req_buf,
scbuf3_jbi_data, scbuf3_jbi_ctag_vld, scbuf3_jbi_ue_err,
sctag3_jbi_por_req_buf, ncio_pio_req, ncio_pio_req_rw, ncio_pio_req_dest,
ncio_pio_ad, ncio_pio_ue, ncio_pio_be, ncio_yid, ncio_mondo_req,
ncio_mondo_ack, ncio_mondo_agnt_id, ncio_mondo_cpu_id, ncio_prqq_level,
ncio_makq_level, io_jbi_j_pack4, io_jbi_j_pack5, io_jbi_j_req4_in_l,
io_jbi_j_req5_in_l, io_jbi_j_par, min_free, min_free_jid, min_trans_jid,
min_aok_on, min_aok_off, min_snp_launch, ncio_mout_nack_pop, min_mout_inject_err,
csr_jbi_config_arb_mode, csr_jbi_arb_timeout_timeval,
csr_jbi_trans_timeout_timeval,
csr_jbi_err_inject_errtype, csr_jbi_err_inject_xormask,
csr_jbi_debug_info_enb, csr_dok_on,
csr_jbi_debug_arb_aggr_arb, csr_jbi_error_config_fe_enb, csr_jbi_log_enb_read_to, dbg_req_transparent,
dbg_req_arbitrate, dbg_req_priority, dbg_data, testmux_sel, hold, rst_tri_en,
cclk, crst_l, clk, rst_l, tx_en_local_m1, arst_l
);
`include "jbi_mout.h"
// SCTAG0.
input [31:0] scbuf0_jbi_data;
input scbuf0_jbi_ctag_vld; // Header cycle of a new response packet.
input scbuf0_jbi_ue_err; // Current data cycle has a uncorrectable error.
input sctag0_jbi_por_req_buf; // Request for DOK_FATAL.
// SCTAG1.
input [31:0] scbuf1_jbi_data;
input scbuf1_jbi_ctag_vld; // Header cycle of a new response packet.
input scbuf1_jbi_ue_err; // Current data cycle has a uncorrectable error.
input sctag1_jbi_por_req_buf; // Request for DOK_FATAL.
// SCTAG2.
input [31:0] scbuf2_jbi_data;
input scbuf2_jbi_ctag_vld; // Header cycle of a new response packet.
input scbuf2_jbi_ue_err; // Current data cycle has a uncorrectable error.
input sctag2_jbi_por_req_buf; // Request for DOK_FATAL.
// SCTAG3.
input [31:0] scbuf3_jbi_data;
input scbuf3_jbi_ctag_vld; // Header cycle of a new response packet.
input scbuf3_jbi_ue_err; // Current data cycle has a uncorrectable error.
input sctag3_jbi_por_req_buf; // Request for DOK_FATAL.
// Non-Cache IO (ncio).
input ncio_pio_req;
input ncio_pio_req_rw;
input [1:0] ncio_pio_req_dest;
output mout_pio_req_adv;
input [63:0] ncio_pio_ad;
input ncio_pio_ue;
input [15:0] ncio_pio_be;
input [`JBI_YID_WIDTH-1:0] ncio_yid;
output mout_pio_pop;
//
input ncio_mondo_req;
input ncio_mondo_ack; // 1=ack; 0=nack
input [`JBI_AD_INT_AGTID_WIDTH-1:0] ncio_mondo_agnt_id;
input [`JBI_AD_INT_CPUID_WIDTH-1:0] ncio_mondo_cpu_id;
output mout_mondo_pop;
input [`JBI_PRQQ_ADDR_WIDTH:0] ncio_prqq_level; // Number of received PIO requests in queue
input [`JBI_MAKQ_ADDR_WIDTH:0] ncio_makq_level; // Number of INTACK/NACK transmit requests in queue.
// IO.
output [7:0] jbi_io_j_adtype;
output jbi_io_j_adtype_en;
output [127:0] jbi_io_j_ad;
output [3:0] jbi_io_j_ad_en;
input [2:0] io_jbi_j_pack4;
input [2:0] io_jbi_j_pack5;
output [3:0] jbi_io_j_adp;
output jbi_io_j_adp_en;
input io_jbi_j_req4_in_l;
input io_jbi_j_req5_in_l;
output jbi_io_j_req0_out_l;
output jbi_io_j_req0_out_en;
output [2:0] jbi_io_j_pack0;
output jbi_io_j_pack0_en;
output [2:0] jbi_io_j_pack1;
output jbi_io_j_pack1_en;
input io_jbi_j_par;
// DTL Control.
output mout_dsbl_sampling;
// Memory In (jbi_min).
input min_free; // Free an assignment to ...
input [3:0] min_free_jid; // 'min_free_jid[]'.
input [`JBI_JID_WIDTH-1:0] min_trans_jid; // Translate this JID to a YID.
output [`JBI_YID_WIDTH-1:0] mout_trans_yid; // Translated 'min_trans_jid[]'.
output mout_trans_valid; // Translation is valid qualifier.
output mout_scb0_jbus_wr_ack; // Inform when L2 sends Write Ack to JBus. (cmp clock)
output mout_scb1_jbus_wr_ack;
output mout_scb2_jbus_wr_ack;
output mout_scb3_jbus_wr_ack;
output mout_scb0_jbus_rd_ack; // Inform when we put read return data on JBus. (jbus clock)
output mout_scb1_jbus_rd_ack;
output mout_scb2_jbus_rd_ack;
output mout_scb3_jbus_rd_ack;
input min_aok_on; // Requests for AOK Flow Control.
input min_aok_off;
input min_snp_launch; // Issue COHACK.
input ncio_mout_nack_pop; // YID recovery from Timedout JBus read request.
output mout_nack;
output [1:0] mout_nack_buf_id;
output [5:0] mout_nack_thr_id;
input min_mout_inject_err; // J_AD error injection request.
output mout_min_inject_err_done;
output mout_csr_inject_output_done;
output [5:0] mout_min_jbus_owner; // JBus owner (logged by min block into JBI_LOG_CTRL[OWNER] as source of data return).
// CSRs (jbi_csr).
input [1:0] csr_jbi_config_arb_mode; // "Arbiter Mode" control from JBI_CONFIG register.
output mout_port_4_present; // "Port Present" in JBI_CONFIG register.
output mout_port_5_present; //
output mout_csr_err_cpar; // "JBus Control Parity Error" to Error Handling registers:
output mout_csr_jbi_log_par_jpar; // log J_PAR
output [2:0] mout_csr_jbi_log_par_jpack0; // log J_PACK0
output [2:0] mout_csr_jbi_log_par_jpack1; // log J_PACK1
output [2:0] mout_csr_jbi_log_par_jpack4; // log J_PACK4
output [2:0] mout_csr_jbi_log_par_jpack5; // log J_PACK5
output [6:0] mout_csr_jbi_log_par_jreq; // log J_REQ[6:0]
output mout_csr_err_arb_to; // "Arbitration Timeout Error" to Error Handling registers:
input [31:0] csr_jbi_arb_timeout_timeval; // "Arbitration Timeout Error" timeout interval.
output [2:0] jbi_log_arb_myreq; // log MYREQ.
output [2:0] jbi_log_arb_reqtype; // log REQTYPE.
output [6:0] jbi_log_arb_aok; // log AOK
output [6:0] jbi_log_arb_dok; // log DOK
output [6:0] jbi_log_arb_jreq; // log J_REQs
output [5:4] mout_csr_err_fatal; // "Reported Fatal Error" to Error Handling registers.
output mout_csr_err_read_to; // "Transaction Timeout - Read Req" to Error Handling registers.
input [31:0] csr_jbi_trans_timeout_timeval; // Interval counter wraparound value.
input csr_jbi_err_inject_errtype; //
input [3:0] csr_jbi_err_inject_xormask; //
output mout_perf_aok_off; // Performance Counter events - AOK OFF
output mout_perf_dok_off; // DOK OFF
input csr_jbi_debug_info_enb; // Put Debug Info in high half of JBus Address Cycles.
input csr_dok_on; // CSR request for DOK_FATAL.
input csr_jbi_debug_arb_aggr_arb; // AGGR_ARB bit of JBI_DEBUG_ARB register.
input csr_jbi_error_config_fe_enb; // Enable DOK Fatal for non-JBI fatal errors.
input csr_jbi_log_enb_read_to; // When negated, do not report Read Timeout errors.
// Dbg.
input dbg_req_transparent; // The Debug Info queue a valid request and wants it sent without impacting the JBus flow.
input dbg_req_arbitrate; // The Debug Info queue a valid request and want fair round robin arbitration.
input dbg_req_priority; // The Debug Info queue a valid request and needs it sent right away.
input [127:0] dbg_data; // Data to put on the JBus.
output mout_dbg_pop; // When asserted, pop the transaction header from the Debug Info queue.
// Misc.
input testmux_sel; // Memory and ATPG test mode signal.
input hold;
input rst_tri_en;
// Clock and reset.
input cclk; // CMP clock.
input crst_l; // CMP clock domain reset.
input clk; // JBus clock.
input rst_l; // JBus clock domain reset.
input tx_en_local_m1; // CMP to JBI clock domain crossing synchronization pulse.
input arst_l; // Asynch reset.
// Wires and Regs.
wire [3:0] int_req_type;
wire [6:0] int_requestors;
wire [127:0] jbi_io_j_ad;
wire [3:0] jbi_io_j_adp;
wire [7:0] jbi_io_j_adtype;
wire [3:0] sel_j_adbus;
wire [3:0] unused_jid;
wire [31:0] scbuf0_jbi_data, scbuf1_jbi_data, scbuf2_jbi_data, scbuf3_jbi_data;
wire [3:0] sct0rdq_trans_count, sct1rdq_trans_count, sct2rdq_trans_count, sct3rdq_trans_count;
wire [5:0] sct0rdq_jid, sct1rdq_jid, sct2rdq_jid, sct3rdq_jid;
wire [127:0] sct0rdq_data, sct1rdq_data, sct2rdq_data, sct3rdq_data;
wire [2:0] sel_queue;
wire [3:0] inj_err_j_ad;
wire [`JBI_YID_WIDTH-1:0] mout_trans_yid;
wire [3:0] nack_error_id;
wire [1:0] ignored;
// SCT0 Outbound Request Queues.
jbi_sct_out_queues sct0_out_queues (
// SCTAG/BUF Outbound Requests and Return Data.
.scbuf_jbi_data (scbuf0_jbi_data),
.scbuf_jbi_ctag_vld (scbuf0_jbi_ctag_vld),
.scbuf_jbi_ue_err (scbuf0_jbi_ue_err),
// JBI Outbound Interface.
.sctrdq_trans_count (sct0rdq_trans_count),
.sctrdq_data1_4 (sct0rdq_data1_4),
.sctrdq_install_state (sct0rdq_install_state),
.sctrdq_unmapped_error (sct0rdq_unmapped_error),
.sctrdq_jid (sct0rdq_jid),
.sctrdq_data (sct0rdq_data),
.sctrdq_ue_err (sct0rdq_ue_err),
.sctrdq_dec_count (sct0rdq_dec_count),
.sctrdq_dequeue (sct0rdq_dequeue),
// Memory In (jbi_min).
.mout_scb_jbus_wr_ack (mout_scb0_jbus_wr_ack),
// Misc.
.testmux_sel (testmux_sel),
.hold (hold),
.rst_tri_en (rst_tri_en),
// Clock and reset.
.cclk (cclk),
.crst_l (crst_l),
.clk (clk),
.rst_l (rst_l),
.tx_en_local_m1 (tx_en_local_m1),
.arst_l (arst_l)
);
// SCT1 Outbound Request Queues.
jbi_sct_out_queues sct1_out_queues (
// Outbound Requests and Return Data.
.scbuf_jbi_data (scbuf1_jbi_data),
.scbuf_jbi_ctag_vld (scbuf1_jbi_ctag_vld),
.scbuf_jbi_ue_err (scbuf1_jbi_ue_err),
// JBI Outbound Interface.
.sctrdq_trans_count (sct1rdq_trans_count),
.sctrdq_data1_4 (sct1rdq_data1_4),
.sctrdq_install_state (sct1rdq_install_state),
.sctrdq_unmapped_error (sct1rdq_unmapped_error),
.sctrdq_jid (sct1rdq_jid),
.sctrdq_data (sct1rdq_data),
.sctrdq_ue_err (sct1rdq_ue_err),
.sctrdq_dec_count (sct1rdq_dec_count),
.sctrdq_dequeue (sct1rdq_dequeue),
// Memory In (jbi_min).
.mout_scb_jbus_wr_ack (mout_scb1_jbus_wr_ack),
// Misc.
.testmux_sel (testmux_sel),
.hold (hold),
.rst_tri_en (rst_tri_en),
// Clock and reset.
.cclk (cclk),
.crst_l (crst_l),
.clk (clk),
.rst_l (rst_l),
.tx_en_local_m1 (tx_en_local_m1),
.arst_l (arst_l)
);
// SCT2 Outbound Request Queues.
jbi_sct_out_queues sct2_out_queues (
// Outbound Requests and Return Data.
.scbuf_jbi_data (scbuf2_jbi_data),
.scbuf_jbi_ctag_vld (scbuf2_jbi_ctag_vld),
.scbuf_jbi_ue_err (scbuf2_jbi_ue_err),
// JBI Outbound Interface.
.sctrdq_trans_count (sct2rdq_trans_count),
.sctrdq_data1_4 (sct2rdq_data1_4),
.sctrdq_install_state (sct2rdq_install_state),
.sctrdq_unmapped_error (sct2rdq_unmapped_error),
.sctrdq_jid (sct2rdq_jid),
.sctrdq_data (sct2rdq_data),
.sctrdq_ue_err (sct2rdq_ue_err),
.sctrdq_dec_count (sct2rdq_dec_count),
.sctrdq_dequeue (sct2rdq_dequeue),
// Memory In (jbi_min).
.mout_scb_jbus_wr_ack (mout_scb2_jbus_wr_ack),
// Misc.
.testmux_sel (testmux_sel),
.hold (hold),
.rst_tri_en (rst_tri_en),
// Clock and reset.
.cclk (cclk),
.crst_l (crst_l),
.clk (clk),
.rst_l (rst_l),
.tx_en_local_m1 (tx_en_local_m1),
.arst_l (arst_l)
);
// SCT3 Outbound Request Queues.
jbi_sct_out_queues sct3_out_queues (
// Outbound Requests and Return Data.
.scbuf_jbi_data (scbuf3_jbi_data),
.scbuf_jbi_ctag_vld (scbuf3_jbi_ctag_vld),
.scbuf_jbi_ue_err (scbuf3_jbi_ue_err),
// JBI Outbound Interface.
.sctrdq_trans_count (sct3rdq_trans_count),
.sctrdq_data1_4 (sct3rdq_data1_4),
.sctrdq_install_state (sct3rdq_install_state),
.sctrdq_unmapped_error (sct3rdq_unmapped_error),
.sctrdq_jid (sct3rdq_jid),
.sctrdq_data (sct3rdq_data),
.sctrdq_ue_err (sct3rdq_ue_err),
.sctrdq_dec_count (sct3rdq_dec_count),
.sctrdq_dequeue (sct3rdq_dequeue),
// Memory In (jbi_min).
.mout_scb_jbus_wr_ack (mout_scb3_jbus_wr_ack),
// Misc.
.testmux_sel (testmux_sel),
.hold (hold),
.rst_tri_en (rst_tri_en),
// Clock and reset.
.cclk (cclk),
.crst_l (crst_l),
.clk (clk),
.rst_l (rst_l),
.tx_en_local_m1 (tx_en_local_m1),
.arst_l (arst_l)
);
// YID to JID Translator.
jbi_jid_to_yid jid_to_yid (
// Translation, port 0.
.trans_jid0 (min_trans_jid[3:0]),
.trans_yid0 (mout_trans_yid),
.trans_valid0 (mout_trans_valid),
// Translation, port 1.
.trans_jid1 (nack_error_id[3:0]),
.trans_yid1 ({ignored[1:0], mout_nack_thr_id[5:0], mout_nack_buf_id[1:0]}),
.trans_valid1 (),
// Allocating an assignment.
.alloc_stall (),
.alloc (alloc),
.alloc_yid (ncio_yid),
.alloc_jid (unused_jid),
// Freeing an assignment, port 0.
.free0 (min_free),
.free_jid0 (min_free_jid),
// Freeing an assignment, port 1.
.free1 (ncio_mout_nack_pop),
.free_jid1 (nack_error_id[3:0]),
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
// Internal Arbiter.
jbi_int_arb int_arb (
// SCT0 RDQ.
.sct0rdq_data1_4 (sct0rdq_data1_4),
.sct0rdq_trans_count (sct0rdq_trans_count),
.sct0rdq_dec_count (sct0rdq_dec_count),
.sct0rdq_ue_err (sct0rdq_ue_err),
.sct0rdq_unmapped_error (sct0rdq_unmapped_error),
// SCT1 RDQ.
.sct1rdq_data1_4 (sct1rdq_data1_4),
.sct1rdq_trans_count (sct1rdq_trans_count),
.sct1rdq_dec_count (sct1rdq_dec_count),
.sct1rdq_ue_err (sct1rdq_ue_err),
.sct1rdq_unmapped_error (sct1rdq_unmapped_error),
// SCT2 RDQ.
.sct2rdq_data1_4 (sct2rdq_data1_4),
.sct2rdq_trans_count (sct2rdq_trans_count),
.sct2rdq_dec_count (sct2rdq_dec_count),
.sct2rdq_ue_err (sct2rdq_ue_err),
.sct2rdq_unmapped_error (sct2rdq_unmapped_error),
// SCT3 RDQ.
.sct3rdq_data1_4 (sct3rdq_data1_4),
.sct3rdq_trans_count (sct3rdq_trans_count),
.sct3rdq_dec_count (sct3rdq_dec_count),
.sct3rdq_ue_err (sct3rdq_ue_err),
.sct3rdq_unmapped_error (sct3rdq_unmapped_error),
// PIO RQQ.
.piorqq_req (ncio_pio_req),
.piorqq_req_rw (ncio_pio_req_rw),
.piorqq_req_dest (ncio_pio_req_dest),
.piorqq_req_adv (mout_pio_req_adv),
// PIO ACKQ.
.pioackq_req (ncio_mondo_req),
.pioackq_ack_nack (ncio_mondo_ack),
.pioackq_req_adv (),
// DEBUG ACKQ.
.dbg_req_transparent (dbg_req_transparent),
.dbg_req_arbitrate (dbg_req_arbitrate),
.dbg_req_priority (dbg_req_priority),
.dbg_req_adv (),
// JBus Arbiter.
.int_req (int_req),
// Arb Timeout support.
.have_trans_waiting (have_trans_waiting),
// JBus Packet Controller.
.int_requestors (int_requestors),
.int_req_type (int_req_type),
.int_granted (int_granted),
.parked_on_us (parked_on_us),
// Flow Control.
.ok_send_address_pkt (ok_send_address_pkt),
.ok_send_data_pkt_to_4 (ok_send_data_pkt_to_4),
.ok_send_data_pkt_to_5 (ok_send_data_pkt_to_5),
// CSRs and errors.
.jbi_log_arb_myreq (jbi_log_arb_myreq),
.jbi_log_arb_reqtype (jbi_log_arb_reqtype),
.csr_jbi_debug_arb_aggr_arb (csr_jbi_debug_arb_aggr_arb),
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
// JBus Arbiter.
jbi_jbus_arb jbus_arb (
// Configuration.
.csr_jbi_config_arb_mode (csr_jbi_config_arb_mode),
// Internal requests.
.int_req (int_req),
.multiple_in_progress (multiple_in_progress),
.multiple_ok (multiple_ok),
.parked_on_us (parked_on_us),
// External requests.
.io_jbi_j_req4_in_l (io_jbi_j_req4_in_l),
.io_jbi_j_req5_in_l (io_jbi_j_req5_in_l),
.jbi_io_j_req0_out_l (jbi_io_j_req0_out_l),
.jbi_io_j_req0_out_en (jbi_io_j_req0_out_en),
// Grant.
.stream_break_point (stream_break_point),
.grant (grant),
// CSRs and errors.
.mout_csr_err_arb_to (mout_csr_err_arb_to),
.csr_jbi_arb_timeout_timeval(csr_jbi_arb_timeout_timeval),
.have_trans_waiting (have_trans_waiting),
.piorqq_req (ncio_pio_req),
.int_requestor_piorqq (int_requestors[LRQ_PIORQQ_BIT]),
.jbi_log_arb_jreq (jbi_log_arb_jreq),
.mout_min_jbus_owner (mout_min_jbus_owner),
// I/O buffer enable for J_ADTYPE[], J_AD[], J_ADP[].
.jbi_io_j_adtype_en (jbi_io_j_adtype_en),
.jbi_io_j_ad_en (jbi_io_j_ad_en),
.jbi_io_j_adp_en (jbi_io_j_adp_en),
.mout_dsbl_sampling (mout_dsbl_sampling),
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
// JBus Packet Controller.
jbi_pktout_ctlr pktout_ctlr (
// JBus Arbiter.
.grant (grant),
.multiple_in_progress (multiple_in_progress),
.stream_break_point (stream_break_point),
// Internal Arbiter.
.multiple_ok (multiple_ok),
.int_req_type (int_req_type),
.int_requestors (int_requestors),
.int_granted (int_granted),
// Flow Control.
.ok_send_address_pkt (ok_send_address_pkt),
.ok_send_data_pkt_to_4 (ok_send_data_pkt_to_4),
.ok_send_data_pkt_to_5 (ok_send_data_pkt_to_5),
// Queues.
.sct0rdq_dequeue (sct0rdq_dequeue),
.sct1rdq_dequeue (sct1rdq_dequeue),
.sct2rdq_dequeue (sct2rdq_dequeue),
.sct3rdq_dequeue (sct3rdq_dequeue),
.piorqq_dequeue (mout_pio_pop),
.pioackq_dequeue (mout_mondo_pop),
.dbg_dequeue (mout_dbg_pop),
// Status bits.
.mout_scb0_jbus_rd_ack (mout_scb0_jbus_rd_ack),
.mout_scb1_jbus_rd_ack (mout_scb1_jbus_rd_ack),
.mout_scb2_jbus_rd_ack (mout_scb2_jbus_rd_ack),
.mout_scb3_jbus_rd_ack (mout_scb3_jbus_rd_ack),
.jbus_out_addr_cycle (jbus_out_addr_cycle),
.jbus_out_data_cycle (jbus_out_data_cycle),
// JID to PIO ID map.
.alloc (alloc),
// J_ADTYPE, J_AD, J_ADP busses.
.sel_j_adbus (sel_j_adbus),
.sel_queue (sel_queue),
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
// JBus Packet Assembler and Driver.
jbi_pktout_asm pktout_asm (
// Outbound Packet Controller.
.sel_j_adbus (sel_j_adbus),
.sel_queue (sel_queue),
// Queues.
// SCT0 RDQ.
.sct0rdq_install_state (sct0rdq_install_state),
.sct0rdq_unmapped_error (sct0rdq_unmapped_error),
.sct0rdq_jid (sct0rdq_jid),
.sct0rdq_data (sct0rdq_data),
.sct0rdq_ue_err (sct0rdq_ue_err),
// SCT1 RDQ.
.sct1rdq_install_state (sct1rdq_install_state),
.sct1rdq_unmapped_error (sct1rdq_unmapped_error),
.sct1rdq_jid (sct1rdq_jid),
.sct1rdq_data (sct1rdq_data),
.sct1rdq_ue_err (sct1rdq_ue_err),
// SCT2 RDQ.
.sct2rdq_install_state (sct2rdq_install_state),
.sct2rdq_unmapped_error (sct2rdq_unmapped_error),
.sct2rdq_jid (sct2rdq_jid),
.sct2rdq_data (sct2rdq_data),
.sct2rdq_ue_err (sct2rdq_ue_err),
// SCT3 RDQ.
.sct3rdq_install_state (sct3rdq_install_state),
.sct3rdq_unmapped_error (sct3rdq_unmapped_error),
.sct3rdq_jid (sct3rdq_jid),
.sct3rdq_data (sct3rdq_data),
.sct3rdq_ue_err (sct3rdq_ue_err),
// PIO RQQ.
.ncio_pio_ue (ncio_pio_ue),
.ncio_pio_be (ncio_pio_be),
.ncio_pio_ad (ncio_pio_ad),
// PIO ACKQ.
.ncio_mondo_agnt_id (ncio_mondo_agnt_id),
.ncio_mondo_cpu_id (ncio_mondo_cpu_id),
// DBGQ.
.dbg_data (dbg_data),
// YID-to-JID Translation.
.unused_jid ({ 2'b00, unused_jid }),
// J_ADTYPE, J_AD, J_ADP busses.
.jbi_io_j_adtype (jbi_io_j_adtype),
.jbi_io_j_ad (jbi_io_j_ad),
.jbi_io_j_adp (jbi_io_j_adp),
// Error injection.
.inj_err_j_ad (inj_err_j_ad),
// Debug Info.
.csr_jbi_debug_info_enb (csr_jbi_debug_info_enb), // Put these data fields in high half of JBus Address Cycles.
.thread_id (ncio_yid[`JBI_YID_THR_HI-1:`JBI_YID_THR_LO]),
.sct0rdq_trans_count (sct0rdq_trans_count[3:0]),
.sct1rdq_trans_count (sct1rdq_trans_count[3:0]),
.sct2rdq_trans_count (sct2rdq_trans_count[3:0]),
.sct3rdq_trans_count (sct3rdq_trans_count[3:0]),
.ncio_prqq_level (ncio_prqq_level[4:0]),
.ncio_makq_level (ncio_makq_level[4:0]),
// Clock.
.clk (clk)
);
// AOK/DOK Flow Control Tracking.
jbi_aok_dok_tracking aok_dok_tracking (
// J_PACK signals.
.j_pack0_m1 (jbi_io_j_pack0),
.j_pack1_m1 (jbi_io_j_pack1),
.j_pack4_p1 (io_jbi_j_pack4),
.j_pack5_p1 (io_jbi_j_pack5),
// Flow control signals.
.ok_send_data_pkt_to_4 (ok_send_data_pkt_to_4),
.ok_send_data_pkt_to_5 (ok_send_data_pkt_to_5),
.ok_send_address_pkt (ok_send_address_pkt),
// CSR Interface.
.jbi_log_arb_aok (jbi_log_arb_aok),
.jbi_log_arb_dok (jbi_log_arb_dok),
.mout_csr_err_fatal (mout_csr_err_fatal),
// Performance Counter events.
.mout_perf_aok_off (mout_perf_aok_off),
.mout_perf_dok_off (mout_perf_dok_off),
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
// Outbound Snoop Response Generator.
jbi_j_pack_out_gen j_pack_out_gen (
// COHACK response requests.
.min_snp_launch (min_snp_launch),
// Flow Control.
.send_aok_off (min_aok_off),
.send_aok_on (min_aok_on),
.send_dok_off (1'b0),
.send_dok_on (1'b0),
// Fatal error control.
.dok_fatal_req_csr (csr_dok_on),
.dok_fatal_req_sctag ({ sctag0_jbi_por_req_buf, sctag1_jbi_por_req_buf, sctag2_jbi_por_req_buf, sctag3_jbi_por_req_buf }),
.csr_jbi_error_config_fe_enb(csr_jbi_error_config_fe_enb),
// JPack out.
.jbi_io_j_pack0 (jbi_io_j_pack0),
.jbi_io_j_pack0_en (jbi_io_j_pack0_en),
.jbi_io_j_pack1 (jbi_io_j_pack1),
.jbi_io_j_pack1_en (jbi_io_j_pack1_en),
// Clock and reset.
.clk (clk),
.rst_l (rst_l),
.cclk (cclk),
.crst_l (crst_l),
.tx_en_local_m1 (tx_en_local_m1)
);
// CSR interface for errors and logging.
jbi_mout_csr mout_csr (
// Port Present detection.
.mout_port_4_present (mout_port_4_present),
.mout_port_5_present (mout_port_5_present),
// Transaction Timeout error detection.
.alloc (alloc),
.unused_jid (unused_jid),
.min_free (min_free),
.min_free_jid (min_free_jid),
.trans_timeout_timeval (csr_jbi_trans_timeout_timeval),
.mout_csr_err_read_to (mout_csr_err_read_to),
.mout_nack (mout_nack),
.nack_error_id (nack_error_id),
.ncio_mout_nack_pop (ncio_mout_nack_pop),
.csr_jbi_log_enb_read_to (csr_jbi_log_enb_read_to),
// J_PAR Error detection.
.j_par (io_jbi_j_par),
.j_req4_in_l_p1 (io_jbi_j_req4_in_l),
.j_req5_in_l_p1 (io_jbi_j_req5_in_l),
.j_req0_out_l_m1 (jbi_io_j_req0_out_l),
.j_pack0_m1 (jbi_io_j_pack0),
.j_pack1_m1 (jbi_io_j_pack1),
.j_pack4_p1 (io_jbi_j_pack4),
.j_pack5_p1 (io_jbi_j_pack5),
.mout_csr_err_cpar (mout_csr_err_cpar),
.mout_csr_jbi_log_par_jpar (mout_csr_jbi_log_par_jpar),
.mout_csr_jbi_log_par_jpack0(mout_csr_jbi_log_par_jpack0),
.mout_csr_jbi_log_par_jpack1(mout_csr_jbi_log_par_jpack1),
.mout_csr_jbi_log_par_jpack4(mout_csr_jbi_log_par_jpack4),
.mout_csr_jbi_log_par_jpack5(mout_csr_jbi_log_par_jpack5),
.mout_csr_jbi_log_par_jreq (mout_csr_jbi_log_par_jreq),
// JBus Error Injection control from JBI_ERR_INJECT.
.min_mout_inject_err (min_mout_inject_err),
.jbi_err_inject_xormask (csr_jbi_err_inject_xormask),
.jbi_err_inject_errtype (csr_jbi_err_inject_errtype),
.jbus_out_addr_cycle (jbus_out_addr_cycle),
.jbus_out_data_cycle (jbus_out_data_cycle),
.inj_err_j_ad (inj_err_j_ad),
.mout_min_inject_err_done (mout_min_inject_err_done),
.mout_csr_inject_output_done(mout_csr_inject_output_done),
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
endmodule
// Local Variables:
// verilog-library-directories:("." "../../include" "../../../include" "../../rtl")
// verilog-module-parents:("jbi")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCIN_SYMBOL_V
`define SKY130_FD_SC_LP__FAHCIN_SYMBOL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fahcin (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCIN_SYMBOL_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
wire reset_sync;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire unxcomplemented_resetxx0;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (reset),
.dout (reset_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
break_on_reset <= 1'b0;
resetrequest <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
break_on_reset <= jdo[19] ? 1
: jdo[18] ? 0
: break_on_reset;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset_sync)
begin
jtag_break <= break_on_reset;
resetlatch <= 1;
end
else if (debugreq & ~debugack & break_on_reset)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input [ 7: 0] address;
input [ 3: 0] byteenable;
input clock;
input [ 31: 0] data;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clock),
.data_a (data),
.q_a (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_ocimem (
// inputs:
address,
byteenable,
clk,
debugaccess,
jdo,
jrst_n,
read,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
ociram_readdata,
waitrequest
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] ociram_readdata;
output waitrequest;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input read;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 8: 0] MonARegAddrInc;
wire MonARegAddrIncAccessingRAM;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon_ram_wr;
wire [ 31: 0] cfgrom_readdata;
reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 7: 0] ociram_addr;
wire [ 3: 0] ociram_byteenable;
wire [ 31: 0] ociram_readdata;
wire [ 31: 0] ociram_wr_data;
wire ociram_wr_en;
reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
jtag_rd <= 1'b0;
jtag_rd_d1 <= 1'b0;
jtag_ram_wr <= 1'b0;
jtag_ram_rd <= 1'b0;
jtag_ram_rd_d1 <= 1'b0;
jtag_ram_access <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
jtag_rd <= 1'b1;
jtag_ram_rd <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
jtag_rd <= 1'b1;
jtag_ram_rd <= ~jdo[17];
jtag_ram_access <= ~jdo[17];
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
MonDReg <= jdo[34 : 3];
jtag_ram_wr <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else
begin
jtag_rd <= 0;
jtag_ram_wr <= 0;
jtag_ram_rd <= 0;
jtag_ram_access <= 0;
if (jtag_rd_d1)
MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata;
end
jtag_rd_d1 <= jtag_rd;
jtag_ram_rd_d1 <= jtag_ram_rd;
if (~waitrequest)
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else if (write)
waitrequest <= ~address[8] & jtag_ram_access;
else if (read)
begin
avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access);
waitrequest <= ~avalon_ociram_readdata_ready;
end
else
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
end
end
assign MonARegAddrInc = MonAReg[10 : 2]+1;
assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8];
assign avalon_ram_wr = write & ~address[8] & debugaccess;
assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0];
assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata;
assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable;
assign ociram_wr_en = jtag_ram_wr | avalon_ram_wr;
//NIOS_SYSTEMV3_NIOS_CPU_ociram_sp_ram, which is an nios_sp_ram
NIOS_SYSTEMV3_NIOS_CPU_ociram_sp_ram_module NIOS_SYSTEMV3_NIOS_CPU_ociram_sp_ram
(
.address (ociram_addr),
.byteenable (ociram_byteenable),
.clock (clk),
.data (ociram_wr_data),
.q (ociram_readdata),
.wren (ociram_wr_en)
);
//synthesis translate_off
`ifdef NO_PLI
defparam NIOS_SYSTEMV3_NIOS_CPU_ociram_sp_ram.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_ociram_default_contents.dat";
`else
defparam NIOS_SYSTEMV3_NIOS_CPU_ociram_sp_ram.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_ociram_default_contents.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam NIOS_SYSTEMV3_NIOS_CPU_ociram_sp_ram.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_ociram_default_contents.mif";
//synthesis read_comments_as_HDL off
assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00200020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001616 :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000000 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h00200000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000000000001;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000000001);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
reset_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 19: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 21: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 21: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 21: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 21: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
trc_enb,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
dct_buffer,
dct_count,
itm,
trc_ctrl,
trc_on
)
;
output [ 29: 0] dct_buffer;
output [ 3: 0] dct_count;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input trc_enb;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire curr_pid;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] excaddr;
wire instr_retired;
wire is_advanced_exception;
wire is_cond_dct;
wire is_dct;
wire is_exception_no_break;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
wire sync_pending;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign is_advanced_exception = 1'b0;
assign is_exception_no_break = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign curr_pid = 1'b0;
assign excaddr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_pending = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_pending;
assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= ~trc_enb &
take_action_tracectrl & jdo[4];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exctype <= 1'b0;
pending_excaddr <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else if (trc_clear || (!0 && !0))
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exctype <= 1'b0;
pending_excaddr <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else
begin
if (!prev_pid_valid)
begin
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if (instr_retired | is_advanced_exception)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception_no_break)
begin
pending_frametype <= 4'b0010;
pending_excaddr <= excaddr;
if (is_fast_tlb_miss_exception)
pending_exctype <= 1'b1;
else
pending_exctype <= 1'b0;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else if (!is_dct & snapped_pid)
begin
pending_frametype <= 4'b0011;
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= 0;
end
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) &
(~record_itrace |
is_exception_no_break |
is_idct |
record_dct_outcome_in_sync |
(!is_dct & snapped_pid)))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~is_advanced_exception)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & (pending_frametype == 4'b0010))
itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype};
else if (record_itrace & (
(pending_frametype == 4'b1000) |
(pending_frametype == 4'b1010) |
(pending_frametype == 4'b1001)))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
if (0 &
((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) &
!snapped_pid & prev_pid_valid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
end
end
else if (record_itrace &
0 & (pending_frametype == 4'b0011))
itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid};
else if (record_itrace & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= {4'b0000, 32'b0};
end
end
else
itm <= {4'b0000, 32'b0};
end
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
if (0)
trc_ctrl_reg[7 : 5] <= jdo[12 : 10];
if (0 & 0)
trc_ctrl_reg[8] <= jdo[13];
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 21: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_trc_ctrl_td_mode, which is an e_instance
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_td_mode NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else if (0)
begin
if (cpu_d_write & ~cpu_d_wait & record_store_addr)
atm <= {4'b0101, cpu_d_address_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_addr)
atm <= {4'b0100, cpu_d_address_0_padded};
else
atm <= {4'b0000, cpu_d_address_0_padded};
if (cpu_d_write & ~cpu_d_wait & record_store_data)
dtm <= {4'b0111, cpu_d_writedata_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_data)
dtm <= {4'b0110, cpu_d_readdata_0_padded};
else
dtm <= {4'b0000, cpu_d_readdata_0_padded};
end
else
begin
atm <= 0;
dtm <= 0;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
)
;
output [ 1: 0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_tm_count;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_tm_count = 0;
end // 3'b000
3'b001: begin
compute_tm_count = 1;
end // 3'b001
3'b010: begin
compute_tm_count = 1;
end // 3'b010
3'b011: begin
compute_tm_count = 2;
end // 3'b011
3'b100: begin
compute_tm_count = 1;
end // 3'b100
3'b101: begin
compute_tm_count = 2;
end // 3'b101
3'b110: begin
compute_tm_count = 2;
end // 3'b110
3'b111: begin
compute_tm_count = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
)
;
output [ 3: 0] fifowp_inc;
input free2;
input free3;
input [ 1: 0] tm_count;
reg [ 3: 0] fifowp_inc;
always @(free2 or free3 or tm_count)
begin
if (free3 & (tm_count == 3))
fifowp_inc = 3;
else if (free2 & (tm_count >= 2))
fifowp_inc = 2;
else if (tm_count >= 1)
fifowp_inc = 1;
else
fifowp_inc = 0;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
)
;
output [ 4: 0] fifocount_inc;
input empty;
input free2;
input free3;
input [ 1: 0] tm_count;
reg [ 4: 0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)
begin
if (empty)
fifocount_inc = tm_count[1 : 0];
else if (free3 & (tm_count == 3))
fifocount_inc = 2;
else if (free2 & (tm_count >= 2))
fifocount_inc = 1;
else if (tm_count >= 1)
fifocount_inc = 0;
else
fifocount_inc = {5{1'b1}};
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dct_buffer,
dct_count,
dtm,
itm,
jrst_n,
reset_n,
test_ending,
test_has_ended,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input test_ending;
input test_has_ended;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_tm_count_tm_count;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
wire [ 35: 0] fifo_read_mux;
reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifocount_inc_fifocount;
wire [ 35: 0] fifohead;
reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifowp1;
wire [ 3: 0] fifowp2;
wire [ 3: 0] fifowp_inc_fifowp;
wire free2;
wire free3;
wire itm_valid;
reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] ovr_pending_atm;
wire [ 35: 0] ovr_pending_dtm;
wire [ 1: 0] tm_count;
wire tm_count_ge1;
wire tm_count_ge2;
wire tm_count_ge3;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign free2 = ~fifocount[4];
assign free3 = ~fifocount[4] & ~&fifocount[3 : 0];
assign empty = ~|fifocount;
assign fifowp1 = fifowp + 1;
assign fifowp2 = fifowp + 2;
//NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_compute_tm_count_tm_count, which is an e_instance
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_compute_tm_count NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_compute_tm_count_tm_count
(
.atm_valid (atm_valid),
.compute_tm_count (compute_tm_count_tm_count),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign tm_count = compute_tm_count_tm_count;
//NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifowp_inc_fifowp, which is an e_instance
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifowp_inc NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifowp_inc_fifowp
(
.fifowp_inc (fifowp_inc_fifowp),
.free2 (free2),
.free3 (free3),
.tm_count (tm_count)
);
//NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifocount_inc_fifocount, which is an e_instance
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifocount_inc NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifocount_inc_fifocount
(
.empty (empty),
.fifocount_inc (fifocount_inc_fifocount),
.free2 (free2),
.free3 (free3),
.tm_count (tm_count)
);
//the_NIOS_SYSTEMV3_NIOS_CPU_oci_test_bench, which is an e_instance
NIOS_SYSTEMV3_NIOS_CPU_oci_test_bench the_NIOS_SYSTEMV3_NIOS_CPU_oci_test_bench
(
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.test_ending (test_ending),
.test_has_ended (test_has_ended)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fiforp <= 0;
fifowp <= 0;
fifocount <= 0;
ovf_pending <= 1;
end
else
begin
fifowp <= fifowp + fifowp_inc_fifowp;
fifocount <= fifocount + fifocount_inc_fifocount;
if (~empty)
fiforp <= fiforp + 1;
if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count)))
ovf_pending <= 1;
else if (atm_valid | dtm_valid)
ovf_pending <= 0;
end
end
assign fifohead = fifo_read_mux;
assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm;
assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm :
(((fifowp == 4'd0) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm :
(((fifowp == 4'd1) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm :
(((fifowp == 4'd2) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm :
(((fifowp == 4'd3) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm :
(((fifowp == 4'd4) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm :
(((fifowp == 4'd5) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm :
(((fifowp == 4'd6) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm :
(((fifowp == 4'd7) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm :
(((fifowp == 4'd8) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm :
(((fifowp == 4'd9) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm :
(((fifowp == 4'd10) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm :
(((fifowp == 4'd11) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm :
(((fifowp == 4'd12) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm :
(((fifowp == 4'd13) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm :
(((fifowp == 4'd14) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm :
(((fifowp == 4'd15) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign tm_count_ge1 = |tm_count;
assign tm_count_ge2 = tm_count[1];
assign tm_count_ge3 = &tm_count;
assign ovr_pending_atm = {ovf_pending, atm[34 : 0]};
assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]};
assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 :
(fiforp == 4'd1)? fifo_1 :
(fiforp == 4'd2)? fifo_2 :
(fiforp == 4'd3)? fifo_3 :
(fiforp == 4'd4)? fifo_4 :
(fiforp == 4'd5)? fifo_5 :
(fiforp == 4'd6)? fifo_6 :
(fiforp == 4'd7)? fifo_7 :
(fiforp == 4'd8)? fifo_8 :
(fiforp == 4'd9)? fifo_9 :
(fiforp == 4'd10)? fifo_10 :
(fiforp == 4'd11)? fifo_11 :
(fiforp == 4'd12)? fifo_12 :
(fiforp == 4'd13)? fifo_13 :
(fiforp == 4'd14)? fifo_14 :
fifo_15;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
)
;
output tr_clk;
output [ 17: 0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [ 35: 0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 17: 0] tr_data;
reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
assign phase = x1^x2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
x1 <= 0;
else
x1 <= ~x1;
end
always @(posedge clkx2 or negedge jrst_n)
begin
if (jrst_n == 0)
begin
x2 <= 0;
tr_clk_reg <= 0;
tr_data_reg <= 0;
end
else
begin
x2 <= x1;
tr_clk_reg <= ~phase;
tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18];
end
end
assign tr_clk = 0 ? tr_clk_reg : 0;
assign tr_data = 0 ? tr_data_reg : 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output trc_enb;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_tracectrl;
input take_action_tracemem_a;
input take_action_tracemem_b;
input take_no_action_tracemem_a;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire trc_enb;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (!0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (take_action_tracectrl &&
(jdo[4] | jdo[3]))
begin
if (jdo[4])
trc_im_addr <= 0;
if (jdo[3])
trc_wrap <= 0;
end
else if (trc_enb & trc_on_chip & tw_valid)
begin
trc_im_addr <= trc_im_addr+1;
if (&trc_im_addr)
trc_wrap <= 1;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trc_jtag_addr <= 0;
else if (take_action_tracemem_a ||
take_no_action_tracemem_a ||
take_action_tracemem_b)
trc_jtag_addr <= take_action_tracemem_a ?
jdo[35 : 19] :
trc_jtag_addr + 1;
end
assign trc_enb = trc_ctrl[0];
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_tw = trc_wrap;
assign tracemem_on = trc_enb;
assign tracemem_trcdata = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_performance_monitors
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address_nxt,
av_ld_data_aligned_filtered,
byteenable_nxt,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess_nxt,
hbreak_enabled,
read_nxt,
reset,
reset_n,
test_ending,
test_has_ended,
write_nxt,
writedata_nxt,
// outputs:
jtag_debug_module_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest,
waitrequest
)
;
output jtag_debug_module_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
output waitrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 19: 0] F_pc;
input [ 8: 0] address_nxt;
input [ 31: 0] av_ld_data_aligned_filtered;
input [ 3: 0] byteenable_nxt;
input clk;
input [ 21: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess_nxt;
input hbreak_enabled;
input read_nxt;
input reset;
input reset_n;
input test_ending;
input test_has_ended;
input write_nxt;
input [ 31: 0] writedata_nxt;
wire [ 31: 0] MonDReg;
reg [ 8: 0] address;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
reg [ 3: 0] byteenable;
wire clkx2;
wire [ 21: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire [ 29: 0] dct_buffer;
wire [ 3: 0] dct_count;
reg debugaccess;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire jtag_debug_module_debugaccess_to_roms;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire [ 31: 0] ociram_readdata;
wire ocireg_ers;
wire ocireg_mrs;
reg read;
reg [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire tr_clk;
wire [ 17: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire trc_enb;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire waitrequest;
reg write;
reg [ 31: 0] writedata;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_debug the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_ocimem the_NIOS_SYSTEMV3_NIOS_CPU_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.byteenable (byteenable),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.ociram_readdata (ociram_readdata),
.read (read),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_avalon_reg the_NIOS_SYSTEMV3_NIOS_CPU_nios2_avalon_reg
(
.address (address),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_break the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_xbrk the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_dbrk the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_itrace the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_dtrace the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifo the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.trc_on (trc_on),
.tw (tw)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_pib the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_pib
(
.clk (clk),
.clkx2 (clkx2),
.jrst_n (jrst_n),
.tr_clk (tr_clk),
.tr_data (tr_data),
.tw (tw)
);
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_im the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci_im
(
.clk (clk),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign jtag_debug_module_debugaccess_to_roms = debugack;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
address <= 0;
else
address <= address_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
byteenable <= 0;
else
byteenable <= byteenable_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
writedata <= 0;
else
writedata <= writedata_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
debugaccess <= 0;
else
debugaccess <= debugaccess_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
read <= 0;
else
read <= read ? waitrequest : read_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
write <= 0;
else
write <= write ? waitrequest : write_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
readdata <= 0;
else
readdata <= address[8] ? oci_reg_readdata : ociram_readdata;
end
NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_wrapper the_NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_clk |
tr_data |
trigout |
debugack;
assign debugreq = 0;
assign clkx2 = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU (
// inputs:
clk,
d_irq,
d_readdata,
d_waitrequest,
i_readdata,
i_waitrequest,
jtag_debug_module_address,
jtag_debug_module_byteenable,
jtag_debug_module_debugaccess,
jtag_debug_module_read,
jtag_debug_module_write,
jtag_debug_module_writedata,
reset_n,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
i_address,
i_read,
jtag_debug_module_debugaccess_to_roms,
jtag_debug_module_readdata,
jtag_debug_module_resetrequest,
jtag_debug_module_waitrequest,
no_ci_readra
)
;
output [ 21: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output [ 21: 0] i_address;
output i_read;
output jtag_debug_module_debugaccess_to_roms;
output [ 31: 0] jtag_debug_module_readdata;
output jtag_debug_module_resetrequest;
output jtag_debug_module_waitrequest;
output no_ci_readra;
input clk;
input [ 31: 0] d_irq;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 8: 0] jtag_debug_module_address;
input [ 3: 0] jtag_debug_module_byteenable;
input jtag_debug_module_debugaccess;
input jtag_debug_module_read;
input jtag_debug_module_write;
input [ 31: 0] jtag_debug_module_writedata;
input reset_n;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_logic;
wire D_ctrl_rdctl_inst;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_st;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 2: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 4: 0] D_iw_shift_imm5;
wire [ 4: 0] D_iw_trap_break_imm5;
wire [ 19: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 55: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 21: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
reg E_valid;
wire [ 55: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 2: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire [ 4: 0] F_av_iw_shift_imm5;
wire [ 4: 0] F_av_iw_trap_break_imm5;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 2: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire [ 4: 0] F_iw_shift_imm5;
wire [ 4: 0] F_iw_trap_break_imm5;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_opx;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_rsv02;
wire F_op_rsv09;
wire F_op_rsv10;
wire F_op_rsv17;
wire F_op_rsv18;
wire F_op_rsv25;
wire F_op_rsv26;
wire F_op_rsv33;
wire F_op_rsv34;
wire F_op_rsv41;
wire F_op_rsv42;
wire F_op_rsv49;
wire F_op_rsv57;
wire F_op_rsv61;
wire F_op_rsv62;
wire F_op_rsv63;
wire F_op_rsvx00;
wire F_op_rsvx10;
wire F_op_rsvx15;
wire F_op_rsvx17;
wire F_op_rsvx21;
wire F_op_rsvx25;
wire F_op_rsvx33;
wire F_op_rsvx34;
wire F_op_rsvx35;
wire F_op_rsvx42;
wire F_op_rsvx43;
wire F_op_rsvx44;
wire F_op_rsvx47;
wire F_op_rsvx50;
wire F_op_rsvx51;
wire F_op_rsvx55;
wire F_op_rsvx56;
wire F_op_rsvx60;
wire F_op_rsvx63;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 19: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 19: 0] F_pc_no_crst_nxt;
wire [ 19: 0] F_pc_nxt;
wire [ 19: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 21: 0] F_pcb;
wire [ 21: 0] F_pcb_nxt;
wire [ 21: 0] F_pcb_plus_four;
wire F_valid;
wire [ 55: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_rdctl_inst;
wire R_ctrl_rdctl_inst_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_st;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
reg R_valid;
wire [ 55: 0] R_vinst;
reg R_wr_dst_reg;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 21: 0] W_mem_baddr;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 55: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 21: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
wire d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 21: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire jtag_debug_module_clk;
wire jtag_debug_module_debugaccess_to_roms;
wire [ 31: 0] jtag_debug_module_readdata;
wire jtag_debug_module_reset;
wire jtag_debug_module_resetrequest;
wire jtag_debug_module_waitrequest;
wire no_ci_readra;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_ending;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_NIOS_SYSTEMV3_NIOS_CPU_test_bench, which is an e_instance
NIOS_SYSTEMV3_NIOS_CPU_test_bench the_NIOS_SYSTEMV3_NIOS_CPU_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.d_write_nxt (d_write_nxt),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_shift_imm5 = F_av_iw[10 : 6];
assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[8 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_shift_imm5 = F_iw[10 : 6];
assign F_iw_trap_break_imm5 = F_iw[10 : 6];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[8 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_shift_imm5 = D_iw[10 : 6];
assign D_iw_trap_break_imm5 = D_iw[10 : 6];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[8 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_rsv02 = F_iw_op == 2;
assign F_op_rsv09 = F_iw_op == 9;
assign F_op_rsv10 = F_iw_op == 10;
assign F_op_rsv17 = F_iw_op == 17;
assign F_op_rsv18 = F_iw_op == 18;
assign F_op_rsv25 = F_iw_op == 25;
assign F_op_rsv26 = F_iw_op == 26;
assign F_op_rsv33 = F_iw_op == 33;
assign F_op_rsv34 = F_iw_op == 34;
assign F_op_rsv41 = F_iw_op == 41;
assign F_op_rsv42 = F_iw_op == 42;
assign F_op_rsv49 = F_iw_op == 49;
assign F_op_rsv57 = F_iw_op == 57;
assign F_op_rsv61 = F_iw_op == 61;
assign F_op_rsv62 = F_iw_op == 62;
assign F_op_rsv63 = F_iw_op == 63;
assign F_op_eret = F_op_opx & (F_iw_opx == 1);
assign F_op_roli = F_op_opx & (F_iw_opx == 2);
assign F_op_rol = F_op_opx & (F_iw_opx == 3);
assign F_op_flushp = F_op_opx & (F_iw_opx == 4);
assign F_op_ret = F_op_opx & (F_iw_opx == 5);
assign F_op_nor = F_op_opx & (F_iw_opx == 6);
assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7);
assign F_op_cmpge = F_op_opx & (F_iw_opx == 8);
assign F_op_bret = F_op_opx & (F_iw_opx == 9);
assign F_op_ror = F_op_opx & (F_iw_opx == 11);
assign F_op_flushi = F_op_opx & (F_iw_opx == 12);
assign F_op_jmp = F_op_opx & (F_iw_opx == 13);
assign F_op_and = F_op_opx & (F_iw_opx == 14);
assign F_op_cmplt = F_op_opx & (F_iw_opx == 16);
assign F_op_slli = F_op_opx & (F_iw_opx == 18);
assign F_op_sll = F_op_opx & (F_iw_opx == 19);
assign F_op_wrprs = F_op_opx & (F_iw_opx == 20);
assign F_op_or = F_op_opx & (F_iw_opx == 22);
assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23);
assign F_op_cmpne = F_op_opx & (F_iw_opx == 24);
assign F_op_srli = F_op_opx & (F_iw_opx == 26);
assign F_op_srl = F_op_opx & (F_iw_opx == 27);
assign F_op_nextpc = F_op_opx & (F_iw_opx == 28);
assign F_op_callr = F_op_opx & (F_iw_opx == 29);
assign F_op_xor = F_op_opx & (F_iw_opx == 30);
assign F_op_mulxss = F_op_opx & (F_iw_opx == 31);
assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32);
assign F_op_divu = F_op_opx & (F_iw_opx == 36);
assign F_op_div = F_op_opx & (F_iw_opx == 37);
assign F_op_rdctl = F_op_opx & (F_iw_opx == 38);
assign F_op_mul = F_op_opx & (F_iw_opx == 39);
assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40);
assign F_op_initi = F_op_opx & (F_iw_opx == 41);
assign F_op_trap = F_op_opx & (F_iw_opx == 45);
assign F_op_wrctl = F_op_opx & (F_iw_opx == 46);
assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48);
assign F_op_add = F_op_opx & (F_iw_opx == 49);
assign F_op_break = F_op_opx & (F_iw_opx == 52);
assign F_op_hbreak = F_op_opx & (F_iw_opx == 53);
assign F_op_sync = F_op_opx & (F_iw_opx == 54);
assign F_op_sub = F_op_opx & (F_iw_opx == 57);
assign F_op_srai = F_op_opx & (F_iw_opx == 58);
assign F_op_sra = F_op_opx & (F_iw_opx == 59);
assign F_op_intr = F_op_opx & (F_iw_opx == 61);
assign F_op_crst = F_op_opx & (F_iw_opx == 62);
assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0);
assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10);
assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15);
assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17);
assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21);
assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25);
assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33);
assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34);
assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35);
assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42);
assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43);
assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44);
assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47);
assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50);
assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51);
assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55);
assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56);
assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60);
assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63);
assign F_op_opx = F_iw_op == 58;
assign F_op_custom = F_iw_op == 50;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign no_ci_readra = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000000001;
assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 524296 :
(F_pc_sel_nxt == 2'b01)? 526856 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[21 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 524288;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw;
assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_jmp_direct_target_waddr = D_iw[31 : 6];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//NIOS_SYSTEMV3_NIOS_CPU_register_bank_a, which is an nios_sdp_ram
NIOS_SYSTEMV3_NIOS_CPU_register_bank_a_module NIOS_SYSTEMV3_NIOS_CPU_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a),
.rdaddress (D_iw_a),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam NIOS_SYSTEMV3_NIOS_CPU_register_bank_a.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_rf_ram_a.dat";
`else
defparam NIOS_SYSTEMV3_NIOS_CPU_register_bank_a.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_rf_ram_a.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam NIOS_SYSTEMV3_NIOS_CPU_register_bank_a.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_rf_ram_a.mif";
//synthesis read_comments_as_HDL off
//NIOS_SYSTEMV3_NIOS_CPU_register_bank_b, which is an nios_sdp_ram
NIOS_SYSTEMV3_NIOS_CPU_register_bank_b_module NIOS_SYSTEMV3_NIOS_CPU_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b),
.rdaddress (D_iw_b),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam NIOS_SYSTEMV3_NIOS_CPU_register_bank_b.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_rf_ram_b.dat";
`else
defparam NIOS_SYSTEMV3_NIOS_CPU_register_bank_b.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_rf_ram_b.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam NIOS_SYSTEMV3_NIOS_CPU_register_bank_b.lpm_file = "NIOS_SYSTEMV3_NIOS_CPU_rf_ram_b.mif";
//synthesis read_comments_as_HDL off
assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid <= 0;
else
E_valid <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall;
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[21 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg :
(D_iw_control_regnum == 3'd1)? W_estatus_reg :
(D_iw_control_regnum == 3'd2)? W_bstatus_reg :
(D_iw_control_regnum == 3'd3)? W_ienable_reg :
(D_iw_control_regnum == 3'd4)? W_ipending_reg :
0;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_stb_data = R_rf_b[7 : 0];
assign R_sth_data = R_rf_b[15 : 0];
assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_mem16)? {R_sth_data, R_sth_data} :
R_rf_b;
assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :
d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rdctl_inst ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br & W_cmp_result;
assign W_mem_baddr = W_alu_result[21 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000000001;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000000001;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
NIOS_SYSTEMV3_NIOS_CPU_nios2_oci the_NIOS_SYSTEMV3_NIOS_CPU_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address_nxt (jtag_debug_module_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.byteenable_nxt (jtag_debug_module_byteenable),
.clk (jtag_debug_module_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debugaccess_nxt (jtag_debug_module_debugaccess),
.hbreak_enabled (hbreak_enabled),
.jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.read_nxt (jtag_debug_module_read),
.readdata (jtag_debug_module_readdata),
.reset (jtag_debug_module_reset),
.reset_n (reset_n),
.resetrequest (jtag_debug_module_resetrequest),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.waitrequest (jtag_debug_module_waitrequest),
.write_nxt (jtag_debug_module_write),
.writedata_nxt (jtag_debug_module_writedata)
);
//jtag_debug_module, which is an e_avalon_slave
assign jtag_debug_module_clk = clk;
assign jtag_debug_module_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = D_op_crst|D_op_rsvx63;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|
D_op_jmpi|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_rsvx50|
D_op_sll|
D_op_rsvx51|
D_op_roli|
D_op_rsvx34|
D_op_rol|
D_op_rsvx35|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_br_uncond = D_op_br|D_op_rsv02;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_rsvx25|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_rsvx00|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq|
D_op_rsvx56;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st = D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_rdctl_inst = D_op_rdctl;
assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rdctl_inst <= 0;
else if (R_en)
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42|
D_op_beq|
D_op_rsv34|
D_op_bne|
D_op_rsv62|
D_op_br|
D_op_rsv02;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {7{8'h2d}};
assign D_vinst = D_valid ? D_inst : {7{8'h2d}};
assign R_vinst = R_valid ? D_inst : {7{8'h2d}};
assign E_vinst = E_valid ? D_inst : {7{8'h2d}};
assign W_vinst = W_valid ? D_inst : {7{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.6 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_ac.v,v $
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No user `defines in this module
module ent_ac
//
// Generated Module inst_ac
//
(
port_ac_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
wire port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:01:56 04/23/2017
// Design Name: decrypt
// Module Name: C:/Users/vkoro/Final_Project/project/des/DES/decrypt_tb.v
// Project Name: DES
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: decrypt
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module decrypt_tb;
// Inputs
reg [63:0] message;
reg [63:0] DESkey;
reg clk;
reg reset;
reg enable;
reg ack;
integer clk_cnt;
parameter CLK_PERIOD = 10;
// Outputs
wire [63:0] decrypted;
wire done;
// Instantiate the Unit Under Test (UUT)
decrypt_dumb uut (
.message(message),
.DESkey(DESkey),
.decrypted(decrypted),
.done(done),
.clk(clk),
.reset(reset),
.enable(enable),
.ack(ack)
);
initial
begin : CLK_GENERATOR
clk = 0;
forever
begin
#(CLK_PERIOD/2) clk = ~clk;
end
end
initial
begin : RESET_GENERATOR
reset = 1;
#(10 * CLK_PERIOD) reset = 0;
end
initial
begin : CLK_COUNTER
clk_cnt = 0;
forever
begin
#(CLK_PERIOD) clk_cnt = clk_cnt + 1;
end
end
initial begin
// Initialize Inputs
message = 0;
DESkey = 0;
enable = 0;
ack = 0;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
message = 64'b1110000010100110111110111111100010010010011001011010011101100101;
DESkey = 64'h133457799BBCDFF1;
enable = 1;
wait(done);
ack = 1;
# 100;
DESkey = 64'h133457799BBCDFF0;
wait(done);
ack = 1;
# 100;
DESkey = 64'hab01986231bc8d01;
//ack = 1;
# 10;
end
endmodule
|
/* -----------------------------------------------------------------------
*
* Copyright 2004,2007 Tommy Thorn - All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, Inc., 53 Temple Place Ste 330,
* Bostom MA 02111-1307, USA; either version 2 of the License, or
* (at your option) any later version; incorporated herein by reference.
*
* -----------------------------------------------------------------------
*
*
* Block ram controller
*/
`timescale 1ns/10ps
`include "pipeconnect.h"
module blockram
(input wire clock
,input wire rst
,output mem_waitrequest
,input [1:0] mem_id
,input [29:0] mem_address
,input mem_read
,input mem_write
,input [31:0] mem_writedata
,input [3:0] mem_writedatamask
,output [31:0] mem_readdata
,output reg [1:0] mem_readdataid = 0
);
parameter burst_bits = 2;
parameter size = 18; // 4 * 2^18 = 1 MiB
parameter INIT_FILE = "";
parameter burst_length = 1 << burst_bits;
wire sel = mem_address[29:26] == 'h4;
reg [burst_bits:0] cnt = ~0;
reg [size-1:0] read_address = 0;
assign mem_waitrequest = !cnt[burst_bits];
dpram memory(.clock(clock),
.address_a(mem_waitrequest
? read_address
: mem_address[size-1:0]),
.byteena_a(mem_writedatamask),
.wrdata_a(mem_writedata),
.wren_a(!mem_waitrequest & sel & mem_write),
.rddata_a(mem_readdata),
.address_b(0),
.byteena_b(0),
.wrdata_b(0),
.wren_b(0),
.rddata_b());
defparam
memory.DATA_WIDTH = 32,
memory.ADDR_WIDTH = size,
memory.INIT_FILE = INIT_FILE;
always @(posedge clock)
if (mem_waitrequest) begin
cnt <= cnt - 1;
read_address <= read_address + 1;
end else begin
mem_readdataid <= 0;
if (sel & mem_read) begin
read_address <= mem_address[size-1:0] + 1;
mem_readdataid <= mem_id;
cnt <= burst_length - 2;
end
end
`define DEBUG_BLOCKRAM 1
`ifdef DEBUG_BLOCKRAM
always @(posedge clock) begin
if (!mem_waitrequest & sel & mem_read)
$display("%05d blockram[%x] -> ? for %d", $time,
{mem_address,2'd0}, mem_id);
if (!mem_waitrequest & sel & mem_write)
$display("%05d blockram[%x] <- %8x/%x", $time,
{mem_address,2'd0}, mem_writedata, mem_writedatamask);
if (mem_readdataid)
$display("%05d blockram[%x] -> %8x for %d", $time,
32'h3fff_fffc + (read_address << 2), mem_readdata, mem_readdataid);
end
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUF_1_V
`define SKY130_FD_SC_LP__BUF_1_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUF_1_V
|
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