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//
// Designed by Qiang Wu
//
`timescale 1ns/1ps
module flow_classification
(// --- data path interface
output [63:0] out_data0,
output [23:0] out_pkt_route0,
output out_wr0,
output reg out_req0,
input out_ack0,
output out_bypass0,
output [63:0] out_data1,
output [23:0] out_pkt_route1,
output out_wr1,
output reg out_req1,
input out_ack1,
output out_bypass1,
input [63:0] in_data,
input [7:0] in_ctrl,
input in_wr,
output in_rdy,
// --- Register interface
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [1:0] reg_src_out,
// --- Misc
input clk,
input reset
);
assign reg_req_out = reg_req_in;
assign reg_ack_out = reg_ack_in;
assign reg_rd_wr_L_out = reg_rd_wr_L_in;
assign reg_addr_out = reg_addr_in;
assign reg_data_out = reg_data_in;
assign reg_src_out = reg_src_in;
reg [63:0] out_data[1:0];
reg [23:0] out_pkt_route[1:0];
reg [1:0] out_wr;
reg [1:0] out_req;
reg [1:0] out_ack;
reg [1:0] out_bypass;
assign out_data0 = out_data[0];
assign out_data1 = out_data[1];
assign out_pkt_route0 = out_pkt_route[0];
assign out_pkt_route1 = out_pkt_route[1];
assign out_wr0 = out_wr[0];
assign out_wr1 = out_wr[1];
assign out_bypass0 = out_bypass[0];
assign out_bypass1 = out_bypass[1];
reg in_rdy_reg;
assign in_rdy = in_rdy_reg;
reg wr_curr;
reg wr_prev;
wire eop;
assign eop = ((wr_curr == 0) && (wr_prev != 0)) ? 1 : 0;
reg [2:0] state;
reg [2:0] state_next;
parameter FC_IDLE = 3'b001,
FC_LOOKUP_ROUTE = 3'b010,
FC_REQ = 3'b011,
FC_ACK = 3'b100,
FC_TX = 3'b101,
FC_CANCEL_REQ = 3'b110,
FC_WAIT_ACK = 3'b111;
reg [1:0] pkt_count;
wire [1:0] pkt_count_plus_1;
assign pkt_count_plus_1 = (pkt_count == 2'b00) ? 0 : pkt_count + 1;
reg curr_output;
//assign curr_output = pkt_count[1];
always @(*) begin
out_req = 0;
in_rdy_reg = 0;
state_next = state;
case(state)
FC_IDLE: begin
// curr_output = 0;
out_req = 0;
in_rdy_reg = 0;
state_next = FC_LOOKUP_ROUTE;
end
FC_LOOKUP_ROUTE: begin
curr_output = pkt_count[1];
if(pkt_count[0] == 1'b1) begin
out_pkt_route[curr_output] = 24'b000_000_000_000_000_000_111_011;
out_bypass[curr_output] = 0;
end else begin
out_pkt_route[curr_output] = 24'b000_000_000_000_000_000_011_111;
out_bypass[curr_output] = 1;
end
state_next = FC_REQ;
end
FC_REQ: begin
out_req[curr_output] = 1;
state_next = FC_ACK;
end
FC_ACK: begin
out_req[curr_output] = 1;
if(out_ack[curr_output]) begin
state_next = FC_TX;
end
end
FC_TX: begin
out_req[curr_output] = 1;
in_rdy_reg = 1;
if(eop) begin
in_rdy_reg = 0;
state_next = FC_CANCEL_REQ;
end
end
FC_CANCEL_REQ: begin
in_rdy_reg = 0;
out_req[curr_output] = 0;
state_next = FC_WAIT_ACK;
end
FC_WAIT_ACK: begin
if(!out_ack[curr_output]) begin
state_next = FC_IDLE;
end
end
default: begin
state_next = FC_IDLE;
end
endcase
end
always @(posedge clk) begin
if(reset) begin
state <= 0;
pkt_count <= 0;
end else begin
state <= state_next;
out_req0 <= out_req[0];
out_req1 <= out_req[1];
out_ack[0] <= out_ack0;
out_ack[1] <= out_ack1;
out_data[curr_output] <= in_data;
out_wr[curr_output] <= in_wr;
wr_prev <= wr_curr;
wr_curr <= in_wr;
if(state == FC_IDLE) begin
pkt_count <= pkt_count_plus_1;
end
end
end
wire [35:0] CONTROL0;
wire [239:0] TRIG0;
/*
chipscope_icon_v1_03_a cs_icon (
.CONTROL0(CONTROL0)
);
chipscope_ila_v1_02_a cs_ila (
.CONTROL(CONTROL0),
.CLK(clk),
.TRIG0(TRIG0)
);
assign TRIG0[63:0] = in_data;
assign TRIG0[71:64] = in_ctrl;
assign TRIG0[80] = in_wr;
assign TRIG0[81] = in_rdy;
assign TRIG0[89:82] = out_data1[7:0];
assign TRIG0[98:90] = out_pkt_route1[8:0];
assign TRIG0[163:100] = out_data0;
assign TRIG0[179:164] = out_pkt_route0;
assign TRIG0[180] = out_wr0;
assign TRIG0[181] = out_req0;
assign TRIG0[182] = out_ack0;
assign TRIG0[183] = out_bypass0;
assign TRIG0[184] = out_wr1;
assign TRIG0[185] = out_req1;
assign TRIG0[186] = out_ack1;
assign TRIG0[187] = out_bypass1;
assign TRIG0[202:200] = state;
assign TRIG0[205:203] = state_next;
assign TRIG0[206] = eop;
*/
endmodule
|
`timescale 1ns/1ps
//THIS MODULE IS INSTANTIATED PER TX QUAD
module tx_reset_sm
(
input refclkdiv2,
input rst_n,
input tx_pll_lol_qd_s,
output reg tx_pcs_rst_ch_c, //TX Lane Reset (modified to have one bit)
output reg rst_qd_c // QUAD Reset
);
parameter count_index = 17;
// States of LSM
localparam QUAD_RESET = 0,
WAIT_FOR_TIMER1 = 1,
CHECK_PLOL = 2,
WAIT_FOR_TIMER2 = 3,
NORMAL = 4;
localparam STATEWIDTH =3;
// Flop variables
reg [STATEWIDTH-1:0] cs /*synthesis syn_encoding="safe, gray"*/; // current state of lsm
// Combinational logic variables
reg [STATEWIDTH-1:0] ns; // next state of lsm
reg tx_pll_lol_qd_s_int;
reg tx_pll_lol_qd_s_int1;
reg [3:0] tx_pcs_rst_ch_c_int; //TX Lane Reset
reg rst_qd_c_int; // QUAD Reset
//SEQUENTIAL
always @(posedge refclkdiv2 or negedge rst_n)
begin
if (rst_n == 1'b0)
begin
cs <= QUAD_RESET;
tx_pll_lol_qd_s_int <= 1;
tx_pll_lol_qd_s_int1 <= 1;
tx_pcs_rst_ch_c <= 1'b1;
rst_qd_c <= 1;
end
else
begin
cs <= ns;
tx_pll_lol_qd_s_int1 <= tx_pll_lol_qd_s;
tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s_int1;
tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int[0];
rst_qd_c <= rst_qd_c_int;
end
end
//
reg reset_timer1, reset_timer2;
//TIMER1 = 20ns;
//Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
// A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
localparam TIMER1WIDTH=3;
reg [TIMER1WIDTH-1:0] counter1;
reg TIMER1;
always @(posedge refclkdiv2 or posedge reset_timer1)
begin
if (reset_timer1)
begin
counter1 <= 0;
TIMER1 <= 0;
end
else
begin
if (counter1[2] == 1)
TIMER1 <=1;
else
begin
TIMER1 <=0;
counter1 <= counter1 + 1 ;
end
end
end
//TIMER2 = 1,400,000 UI;
//WORST CASE CYCLES is with smallest multipier factor.
// This would be with X8 clock multiplier in DIV2 mode
// IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES
// SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
// An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
//localparam TIMER2WIDTH=19;
//1,400,000 * 400 ps / 20 ns = 28000
// so a 16 bit counter is enough
localparam TIMER2WIDTH=18;
reg [TIMER2WIDTH-1:0] counter2;
reg TIMER2;
always @(posedge refclkdiv2 or posedge reset_timer2)
begin
if (reset_timer2)
begin
counter2 <= 0;
TIMER2 <= 0;
end
else
begin
// `ifdef SIM //IF SIM parameter is set, define lower value
// //TO SAVE SIMULATION TIME
// if (counter2[4] == 1)
// `else
// if (counter2[18] == 1)
// `endif
if (counter2[count_index] == 1)
TIMER2 <=1;
else
begin
TIMER2 <=0;
counter2 <= counter2 + 1 ;
end
end
end
always @(*)
begin : NEXT_STATE
reset_timer1 = 0;
reset_timer2 = 0;
case (cs)
QUAD_RESET: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 1;
reset_timer1 = 1;
ns = WAIT_FOR_TIMER1;
end
WAIT_FOR_TIMER1: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 1;
if (TIMER1)
ns = CHECK_PLOL;
else
ns = WAIT_FOR_TIMER1;
end
CHECK_PLOL: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 0;
reset_timer2 = 1;
ns = WAIT_FOR_TIMER2;
end
WAIT_FOR_TIMER2: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 0;
if (TIMER2)
if (tx_pll_lol_qd_s_int)
ns = QUAD_RESET;
else
ns = NORMAL;
else
ns = WAIT_FOR_TIMER2;
end
NORMAL: begin
tx_pcs_rst_ch_c_int = 4'h0;
rst_qd_c_int = 0;
if (tx_pll_lol_qd_s_int)
ns = QUAD_RESET;
else
ns = NORMAL;
end
// prevent lockup in undefined state
default: begin
tx_pcs_rst_ch_c_int = 4'hF;
rst_qd_c_int = 1;
ns = QUAD_RESET;
end
endcase // case
end //NEXT_STATE
endmodule
|
// system_acl_iface_acl_kernel_interface_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.05.04.18:11:58
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface_mm_interconnect_1 (
input wire clk_reset_clk_clk, // clk_reset_clk.clk
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cntrl_reset_reset_bridge_in_reset_reset, // kernel_cntrl_reset_reset_bridge_in_reset.reset
input wire sw_reset_clk_reset_reset_bridge_in_reset_reset, // sw_reset_clk_reset_reset_bridge_in_reset.reset
input wire [13:0] kernel_cntrl_m0_address, // kernel_cntrl_m0.address
output wire kernel_cntrl_m0_waitrequest, // .waitrequest
input wire [0:0] kernel_cntrl_m0_burstcount, // .burstcount
input wire [3:0] kernel_cntrl_m0_byteenable, // .byteenable
input wire kernel_cntrl_m0_read, // .read
output wire [31:0] kernel_cntrl_m0_readdata, // .readdata
output wire kernel_cntrl_m0_readdatavalid, // .readdatavalid
input wire kernel_cntrl_m0_write, // .write
input wire [31:0] kernel_cntrl_m0_writedata, // .writedata
input wire kernel_cntrl_m0_debugaccess, // .debugaccess
output wire address_span_extender_0_cntl_write, // address_span_extender_0_cntl.write
output wire address_span_extender_0_cntl_read, // .read
input wire [63:0] address_span_extender_0_cntl_readdata, // .readdata
output wire [63:0] address_span_extender_0_cntl_writedata, // .writedata
output wire [7:0] address_span_extender_0_cntl_byteenable, // .byteenable
output wire [9:0] address_span_extender_0_windowed_slave_address, // address_span_extender_0_windowed_slave.address
output wire address_span_extender_0_windowed_slave_write, // .write
output wire address_span_extender_0_windowed_slave_read, // .read
input wire [31:0] address_span_extender_0_windowed_slave_readdata, // .readdata
output wire [31:0] address_span_extender_0_windowed_slave_writedata, // .writedata
output wire [0:0] address_span_extender_0_windowed_slave_burstcount, // .burstcount
output wire [3:0] address_span_extender_0_windowed_slave_byteenable, // .byteenable
input wire address_span_extender_0_windowed_slave_readdatavalid, // .readdatavalid
input wire address_span_extender_0_windowed_slave_waitrequest, // .waitrequest
output wire irq_ena_0_s_write, // irq_ena_0_s.write
output wire irq_ena_0_s_read, // .read
input wire [31:0] irq_ena_0_s_readdata, // .readdata
output wire [31:0] irq_ena_0_s_writedata, // .writedata
output wire [3:0] irq_ena_0_s_byteenable, // .byteenable
input wire irq_ena_0_s_waitrequest, // .waitrequest
output wire mem_org_mode_s_write, // mem_org_mode_s.write
output wire mem_org_mode_s_read, // .read
input wire [31:0] mem_org_mode_s_readdata, // .readdata
output wire [31:0] mem_org_mode_s_writedata, // .writedata
input wire mem_org_mode_s_waitrequest, // .waitrequest
output wire sw_reset_s_write, // sw_reset_s.write
output wire sw_reset_s_read, // .read
input wire [63:0] sw_reset_s_readdata, // .readdata
output wire [63:0] sw_reset_s_writedata, // .writedata
output wire [7:0] sw_reset_s_byteenable, // .byteenable
input wire sw_reset_s_waitrequest, // .waitrequest
output wire [8:0] sys_description_rom_s1_address, // sys_description_rom_s1.address
output wire sys_description_rom_s1_write, // .write
input wire [63:0] sys_description_rom_s1_readdata, // .readdata
output wire [63:0] sys_description_rom_s1_writedata, // .writedata
output wire [7:0] sys_description_rom_s1_byteenable, // .byteenable
output wire sys_description_rom_s1_chipselect, // .chipselect
output wire sys_description_rom_s1_clken, // .clken
output wire sys_description_rom_s1_debugaccess, // .debugaccess
output wire version_id_0_s_read, // version_id_0_s.read
input wire [31:0] version_id_0_s_readdata // .readdata
);
wire kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest; // kernel_cntrl_m0_agent:av_waitrequest -> kernel_cntrl_m0_translator:uav_waitrequest
wire [2:0] kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount; // kernel_cntrl_m0_translator:uav_burstcount -> kernel_cntrl_m0_agent:av_burstcount
wire [31:0] kernel_cntrl_m0_translator_avalon_universal_master_0_writedata; // kernel_cntrl_m0_translator:uav_writedata -> kernel_cntrl_m0_agent:av_writedata
wire [13:0] kernel_cntrl_m0_translator_avalon_universal_master_0_address; // kernel_cntrl_m0_translator:uav_address -> kernel_cntrl_m0_agent:av_address
wire kernel_cntrl_m0_translator_avalon_universal_master_0_lock; // kernel_cntrl_m0_translator:uav_lock -> kernel_cntrl_m0_agent:av_lock
wire kernel_cntrl_m0_translator_avalon_universal_master_0_write; // kernel_cntrl_m0_translator:uav_write -> kernel_cntrl_m0_agent:av_write
wire kernel_cntrl_m0_translator_avalon_universal_master_0_read; // kernel_cntrl_m0_translator:uav_read -> kernel_cntrl_m0_agent:av_read
wire [31:0] kernel_cntrl_m0_translator_avalon_universal_master_0_readdata; // kernel_cntrl_m0_agent:av_readdata -> kernel_cntrl_m0_translator:uav_readdata
wire kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess; // kernel_cntrl_m0_translator:uav_debugaccess -> kernel_cntrl_m0_agent:av_debugaccess
wire [3:0] kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable; // kernel_cntrl_m0_translator:uav_byteenable -> kernel_cntrl_m0_agent:av_byteenable
wire kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid; // kernel_cntrl_m0_agent:av_readdatavalid -> kernel_cntrl_m0_translator:uav_readdatavalid
wire address_span_extender_0_windowed_slave_agent_m0_waitrequest; // address_span_extender_0_windowed_slave_translator:uav_waitrequest -> address_span_extender_0_windowed_slave_agent:m0_waitrequest
wire [2:0] address_span_extender_0_windowed_slave_agent_m0_burstcount; // address_span_extender_0_windowed_slave_agent:m0_burstcount -> address_span_extender_0_windowed_slave_translator:uav_burstcount
wire [31:0] address_span_extender_0_windowed_slave_agent_m0_writedata; // address_span_extender_0_windowed_slave_agent:m0_writedata -> address_span_extender_0_windowed_slave_translator:uav_writedata
wire [13:0] address_span_extender_0_windowed_slave_agent_m0_address; // address_span_extender_0_windowed_slave_agent:m0_address -> address_span_extender_0_windowed_slave_translator:uav_address
wire address_span_extender_0_windowed_slave_agent_m0_write; // address_span_extender_0_windowed_slave_agent:m0_write -> address_span_extender_0_windowed_slave_translator:uav_write
wire address_span_extender_0_windowed_slave_agent_m0_lock; // address_span_extender_0_windowed_slave_agent:m0_lock -> address_span_extender_0_windowed_slave_translator:uav_lock
wire address_span_extender_0_windowed_slave_agent_m0_read; // address_span_extender_0_windowed_slave_agent:m0_read -> address_span_extender_0_windowed_slave_translator:uav_read
wire [31:0] address_span_extender_0_windowed_slave_agent_m0_readdata; // address_span_extender_0_windowed_slave_translator:uav_readdata -> address_span_extender_0_windowed_slave_agent:m0_readdata
wire address_span_extender_0_windowed_slave_agent_m0_readdatavalid; // address_span_extender_0_windowed_slave_translator:uav_readdatavalid -> address_span_extender_0_windowed_slave_agent:m0_readdatavalid
wire address_span_extender_0_windowed_slave_agent_m0_debugaccess; // address_span_extender_0_windowed_slave_agent:m0_debugaccess -> address_span_extender_0_windowed_slave_translator:uav_debugaccess
wire [3:0] address_span_extender_0_windowed_slave_agent_m0_byteenable; // address_span_extender_0_windowed_slave_agent:m0_byteenable -> address_span_extender_0_windowed_slave_translator:uav_byteenable
wire address_span_extender_0_windowed_slave_agent_rf_source_endofpacket; // address_span_extender_0_windowed_slave_agent:rf_source_endofpacket -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_endofpacket
wire address_span_extender_0_windowed_slave_agent_rf_source_valid; // address_span_extender_0_windowed_slave_agent:rf_source_valid -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_valid
wire address_span_extender_0_windowed_slave_agent_rf_source_startofpacket; // address_span_extender_0_windowed_slave_agent:rf_source_startofpacket -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_startofpacket
wire [89:0] address_span_extender_0_windowed_slave_agent_rf_source_data; // address_span_extender_0_windowed_slave_agent:rf_source_data -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_data
wire address_span_extender_0_windowed_slave_agent_rf_source_ready; // address_span_extender_0_windowed_slave_agent_rsp_fifo:in_ready -> address_span_extender_0_windowed_slave_agent:rf_source_ready
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_endofpacket -> address_span_extender_0_windowed_slave_agent:rf_sink_endofpacket
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_valid -> address_span_extender_0_windowed_slave_agent:rf_sink_valid
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_startofpacket -> address_span_extender_0_windowed_slave_agent:rf_sink_startofpacket
wire [89:0] address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_data -> address_span_extender_0_windowed_slave_agent:rf_sink_data
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready; // address_span_extender_0_windowed_slave_agent:rf_sink_ready -> address_span_extender_0_windowed_slave_agent_rsp_fifo:out_ready
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid; // address_span_extender_0_windowed_slave_agent:rdata_fifo_src_valid -> address_span_extender_0_windowed_slave_agent_rdata_fifo:in_valid
wire [33:0] address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data; // address_span_extender_0_windowed_slave_agent:rdata_fifo_src_data -> address_span_extender_0_windowed_slave_agent_rdata_fifo:in_data
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready; // address_span_extender_0_windowed_slave_agent_rdata_fifo:in_ready -> address_span_extender_0_windowed_slave_agent:rdata_fifo_src_ready
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid; // address_span_extender_0_windowed_slave_agent_rdata_fifo:out_valid -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_valid
wire [33:0] address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data; // address_span_extender_0_windowed_slave_agent_rdata_fifo:out_data -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_data
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready; // address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_ready -> address_span_extender_0_windowed_slave_agent_rdata_fifo:out_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> address_span_extender_0_windowed_slave_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> address_span_extender_0_windowed_slave_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> address_span_extender_0_windowed_slave_agent:cp_startofpacket
wire [88:0] cmd_mux_src_data; // cmd_mux:src_data -> address_span_extender_0_windowed_slave_agent:cp_data
wire [6:0] cmd_mux_src_channel; // cmd_mux:src_channel -> address_span_extender_0_windowed_slave_agent:cp_channel
wire cmd_mux_src_ready; // address_span_extender_0_windowed_slave_agent:cp_ready -> cmd_mux:src_ready
wire address_span_extender_0_cntl_agent_m0_waitrequest; // address_span_extender_0_cntl_translator:uav_waitrequest -> address_span_extender_0_cntl_agent:m0_waitrequest
wire [3:0] address_span_extender_0_cntl_agent_m0_burstcount; // address_span_extender_0_cntl_agent:m0_burstcount -> address_span_extender_0_cntl_translator:uav_burstcount
wire [63:0] address_span_extender_0_cntl_agent_m0_writedata; // address_span_extender_0_cntl_agent:m0_writedata -> address_span_extender_0_cntl_translator:uav_writedata
wire [13:0] address_span_extender_0_cntl_agent_m0_address; // address_span_extender_0_cntl_agent:m0_address -> address_span_extender_0_cntl_translator:uav_address
wire address_span_extender_0_cntl_agent_m0_write; // address_span_extender_0_cntl_agent:m0_write -> address_span_extender_0_cntl_translator:uav_write
wire address_span_extender_0_cntl_agent_m0_lock; // address_span_extender_0_cntl_agent:m0_lock -> address_span_extender_0_cntl_translator:uav_lock
wire address_span_extender_0_cntl_agent_m0_read; // address_span_extender_0_cntl_agent:m0_read -> address_span_extender_0_cntl_translator:uav_read
wire [63:0] address_span_extender_0_cntl_agent_m0_readdata; // address_span_extender_0_cntl_translator:uav_readdata -> address_span_extender_0_cntl_agent:m0_readdata
wire address_span_extender_0_cntl_agent_m0_readdatavalid; // address_span_extender_0_cntl_translator:uav_readdatavalid -> address_span_extender_0_cntl_agent:m0_readdatavalid
wire address_span_extender_0_cntl_agent_m0_debugaccess; // address_span_extender_0_cntl_agent:m0_debugaccess -> address_span_extender_0_cntl_translator:uav_debugaccess
wire [7:0] address_span_extender_0_cntl_agent_m0_byteenable; // address_span_extender_0_cntl_agent:m0_byteenable -> address_span_extender_0_cntl_translator:uav_byteenable
wire address_span_extender_0_cntl_agent_rf_source_endofpacket; // address_span_extender_0_cntl_agent:rf_source_endofpacket -> address_span_extender_0_cntl_agent_rsp_fifo:in_endofpacket
wire address_span_extender_0_cntl_agent_rf_source_valid; // address_span_extender_0_cntl_agent:rf_source_valid -> address_span_extender_0_cntl_agent_rsp_fifo:in_valid
wire address_span_extender_0_cntl_agent_rf_source_startofpacket; // address_span_extender_0_cntl_agent:rf_source_startofpacket -> address_span_extender_0_cntl_agent_rsp_fifo:in_startofpacket
wire [125:0] address_span_extender_0_cntl_agent_rf_source_data; // address_span_extender_0_cntl_agent:rf_source_data -> address_span_extender_0_cntl_agent_rsp_fifo:in_data
wire address_span_extender_0_cntl_agent_rf_source_ready; // address_span_extender_0_cntl_agent_rsp_fifo:in_ready -> address_span_extender_0_cntl_agent:rf_source_ready
wire address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket; // address_span_extender_0_cntl_agent_rsp_fifo:out_endofpacket -> address_span_extender_0_cntl_agent:rf_sink_endofpacket
wire address_span_extender_0_cntl_agent_rsp_fifo_out_valid; // address_span_extender_0_cntl_agent_rsp_fifo:out_valid -> address_span_extender_0_cntl_agent:rf_sink_valid
wire address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket; // address_span_extender_0_cntl_agent_rsp_fifo:out_startofpacket -> address_span_extender_0_cntl_agent:rf_sink_startofpacket
wire [125:0] address_span_extender_0_cntl_agent_rsp_fifo_out_data; // address_span_extender_0_cntl_agent_rsp_fifo:out_data -> address_span_extender_0_cntl_agent:rf_sink_data
wire address_span_extender_0_cntl_agent_rsp_fifo_out_ready; // address_span_extender_0_cntl_agent:rf_sink_ready -> address_span_extender_0_cntl_agent_rsp_fifo:out_ready
wire address_span_extender_0_cntl_agent_rdata_fifo_src_valid; // address_span_extender_0_cntl_agent:rdata_fifo_src_valid -> address_span_extender_0_cntl_agent_rdata_fifo:in_valid
wire [65:0] address_span_extender_0_cntl_agent_rdata_fifo_src_data; // address_span_extender_0_cntl_agent:rdata_fifo_src_data -> address_span_extender_0_cntl_agent_rdata_fifo:in_data
wire address_span_extender_0_cntl_agent_rdata_fifo_src_ready; // address_span_extender_0_cntl_agent_rdata_fifo:in_ready -> address_span_extender_0_cntl_agent:rdata_fifo_src_ready
wire address_span_extender_0_cntl_agent_rdata_fifo_out_valid; // address_span_extender_0_cntl_agent_rdata_fifo:out_valid -> address_span_extender_0_cntl_agent:rdata_fifo_sink_valid
wire [65:0] address_span_extender_0_cntl_agent_rdata_fifo_out_data; // address_span_extender_0_cntl_agent_rdata_fifo:out_data -> address_span_extender_0_cntl_agent:rdata_fifo_sink_data
wire address_span_extender_0_cntl_agent_rdata_fifo_out_ready; // address_span_extender_0_cntl_agent:rdata_fifo_sink_ready -> address_span_extender_0_cntl_agent_rdata_fifo:out_ready
wire sys_description_rom_s1_agent_m0_waitrequest; // sys_description_rom_s1_translator:uav_waitrequest -> sys_description_rom_s1_agent:m0_waitrequest
wire [3:0] sys_description_rom_s1_agent_m0_burstcount; // sys_description_rom_s1_agent:m0_burstcount -> sys_description_rom_s1_translator:uav_burstcount
wire [63:0] sys_description_rom_s1_agent_m0_writedata; // sys_description_rom_s1_agent:m0_writedata -> sys_description_rom_s1_translator:uav_writedata
wire [13:0] sys_description_rom_s1_agent_m0_address; // sys_description_rom_s1_agent:m0_address -> sys_description_rom_s1_translator:uav_address
wire sys_description_rom_s1_agent_m0_write; // sys_description_rom_s1_agent:m0_write -> sys_description_rom_s1_translator:uav_write
wire sys_description_rom_s1_agent_m0_lock; // sys_description_rom_s1_agent:m0_lock -> sys_description_rom_s1_translator:uav_lock
wire sys_description_rom_s1_agent_m0_read; // sys_description_rom_s1_agent:m0_read -> sys_description_rom_s1_translator:uav_read
wire [63:0] sys_description_rom_s1_agent_m0_readdata; // sys_description_rom_s1_translator:uav_readdata -> sys_description_rom_s1_agent:m0_readdata
wire sys_description_rom_s1_agent_m0_readdatavalid; // sys_description_rom_s1_translator:uav_readdatavalid -> sys_description_rom_s1_agent:m0_readdatavalid
wire sys_description_rom_s1_agent_m0_debugaccess; // sys_description_rom_s1_agent:m0_debugaccess -> sys_description_rom_s1_translator:uav_debugaccess
wire [7:0] sys_description_rom_s1_agent_m0_byteenable; // sys_description_rom_s1_agent:m0_byteenable -> sys_description_rom_s1_translator:uav_byteenable
wire sys_description_rom_s1_agent_rf_source_endofpacket; // sys_description_rom_s1_agent:rf_source_endofpacket -> sys_description_rom_s1_agent_rsp_fifo:in_endofpacket
wire sys_description_rom_s1_agent_rf_source_valid; // sys_description_rom_s1_agent:rf_source_valid -> sys_description_rom_s1_agent_rsp_fifo:in_valid
wire sys_description_rom_s1_agent_rf_source_startofpacket; // sys_description_rom_s1_agent:rf_source_startofpacket -> sys_description_rom_s1_agent_rsp_fifo:in_startofpacket
wire [125:0] sys_description_rom_s1_agent_rf_source_data; // sys_description_rom_s1_agent:rf_source_data -> sys_description_rom_s1_agent_rsp_fifo:in_data
wire sys_description_rom_s1_agent_rf_source_ready; // sys_description_rom_s1_agent_rsp_fifo:in_ready -> sys_description_rom_s1_agent:rf_source_ready
wire sys_description_rom_s1_agent_rsp_fifo_out_endofpacket; // sys_description_rom_s1_agent_rsp_fifo:out_endofpacket -> sys_description_rom_s1_agent:rf_sink_endofpacket
wire sys_description_rom_s1_agent_rsp_fifo_out_valid; // sys_description_rom_s1_agent_rsp_fifo:out_valid -> sys_description_rom_s1_agent:rf_sink_valid
wire sys_description_rom_s1_agent_rsp_fifo_out_startofpacket; // sys_description_rom_s1_agent_rsp_fifo:out_startofpacket -> sys_description_rom_s1_agent:rf_sink_startofpacket
wire [125:0] sys_description_rom_s1_agent_rsp_fifo_out_data; // sys_description_rom_s1_agent_rsp_fifo:out_data -> sys_description_rom_s1_agent:rf_sink_data
wire sys_description_rom_s1_agent_rsp_fifo_out_ready; // sys_description_rom_s1_agent:rf_sink_ready -> sys_description_rom_s1_agent_rsp_fifo:out_ready
wire sys_description_rom_s1_agent_rdata_fifo_src_valid; // sys_description_rom_s1_agent:rdata_fifo_src_valid -> sys_description_rom_s1_agent:rdata_fifo_sink_valid
wire [65:0] sys_description_rom_s1_agent_rdata_fifo_src_data; // sys_description_rom_s1_agent:rdata_fifo_src_data -> sys_description_rom_s1_agent:rdata_fifo_sink_data
wire sys_description_rom_s1_agent_rdata_fifo_src_ready; // sys_description_rom_s1_agent:rdata_fifo_sink_ready -> sys_description_rom_s1_agent:rdata_fifo_src_ready
wire sw_reset_s_agent_m0_waitrequest; // sw_reset_s_translator:uav_waitrequest -> sw_reset_s_agent:m0_waitrequest
wire [3:0] sw_reset_s_agent_m0_burstcount; // sw_reset_s_agent:m0_burstcount -> sw_reset_s_translator:uav_burstcount
wire [63:0] sw_reset_s_agent_m0_writedata; // sw_reset_s_agent:m0_writedata -> sw_reset_s_translator:uav_writedata
wire [13:0] sw_reset_s_agent_m0_address; // sw_reset_s_agent:m0_address -> sw_reset_s_translator:uav_address
wire sw_reset_s_agent_m0_write; // sw_reset_s_agent:m0_write -> sw_reset_s_translator:uav_write
wire sw_reset_s_agent_m0_lock; // sw_reset_s_agent:m0_lock -> sw_reset_s_translator:uav_lock
wire sw_reset_s_agent_m0_read; // sw_reset_s_agent:m0_read -> sw_reset_s_translator:uav_read
wire [63:0] sw_reset_s_agent_m0_readdata; // sw_reset_s_translator:uav_readdata -> sw_reset_s_agent:m0_readdata
wire sw_reset_s_agent_m0_readdatavalid; // sw_reset_s_translator:uav_readdatavalid -> sw_reset_s_agent:m0_readdatavalid
wire sw_reset_s_agent_m0_debugaccess; // sw_reset_s_agent:m0_debugaccess -> sw_reset_s_translator:uav_debugaccess
wire [7:0] sw_reset_s_agent_m0_byteenable; // sw_reset_s_agent:m0_byteenable -> sw_reset_s_translator:uav_byteenable
wire sw_reset_s_agent_rf_source_endofpacket; // sw_reset_s_agent:rf_source_endofpacket -> sw_reset_s_agent_rsp_fifo:in_endofpacket
wire sw_reset_s_agent_rf_source_valid; // sw_reset_s_agent:rf_source_valid -> sw_reset_s_agent_rsp_fifo:in_valid
wire sw_reset_s_agent_rf_source_startofpacket; // sw_reset_s_agent:rf_source_startofpacket -> sw_reset_s_agent_rsp_fifo:in_startofpacket
wire [125:0] sw_reset_s_agent_rf_source_data; // sw_reset_s_agent:rf_source_data -> sw_reset_s_agent_rsp_fifo:in_data
wire sw_reset_s_agent_rf_source_ready; // sw_reset_s_agent_rsp_fifo:in_ready -> sw_reset_s_agent:rf_source_ready
wire sw_reset_s_agent_rsp_fifo_out_endofpacket; // sw_reset_s_agent_rsp_fifo:out_endofpacket -> sw_reset_s_agent:rf_sink_endofpacket
wire sw_reset_s_agent_rsp_fifo_out_valid; // sw_reset_s_agent_rsp_fifo:out_valid -> sw_reset_s_agent:rf_sink_valid
wire sw_reset_s_agent_rsp_fifo_out_startofpacket; // sw_reset_s_agent_rsp_fifo:out_startofpacket -> sw_reset_s_agent:rf_sink_startofpacket
wire [125:0] sw_reset_s_agent_rsp_fifo_out_data; // sw_reset_s_agent_rsp_fifo:out_data -> sw_reset_s_agent:rf_sink_data
wire sw_reset_s_agent_rsp_fifo_out_ready; // sw_reset_s_agent:rf_sink_ready -> sw_reset_s_agent_rsp_fifo:out_ready
wire sw_reset_s_agent_rdata_fifo_src_valid; // sw_reset_s_agent:rdata_fifo_src_valid -> sw_reset_s_agent:rdata_fifo_sink_valid
wire [65:0] sw_reset_s_agent_rdata_fifo_src_data; // sw_reset_s_agent:rdata_fifo_src_data -> sw_reset_s_agent:rdata_fifo_sink_data
wire sw_reset_s_agent_rdata_fifo_src_ready; // sw_reset_s_agent:rdata_fifo_sink_ready -> sw_reset_s_agent:rdata_fifo_src_ready
wire mem_org_mode_s_agent_m0_waitrequest; // mem_org_mode_s_translator:uav_waitrequest -> mem_org_mode_s_agent:m0_waitrequest
wire [2:0] mem_org_mode_s_agent_m0_burstcount; // mem_org_mode_s_agent:m0_burstcount -> mem_org_mode_s_translator:uav_burstcount
wire [31:0] mem_org_mode_s_agent_m0_writedata; // mem_org_mode_s_agent:m0_writedata -> mem_org_mode_s_translator:uav_writedata
wire [13:0] mem_org_mode_s_agent_m0_address; // mem_org_mode_s_agent:m0_address -> mem_org_mode_s_translator:uav_address
wire mem_org_mode_s_agent_m0_write; // mem_org_mode_s_agent:m0_write -> mem_org_mode_s_translator:uav_write
wire mem_org_mode_s_agent_m0_lock; // mem_org_mode_s_agent:m0_lock -> mem_org_mode_s_translator:uav_lock
wire mem_org_mode_s_agent_m0_read; // mem_org_mode_s_agent:m0_read -> mem_org_mode_s_translator:uav_read
wire [31:0] mem_org_mode_s_agent_m0_readdata; // mem_org_mode_s_translator:uav_readdata -> mem_org_mode_s_agent:m0_readdata
wire mem_org_mode_s_agent_m0_readdatavalid; // mem_org_mode_s_translator:uav_readdatavalid -> mem_org_mode_s_agent:m0_readdatavalid
wire mem_org_mode_s_agent_m0_debugaccess; // mem_org_mode_s_agent:m0_debugaccess -> mem_org_mode_s_translator:uav_debugaccess
wire [3:0] mem_org_mode_s_agent_m0_byteenable; // mem_org_mode_s_agent:m0_byteenable -> mem_org_mode_s_translator:uav_byteenable
wire mem_org_mode_s_agent_rf_source_endofpacket; // mem_org_mode_s_agent:rf_source_endofpacket -> mem_org_mode_s_agent_rsp_fifo:in_endofpacket
wire mem_org_mode_s_agent_rf_source_valid; // mem_org_mode_s_agent:rf_source_valid -> mem_org_mode_s_agent_rsp_fifo:in_valid
wire mem_org_mode_s_agent_rf_source_startofpacket; // mem_org_mode_s_agent:rf_source_startofpacket -> mem_org_mode_s_agent_rsp_fifo:in_startofpacket
wire [89:0] mem_org_mode_s_agent_rf_source_data; // mem_org_mode_s_agent:rf_source_data -> mem_org_mode_s_agent_rsp_fifo:in_data
wire mem_org_mode_s_agent_rf_source_ready; // mem_org_mode_s_agent_rsp_fifo:in_ready -> mem_org_mode_s_agent:rf_source_ready
wire mem_org_mode_s_agent_rsp_fifo_out_endofpacket; // mem_org_mode_s_agent_rsp_fifo:out_endofpacket -> mem_org_mode_s_agent:rf_sink_endofpacket
wire mem_org_mode_s_agent_rsp_fifo_out_valid; // mem_org_mode_s_agent_rsp_fifo:out_valid -> mem_org_mode_s_agent:rf_sink_valid
wire mem_org_mode_s_agent_rsp_fifo_out_startofpacket; // mem_org_mode_s_agent_rsp_fifo:out_startofpacket -> mem_org_mode_s_agent:rf_sink_startofpacket
wire [89:0] mem_org_mode_s_agent_rsp_fifo_out_data; // mem_org_mode_s_agent_rsp_fifo:out_data -> mem_org_mode_s_agent:rf_sink_data
wire mem_org_mode_s_agent_rsp_fifo_out_ready; // mem_org_mode_s_agent:rf_sink_ready -> mem_org_mode_s_agent_rsp_fifo:out_ready
wire mem_org_mode_s_agent_rdata_fifo_src_valid; // mem_org_mode_s_agent:rdata_fifo_src_valid -> mem_org_mode_s_agent:rdata_fifo_sink_valid
wire [33:0] mem_org_mode_s_agent_rdata_fifo_src_data; // mem_org_mode_s_agent:rdata_fifo_src_data -> mem_org_mode_s_agent:rdata_fifo_sink_data
wire mem_org_mode_s_agent_rdata_fifo_src_ready; // mem_org_mode_s_agent:rdata_fifo_sink_ready -> mem_org_mode_s_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> mem_org_mode_s_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> mem_org_mode_s_agent:cp_valid
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> mem_org_mode_s_agent:cp_startofpacket
wire [88:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> mem_org_mode_s_agent:cp_data
wire [6:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> mem_org_mode_s_agent:cp_channel
wire cmd_mux_004_src_ready; // mem_org_mode_s_agent:cp_ready -> cmd_mux_004:src_ready
wire version_id_0_s_agent_m0_waitrequest; // version_id_0_s_translator:uav_waitrequest -> version_id_0_s_agent:m0_waitrequest
wire [2:0] version_id_0_s_agent_m0_burstcount; // version_id_0_s_agent:m0_burstcount -> version_id_0_s_translator:uav_burstcount
wire [31:0] version_id_0_s_agent_m0_writedata; // version_id_0_s_agent:m0_writedata -> version_id_0_s_translator:uav_writedata
wire [13:0] version_id_0_s_agent_m0_address; // version_id_0_s_agent:m0_address -> version_id_0_s_translator:uav_address
wire version_id_0_s_agent_m0_write; // version_id_0_s_agent:m0_write -> version_id_0_s_translator:uav_write
wire version_id_0_s_agent_m0_lock; // version_id_0_s_agent:m0_lock -> version_id_0_s_translator:uav_lock
wire version_id_0_s_agent_m0_read; // version_id_0_s_agent:m0_read -> version_id_0_s_translator:uav_read
wire [31:0] version_id_0_s_agent_m0_readdata; // version_id_0_s_translator:uav_readdata -> version_id_0_s_agent:m0_readdata
wire version_id_0_s_agent_m0_readdatavalid; // version_id_0_s_translator:uav_readdatavalid -> version_id_0_s_agent:m0_readdatavalid
wire version_id_0_s_agent_m0_debugaccess; // version_id_0_s_agent:m0_debugaccess -> version_id_0_s_translator:uav_debugaccess
wire [3:0] version_id_0_s_agent_m0_byteenable; // version_id_0_s_agent:m0_byteenable -> version_id_0_s_translator:uav_byteenable
wire version_id_0_s_agent_rf_source_endofpacket; // version_id_0_s_agent:rf_source_endofpacket -> version_id_0_s_agent_rsp_fifo:in_endofpacket
wire version_id_0_s_agent_rf_source_valid; // version_id_0_s_agent:rf_source_valid -> version_id_0_s_agent_rsp_fifo:in_valid
wire version_id_0_s_agent_rf_source_startofpacket; // version_id_0_s_agent:rf_source_startofpacket -> version_id_0_s_agent_rsp_fifo:in_startofpacket
wire [89:0] version_id_0_s_agent_rf_source_data; // version_id_0_s_agent:rf_source_data -> version_id_0_s_agent_rsp_fifo:in_data
wire version_id_0_s_agent_rf_source_ready; // version_id_0_s_agent_rsp_fifo:in_ready -> version_id_0_s_agent:rf_source_ready
wire version_id_0_s_agent_rsp_fifo_out_endofpacket; // version_id_0_s_agent_rsp_fifo:out_endofpacket -> version_id_0_s_agent:rf_sink_endofpacket
wire version_id_0_s_agent_rsp_fifo_out_valid; // version_id_0_s_agent_rsp_fifo:out_valid -> version_id_0_s_agent:rf_sink_valid
wire version_id_0_s_agent_rsp_fifo_out_startofpacket; // version_id_0_s_agent_rsp_fifo:out_startofpacket -> version_id_0_s_agent:rf_sink_startofpacket
wire [89:0] version_id_0_s_agent_rsp_fifo_out_data; // version_id_0_s_agent_rsp_fifo:out_data -> version_id_0_s_agent:rf_sink_data
wire version_id_0_s_agent_rsp_fifo_out_ready; // version_id_0_s_agent:rf_sink_ready -> version_id_0_s_agent_rsp_fifo:out_ready
wire version_id_0_s_agent_rdata_fifo_src_valid; // version_id_0_s_agent:rdata_fifo_src_valid -> version_id_0_s_agent:rdata_fifo_sink_valid
wire [33:0] version_id_0_s_agent_rdata_fifo_src_data; // version_id_0_s_agent:rdata_fifo_src_data -> version_id_0_s_agent:rdata_fifo_sink_data
wire version_id_0_s_agent_rdata_fifo_src_ready; // version_id_0_s_agent:rdata_fifo_sink_ready -> version_id_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> version_id_0_s_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> version_id_0_s_agent:cp_valid
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> version_id_0_s_agent:cp_startofpacket
wire [88:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> version_id_0_s_agent:cp_data
wire [6:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> version_id_0_s_agent:cp_channel
wire cmd_mux_005_src_ready; // version_id_0_s_agent:cp_ready -> cmd_mux_005:src_ready
wire irq_ena_0_s_agent_m0_waitrequest; // irq_ena_0_s_translator:uav_waitrequest -> irq_ena_0_s_agent:m0_waitrequest
wire [2:0] irq_ena_0_s_agent_m0_burstcount; // irq_ena_0_s_agent:m0_burstcount -> irq_ena_0_s_translator:uav_burstcount
wire [31:0] irq_ena_0_s_agent_m0_writedata; // irq_ena_0_s_agent:m0_writedata -> irq_ena_0_s_translator:uav_writedata
wire [13:0] irq_ena_0_s_agent_m0_address; // irq_ena_0_s_agent:m0_address -> irq_ena_0_s_translator:uav_address
wire irq_ena_0_s_agent_m0_write; // irq_ena_0_s_agent:m0_write -> irq_ena_0_s_translator:uav_write
wire irq_ena_0_s_agent_m0_lock; // irq_ena_0_s_agent:m0_lock -> irq_ena_0_s_translator:uav_lock
wire irq_ena_0_s_agent_m0_read; // irq_ena_0_s_agent:m0_read -> irq_ena_0_s_translator:uav_read
wire [31:0] irq_ena_0_s_agent_m0_readdata; // irq_ena_0_s_translator:uav_readdata -> irq_ena_0_s_agent:m0_readdata
wire irq_ena_0_s_agent_m0_readdatavalid; // irq_ena_0_s_translator:uav_readdatavalid -> irq_ena_0_s_agent:m0_readdatavalid
wire irq_ena_0_s_agent_m0_debugaccess; // irq_ena_0_s_agent:m0_debugaccess -> irq_ena_0_s_translator:uav_debugaccess
wire [3:0] irq_ena_0_s_agent_m0_byteenable; // irq_ena_0_s_agent:m0_byteenable -> irq_ena_0_s_translator:uav_byteenable
wire irq_ena_0_s_agent_rf_source_endofpacket; // irq_ena_0_s_agent:rf_source_endofpacket -> irq_ena_0_s_agent_rsp_fifo:in_endofpacket
wire irq_ena_0_s_agent_rf_source_valid; // irq_ena_0_s_agent:rf_source_valid -> irq_ena_0_s_agent_rsp_fifo:in_valid
wire irq_ena_0_s_agent_rf_source_startofpacket; // irq_ena_0_s_agent:rf_source_startofpacket -> irq_ena_0_s_agent_rsp_fifo:in_startofpacket
wire [89:0] irq_ena_0_s_agent_rf_source_data; // irq_ena_0_s_agent:rf_source_data -> irq_ena_0_s_agent_rsp_fifo:in_data
wire irq_ena_0_s_agent_rf_source_ready; // irq_ena_0_s_agent_rsp_fifo:in_ready -> irq_ena_0_s_agent:rf_source_ready
wire irq_ena_0_s_agent_rsp_fifo_out_endofpacket; // irq_ena_0_s_agent_rsp_fifo:out_endofpacket -> irq_ena_0_s_agent:rf_sink_endofpacket
wire irq_ena_0_s_agent_rsp_fifo_out_valid; // irq_ena_0_s_agent_rsp_fifo:out_valid -> irq_ena_0_s_agent:rf_sink_valid
wire irq_ena_0_s_agent_rsp_fifo_out_startofpacket; // irq_ena_0_s_agent_rsp_fifo:out_startofpacket -> irq_ena_0_s_agent:rf_sink_startofpacket
wire [89:0] irq_ena_0_s_agent_rsp_fifo_out_data; // irq_ena_0_s_agent_rsp_fifo:out_data -> irq_ena_0_s_agent:rf_sink_data
wire irq_ena_0_s_agent_rsp_fifo_out_ready; // irq_ena_0_s_agent:rf_sink_ready -> irq_ena_0_s_agent_rsp_fifo:out_ready
wire irq_ena_0_s_agent_rdata_fifo_src_valid; // irq_ena_0_s_agent:rdata_fifo_src_valid -> irq_ena_0_s_agent:rdata_fifo_sink_valid
wire [33:0] irq_ena_0_s_agent_rdata_fifo_src_data; // irq_ena_0_s_agent:rdata_fifo_src_data -> irq_ena_0_s_agent:rdata_fifo_sink_data
wire irq_ena_0_s_agent_rdata_fifo_src_ready; // irq_ena_0_s_agent:rdata_fifo_sink_ready -> irq_ena_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> irq_ena_0_s_agent:cp_endofpacket
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> irq_ena_0_s_agent:cp_valid
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> irq_ena_0_s_agent:cp_startofpacket
wire [88:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> irq_ena_0_s_agent:cp_data
wire [6:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> irq_ena_0_s_agent:cp_channel
wire cmd_mux_006_src_ready; // irq_ena_0_s_agent:cp_ready -> cmd_mux_006:src_ready
wire kernel_cntrl_m0_agent_cp_endofpacket; // kernel_cntrl_m0_agent:cp_endofpacket -> router:sink_endofpacket
wire kernel_cntrl_m0_agent_cp_valid; // kernel_cntrl_m0_agent:cp_valid -> router:sink_valid
wire kernel_cntrl_m0_agent_cp_startofpacket; // kernel_cntrl_m0_agent:cp_startofpacket -> router:sink_startofpacket
wire [88:0] kernel_cntrl_m0_agent_cp_data; // kernel_cntrl_m0_agent:cp_data -> router:sink_data
wire kernel_cntrl_m0_agent_cp_ready; // router:sink_ready -> kernel_cntrl_m0_agent:cp_ready
wire address_span_extender_0_windowed_slave_agent_rp_endofpacket; // address_span_extender_0_windowed_slave_agent:rp_endofpacket -> router_001:sink_endofpacket
wire address_span_extender_0_windowed_slave_agent_rp_valid; // address_span_extender_0_windowed_slave_agent:rp_valid -> router_001:sink_valid
wire address_span_extender_0_windowed_slave_agent_rp_startofpacket; // address_span_extender_0_windowed_slave_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [88:0] address_span_extender_0_windowed_slave_agent_rp_data; // address_span_extender_0_windowed_slave_agent:rp_data -> router_001:sink_data
wire address_span_extender_0_windowed_slave_agent_rp_ready; // router_001:sink_ready -> address_span_extender_0_windowed_slave_agent:rp_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire [88:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire [6:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire address_span_extender_0_cntl_agent_rp_endofpacket; // address_span_extender_0_cntl_agent:rp_endofpacket -> router_002:sink_endofpacket
wire address_span_extender_0_cntl_agent_rp_valid; // address_span_extender_0_cntl_agent:rp_valid -> router_002:sink_valid
wire address_span_extender_0_cntl_agent_rp_startofpacket; // address_span_extender_0_cntl_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [124:0] address_span_extender_0_cntl_agent_rp_data; // address_span_extender_0_cntl_agent:rp_data -> router_002:sink_data
wire address_span_extender_0_cntl_agent_rp_ready; // router_002:sink_ready -> address_span_extender_0_cntl_agent:rp_ready
wire sys_description_rom_s1_agent_rp_endofpacket; // sys_description_rom_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
wire sys_description_rom_s1_agent_rp_valid; // sys_description_rom_s1_agent:rp_valid -> router_003:sink_valid
wire sys_description_rom_s1_agent_rp_startofpacket; // sys_description_rom_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [124:0] sys_description_rom_s1_agent_rp_data; // sys_description_rom_s1_agent:rp_data -> router_003:sink_data
wire sys_description_rom_s1_agent_rp_ready; // router_003:sink_ready -> sys_description_rom_s1_agent:rp_ready
wire sw_reset_s_agent_rp_endofpacket; // sw_reset_s_agent:rp_endofpacket -> router_004:sink_endofpacket
wire sw_reset_s_agent_rp_valid; // sw_reset_s_agent:rp_valid -> router_004:sink_valid
wire sw_reset_s_agent_rp_startofpacket; // sw_reset_s_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [124:0] sw_reset_s_agent_rp_data; // sw_reset_s_agent:rp_data -> router_004:sink_data
wire sw_reset_s_agent_rp_ready; // router_004:sink_ready -> sw_reset_s_agent:rp_ready
wire mem_org_mode_s_agent_rp_endofpacket; // mem_org_mode_s_agent:rp_endofpacket -> router_005:sink_endofpacket
wire mem_org_mode_s_agent_rp_valid; // mem_org_mode_s_agent:rp_valid -> router_005:sink_valid
wire mem_org_mode_s_agent_rp_startofpacket; // mem_org_mode_s_agent:rp_startofpacket -> router_005:sink_startofpacket
wire [88:0] mem_org_mode_s_agent_rp_data; // mem_org_mode_s_agent:rp_data -> router_005:sink_data
wire mem_org_mode_s_agent_rp_ready; // router_005:sink_ready -> mem_org_mode_s_agent:rp_ready
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_004:sink_valid
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire [88:0] router_005_src_data; // router_005:src_data -> rsp_demux_004:sink_data
wire [6:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_004:sink_channel
wire router_005_src_ready; // rsp_demux_004:sink_ready -> router_005:src_ready
wire version_id_0_s_agent_rp_endofpacket; // version_id_0_s_agent:rp_endofpacket -> router_006:sink_endofpacket
wire version_id_0_s_agent_rp_valid; // version_id_0_s_agent:rp_valid -> router_006:sink_valid
wire version_id_0_s_agent_rp_startofpacket; // version_id_0_s_agent:rp_startofpacket -> router_006:sink_startofpacket
wire [88:0] version_id_0_s_agent_rp_data; // version_id_0_s_agent:rp_data -> router_006:sink_data
wire version_id_0_s_agent_rp_ready; // router_006:sink_ready -> version_id_0_s_agent:rp_ready
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_005:sink_valid
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire [88:0] router_006_src_data; // router_006:src_data -> rsp_demux_005:sink_data
wire [6:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_005:sink_channel
wire router_006_src_ready; // rsp_demux_005:sink_ready -> router_006:src_ready
wire irq_ena_0_s_agent_rp_endofpacket; // irq_ena_0_s_agent:rp_endofpacket -> router_007:sink_endofpacket
wire irq_ena_0_s_agent_rp_valid; // irq_ena_0_s_agent:rp_valid -> router_007:sink_valid
wire irq_ena_0_s_agent_rp_startofpacket; // irq_ena_0_s_agent:rp_startofpacket -> router_007:sink_startofpacket
wire [88:0] irq_ena_0_s_agent_rp_data; // irq_ena_0_s_agent:rp_data -> router_007:sink_data
wire irq_ena_0_s_agent_rp_ready; // router_007:sink_ready -> irq_ena_0_s_agent:rp_ready
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_006:sink_valid
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire [88:0] router_007_src_data; // router_007:src_data -> rsp_demux_006:sink_data
wire [6:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_006:sink_channel
wire router_007_src_ready; // rsp_demux_006:sink_ready -> router_007:src_ready
wire router_src_endofpacket; // router:src_endofpacket -> kernel_cntrl_m0_limiter:cmd_sink_endofpacket
wire router_src_valid; // router:src_valid -> kernel_cntrl_m0_limiter:cmd_sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> kernel_cntrl_m0_limiter:cmd_sink_startofpacket
wire [88:0] router_src_data; // router:src_data -> kernel_cntrl_m0_limiter:cmd_sink_data
wire [6:0] router_src_channel; // router:src_channel -> kernel_cntrl_m0_limiter:cmd_sink_channel
wire router_src_ready; // kernel_cntrl_m0_limiter:cmd_sink_ready -> router:src_ready
wire kernel_cntrl_m0_limiter_cmd_src_endofpacket; // kernel_cntrl_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire kernel_cntrl_m0_limiter_cmd_src_startofpacket; // kernel_cntrl_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire [88:0] kernel_cntrl_m0_limiter_cmd_src_data; // kernel_cntrl_m0_limiter:cmd_src_data -> cmd_demux:sink_data
wire [6:0] kernel_cntrl_m0_limiter_cmd_src_channel; // kernel_cntrl_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire kernel_cntrl_m0_limiter_cmd_src_ready; // cmd_demux:sink_ready -> kernel_cntrl_m0_limiter:cmd_src_ready
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> kernel_cntrl_m0_limiter:rsp_sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> kernel_cntrl_m0_limiter:rsp_sink_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> kernel_cntrl_m0_limiter:rsp_sink_startofpacket
wire [88:0] rsp_mux_src_data; // rsp_mux:src_data -> kernel_cntrl_m0_limiter:rsp_sink_data
wire [6:0] rsp_mux_src_channel; // rsp_mux:src_channel -> kernel_cntrl_m0_limiter:rsp_sink_channel
wire rsp_mux_src_ready; // kernel_cntrl_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire kernel_cntrl_m0_limiter_rsp_src_endofpacket; // kernel_cntrl_m0_limiter:rsp_src_endofpacket -> kernel_cntrl_m0_agent:rp_endofpacket
wire kernel_cntrl_m0_limiter_rsp_src_valid; // kernel_cntrl_m0_limiter:rsp_src_valid -> kernel_cntrl_m0_agent:rp_valid
wire kernel_cntrl_m0_limiter_rsp_src_startofpacket; // kernel_cntrl_m0_limiter:rsp_src_startofpacket -> kernel_cntrl_m0_agent:rp_startofpacket
wire [88:0] kernel_cntrl_m0_limiter_rsp_src_data; // kernel_cntrl_m0_limiter:rsp_src_data -> kernel_cntrl_m0_agent:rp_data
wire [6:0] kernel_cntrl_m0_limiter_rsp_src_channel; // kernel_cntrl_m0_limiter:rsp_src_channel -> kernel_cntrl_m0_agent:rp_channel
wire kernel_cntrl_m0_limiter_rsp_src_ready; // kernel_cntrl_m0_agent:rp_ready -> kernel_cntrl_m0_limiter:rsp_src_ready
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [88:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire [6:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire [88:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire [6:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire [88:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire [6:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire [88:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire [6:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire [88:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
wire [6:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire [88:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire [6:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire [88:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire [6:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire [88:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire [6:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire [88:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire [6:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
wire [88:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
wire [6:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> address_span_extender_0_cntl_cmd_width_adapter:in_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> address_span_extender_0_cntl_cmd_width_adapter:in_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> address_span_extender_0_cntl_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> address_span_extender_0_cntl_cmd_width_adapter:in_data
wire [6:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> address_span_extender_0_cntl_cmd_width_adapter:in_channel
wire cmd_mux_001_src_ready; // address_span_extender_0_cntl_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
wire address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket; // address_span_extender_0_cntl_cmd_width_adapter:out_endofpacket -> address_span_extender_0_cntl_agent:cp_endofpacket
wire address_span_extender_0_cntl_cmd_width_adapter_src_valid; // address_span_extender_0_cntl_cmd_width_adapter:out_valid -> address_span_extender_0_cntl_agent:cp_valid
wire address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket; // address_span_extender_0_cntl_cmd_width_adapter:out_startofpacket -> address_span_extender_0_cntl_agent:cp_startofpacket
wire [124:0] address_span_extender_0_cntl_cmd_width_adapter_src_data; // address_span_extender_0_cntl_cmd_width_adapter:out_data -> address_span_extender_0_cntl_agent:cp_data
wire address_span_extender_0_cntl_cmd_width_adapter_src_ready; // address_span_extender_0_cntl_agent:cp_ready -> address_span_extender_0_cntl_cmd_width_adapter:out_ready
wire [6:0] address_span_extender_0_cntl_cmd_width_adapter_src_channel; // address_span_extender_0_cntl_cmd_width_adapter:out_channel -> address_span_extender_0_cntl_agent:cp_channel
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> sys_description_rom_s1_cmd_width_adapter:in_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> sys_description_rom_s1_cmd_width_adapter:in_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> sys_description_rom_s1_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> sys_description_rom_s1_cmd_width_adapter:in_data
wire [6:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> sys_description_rom_s1_cmd_width_adapter:in_channel
wire cmd_mux_002_src_ready; // sys_description_rom_s1_cmd_width_adapter:in_ready -> cmd_mux_002:src_ready
wire sys_description_rom_s1_cmd_width_adapter_src_endofpacket; // sys_description_rom_s1_cmd_width_adapter:out_endofpacket -> sys_description_rom_s1_agent:cp_endofpacket
wire sys_description_rom_s1_cmd_width_adapter_src_valid; // sys_description_rom_s1_cmd_width_adapter:out_valid -> sys_description_rom_s1_agent:cp_valid
wire sys_description_rom_s1_cmd_width_adapter_src_startofpacket; // sys_description_rom_s1_cmd_width_adapter:out_startofpacket -> sys_description_rom_s1_agent:cp_startofpacket
wire [124:0] sys_description_rom_s1_cmd_width_adapter_src_data; // sys_description_rom_s1_cmd_width_adapter:out_data -> sys_description_rom_s1_agent:cp_data
wire sys_description_rom_s1_cmd_width_adapter_src_ready; // sys_description_rom_s1_agent:cp_ready -> sys_description_rom_s1_cmd_width_adapter:out_ready
wire [6:0] sys_description_rom_s1_cmd_width_adapter_src_channel; // sys_description_rom_s1_cmd_width_adapter:out_channel -> sys_description_rom_s1_agent:cp_channel
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sw_reset_s_cmd_width_adapter:in_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sw_reset_s_cmd_width_adapter:in_valid
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sw_reset_s_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sw_reset_s_cmd_width_adapter:in_data
wire [6:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sw_reset_s_cmd_width_adapter:in_channel
wire cmd_mux_003_src_ready; // sw_reset_s_cmd_width_adapter:in_ready -> cmd_mux_003:src_ready
wire sw_reset_s_cmd_width_adapter_src_endofpacket; // sw_reset_s_cmd_width_adapter:out_endofpacket -> sw_reset_s_agent:cp_endofpacket
wire sw_reset_s_cmd_width_adapter_src_valid; // sw_reset_s_cmd_width_adapter:out_valid -> sw_reset_s_agent:cp_valid
wire sw_reset_s_cmd_width_adapter_src_startofpacket; // sw_reset_s_cmd_width_adapter:out_startofpacket -> sw_reset_s_agent:cp_startofpacket
wire [124:0] sw_reset_s_cmd_width_adapter_src_data; // sw_reset_s_cmd_width_adapter:out_data -> sw_reset_s_agent:cp_data
wire sw_reset_s_cmd_width_adapter_src_ready; // sw_reset_s_agent:cp_ready -> sw_reset_s_cmd_width_adapter:out_ready
wire [6:0] sw_reset_s_cmd_width_adapter_src_channel; // sw_reset_s_cmd_width_adapter:out_channel -> sw_reset_s_agent:cp_channel
wire router_002_src_endofpacket; // router_002:src_endofpacket -> address_span_extender_0_cntl_rsp_width_adapter:in_endofpacket
wire router_002_src_valid; // router_002:src_valid -> address_span_extender_0_cntl_rsp_width_adapter:in_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> address_span_extender_0_cntl_rsp_width_adapter:in_startofpacket
wire [124:0] router_002_src_data; // router_002:src_data -> address_span_extender_0_cntl_rsp_width_adapter:in_data
wire [6:0] router_002_src_channel; // router_002:src_channel -> address_span_extender_0_cntl_rsp_width_adapter:in_channel
wire router_002_src_ready; // address_span_extender_0_cntl_rsp_width_adapter:in_ready -> router_002:src_ready
wire address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket; // address_span_extender_0_cntl_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
wire address_span_extender_0_cntl_rsp_width_adapter_src_valid; // address_span_extender_0_cntl_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
wire address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket; // address_span_extender_0_cntl_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
wire [88:0] address_span_extender_0_cntl_rsp_width_adapter_src_data; // address_span_extender_0_cntl_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
wire address_span_extender_0_cntl_rsp_width_adapter_src_ready; // rsp_demux_001:sink_ready -> address_span_extender_0_cntl_rsp_width_adapter:out_ready
wire [6:0] address_span_extender_0_cntl_rsp_width_adapter_src_channel; // address_span_extender_0_cntl_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
wire router_003_src_endofpacket; // router_003:src_endofpacket -> sys_description_rom_s1_rsp_width_adapter:in_endofpacket
wire router_003_src_valid; // router_003:src_valid -> sys_description_rom_s1_rsp_width_adapter:in_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> sys_description_rom_s1_rsp_width_adapter:in_startofpacket
wire [124:0] router_003_src_data; // router_003:src_data -> sys_description_rom_s1_rsp_width_adapter:in_data
wire [6:0] router_003_src_channel; // router_003:src_channel -> sys_description_rom_s1_rsp_width_adapter:in_channel
wire router_003_src_ready; // sys_description_rom_s1_rsp_width_adapter:in_ready -> router_003:src_ready
wire sys_description_rom_s1_rsp_width_adapter_src_endofpacket; // sys_description_rom_s1_rsp_width_adapter:out_endofpacket -> rsp_demux_002:sink_endofpacket
wire sys_description_rom_s1_rsp_width_adapter_src_valid; // sys_description_rom_s1_rsp_width_adapter:out_valid -> rsp_demux_002:sink_valid
wire sys_description_rom_s1_rsp_width_adapter_src_startofpacket; // sys_description_rom_s1_rsp_width_adapter:out_startofpacket -> rsp_demux_002:sink_startofpacket
wire [88:0] sys_description_rom_s1_rsp_width_adapter_src_data; // sys_description_rom_s1_rsp_width_adapter:out_data -> rsp_demux_002:sink_data
wire sys_description_rom_s1_rsp_width_adapter_src_ready; // rsp_demux_002:sink_ready -> sys_description_rom_s1_rsp_width_adapter:out_ready
wire [6:0] sys_description_rom_s1_rsp_width_adapter_src_channel; // sys_description_rom_s1_rsp_width_adapter:out_channel -> rsp_demux_002:sink_channel
wire router_004_src_endofpacket; // router_004:src_endofpacket -> sw_reset_s_rsp_width_adapter:in_endofpacket
wire router_004_src_valid; // router_004:src_valid -> sw_reset_s_rsp_width_adapter:in_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> sw_reset_s_rsp_width_adapter:in_startofpacket
wire [124:0] router_004_src_data; // router_004:src_data -> sw_reset_s_rsp_width_adapter:in_data
wire [6:0] router_004_src_channel; // router_004:src_channel -> sw_reset_s_rsp_width_adapter:in_channel
wire router_004_src_ready; // sw_reset_s_rsp_width_adapter:in_ready -> router_004:src_ready
wire sw_reset_s_rsp_width_adapter_src_endofpacket; // sw_reset_s_rsp_width_adapter:out_endofpacket -> rsp_demux_003:sink_endofpacket
wire sw_reset_s_rsp_width_adapter_src_valid; // sw_reset_s_rsp_width_adapter:out_valid -> rsp_demux_003:sink_valid
wire sw_reset_s_rsp_width_adapter_src_startofpacket; // sw_reset_s_rsp_width_adapter:out_startofpacket -> rsp_demux_003:sink_startofpacket
wire [88:0] sw_reset_s_rsp_width_adapter_src_data; // sw_reset_s_rsp_width_adapter:out_data -> rsp_demux_003:sink_data
wire sw_reset_s_rsp_width_adapter_src_ready; // rsp_demux_003:sink_ready -> sw_reset_s_rsp_width_adapter:out_ready
wire [6:0] sw_reset_s_rsp_width_adapter_src_channel; // sw_reset_s_rsp_width_adapter:out_channel -> rsp_demux_003:sink_channel
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> crosser:in_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
wire [88:0] cmd_demux_src0_data; // cmd_demux:src0_data -> crosser:in_data
wire [6:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> crosser:in_channel
wire cmd_demux_src0_ready; // crosser:in_ready -> cmd_demux:src0_ready
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux:sink0_valid
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
wire [88:0] crosser_out_data; // crosser:out_data -> cmd_mux:sink0_data
wire [6:0] crosser_out_channel; // crosser:out_channel -> cmd_mux:sink0_channel
wire crosser_out_ready; // cmd_mux:sink0_ready -> crosser:out_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> crosser_001:in_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> crosser_001:in_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> crosser_001:in_startofpacket
wire [88:0] cmd_demux_src1_data; // cmd_demux:src1_data -> crosser_001:in_data
wire [6:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> crosser_001:in_channel
wire cmd_demux_src1_ready; // crosser_001:in_ready -> cmd_demux:src1_ready
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_001:sink0_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_001:sink0_valid
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [88:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_001:sink0_data
wire [6:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_001:sink0_channel
wire crosser_001_out_ready; // cmd_mux_001:sink0_ready -> crosser_001:out_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> crosser_002:in_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> crosser_002:in_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> crosser_002:in_startofpacket
wire [88:0] rsp_demux_src0_data; // rsp_demux:src0_data -> crosser_002:in_data
wire [6:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> crosser_002:in_channel
wire rsp_demux_src0_ready; // crosser_002:in_ready -> rsp_demux:src0_ready
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> rsp_mux:sink0_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> rsp_mux:sink0_valid
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> rsp_mux:sink0_startofpacket
wire [88:0] crosser_002_out_data; // crosser_002:out_data -> rsp_mux:sink0_data
wire [6:0] crosser_002_out_channel; // crosser_002:out_channel -> rsp_mux:sink0_channel
wire crosser_002_out_ready; // rsp_mux:sink0_ready -> crosser_002:out_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> crosser_003:in_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> crosser_003:in_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> crosser_003:in_startofpacket
wire [88:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> crosser_003:in_data
wire [6:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> crosser_003:in_channel
wire rsp_demux_001_src0_ready; // crosser_003:in_ready -> rsp_demux_001:src0_ready
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_mux:sink1_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_mux:sink1_valid
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_mux:sink1_startofpacket
wire [88:0] crosser_003_out_data; // crosser_003:out_data -> rsp_mux:sink1_data
wire [6:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_mux:sink1_channel
wire crosser_003_out_ready; // rsp_mux:sink1_ready -> crosser_003:out_ready
wire [6:0] kernel_cntrl_m0_limiter_cmd_valid_data; // kernel_cntrl_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) kernel_cntrl_m0_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cntrl_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (kernel_cntrl_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (kernel_cntrl_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (kernel_cntrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (kernel_cntrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (kernel_cntrl_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (kernel_cntrl_m0_address), // avalon_anti_master_0.address
.av_waitrequest (kernel_cntrl_m0_waitrequest), // .waitrequest
.av_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.av_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.av_read (kernel_cntrl_m0_read), // .read
.av_readdata (kernel_cntrl_m0_readdata), // .readdata
.av_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.av_write (kernel_cntrl_m0_write), // .write
.av_writedata (kernel_cntrl_m0_writedata), // .writedata
.av_debugaccess (kernel_cntrl_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (10),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_0_windowed_slave_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_windowed_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (address_span_extender_0_windowed_slave_agent_m0_burstcount), // .burstcount
.uav_read (address_span_extender_0_windowed_slave_agent_m0_read), // .read
.uav_write (address_span_extender_0_windowed_slave_agent_m0_write), // .write
.uav_waitrequest (address_span_extender_0_windowed_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_windowed_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_windowed_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_windowed_slave_agent_m0_readdata), // .readdata
.uav_writedata (address_span_extender_0_windowed_slave_agent_m0_writedata), // .writedata
.uav_lock (address_span_extender_0_windowed_slave_agent_m0_lock), // .lock
.uav_debugaccess (address_span_extender_0_windowed_slave_agent_m0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_windowed_slave_address), // avalon_anti_slave_0.address
.av_write (address_span_extender_0_windowed_slave_write), // .write
.av_read (address_span_extender_0_windowed_slave_read), // .read
.av_readdata (address_span_extender_0_windowed_slave_readdata), // .readdata
.av_writedata (address_span_extender_0_windowed_slave_writedata), // .writedata
.av_burstcount (address_span_extender_0_windowed_slave_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_windowed_slave_byteenable), // .byteenable
.av_readdatavalid (address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.av_waitrequest (address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_0_cntl_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_cntl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (address_span_extender_0_cntl_agent_m0_burstcount), // .burstcount
.uav_read (address_span_extender_0_cntl_agent_m0_read), // .read
.uav_write (address_span_extender_0_cntl_agent_m0_write), // .write
.uav_waitrequest (address_span_extender_0_cntl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_cntl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_cntl_agent_m0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_cntl_agent_m0_readdata), // .readdata
.uav_writedata (address_span_extender_0_cntl_agent_m0_writedata), // .writedata
.uav_lock (address_span_extender_0_cntl_agent_m0_lock), // .lock
.uav_debugaccess (address_span_extender_0_cntl_agent_m0_debugaccess), // .debugaccess
.av_write (address_span_extender_0_cntl_write), // avalon_anti_slave_0.write
.av_read (address_span_extender_0_cntl_read), // .read
.av_readdata (address_span_extender_0_cntl_readdata), // .readdata
.av_writedata (address_span_extender_0_cntl_writedata), // .writedata
.av_byteenable (address_span_extender_0_cntl_byteenable), // .byteenable
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (2),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sys_description_rom_s1_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sys_description_rom_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sys_description_rom_s1_agent_m0_burstcount), // .burstcount
.uav_read (sys_description_rom_s1_agent_m0_read), // .read
.uav_write (sys_description_rom_s1_agent_m0_write), // .write
.uav_waitrequest (sys_description_rom_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sys_description_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sys_description_rom_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sys_description_rom_s1_agent_m0_readdata), // .readdata
.uav_writedata (sys_description_rom_s1_agent_m0_writedata), // .writedata
.uav_lock (sys_description_rom_s1_agent_m0_lock), // .lock
.uav_debugaccess (sys_description_rom_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sys_description_rom_s1_address), // avalon_anti_slave_0.address
.av_write (sys_description_rom_s1_write), // .write
.av_readdata (sys_description_rom_s1_readdata), // .readdata
.av_writedata (sys_description_rom_s1_writedata), // .writedata
.av_byteenable (sys_description_rom_s1_byteenable), // .byteenable
.av_chipselect (sys_description_rom_s1_chipselect), // .chipselect
.av_clken (sys_description_rom_s1_clken), // .clken
.av_debugaccess (sys_description_rom_s1_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sw_reset_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sw_reset_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sw_reset_s_agent_m0_burstcount), // .burstcount
.uav_read (sw_reset_s_agent_m0_read), // .read
.uav_write (sw_reset_s_agent_m0_write), // .write
.uav_waitrequest (sw_reset_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sw_reset_s_agent_m0_byteenable), // .byteenable
.uav_readdata (sw_reset_s_agent_m0_readdata), // .readdata
.uav_writedata (sw_reset_s_agent_m0_writedata), // .writedata
.uav_lock (sw_reset_s_agent_m0_lock), // .lock
.uav_debugaccess (sw_reset_s_agent_m0_debugaccess), // .debugaccess
.av_write (sw_reset_s_write), // avalon_anti_slave_0.write
.av_read (sw_reset_s_read), // .read
.av_readdata (sw_reset_s_readdata), // .readdata
.av_writedata (sw_reset_s_writedata), // .writedata
.av_byteenable (sw_reset_s_byteenable), // .byteenable
.av_waitrequest (sw_reset_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) mem_org_mode_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (mem_org_mode_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (mem_org_mode_s_agent_m0_burstcount), // .burstcount
.uav_read (mem_org_mode_s_agent_m0_read), // .read
.uav_write (mem_org_mode_s_agent_m0_write), // .write
.uav_waitrequest (mem_org_mode_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (mem_org_mode_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (mem_org_mode_s_agent_m0_byteenable), // .byteenable
.uav_readdata (mem_org_mode_s_agent_m0_readdata), // .readdata
.uav_writedata (mem_org_mode_s_agent_m0_writedata), // .writedata
.uav_lock (mem_org_mode_s_agent_m0_lock), // .lock
.uav_debugaccess (mem_org_mode_s_agent_m0_debugaccess), // .debugaccess
.av_write (mem_org_mode_s_write), // avalon_anti_slave_0.write
.av_read (mem_org_mode_s_read), // .read
.av_readdata (mem_org_mode_s_readdata), // .readdata
.av_writedata (mem_org_mode_s_writedata), // .writedata
.av_waitrequest (mem_org_mode_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) version_id_0_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (version_id_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.uav_read (version_id_0_s_agent_m0_read), // .read
.uav_write (version_id_0_s_agent_m0_write), // .write
.uav_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.uav_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.uav_lock (version_id_0_s_agent_m0_lock), // .lock
.uav_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.av_read (version_id_0_s_read), // avalon_anti_slave_0.read
.av_readdata (version_id_0_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) irq_ena_0_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (irq_ena_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (irq_ena_0_s_agent_m0_burstcount), // .burstcount
.uav_read (irq_ena_0_s_agent_m0_read), // .read
.uav_write (irq_ena_0_s_agent_m0_write), // .write
.uav_waitrequest (irq_ena_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (irq_ena_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (irq_ena_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (irq_ena_0_s_agent_m0_readdata), // .readdata
.uav_writedata (irq_ena_0_s_agent_m0_writedata), // .writedata
.uav_lock (irq_ena_0_s_agent_m0_lock), // .lock
.uav_debugaccess (irq_ena_0_s_agent_m0_debugaccess), // .debugaccess
.av_write (irq_ena_0_s_write), // avalon_anti_slave_0.write
.av_read (irq_ena_0_s_read), // .read
.av_readdata (irq_ena_0_s_readdata), // .readdata
.av_writedata (irq_ena_0_s_writedata), // .writedata
.av_byteenable (irq_ena_0_s_byteenable), // .byteenable
.av_waitrequest (irq_ena_0_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_BEGIN_BURST (68),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_BURST_TYPE_H (65),
.PKT_BURST_TYPE_L (64),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_TRANS_EXCLUSIVE (55),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_THREAD_ID_H (76),
.PKT_THREAD_ID_L (76),
.PKT_CACHE_H (83),
.PKT_CACHE_L (80),
.PKT_DATA_SIDEBAND_H (67),
.PKT_DATA_SIDEBAND_L (67),
.PKT_QOS_H (69),
.PKT_QOS_L (69),
.PKT_ADDR_SIDEBAND_H (66),
.PKT_ADDR_SIDEBAND_L (66),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_DATA_W (89),
.ST_CHANNEL_W (7),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) kernel_cntrl_m0_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (kernel_cntrl_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (kernel_cntrl_m0_translator_avalon_universal_master_0_write), // .write
.av_read (kernel_cntrl_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (kernel_cntrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (kernel_cntrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (kernel_cntrl_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (kernel_cntrl_m0_agent_cp_valid), // cp.valid
.cp_data (kernel_cntrl_m0_agent_cp_data), // .data
.cp_startofpacket (kernel_cntrl_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cntrl_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (kernel_cntrl_m0_agent_cp_ready), // .ready
.rp_valid (kernel_cntrl_m0_limiter_rsp_src_valid), // rp.valid
.rp_data (kernel_cntrl_m0_limiter_rsp_src_data), // .data
.rp_channel (kernel_cntrl_m0_limiter_rsp_src_channel), // .channel
.rp_startofpacket (kernel_cntrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (kernel_cntrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (kernel_cntrl_m0_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_windowed_slave_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (address_span_extender_0_windowed_slave_agent_m0_address), // m0.address
.m0_burstcount (address_span_extender_0_windowed_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (address_span_extender_0_windowed_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (address_span_extender_0_windowed_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (address_span_extender_0_windowed_slave_agent_m0_lock), // .lock
.m0_readdata (address_span_extender_0_windowed_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (address_span_extender_0_windowed_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (address_span_extender_0_windowed_slave_agent_m0_read), // .read
.m0_waitrequest (address_span_extender_0_windowed_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (address_span_extender_0_windowed_slave_agent_m0_writedata), // .writedata
.m0_write (address_span_extender_0_windowed_slave_agent_m0_write), // .write
.rp_endofpacket (address_span_extender_0_windowed_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (address_span_extender_0_windowed_slave_agent_rp_ready), // .ready
.rp_valid (address_span_extender_0_windowed_slave_agent_rp_valid), // .valid
.rp_data (address_span_extender_0_windowed_slave_agent_rp_data), // .data
.rp_startofpacket (address_span_extender_0_windowed_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (address_span_extender_0_windowed_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (address_span_extender_0_windowed_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (address_span_extender_0_windowed_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (address_span_extender_0_windowed_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (address_span_extender_0_windowed_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_windowed_slave_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_windowed_slave_agent_rf_source_data), // in.data
.in_valid (address_span_extender_0_windowed_slave_agent_rf_source_valid), // .valid
.in_ready (address_span_extender_0_windowed_slave_agent_rf_source_ready), // .ready
.in_startofpacket (address_span_extender_0_windowed_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (address_span_extender_0_windowed_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_windowed_slave_agent_rdata_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_cntl_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (address_span_extender_0_cntl_agent_m0_address), // m0.address
.m0_burstcount (address_span_extender_0_cntl_agent_m0_burstcount), // .burstcount
.m0_byteenable (address_span_extender_0_cntl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (address_span_extender_0_cntl_agent_m0_debugaccess), // .debugaccess
.m0_lock (address_span_extender_0_cntl_agent_m0_lock), // .lock
.m0_readdata (address_span_extender_0_cntl_agent_m0_readdata), // .readdata
.m0_readdatavalid (address_span_extender_0_cntl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (address_span_extender_0_cntl_agent_m0_read), // .read
.m0_waitrequest (address_span_extender_0_cntl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (address_span_extender_0_cntl_agent_m0_writedata), // .writedata
.m0_write (address_span_extender_0_cntl_agent_m0_write), // .write
.rp_endofpacket (address_span_extender_0_cntl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (address_span_extender_0_cntl_agent_rp_ready), // .ready
.rp_valid (address_span_extender_0_cntl_agent_rp_valid), // .valid
.rp_data (address_span_extender_0_cntl_agent_rp_data), // .data
.rp_startofpacket (address_span_extender_0_cntl_agent_rp_startofpacket), // .startofpacket
.cp_ready (address_span_extender_0_cntl_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (address_span_extender_0_cntl_cmd_width_adapter_src_valid), // .valid
.cp_data (address_span_extender_0_cntl_cmd_width_adapter_src_data), // .data
.cp_startofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (address_span_extender_0_cntl_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (address_span_extender_0_cntl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (address_span_extender_0_cntl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (address_span_extender_0_cntl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (address_span_extender_0_cntl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (address_span_extender_0_cntl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (address_span_extender_0_cntl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (address_span_extender_0_cntl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (address_span_extender_0_cntl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (address_span_extender_0_cntl_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (address_span_extender_0_cntl_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (address_span_extender_0_cntl_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (address_span_extender_0_cntl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (address_span_extender_0_cntl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (address_span_extender_0_cntl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_cntl_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_cntl_agent_rf_source_data), // in.data
.in_valid (address_span_extender_0_cntl_agent_rf_source_valid), // .valid
.in_ready (address_span_extender_0_cntl_agent_rf_source_ready), // .ready
.in_startofpacket (address_span_extender_0_cntl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (address_span_extender_0_cntl_agent_rf_source_endofpacket), // .endofpacket
.out_data (address_span_extender_0_cntl_agent_rsp_fifo_out_data), // out.data
.out_valid (address_span_extender_0_cntl_agent_rsp_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_cntl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (66),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_cntl_agent_rdata_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_cntl_agent_rdata_fifo_src_data), // in.data
.in_valid (address_span_extender_0_cntl_agent_rdata_fifo_src_valid), // .valid
.in_ready (address_span_extender_0_cntl_agent_rdata_fifo_src_ready), // .ready
.out_data (address_span_extender_0_cntl_agent_rdata_fifo_out_data), // out.data
.out_valid (address_span_extender_0_cntl_agent_rdata_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_cntl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sys_description_rom_s1_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sys_description_rom_s1_agent_m0_address), // m0.address
.m0_burstcount (sys_description_rom_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sys_description_rom_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sys_description_rom_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sys_description_rom_s1_agent_m0_lock), // .lock
.m0_readdata (sys_description_rom_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sys_description_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sys_description_rom_s1_agent_m0_read), // .read
.m0_waitrequest (sys_description_rom_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sys_description_rom_s1_agent_m0_writedata), // .writedata
.m0_write (sys_description_rom_s1_agent_m0_write), // .write
.rp_endofpacket (sys_description_rom_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sys_description_rom_s1_agent_rp_ready), // .ready
.rp_valid (sys_description_rom_s1_agent_rp_valid), // .valid
.rp_data (sys_description_rom_s1_agent_rp_data), // .data
.rp_startofpacket (sys_description_rom_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sys_description_rom_s1_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (sys_description_rom_s1_cmd_width_adapter_src_valid), // .valid
.cp_data (sys_description_rom_s1_cmd_width_adapter_src_data), // .data
.cp_startofpacket (sys_description_rom_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (sys_description_rom_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (sys_description_rom_s1_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (sys_description_rom_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sys_description_rom_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sys_description_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sys_description_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sys_description_rom_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sys_description_rom_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sys_description_rom_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sys_description_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sys_description_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sys_description_rom_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sys_description_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sys_description_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sys_description_rom_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sys_description_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sys_description_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sys_description_rom_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (3),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sys_description_rom_s1_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sys_description_rom_s1_agent_rf_source_data), // in.data
.in_valid (sys_description_rom_s1_agent_rf_source_valid), // .valid
.in_ready (sys_description_rom_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sys_description_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sys_description_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sys_description_rom_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sys_description_rom_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sys_description_rom_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sys_description_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sys_description_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sw_reset_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sw_reset_s_agent_m0_address), // m0.address
.m0_burstcount (sw_reset_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (sw_reset_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sw_reset_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (sw_reset_s_agent_m0_lock), // .lock
.m0_readdata (sw_reset_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sw_reset_s_agent_m0_read), // .read
.m0_waitrequest (sw_reset_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sw_reset_s_agent_m0_writedata), // .writedata
.m0_write (sw_reset_s_agent_m0_write), // .write
.rp_endofpacket (sw_reset_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sw_reset_s_agent_rp_ready), // .ready
.rp_valid (sw_reset_s_agent_rp_valid), // .valid
.rp_data (sw_reset_s_agent_rp_data), // .data
.rp_startofpacket (sw_reset_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (sw_reset_s_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (sw_reset_s_cmd_width_adapter_src_valid), // .valid
.cp_data (sw_reset_s_cmd_width_adapter_src_data), // .data
.cp_startofpacket (sw_reset_s_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (sw_reset_s_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (sw_reset_s_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (sw_reset_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sw_reset_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sw_reset_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sw_reset_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sw_reset_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sw_reset_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sw_reset_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sw_reset_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sw_reset_s_agent_rf_source_data), // in.data
.in_valid (sw_reset_s_agent_rf_source_valid), // .valid
.in_ready (sw_reset_s_agent_rf_source_ready), // .ready
.in_startofpacket (sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (sw_reset_s_agent_rsp_fifo_out_data), // out.data
.out_valid (sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (sw_reset_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) mem_org_mode_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (mem_org_mode_s_agent_m0_address), // m0.address
.m0_burstcount (mem_org_mode_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (mem_org_mode_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (mem_org_mode_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (mem_org_mode_s_agent_m0_lock), // .lock
.m0_readdata (mem_org_mode_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (mem_org_mode_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (mem_org_mode_s_agent_m0_read), // .read
.m0_waitrequest (mem_org_mode_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (mem_org_mode_s_agent_m0_writedata), // .writedata
.m0_write (mem_org_mode_s_agent_m0_write), // .write
.rp_endofpacket (mem_org_mode_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (mem_org_mode_s_agent_rp_ready), // .ready
.rp_valid (mem_org_mode_s_agent_rp_valid), // .valid
.rp_data (mem_org_mode_s_agent_rp_data), // .data
.rp_startofpacket (mem_org_mode_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (mem_org_mode_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (mem_org_mode_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (mem_org_mode_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (mem_org_mode_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (mem_org_mode_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (mem_org_mode_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (mem_org_mode_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (mem_org_mode_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (mem_org_mode_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (mem_org_mode_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (mem_org_mode_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (mem_org_mode_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (mem_org_mode_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (mem_org_mode_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (mem_org_mode_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (mem_org_mode_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) mem_org_mode_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (mem_org_mode_s_agent_rf_source_data), // in.data
.in_valid (mem_org_mode_s_agent_rf_source_valid), // .valid
.in_ready (mem_org_mode_s_agent_rf_source_ready), // .ready
.in_startofpacket (mem_org_mode_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (mem_org_mode_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (mem_org_mode_s_agent_rsp_fifo_out_data), // out.data
.out_valid (mem_org_mode_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (mem_org_mode_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (mem_org_mode_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (mem_org_mode_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) version_id_0_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (version_id_0_s_agent_m0_address), // m0.address
.m0_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (version_id_0_s_agent_m0_lock), // .lock
.m0_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (version_id_0_s_agent_m0_read), // .read
.m0_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.m0_write (version_id_0_s_agent_m0_write), // .write
.rp_endofpacket (version_id_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (version_id_0_s_agent_rp_ready), // .ready
.rp_valid (version_id_0_s_agent_rp_valid), // .valid
.rp_data (version_id_0_s_agent_rp_data), // .data
.rp_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (version_id_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (version_id_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (version_id_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (version_id_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (version_id_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_0_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_0_s_agent_rf_source_data), // in.data
.in_valid (version_id_0_s_agent_rf_source_valid), // .valid
.in_ready (version_id_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (version_id_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (version_id_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) irq_ena_0_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (irq_ena_0_s_agent_m0_address), // m0.address
.m0_burstcount (irq_ena_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (irq_ena_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (irq_ena_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (irq_ena_0_s_agent_m0_lock), // .lock
.m0_readdata (irq_ena_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (irq_ena_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (irq_ena_0_s_agent_m0_read), // .read
.m0_waitrequest (irq_ena_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (irq_ena_0_s_agent_m0_writedata), // .writedata
.m0_write (irq_ena_0_s_agent_m0_write), // .write
.rp_endofpacket (irq_ena_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (irq_ena_0_s_agent_rp_ready), // .ready
.rp_valid (irq_ena_0_s_agent_rp_valid), // .valid
.rp_data (irq_ena_0_s_agent_rp_data), // .data
.rp_startofpacket (irq_ena_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (irq_ena_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (irq_ena_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (irq_ena_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (irq_ena_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (irq_ena_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (irq_ena_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (irq_ena_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (irq_ena_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (irq_ena_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (irq_ena_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (irq_ena_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (irq_ena_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (irq_ena_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (irq_ena_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (irq_ena_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (irq_ena_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) irq_ena_0_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (irq_ena_0_s_agent_rf_source_data), // in.data
.in_valid (irq_ena_0_s_agent_rf_source_valid), // .valid
.in_ready (irq_ena_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (irq_ena_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (irq_ena_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (irq_ena_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (irq_ena_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (irq_ena_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (irq_ena_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (irq_ena_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router router (
.sink_ready (kernel_cntrl_m0_agent_cp_ready), // sink.ready
.sink_valid (kernel_cntrl_m0_agent_cp_valid), // .valid
.sink_data (kernel_cntrl_m0_agent_cp_data), // .data
.sink_startofpacket (kernel_cntrl_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cntrl_m0_agent_cp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001 router_001 (
.sink_ready (address_span_extender_0_windowed_slave_agent_rp_ready), // sink.ready
.sink_valid (address_span_extender_0_windowed_slave_agent_rp_valid), // .valid
.sink_data (address_span_extender_0_windowed_slave_agent_rp_data), // .data
.sink_startofpacket (address_span_extender_0_windowed_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_windowed_slave_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_002 router_002 (
.sink_ready (address_span_extender_0_cntl_agent_rp_ready), // sink.ready
.sink_valid (address_span_extender_0_cntl_agent_rp_valid), // .valid
.sink_data (address_span_extender_0_cntl_agent_rp_data), // .data
.sink_startofpacket (address_span_extender_0_cntl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_cntl_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_003 router_003 (
.sink_ready (sys_description_rom_s1_agent_rp_ready), // sink.ready
.sink_valid (sys_description_rom_s1_agent_rp_valid), // .valid
.sink_data (sys_description_rom_s1_agent_rp_data), // .data
.sink_startofpacket (sys_description_rom_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sys_description_rom_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_003 router_004 (
.sink_ready (sw_reset_s_agent_rp_ready), // sink.ready
.sink_valid (sw_reset_s_agent_rp_valid), // .valid
.sink_data (sw_reset_s_agent_rp_data), // .data
.sink_startofpacket (sw_reset_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sw_reset_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_005 (
.sink_ready (mem_org_mode_s_agent_rp_ready), // sink.ready
.sink_valid (mem_org_mode_s_agent_rp_valid), // .valid
.sink_data (mem_org_mode_s_agent_rp_data), // .data
.sink_startofpacket (mem_org_mode_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (mem_org_mode_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_006 (
.sink_ready (version_id_0_s_agent_rp_ready), // sink.ready
.sink_valid (version_id_0_s_agent_rp_valid), // .valid
.sink_data (version_id_0_s_agent_rp_data), // .data
.sink_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (version_id_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_007 (
.sink_ready (irq_ena_0_s_agent_rp_ready), // sink.ready
.sink_valid (irq_ena_0_s_agent_rp_valid), // .valid
.sink_data (irq_ena_0_s_agent_rp_data), // .data
.sink_startofpacket (irq_ena_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (irq_ena_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.MAX_OUTSTANDING_RESPONSES (5),
.PIPELINED (0),
.ST_DATA_W (89),
.ST_CHANNEL_W (7),
.VALID_WIDTH (7),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) kernel_cntrl_m0_limiter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (kernel_cntrl_m0_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (kernel_cntrl_m0_limiter_cmd_src_data), // .data
.cmd_src_channel (kernel_cntrl_m0_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (kernel_cntrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (kernel_cntrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (kernel_cntrl_m0_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (kernel_cntrl_m0_limiter_rsp_src_valid), // .valid
.rsp_src_data (kernel_cntrl_m0_limiter_rsp_src_data), // .data
.rsp_src_channel (kernel_cntrl_m0_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (kernel_cntrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (kernel_cntrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (kernel_cntrl_m0_limiter_cmd_valid_data) // cmd_valid.data
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_demux cmd_demux (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cntrl_m0_limiter_cmd_src_ready), // sink.ready
.sink_channel (kernel_cntrl_m0_limiter_cmd_src_channel), // .channel
.sink_data (kernel_cntrl_m0_limiter_cmd_src_data), // .data
.sink_startofpacket (kernel_cntrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cntrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (kernel_cntrl_m0_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux_001 (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (crosser_001_out_ready), // sink0.ready
.sink0_valid (crosser_001_out_valid), // .valid
.sink0_channel (crosser_001_out_channel), // .channel
.sink0_data (crosser_001_out_data), // .data
.sink0_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_001_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_002 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_003 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_004 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_005 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_006 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_src6_valid), // .valid
.sink0_channel (cmd_demux_src6_channel), // .channel
.sink0_data (cmd_demux_src6_data), // .data
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux rsp_demux_001 (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (address_span_extender_0_cntl_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (address_span_extender_0_cntl_rsp_width_adapter_src_channel), // .channel
.sink_data (address_span_extender_0_cntl_rsp_width_adapter_src_data), // .data
.sink_startofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (address_span_extender_0_cntl_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_002 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sys_description_rom_s1_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sys_description_rom_s1_rsp_width_adapter_src_channel), // .channel
.sink_data (sys_description_rom_s1_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sys_description_rom_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sys_description_rom_s1_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sys_description_rom_s1_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_003 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sw_reset_s_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sw_reset_s_rsp_width_adapter_src_channel), // .channel
.sink_data (sw_reset_s_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sw_reset_s_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sw_reset_s_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sw_reset_s_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_004 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_005 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_006 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_mux rsp_mux (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_002_out_ready), // sink0.ready
.sink0_valid (crosser_002_out_valid), // .valid
.sink0_channel (crosser_002_out_channel), // .channel
.sink0_data (crosser_002_out_data), // .data
.sink0_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.sink1_ready (crosser_003_out_ready), // sink1.ready
.sink1_valid (crosser_003_out_valid), // .valid
.sink1_channel (crosser_003_out_channel), // .channel
.sink1_data (crosser_003_out_data), // .data
.sink1_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) address_span_extender_0_cntl_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_001_src_valid), // sink.valid
.in_channel (cmd_mux_001_src_channel), // .channel
.in_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_001_src_ready), // .ready
.in_data (cmd_mux_001_src_data), // .data
.out_endofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (address_span_extender_0_cntl_cmd_width_adapter_src_data), // .data
.out_channel (address_span_extender_0_cntl_cmd_width_adapter_src_channel), // .channel
.out_valid (address_span_extender_0_cntl_cmd_width_adapter_src_valid), // .valid
.out_ready (address_span_extender_0_cntl_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sys_description_rom_s1_cmd_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_002_src_valid), // sink.valid
.in_channel (cmd_mux_002_src_channel), // .channel
.in_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_002_src_ready), // .ready
.in_data (cmd_mux_002_src_data), // .data
.out_endofpacket (sys_description_rom_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sys_description_rom_s1_cmd_width_adapter_src_data), // .data
.out_channel (sys_description_rom_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sys_description_rom_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sys_description_rom_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sys_description_rom_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sw_reset_s_cmd_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_003_src_valid), // sink.valid
.in_channel (cmd_mux_003_src_channel), // .channel
.in_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_003_src_ready), // .ready
.in_data (cmd_mux_003_src_data), // .data
.out_endofpacket (sw_reset_s_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sw_reset_s_cmd_width_adapter_src_data), // .data
.out_channel (sw_reset_s_cmd_width_adapter_src_channel), // .channel
.out_valid (sw_reset_s_cmd_width_adapter_src_valid), // .valid
.out_ready (sw_reset_s_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sw_reset_s_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) address_span_extender_0_cntl_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_002_src_valid), // sink.valid
.in_channel (router_002_src_channel), // .channel
.in_startofpacket (router_002_src_startofpacket), // .startofpacket
.in_endofpacket (router_002_src_endofpacket), // .endofpacket
.in_ready (router_002_src_ready), // .ready
.in_data (router_002_src_data), // .data
.out_endofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (address_span_extender_0_cntl_rsp_width_adapter_src_data), // .data
.out_channel (address_span_extender_0_cntl_rsp_width_adapter_src_channel), // .channel
.out_valid (address_span_extender_0_cntl_rsp_width_adapter_src_valid), // .valid
.out_ready (address_span_extender_0_cntl_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sys_description_rom_s1_rsp_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_003_src_valid), // sink.valid
.in_channel (router_003_src_channel), // .channel
.in_startofpacket (router_003_src_startofpacket), // .startofpacket
.in_endofpacket (router_003_src_endofpacket), // .endofpacket
.in_ready (router_003_src_ready), // .ready
.in_data (router_003_src_data), // .data
.out_endofpacket (sys_description_rom_s1_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sys_description_rom_s1_rsp_width_adapter_src_data), // .data
.out_channel (sys_description_rom_s1_rsp_width_adapter_src_channel), // .channel
.out_valid (sys_description_rom_s1_rsp_width_adapter_src_valid), // .valid
.out_ready (sys_description_rom_s1_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sys_description_rom_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sw_reset_s_rsp_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_004_src_valid), // sink.valid
.in_channel (router_004_src_channel), // .channel
.in_startofpacket (router_004_src_startofpacket), // .startofpacket
.in_endofpacket (router_004_src_endofpacket), // .endofpacket
.in_ready (router_004_src_ready), // .ready
.in_data (router_004_src_data), // .data
.out_endofpacket (sw_reset_s_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sw_reset_s_rsp_width_adapter_src_data), // .data
.out_channel (sw_reset_s_rsp_width_adapter_src_channel), // .channel
.out_valid (sw_reset_s_rsp_width_adapter_src_valid), // .valid
.out_ready (sw_reset_s_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sw_reset_s_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_reset_clk_clk), // in_clk.clk
.in_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (kernel_clk_out_clk_clk), // out_clk.clk
.out_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src0_ready), // in.ready
.in_valid (cmd_demux_src0_valid), // .valid
.in_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.in_channel (cmd_demux_src0_channel), // .channel
.in_data (cmd_demux_src0_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_reset_clk_clk), // in_clk.clk
.in_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (kernel_clk_out_clk_clk), // out_clk.clk
.out_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src1_ready), // in.ready
.in_valid (cmd_demux_src1_valid), // .valid
.in_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.in_channel (cmd_demux_src1_channel), // .channel
.in_data (cmd_demux_src1_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (kernel_clk_out_clk_clk), // in_clk.clk
.in_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_reset_clk_clk), // out_clk.clk
.out_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_src0_ready), // in.ready
.in_valid (rsp_demux_src0_valid), // .valid
.in_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_src0_channel), // .channel
.in_data (rsp_demux_src0_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (kernel_clk_out_clk_clk), // in_clk.clk
.in_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_reset_clk_clk), // out_clk.clk
.out_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_001_src0_ready), // in.ready
.in_valid (rsp_demux_001_src0_valid), // .valid
.in_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_001_src0_channel), // .channel
.in_data (rsp_demux_001_src0_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 9
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xbar_1 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96]" *)
output wire [127 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]" *)
output wire [11 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96]" *)
output wire [127 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12]" *)
output wire [15 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]" *)
input wire [7 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]" *)
input wire [3 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]" *)
output wire [3 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96]" *)
output wire [127 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]" *)
output wire [11 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96]" *)
input wire [127 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]" *)
input wire [7 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]" *)
input wire [3 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]" *)
output wire [3 : 0] m_axi_rready;
axi_crossbar_v2_1_9_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(4),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(256'H0000000043c100000000000043c0000000000000428000000000000040400000),
.C_M_AXI_ADDR_WIDTH(128'H00000010000000100000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(128'H00000001000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(128'H00000001000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(128'H00000001000000010000000100000001),
.C_M_AXI_READ_ISSUING(128'H00000001000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(128'H00000000000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(4'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(4'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(4'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(4'HF),
.m_axi_ruser(4'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
* Copyright 2015, Stephen A. Rodgers. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
// A parallel input shift register clocked on falling edge
`default_nettype none
`timescale 1ns/1ns
// Main test module
module testbench;
reg clk;
reg rstn;
reg datain_ch0;
reg datain_ch1;
reg datain_ch2;
reg datain_ch3;
integer i;
wire serialout;
wire testout0;
wire testout1;
wire testout2;
wire testout3;
root test_root(
.clk(clk),
.rstn(rstn),
.datain_ch0(datain_ch0),
.datain_ch1(datain_ch1),
.datain_ch2(datain_ch2),
.datain_ch3(datain_ch3),
.serialout(serialout),
.testout0(testout0),
.testout1(testout1),
.testout2(testout2),
.testout3(testout3)
);
initial begin
$dumpvars(0, testbench);
clk = 0;
rstn = 0;
datain_ch0 = 0;
datain_ch1 = 0;
datain_ch2 = 0;
datain_ch3 = 0;
#10
rstn = 1;
#5000000
datain_ch1 = 1;
#1090
datain_ch0 = 1;
#610
datain_ch0 = 0;
#8300
datain_ch1 = 0;
//datain_ch0 = 1;
//#2
//datain_ch0 = 0;
#10000000 $finish;
end
always #5 clk = ~clk;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:33:46 01/07/2015
// Design Name: uart
// Module Name: E:/Study/PentiumX/Hardware/PentiumX_OnSoC/test_uart.v
// Project Name: PentiumX_OnSoC
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: uart
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_uart;
// Inputs
reg [31:0] dat_i;
reg [31:0] adr_i;
reg we_i;
reg stb_i;
reg sys_clk;
reg sys_rst;
reg uart_rx;
// Outputs
wire [31:0] dat_o;
wire ack_o;
wire rx_irq;
wire tx_irq;
wire uart_tx;
// Instantiate the Unit Under Test (UUT)
uart uut (
.dat_i(dat_i),
.adr_i(adr_i),
.we_i(we_i),
.stb_i(stb_i),
.dat_o(dat_o),
.ack_o(ack_o),
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.rx_irq(rx_irq),
.tx_irq(tx_irq),
.uart_rx(uart_rx),
.uart_tx(uart_tx)
);
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
initial forever begin
sys_clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) sys_clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
initial begin
// Initialize Inputs
dat_i = 32'h0000_00ff;
adr_i = 0;
we_i = 0;
stb_i = 0;
//sys_clk = 0;
sys_rst = 0;
uart_rx = 0;
// Wait 100 ns for global reset to finish
#100 ;
#100 sys_rst = 1;
#100 sys_rst = 0;
//#100 we_i = 0;
#100 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#100 stb_i = 1;
// Add stimulus here
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_pdl_even.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_pdl_even(/*AUTOARG*/
// Outputs
arbpc0_pcxdp_grant_pa, arbpc0_pcxdp_q0_hold_pa_l,
arbpc0_pcxdp_qsel0_pa, arbpc0_pcxdp_qsel1_pa_l,
arbpc0_pcxdp_shift_px, arbpc2_pcxdp_grant_pa,
arbpc2_pcxdp_q0_hold_pa_l, arbpc2_pcxdp_qsel0_pa,
arbpc2_pcxdp_qsel1_pa_l, arbpc2_pcxdp_shift_px,
// Inputs
arbpc0_pcxdp_grant_bufp1_pa_l, arbpc0_pcxdp_q0_hold_bufp1_pa,
arbpc0_pcxdp_qsel0_bufp1_pa_l, arbpc0_pcxdp_qsel1_bufp1_pa,
arbpc0_pcxdp_shift_bufp1_px_l, arbpc2_pcxdp_grant_bufp1_pa_l,
arbpc2_pcxdp_q0_hold_bufp1_pa, arbpc2_pcxdp_qsel0_bufp1_pa_l,
arbpc2_pcxdp_qsel1_bufp1_pa, arbpc2_pcxdp_shift_bufp1_px_l
);
output arbpc0_pcxdp_grant_pa ;
output arbpc0_pcxdp_q0_hold_pa_l ;
output arbpc0_pcxdp_qsel0_pa ;
output arbpc0_pcxdp_qsel1_pa_l ;
output arbpc0_pcxdp_shift_px ;
output arbpc2_pcxdp_grant_pa ;
output arbpc2_pcxdp_q0_hold_pa_l ;
output arbpc2_pcxdp_qsel0_pa ;
output arbpc2_pcxdp_qsel1_pa_l ;
output arbpc2_pcxdp_shift_px ;
input arbpc0_pcxdp_grant_bufp1_pa_l;
input arbpc0_pcxdp_q0_hold_bufp1_pa;
input arbpc0_pcxdp_qsel0_bufp1_pa_l;
input arbpc0_pcxdp_qsel1_bufp1_pa;
input arbpc0_pcxdp_shift_bufp1_px_l;
input arbpc2_pcxdp_grant_bufp1_pa_l;
input arbpc2_pcxdp_q0_hold_bufp1_pa;
input arbpc2_pcxdp_qsel0_bufp1_pa_l;
input arbpc2_pcxdp_qsel1_bufp1_pa;
input arbpc2_pcxdp_shift_bufp1_px_l;
assign arbpc0_pcxdp_grant_pa = ~arbpc0_pcxdp_grant_bufp1_pa_l;
assign arbpc0_pcxdp_q0_hold_pa_l = ~arbpc0_pcxdp_q0_hold_bufp1_pa;
assign arbpc0_pcxdp_qsel0_pa = ~arbpc0_pcxdp_qsel0_bufp1_pa_l;
assign arbpc0_pcxdp_qsel1_pa_l = ~arbpc0_pcxdp_qsel1_bufp1_pa;
assign arbpc0_pcxdp_shift_px = ~arbpc0_pcxdp_shift_bufp1_px_l;
assign arbpc2_pcxdp_grant_pa = ~arbpc2_pcxdp_grant_bufp1_pa_l;
assign arbpc2_pcxdp_q0_hold_pa_l = ~arbpc2_pcxdp_q0_hold_bufp1_pa;
assign arbpc2_pcxdp_qsel0_pa = ~arbpc2_pcxdp_qsel0_bufp1_pa_l;
assign arbpc2_pcxdp_qsel1_pa_l = ~arbpc2_pcxdp_qsel1_bufp1_pa;
assign arbpc2_pcxdp_shift_px = ~arbpc2_pcxdp_shift_bufp1_px_l;
endmodule
|
/*
Copyright (c) 2015-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream XGMII frame transmitter (AXI in, XGMII out)
*/
module axis_xgmii_tx_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE,
parameter PTP_TAG_WIDTH = 16,
parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* XGMII output
*/
output wire [DATA_WIDTH-1:0] xgmii_txd,
output wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
output wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag,
output wire m_axis_ptp_ts_valid,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
/*
* Status
*/
output wire [1:0] start_packet,
output wire error_underflow
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
end
localparam MIN_FL_NOCRC = MIN_FRAME_LENGTH-4;
localparam MIN_FL_NOCRC_MS = MIN_FL_NOCRC & 16'hfff8;
localparam MIN_FL_NOCRC_LS = MIN_FL_NOCRC & 16'h0007;
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [7:0]
XGMII_IDLE = 8'h07,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PAYLOAD = 3'd1,
STATE_PAD = 3'd2,
STATE_FCS_1 = 3'd3,
STATE_FCS_2 = 3'd4,
STATE_IFG = 3'd5,
STATE_WAIT_END = 3'd6;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg swap_lanes;
reg unswap_lanes;
reg lanes_swapped = 1'b0;
reg [31:0] swap_txd = 32'd0;
reg [3:0] swap_txc = 4'd0;
reg [DATA_WIDTH-1:0] s_axis_tdata_masked;
reg [DATA_WIDTH-1:0] s_tdata_reg = {DATA_WIDTH{1'b0}}, s_tdata_next;
reg [KEEP_WIDTH-1:0] s_tkeep_reg = {KEEP_WIDTH{1'b0}}, s_tkeep_next;
reg [DATA_WIDTH-1:0] fcs_output_txd_0;
reg [DATA_WIDTH-1:0] fcs_output_txd_1;
reg [CTRL_WIDTH-1:0] fcs_output_txc_0;
reg [CTRL_WIDTH-1:0] fcs_output_txc_1;
reg [7:0] ifg_offset;
reg extra_cycle;
reg [15:0] frame_ptr_reg = 16'd0, frame_ptr_next;
reg [7:0] ifg_count_reg = 8'd0, ifg_count_next;
reg [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0, m_axis_ptp_ts_next;
reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0, m_axis_ptp_ts_tag_next;
reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next;
reg m_axis_ptp_ts_valid_int_reg = 1'b0, m_axis_ptp_ts_valid_int_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
wire [31:0] crc_next0;
wire [31:0] crc_next1;
wire [31:0] crc_next2;
wire [31:0] crc_next3;
wire [31:0] crc_next4;
wire [31:0] crc_next5;
wire [31:0] crc_next6;
wire [31:0] crc_next7;
reg [DATA_WIDTH-1:0] xgmii_txd_reg = {CTRL_WIDTH{XGMII_IDLE}}, xgmii_txd_next;
reg [CTRL_WIDTH-1:0] xgmii_txc_reg = {CTRL_WIDTH{1'b1}}, xgmii_txc_next;
reg start_packet_reg = 2'b00, start_packet_next;
reg error_underflow_reg = 1'b0, error_underflow_next;
assign s_axis_tready = s_axis_tready_reg;
assign xgmii_txd = xgmii_txd_reg;
assign xgmii_txc = xgmii_txc_reg;
assign m_axis_ptp_ts = PTP_TS_ENABLE ? m_axis_ptp_ts_reg : 0;
assign m_axis_ptp_ts_tag = PTP_TAG_ENABLE ? m_axis_ptp_ts_tag_reg : 0;
assign m_axis_ptp_ts_valid = PTP_TS_ENABLE || PTP_TAG_ENABLE ? m_axis_ptp_ts_valid_reg : 1'b0;
assign start_packet = start_packet_reg;
assign error_underflow = error_underflow_reg;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(s_tdata_reg[7:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next0)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(16),
.STYLE("AUTO")
)
eth_crc_16 (
.data_in(s_tdata_reg[15:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next1)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(24),
.STYLE("AUTO")
)
eth_crc_24 (
.data_in(s_tdata_reg[23:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next2)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_32 (
.data_in(s_tdata_reg[31:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next3)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(40),
.STYLE("AUTO")
)
eth_crc_40 (
.data_in(s_tdata_reg[39:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next4)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(48),
.STYLE("AUTO")
)
eth_crc_48 (
.data_in(s_tdata_reg[47:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next5)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(56),
.STYLE("AUTO")
)
eth_crc_56 (
.data_in(s_tdata_reg[55:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next6)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(64),
.STYLE("AUTO")
)
eth_crc_64 (
.data_in(s_tdata_reg[63:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next7)
);
function [3:0] keep2count;
input [7:0] k;
casez (k)
8'bzzzzzzz0: keep2count = 4'd0;
8'bzzzzzz01: keep2count = 4'd1;
8'bzzzzz011: keep2count = 4'd2;
8'bzzzz0111: keep2count = 4'd3;
8'bzzz01111: keep2count = 4'd4;
8'bzz011111: keep2count = 4'd5;
8'bz0111111: keep2count = 4'd6;
8'b01111111: keep2count = 4'd7;
8'b11111111: keep2count = 4'd8;
endcase
endfunction
// Mask input data
integer j;
always @* begin
for (j = 0; j < 8; j = j + 1) begin
s_axis_tdata_masked[j*8 +: 8] = s_axis_tkeep[j] ? s_axis_tdata[j*8 +: 8] : 8'd0;
end
end
// FCS cycle calculation
always @* begin
casez (s_tkeep_reg)
8'bzzzzzz01: begin
fcs_output_txd_0 = {{2{XGMII_IDLE}}, XGMII_TERM, ~crc_next0[31:0], s_tdata_reg[7:0]};
fcs_output_txd_1 = {8{XGMII_IDLE}};
fcs_output_txc_0 = 8'b11100000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd3;
extra_cycle = 1'b0;
end
8'bzzzzz011: begin
fcs_output_txd_0 = {XGMII_IDLE, XGMII_TERM, ~crc_next1[31:0], s_tdata_reg[15:0]};
fcs_output_txd_1 = {8{XGMII_IDLE}};
fcs_output_txc_0 = 8'b11000000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd2;
extra_cycle = 1'b0;
end
8'bzzzz0111: begin
fcs_output_txd_0 = {XGMII_TERM, ~crc_next2[31:0], s_tdata_reg[23:0]};
fcs_output_txd_1 = {8{XGMII_IDLE}};
fcs_output_txc_0 = 8'b10000000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd1;
extra_cycle = 1'b0;
end
8'bzzz01111: begin
fcs_output_txd_0 = {~crc_next3[31:0], s_tdata_reg[31:0]};
fcs_output_txd_1 = {{7{XGMII_IDLE}}, XGMII_TERM};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111111;
ifg_offset = 8'd8;
extra_cycle = 1'b1;
end
8'bzz011111: begin
fcs_output_txd_0 = {~crc_next4[23:0], s_tdata_reg[39:0]};
fcs_output_txd_1 = {{6{XGMII_IDLE}}, XGMII_TERM, ~crc_next4[31:24]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111110;
ifg_offset = 8'd7;
extra_cycle = 1'b1;
end
8'bz0111111: begin
fcs_output_txd_0 = {~crc_next5[15:0], s_tdata_reg[47:0]};
fcs_output_txd_1 = {{5{XGMII_IDLE}}, XGMII_TERM, ~crc_next5[31:16]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111100;
ifg_offset = 8'd6;
extra_cycle = 1'b1;
end
8'b01111111: begin
fcs_output_txd_0 = {~crc_next6[7:0], s_tdata_reg[55:0]};
fcs_output_txd_1 = {{4{XGMII_IDLE}}, XGMII_TERM, ~crc_next6[31:8]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11111000;
ifg_offset = 8'd5;
extra_cycle = 1'b1;
end
8'b11111111: begin
fcs_output_txd_0 = s_tdata_reg;
fcs_output_txd_1 = {{3{XGMII_IDLE}}, XGMII_TERM, ~crc_next7[31:0]};
fcs_output_txc_0 = 8'b00000000;
fcs_output_txc_1 = 8'b11110000;
ifg_offset = 8'd4;
extra_cycle = 1'b1;
end
default: begin
fcs_output_txd_0 = {CTRL_WIDTH{XGMII_ERROR}};
fcs_output_txd_1 = {CTRL_WIDTH{XGMII_ERROR}};
fcs_output_txc_0 = {CTRL_WIDTH{1'b1}};
fcs_output_txc_1 = {CTRL_WIDTH{1'b1}};
ifg_offset = 8'd0;
extra_cycle = 1'b1;
end
endcase
end
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
swap_lanes = 1'b0;
unswap_lanes = 1'b0;
frame_ptr_next = frame_ptr_reg;
ifg_count_next = ifg_count_reg;
deficit_idle_count_next = deficit_idle_count_reg;
s_axis_tready_next = 1'b0;
s_tdata_next = s_tdata_reg;
s_tkeep_next = s_tkeep_reg;
m_axis_ptp_ts_next = m_axis_ptp_ts_reg;
m_axis_ptp_ts_tag_next = m_axis_ptp_ts_tag_reg;
m_axis_ptp_ts_valid_next = 1'b0;
m_axis_ptp_ts_valid_int_next = 1'b0;
// XGMII idle
xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
xgmii_txc_next = {CTRL_WIDTH{1'b1}};
start_packet_next = 2'b00;
error_underflow_next = 1'b0;
if (m_axis_ptp_ts_valid_int_reg) begin
m_axis_ptp_ts_valid_next = 1'b1;
if (PTP_TS_WIDTH == 96 && $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000) > 0) begin
// ns field rollover
m_axis_ptp_ts_next[45:16] = $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000);
m_axis_ptp_ts_next[95:48] = m_axis_ptp_ts_reg[95:48] + 1;
end
end
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 16'd8;
reset_crc = 1'b1;
s_axis_tready_next = 1'b1;
// XGMII idle
xgmii_txd_next = {CTRL_WIDTH{XGMII_IDLE}};
xgmii_txc_next = {CTRL_WIDTH{1'b1}};
s_tdata_next = s_axis_tdata_masked;
s_tkeep_next = s_axis_tkeep;
if (s_axis_tvalid) begin
// XGMII start and preamble
if (ifg_count_reg > 8'd0) begin
// need to send more idles - swap lanes
swap_lanes = 1'b1;
if (PTP_TS_WIDTH == 96) begin
m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
m_axis_ptp_ts_next[95:48] = ptp_ts[95:48];
end else begin
m_axis_ptp_ts_next = ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
end
m_axis_ptp_ts_tag_next = s_axis_tuser >> 1;
m_axis_ptp_ts_valid_int_next = 1'b1;
start_packet_next = 2'b10;
end else begin
// no more idles - unswap
unswap_lanes = 1'b1;
if (PTP_TS_WIDTH == 96) begin
m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
m_axis_ptp_ts_next[95:48] = ptp_ts[95:48];
end else begin
m_axis_ptp_ts_next = ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
end
m_axis_ptp_ts_tag_next = s_axis_tuser >> 1;
m_axis_ptp_ts_valid_int_next = 1'b1;
start_packet_next = 2'b01;
end
xgmii_txd_next = {ETH_SFD, {6{ETH_PRE}}, XGMII_START};
xgmii_txc_next = 8'b00000001;
s_axis_tready_next = 1'b1;
state_next = STATE_PAYLOAD;
end else begin
ifg_count_next = 8'd0;
deficit_idle_count_next = 2'd0;
unswap_lanes = 1'b1;
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// transfer payload
update_crc = 1'b1;
s_axis_tready_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd8;
xgmii_txd_next = s_tdata_reg;
xgmii_txc_next = 8'b00000000;
s_tdata_next = s_axis_tdata_masked;
s_tkeep_next = s_axis_tkeep;
if (s_axis_tvalid) begin
if (s_axis_tlast) begin
frame_ptr_next = frame_ptr_reg + keep2count(s_axis_tkeep);
s_axis_tready_next = 1'b0;
if (s_axis_tuser[0]) begin
xgmii_txd_next = {{3{XGMII_IDLE}}, XGMII_TERM, {4{XGMII_ERROR}}};
xgmii_txc_next = 8'b11111111;
frame_ptr_next = 16'd0;
ifg_count_next = 8'd8;
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b0;
if (ENABLE_PADDING && (frame_ptr_reg < MIN_FL_NOCRC_MS || (frame_ptr_reg == MIN_FL_NOCRC_MS && keep2count(s_axis_tkeep) < MIN_FL_NOCRC_LS))) begin
s_tkeep_next = 8'hff;
frame_ptr_next = frame_ptr_reg + 16'd8;
if (frame_ptr_reg < (MIN_FL_NOCRC_LS > 0 ? MIN_FL_NOCRC_MS : MIN_FL_NOCRC_MS-8)) begin
state_next = STATE_PAD;
end else begin
s_tkeep_next = 8'hff >> ((8-MIN_FL_NOCRC_LS) % 8);
state_next = STATE_FCS_1;
end
end else begin
state_next = STATE_FCS_1;
end
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
// tvalid deassert, fail frame
xgmii_txd_next = {{3{XGMII_IDLE}}, XGMII_TERM, {4{XGMII_ERROR}}};
xgmii_txc_next = 8'b11111111;
frame_ptr_next = 16'd0;
ifg_count_next = 8'd8;
error_underflow_next = 1'b1;
state_next = STATE_WAIT_END;
end
end
STATE_PAD: begin
// pad frame to MIN_FRAME_LENGTH
s_axis_tready_next = 1'b0;
xgmii_txd_next = s_tdata_reg;
xgmii_txc_next = {CTRL_WIDTH{1'b0}};
s_tdata_next = 64'd0;
s_tkeep_next = 8'hff;
update_crc = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd8;
if (frame_ptr_reg < (MIN_FL_NOCRC_LS > 0 ? MIN_FL_NOCRC_MS : MIN_FL_NOCRC_MS-8)) begin
state_next = STATE_PAD;
end else begin
s_tkeep_next = 8'hff >> ((8-MIN_FL_NOCRC_LS) % 8);
state_next = STATE_FCS_1;
end
end
STATE_FCS_1: begin
// last cycle
s_axis_tready_next = 1'b0;
xgmii_txd_next = fcs_output_txd_0;
xgmii_txc_next = fcs_output_txc_0;
frame_ptr_next = 16'd0;
ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + (lanes_swapped ? 8'd4 : 8'd0) + deficit_idle_count_reg;
if (extra_cycle) begin
state_next = STATE_FCS_2;
end else begin
state_next = STATE_IFG;
end
end
STATE_FCS_2: begin
// last cycle
s_axis_tready_next = 1'b0;
xgmii_txd_next = fcs_output_txd_1;
xgmii_txc_next = fcs_output_txc_1;
reset_crc = 1'b1;
frame_ptr_next = 16'd0;
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = ifg_count_next - 8'd4;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
end
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end
end
STATE_IFG: begin
// send IFG
if (ifg_count_reg > 8'd8) begin
ifg_count_next = ifg_count_reg - 8'd8;
end else begin
ifg_count_next = 8'd0;
end
reset_crc = 1'b1;
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = ifg_count_next - 8'd4;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
end
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end
end
STATE_WAIT_END: begin
// wait for end of frame
s_axis_tready_next = 1'b1;
if (ifg_count_reg > 8'd8) begin
ifg_count_next = ifg_count_reg - 8'd8;
end else begin
ifg_count_next = 8'd0;
end
reset_crc = 1'b1;
if (s_axis_tvalid) begin
if (s_axis_tlast) begin
s_axis_tready_next = 1'b0;
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = ifg_count_next - 8'd4;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
end
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end
end else begin
state_next = STATE_WAIT_END;
end
end else begin
state_next = STATE_WAIT_END;
end
end
endcase
end
always @(posedge clk) begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
ifg_count_reg <= ifg_count_next;
deficit_idle_count_reg <= deficit_idle_count_next;
s_tdata_reg <= s_tdata_next;
s_tkeep_reg <= s_tkeep_next;
s_axis_tready_reg <= s_axis_tready_next;
m_axis_ptp_ts_reg <= m_axis_ptp_ts_next;
m_axis_ptp_ts_tag_reg <= m_axis_ptp_ts_tag_next;
m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_next;
m_axis_ptp_ts_valid_int_reg <= m_axis_ptp_ts_valid_int_next;
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next7;
end
swap_txd <= xgmii_txd_next[63:32];
swap_txc <= xgmii_txc_next[7:4];
if (swap_lanes || (lanes_swapped && !unswap_lanes)) begin
lanes_swapped <= 1'b1;
xgmii_txd_reg <= {xgmii_txd_next[31:0], swap_txd};
xgmii_txc_reg <= {xgmii_txc_next[3:0], swap_txc};
end else begin
lanes_swapped <= 1'b0;
xgmii_txd_reg <= xgmii_txd_next;
xgmii_txc_reg <= xgmii_txc_next;
end
start_packet_reg <= start_packet_next;
error_underflow_reg <= error_underflow_next;
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 16'd0;
ifg_count_reg <= 8'd0;
deficit_idle_count_reg <= 2'd0;
s_axis_tready_reg <= 1'b0;
m_axis_ptp_ts_valid_reg <= 1'b0;
m_axis_ptp_ts_valid_int_reg <= 1'b0;
xgmii_txd_reg <= {CTRL_WIDTH{XGMII_IDLE}};
xgmii_txc_reg <= {CTRL_WIDTH{1'b1}};
start_packet_reg <= 2'b00;
error_underflow_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
lanes_swapped <= 1'b0;
end
end
endmodule
`resetall
|
//`#start header` -- edit after this line, do not edit this line
// Copyright (C) 2013 Michael McMaster <[email protected]>
//
// This file is part of SCSI2SD.
//
// SCSI2SD is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// SCSI2SD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 10/16/2013 at 00:01
// Component: scsiTarget
module scsiTarget (
output [7:0] DBx_out, // Active High, connected to SCSI bus via inverter
output REQ, // Active High, connected to SCSI bus via inverter
input nACK, // Active LOW, connected directly to SCSI bus.
input [7:0] nDBx_in, // Active LOW, connected directly to SCSI bus.
input nDBP, // Active LOW, connected directly to SCSI bus
input IO, // Active High, set by CPU via status register.
input nRST, // Active LOW, connected directly to SCSI bus.
input clk,
output tx_intr,
output rx_intr,
output parityErr
);
//`#start body` -- edit after this line, do not edit this line
/////////////////////////////////////////////////////////////////////////////
// Force Clock Sync
/////////////////////////////////////////////////////////////////////////////
// The udb_clock_enable primitive component is used to indicate that the input
// clock must always be synchronous and if not implement synchronizers to make
// it synchronous.
wire op_clk;
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync
(
.clock_in(clk),
.enable(1'b1),
.clock_out(op_clk)
);
/////////////////////////////////////////////////////////////////////////////
// CONSTANTS
/////////////////////////////////////////////////////////////////////////////
localparam IO_WRITE = 1'b1;
localparam IO_READ = 1'b0;
/////////////////////////////////////////////////////////////////////////////
// STATE MACHINE
/////////////////////////////////////////////////////////////////////////////
// TX States:
// IDLE
// Wait for the SCSI Initiator to be ready
// FIFOLOAD
// Load F0 into A0. Feed (old) A0 into the ALU SRCA.
// TX
// Load data register from PO. PO is fed by A0 going into the ALU via SRCA
// A0 must remain unchanged.
// DESKEW_INIT
// DBx output signals will be output in this state
// Load deskew clock count into A0 from D0
// DESKEW
// DBx output signals will be output in this state
// Wait for the SCSI deskew time of 55ns. (DEC A0).
// A1 must be fed into SRCA, so PO is now useless.
// READY
// REQ and DBx output signals will be output in this state
// Wait for acknowledgement from the SCSI initiator
// Wait for space in output fifo
// RX
// Dummy state for flow control.
// REQ signal will be output in this state
// PI enabled for input into ALU "PASS" operation, storing into F1.
//
// RX States:
// IDLE
// Wait for a dummy "enabling" entry in the input FIFO,
// and for the SCSI Initiator to be ready
// FIFOLOAD
// Load F0 into A0.
// The input FIFO is used to control the number of bytes we attempt to
// read from the SCSI bus.
// READY
// REQ signal will be output in this state
// Wait for the initiator to send a byte on the SCSI bus.
// Wait for space in output fifo
// RX
// REQ signal will be output in this state
// PI enabled for input into ALU "PASS" operation, storing into F1.
localparam STATE_IDLE = 3'b000;
localparam STATE_FIFOLOAD = 3'b001;
localparam STATE_TX = 3'b010;
localparam STATE_DESKEW_INIT = 3'b011;
localparam STATE_DESKEW = 3'b100;
localparam STATE_WAIT_TIL_READY = 3'b101;
localparam STATE_READY = 3'b110;
localparam STATE_RX = 3'b111;
// state selects the datapath register.
reg[2:0] state;
// Data being read/written from/to the SCSI bus
reg[7:0] data;
// Set by the datapath zero detector (z1). High when A1 counts down to zero.
wire deskewComplete;
// Parallel input to the datapath SRCA.
// Selected for input through to the ALU if CFB EN bit set for the datapath
// state and enabled by PI DYN bit in CFG15-14
wire[7:0] pi;
// Parallel output from the selected SRCA value (A0 or A1) to the ALU.
wire[7:0] po;
// Set true to trigger storing A1 into F1. Set while in STATE_RX
reg fifoStore;
// Set to true on detecting a parity input while reading
reg parityErrReg;
// Temp values in parity calcs. We need to do it in 2 steps to avoid
// timing issues and running-out-of resources
reg[2:0] genParity;
reg REQReg;
// Set Output Pins
assign REQ = REQReg; // STATE_READY & STATE_RX
assign DBx_out[7:0] = data;
assign pi[7:0] = ~nDBx_in[7:0]; // Invert active low scsi bus
assign parityErr = parityErrReg;
/////////////////////////////////////////////////////////////////////////////
// FIFO Status Register
/////////////////////////////////////////////////////////////////////////////
// Status Register: scsiTarget_StatusReg__STATUS_REG
// Bit 0: Tx FIFO not full
// Bit 1: Rx FIFO not empty
// Bit 2: Tx FIFO empty
// Bit 3: Rx FIFO full
// Bit 4: TX Complete. Fifos empty and idle.
//
// TX FIFO Register: scsiTarget_scsiTarget_u0__F0_REG
// RX FIFO Register: scsiTarget_scsiTarget_u0__F1_REG
// Use with CY_GET_REG8 and CY_SET_REG8
wire f0_bus_stat; // Tx FIFO not full
wire f0_blk_stat; // Tx FIFO empty
wire f1_bus_stat; // Rx FIFO not empty
wire f1_blk_stat; // Rx FIFO full
wire txComplete = f0_blk_stat && (state == STATE_IDLE) && nACK;
cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg
(
.clock(op_clk),
.status({3'b0, txComplete, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat})
);
// DMA outputs
//assign tx_intr = f0_bus_stat;
assign tx_intr = f0_blk_stat;
//assign rx_intr = f1_bus_stat;
assign rx_intr = f1_blk_stat;
/////////////////////////////////////////////////////////////////////////////
// State machine
/////////////////////////////////////////////////////////////////////////////
always @(posedge op_clk) begin
case (state)
STATE_IDLE:
begin
if (!nRST) state <= STATE_IDLE;
else if (!f0_blk_stat) // Input FIFO has some data
state <= STATE_FIFOLOAD;
else
state <= STATE_IDLE;
// Clear our output pins
data <= 8'b0;
REQReg <= 1'b0;
fifoStore <= 1'b0;
parityErrReg <= 1'b0;
end
STATE_FIFOLOAD:
if (!nRST) state <= STATE_IDLE;
else if (IO == IO_WRITE)
state <= STATE_TX;
// Check that SCSI initiator is ready, and output FIFO is not full.
else if (nACK && !f1_blk_stat) begin
state <= STATE_READY;
REQReg <= 1'b1;
end else begin
state <= STATE_WAIT_TIL_READY;
end
STATE_TX:
begin
if (!nRST) state <= STATE_IDLE;
else state <= STATE_DESKEW_INIT;
data <= po;
end
STATE_DESKEW_INIT:
if (!nRST) state <= STATE_IDLE;
else state <= STATE_DESKEW;
STATE_DESKEW:
if (!nRST) state <= STATE_IDLE;
else if(deskewComplete && nACK) begin
state <= STATE_READY;
REQReg <= 1'b1;
end else if (deskewComplete) begin
state <= STATE_WAIT_TIL_READY;
end else state <= STATE_DESKEW;
STATE_WAIT_TIL_READY:
if (!nRST) state <= STATE_IDLE;
// Check that SCSI initiator is ready, and output FIFO is not full.
// Note that output FIFO is unused in TX mode.
else if (nACK && ((IO == IO_WRITE) || !f1_blk_stat)) begin
state <= STATE_READY;
REQReg <= 1'b1;
end else begin
state <= STATE_WAIT_TIL_READY;
end
STATE_READY:
if (!nRST) state <= STATE_IDLE;
else if (~nACK) begin
state <= STATE_RX;
fifoStore <= 1'b1;
genParity[0] <= (~nDBP) ^ 1'b1 ^ ~nDBx_in[7] ^ ~nDBx_in[6];
genParity[1] <= ~nDBx_in[5] ^ ~nDBx_in[4] ^ ~nDBx_in[3];
genParity[2] <= ~nDBx_in[2] ^ ~nDBx_in[1] ^ ~nDBx_in[0];
end else state <= STATE_READY;
STATE_RX:
begin
state <= STATE_IDLE;
REQReg <= 1'b0;
fifoStore <= 1'b0;
parityErrReg <= 1'b0;
data <= 8'b0;
if (IO == IO_READ) begin
parityErrReg <= ^genParity[2:0];
end
end
default: state <= STATE_IDLE;
endcase
end
// D0 is used for the deskew count.
// The data output is valid during the DESKEW_INIT phase as well,
// so we subtract 1.
// SCSI-1 deskew + cable skew = 55ns
// D0 = [0.000000055 / (1 / clk)] - 1 = 2
// SCSI-2 FAST deskew + cable skew = 25ns
// D0 = [0.000000025 / (1 / clk)] - 1 = 0
cy_psoc3_dp #(.d0_init(2),
.cy_dpconfig(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: FIFO Load*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: TX*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: DESKEW INIT*/
`CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: DESKEW*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: WAIT TIL READY*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: READY*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: RX*/
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, `SC_PI_DYN_EN,
1'h0, `SC_FIFO1_ALU, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
}
)) datapath(
/* input */ .reset(1'b0),
/* input */ .clk(op_clk),
/* input [02:00] */ .cs_addr(state),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(fifoStore),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(deskewComplete),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(),
/* output */ .f0_bus_stat(f0_bus_stat),
/* output */ .f0_blk_stat(f0_blk_stat),
/* output */ .f1_bus_stat(f1_bus_stat),
/* output */ .f1_blk_stat(f1_blk_stat),
/* input */ .ci(1'b0), // Carry in from previous stage
/* output */ .co(), // Carry out to next stage
/* input */ .sir(1'b0), // Shift in from right side
/* output */ .sor(), // Shift out to right side
/* input */ .sil(1'b0), // Shift in from left side
/* output */ .sol(), // Shift out to left side
/* input */ .msbi(1'b0), // MSB chain in
/* output */ .msbo(), // MSB chain out
/* input [01:00] */ .cei(2'b0), // Compare equal in from prev stage
/* output [01:00] */ .ceo(), // Compare equal out to next stage
/* input [01:00] */ .cli(2'b0), // Compare less than in from prv stage
/* output [01:00] */ .clo(), // Compare less than out to next stage
/* input [01:00] */ .zi(2'b0), // Zero detect in from previous stage
/* output [01:00] */ .zo(), // Zero detect out to next stage
/* input [01:00] */ .fi(2'b0), // 0xFF detect in from previous stage
/* output [01:00] */ .fo(), // 0xFF detect out to next stage
/* input [01:00] */ .capi(2'b0), // Software capture from previous stage
/* output [01:00] */ .capo(), // Software capture to next stage
/* input */ .cfbi(1'b0), // CRC Feedback in from previous stage
/* output */ .cfbo(), // CRC Feedback out to next stage
/* input [07:00] */ .pi(pi), // Parallel data port
/* output [07:00] */ .po(po) // Parallel data port
);
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
|
/*
* support_dma - processes DMA on the support memory
*
* Used for uploading code to the suport CPU
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
module support_dma (
input clk_i,
input enable_i, // When this goes high, it resets the state machine to first state
input d_avail_i, // Goes high when data is available
input [7:0] data_i,
output [15:0] adr_o, // DMA address
output [7:0] data_o,
output wr_o, // To memory
output rd_o, // To SPI
output n_reset_o // To clear the UART before starting
);
// Wire definitions ===========================================================================
// Registers ==================================================================================
reg [2:0] state = 3'd0;
reg [15:0] address = 0;
reg mem_wr = 0;
reg inbound_rd = 0, d_avail = 0;
reg n_reset = 1;
// Assignments ================================================================================
assign rd_o = inbound_rd;
assign data_o = data_i;
assign n_reset_o = n_reset;
//TESTING assign adr_o = {4'b1110,address[11:0]};
assign adr_o = address;
assign wr_o = mem_wr;
// Module connections =========================================================================
always @( posedge clk_i ) d_avail <= d_avail_i; // d_avail is set on negedge
// Simulation branches and control ============================================================
always @(negedge clk_i)
begin
case (state)
0 :begin
address <= 16'd0;
mem_wr <= 0;
inbound_rd <= 0;
if( enable_i ) state <= 3'd1;
end
1 :begin
n_reset <= 0;
state <= 3'd2;
end
2 :begin
n_reset <= 1; // Reset going high will update fifo counters, so wait another step
state <= 3'd3; // For the d_avail_i to be updated
end
3 :begin
if( !enable_i )
state <= 3'd0;
else
if( d_avail )
state <= 3'd4;
end
4 :begin
inbound_rd <= 1'b1; // read takes effect immediately
state <= 3'd5;
end
5 :begin
inbound_rd <= 1'b0;
mem_wr <= 1'b1; // Write only takes effect on next clock posedge
state <= 3'd6;
end
6 :begin
mem_wr <= 1'd0;
state <= 3'd7;
end
7 :begin
address <= address + 1'b1;
state <= 3'd3;
end
default:
state <= 3'd0;
endcase
end
// Other logic ================================================================================
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22OI_SYMBOL_V
`define SKY130_FD_SC_MS__A22OI_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22OI_SYMBOL_V
|
/*
* Copyright (C) 2015 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
*/
`timescale 1ns / 1ps
// 6 clocks
module sincos (input c,
input [25:0] a,
output signed [NBD-1:0] o_cos, o_sin);
parameter NBD = 25;
parameter SIN_EN = 1'b1;
reg [23:0] a0 = 0;
reg [23:0] a1 = 0;
reg s0 = 0;
reg s1 = 0;
// 90 degrees - a, off by one
wire [25:0] a_sin = (SIN_EN << (24)) + ~a;
always @ (posedge c) begin
a0 <= a[24] ? ~ a[23:0] : a[23:0];
a1 <= a_sin[24] ? ~ a_sin[23:0] : a_sin[23:0];
s0 <= a[25] ^ a[24];
s1 <= a_sin[25] ^ a_sin[24];
end
wire [34:0] rd0, rd1;
cosrom cosrom
(.c(c), .a0(a0[23:14]), .a1(a1[23:14]), .d0(rd0), .d1(rd1));
cosine_int #(.NBO(NBD)) cos_0
(.c(c), .a(a0[13:0]), .rom_d(rd0), .s(s0), .o(o_cos));
cosine_int #(.NBO(NBD)) cos_1
(.c(c), .a(a1[13:0]), .rom_d(rd1), .s(s1), .o(o_sin));
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
`timescale 1ps/1ps
module DSP48E1 (
ACOUT,
BCOUT,
CARRYCASCOUT,
CARRYOUT,
MULTSIGNOUT,
OVERFLOW,
P,
PATTERNBDETECT,
PATTERNDETECT,
PCOUT,
UNDERFLOW,
A,
ACIN,
ALUMODE,
B,
BCIN,
C,
CARRYCASCIN,
CARRYIN,
CARRYINSEL,
CEA1,
CEA2,
CEAD,
CEALUMODE,
CEB1,
CEB2,
CEC,
CECARRYIN,
CECTRL,
CED,
CEINMODE,
CEM,
CEP,
CLK,
D,
INMODE,
MULTSIGNIN,
OPMODE,
PCIN,
RSTA,
RSTALLCARRYIN,
RSTALUMODE,
RSTB,
RSTC,
RSTCTRL,
RSTD,
RSTINMODE,
RSTM,
RSTP);
parameter ACASCREG = 1;
parameter ADREG = 1;
parameter ALUMODEREG = 1;
parameter AREG = 1;
parameter AUTORESET_PATDET = "NO_RESET";
parameter A_INPUT = "DIRECT";
parameter BCASCREG = 1;
parameter BREG = 1;
parameter B_INPUT = "DIRECT";
parameter CARRYINREG = 1;
parameter CARRYINSELREG = 1;
parameter CREG = 1;
parameter DREG = 1;
parameter INMODEREG = 1;
parameter MASK = 'h3fffffffffff;
parameter MREG = 1;
parameter OPMODEREG = 1;
parameter PATTERN = 0;
parameter PREG = 1;
parameter SEL_MASK = "MASK";
parameter SEL_PATTERN = "PATTERN";
parameter USE_DPORT = 0;
parameter USE_MULT = "MULTIPLY";
parameter USE_PATTERN_DETECT = "NO_PATDET";
parameter USE_SIMD = "ONE48";
output [29:0] ACOUT;
output [17:0] BCOUT;
output CARRYCASCOUT;
output [ 3:0] CARRYOUT;
output MULTSIGNOUT;
output OVERFLOW;
output [47:0] P;
output PATTERNBDETECT;
output PATTERNDETECT;
output [47:0] PCOUT;
output UNDERFLOW;
input [29:0] A;
input [29:0] ACIN;
input [ 3:0] ALUMODE;
input [17:0] B;
input [17:0] BCIN;
input [47:0] C;
input CARRYCASCIN;
input CARRYIN;
input [ 2:0] CARRYINSEL;
input CEA1;
input CEA2;
input CEAD;
input CEALUMODE;
input CEB1;
input CEB2;
input CEC;
input CECARRYIN;
input CECTRL;
input CED;
input CEINMODE;
input CEM;
input CEP;
input CLK;
input [24:0] D;
input [ 4:0] INMODE;
input MULTSIGNIN;
input [ 6:0] OPMODE;
input [47:0] PCIN;
input RSTA;
input RSTALLCARRYIN;
input RSTALUMODE;
input RSTB;
input RSTC;
input RSTCTRL;
input RSTD;
input RSTINMODE;
input RSTM;
input RSTP;
assign ACOUT = 30'd0;
assign BCOUT = 18'd0;
assign CARRYCASCOUT = 1'd0;
assign CARRYOUT = 4'd0;
assign MULTSIGNOUT = 1'd0;
assign OVERFLOW = 1'd0;
assign P = 48'd0;
assign PATTERNBDETECT = 1'd0;
assign PATTERNDETECT = 1'd0;
assign PCOUT = 48'd0;
assign UNDERFLOW = 1'd0;
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Wed Apr 13 17:20:49 2016
// Host : Dries007-Arch running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/FiFo/FiFo_stub.v
// Design : FiFo
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_0_1,Vivado 2015.4" *)
module FiFo(clk, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,din[7:0],wr_en,rd_en,dout[7:0],full,empty" */;
input clk;
input [7:0]din;
input wr_en;
input rd_en;
output [7:0]dout;
output full;
output empty;
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Fetch - Instantiates the fetch stage sub-modules of //
// the Amber 2 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Instantiates the Cache and Wishbone I/F //
// Also contains a little bit of logic to decode memory //
// accesses to decide if they are cached or not //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a23_fetch
(
input i_clk,
input [31:0] i_address,
input i_address_valid,
input [31:0] i_address_nxt, // un-registered version of address to the cache rams
input [31:0] i_write_data,
input i_write_enable,
output [31:0] o_read_data,
input i_priviledged,
input i_exclusive, // high for read part of swap access
input [3:0] i_byte_enable,
input i_data_access, // high for data petch, low for instruction fetch
input i_cache_enable, // cache enable
input i_cache_flush, // cache flush
input [31:0] i_cacheable_area, // each bit corresponds to 2MB address space
input i_system_rdy,
output o_fetch_stall, // when this is asserted all registers
// in all 3 pipeline stages are held
// at their current values
// Wishbone Master I/F
output [31:0] o_wb_adr,
output [3:0] o_wb_sel,
output o_wb_we,
input [31:0] i_wb_dat,
output [31:0] o_wb_dat,
output o_wb_cyc,
output o_wb_stb,
input i_wb_ack,
input i_wb_err
);
//`include "memory_configuration.vh"
function in_cachable_mem;
input [31:0] address;
begin
in_cachable_mem = 1'b0 ;
end
endfunction
wire cache_stall;
wire wb_stall;
wire [31:0] cache_read_data;
wire sel_cache;
wire sel_wb;
wire cache_wb_req;
wire address_cachable;
// ======================================
// Memory Decode
// ======================================
assign address_cachable = in_cachable_mem( i_address ) && i_cacheable_area[i_address[25:21]];
assign sel_cache = address_cachable && i_address_valid && i_cache_enable && !i_exclusive;
// Don't start wishbone transfers when the cache is stalling the core
// The cache stalls the core during its initialization sequence
assign sel_wb = !sel_cache && i_address_valid && !(cache_stall);
// Return read data either from the wishbone bus or the cache
assign o_read_data = sel_cache ? cache_read_data :
sel_wb ? i_wb_dat :
32'hffeeddcc ;
// Stall the instruction decode and execute stages of the core
// when the fetch stage needs more than 1 cycle to return the requested
// read data
assign o_fetch_stall = !i_system_rdy || wb_stall || cache_stall;
// ======================================
// L1 Cache (Unified Instruction and Data)
// ======================================
a23_cache u_cache (
.i_clk ( i_clk ),
.i_select ( sel_cache ),
.i_exclusive ( i_exclusive ),
.i_write_data ( i_write_data ),
.i_write_enable ( i_write_enable ),
.i_address ( i_address ),
.i_address_nxt ( i_address_nxt ),
.i_byte_enable ( i_byte_enable ),
.i_cache_enable ( i_cache_enable ),
.i_cache_flush ( i_cache_flush ),
.o_read_data ( cache_read_data ),
.o_stall ( cache_stall ),
.i_core_stall ( o_fetch_stall ),
.o_wb_req ( cache_wb_req ),
.i_wb_address ( o_wb_adr ),
.i_wb_read_data ( i_wb_dat ),
.i_wb_stall ( o_wb_stb & ~i_wb_ack )
);
// ======================================
// Wishbone Master I/F
// ======================================
a23_wishbone u_wishbone (
// CPU Side
.i_clk ( i_clk ),
// Core Accesses to Wishbone bus
.i_select ( sel_wb ),
.i_write_data ( i_write_data ),
.i_write_enable ( i_write_enable ),
.i_byte_enable ( i_byte_enable ),
.i_data_access ( i_data_access ),
.i_exclusive ( i_exclusive ),
.i_address ( i_address ),
.o_stall ( wb_stall ),
// Cache Accesses to Wishbone bus
// L1 Cache enable - used for hprot
.i_cache_req ( cache_wb_req ),
.o_wb_adr ( o_wb_adr ),
.o_wb_sel ( o_wb_sel ),
.o_wb_we ( o_wb_we ),
.i_wb_dat ( i_wb_dat ),
.o_wb_dat ( o_wb_dat ),
.o_wb_cyc ( o_wb_cyc ),
.o_wb_stb ( o_wb_stb ),
.i_wb_ack ( i_wb_ack ),
.i_wb_err ( i_wb_err )
);
endmodule
|
`timescale 1ns/1ps
`include "../global.v"
module FPU_top_tb();
reg clk, reset;
reg [3:0] opCode;
reg [1:0] roundingMode;
reg [31:0] A;
reg [31:0] B;
reg [31:0] ER; //expected result
wire resultReady;
wire [31:0] result;
wire invalidOperation, divisionByZero, overflow, underflow, inexact;
integer file;
integer mulVectorCount = 100;
integer addVectorCount = 100;
integer subVectorCount = 100;
integer divVectorCount = 200;
fpu_top inst_fpu_top
(
.clk_in (clk),
.reset_in (reset_in),
.fpuOpCode_in (opCode),
.roundingMode_in (roundingMode),
.operandA_in (A),
.operandB_in (B),
.resultReady_out (resultReady),
.result_out (result),
.invalidOperation_out (invalidOperation),
.divisionByZero_out (divisionByZero),
.overflow_out (overflow),
.underflow_out (underflow),
.inexact_out (inexact)
);
//clock
parameter HCP = 10;
initial forever begin
#HCP clk = ~clk;
end
initial begin
clk = 1'b0;
reset = 1'b1;
$display("---------------- Mul automated testbench ----------------");
opCode = `FPU_INSTR_MUL;
$display("Round towards zero");
roundingMode = `ROUNDING_MODE_TRUNCATE;
file = $fopen("test/mul/trunc/mul-vectors-p-p.txt", "r"); runSingleFile(file, mulVectorCount);
file = $fopen("test/mul/trunc/mul-vectors-p-n.txt", "r"); runSingleFile(file, mulVectorCount);
file = $fopen("test/mul/trunc/mul-vectors-n-p.txt", "r"); runSingleFile(file, mulVectorCount);
file = $fopen("test/mul/trunc/mul-vectors-n-n.txt", "r"); runSingleFile(file, mulVectorCount);
$display("Round towards +Inf");
roundingMode = `ROUNDING_MODE_POS_INF;
file = $fopen("test/mul/pinf/mul-vectors-p-p.txt", "r"); runSingleFile(file, mulVectorCount);
file = $fopen("test/mul/pinf/mul-vectors-p-n.txt", "r"); runSingleFile(file, mulVectorCount);
file = $fopen("test/mul/pinf/mul-vectors-n-p.txt", "r"); runSingleFile(file, mulVectorCount);
file = $fopen("test/mul/pinf/mul-vectors-n-n.txt", "r"); runSingleFile(file, mulVectorCount);
$display("Round towards -Inf");
roundingMode = `ROUNDING_MODE_NEG_INF;
file = $fopen("test/mul/ninf/mul-vectors-p-p.txt", "r"); runSingleFile(file, mulVectorCount);
file = $fopen("test/mul/ninf/mul-vectors-p-n.txt", "r"); runSingleFile(file, mulVectorCount);
file = $fopen("test/mul/ninf/mul-vectors-n-p.txt", "r"); runSingleFile(file, mulVectorCount);
file = $fopen("test/mul/ninf/mul-vectors-n-n.txt", "r"); runSingleFile(file, mulVectorCount);
/*$display("Round towards nearest event");
roundingMode = `ROUNDING_MODE_NEAREST_EVEN;
file = $fopen("test/mul/nearest/mul-vectors-p-p.txt", "r"); runSingleFile(file, mulVectorCount);
file = $fopen("test/mul/nearest/mul-vectors-p-n.txt", "r"); runSingleFile(file, mulVectorCount);
file = $fopen("test/mul/nearest/mul-vectors-n-p.txt", "r"); runSingleFile(file, mulVectorCount);
file = $fopen("test/mul/nearest/mul-vectors-n-n.txt", "r"); runSingleFile(file, mulVectorCount);*/
$display("---------------- Add/Sub automatic testbench ----------------");
$display("Add:");
opCode = `FPU_INSTR_ADD;
$display("Round towards zero");
roundingMode = `ROUNDING_MODE_TRUNCATE;
file = $fopen("test/add/trunc/add-vectors-p-p.txt", "r"); runSingleFile(file, addVectorCount);
file = $fopen("test/add/trunc/add-vectors-p-n.txt", "r"); runSingleFile(file, addVectorCount);
file = $fopen("test/add/trunc/add-vectors-n-p.txt", "r"); runSingleFile(file, addVectorCount);
file = $fopen("test/add/trunc/add-vectors-n-n.txt", "r"); runSingleFile(file, addVectorCount);
$display("Round towards +Inf");
roundingMode = `ROUNDING_MODE_POS_INF;
file = $fopen("test/add/pinf/add-vectors-p-p.txt", "r"); runSingleFile(file, addVectorCount);
file = $fopen("test/add/pinf/add-vectors-p-n.txt", "r"); runSingleFile(file, addVectorCount);
file = $fopen("test/add/pinf/add-vectors-n-p.txt", "r"); runSingleFile(file, addVectorCount);
file = $fopen("test/add/pinf/add-vectors-n-n.txt", "r"); runSingleFile(file, addVectorCount);
$display("Round towards -Inf");
roundingMode = `ROUNDING_MODE_NEG_INF;
file = $fopen("test/add/ninf/add-vectors-p-p.txt", "r"); runSingleFile(file, addVectorCount);
file = $fopen("test/add/ninf/add-vectors-p-n.txt", "r"); runSingleFile(file, addVectorCount);
file = $fopen("test/add/ninf/add-vectors-n-p.txt", "r"); runSingleFile(file, addVectorCount);
file = $fopen("test/add/ninf/add-vectors-n-n.txt", "r"); runSingleFile(file, addVectorCount);
/*$display("Round towards nearest even");
roundingMode = `ROUNDING_MODE_NEAREST_EVEN;
file = $fopen("test/add/nearest/add-vectors-p-p.txt", "r"); runSingleFile(file, addVectorCount);
file = $fopen("test/add/nearest/add-vectors-p-n.txt", "r"); runSingleFile(file, addVectorCount);
file = $fopen("test/add/nearest/add-vectors-n-p.txt", "r"); runSingleFile(file, addVectorCount);
file = $fopen("test/add/nearest/add-vectors-n-n.txt", "r"); runSingleFile(file, addVectorCount);
*/
$display("----------------");
$display("Sub:");
opCode = `FPU_INSTR_SUB;
$display("Round towards zero");
roundingMode = `ROUNDING_MODE_TRUNCATE;
file = $fopen("test/sub/trunc/sub-vectors-p-p.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/sub/trunc/sub-vectors-p-n.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/sub/trunc/sub-vectors-n-p.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/sub/trunc/sub-vectors-n-n.txt", "r"); runSingleFile(file, subVectorCount);
$display("Round towards +Inf");
roundingMode = `ROUNDING_MODE_POS_INF;
file = $fopen("test/sub/pinf/sub-vectors-p-p.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/sub/pinf/sub-vectors-p-n.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/sub/pinf/sub-vectors-n-p.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/sub/pinf/sub-vectors-n-n.txt", "r"); runSingleFile(file, subVectorCount);
$display("Round towards -Inf");
roundingMode = `ROUNDING_MODE_NEG_INF;
file = $fopen("test/sub/ninf/sub-vectors-p-p.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/sub/ninf/sub-vectors-p-n.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/sub/ninf/sub-vectors-n-p.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/sub/ninf/sub-vectors-n-n.txt", "r"); runSingleFile(file, subVectorCount);
/*$display("Round towards nearest event");
roundingMode = `ROUNDING_MODE_NEAREST_EVEN;
file = $fopen("test/sub/nearest/sub-vectors-p-p.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/sub/nearest/sub-vectors-p-n.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/sub/nearest/sub-vectors-n-p.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/sub/nearest/sub-vectors-n-n.txt", "r"); runSingleFile(file, subVectorCount);
*/
$display("---------------- DIV automatic testbench ----------------");
opCode = `FPU_INSTR_DIV;
$display("Round towards zero");
roundingMode = `ROUNDING_MODE_TRUNCATE;
file = $fopen("test/div/trunc/div-vectors-p-p.txt", "r"); runSingleFile(file, 1);
file = $fopen("test/div/trunc/div-vectors-p-n.txt", "r"); runSingleFile(file, divVectorCount);
file = $fopen("test/div/trunc/div-vectors-n-p.txt", "r"); runSingleFile(file, divVectorCount);
file = $fopen("test/div/trunc/div-vectors-n-n.txt", "r"); runSingleFile(file, divVectorCount);
/*$display("Round towards +Inf");
roundingMode = `ROUNDING_MODE_POS_INF;
file = $fopen("test/div/pinf/div-vectors-p-p.txt", "r"); runSingleFile(file, divVectorCount);
file = $fopen("test/div/pinf/div-vectors-p-n.txt", "r"); runSingleFile(file, divVectorCount);
file = $fopen("test/div/pinf/div-vectors-n-p.txt", "r"); runSingleFile(file, divVectorCount);
file = $fopen("test/div/pinf/div-vectors-n-n.txt", "r"); runSingleFile(file, divVectorCount);
$display("Round towards -Inf");
roundingMode = `ROUNDING_MODE_NEG_INF;
file = $fopen("test/div/ninf/div-vectors-p-p.txt", "r"); runSingleFile(file, divVectorCount);
file = $fopen("test/div/ninf/div-vectors-p-n.txt", "r"); runSingleFile(file, divVectorCount);
file = $fopen("test/div/ninf/div-vectors-n-p.txt", "r"); runSingleFile(file, divVectorCount);
file = $fopen("test/div/ninf/div-vectors-n-n.txt", "r"); runSingleFile(file, divVectorCount); */
/*$display("Round towards nearest event");
roundingMode = `ROUNDING_MODE_NEAREST_EVEN;
file = $fopen("test/div/nearest/div-vectors-p-p.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/div/nearest/div-vectors-p-n.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/div/nearest/div-vectors-n-p.txt", "r"); runSingleFile(file, subVectorCount);
file = $fopen("test/div/nearest/div-vectors-n-n.txt", "r"); runSingleFile(file, subVectorCount);
*/
$display("----------------");
#20
$finish;
end
task runSingleFile;
input integer file;
input integer vectorCount;
integer status, cnt, errorCount;
begin
cnt = 0;
errorCount = 0;
while (cnt < vectorCount) begin
status = $fscanf(file, "%x\t%x\t%x\n", A[31:0], B[31:0], ER[31:0]);
#(2*HCP) reset = 1'b0;
@(posedge resultReady) #1;
if (ER !== result) begin
$display("Vector %d: Wrong result!", cnt);
$display("A: %b\t%x\t%b\n", A[31], A[30:23], A[22:0]);
$display("B: %b\t%x\t%b\n", B[31], B[30:23], B[22:0]);
$display("ER: %b\t%x\t%b\n", ER[31], ER[30:23], ER[22:0]);
$display("R: %b\t%x\t%b\n", result[31], result[30:23], result[22:0]);
errorCount = errorCount + 1;
end else begin
/*$display("Vector %d: Correct result", cnt);
$display("A: %b\t%x\t%b\n", A[31], A[30:23], A[22:0]);
$display("B: %b\t%x\t%b\n", B[31], B[30:23], B[22:0]);
$display("ER: %b\t%x\t%b\n", ER[31], ER[30:23], ER[22:0]);
$display("R: %b\t%x\t%b\n", result[31], result[30:23], result[22:0]);*/
end
reset = 1'b1;
cnt = cnt + 1;
end
$display("Finished, %d vectors simulated, %d error(s)", cnt, errorCount);
$fclose(file);
end
endtask
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2015 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Application : Vivado HLS
// / / Filename: tb_multiSRC_onboard.v
// /___/ /\ Timestamp: Tue May 12 5:00:00 PST 2015
// \ \ / \
// \___\/\___\
//
//Command: N/A
//Device: 7K325T-2
//Design Name: multiSRC
//Purpose:
// This file is the functional verification testbench for the multiSRC
// onboard test.
//Reference:
// XAPP1236
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module tb_multiSRC_onboard;
parameter CLKCYCLE = 4;
reg test_start;
wire test_done;
wire test_pass;
reg clk;
reg rst;
integer i;
wire ap_start;
wire ap_ready;
wire ap_idle;
wire ap_done;
wire dut_rst;
wire vld_x;
wire vld_y;
wire [15:0] x;
wire [2:0] rat;
wire [47:0] y;
//-----------------------------------
// generate clock and reset
//-----------------------------------
initial begin
clk=1'b0;
rst=1'b1;
#14;
@(posedge clk);
@(posedge clk);
@(posedge clk);
rst=1'b0;
end
//---- clock gen -------------------
always
#(CLKCYCLE/2) clk = ~clk;
//----------------------------------
initial begin
test_start=1'b0;
#30;
test_start=1'b1;
#100;
test_start=1'b0;
for(i=0;i< (2048+8192);i=i+1) begin
@(posedge clk);
end
test_start=1'b1;
#100;
test_start=1'b0;
end
test_bench_onboard TB
(
.clk(clk),
.rst(rst),
.test_start(test_start),
.test_done(test_done),
.test_pass(test_pass),
.ap_ready(ap_ready),
.ap_idle(ap_idle),
.ap_done(ap_done),
.dut_vld_y(vld_y),
.dut_y(y),
.dut_rst(dut_rst),
.dut_start(ap_start),
.dut_vld_x(vld_x),
.dut_x(x),
.dut_rat(rat)
);
multiSRC DUT(
.ap_clk(clk),
.ap_rst(dut_rst),
.ap_start(ap_start),
.ap_done(ap_done),
.ap_idle(ap_idle),
.ap_ready(ap_ready),
.vld_i(vld_x),
.x_i_V(x),
.rat_i_V(rat),
.vld_o(vld_y),
.y_o_V(y)
);
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram (
address,
byteena,
clock,
data,
rden,
wren,
q);
input [9:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input rden;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.rden_a (rden),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_addr_cmd_datapath(
clk,
reset_n,
afi_address,
afi_bank,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_rst_n,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_reset_n,
phy_ddio_odt
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter NUM_AC_FR_CYCLE_SHIFTS = "";
localparam RATE_MULT = 2;
input reset_n;
input clk;
input [AFI_ADDRESS_WIDTH-1:0] afi_address;
input [AFI_BANK_WIDTH-1:0] afi_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [AFI_CONTROL_WIDTH-1:0] afi_rst_n;
output [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
output [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
output [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
output [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
output [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
wire [AFI_ADDRESS_WIDTH-1:0] afi_address_r = afi_address;
wire [AFI_BANK_WIDTH-1:0] afi_bank_r = afi_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n_r = afi_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] afi_cke_r = afi_cke;
wire [AFI_ODT_WIDTH-1:0] afi_odt_r = afi_odt;
wire [AFI_CONTROL_WIDTH-1:0] afi_ras_n_r = afi_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_cas_n_r = afi_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_we_n_r = afi_we_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_rst_n_r = afi_rst_n;
wire [1:0] shift_fr_cycle =
(NUM_AC_FR_CYCLE_SHIFTS == 0) ? 2'b00 : (
(NUM_AC_FR_CYCLE_SHIFTS == 1) ? 2'b01 : (
(NUM_AC_FR_CYCLE_SHIFTS == 2) ? 2'b10 : (
2'b11 )));
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_fr_cycle_shifter uaddr_cmd_shift_address(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_address_r),
.dataout (phy_ddio_address)
);
defparam uaddr_cmd_shift_address.DATA_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_shift_address.REG_POST_RESET_HIGH = "false";
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_fr_cycle_shifter uaddr_cmd_shift_bank(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_bank_r),
.dataout (phy_ddio_bank)
);
defparam uaddr_cmd_shift_bank.DATA_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_shift_bank.REG_POST_RESET_HIGH = "false";
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_fr_cycle_shifter uaddr_cmd_shift_cke(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cke_r),
.dataout (phy_ddio_cke)
);
defparam uaddr_cmd_shift_cke.DATA_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_shift_cke.REG_POST_RESET_HIGH = "false";
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_fr_cycle_shifter uaddr_cmd_shift_cs_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cs_n_r),
.dataout (phy_ddio_cs_n)
);
defparam uaddr_cmd_shift_cs_n.DATA_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_shift_cs_n.REG_POST_RESET_HIGH = "true";
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_fr_cycle_shifter uaddr_cmd_shift_odt(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_odt_r),
.dataout (phy_ddio_odt)
);
defparam uaddr_cmd_shift_odt.DATA_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_shift_odt.REG_POST_RESET_HIGH = "false";
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_fr_cycle_shifter uaddr_cmd_shift_ras_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_ras_n_r),
.dataout (phy_ddio_ras_n)
);
defparam uaddr_cmd_shift_ras_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_ras_n.REG_POST_RESET_HIGH = "true";
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_fr_cycle_shifter uaddr_cmd_shift_cas_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cas_n_r),
.dataout (phy_ddio_cas_n)
);
defparam uaddr_cmd_shift_cas_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_cas_n.REG_POST_RESET_HIGH = "true";
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_fr_cycle_shifter uaddr_cmd_shift_we_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_we_n_r),
.dataout (phy_ddio_we_n)
);
defparam uaddr_cmd_shift_we_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_we_n.REG_POST_RESET_HIGH = "true";
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_fr_cycle_shifter uaddr_cmd_shift_rst_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_rst_n_r),
.dataout (phy_ddio_reset_n)
);
defparam uaddr_cmd_shift_rst_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_rst_n.REG_POST_RESET_HIGH = "true";
endmodule
|
// lpddr2_cntrlr_0002.v
// This file was auto-generated from alt_mem_if_lpddr2_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module lpddr2_cntrlr_0002 (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire afi_clk, // afi_clk.clk
output wire afi_half_clk, // afi_half_clk.clk
output wire afi_reset_n, // afi_reset.reset_n
output wire afi_reset_export_n, // afi_reset_export.reset_n
output wire [9:0] mem_ca, // memory.mem_ca
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire avl_ready_0, // avl_0.waitrequest_n
input wire avl_burstbegin_0, // .beginbursttransfer
input wire [26:0] avl_addr_0, // .address
output wire avl_rdata_valid_0, // .readdatavalid
output wire [31:0] avl_rdata_0, // .readdata
input wire [31:0] avl_wdata_0, // .writedata
input wire [3:0] avl_be_0, // .byteenable
input wire avl_read_req_0, // .read
input wire avl_write_req_0, // .write
input wire [2:0] avl_size_0, // .burstcount
input wire mp_cmd_clk_0_clk, // mp_cmd_clk_0.clk
input wire mp_cmd_reset_n_0_reset_n, // mp_cmd_reset_n_0.reset_n
input wire mp_rfifo_clk_0_clk, // mp_rfifo_clk_0.clk
input wire mp_rfifo_reset_n_0_reset_n, // mp_rfifo_reset_n_0.reset_n
input wire mp_wfifo_clk_0_clk, // mp_wfifo_clk_0.clk
input wire mp_wfifo_reset_n_0_reset_n, // mp_wfifo_reset_n_0.reset_n
output wire local_init_done, // status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
input wire oct_rzqin, // oct.rzqin
output wire pll_mem_clk, // pll_sharing.pll_mem_clk
output wire pll_write_clk, // .pll_write_clk
output wire pll_locked, // .pll_locked
output wire pll_write_clk_pre_phy_clk, // .pll_write_clk_pre_phy_clk
output wire pll_addr_cmd_clk, // .pll_addr_cmd_clk
output wire pll_avl_clk, // .pll_avl_clk
output wire pll_config_clk, // .pll_config_clk
output wire pll_mem_phy_clk, // .pll_mem_phy_clk
output wire afi_phy_clk, // .afi_phy_clk
output wire pll_avl_phy_clk // .pll_avl_phy_clk
);
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_avl_clk_clk; // p0:avl_clk -> s0:avl_clk
wire p0_avl_reset_reset; // p0:avl_reset_n -> s0:avl_reset_n
wire p0_scc_clk_clk; // p0:scc_clk -> s0:scc_clk
wire p0_scc_reset_reset; // p0:scc_reset_n -> s0:reset_n_scc_clk
wire [31:0] s0_scc_scc_dq_ena; // s0:scc_dq_ena -> p0:scc_dq_ena
wire [0:0] s0_scc_scc_upd; // s0:scc_upd -> p0:scc_upd
wire [3:0] s0_scc_scc_dqs_io_ena; // s0:scc_dqs_io_ena -> p0:scc_dqs_io_ena
wire [3:0] s0_scc_scc_dm_ena; // s0:scc_dm_ena -> p0:scc_dm_ena
wire [3:0] p0_scc_capture_strobe_tracking; // p0:capture_strobe_tracking -> s0:capture_strobe_tracking
wire [3:0] s0_scc_scc_dqs_ena; // s0:scc_dqs_ena -> p0:scc_dqs_ena
wire [0:0] s0_scc_scc_data; // s0:scc_data -> p0:scc_data
wire [0:0] s0_tracking_afi_seq_busy; // s0:afi_seq_busy -> c0:afi_seq_busy
wire [31:0] s0_avl_readdata; // p0:avl_readdata -> s0:avl_readdata
wire s0_avl_waitrequest; // p0:avl_waitrequest -> s0:avl_waitrequest
wire [15:0] s0_avl_address; // s0:avl_address -> p0:avl_address
wire s0_avl_read; // s0:avl_read -> p0:avl_read
wire s0_avl_write; // s0:avl_write -> p0:avl_write
wire [31:0] s0_avl_writedata; // s0:avl_writedata -> p0:avl_writedata
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire c0_afi_afi_init_req; // c0:afi_init_req -> s0:afi_init_req
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [0:0] c0_afi_afi_ctl_refresh_done; // c0:afi_ctl_refresh_done -> s0:afi_ctl_refresh_done
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire c0_afi_afi_cal_req; // c0:afi_cal_req -> s0:afi_cal_req
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [0:0] c0_afi_afi_ctl_long_idle; // c0:afi_ctl_long_idle -> s0:afi_ctl_long_idle
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire [15:0] oct0_oct_sharing_parallelterminationcontrol; // oct0:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct0_oct_sharing_seriesterminationcontrol; // oct0:seriesterminationcontrol -> p0:seriesterminationcontrol
wire p0_dll_clk_clk; // p0:dll_clk -> dll0:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll0:dll_pll_locked
wire [6:0] dll0_dll_sharing_dll_delayctrl; // dll0:dll_delayctrl -> p0:dll_delayctrl
lpddr2_cntrlr_pll0 pll0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.pll_mem_clk (pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_write_clk), // .pll_write_clk
.pll_locked (pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_avl_phy_clk) // .pll_avl_phy_clk
);
lpddr2_cntrlr_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_reset_export_n (afi_reset_export_n), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (p0_avl_clk_clk), // avl_clk.clk
.avl_reset_n (p0_avl_reset_reset), // avl_reset.reset_n
.scc_clk (p0_scc_clk_clk), // scc_clk.clk
.scc_reset_n (p0_scc_reset_reset), // scc_reset.reset_n
.avl_address (s0_avl_address), // avl.address
.avl_write (s0_avl_write), // .write
.avl_writedata (s0_avl_writedata), // .writedata
.avl_read (s0_avl_read), // .read
.avl_readdata (s0_avl_readdata), // .readdata
.avl_waitrequest (s0_avl_waitrequest), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (s0_scc_scc_data), // scc.scc_data
.scc_dqs_ena (s0_scc_scc_dqs_ena), // .scc_dqs_ena
.scc_dqs_io_ena (s0_scc_scc_dqs_io_ena), // .scc_dqs_io_ena
.scc_dq_ena (s0_scc_scc_dq_ena), // .scc_dq_ena
.scc_dm_ena (s0_scc_scc_dm_ena), // .scc_dm_ena
.capture_strobe_tracking (p0_scc_capture_strobe_tracking), // .capture_strobe_tracking
.scc_upd (s0_scc_scc_upd), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_write_clk), // .pll_write_clk
.pll_locked (pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll0_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct0_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct0_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_ca (mem_ca), // memory.mem_ca
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
lpddr2_cntrlr_s0 s0 (
.avl_clk (p0_avl_clk_clk), // avl_clk.clk
.avl_reset_n (p0_avl_reset_reset), // avl_reset.reset_n
.scc_clk (p0_scc_clk_clk), // scc_clk.clk
.reset_n_scc_clk (p0_scc_reset_reset), // scc_reset.reset_n
.scc_data (s0_scc_scc_data), // scc.scc_data
.scc_dqs_ena (s0_scc_scc_dqs_ena), // .scc_dqs_ena
.scc_dqs_io_ena (s0_scc_scc_dqs_io_ena), // .scc_dqs_io_ena
.scc_dq_ena (s0_scc_scc_dq_ena), // .scc_dq_ena
.scc_dm_ena (s0_scc_scc_dm_ena), // .scc_dm_ena
.capture_strobe_tracking (p0_scc_capture_strobe_tracking), // .capture_strobe_tracking
.scc_upd (s0_scc_scc_upd), // .scc_upd
.afi_init_req (c0_afi_afi_init_req), // afi_init_cal_req.afi_init_req
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
.avl_address (s0_avl_address), // avl.address
.avl_write (s0_avl_write), // .write
.avl_writedata (s0_avl_writedata), // .writedata
.avl_read (s0_avl_read), // .read
.avl_readdata (s0_avl_readdata), // .readdata
.avl_waitrequest (s0_avl_waitrequest), // .waitrequest
.afi_seq_busy (s0_tracking_afi_seq_busy), // tracking.afi_seq_busy
.afi_ctl_refresh_done (c0_afi_afi_ctl_refresh_done), // .afi_ctl_refresh_done
.afi_ctl_long_idle (c0_afi_afi_ctl_long_idle) // .afi_ctl_long_idle
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (26),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (32),
.AVL_ADDR_WIDTH_PORT_0 (27),
.AVL_NUM_SYMBOLS_PORT_0 (4),
.LSB_WFIFO_PORT_0 (0),
.MSB_WFIFO_PORT_0 (0),
.LSB_RFIFO_PORT_0 (0),
.MSB_RFIFO_PORT_0 (0),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("LPDDR2"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("TRUE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("BI_DIRECTION"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("LPDDR2_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_14"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1066_6_6_6"),
.ENUM_MEM_IF_TCCD ("TCCD_2"),
.ENUM_MEM_IF_TCL ("TCL_7"),
.ENUM_MEM_IF_TCWL ("TCWL_4"),
.ENUM_MEM_IF_TFAW ("TFAW_16"),
.ENUM_MEM_IF_TRAS ("TRAS_23"),
.ENUM_MEM_IF_TRC ("TRC_29"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_4"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_5"),
.ENUM_MEM_IF_TWTR ("TWTR_2"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_32"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("TRUE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_0"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_32"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("TRUE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_0"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("ODT_DISABLED"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (4),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (4),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (4),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (1248),
.INTG_MEM_IF_TRFC (20),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (20),
.AFI_BANKADDR_WIDTH (0),
.AFI_CONTROL_WIDTH (2),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (0),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (afi_clk), // afi_clk.clk
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.mp_cmd_clk_0 (mp_cmd_clk_0_clk), // mp_cmd_clk_0.clk
.mp_cmd_reset_n_0 (mp_cmd_reset_n_0_reset_n), // mp_cmd_reset_n_0.reset_n
.mp_rfifo_clk_0 (mp_rfifo_clk_0_clk), // mp_rfifo_clk_0.clk
.mp_rfifo_reset_n_0 (mp_rfifo_reset_n_0_reset_n), // mp_rfifo_reset_n_0.reset_n
.mp_wfifo_clk_0 (mp_wfifo_clk_0_clk), // mp_wfifo_clk_0.clk
.mp_wfifo_reset_n_0 (mp_wfifo_reset_n_0_reset_n), // mp_wfifo_reset_n_0.reset_n
.avl_ready_0 (avl_ready_0), // avl_0.waitrequest_n
.avl_burstbegin_0 (avl_burstbegin_0), // .beginbursttransfer
.avl_addr_0 (avl_addr_0), // .address
.avl_rdata_valid_0 (avl_rdata_valid_0), // .readdatavalid
.avl_rdata_0 (avl_rdata_0), // .readdata
.avl_wdata_0 (avl_wdata_0), // .writedata
.avl_be_0 (avl_be_0), // .byteenable
.avl_read_req_0 (avl_read_req_0), // .read
.avl_write_req_0 (avl_write_req_0), // .write
.avl_size_0 (avl_size_0), // .burstcount
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (c0_afi_afi_init_req), // .afi_init_req
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
.afi_seq_busy (s0_tracking_afi_seq_busy), // .afi_seq_busy
.afi_ctl_refresh_done (c0_afi_afi_ctl_refresh_done), // .afi_ctl_refresh_done
.afi_ctl_long_idle (c0_afi_afi_ctl_long_idle), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct0 (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct0_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct0_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("3125 ps")
) dll0 (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll0_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_set_verbosity O 1 const
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// valid O 1
// addr O 64 reg
// cword O 64
// st_amo_val O 64
// exc O 1
// exc_code O 4 reg
// RDY_server_flush_request_put O 1 reg
// RDY_server_flush_response_get O 1
// RDY_tlb_flush O 1 const
// mem_master_awvalid O 1 reg
// mem_master_awid O 4 reg
// mem_master_awaddr O 64 reg
// mem_master_awlen O 8 reg
// mem_master_awsize O 3 reg
// mem_master_awburst O 2 reg
// mem_master_awlock O 1 reg
// mem_master_awcache O 4 reg
// mem_master_awprot O 3 reg
// mem_master_awqos O 4 reg
// mem_master_awregion O 4 reg
// mem_master_wvalid O 1 reg
// mem_master_wdata O 64 reg
// mem_master_wstrb O 8 reg
// mem_master_wlast O 1 reg
// mem_master_bready O 1 reg
// mem_master_arvalid O 1 reg
// mem_master_arid O 4 reg
// mem_master_araddr O 64 reg
// mem_master_arlen O 8 reg
// mem_master_arsize O 3 reg
// mem_master_arburst O 2 reg
// mem_master_arlock O 1 reg
// mem_master_arcache O 4 reg
// mem_master_arprot O 3 reg
// mem_master_arqos O 4 reg
// mem_master_arregion O 4 reg
// mem_master_rready O 1 reg
// RDY_set_watch_tohost O 1 const
// mv_tohost_value O 64 reg
// RDY_mv_tohost_value O 1 const
// RDY_ma_ddr4_ready O 1 const
// mv_status O 8
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// req_op I 2
// req_f3 I 3
// req_amo_funct7 I 7 reg
// req_addr I 64
// req_st_value I 64
// req_priv I 2 unused
// req_sstatus_SUM I 1 unused
// req_mstatus_MXR I 1 unused
// req_satp I 64 unused
// mem_master_awready I 1
// mem_master_wready I 1
// mem_master_bvalid I 1
// mem_master_bid I 4 reg
// mem_master_bresp I 2 reg
// mem_master_arready I 1
// mem_master_rvalid I 1
// mem_master_rid I 4 reg
// mem_master_rdata I 64 reg
// mem_master_rresp I 2 reg
// mem_master_rlast I 1 reg
// set_watch_tohost_watch_tohost I 1 reg
// set_watch_tohost_tohost_addr I 64 reg
// EN_set_verbosity I 1
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_req I 1
// EN_server_flush_request_put I 1
// EN_server_flush_response_get I 1
// EN_tlb_flush I 1 unused
// EN_set_watch_tohost I 1
// EN_ma_ddr4_ready I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkMMU_Cache(CLK,
RST_N,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
req_op,
req_f3,
req_amo_funct7,
req_addr,
req_st_value,
req_priv,
req_sstatus_SUM,
req_mstatus_MXR,
req_satp,
EN_req,
valid,
addr,
cword,
st_amo_val,
exc,
exc_code,
EN_server_flush_request_put,
RDY_server_flush_request_put,
EN_server_flush_response_get,
RDY_server_flush_response_get,
EN_tlb_flush,
RDY_tlb_flush,
mem_master_awvalid,
mem_master_awid,
mem_master_awaddr,
mem_master_awlen,
mem_master_awsize,
mem_master_awburst,
mem_master_awlock,
mem_master_awcache,
mem_master_awprot,
mem_master_awqos,
mem_master_awregion,
mem_master_awready,
mem_master_wvalid,
mem_master_wdata,
mem_master_wstrb,
mem_master_wlast,
mem_master_wready,
mem_master_bvalid,
mem_master_bid,
mem_master_bresp,
mem_master_bready,
mem_master_arvalid,
mem_master_arid,
mem_master_araddr,
mem_master_arlen,
mem_master_arsize,
mem_master_arburst,
mem_master_arlock,
mem_master_arcache,
mem_master_arprot,
mem_master_arqos,
mem_master_arregion,
mem_master_arready,
mem_master_rvalid,
mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast,
mem_master_rready,
set_watch_tohost_watch_tohost,
set_watch_tohost_tohost_addr,
EN_set_watch_tohost,
RDY_set_watch_tohost,
mv_tohost_value,
RDY_mv_tohost_value,
EN_ma_ddr4_ready,
RDY_ma_ddr4_ready,
mv_status);
parameter [0 : 0] dmem_not_imem = 1'b0;
input CLK;
input RST_N;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method req
input [1 : 0] req_op;
input [2 : 0] req_f3;
input [6 : 0] req_amo_funct7;
input [63 : 0] req_addr;
input [63 : 0] req_st_value;
input [1 : 0] req_priv;
input req_sstatus_SUM;
input req_mstatus_MXR;
input [63 : 0] req_satp;
input EN_req;
// value method valid
output valid;
// value method addr
output [63 : 0] addr;
// value method cword
output [63 : 0] cword;
// value method st_amo_val
output [63 : 0] st_amo_val;
// value method exc
output exc;
// value method exc_code
output [3 : 0] exc_code;
// action method server_flush_request_put
input EN_server_flush_request_put;
output RDY_server_flush_request_put;
// action method server_flush_response_get
input EN_server_flush_response_get;
output RDY_server_flush_response_get;
// action method tlb_flush
input EN_tlb_flush;
output RDY_tlb_flush;
// value method mem_master_m_awvalid
output mem_master_awvalid;
// value method mem_master_m_awid
output [3 : 0] mem_master_awid;
// value method mem_master_m_awaddr
output [63 : 0] mem_master_awaddr;
// value method mem_master_m_awlen
output [7 : 0] mem_master_awlen;
// value method mem_master_m_awsize
output [2 : 0] mem_master_awsize;
// value method mem_master_m_awburst
output [1 : 0] mem_master_awburst;
// value method mem_master_m_awlock
output mem_master_awlock;
// value method mem_master_m_awcache
output [3 : 0] mem_master_awcache;
// value method mem_master_m_awprot
output [2 : 0] mem_master_awprot;
// value method mem_master_m_awqos
output [3 : 0] mem_master_awqos;
// value method mem_master_m_awregion
output [3 : 0] mem_master_awregion;
// value method mem_master_m_awuser
// action method mem_master_m_awready
input mem_master_awready;
// value method mem_master_m_wvalid
output mem_master_wvalid;
// value method mem_master_m_wdata
output [63 : 0] mem_master_wdata;
// value method mem_master_m_wstrb
output [7 : 0] mem_master_wstrb;
// value method mem_master_m_wlast
output mem_master_wlast;
// value method mem_master_m_wuser
// action method mem_master_m_wready
input mem_master_wready;
// action method mem_master_m_bvalid
input mem_master_bvalid;
input [3 : 0] mem_master_bid;
input [1 : 0] mem_master_bresp;
// value method mem_master_m_bready
output mem_master_bready;
// value method mem_master_m_arvalid
output mem_master_arvalid;
// value method mem_master_m_arid
output [3 : 0] mem_master_arid;
// value method mem_master_m_araddr
output [63 : 0] mem_master_araddr;
// value method mem_master_m_arlen
output [7 : 0] mem_master_arlen;
// value method mem_master_m_arsize
output [2 : 0] mem_master_arsize;
// value method mem_master_m_arburst
output [1 : 0] mem_master_arburst;
// value method mem_master_m_arlock
output mem_master_arlock;
// value method mem_master_m_arcache
output [3 : 0] mem_master_arcache;
// value method mem_master_m_arprot
output [2 : 0] mem_master_arprot;
// value method mem_master_m_arqos
output [3 : 0] mem_master_arqos;
// value method mem_master_m_arregion
output [3 : 0] mem_master_arregion;
// value method mem_master_m_aruser
// action method mem_master_m_arready
input mem_master_arready;
// action method mem_master_m_rvalid
input mem_master_rvalid;
input [3 : 0] mem_master_rid;
input [63 : 0] mem_master_rdata;
input [1 : 0] mem_master_rresp;
input mem_master_rlast;
// value method mem_master_m_rready
output mem_master_rready;
// action method set_watch_tohost
input set_watch_tohost_watch_tohost;
input [63 : 0] set_watch_tohost_tohost_addr;
input EN_set_watch_tohost;
output RDY_set_watch_tohost;
// value method mv_tohost_value
output [63 : 0] mv_tohost_value;
output RDY_mv_tohost_value;
// action method ma_ddr4_ready
input EN_ma_ddr4_ready;
output RDY_ma_ddr4_ready;
// value method mv_status
output [7 : 0] mv_status;
// signals for module outputs
reg [63 : 0] cword;
wire [63 : 0] addr,
mem_master_araddr,
mem_master_awaddr,
mem_master_wdata,
mv_tohost_value,
st_amo_val;
wire [7 : 0] mem_master_arlen,
mem_master_awlen,
mem_master_wstrb,
mv_status;
wire [3 : 0] exc_code,
mem_master_arcache,
mem_master_arid,
mem_master_arqos,
mem_master_arregion,
mem_master_awcache,
mem_master_awid,
mem_master_awqos,
mem_master_awregion;
wire [2 : 0] mem_master_arprot,
mem_master_arsize,
mem_master_awprot,
mem_master_awsize;
wire [1 : 0] mem_master_arburst, mem_master_awburst;
wire RDY_ma_ddr4_ready,
RDY_mv_tohost_value,
RDY_server_flush_request_put,
RDY_server_flush_response_get,
RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_set_verbosity,
RDY_set_watch_tohost,
RDY_tlb_flush,
exc,
mem_master_arlock,
mem_master_arvalid,
mem_master_awlock,
mem_master_awvalid,
mem_master_bready,
mem_master_rready,
mem_master_wlast,
mem_master_wvalid,
valid;
// inlined wires
wire [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1,
ctr_wr_rsps_pending_crg$port1__write_1,
ctr_wr_rsps_pending_crg$port2__read,
ctr_wr_rsps_pending_crg$port3__read;
wire ctr_wr_rsps_pending_crg$EN_port2__write, dw_valid$whas;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register ctr_wr_rsps_pending_crg
reg [3 : 0] ctr_wr_rsps_pending_crg;
wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN;
wire ctr_wr_rsps_pending_crg$EN;
// register rg_addr
reg [63 : 0] rg_addr;
wire [63 : 0] rg_addr$D_IN;
wire rg_addr$EN;
// register rg_amo_funct7
reg [6 : 0] rg_amo_funct7;
wire [6 : 0] rg_amo_funct7$D_IN;
wire rg_amo_funct7$EN;
// register rg_cset_cword_in_cache
reg [8 : 0] rg_cset_cword_in_cache;
wire [8 : 0] rg_cset_cword_in_cache$D_IN;
wire rg_cset_cword_in_cache$EN;
// register rg_cset_in_cache
reg [5 : 0] rg_cset_in_cache;
wire [5 : 0] rg_cset_in_cache$D_IN;
wire rg_cset_in_cache$EN;
// register rg_ddr4_ready
reg rg_ddr4_ready;
wire rg_ddr4_ready$D_IN, rg_ddr4_ready$EN;
// register rg_error_during_refill
reg rg_error_during_refill;
wire rg_error_during_refill$D_IN, rg_error_during_refill$EN;
// register rg_exc_code
reg [3 : 0] rg_exc_code;
reg [3 : 0] rg_exc_code$D_IN;
wire rg_exc_code$EN;
// register rg_f3
reg [2 : 0] rg_f3;
wire [2 : 0] rg_f3$D_IN;
wire rg_f3$EN;
// register rg_ld_val
reg [63 : 0] rg_ld_val;
reg [63 : 0] rg_ld_val$D_IN;
wire rg_ld_val$EN;
// register rg_lower_word32
reg [31 : 0] rg_lower_word32;
wire [31 : 0] rg_lower_word32$D_IN;
wire rg_lower_word32$EN;
// register rg_lower_word32_full
reg rg_lower_word32_full;
wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN;
// register rg_lrsc_pa
reg [63 : 0] rg_lrsc_pa;
wire [63 : 0] rg_lrsc_pa$D_IN;
wire rg_lrsc_pa$EN;
// register rg_lrsc_valid
reg rg_lrsc_valid;
wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN;
// register rg_op
reg [1 : 0] rg_op;
wire [1 : 0] rg_op$D_IN;
wire rg_op$EN;
// register rg_pa
reg [63 : 0] rg_pa;
wire [63 : 0] rg_pa$D_IN;
wire rg_pa$EN;
// register rg_pte_pa
reg [63 : 0] rg_pte_pa;
wire [63 : 0] rg_pte_pa$D_IN;
wire rg_pte_pa$EN;
// register rg_st_amo_val
reg [63 : 0] rg_st_amo_val;
wire [63 : 0] rg_st_amo_val$D_IN;
wire rg_st_amo_val$EN;
// register rg_state
reg [4 : 0] rg_state;
reg [4 : 0] rg_state$D_IN;
wire rg_state$EN;
// register rg_tohost_addr
reg [63 : 0] rg_tohost_addr;
wire [63 : 0] rg_tohost_addr$D_IN;
wire rg_tohost_addr$EN;
// register rg_tohost_value
reg [63 : 0] rg_tohost_value;
wire [63 : 0] rg_tohost_value$D_IN;
wire rg_tohost_value$EN;
// register rg_victim_way
reg rg_victim_way;
wire rg_victim_way$D_IN, rg_victim_way$EN;
// register rg_watch_tohost
reg rg_watch_tohost;
wire rg_watch_tohost$D_IN, rg_watch_tohost$EN;
// register rg_wr_rsp_err
reg rg_wr_rsp_err;
wire rg_wr_rsp_err$D_IN, rg_wr_rsp_err$EN;
// ports of submodule f_fabric_write_reqs
reg [130 : 0] f_fabric_write_reqs$D_IN;
wire [130 : 0] f_fabric_write_reqs$D_OUT;
wire f_fabric_write_reqs$CLR,
f_fabric_write_reqs$DEQ,
f_fabric_write_reqs$EMPTY_N,
f_fabric_write_reqs$ENQ,
f_fabric_write_reqs$FULL_N;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule master_xactor_f_rd_addr
wire [96 : 0] master_xactor_f_rd_addr$D_IN, master_xactor_f_rd_addr$D_OUT;
wire master_xactor_f_rd_addr$CLR,
master_xactor_f_rd_addr$DEQ,
master_xactor_f_rd_addr$EMPTY_N,
master_xactor_f_rd_addr$ENQ,
master_xactor_f_rd_addr$FULL_N;
// ports of submodule master_xactor_f_rd_data
wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT;
wire master_xactor_f_rd_data$CLR,
master_xactor_f_rd_data$DEQ,
master_xactor_f_rd_data$EMPTY_N,
master_xactor_f_rd_data$ENQ,
master_xactor_f_rd_data$FULL_N;
// ports of submodule master_xactor_f_wr_addr
wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT;
wire master_xactor_f_wr_addr$CLR,
master_xactor_f_wr_addr$DEQ,
master_xactor_f_wr_addr$EMPTY_N,
master_xactor_f_wr_addr$ENQ,
master_xactor_f_wr_addr$FULL_N;
// ports of submodule master_xactor_f_wr_data
wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT;
wire master_xactor_f_wr_data$CLR,
master_xactor_f_wr_data$DEQ,
master_xactor_f_wr_data$EMPTY_N,
master_xactor_f_wr_data$ENQ,
master_xactor_f_wr_data$FULL_N;
// ports of submodule master_xactor_f_wr_resp
wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT;
wire master_xactor_f_wr_resp$CLR,
master_xactor_f_wr_resp$DEQ,
master_xactor_f_wr_resp$EMPTY_N,
master_xactor_f_wr_resp$ENQ,
master_xactor_f_wr_resp$FULL_N;
// ports of submodule ram_cword_set
reg [127 : 0] ram_cword_set$DIB;
reg [8 : 0] ram_cword_set$ADDRB;
wire [127 : 0] ram_cword_set$DIA, ram_cword_set$DOB;
wire [8 : 0] ram_cword_set$ADDRA;
wire ram_cword_set$ENA,
ram_cword_set$ENB,
ram_cword_set$WEA,
ram_cword_set$WEB;
// ports of submodule ram_state_and_ctag_cset
wire [105 : 0] ram_state_and_ctag_cset$DIA,
ram_state_and_ctag_cset$DIB,
ram_state_and_ctag_cset$DOB;
wire [5 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB;
wire ram_state_and_ctag_cset$ENA,
ram_state_and_ctag_cset$ENB,
ram_state_and_ctag_cset$WEA,
ram_state_and_ctag_cset$WEB;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr;
wire soc_map$m_is_mem_addr;
// rule scheduling signals
wire CAN_FIRE_RL_rl_ST_AMO_response,
CAN_FIRE_RL_rl_cache_refill_rsps_loop,
CAN_FIRE_RL_rl_discard_write_rsp,
CAN_FIRE_RL_rl_drive_exception_rsp,
CAN_FIRE_RL_rl_fabric_send_write_req,
CAN_FIRE_RL_rl_io_AMO_SC_req,
CAN_FIRE_RL_rl_io_AMO_op_req,
CAN_FIRE_RL_rl_io_AMO_read_rsp,
CAN_FIRE_RL_rl_io_read_req,
CAN_FIRE_RL_rl_io_read_rsp,
CAN_FIRE_RL_rl_io_write_req,
CAN_FIRE_RL_rl_maintain_io_read_rsp,
CAN_FIRE_RL_rl_probe_and_immed_rsp,
CAN_FIRE_RL_rl_rereq,
CAN_FIRE_RL_rl_reset,
CAN_FIRE_RL_rl_start_cache_refill,
CAN_FIRE_RL_rl_start_reset,
CAN_FIRE_ma_ddr4_ready,
CAN_FIRE_mem_master_m_arready,
CAN_FIRE_mem_master_m_awready,
CAN_FIRE_mem_master_m_bvalid,
CAN_FIRE_mem_master_m_rvalid,
CAN_FIRE_mem_master_m_wready,
CAN_FIRE_req,
CAN_FIRE_server_flush_request_put,
CAN_FIRE_server_flush_response_get,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_set_verbosity,
CAN_FIRE_set_watch_tohost,
CAN_FIRE_tlb_flush,
WILL_FIRE_RL_rl_ST_AMO_response,
WILL_FIRE_RL_rl_cache_refill_rsps_loop,
WILL_FIRE_RL_rl_discard_write_rsp,
WILL_FIRE_RL_rl_drive_exception_rsp,
WILL_FIRE_RL_rl_fabric_send_write_req,
WILL_FIRE_RL_rl_io_AMO_SC_req,
WILL_FIRE_RL_rl_io_AMO_op_req,
WILL_FIRE_RL_rl_io_AMO_read_rsp,
WILL_FIRE_RL_rl_io_read_req,
WILL_FIRE_RL_rl_io_read_rsp,
WILL_FIRE_RL_rl_io_write_req,
WILL_FIRE_RL_rl_maintain_io_read_rsp,
WILL_FIRE_RL_rl_probe_and_immed_rsp,
WILL_FIRE_RL_rl_rereq,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_RL_rl_start_cache_refill,
WILL_FIRE_RL_rl_start_reset,
WILL_FIRE_ma_ddr4_ready,
WILL_FIRE_mem_master_m_arready,
WILL_FIRE_mem_master_m_awready,
WILL_FIRE_mem_master_m_bvalid,
WILL_FIRE_mem_master_m_rvalid,
WILL_FIRE_mem_master_m_wready,
WILL_FIRE_req,
WILL_FIRE_server_flush_request_put,
WILL_FIRE_server_flush_response_get,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_set_verbosity,
WILL_FIRE_set_watch_tohost,
WILL_FIRE_tlb_flush;
// inputs to muxes for submodule ports
wire [130 : 0] MUX_f_fabric_write_reqs$enq_1__VAL_1,
MUX_f_fabric_write_reqs$enq_1__VAL_2,
MUX_f_fabric_write_reqs$enq_1__VAL_3;
wire [127 : 0] MUX_ram_cword_set$a_put_3__VAL_1,
MUX_ram_cword_set$a_put_3__VAL_2;
wire [105 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1;
wire [96 : 0] MUX_master_xactor_f_rd_addr$enq_1__VAL_1,
MUX_master_xactor_f_rd_addr$enq_1__VAL_2;
wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3,
MUX_rg_ld_val$write_1__VAL_2;
wire [8 : 0] MUX_ram_cword_set$b_put_2__VAL_2,
MUX_ram_cword_set$b_put_2__VAL_4;
wire [5 : 0] MUX_rg_cset_in_cache$write_1__VAL_1;
wire [4 : 0] MUX_rg_state$write_1__VAL_1,
MUX_rg_state$write_1__VAL_10,
MUX_rg_state$write_1__VAL_12,
MUX_rg_state$write_1__VAL_3;
wire [3 : 0] MUX_rg_exc_code$write_1__VAL_1;
wire MUX_dw_output_ld_val$wset_1__SEL_1,
MUX_dw_output_ld_val$wset_1__SEL_2,
MUX_dw_output_ld_val$wset_1__SEL_3,
MUX_dw_output_ld_val$wset_1__SEL_4,
MUX_f_fabric_write_reqs$enq_1__SEL_2,
MUX_master_xactor_f_rd_addr$enq_1__SEL_1,
MUX_ram_cword_set$a_put_1__SEL_1,
MUX_ram_cword_set$b_put_1__SEL_1,
MUX_ram_cword_set$b_put_1__SEL_2,
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1,
MUX_rg_exc_code$write_1__SEL_1,
MUX_rg_exc_code$write_1__SEL_2,
MUX_rg_exc_code$write_1__SEL_3,
MUX_rg_exc_code$write_1__SEL_4,
MUX_rg_ld_val$write_1__SEL_2,
MUX_rg_lrsc_valid$write_1__SEL_2,
MUX_rg_state$write_1__SEL_10,
MUX_rg_state$write_1__SEL_12,
MUX_rg_state$write_1__SEL_13,
MUX_rg_state$write_1__SEL_2,
MUX_rg_state$write_1__SEL_3;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h4255;
reg [31 : 0] v__h4354;
reg [31 : 0] v__h4504;
reg [31 : 0] v__h19794;
reg [31 : 0] v__h23510;
reg [31 : 0] v__h37786;
reg [31 : 0] v__h26828;
reg [31 : 0] v__h27567;
reg [31 : 0] v__h27808;
reg [31 : 0] v__h37718;
reg [31 : 0] v__h30273;
reg [31 : 0] v__h30623;
reg [31 : 0] v__h31725;
reg [31 : 0] v__h31832;
reg [31 : 0] v__h31937;
reg [31 : 0] v__h32017;
reg [31 : 0] v__h32227;
reg [31 : 0] v__h32345;
reg [31 : 0] v__h32639;
reg [31 : 0] v__h32814;
reg [31 : 0] v__h35073;
reg [31 : 0] v__h32910;
reg [31 : 0] v__h35651;
reg [31 : 0] v__h35693;
reg [31 : 0] v__h3787;
reg [31 : 0] v__h36063;
reg [31 : 0] v__h3781;
reg [31 : 0] v__h4249;
reg [31 : 0] v__h4348;
reg [31 : 0] v__h4498;
reg [31 : 0] v__h19788;
reg [31 : 0] v__h23504;
reg [31 : 0] v__h26822;
reg [31 : 0] v__h27561;
reg [31 : 0] v__h27802;
reg [31 : 0] v__h30267;
reg [31 : 0] v__h30617;
reg [31 : 0] v__h31719;
reg [31 : 0] v__h31826;
reg [31 : 0] v__h31931;
reg [31 : 0] v__h32011;
reg [31 : 0] v__h32221;
reg [31 : 0] v__h32339;
reg [31 : 0] v__h32633;
reg [31 : 0] v__h32808;
reg [31 : 0] v__h32904;
reg [31 : 0] v__h35067;
reg [31 : 0] v__h35645;
reg [31 : 0] v__h35687;
reg [31 : 0] v__h36057;
reg [31 : 0] v__h37712;
reg [31 : 0] v__h37780;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_old_cword0949_BIT_ETC__q30,
CASE_rg_addr_BITS_2_TO_0_0x0_old_cword0949_BIT_ETC__q33,
CASE_rg_addr_BITS_2_TO_0_0x0_result1503_0x4_re_ETC__q34,
CASE_rg_addr_BITS_2_TO_0_0x0_result1568_0x4_re_ETC__q35,
CASE_rg_addr_BITS_2_TO_0_0x0_result4781_0x4_re_ETC__q50,
CASE_rg_addr_BITS_2_TO_0_0x0_result9616_0x4_re_ETC__q29,
CASE_rg_f3_0b0_IF_rg_addr_9_BITS_2_TO_0_30_EQ__ETC__q52,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d325,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d337,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d714,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d734,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d843,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d853,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d427,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d436,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d504,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d513,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d316,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d698,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d726,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d835,
IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC___d346,
IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_IF_rg_f3_53_E_ETC___d385,
_theResult_____2__h24034,
_theResult_____2__h32986,
ld_val__h30732,
mem_req_wr_data_wdata__h2980,
n__h20960,
n__h23896,
new_ld_val__h32940,
old_cword__h20949,
w1__h24026,
w1__h32974,
w1__h32978;
reg [7 : 0] mem_req_wr_data_wstrb__h2981;
reg [2 : 0] value__h32526, x__h2801;
wire [63 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__04_BIT__ETC___d447,
IF_NOT_ram_state_and_ctag_cset_b_read__04_BIT__ETC___d524,
IF_ram_state_and_ctag_cset_b_read__04_BIT_105__ETC___d446,
IF_ram_state_and_ctag_cset_b_read__04_BIT_105__ETC___d523,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_1_E_ETC___d354,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_IF__ETC___d854,
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_ram_ETC___d339,
IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_rg_st_amo_val_ETC___d454,
IF_rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_ETC___d531,
_theResult___snd_fst__h2988,
cline_fabric_addr__h26881,
new_st_val__h23732,
new_st_val__h24038,
new_st_val__h24129,
new_st_val__h25109,
new_st_val__h25113,
new_st_val__h25117,
new_st_val__h25121,
new_st_val__h25126,
new_st_val__h25132,
new_st_val__h25137,
new_st_val__h32990,
new_st_val__h33081,
new_st_val__h34941,
new_st_val__h34945,
new_st_val__h34949,
new_st_val__h34953,
new_st_val__h34958,
new_st_val__h34964,
new_st_val__h34969,
new_value__h22600,
new_value__h6175,
result__h18884,
result__h18912,
result__h18940,
result__h18968,
result__h18996,
result__h19024,
result__h19052,
result__h19080,
result__h19125,
result__h19153,
result__h19181,
result__h19209,
result__h19237,
result__h19265,
result__h19293,
result__h19321,
result__h19366,
result__h19394,
result__h19422,
result__h19450,
result__h19491,
result__h19519,
result__h19547,
result__h19575,
result__h19616,
result__h19644,
result__h19683,
result__h19711,
result__h30792,
result__h30822,
result__h30849,
result__h30876,
result__h30903,
result__h30930,
result__h30957,
result__h30984,
result__h31028,
result__h31055,
result__h31082,
result__h31109,
result__h31136,
result__h31163,
result__h31190,
result__h31217,
result__h31261,
result__h31288,
result__h31315,
result__h31342,
result__h31382,
result__h31409,
result__h31436,
result__h31463,
result__h31503,
result__h31530,
result__h31568,
result__h31595,
result__h33169,
result__h34077,
result__h34105,
result__h34133,
result__h34161,
result__h34189,
result__h34217,
result__h34245,
result__h34290,
result__h34318,
result__h34346,
result__h34374,
result__h34402,
result__h34430,
result__h34458,
result__h34486,
result__h34531,
result__h34559,
result__h34587,
result__h34615,
result__h34656,
result__h34684,
result__h34712,
result__h34740,
result__h34781,
result__h34809,
result__h34848,
result__h34876,
w1___1__h24097,
w1___1__h33049,
w2___1__h33050,
w2__h32980,
word64__h6008,
x__h20181,
x__h32969,
x__h6198,
y__h12528,
y__h6199,
y__h6213;
wire [31 : 0] IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC__q31,
ld_val0732_BITS_31_TO_0__q38,
ld_val0732_BITS_63_TO_32__q45,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10,
rg_st_amo_val_BITS_31_TO_0__q32,
w12974_BITS_31_TO_0__q51,
word64008_BITS_31_TO_0__q17,
word64008_BITS_63_TO_32__q24;
wire [15 : 0] ld_val0732_BITS_15_TO_0__q37,
ld_val0732_BITS_31_TO_16__q41,
ld_val0732_BITS_47_TO_32__q44,
ld_val0732_BITS_63_TO_48__q48,
master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6,
master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13,
word64008_BITS_15_TO_0__q16,
word64008_BITS_31_TO_16__q20,
word64008_BITS_47_TO_32__q23,
word64008_BITS_63_TO_48__q27;
wire [7 : 0] ld_val0732_BITS_15_TO_8__q39,
ld_val0732_BITS_23_TO_16__q40,
ld_val0732_BITS_31_TO_24__q42,
ld_val0732_BITS_39_TO_32__q43,
ld_val0732_BITS_47_TO_40__q46,
ld_val0732_BITS_55_TO_48__q47,
ld_val0732_BITS_63_TO_56__q49,
ld_val0732_BITS_7_TO_0__q36,
master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1,
master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4,
master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7,
master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8,
master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11,
master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14,
strobe64__h2918,
strobe64__h2920,
strobe64__h2922,
word64008_BITS_15_TO_8__q18,
word64008_BITS_23_TO_16__q19,
word64008_BITS_31_TO_24__q21,
word64008_BITS_39_TO_32__q22,
word64008_BITS_47_TO_40__q25,
word64008_BITS_55_TO_48__q26,
word64008_BITS_63_TO_56__q28,
word64008_BITS_7_TO_0__q15;
wire [5 : 0] shift_bits__h2768;
wire [4 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__04_BIT__ETC___d151,
IF_rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_ETC___d153,
IF_rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_ETC___d152;
wire [3 : 0] access_exc_code__h2535, b__h26782;
wire [1 : 0] tmp__h27043, tmp__h27044;
wire IF_rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_ETC___d120,
NOT_cfg_verbosity_read__1_ULE_1_2___d43,
NOT_cfg_verbosity_read__1_ULE_2_97___d598,
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d161,
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d360,
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d368,
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d371,
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d377,
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d381,
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d392,
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d534,
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d546,
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d576,
NOT_ram_state_and_ctag_cset_b_read__04_BIT_52__ETC___d119,
NOT_ram_state_and_ctag_cset_b_read__04_BIT_52__ETC___d167,
NOT_ram_state_and_ctag_cset_b_read__04_BIT_52__ETC___d369,
NOT_ram_state_and_ctag_cset_b_read__04_BIT_52__ETC___d374,
NOT_req_f3_BITS_1_TO_0_39_EQ_0b0_40_41_AND_NOT_ETC___d960,
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d148,
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d529,
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d549,
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d557,
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d569,
NOT_rg_op_3_EQ_1_1_73_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d389,
NOT_rg_op_3_EQ_1_1_73_AND_ram_state_and_ctag_c_ETC___d378,
NOT_rg_op_3_EQ_2_5_40_OR_NOT_rg_amo_funct7_6_B_ETC___d387,
NOT_rg_op_3_EQ_2_5_40_OR_NOT_rg_amo_funct7_6_B_ETC___d547,
NOT_rg_op_3_EQ_2_5_40_OR_NOT_rg_amo_funct7_6_B_ETC___d551,
NOT_rg_op_3_EQ_2_5_40_OR_NOT_rg_amo_funct7_6_B_ETC___d555,
dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d122,
lrsc_result__h20171,
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115,
ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109,
ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d164,
ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d175,
ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d358,
ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d571,
req_f3_BITS_1_TO_0_39_EQ_0b0_40_OR_req_f3_BITS_ETC___d969,
rg_addr_9_EQ_rg_lrsc_pa_7___d165,
rg_amo_funct7_6_BITS_6_TO_2_7_EQ_0b10_8_AND_ra_ETC___d363,
rg_lrsc_pa_7_EQ_rg_addr_9___d98,
rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d138,
rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d169,
rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d179,
rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d181,
rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d184,
rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d177,
rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d390,
rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d527,
rg_op_3_EQ_2_5_AND_rg_amo_funct7_6_BITS_6_TO_2_ETC___d561,
rg_state_6_EQ_13_54_AND_rg_op_3_EQ_0_4_OR_rg_o_ETC___d656;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
!f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
!f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = dw_valid$whas ;
// value method addr
assign addr = rg_addr ;
// value method cword
always@(MUX_dw_output_ld_val$wset_1__SEL_1 or
ld_val__h30732 or
MUX_dw_output_ld_val$wset_1__SEL_2 or
new_ld_val__h32940 or
MUX_dw_output_ld_val$wset_1__SEL_3 or
MUX_dw_output_ld_val$wset_1__VAL_3 or
MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_1: cword = ld_val__h30732;
MUX_dw_output_ld_val$wset_1__SEL_2: cword = new_ld_val__h32940;
MUX_dw_output_ld_val$wset_1__SEL_3:
cword = MUX_dw_output_ld_val$wset_1__VAL_3;
MUX_dw_output_ld_val$wset_1__SEL_4: cword = rg_ld_val;
default: cword = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
// value method st_amo_val
assign st_amo_val =
MUX_dw_output_ld_val$wset_1__SEL_3 ? 64'd0 : rg_st_amo_val ;
// value method exc
assign exc = rg_state == 5'd4 ;
// value method exc_code
assign exc_code = rg_exc_code ;
// action method server_flush_request_put
assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ;
// action method server_flush_response_get
assign RDY_server_flush_response_get =
f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_flush_response_get =
f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ;
// action method tlb_flush
assign RDY_tlb_flush = 1'd1 ;
assign CAN_FIRE_tlb_flush = 1'd1 ;
assign WILL_FIRE_tlb_flush = EN_tlb_flush ;
// value method mem_master_m_awvalid
assign mem_master_awvalid = master_xactor_f_wr_addr$EMPTY_N ;
// value method mem_master_m_awid
assign mem_master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ;
// value method mem_master_m_awaddr
assign mem_master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ;
// value method mem_master_m_awlen
assign mem_master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ;
// value method mem_master_m_awsize
assign mem_master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ;
// value method mem_master_m_awburst
assign mem_master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ;
// value method mem_master_m_awlock
assign mem_master_awlock = master_xactor_f_wr_addr$D_OUT[15] ;
// value method mem_master_m_awcache
assign mem_master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ;
// value method mem_master_m_awprot
assign mem_master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ;
// value method mem_master_m_awqos
assign mem_master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ;
// value method mem_master_m_awregion
assign mem_master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ;
// action method mem_master_m_awready
assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_mem_master_m_awready = 1'd1 ;
// value method mem_master_m_wvalid
assign mem_master_wvalid = master_xactor_f_wr_data$EMPTY_N ;
// value method mem_master_m_wdata
assign mem_master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ;
// value method mem_master_m_wstrb
assign mem_master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ;
// value method mem_master_m_wlast
assign mem_master_wlast = master_xactor_f_wr_data$D_OUT[0] ;
// action method mem_master_m_wready
assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_mem_master_m_wready = 1'd1 ;
// action method mem_master_m_bvalid
assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;
// value method mem_master_m_bready
assign mem_master_bready = master_xactor_f_wr_resp$FULL_N ;
// value method mem_master_m_arvalid
assign mem_master_arvalid = master_xactor_f_rd_addr$EMPTY_N ;
// value method mem_master_m_arid
assign mem_master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ;
// value method mem_master_m_araddr
assign mem_master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ;
// value method mem_master_m_arlen
assign mem_master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ;
// value method mem_master_m_arsize
assign mem_master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ;
// value method mem_master_m_arburst
assign mem_master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ;
// value method mem_master_m_arlock
assign mem_master_arlock = master_xactor_f_rd_addr$D_OUT[15] ;
// value method mem_master_m_arcache
assign mem_master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ;
// value method mem_master_m_arprot
assign mem_master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ;
// value method mem_master_m_arqos
assign mem_master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ;
// value method mem_master_m_arregion
assign mem_master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ;
// action method mem_master_m_arready
assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_mem_master_m_arready = 1'd1 ;
// action method mem_master_m_rvalid
assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;
// value method mem_master_m_rready
assign mem_master_rready = master_xactor_f_rd_data$FULL_N ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// value method mv_tohost_value
assign mv_tohost_value = rg_tohost_value ;
assign RDY_mv_tohost_value = 1'd1 ;
// action method ma_ddr4_ready
assign RDY_ma_ddr4_ready = 1'd1 ;
assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;
// value method mv_status
assign mv_status = rg_wr_rsp_err ? 8'd1 : 8'd0 ;
// submodule f_fabric_write_reqs
FIFO2 #(.width(32'd131), .guarded(32'd1)) f_fabric_write_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_fabric_write_reqs$D_IN),
.ENQ(f_fabric_write_reqs$ENQ),
.DEQ(f_fabric_write_reqs$DEQ),
.CLR(f_fabric_write_reqs$CLR),
.D_OUT(f_fabric_write_reqs$D_OUT),
.FULL_N(f_fabric_write_reqs$FULL_N),
.EMPTY_N(f_fabric_write_reqs$EMPTY_N));
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule master_xactor_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_addr$D_IN),
.ENQ(master_xactor_f_rd_addr$ENQ),
.DEQ(master_xactor_f_rd_addr$DEQ),
.CLR(master_xactor_f_rd_addr$CLR),
.D_OUT(master_xactor_f_rd_addr$D_OUT),
.FULL_N(master_xactor_f_rd_addr$FULL_N),
.EMPTY_N(master_xactor_f_rd_addr$EMPTY_N));
// submodule master_xactor_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_data$D_IN),
.ENQ(master_xactor_f_rd_data$ENQ),
.DEQ(master_xactor_f_rd_data$DEQ),
.CLR(master_xactor_f_rd_data$CLR),
.D_OUT(master_xactor_f_rd_data$D_OUT),
.FULL_N(master_xactor_f_rd_data$FULL_N),
.EMPTY_N(master_xactor_f_rd_data$EMPTY_N));
// submodule master_xactor_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_addr$D_IN),
.ENQ(master_xactor_f_wr_addr$ENQ),
.DEQ(master_xactor_f_wr_addr$DEQ),
.CLR(master_xactor_f_wr_addr$CLR),
.D_OUT(master_xactor_f_wr_addr$D_OUT),
.FULL_N(master_xactor_f_wr_addr$FULL_N),
.EMPTY_N(master_xactor_f_wr_addr$EMPTY_N));
// submodule master_xactor_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_data$D_IN),
.ENQ(master_xactor_f_wr_data$ENQ),
.DEQ(master_xactor_f_wr_data$DEQ),
.CLR(master_xactor_f_wr_data$CLR),
.D_OUT(master_xactor_f_wr_data$D_OUT),
.FULL_N(master_xactor_f_wr_data$FULL_N),
.EMPTY_N(master_xactor_f_wr_data$EMPTY_N));
// submodule master_xactor_f_wr_resp
FIFO2 #(.width(32'd6), .guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_resp$D_IN),
.ENQ(master_xactor_f_wr_resp$ENQ),
.DEQ(master_xactor_f_wr_resp$DEQ),
.CLR(master_xactor_f_wr_resp$CLR),
.D_OUT(master_xactor_f_wr_resp$D_OUT),
.FULL_N(master_xactor_f_wr_resp$FULL_N),
.EMPTY_N(master_xactor_f_wr_resp$EMPTY_N));
// submodule ram_cword_set
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd9),
.DATA_WIDTH(32'd128),
.MEMSIZE(10'd512)) ram_cword_set(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(ram_cword_set$ADDRA),
.ADDRB(ram_cword_set$ADDRB),
.DIA(ram_cword_set$DIA),
.DIB(ram_cword_set$DIB),
.WEA(ram_cword_set$WEA),
.WEB(ram_cword_set$WEB),
.ENA(ram_cword_set$ENA),
.ENB(ram_cword_set$ENB),
.DOA(),
.DOB(ram_cword_set$DOB));
// submodule ram_state_and_ctag_cset
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd6),
.DATA_WIDTH(32'd106),
.MEMSIZE(7'd64)) ram_state_and_ctag_cset(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(ram_state_and_ctag_cset$ADDRA),
.ADDRB(ram_state_and_ctag_cset$ADDRB),
.DIA(ram_state_and_ctag_cset$DIA),
.DIB(ram_state_and_ctag_cset$DIB),
.WEA(ram_state_and_ctag_cset$WEA),
.WEB(ram_state_and_ctag_cset$WEB),
.ENA(ram_state_and_ctag_cset$ENA),
.ENB(ram_state_and_ctag_cset$ENB),
.DOA(),
.DOB(ram_state_and_ctag_cset$DOB));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(soc_map$m_is_mem_addr),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_rl_fabric_send_write_req
assign CAN_FIRE_RL_rl_fabric_send_write_req =
ctr_wr_rsps_pending_crg != 4'd15 &&
f_fabric_write_reqs$EMPTY_N &&
master_xactor_f_wr_addr$FULL_N &&
master_xactor_f_wr_data$FULL_N &&
rg_ddr4_ready ;
assign WILL_FIRE_RL_rl_fabric_send_write_req =
CAN_FIRE_RL_rl_fabric_send_write_req ;
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset =
(rg_cset_in_cache != 6'd63 ||
f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) &&
rg_state == 5'd1 ;
assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;
// rule RL_rl_probe_and_immed_rsp
assign CAN_FIRE_RL_rl_probe_and_immed_rsp =
dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d122 &&
rg_ddr4_ready &&
rg_state == 5'd3 ;
assign WILL_FIRE_RL_rl_probe_and_immed_rsp =
CAN_FIRE_RL_rl_probe_and_immed_rsp &&
!WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_start_cache_refill
assign CAN_FIRE_RL_rl_start_cache_refill =
master_xactor_f_rd_addr$FULL_N && rg_state == 5'd9 &&
b__h26782 == 4'd0 ;
assign WILL_FIRE_RL_rl_start_cache_refill =
CAN_FIRE_RL_rl_start_cache_refill &&
!WILL_FIRE_RL_rl_start_reset &&
!EN_req ;
// rule RL_rl_cache_refill_rsps_loop
assign CAN_FIRE_RL_rl_cache_refill_rsps_loop =
master_xactor_f_rd_data$EMPTY_N && rg_state == 5'd10 ;
assign WILL_FIRE_RL_rl_cache_refill_rsps_loop =
CAN_FIRE_RL_rl_cache_refill_rsps_loop &&
!WILL_FIRE_RL_rl_start_reset &&
!EN_req ;
// rule RL_rl_rereq
assign CAN_FIRE_RL_rl_rereq = rg_state == 5'd11 ;
assign WILL_FIRE_RL_rl_rereq =
CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ;
// rule RL_rl_ST_AMO_response
assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 5'd12 ;
assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ;
// rule RL_rl_io_read_req
assign CAN_FIRE_RL_rl_io_read_req =
master_xactor_f_rd_addr$FULL_N &&
rg_state_6_EQ_13_54_AND_rg_op_3_EQ_0_4_OR_rg_o_ETC___d656 ;
assign WILL_FIRE_RL_rl_io_read_req =
CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_read_rsp
assign CAN_FIRE_RL_rl_io_read_rsp =
master_xactor_f_rd_data$EMPTY_N && rg_state == 5'd14 ;
assign WILL_FIRE_RL_rl_io_read_rsp =
CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_maintain_io_read_rsp
assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 5'd15 ;
assign WILL_FIRE_RL_rl_maintain_io_read_rsp =
CAN_FIRE_RL_rl_maintain_io_read_rsp ;
// rule RL_rl_io_write_req
assign CAN_FIRE_RL_rl_io_write_req =
f_fabric_write_reqs$FULL_N && rg_state == 5'd13 &&
rg_op == 2'd1 ;
assign WILL_FIRE_RL_rl_io_write_req =
CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_SC_req
assign CAN_FIRE_RL_rl_io_AMO_SC_req =
rg_state == 5'd13 && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 ;
assign WILL_FIRE_RL_rl_io_AMO_SC_req =
CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_op_req
assign CAN_FIRE_RL_rl_io_AMO_op_req =
master_xactor_f_rd_addr$FULL_N && rg_state == 5'd13 &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] != 5'b00010 &&
rg_amo_funct7[6:2] != 5'b00011 ;
assign WILL_FIRE_RL_rl_io_AMO_op_req =
CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_read_rsp
assign CAN_FIRE_RL_rl_io_AMO_read_rsp =
master_xactor_f_rd_data$EMPTY_N &&
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
f_fabric_write_reqs$FULL_N) &&
rg_state == 5'd16 ;
assign WILL_FIRE_RL_rl_io_AMO_read_rsp = MUX_rg_state$write_1__SEL_3 ;
// rule RL_rl_discard_write_rsp
assign CAN_FIRE_RL_rl_discard_write_rsp =
b__h26782 != 4'd0 && master_xactor_f_wr_resp$EMPTY_N ;
assign WILL_FIRE_RL_rl_discard_write_rsp =
CAN_FIRE_RL_rl_discard_write_rsp ;
// rule RL_rl_drive_exception_rsp
assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ;
assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ;
// rule RL_rl_start_reset
assign CAN_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_2 ;
assign WILL_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_2 ;
// inputs to muxes for submodule ports
assign MUX_dw_output_ld_val$wset_1__SEL_1 =
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_dw_output_ld_val$wset_1__SEL_2 =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_dw_output_ld_val$wset_1__SEL_3 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d184 ;
assign MUX_dw_output_ld_val$wset_1__SEL_4 =
WILL_FIRE_RL_rl_maintain_io_read_rsp ||
WILL_FIRE_RL_rl_ST_AMO_response ;
assign MUX_f_fabric_write_reqs$enq_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d529 ;
assign MUX_master_xactor_f_rd_addr$enq_1__SEL_1 =
WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ;
assign MUX_ram_cword_set$a_put_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_ram_cword_set$b_put_1__SEL_1 =
EN_req &&
req_f3_BITS_1_TO_0_39_EQ_0b0_40_OR_req_f3_BITS_ETC___d969 ;
assign MUX_ram_cword_set$b_put_1__SEL_2 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] != 3'd7 ;
assign MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] == 3'd0 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_1 =
EN_req &&
NOT_req_f3_BITS_1_TO_0_39_EQ_0b0_40_41_AND_NOT_ETC___d960 ;
assign MUX_rg_exc_code$write_1__SEL_2 =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_3 =
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_4 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_ld_val$write_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d381 ;
assign MUX_rg_lrsc_valid$write_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d179 ;
assign MUX_rg_state$write_1__SEL_2 =
f_reset_reqs$EMPTY_N && rg_state != 5'd1 ;
assign MUX_rg_state$write_1__SEL_3 =
CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ;
assign MUX_rg_state$write_1__SEL_10 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] == 3'd7 ;
assign MUX_rg_state$write_1__SEL_12 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(dmem_not_imem && !soc_map$m_is_mem_addr ||
rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d138 ||
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d148) ;
assign MUX_rg_state$write_1__SEL_13 =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
assign MUX_dw_output_ld_val$wset_1__VAL_3 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
new_value__h6175 :
new_value__h22600 ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_1 = { rg_f3, rg_pa, x__h32969 } ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_2 =
{ rg_f3,
rg_addr,
IF_rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_ETC___d531 } ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_3 =
{ rg_f3, rg_pa, rg_st_amo_val } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_1 =
{ 4'd0, rg_pa, 8'd0, value__h32526, 18'd65536 } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_2 =
{ 4'd0, cline_fabric_addr__h26881, 29'd15532032 } ;
assign MUX_ram_cword_set$a_put_3__VAL_1 =
rg_victim_way ?
{ master_xactor_f_rd_data$D_OUT[66:3],
ram_cword_set$DOB[63:0] } :
{ ram_cword_set$DOB[127:64],
master_xactor_f_rd_data$D_OUT[66:3] } ;
assign MUX_ram_cword_set$a_put_3__VAL_2 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
{ IF_ram_state_and_ctag_cset_b_read__04_BIT_105__ETC___d446,
IF_NOT_ram_state_and_ctag_cset_b_read__04_BIT__ETC___d447 } :
{ IF_ram_state_and_ctag_cset_b_read__04_BIT_105__ETC___d523,
IF_NOT_ram_state_and_ctag_cset_b_read__04_BIT__ETC___d524 } ;
assign MUX_ram_cword_set$b_put_2__VAL_2 = rg_cset_cword_in_cache + 9'd1 ;
assign MUX_ram_cword_set$b_put_2__VAL_4 = { rg_addr[11:6], 3'd0 } ;
assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 =
{ rg_victim_way || ram_state_and_ctag_cset$DOB[105],
rg_victim_way ?
rg_pa[63:12] :
ram_state_and_ctag_cset$DOB[104:53],
!rg_victim_way || ram_state_and_ctag_cset$DOB[52],
rg_victim_way ?
ram_state_and_ctag_cset$DOB[51:0] :
rg_pa[63:12] } ;
assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 6'd1 ;
assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ;
assign MUX_rg_ld_val$write_1__VAL_2 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
x__h20181 :
IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_IF_rg_f3_53_E_ETC___d385 ;
assign MUX_rg_state$write_1__VAL_1 =
NOT_req_f3_BITS_1_TO_0_39_EQ_0b0_40_41_AND_NOT_ETC___d960 ?
5'd4 :
5'd3 ;
assign MUX_rg_state$write_1__VAL_3 =
(master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ? 5'd15 : 5'd4 ;
assign MUX_rg_state$write_1__VAL_10 =
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
rg_error_during_refill) ?
5'd4 :
5'd11 ;
assign MUX_rg_state$write_1__VAL_12 =
(dmem_not_imem && !soc_map$m_is_mem_addr) ?
5'd13 :
IF_rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_ETC___d153 ;
// inlined wires
assign dw_valid$whas =
(WILL_FIRE_RL_rl_io_AMO_read_rsp ||
WILL_FIRE_RL_rl_io_read_rsp) &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d184 ||
WILL_FIRE_RL_rl_drive_exception_rsp ||
WILL_FIRE_RL_rl_maintain_io_read_rsp ||
WILL_FIRE_RL_rl_ST_AMO_response ;
assign ctr_wr_rsps_pending_crg$port0__write_1 =
ctr_wr_rsps_pending_crg + 4'd1 ;
assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h26782 - 4'd1 ;
assign ctr_wr_rsps_pending_crg$port2__read =
CAN_FIRE_RL_rl_discard_write_rsp ?
ctr_wr_rsps_pending_crg$port1__write_1 :
b__h26782 ;
assign ctr_wr_rsps_pending_crg$EN_port2__write =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
assign ctr_wr_rsps_pending_crg$port3__read =
ctr_wr_rsps_pending_crg$EN_port2__write ?
4'd0 :
ctr_wr_rsps_pending_crg$port2__read ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity ;
// register ctr_wr_rsps_pending_crg
assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ;
assign ctr_wr_rsps_pending_crg$EN = 1'b1 ;
// register rg_addr
assign rg_addr$D_IN = req_addr ;
assign rg_addr$EN = EN_req ;
// register rg_amo_funct7
assign rg_amo_funct7$D_IN = req_amo_funct7 ;
assign rg_amo_funct7$EN = EN_req ;
// register rg_cset_cword_in_cache
assign rg_cset_cword_in_cache$D_IN =
MUX_ram_cword_set$b_put_1__SEL_2 ?
MUX_ram_cword_set$b_put_2__VAL_2 :
MUX_ram_cword_set$b_put_2__VAL_4 ;
assign rg_cset_cword_in_cache$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] != 3'd7 ||
WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_cset_in_cache
assign rg_cset_in_cache$D_IN =
WILL_FIRE_RL_rl_reset ?
MUX_rg_cset_in_cache$write_1__VAL_1 :
6'd0 ;
assign rg_cset_in_cache$EN =
WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ;
// register rg_ddr4_ready
assign rg_ddr4_ready$D_IN = 1'd1 ;
assign rg_ddr4_ready$EN = EN_ma_ddr4_ready ;
// register rg_error_during_refill
assign rg_error_during_refill$D_IN = MUX_rg_exc_code$write_1__SEL_4 ;
assign rg_error_during_refill$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_exc_code
always@(MUX_rg_exc_code$write_1__SEL_1 or
MUX_rg_exc_code$write_1__VAL_1 or
MUX_rg_exc_code$write_1__SEL_2 or
MUX_rg_exc_code$write_1__SEL_3 or
MUX_rg_exc_code$write_1__SEL_4 or access_exc_code__h2535)
case (1'b1)
MUX_rg_exc_code$write_1__SEL_1:
rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1;
MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7;
MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5;
MUX_rg_exc_code$write_1__SEL_4: rg_exc_code$D_IN = access_exc_code__h2535;
default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign rg_exc_code$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
EN_req &&
NOT_req_f3_BITS_1_TO_0_39_EQ_0b0_40_41_AND_NOT_ETC___d960 ;
// register rg_f3
assign rg_f3$D_IN = req_f3 ;
assign rg_f3$EN = EN_req ;
// register rg_ld_val
always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
new_ld_val__h32940 or
MUX_rg_ld_val$write_1__SEL_2 or
MUX_rg_ld_val$write_1__VAL_2 or
WILL_FIRE_RL_rl_io_read_rsp or
ld_val__h30732 or WILL_FIRE_RL_rl_io_AMO_SC_req)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_2: rg_ld_val$D_IN = new_ld_val__h32940;
MUX_rg_ld_val$write_1__SEL_2:
rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2;
WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h30732;
WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1;
default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_ld_val$EN =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d381 ||
WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_io_AMO_SC_req ;
// register rg_lower_word32
assign rg_lower_word32$D_IN = 32'h0 ;
assign rg_lower_word32$EN = 1'b0 ;
// register rg_lower_word32_full
assign rg_lower_word32_full$D_IN = 1'd0 ;
assign rg_lower_word32_full$EN =
WILL_FIRE_RL_rl_start_cache_refill ||
WILL_FIRE_RL_rl_start_reset ;
// register rg_lrsc_pa
assign rg_lrsc_pa$D_IN = rg_addr ;
assign rg_lrsc_pa$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7_6_BITS_6_TO_2_7_EQ_0b10_8_AND_ra_ETC___d363 ;
// register rg_lrsc_valid
assign rg_lrsc_valid$D_IN =
MUX_rg_lrsc_valid$write_1__SEL_2 &&
rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d181 ;
assign rg_lrsc_valid$EN =
WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d179 ||
WILL_FIRE_RL_rl_start_reset ;
// register rg_op
assign rg_op$D_IN = req_op ;
assign rg_op$EN = EN_req ;
// register rg_pa
assign rg_pa$D_IN = EN_req ? req_addr : rg_addr ;
assign rg_pa$EN = EN_req || WILL_FIRE_RL_rl_probe_and_immed_rsp ;
// register rg_pte_pa
assign rg_pte_pa$D_IN = 64'h0 ;
assign rg_pte_pa$EN = 1'b0 ;
// register rg_st_amo_val
assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h23732 ;
assign rg_st_amo_val$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d576 ||
EN_req ;
// register rg_state
always@(EN_req or
MUX_rg_state$write_1__VAL_1 or
WILL_FIRE_RL_rl_start_reset or
WILL_FIRE_RL_rl_io_AMO_read_rsp or
MUX_rg_state$write_1__VAL_3 or
WILL_FIRE_RL_rl_io_AMO_op_req or
WILL_FIRE_RL_rl_io_AMO_SC_req or
WILL_FIRE_RL_rl_io_write_req or
WILL_FIRE_RL_rl_io_read_rsp or
WILL_FIRE_RL_rl_io_read_req or
WILL_FIRE_RL_rl_rereq or
MUX_rg_state$write_1__SEL_10 or
MUX_rg_state$write_1__VAL_10 or
WILL_FIRE_RL_rl_start_cache_refill or
MUX_rg_state$write_1__SEL_12 or
MUX_rg_state$write_1__VAL_12 or MUX_rg_state$write_1__SEL_13)
case (1'b1)
EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_1;
WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 5'd1;
WILL_FIRE_RL_rl_io_AMO_read_rsp:
rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 5'd16;
WILL_FIRE_RL_rl_io_AMO_SC_req || WILL_FIRE_RL_rl_io_write_req:
rg_state$D_IN = 5'd12;
WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 5'd14;
WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 5'd3;
MUX_rg_state$write_1__SEL_10:
rg_state$D_IN = MUX_rg_state$write_1__VAL_10;
WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 5'd10;
MUX_rg_state$write_1__SEL_12:
rg_state$D_IN = MUX_rg_state$write_1__VAL_12;
MUX_rg_state$write_1__SEL_13: rg_state$D_IN = 5'd2;
default: rg_state$D_IN = 5'b01010 /* unspecified value */ ;
endcase
assign rg_state$EN =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] == 3'd7 ||
MUX_rg_state$write_1__SEL_12 ||
WILL_FIRE_RL_rl_io_AMO_read_rsp ||
WILL_FIRE_RL_rl_io_read_rsp ||
EN_req ||
WILL_FIRE_RL_rl_start_reset ||
WILL_FIRE_RL_rl_rereq ||
WILL_FIRE_RL_rl_start_cache_refill ||
WILL_FIRE_RL_rl_io_AMO_SC_req ||
WILL_FIRE_RL_rl_io_write_req ||
WILL_FIRE_RL_rl_io_read_req ||
WILL_FIRE_RL_rl_io_AMO_op_req ;
// register rg_tohost_addr
assign rg_tohost_addr$D_IN = set_watch_tohost_tohost_addr ;
assign rg_tohost_addr$EN = EN_set_watch_tohost ;
// register rg_tohost_value
assign rg_tohost_value$D_IN = rg_st_amo_val ;
assign rg_tohost_value$EN =
WILL_FIRE_RL_rl_ST_AMO_response && rg_watch_tohost &&
rg_pa == rg_tohost_addr &&
rg_st_amo_val != 64'd0 ;
// register rg_victim_way
assign rg_victim_way$D_IN = tmp__h27044[0] ;
assign rg_victim_way$EN = WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_watch_tohost
assign rg_watch_tohost$D_IN = set_watch_tohost_watch_tohost ;
assign rg_watch_tohost$EN = EN_set_watch_tohost ;
// register rg_wr_rsp_err
assign rg_wr_rsp_err$D_IN = 1'd1 ;
assign rg_wr_rsp_err$EN =
WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 ;
// submodule f_fabric_write_reqs
always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
MUX_f_fabric_write_reqs$enq_1__VAL_1 or
MUX_f_fabric_write_reqs$enq_1__SEL_2 or
MUX_f_fabric_write_reqs$enq_1__VAL_2 or
WILL_FIRE_RL_rl_io_write_req or
MUX_f_fabric_write_reqs$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_2:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_1;
MUX_f_fabric_write_reqs$enq_1__SEL_2:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_2;
WILL_FIRE_RL_rl_io_write_req:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_3;
default: f_fabric_write_reqs$D_IN =
131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_fabric_write_reqs$ENQ =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d529 ||
WILL_FIRE_RL_rl_io_write_req ;
assign f_fabric_write_reqs$DEQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign f_fabric_write_reqs$CLR = 1'b0 ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = !EN_server_reset_request_put ;
assign f_reset_reqs$ENQ =
EN_server_reset_request_put || EN_server_flush_request_put ;
assign f_reset_reqs$DEQ =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ;
assign f_reset_rsps$ENQ =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
assign f_reset_rsps$DEQ =
EN_server_flush_response_get || EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule master_xactor_f_rd_addr
assign master_xactor_f_rd_addr$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ?
MUX_master_xactor_f_rd_addr$enq_1__VAL_1 :
MUX_master_xactor_f_rd_addr$enq_1__VAL_2 ;
assign master_xactor_f_rd_addr$ENQ =
WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ||
WILL_FIRE_RL_rl_start_cache_refill ;
assign master_xactor_f_rd_addr$DEQ =
master_xactor_f_rd_addr$EMPTY_N && mem_master_arready ;
assign master_xactor_f_rd_addr$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_rd_data
assign master_xactor_f_rd_data$D_IN =
{ mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast } ;
assign master_xactor_f_rd_data$ENQ =
mem_master_rvalid && master_xactor_f_rd_data$FULL_N ;
assign master_xactor_f_rd_data$DEQ =
WILL_FIRE_RL_rl_io_AMO_read_rsp || WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop ;
assign master_xactor_f_rd_data$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_addr
assign master_xactor_f_wr_addr$D_IN =
{ 4'd0,
f_fabric_write_reqs$D_OUT[127:64],
8'd0,
x__h2801,
18'd65536 } ;
assign master_xactor_f_wr_addr$ENQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign master_xactor_f_wr_addr$DEQ =
master_xactor_f_wr_addr$EMPTY_N && mem_master_awready ;
assign master_xactor_f_wr_addr$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_data
assign master_xactor_f_wr_data$D_IN =
{ mem_req_wr_data_wdata__h2980,
mem_req_wr_data_wstrb__h2981,
1'd1 } ;
assign master_xactor_f_wr_data$ENQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign master_xactor_f_wr_data$DEQ =
master_xactor_f_wr_data$EMPTY_N && mem_master_wready ;
assign master_xactor_f_wr_data$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_resp
assign master_xactor_f_wr_resp$D_IN = { mem_master_bid, mem_master_bresp } ;
assign master_xactor_f_wr_resp$ENQ =
mem_master_bvalid && master_xactor_f_wr_resp$FULL_N ;
assign master_xactor_f_wr_resp$DEQ = CAN_FIRE_RL_rl_discard_write_rsp ;
assign master_xactor_f_wr_resp$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule ram_cword_set
assign ram_cword_set$ADDRA =
MUX_ram_cword_set$a_put_1__SEL_1 ?
rg_cset_cword_in_cache :
rg_addr[11:3] ;
always@(MUX_ram_cword_set$b_put_1__SEL_1 or
req_addr or
MUX_ram_cword_set$b_put_1__SEL_2 or
MUX_ram_cword_set$b_put_2__VAL_2 or
WILL_FIRE_RL_rl_rereq or
rg_addr or
WILL_FIRE_RL_rl_start_cache_refill or
MUX_ram_cword_set$b_put_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_ram_cword_set$b_put_1__SEL_1: ram_cword_set$ADDRB = req_addr[11:3];
MUX_ram_cword_set$b_put_1__SEL_2:
ram_cword_set$ADDRB = MUX_ram_cword_set$b_put_2__VAL_2;
WILL_FIRE_RL_rl_rereq: ram_cword_set$ADDRB = rg_addr[11:3];
WILL_FIRE_RL_rl_start_cache_refill:
ram_cword_set$ADDRB = MUX_ram_cword_set$b_put_2__VAL_4;
default: ram_cword_set$ADDRB = 9'b010101010 /* unspecified value */ ;
endcase
end
assign ram_cword_set$DIA =
MUX_ram_cword_set$a_put_1__SEL_1 ?
MUX_ram_cword_set$a_put_3__VAL_1 :
MUX_ram_cword_set$a_put_3__VAL_2 ;
always@(MUX_ram_cword_set$b_put_1__SEL_1 or
MUX_ram_cword_set$b_put_1__SEL_2 or
WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill)
begin
case (1'b1) // synopsys parallel_case
MUX_ram_cword_set$b_put_1__SEL_1:
ram_cword_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
MUX_ram_cword_set$b_put_1__SEL_2:
ram_cword_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_rl_rereq:
ram_cword_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_rl_start_cache_refill:
ram_cword_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
default: ram_cword_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign ram_cword_set$WEA = 1'd1 ;
assign ram_cword_set$WEB = 1'd0 ;
assign ram_cword_set$ENA =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d392 ;
assign ram_cword_set$ENB =
EN_req &&
req_f3_BITS_1_TO_0_39_EQ_0b0_40_OR_req_f3_BITS_ETC___d969 ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] != 3'd7 ||
WILL_FIRE_RL_rl_rereq ||
WILL_FIRE_RL_rl_start_cache_refill ;
// submodule ram_state_and_ctag_cset
assign ram_state_and_ctag_cset$ADDRA =
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
rg_addr[11:6] :
rg_cset_in_cache ;
assign ram_state_and_ctag_cset$ADDRB =
MUX_ram_cword_set$b_put_1__SEL_1 ?
req_addr[11:6] :
rg_addr[11:6] ;
assign ram_state_and_ctag_cset$DIA =
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 :
106'h15555555555554AAAAAAAAAAAAA ;
assign ram_state_and_ctag_cset$DIB =
MUX_ram_cword_set$b_put_1__SEL_1 ?
106'h2AAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ :
106'h2AAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign ram_state_and_ctag_cset$WEA = 1'd1 ;
assign ram_state_and_ctag_cset$WEB = 1'd0 ;
assign ram_state_and_ctag_cset$ENA =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] == 3'd0 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_reset ;
assign ram_state_and_ctag_cset$ENB =
EN_req &&
req_f3_BITS_1_TO_0_39_EQ_0b0_40_OR_req_f3_BITS_ETC___d969 ||
WILL_FIRE_RL_rl_rereq ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = rg_addr ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_NOT_ram_state_and_ctag_cset_b_read__04_BIT__ETC___d151 =
((!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115)) ?
5'd9 :
5'd12 ;
assign IF_NOT_ram_state_and_ctag_cset_b_read__04_BIT__ETC___d447 =
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) ?
n__h20960 :
ram_cword_set$DOB[63:0] ;
assign IF_NOT_ram_state_and_ctag_cset_b_read__04_BIT__ETC___d524 =
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) ?
n__h23896 :
ram_cword_set$DOB[63:0] ;
assign IF_ram_state_and_ctag_cset_b_read__04_BIT_105__ETC___d446 =
(ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) ?
n__h20960 :
ram_cword_set$DOB[127:64] ;
assign IF_ram_state_and_ctag_cset_b_read__04_BIT_105__ETC___d523 =
(ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) ?
n__h23896 :
ram_cword_set$DOB[127:64] ;
assign IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_1_E_ETC___d354 =
(rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ;
assign IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_IF__ETC___d854 =
(rg_addr[2:0] == 3'h0) ? ld_val__h30732 : 64'd0 ;
assign IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_ram_ETC___d339 =
(rg_addr[2:0] == 3'h0) ? word64__h6008 : 64'd0 ;
assign IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC__q31 =
IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC___d346[31:0] ;
assign IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_rg_st_amo_val_ETC___d454 =
(rg_f3 == 3'b010) ?
{ {32{rg_st_amo_val_BITS_31_TO_0__q32[31]}},
rg_st_amo_val_BITS_31_TO_0__q32 } :
rg_st_amo_val ;
assign IF_rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_ETC___d153 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
5'd9 :
IF_rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_ETC___d152 ;
assign IF_rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_ETC___d120 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h20171 ||
f_fabric_write_reqs$FULL_N :
NOT_ram_state_and_ctag_cset_b_read__04_BIT_52__ETC___d119 ;
assign IF_rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_ETC___d152 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
5'd12 :
IF_NOT_ram_state_and_ctag_cset_b_read__04_BIT__ETC___d151 ;
assign IF_rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_ETC___d531 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
rg_st_amo_val :
new_st_val__h23732 ;
assign NOT_cfg_verbosity_read__1_ULE_1_2___d43 = cfg_verbosity > 4'd1 ;
assign NOT_cfg_verbosity_read__1_ULE_2_97___d598 = cfg_verbosity > 4'd2 ;
assign NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d161 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109 &&
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115 ;
assign NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d360 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d358 ;
assign NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d368 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d358 ;
assign NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d371 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
NOT_ram_state_and_ctag_cset_b_read__04_BIT_52__ETC___d369 ;
assign NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d377 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
NOT_ram_state_and_ctag_cset_b_read__04_BIT_52__ETC___d374 ;
assign NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d381 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
NOT_rg_op_3_EQ_1_1_73_AND_ram_state_and_ctag_c_ETC___d378) ;
assign NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d392 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d390 ;
assign NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d534 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 &&
rg_addr_9_EQ_rg_lrsc_pa_7___d165 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 ;
assign NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d546 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 ;
assign NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d576 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
NOT_rg_op_3_EQ_1_1_73_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d389 ;
assign NOT_ram_state_and_ctag_cset_b_read__04_BIT_52__ETC___d119 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) ||
f_fabric_write_reqs$FULL_N ;
assign NOT_ram_state_and_ctag_cset_b_read__04_BIT_52__ETC___d167 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
rg_addr_9_EQ_rg_lrsc_pa_7___d165 ;
assign NOT_ram_state_and_ctag_cset_b_read__04_BIT_52__ETC___d369 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 ;
assign NOT_ram_state_and_ctag_cset_b_read__04_BIT_52__ETC___d374 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) &&
rg_addr_9_EQ_rg_lrsc_pa_7___d165 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 ;
assign NOT_req_f3_BITS_1_TO_0_39_EQ_0b0_40_41_AND_NOT_ETC___d960 =
req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) &&
(req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) &&
(req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ;
assign NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d148 =
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_7_EQ_rg_addr_9___d98) ;
assign NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d529 =
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d527 ||
NOT_rg_op_3_EQ_1_1_73_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d389) ;
assign NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d549 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_3_EQ_2_5_40_OR_NOT_rg_amo_funct7_6_B_ETC___d547 ;
assign NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d557 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_3_EQ_2_5_40_OR_NOT_rg_amo_funct7_6_B_ETC___d555 ;
assign NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d569 =
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d358 ;
assign NOT_rg_op_3_EQ_1_1_73_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d389 =
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) ;
assign NOT_rg_op_3_EQ_1_1_73_AND_ram_state_and_ctag_c_ETC___d378 =
rg_op != 2'd1 &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) ;
assign NOT_rg_op_3_EQ_2_5_40_OR_NOT_rg_amo_funct7_6_B_ETC___d387 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_7_EQ_rg_addr_9___d98) &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) ;
assign NOT_rg_op_3_EQ_2_5_40_OR_NOT_rg_amo_funct7_6_B_ETC___d547 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_7_EQ_rg_addr_9___d98) &&
ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d358 ;
assign NOT_rg_op_3_EQ_2_5_40_OR_NOT_rg_amo_funct7_6_B_ETC___d551 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_7_EQ_rg_addr_9___d98) &&
NOT_ram_state_and_ctag_cset_b_read__04_BIT_52__ETC___d369 ;
assign NOT_rg_op_3_EQ_2_5_40_OR_NOT_rg_amo_funct7_6_B_ETC___d555 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_7_EQ_rg_addr_9___d98) &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 ;
assign _theResult___snd_fst__h2988 =
f_fabric_write_reqs$D_OUT[63:0] << shift_bits__h2768 ;
assign access_exc_code__h2535 =
dmem_not_imem ?
((rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
4'd5 :
4'd7) :
4'd1 ;
assign b__h26782 =
CAN_FIRE_RL_rl_fabric_send_write_req ?
ctr_wr_rsps_pending_crg$port0__write_1 :
ctr_wr_rsps_pending_crg ;
assign cline_fabric_addr__h26881 = { rg_pa[63:6], 6'd0 } ;
assign dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d122 =
dmem_not_imem && !soc_map$m_is_mem_addr || rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
IF_rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_ETC___d120 ;
assign ld_val0732_BITS_15_TO_0__q37 = ld_val__h30732[15:0] ;
assign ld_val0732_BITS_15_TO_8__q39 = ld_val__h30732[15:8] ;
assign ld_val0732_BITS_23_TO_16__q40 = ld_val__h30732[23:16] ;
assign ld_val0732_BITS_31_TO_0__q38 = ld_val__h30732[31:0] ;
assign ld_val0732_BITS_31_TO_16__q41 = ld_val__h30732[31:16] ;
assign ld_val0732_BITS_31_TO_24__q42 = ld_val__h30732[31:24] ;
assign ld_val0732_BITS_39_TO_32__q43 = ld_val__h30732[39:32] ;
assign ld_val0732_BITS_47_TO_32__q44 = ld_val__h30732[47:32] ;
assign ld_val0732_BITS_47_TO_40__q46 = ld_val__h30732[47:40] ;
assign ld_val0732_BITS_55_TO_48__q47 = ld_val__h30732[55:48] ;
assign ld_val0732_BITS_63_TO_32__q45 = ld_val__h30732[63:32] ;
assign ld_val0732_BITS_63_TO_48__q48 = ld_val__h30732[63:48] ;
assign ld_val0732_BITS_63_TO_56__q49 = ld_val__h30732[63:56] ;
assign ld_val0732_BITS_7_TO_0__q36 = ld_val__h30732[7:0] ;
assign lrsc_result__h20171 =
!rg_lrsc_valid || !rg_lrsc_pa_7_EQ_rg_addr_9___d98 ;
assign master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1 =
master_xactor_f_rd_data$D_OUT[10:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4 =
master_xactor_f_rd_data$D_OUT[18:11] ;
assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2 =
master_xactor_f_rd_data$D_OUT[18:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5 =
master_xactor_f_rd_data$D_OUT[26:19] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6 =
master_xactor_f_rd_data$D_OUT[34:19] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7 =
master_xactor_f_rd_data$D_OUT[34:27] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3 =
master_xactor_f_rd_data$D_OUT[34:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8 =
master_xactor_f_rd_data$D_OUT[42:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9 =
master_xactor_f_rd_data$D_OUT[50:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 =
master_xactor_f_rd_data$D_OUT[50:43] ;
assign master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 =
master_xactor_f_rd_data$D_OUT[58:51] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 =
master_xactor_f_rd_data$D_OUT[66:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 =
master_xactor_f_rd_data$D_OUT[66:51] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 =
master_xactor_f_rd_data$D_OUT[66:59] ;
assign new_st_val__h23732 =
(rg_f3 == 3'b010) ?
new_st_val__h24038 :
_theResult_____2__h24034 ;
assign new_st_val__h24038 = { 32'd0, _theResult_____2__h24034[31:0] } ;
assign new_st_val__h24129 =
IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_IF_rg_f3_53_E_ETC___d385 +
IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_rg_st_amo_val_ETC___d454 ;
assign new_st_val__h25109 = w1__h24026 ^ w2__h32980 ;
assign new_st_val__h25113 = w1__h24026 & w2__h32980 ;
assign new_st_val__h25117 = w1__h24026 | w2__h32980 ;
assign new_st_val__h25121 =
(w1__h24026 < w2__h32980) ? w1__h24026 : w2__h32980 ;
assign new_st_val__h25126 =
(w1__h24026 <= w2__h32980) ? w2__h32980 : w1__h24026 ;
assign new_st_val__h25132 =
((IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_IF_rg_f3_53_E_ETC___d385 ^
64'h8000000000000000) <
(IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_rg_st_amo_val_ETC___d454 ^
64'h8000000000000000)) ?
w1__h24026 :
w2__h32980 ;
assign new_st_val__h25137 =
((IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_IF_rg_f3_53_E_ETC___d385 ^
64'h8000000000000000) <=
(IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_rg_st_amo_val_ETC___d454 ^
64'h8000000000000000)) ?
w2__h32980 :
w1__h24026 ;
assign new_st_val__h32990 = { 32'd0, _theResult_____2__h32986[31:0] } ;
assign new_st_val__h33081 =
new_ld_val__h32940 +
IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_rg_st_amo_val_ETC___d454 ;
assign new_st_val__h34941 = w1__h32978 ^ w2__h32980 ;
assign new_st_val__h34945 = w1__h32978 & w2__h32980 ;
assign new_st_val__h34949 = w1__h32978 | w2__h32980 ;
assign new_st_val__h34953 =
(w1__h32978 < w2__h32980) ? w1__h32978 : w2__h32980 ;
assign new_st_val__h34958 =
(w1__h32978 <= w2__h32980) ? w2__h32980 : w1__h32978 ;
assign new_st_val__h34964 =
((new_ld_val__h32940 ^ 64'h8000000000000000) <
(IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_rg_st_amo_val_ETC___d454 ^
64'h8000000000000000)) ?
w1__h32978 :
w2__h32980 ;
assign new_st_val__h34969 =
((new_ld_val__h32940 ^ 64'h8000000000000000) <=
(IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_rg_st_amo_val_ETC___d454 ^
64'h8000000000000000)) ?
w2__h32980 :
w1__h32978 ;
assign new_value__h22600 =
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
64'd1 :
CASE_rg_f3_0b0_IF_rg_addr_9_BITS_2_TO_0_30_EQ__ETC__q52 ;
assign new_value__h6175 =
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
word64__h6008 :
IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC___d346 ;
assign ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115 =
ram_state_and_ctag_cset$DOB[104:53] == rg_addr[63:12] ;
assign ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109 =
ram_state_and_ctag_cset$DOB[51:0] == rg_addr[63:12] ;
assign ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d164 =
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 ;
assign ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d175 =
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) &&
rg_addr_9_EQ_rg_lrsc_pa_7___d165 ;
assign ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d358 =
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 ;
assign ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d571 =
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) &&
rg_addr_9_EQ_rg_lrsc_pa_7___d165 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 ;
assign req_f3_BITS_1_TO_0_39_EQ_0b0_40_OR_req_f3_BITS_ETC___d969 =
req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] ||
req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 ||
req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ;
assign result__h18884 =
{ {56{word64008_BITS_7_TO_0__q15[7]}},
word64008_BITS_7_TO_0__q15 } ;
assign result__h18912 =
{ {56{word64008_BITS_15_TO_8__q18[7]}},
word64008_BITS_15_TO_8__q18 } ;
assign result__h18940 =
{ {56{word64008_BITS_23_TO_16__q19[7]}},
word64008_BITS_23_TO_16__q19 } ;
assign result__h18968 =
{ {56{word64008_BITS_31_TO_24__q21[7]}},
word64008_BITS_31_TO_24__q21 } ;
assign result__h18996 =
{ {56{word64008_BITS_39_TO_32__q22[7]}},
word64008_BITS_39_TO_32__q22 } ;
assign result__h19024 =
{ {56{word64008_BITS_47_TO_40__q25[7]}},
word64008_BITS_47_TO_40__q25 } ;
assign result__h19052 =
{ {56{word64008_BITS_55_TO_48__q26[7]}},
word64008_BITS_55_TO_48__q26 } ;
assign result__h19080 =
{ {56{word64008_BITS_63_TO_56__q28[7]}},
word64008_BITS_63_TO_56__q28 } ;
assign result__h19125 = { 56'd0, word64__h6008[7:0] } ;
assign result__h19153 = { 56'd0, word64__h6008[15:8] } ;
assign result__h19181 = { 56'd0, word64__h6008[23:16] } ;
assign result__h19209 = { 56'd0, word64__h6008[31:24] } ;
assign result__h19237 = { 56'd0, word64__h6008[39:32] } ;
assign result__h19265 = { 56'd0, word64__h6008[47:40] } ;
assign result__h19293 = { 56'd0, word64__h6008[55:48] } ;
assign result__h19321 = { 56'd0, word64__h6008[63:56] } ;
assign result__h19366 =
{ {48{word64008_BITS_15_TO_0__q16[15]}},
word64008_BITS_15_TO_0__q16 } ;
assign result__h19394 =
{ {48{word64008_BITS_31_TO_16__q20[15]}},
word64008_BITS_31_TO_16__q20 } ;
assign result__h19422 =
{ {48{word64008_BITS_47_TO_32__q23[15]}},
word64008_BITS_47_TO_32__q23 } ;
assign result__h19450 =
{ {48{word64008_BITS_63_TO_48__q27[15]}},
word64008_BITS_63_TO_48__q27 } ;
assign result__h19491 = { 48'd0, word64__h6008[15:0] } ;
assign result__h19519 = { 48'd0, word64__h6008[31:16] } ;
assign result__h19547 = { 48'd0, word64__h6008[47:32] } ;
assign result__h19575 = { 48'd0, word64__h6008[63:48] } ;
assign result__h19616 =
{ {32{word64008_BITS_31_TO_0__q17[31]}},
word64008_BITS_31_TO_0__q17 } ;
assign result__h19644 =
{ {32{word64008_BITS_63_TO_32__q24[31]}},
word64008_BITS_63_TO_32__q24 } ;
assign result__h19683 = { 32'd0, word64__h6008[31:0] } ;
assign result__h19711 = { 32'd0, word64__h6008[63:32] } ;
assign result__h30792 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1[7]}},
master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1 } ;
assign result__h30822 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4[7]}},
master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4 } ;
assign result__h30849 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5[7]}},
master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5 } ;
assign result__h30876 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7[7]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7 } ;
assign result__h30903 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8[7]}},
master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8 } ;
assign result__h30930 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11[7]}},
master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 } ;
assign result__h30957 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12[7]}},
master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 } ;
assign result__h30984 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14[7]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 } ;
assign result__h31028 = { 56'd0, master_xactor_f_rd_data$D_OUT[10:3] } ;
assign result__h31055 = { 56'd0, master_xactor_f_rd_data$D_OUT[18:11] } ;
assign result__h31082 = { 56'd0, master_xactor_f_rd_data$D_OUT[26:19] } ;
assign result__h31109 = { 56'd0, master_xactor_f_rd_data$D_OUT[34:27] } ;
assign result__h31136 = { 56'd0, master_xactor_f_rd_data$D_OUT[42:35] } ;
assign result__h31163 = { 56'd0, master_xactor_f_rd_data$D_OUT[50:43] } ;
assign result__h31190 = { 56'd0, master_xactor_f_rd_data$D_OUT[58:51] } ;
assign result__h31217 = { 56'd0, master_xactor_f_rd_data$D_OUT[66:59] } ;
assign result__h31261 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2[15]}},
master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2 } ;
assign result__h31288 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6[15]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6 } ;
assign result__h31315 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9[15]}},
master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9 } ;
assign result__h31342 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13[15]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 } ;
assign result__h31382 = { 48'd0, master_xactor_f_rd_data$D_OUT[18:3] } ;
assign result__h31409 = { 48'd0, master_xactor_f_rd_data$D_OUT[34:19] } ;
assign result__h31436 = { 48'd0, master_xactor_f_rd_data$D_OUT[50:35] } ;
assign result__h31463 = { 48'd0, master_xactor_f_rd_data$D_OUT[66:51] } ;
assign result__h31503 =
{ {32{master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3[31]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3 } ;
assign result__h31530 =
{ {32{master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10[31]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 } ;
assign result__h31568 = { 32'd0, master_xactor_f_rd_data$D_OUT[34:3] } ;
assign result__h31595 = { 32'd0, master_xactor_f_rd_data$D_OUT[66:35] } ;
assign result__h33169 =
{ {56{ld_val0732_BITS_7_TO_0__q36[7]}},
ld_val0732_BITS_7_TO_0__q36 } ;
assign result__h34077 =
{ {56{ld_val0732_BITS_15_TO_8__q39[7]}},
ld_val0732_BITS_15_TO_8__q39 } ;
assign result__h34105 =
{ {56{ld_val0732_BITS_23_TO_16__q40[7]}},
ld_val0732_BITS_23_TO_16__q40 } ;
assign result__h34133 =
{ {56{ld_val0732_BITS_31_TO_24__q42[7]}},
ld_val0732_BITS_31_TO_24__q42 } ;
assign result__h34161 =
{ {56{ld_val0732_BITS_39_TO_32__q43[7]}},
ld_val0732_BITS_39_TO_32__q43 } ;
assign result__h34189 =
{ {56{ld_val0732_BITS_47_TO_40__q46[7]}},
ld_val0732_BITS_47_TO_40__q46 } ;
assign result__h34217 =
{ {56{ld_val0732_BITS_55_TO_48__q47[7]}},
ld_val0732_BITS_55_TO_48__q47 } ;
assign result__h34245 =
{ {56{ld_val0732_BITS_63_TO_56__q49[7]}},
ld_val0732_BITS_63_TO_56__q49 } ;
assign result__h34290 = { 56'd0, ld_val__h30732[7:0] } ;
assign result__h34318 = { 56'd0, ld_val__h30732[15:8] } ;
assign result__h34346 = { 56'd0, ld_val__h30732[23:16] } ;
assign result__h34374 = { 56'd0, ld_val__h30732[31:24] } ;
assign result__h34402 = { 56'd0, ld_val__h30732[39:32] } ;
assign result__h34430 = { 56'd0, ld_val__h30732[47:40] } ;
assign result__h34458 = { 56'd0, ld_val__h30732[55:48] } ;
assign result__h34486 = { 56'd0, ld_val__h30732[63:56] } ;
assign result__h34531 =
{ {48{ld_val0732_BITS_15_TO_0__q37[15]}},
ld_val0732_BITS_15_TO_0__q37 } ;
assign result__h34559 =
{ {48{ld_val0732_BITS_31_TO_16__q41[15]}},
ld_val0732_BITS_31_TO_16__q41 } ;
assign result__h34587 =
{ {48{ld_val0732_BITS_47_TO_32__q44[15]}},
ld_val0732_BITS_47_TO_32__q44 } ;
assign result__h34615 =
{ {48{ld_val0732_BITS_63_TO_48__q48[15]}},
ld_val0732_BITS_63_TO_48__q48 } ;
assign result__h34656 = { 48'd0, ld_val__h30732[15:0] } ;
assign result__h34684 = { 48'd0, ld_val__h30732[31:16] } ;
assign result__h34712 = { 48'd0, ld_val__h30732[47:32] } ;
assign result__h34740 = { 48'd0, ld_val__h30732[63:48] } ;
assign result__h34781 =
{ {32{ld_val0732_BITS_31_TO_0__q38[31]}},
ld_val0732_BITS_31_TO_0__q38 } ;
assign result__h34809 =
{ {32{ld_val0732_BITS_63_TO_32__q45[31]}},
ld_val0732_BITS_63_TO_32__q45 } ;
assign result__h34848 = { 32'd0, ld_val__h30732[31:0] } ;
assign result__h34876 = { 32'd0, ld_val__h30732[63:32] } ;
assign rg_addr_9_EQ_rg_lrsc_pa_7___d165 = rg_addr == rg_lrsc_pa ;
assign rg_amo_funct7_6_BITS_6_TO_2_7_EQ_0b10_8_AND_ra_ETC___d363 =
rg_amo_funct7[6:2] == 5'b00010 &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) ;
assign rg_lrsc_pa_7_EQ_rg_addr_9___d98 = rg_lrsc_pa == rg_addr ;
assign rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d138 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) ;
assign rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d169 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d164 ||
NOT_ram_state_and_ctag_cset_b_read__04_BIT_52__ETC___d167) ;
assign rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d179 =
rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d169 ||
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d177 ;
assign rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d181 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115) ;
assign rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d184 =
rg_op_3_EQ_0_4_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d181 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h20171 ;
assign rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d177 =
rg_op == 2'd1 && rg_addr_9_EQ_rg_lrsc_pa_7___d165 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d175 ;
assign rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d390 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_3_EQ_2_5_40_OR_NOT_rg_amo_funct7_6_B_ETC___d387 ||
NOT_rg_op_3_EQ_1_1_73_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d389 ;
assign rg_op_3_EQ_1_1_OR_rg_op_3_EQ_2_5_AND_rg_amo_fu_ETC___d527 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_7_EQ_rg_addr_9___d98) ;
assign rg_op_3_EQ_2_5_AND_rg_amo_funct7_6_BITS_6_TO_2_ETC___d561 =
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h20171 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 ;
assign rg_st_amo_val_BITS_31_TO_0__q32 = rg_st_amo_val[31:0] ;
assign rg_state_6_EQ_13_54_AND_rg_op_3_EQ_0_4_OR_rg_o_ETC___d656 =
rg_state == 5'd13 &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
b__h26782 == 4'd0 ;
assign shift_bits__h2768 = { f_fabric_write_reqs$D_OUT[66:64], 3'b0 } ;
assign strobe64__h2918 = 8'b00000001 << f_fabric_write_reqs$D_OUT[66:64] ;
assign strobe64__h2920 = 8'b00000011 << f_fabric_write_reqs$D_OUT[66:64] ;
assign strobe64__h2922 = 8'b00001111 << f_fabric_write_reqs$D_OUT[66:64] ;
assign tmp__h27043 = { 1'd0, rg_victim_way } ;
assign tmp__h27044 = tmp__h27043 + 2'd1 ;
assign w12974_BITS_31_TO_0__q51 = w1__h32974[31:0] ;
assign w1___1__h24097 =
{ 32'd0,
IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC___d346[31:0] } ;
assign w1___1__h33049 = { 32'd0, w1__h32974[31:0] } ;
assign w2___1__h33050 = { 32'd0, rg_st_amo_val[31:0] } ;
assign w2__h32980 = (rg_f3 == 3'b010) ? w2___1__h33050 : rg_st_amo_val ;
assign word64008_BITS_15_TO_0__q16 = word64__h6008[15:0] ;
assign word64008_BITS_15_TO_8__q18 = word64__h6008[15:8] ;
assign word64008_BITS_23_TO_16__q19 = word64__h6008[23:16] ;
assign word64008_BITS_31_TO_0__q17 = word64__h6008[31:0] ;
assign word64008_BITS_31_TO_16__q20 = word64__h6008[31:16] ;
assign word64008_BITS_31_TO_24__q21 = word64__h6008[31:24] ;
assign word64008_BITS_39_TO_32__q22 = word64__h6008[39:32] ;
assign word64008_BITS_47_TO_32__q23 = word64__h6008[47:32] ;
assign word64008_BITS_47_TO_40__q25 = word64__h6008[47:40] ;
assign word64008_BITS_55_TO_48__q26 = word64__h6008[55:48] ;
assign word64008_BITS_63_TO_32__q24 = word64__h6008[63:32] ;
assign word64008_BITS_63_TO_48__q27 = word64__h6008[63:48] ;
assign word64008_BITS_63_TO_56__q28 = word64__h6008[63:56] ;
assign word64008_BITS_7_TO_0__q15 = word64__h6008[7:0] ;
assign word64__h6008 = x__h6198 | y__h6199 ;
assign x__h20181 = { 63'd0, lrsc_result__h20171 } ;
assign x__h32969 =
(rg_f3 == 3'b010) ?
new_st_val__h32990 :
_theResult_____2__h32986 ;
assign x__h6198 = ram_cword_set$DOB[63:0] & y__h6213 ;
assign y__h12528 =
{64{ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115}} ;
assign y__h6199 = ram_cword_set$DOB[127:64] & y__h12528 ;
assign y__h6213 =
{64{ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__04_BITS_51_TO__ETC___d109}} ;
always@(f_fabric_write_reqs$D_OUT)
begin
case (f_fabric_write_reqs$D_OUT[129:128])
2'b0: x__h2801 = 3'b0;
2'b01: x__h2801 = 3'b001;
2'b10: x__h2801 = 3'b010;
2'b11: x__h2801 = 3'b011;
endcase
end
always@(rg_f3)
begin
case (rg_f3[1:0])
2'b0: value__h32526 = 3'b0;
2'b01: value__h32526 = 3'b001;
2'b10: value__h32526 = 3'b010;
2'd3: value__h32526 = 3'b011;
endcase
end
always@(f_fabric_write_reqs$D_OUT or
strobe64__h2918 or strobe64__h2920 or strobe64__h2922)
begin
case (f_fabric_write_reqs$D_OUT[129:128])
2'b0: mem_req_wr_data_wstrb__h2981 = strobe64__h2918;
2'b01: mem_req_wr_data_wstrb__h2981 = strobe64__h2920;
2'b10: mem_req_wr_data_wstrb__h2981 = strobe64__h2922;
2'b11: mem_req_wr_data_wstrb__h2981 = 8'b11111111;
endcase
end
always@(f_fabric_write_reqs$D_OUT or _theResult___snd_fst__h2988)
begin
case (f_fabric_write_reqs$D_OUT[129:128])
2'b0, 2'b01, 2'b10:
mem_req_wr_data_wdata__h2980 = _theResult___snd_fst__h2988;
2'd3: mem_req_wr_data_wdata__h2980 = f_fabric_write_reqs$D_OUT[63:0];
endcase
end
always@(ram_state_and_ctag_cset$DOB or
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115 or
ram_cword_set$DOB)
begin
case (ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__04_BITS_104_TO_ETC___d115)
1'd0: old_cword__h20949 = ram_cword_set$DOB[63:0];
1'd1: old_cword__h20949 = ram_cword_set$DOB[127:64];
endcase
end
always@(rg_addr or
result__h18884 or
result__h18912 or
result__h18940 or
result__h18968 or
result__h18996 or
result__h19024 or result__h19052 or result__h19080)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286 =
result__h18884;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286 =
result__h18912;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286 =
result__h18940;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286 =
result__h18968;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286 =
result__h18996;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286 =
result__h19024;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286 =
result__h19052;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286 =
result__h19080;
endcase
end
always@(rg_addr or
result__h19125 or
result__h19153 or
result__h19181 or
result__h19209 or
result__h19237 or
result__h19265 or result__h19293 or result__h19321)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303 =
result__h19125;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303 =
result__h19153;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303 =
result__h19181;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303 =
result__h19209;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303 =
result__h19237;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303 =
result__h19265;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303 =
result__h19293;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303 =
result__h19321;
endcase
end
always@(rg_addr or
result__h19366 or
result__h19394 or result__h19422 or result__h19450)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d316 =
result__h19366;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d316 =
result__h19394;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d316 =
result__h19422;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d316 =
result__h19450;
default: IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d316 =
64'd0;
endcase
end
always@(rg_addr or result__h19683 or result__h19711)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d337 =
result__h19683;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d337 =
result__h19711;
default: IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d337 =
64'd0;
endcase
end
always@(rg_addr or
result__h19491 or
result__h19519 or result__h19547 or result__h19575)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d325 =
result__h19491;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d325 =
result__h19519;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d325 =
result__h19547;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d325 =
result__h19575;
default: IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d325 =
64'd0;
endcase
end
always@(rg_addr or result__h19616 or result__h19644)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result9616_0x4_re_ETC__q29 =
result__h19616;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result9616_0x4_re_ETC__q29 =
result__h19644;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result9616_0x4_re_ETC__q29 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d316 or
CASE_rg_addr_BITS_2_TO_0_0x0_result9616_0x4_re_ETC__q29 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_ram_ETC___d339 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d325 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d337)
begin
case (rg_f3)
3'b0:
IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC___d346 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286;
3'b001:
IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC___d346 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d316;
3'b010:
IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC___d346 =
CASE_rg_addr_BITS_2_TO_0_0x0_result9616_0x4_re_ETC__q29;
3'b011:
IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC___d346 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_ram_ETC___d339;
3'b100:
IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC___d346 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303;
3'b101:
IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC___d346 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d325;
3'b110:
IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC___d346 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d337;
3'd7: IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC___d346 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d316 or
w1___1__h24097 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_ram_ETC___d339 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d325 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d337)
begin
case (rg_f3)
3'b0:
w1__h24026 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286;
3'b001:
w1__h24026 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d316;
3'b010: w1__h24026 = w1___1__h24097;
3'b011:
w1__h24026 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_ram_ETC___d339;
3'b100:
w1__h24026 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303;
3'b101:
w1__h24026 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d325;
3'b110:
w1__h24026 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d337;
3'd7: w1__h24026 = 64'd0;
endcase
end
always@(rg_addr or old_cword__h20949 or rg_st_amo_val)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d436 =
{ old_cword__h20949[63:16], rg_st_amo_val[15:0] };
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d436 =
{ old_cword__h20949[63:32],
rg_st_amo_val[15:0],
old_cword__h20949[15:0] };
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d436 =
{ old_cword__h20949[63:48],
rg_st_amo_val[15:0],
old_cword__h20949[31:0] };
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d436 =
{ rg_st_amo_val[15:0], old_cword__h20949[47:0] };
default: IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d436 =
old_cword__h20949;
endcase
end
always@(rg_addr or old_cword__h20949 or rg_st_amo_val)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d427 =
{ old_cword__h20949[63:8], rg_st_amo_val[7:0] };
3'h1:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d427 =
{ old_cword__h20949[63:16],
rg_st_amo_val[7:0],
old_cword__h20949[7:0] };
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d427 =
{ old_cword__h20949[63:24],
rg_st_amo_val[7:0],
old_cword__h20949[15:0] };
3'h3:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d427 =
{ old_cword__h20949[63:32],
rg_st_amo_val[7:0],
old_cword__h20949[23:0] };
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d427 =
{ old_cword__h20949[63:40],
rg_st_amo_val[7:0],
old_cword__h20949[31:0] };
3'h5:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d427 =
{ old_cword__h20949[63:48],
rg_st_amo_val[7:0],
old_cword__h20949[39:0] };
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d427 =
{ old_cword__h20949[63:56],
rg_st_amo_val[7:0],
old_cword__h20949[47:0] };
3'h7:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d427 =
{ rg_st_amo_val[7:0], old_cword__h20949[55:0] };
endcase
end
always@(rg_addr or old_cword__h20949 or rg_st_amo_val)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_old_cword0949_BIT_ETC__q30 =
{ old_cword__h20949[63:32], rg_st_amo_val[31:0] };
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_old_cword0949_BIT_ETC__q30 =
{ rg_st_amo_val[31:0], old_cword__h20949[31:0] };
default: CASE_rg_addr_BITS_2_TO_0_0x0_old_cword0949_BIT_ETC__q30 =
old_cword__h20949;
endcase
end
always@(rg_f3 or
old_cword__h20949 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d427 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d436 or
CASE_rg_addr_BITS_2_TO_0_0x0_old_cword0949_BIT_ETC__q30 or
rg_st_amo_val)
begin
case (rg_f3)
3'b0:
n__h20960 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d427;
3'b001:
n__h20960 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d436;
3'b010:
n__h20960 = CASE_rg_addr_BITS_2_TO_0_0x0_old_cword0949_BIT_ETC__q30;
3'b011: n__h20960 = rg_st_amo_val;
default: n__h20960 = old_cword__h20949;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d316 or
IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC__q31 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_ram_ETC___d339 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d325 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d337)
begin
case (rg_f3)
3'b0:
IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_IF_rg_f3_53_E_ETC___d385 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d286;
3'b001:
IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_IF_rg_f3_53_E_ETC___d385 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d316;
3'b010:
IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_IF_rg_f3_53_E_ETC___d385 =
{ {32{IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC__q31[31]}},
IF_rg_f3_53_EQ_0b0_54_THEN_IF_rg_addr_9_BITS_2_ETC__q31 };
3'b011:
IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_IF_rg_f3_53_E_ETC___d385 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_ram_ETC___d339;
3'b100:
IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_IF_rg_f3_53_E_ETC___d385 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d303;
3'b101:
IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_IF_rg_f3_53_E_ETC___d385 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d325;
3'b110:
IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_IF_rg_f3_53_E_ETC___d385 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d337;
3'd7: IF_rg_f3_53_EQ_0b10_26_THEN_SEXT_IF_rg_f3_53_E_ETC___d385 = 64'd0;
endcase
end
always@(rg_amo_funct7 or
new_st_val__h25137 or
new_st_val__h24129 or
w2__h32980 or
new_st_val__h25109 or
new_st_val__h25117 or
new_st_val__h25113 or
new_st_val__h25132 or new_st_val__h25121 or new_st_val__h25126)
begin
case (rg_amo_funct7[6:2])
5'b0: _theResult_____2__h24034 = new_st_val__h24129;
5'b00001: _theResult_____2__h24034 = w2__h32980;
5'b00100: _theResult_____2__h24034 = new_st_val__h25109;
5'b01000: _theResult_____2__h24034 = new_st_val__h25117;
5'b01100: _theResult_____2__h24034 = new_st_val__h25113;
5'b10000: _theResult_____2__h24034 = new_st_val__h25132;
5'b11000: _theResult_____2__h24034 = new_st_val__h25121;
5'b11100: _theResult_____2__h24034 = new_st_val__h25126;
default: _theResult_____2__h24034 = new_st_val__h25137;
endcase
end
always@(rg_addr or old_cword__h20949 or new_st_val__h23732)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d513 =
{ old_cword__h20949[63:16], new_st_val__h23732[15:0] };
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d513 =
{ old_cword__h20949[63:32],
new_st_val__h23732[15:0],
old_cword__h20949[15:0] };
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d513 =
{ old_cword__h20949[63:48],
new_st_val__h23732[15:0],
old_cword__h20949[31:0] };
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d513 =
{ new_st_val__h23732[15:0], old_cword__h20949[47:0] };
default: IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d513 =
old_cword__h20949;
endcase
end
always@(rg_addr or old_cword__h20949 or new_st_val__h23732)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d504 =
{ old_cword__h20949[63:8], new_st_val__h23732[7:0] };
3'h1:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d504 =
{ old_cword__h20949[63:16],
new_st_val__h23732[7:0],
old_cword__h20949[7:0] };
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d504 =
{ old_cword__h20949[63:24],
new_st_val__h23732[7:0],
old_cword__h20949[15:0] };
3'h3:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d504 =
{ old_cword__h20949[63:32],
new_st_val__h23732[7:0],
old_cword__h20949[23:0] };
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d504 =
{ old_cword__h20949[63:40],
new_st_val__h23732[7:0],
old_cword__h20949[31:0] };
3'h5:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d504 =
{ old_cword__h20949[63:48],
new_st_val__h23732[7:0],
old_cword__h20949[39:0] };
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d504 =
{ old_cword__h20949[63:56],
new_st_val__h23732[7:0],
old_cword__h20949[47:0] };
3'h7:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d504 =
{ new_st_val__h23732[7:0], old_cword__h20949[55:0] };
endcase
end
always@(rg_addr or old_cword__h20949 or new_st_val__h23732)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_old_cword0949_BIT_ETC__q33 =
{ old_cword__h20949[63:32], new_st_val__h23732[31:0] };
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_old_cword0949_BIT_ETC__q33 =
{ new_st_val__h23732[31:0], old_cword__h20949[31:0] };
default: CASE_rg_addr_BITS_2_TO_0_0x0_old_cword0949_BIT_ETC__q33 =
old_cword__h20949;
endcase
end
always@(rg_f3 or
old_cword__h20949 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d504 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d513 or
CASE_rg_addr_BITS_2_TO_0_0x0_old_cword0949_BIT_ETC__q33 or
new_st_val__h23732)
begin
case (rg_f3)
3'b0:
n__h23896 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d504;
3'b001:
n__h23896 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEL_ETC___d513;
3'b010:
n__h23896 = CASE_rg_addr_BITS_2_TO_0_0x0_old_cword0949_BIT_ETC__q33;
3'b011: n__h23896 = new_st_val__h23732;
default: n__h23896 = old_cword__h20949;
endcase
end
always@(rg_addr or
result__h31382 or
result__h31409 or result__h31436 or result__h31463)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d734 =
result__h31382;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d734 =
result__h31409;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d734 =
result__h31436;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d734 =
result__h31463;
default: IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d734 =
64'd0;
endcase
end
always@(rg_addr or
result__h31028 or
result__h31055 or
result__h31082 or
result__h31109 or
result__h31136 or
result__h31163 or result__h31190 or result__h31217)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d714 =
result__h31028;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d714 =
result__h31055;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d714 =
result__h31082;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d714 =
result__h31109;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d714 =
result__h31136;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d714 =
result__h31163;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d714 =
result__h31190;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d714 =
result__h31217;
endcase
end
always@(rg_addr or
result__h31261 or
result__h31288 or result__h31315 or result__h31342)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d726 =
result__h31261;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d726 =
result__h31288;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d726 =
result__h31315;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d726 =
result__h31342;
default: IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d726 =
64'd0;
endcase
end
always@(rg_addr or
result__h30792 or
result__h30822 or
result__h30849 or
result__h30876 or
result__h30903 or
result__h30930 or result__h30957 or result__h30984)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d698 =
result__h30792;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d698 =
result__h30822;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d698 =
result__h30849;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d698 =
result__h30876;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d698 =
result__h30903;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d698 =
result__h30930;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d698 =
result__h30957;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d698 =
result__h30984;
endcase
end
always@(rg_addr or result__h31503 or result__h31530)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result1503_0x4_re_ETC__q34 =
result__h31503;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result1503_0x4_re_ETC__q34 =
result__h31530;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result1503_0x4_re_ETC__q34 =
64'd0;
endcase
end
always@(rg_addr or result__h31568 or result__h31595)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result1568_0x4_re_ETC__q35 =
result__h31568;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result1568_0x4_re_ETC__q35 =
result__h31595;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result1568_0x4_re_ETC__q35 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d698 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d726 or
CASE_rg_addr_BITS_2_TO_0_0x0_result1503_0x4_re_ETC__q34 or
rg_addr or
master_xactor_f_rd_data$D_OUT or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d714 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d734 or
CASE_rg_addr_BITS_2_TO_0_0x0_result1568_0x4_re_ETC__q35)
begin
case (rg_f3)
3'b0:
ld_val__h30732 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d698;
3'b001:
ld_val__h30732 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d726;
3'b010:
ld_val__h30732 =
CASE_rg_addr_BITS_2_TO_0_0x0_result1503_0x4_re_ETC__q34;
3'b011:
ld_val__h30732 =
(rg_addr[2:0] == 3'h0) ?
master_xactor_f_rd_data$D_OUT[66:3] :
64'd0;
3'b100:
ld_val__h30732 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d714;
3'b101:
ld_val__h30732 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d734;
3'b110:
ld_val__h30732 =
CASE_rg_addr_BITS_2_TO_0_0x0_result1568_0x4_re_ETC__q35;
3'd7: ld_val__h30732 = 64'd0;
endcase
end
always@(rg_addr or result__h34848 or result__h34876)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d853 =
result__h34848;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d853 =
result__h34876;
default: IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d853 =
64'd0;
endcase
end
always@(rg_addr or
result__h34656 or
result__h34684 or result__h34712 or result__h34740)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d843 =
result__h34656;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d843 =
result__h34684;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d843 =
result__h34712;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d843 =
result__h34740;
default: IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d843 =
64'd0;
endcase
end
always@(rg_addr or
result__h34290 or
result__h34318 or
result__h34346 or
result__h34374 or
result__h34402 or
result__h34430 or result__h34458 or result__h34486)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823 =
result__h34290;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823 =
result__h34318;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823 =
result__h34346;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823 =
result__h34374;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823 =
result__h34402;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823 =
result__h34430;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823 =
result__h34458;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823 =
result__h34486;
endcase
end
always@(rg_addr or
result__h34531 or
result__h34559 or result__h34587 or result__h34615)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d835 =
result__h34531;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d835 =
result__h34559;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d835 =
result__h34587;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d835 =
result__h34615;
default: IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d835 =
64'd0;
endcase
end
always@(rg_addr or
result__h33169 or
result__h34077 or
result__h34105 or
result__h34133 or
result__h34161 or
result__h34189 or result__h34217 or result__h34245)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807 =
result__h33169;
3'h1:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807 =
result__h34077;
3'h2:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807 =
result__h34105;
3'h3:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807 =
result__h34133;
3'h4:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807 =
result__h34161;
3'h5:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807 =
result__h34189;
3'h6:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807 =
result__h34217;
3'h7:
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807 =
result__h34245;
endcase
end
always@(rg_addr or result__h34781 or result__h34809)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result4781_0x4_re_ETC__q50 =
result__h34781;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result4781_0x4_re_ETC__q50 =
result__h34809;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result4781_0x4_re_ETC__q50 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d835 or
CASE_rg_addr_BITS_2_TO_0_0x0_result4781_0x4_re_ETC__q50 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_IF__ETC___d854 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d843 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d853)
begin
case (rg_f3)
3'b0:
w1__h32974 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807;
3'b001:
w1__h32974 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d835;
3'b010:
w1__h32974 =
CASE_rg_addr_BITS_2_TO_0_0x0_result4781_0x4_re_ETC__q50;
3'b011:
w1__h32974 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_IF__ETC___d854;
3'b100:
w1__h32974 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823;
3'b101:
w1__h32974 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d843;
3'b110:
w1__h32974 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d853;
3'd7: w1__h32974 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d835 or
w1___1__h33049 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_IF__ETC___d854 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d843 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d853)
begin
case (rg_f3)
3'b0:
w1__h32978 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807;
3'b001:
w1__h32978 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d835;
3'b010: w1__h32978 = w1___1__h33049;
3'b011:
w1__h32978 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_IF__ETC___d854;
3'b100:
w1__h32978 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823;
3'b101:
w1__h32978 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d843;
3'b110:
w1__h32978 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d853;
3'd7: w1__h32978 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d835 or
w12974_BITS_31_TO_0__q51 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_IF__ETC___d854 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d843 or
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d853)
begin
case (rg_f3)
3'b0:
new_ld_val__h32940 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d807;
3'b001:
new_ld_val__h32940 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_SEX_ETC___d835;
3'b010:
new_ld_val__h32940 =
{ {32{w12974_BITS_31_TO_0__q51[31]}},
w12974_BITS_31_TO_0__q51 };
3'b011:
new_ld_val__h32940 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_IF__ETC___d854;
3'b100:
new_ld_val__h32940 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d823;
3'b101:
new_ld_val__h32940 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d843;
3'b110:
new_ld_val__h32940 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_0_C_ETC___d853;
3'd7: new_ld_val__h32940 = 64'd0;
endcase
end
always@(rg_amo_funct7 or
new_st_val__h34969 or
new_st_val__h33081 or
w2__h32980 or
new_st_val__h34941 or
new_st_val__h34949 or
new_st_val__h34945 or
new_st_val__h34964 or new_st_val__h34953 or new_st_val__h34958)
begin
case (rg_amo_funct7[6:2])
5'b0: _theResult_____2__h32986 = new_st_val__h33081;
5'b00001: _theResult_____2__h32986 = w2__h32980;
5'b00100: _theResult_____2__h32986 = new_st_val__h34941;
5'b01000: _theResult_____2__h32986 = new_st_val__h34949;
5'b01100: _theResult_____2__h32986 = new_st_val__h34945;
5'b10000: _theResult_____2__h32986 = new_st_val__h34964;
5'b11000: _theResult_____2__h32986 = new_st_val__h34953;
5'b11100: _theResult_____2__h32986 = new_st_val__h34958;
default: _theResult_____2__h32986 = new_st_val__h34969;
endcase
end
always@(rg_f3 or IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_1_E_ETC___d354)
begin
case (rg_f3)
3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110:
CASE_rg_f3_0b0_IF_rg_addr_9_BITS_2_TO_0_30_EQ__ETC__q52 =
IF_rg_addr_9_BITS_2_TO_0_30_EQ_0x0_55_THEN_1_E_ETC___d354;
3'd7: CASE_rg_f3_0b0_IF_rg_addr_9_BITS_2_TO_0_30_EQ__ETC__q52 = 64'd0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0;
rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 6'd0;
rg_ddr4_ready <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 5'd0;
rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'h0000000080001000;
rg_tohost_value <= `BSV_ASSIGNMENT_DELAY 64'd0;
rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_wr_rsp_err <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (ctr_wr_rsps_pending_crg$EN)
ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
ctr_wr_rsps_pending_crg$D_IN;
if (rg_cset_in_cache$EN)
rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN;
if (rg_ddr4_ready$EN)
rg_ddr4_ready <= `BSV_ASSIGNMENT_DELAY rg_ddr4_ready$D_IN;
if (rg_lower_word32_full$EN)
rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY
rg_lower_word32_full$D_IN;
if (rg_lrsc_valid$EN)
rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
if (rg_tohost_addr$EN)
rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN;
if (rg_tohost_value$EN)
rg_tohost_value <= `BSV_ASSIGNMENT_DELAY rg_tohost_value$D_IN;
if (rg_watch_tohost$EN)
rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY rg_watch_tohost$D_IN;
if (rg_wr_rsp_err$EN)
rg_wr_rsp_err <= `BSV_ASSIGNMENT_DELAY rg_wr_rsp_err$D_IN;
end
if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN;
if (rg_amo_funct7$EN)
rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN;
if (rg_cset_cword_in_cache$EN)
rg_cset_cword_in_cache <= `BSV_ASSIGNMENT_DELAY
rg_cset_cword_in_cache$D_IN;
if (rg_error_during_refill$EN)
rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY
rg_error_during_refill$D_IN;
if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN;
if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN;
if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN;
if (rg_lower_word32$EN)
rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN;
if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN;
if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN;
if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN;
if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN;
if (rg_st_amo_val$EN)
rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN;
if (rg_victim_way$EN)
rg_victim_way <= `BSV_ASSIGNMENT_DELAY rg_victim_way$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
ctr_wr_rsps_pending_crg = 4'hA;
rg_addr = 64'hAAAAAAAAAAAAAAAA;
rg_amo_funct7 = 7'h2A;
rg_cset_cword_in_cache = 9'h0AA;
rg_cset_in_cache = 6'h2A;
rg_ddr4_ready = 1'h0;
rg_error_during_refill = 1'h0;
rg_exc_code = 4'hA;
rg_f3 = 3'h2;
rg_ld_val = 64'hAAAAAAAAAAAAAAAA;
rg_lower_word32 = 32'hAAAAAAAA;
rg_lower_word32_full = 1'h0;
rg_lrsc_pa = 64'hAAAAAAAAAAAAAAAA;
rg_lrsc_valid = 1'h0;
rg_op = 2'h2;
rg_pa = 64'hAAAAAAAAAAAAAAAA;
rg_pte_pa = 64'hAAAAAAAAAAAAAAAA;
rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA;
rg_state = 5'h0A;
rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA;
rg_tohost_value = 64'hAAAAAAAAAAAAAAAA;
rg_victim_way = 1'h0;
rg_watch_tohost = 1'h0;
rg_wr_rsp_err = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", f_fabric_write_reqs$D_OUT[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", x__h2801);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", mem_req_wr_data_wdata__h2980);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", mem_req_wr_data_wstrb__h2981);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
cfg_verbosity != 4'd0 &&
!f_reset_reqs$D_OUT)
begin
v__h4255 = $stime;
#0;
end
v__h4249 = v__h4255 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
cfg_verbosity != 4'd0 &&
!f_reset_reqs$D_OUT)
if (dmem_not_imem)
$display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
v__h4249,
"D_MMU_Cache",
$signed(32'd64),
$signed(32'd2));
else
$display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
v__h4249,
"I_MMU_Cache",
$signed(32'd64),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
f_reset_reqs$D_OUT)
begin
v__h4354 = $stime;
#0;
end
v__h4348 = v__h4354 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
f_reset_reqs$D_OUT)
if (dmem_not_imem)
$display("%0d: %s.rl_reset: Flushed", v__h4348, "D_MMU_Cache");
else
$display("%0d: %s.rl_reset: Flushed", v__h4348, "I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h4504 = $stime;
#0;
end
v__h4498 = v__h4504 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
v__h4498,
"D_MMU_Cache",
rg_addr);
else
$display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
v__h4498,
"I_MMU_Cache",
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}",
rg_addr[63:12],
rg_addr[11:6],
rg_addr[5:3],
rg_addr[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" CSet 0x%0x: (state, tag):", rg_addr[11:6]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" (");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
ram_state_and_ctag_cset$DOB[52])
$write("CTAG_CLEAN");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
!ram_state_and_ctag_cset$DOB[52])
$write("CTAG_EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
ram_state_and_ctag_cset$DOB[52])
$write(", 0x%0x", ram_state_and_ctag_cset$DOB[51:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
!ram_state_and_ctag_cset$DOB[52])
$write(", --");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(")");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" (");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
ram_state_and_ctag_cset$DOB[105])
$write("CTAG_CLEAN");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
!ram_state_and_ctag_cset$DOB[105])
$write("CTAG_EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
ram_state_and_ctag_cset$DOB[105])
$write(", 0x%0x", ram_state_and_ctag_cset$DOB[104:53]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
!ram_state_and_ctag_cset$DOB[105])
$write(", --");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(")");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" CSet 0x%0x, CWord 0x%0x: ",
rg_addr[11:6],
rg_addr[5:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" 0x%0x", ram_cword_set$DOB[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" 0x%0x", ram_cword_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" TLB result: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("VM_Xlate_Result { ", "outcome: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("VM_XLATE_OK");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "pa: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'hA, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp && dmem_not_imem &&
!soc_map$m_is_mem_addr &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$display(" => IO_REQ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d161)
$display(" ASSERTION ERROR: fn_test_cache_hit_or_miss: multiple hits in set at [%0d] and [%0d]",
$signed(32'd1),
1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d360)
begin
v__h19794 = $stime;
#0;
end
v__h19788 = v__h19794 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d360)
if (dmem_not_imem)
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h19788,
"D_MMU_Cache",
rg_addr,
word64__h6008,
64'd0);
else
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h19788,
"I_MMU_Cache",
rg_addr,
word64__h6008,
64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d368)
$display(" AMO LR: reserving PA 0x%0h", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d360)
$display(" Read-hit: addr 0x%0h word64 0x%0h",
rg_addr,
word64__h6008);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d371)
$display(" Read Miss: -> CACHE_START_REFILL.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d377)
$display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h",
rg_lrsc_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d534)
$display(" ST: cancelling LR/SC reservation for PA", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
rg_lrsc_valid &&
!rg_lrsc_pa_7_EQ_rg_addr_9___d98 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h",
rg_lrsc_pa,
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
!rg_lrsc_valid &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$display(" AMO SC: fail due to invalid LR/SC reservation");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_56_OR_soc_map_m_is_mem_addr__ETC___d546)
$display(" AMO SC result = %0d", lrsc_result__h20171);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d549)
$display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h",
rg_addr,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d549)
$write(" New Word64_Set:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d549)
$write(" CSet 0x%0x, CWord 0x%0x: ",
rg_addr[11:6],
rg_addr[5:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d549)
$write(" 0x%0x",
IF_NOT_ram_state_and_ctag_cset_b_read__04_BIT__ETC___d447);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d549)
$write(" 0x%0x",
IF_ram_state_and_ctag_cset_b_read__04_BIT_105__ETC___d446);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d549)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_3_EQ_2_5_40_OR_NOT_rg_amo_funct7_6_B_ETC___d551)
$display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h",
rg_addr,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d557)
$display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h",
rg_addr,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d557)
$display(" => rl_write_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_3_EQ_2_5_AND_rg_amo_funct7_6_BITS_6_TO_2_ETC___d561)
begin
v__h23510 = $stime;
#0;
end
v__h23504 = v__h23510 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_3_EQ_2_5_AND_rg_amo_funct7_6_BITS_6_TO_2_ETC___d561)
if (dmem_not_imem)
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h23504,
"D_MMU_Cache",
rg_addr,
64'd1,
64'd0);
else
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h23504,
"I_MMU_Cache",
rg_addr,
64'd1,
64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_3_EQ_2_5_AND_rg_amo_funct7_6_BITS_6_TO_2_ETC___d561)
$display(" AMO SC: Fail response for addr 0x%0h", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
NOT_ram_state_and_ctag_cset_b_read__04_BIT_52__ETC___d369)
$display(" AMO Miss: -> CACHE_START_REFILL.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d569)
$display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h",
rg_addr,
rg_amo_funct7,
rg_f3,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d569)
$display(" PA 0x%0h ", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d569)
$display(" Cache word64 0x%0h, load-result 0x%0h",
word64__h6008,
word64__h6008);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d569)
$display(" 0x%0h op 0x%0h -> 0x%0h",
word64__h6008,
word64__h6008,
new_st_val__h23732);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d569)
$write(" New Word64_Set:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d569)
$write(" CSet 0x%0x, CWord 0x%0x: ",
rg_addr[11:6],
rg_addr[5:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d569)
$write(" 0x%0x",
IF_NOT_ram_state_and_ctag_cset_b_read__04_BIT__ETC___d524);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d569)
$write(" 0x%0x",
IF_ram_state_and_ctag_cset_b_read__04_BIT_105__ETC___d523);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_3_EQ_0_4_39_AND_NOT_rg_op_3_EQ_2_5_4_ETC___d569)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__04_BIT_52_05_A_ETC___d571)
$display(" AMO_op: cancelling LR/SC reservation for PA",
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_ddr4_ready)
begin
v__h37786 = $stime;
#0;
end
v__h37780 = v__h37786 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_ddr4_ready)
$display("%0d: %m.ma_ddr4_ready: Enabling MMU_Cache", v__h37780);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h26828 = $stime;
#0;
end
v__h26822 = v__h26828 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s.rl_start_cache_refill: ",
v__h26822,
"D_MMU_Cache");
else
$display("%0d: %s.rl_start_cache_refill: ",
v__h26822,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", cline_fabric_addr__h26881);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 8'd7);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$display(" Victim way %0d; => CACHE_REFILL", tmp__h27044[0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
begin
v__h27567 = $stime;
#0;
end
v__h27561 = v__h27567 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
if (dmem_not_imem)
$display("%0d: %s.rl_cache_refill_rsps_loop:",
v__h27561,
"D_MMU_Cache");
else
$display("%0d: %s.rl_cache_refill_rsps_loop:",
v__h27561,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h27808 = $stime;
#0;
end
v__h27802 = v__h27808 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
v__h27802,
"D_MMU_Cache",
access_exc_code__h2535);
else
$display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
v__h27802,
"I_MMU_Cache",
access_exc_code__h2535);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] == 3'd7 &&
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
rg_error_during_refill) &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$display(" => MODULE_EXCEPTION_RSP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_cset_cword_in_cache[2:0] == 3'd7 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
!rg_error_during_refill &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$display(" => CACHE_REREQ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$display(" Updating Cache cword_set 0x%0h, cword_in_cline %0d) old => new",
rg_cset_cword_in_cache,
rg_cset_cword_in_cache[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write(" CSet 0x%0x, CWord 0x%0x: ",
rg_addr[11:6],
rg_cset_cword_in_cache[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write(" 0x%0x", ram_cword_set$DOB[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write(" 0x%0x", ram_cword_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write(" CSet 0x%0x, CWord 0x%0x: ",
rg_addr[11:6],
rg_cset_cword_in_cache[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write(" 0x%0x",
rg_victim_way ?
ram_cword_set$DOB[63:0] :
master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write(" 0x%0x",
rg_victim_way ?
master_xactor_f_rd_data$D_OUT[66:3] :
ram_cword_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__1_ULE_2_97___d598)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_rereq && NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$display(" fa_req_ram_B tagCSet [0x%0x] cword_set [0x%0d]",
rg_addr[11:6],
rg_addr[11:3]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_watch_tohost)
begin
v__h37718 = $stime;
#0;
end
v__h37712 = v__h37718 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_watch_tohost)
$display("%0d: %m.set_watch_tohost: watch %0d, addr %0h",
v__h37712,
set_watch_tohost_watch_tohost,
set_watch_tohost_tohost_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h30273 = $stime;
#0;
end
v__h30267 = v__h30273 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h",
v__h30267,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h",
v__h30267,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", value__h32526);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h30623 = $stime;
#0;
end
v__h30617 = v__h30623 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h30617,
"D_MMU_Cache",
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h30617,
"I_MMU_Cache",
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h31725 = $stime;
#0;
end
v__h31719 = v__h31725 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31719,
"D_MMU_Cache",
rg_addr,
ld_val__h30732);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31719,
"I_MMU_Cache",
rg_addr,
ld_val__h30732);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h31832 = $stime;
#0;
end
v__h31826 = v__h31832 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
v__h31826,
"D_MMU_Cache");
else
$display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
v__h31826,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h31937 = $stime;
#0;
end
v__h31931 = v__h31937 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31931,
"D_MMU_Cache",
rg_addr,
rg_ld_val);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31931,
"I_MMU_Cache",
rg_addr,
rg_ld_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h32017 = $stime;
#0;
end
v__h32011 = v__h32017 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32011,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32011,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h32227 = $stime;
#0;
end
v__h32221 = v__h32227 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32221,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32221,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$display(" FAIL due to I/O address.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h32345 = $stime;
#0;
end
v__h32339 = v__h32345 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h",
v__h32339,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h",
v__h32339,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", value__h32526);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h32639 = $stime;
#0;
end
v__h32633 = v__h32639 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h32633,
"D_MMU_Cache",
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h32633,
"I_MMU_Cache",
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h32814 = $stime;
#0;
end
v__h32808 = v__h32814 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32808,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32808,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h35073 = $stime;
#0;
end
v__h35067 = v__h35073 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h35067,
"D_MMU_Cache",
rg_addr,
new_ld_val__h32940);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h35067,
"I_MMU_Cache",
rg_addr,
new_ld_val__h32940);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h32910 = $stime;
#0;
end
v__h32904 = v__h32910 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
v__h32904,
"D_MMU_Cache");
else
$display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
v__h32904,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h35651 = $stime;
#0;
end
v__h35645 = v__h35651 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
if (dmem_not_imem)
$write("%0d: %s.rl_discard_write_rsp: pending %0d ",
v__h35645,
"D_MMU_Cache",
$unsigned(b__h26782));
else
$write("%0d: %s.rl_discard_write_rsp: pending %0d ",
v__h35645,
"I_MMU_Cache",
$unsigned(b__h26782));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
begin
v__h35693 = $stime;
#0;
end
v__h35687 = v__h35693 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
if (dmem_not_imem)
$display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
v__h35687,
"D_MMU_Cache");
else
$display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
v__h35687,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_reset)
begin
v__h3787 = $stime;
#0;
end
v__h3781 = v__h3787 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_reset)
if (dmem_not_imem)
$display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
v__h3781,
"D_MMU_Cache",
$signed(32'd8),
$signed(32'd2),
$signed(32'd64),
$signed(32'd8));
else
$display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
v__h3781,
"I_MMU_Cache",
$signed(32'd8),
$signed(32'd2),
$signed(32'd64),
$signed(32'd8));
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__1_ULE_1_2___d43)
begin
v__h36063 = $stime;
#0;
end
v__h36057 = v__h36063 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write("%0d: %m.req: op:", v__h36057);
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__1_ULE_1_2___d43 && req_op == 2'd0)
$write("CACHE_LD");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__1_ULE_1_2___d43 && req_op == 2'd1)
$write("CACHE_ST");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
req_op != 2'd0 &&
req_op != 2'd1)
$write("CACHE_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" f3:%0d addr:0x%0h st_value:0x%0h",
req_f3,
req_addr,
req_st_value,
"\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" priv:");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
req_priv == 2'b0)
$write("U");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
req_priv == 2'b01)
$write("S");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
req_priv == 2'b11)
$write("M");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__1_ULE_1_2___d43 &&
req_priv != 2'b0 &&
req_priv != 2'b01 &&
req_priv != 2'b11)
$write("RESERVED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
req_sstatus_SUM,
req_mstatus_MXR,
req_satp,
"\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$display(" amo_funct7 = 0x%0h", req_amo_funct7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_req &&
req_f3_BITS_1_TO_0_39_EQ_0b0_40_OR_req_f3_BITS_ETC___d969 &&
NOT_cfg_verbosity_read__1_ULE_1_2___d43)
$display(" fa_req_ram_B tagCSet [0x%0x] cword_set [0x%0d]",
req_addr[11:6],
req_addr[11:3]);
end
// synopsys translate_on
endmodule // mkMMU_Cache
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module fadder(
input [WIDTH-1 : 0] a,
input [WIDTH - 1 : 0] b,
input sub_enable,
input carry_in,
output [WIDTH - 1 : 0] res,
output carry_out);
parameter WIDTH = 8;
wire [WIDTH - 1 : 0] carry;
wire [WIDTH - 1 : 0] b_in;
assign carry_out = carry[WIDTH-1];
assign b_in = sub_enable ? ~(b) : b;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
if (i == 0) begin
assign res[i] = (a[i] ^ b_in[i]) ^ carry_in;
assign carry[i] = ((a[i] ^ b_in[i]) & carry_in) | (a[i] & b_in[i]);
end else begin
assign res[i] = (a[i] ^ b_in[i]) ^ carry[i-1];
assign carry[i] = ((a[i] ^ b_in[i]) & carry[i-1]) | (a[i] & b_in[i]);
end
end
endgenerate
endmodule
|
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2013, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
ROM_form.v
Production template for a 2K program for KCPSM6 in a 7-Series device using a
RAMB36E1 primitive.
Nick Sawyer (Xilinx Ltd)
Ken Chapman (Xilinx Ltd)
5th August 2011 - First Release
14th March 2013 - Unused address inputs on BRAMs connected High to reflect
descriptions UG473.
This is a verilog template file for the KCPSM6 assembler.
This verilog file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.v' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the verilog.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2013, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// Production definition of a 2K program for KCPSM6 in a 7-Series device using a
// RAMB36E1 primitive.
//
// Note: The complete 12-bit address bus is connected to KCPSM6 to facilitate future code
// expansion with minimum changes being required to the hardware description.
// Only the lower 11-bits of the address are actually used for the 2K address range
// 000 to 7FF hex.
//
// Program defined by '{psmname}.psm'.
//
// Generated by KCPSM6 Assembler: {timestamp}.
//
// Assembler used ROM_form template: ROM_form_7S_2K_14March13.v
//
//
module {name} (
input [11:0] address,
output [17:0] instruction,
input enable,
input clk);
//
//
wire [15:0] address_a;
wire [35:0] data_in_a;
wire [35:0] data_out_a;
wire [15:0] address_b;
wire [35:0] data_in_b;
wire [35:0] data_out_b;
wire enable_b;
wire clk_b;
wire [7:0] we_b;
//
//
assign address_a = {1'b1, address[10:0], 4'b1111};
assign instruction = {data_out_a[33:32], data_out_a[15:0]};
assign data_in_a = {35'b000000000000000000000000000000000000, address[11]};
//
assign address_b = 16'b1111111111111111;
assign data_in_b = {2'h0, data_out_b[33:32], 16'h0000, data_out_b[15:0]};
assign enable_b = 1'b0;
assign we_b = 8'h00;
assign clk_b = 1'b0;
//
RAMB36E1 # ( .READ_WIDTH_A (18),
.WRITE_WIDTH_A (18),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (18),
.WRITE_WIDTH_B (18),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("7SERIES"),
.INIT_00 (256'h{INIT_00}),
.INIT_01 (256'h{INIT_01}),
.INIT_02 (256'h{INIT_02}),
.INIT_03 (256'h{INIT_03}),
.INIT_04 (256'h{INIT_04}),
.INIT_05 (256'h{INIT_05}),
.INIT_06 (256'h{INIT_06}),
.INIT_07 (256'h{INIT_07}),
.INIT_08 (256'h{INIT_08}),
.INIT_09 (256'h{INIT_09}),
.INIT_0A (256'h{INIT_0A}),
.INIT_0B (256'h{INIT_0B}),
.INIT_0C (256'h{INIT_0C}),
.INIT_0D (256'h{INIT_0D}),
.INIT_0E (256'h{INIT_0E}),
.INIT_0F (256'h{INIT_0F}),
.INIT_10 (256'h{INIT_10}),
.INIT_11 (256'h{INIT_11}),
.INIT_12 (256'h{INIT_12}),
.INIT_13 (256'h{INIT_13}),
.INIT_14 (256'h{INIT_14}),
.INIT_15 (256'h{INIT_15}),
.INIT_16 (256'h{INIT_16}),
.INIT_17 (256'h{INIT_17}),
.INIT_18 (256'h{INIT_18}),
.INIT_19 (256'h{INIT_19}),
.INIT_1A (256'h{INIT_1A}),
.INIT_1B (256'h{INIT_1B}),
.INIT_1C (256'h{INIT_1C}),
.INIT_1D (256'h{INIT_1D}),
.INIT_1E (256'h{INIT_1E}),
.INIT_1F (256'h{INIT_1F}),
.INIT_20 (256'h{INIT_20}),
.INIT_21 (256'h{INIT_21}),
.INIT_22 (256'h{INIT_22}),
.INIT_23 (256'h{INIT_23}),
.INIT_24 (256'h{INIT_24}),
.INIT_25 (256'h{INIT_25}),
.INIT_26 (256'h{INIT_26}),
.INIT_27 (256'h{INIT_27}),
.INIT_28 (256'h{INIT_28}),
.INIT_29 (256'h{INIT_29}),
.INIT_2A (256'h{INIT_2A}),
.INIT_2B (256'h{INIT_2B}),
.INIT_2C (256'h{INIT_2C}),
.INIT_2D (256'h{INIT_2D}),
.INIT_2E (256'h{INIT_2E}),
.INIT_2F (256'h{INIT_2F}),
.INIT_30 (256'h{INIT_30}),
.INIT_31 (256'h{INIT_31}),
.INIT_32 (256'h{INIT_32}),
.INIT_33 (256'h{INIT_33}),
.INIT_34 (256'h{INIT_34}),
.INIT_35 (256'h{INIT_35}),
.INIT_36 (256'h{INIT_36}),
.INIT_37 (256'h{INIT_37}),
.INIT_38 (256'h{INIT_38}),
.INIT_39 (256'h{INIT_39}),
.INIT_3A (256'h{INIT_3A}),
.INIT_3B (256'h{INIT_3B}),
.INIT_3C (256'h{INIT_3C}),
.INIT_3D (256'h{INIT_3D}),
.INIT_3E (256'h{INIT_3E}),
.INIT_3F (256'h{INIT_3F}),
.INIT_40 (256'h{INIT_40}),
.INIT_41 (256'h{INIT_41}),
.INIT_42 (256'h{INIT_42}),
.INIT_43 (256'h{INIT_43}),
.INIT_44 (256'h{INIT_44}),
.INIT_45 (256'h{INIT_45}),
.INIT_46 (256'h{INIT_46}),
.INIT_47 (256'h{INIT_47}),
.INIT_48 (256'h{INIT_48}),
.INIT_49 (256'h{INIT_49}),
.INIT_4A (256'h{INIT_4A}),
.INIT_4B (256'h{INIT_4B}),
.INIT_4C (256'h{INIT_4C}),
.INIT_4D (256'h{INIT_4D}),
.INIT_4E (256'h{INIT_4E}),
.INIT_4F (256'h{INIT_4F}),
.INIT_50 (256'h{INIT_50}),
.INIT_51 (256'h{INIT_51}),
.INIT_52 (256'h{INIT_52}),
.INIT_53 (256'h{INIT_53}),
.INIT_54 (256'h{INIT_54}),
.INIT_55 (256'h{INIT_55}),
.INIT_56 (256'h{INIT_56}),
.INIT_57 (256'h{INIT_57}),
.INIT_58 (256'h{INIT_58}),
.INIT_59 (256'h{INIT_59}),
.INIT_5A (256'h{INIT_5A}),
.INIT_5B (256'h{INIT_5B}),
.INIT_5C (256'h{INIT_5C}),
.INIT_5D (256'h{INIT_5D}),
.INIT_5E (256'h{INIT_5E}),
.INIT_5F (256'h{INIT_5F}),
.INIT_60 (256'h{INIT_60}),
.INIT_61 (256'h{INIT_61}),
.INIT_62 (256'h{INIT_62}),
.INIT_63 (256'h{INIT_63}),
.INIT_64 (256'h{INIT_64}),
.INIT_65 (256'h{INIT_65}),
.INIT_66 (256'h{INIT_66}),
.INIT_67 (256'h{INIT_67}),
.INIT_68 (256'h{INIT_68}),
.INIT_69 (256'h{INIT_69}),
.INIT_6A (256'h{INIT_6A}),
.INIT_6B (256'h{INIT_6B}),
.INIT_6C (256'h{INIT_6C}),
.INIT_6D (256'h{INIT_6D}),
.INIT_6E (256'h{INIT_6E}),
.INIT_6F (256'h{INIT_6F}),
.INIT_70 (256'h{INIT_70}),
.INIT_71 (256'h{INIT_71}),
.INIT_72 (256'h{INIT_72}),
.INIT_73 (256'h{INIT_73}),
.INIT_74 (256'h{INIT_74}),
.INIT_75 (256'h{INIT_75}),
.INIT_76 (256'h{INIT_76}),
.INIT_77 (256'h{INIT_77}),
.INIT_78 (256'h{INIT_78}),
.INIT_79 (256'h{INIT_79}),
.INIT_7A (256'h{INIT_7A}),
.INIT_7B (256'h{INIT_7B}),
.INIT_7C (256'h{INIT_7C}),
.INIT_7D (256'h{INIT_7D}),
.INIT_7E (256'h{INIT_7E}),
.INIT_7F (256'h{INIT_7F}),
.INITP_00 (256'h{INITP_00}),
.INITP_01 (256'h{INITP_01}),
.INITP_02 (256'h{INITP_02}),
.INITP_03 (256'h{INITP_03}),
.INITP_04 (256'h{INITP_04}),
.INITP_05 (256'h{INITP_05}),
.INITP_06 (256'h{INITP_06}),
.INITP_07 (256'h{INITP_07}),
.INITP_08 (256'h{INITP_08}),
.INITP_09 (256'h{INITP_09}),
.INITP_0A (256'h{INITP_0A}),
.INITP_0B (256'h{INITP_0B}),
.INITP_0C (256'h{INITP_0C}),
.INITP_0D (256'h{INITP_0D}),
.INITP_0E (256'h{INITP_0E}),
.INITP_0F (256'h{INITP_0F}))
kcpsm6_rom( .ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a[31:0]),
.DOPADOP (data_out_a[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'h0),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b[31:0]),
.DOPBDOP (data_out_b[35:32]),
.DIBDI (data_in_b[31:0]),
.DIPBDIP (data_in_b[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
//
//
endmodule
//
////////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE {name}.v
//
////////////////////////////////////////////////////////////////////////////////////
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
//
//
//
//
// Create Date: 12:12:51 08/04/2014
// Module Name: SpiCtrl
// Project Name: ZedboardOLED
// Target Devices: Zynq
// Tool versions: Vivado 14.2 (64-bits)
// Description: Spi block that sends SPI data formatted SCLK active low with
// SDO changing on the falling edge
//
// Revision: 1.0 - SPI completed
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////
module SpiCtrl(
CLK,
RST,
SPI_EN,
SPI_DATA,
SDO,
SCLK,
SPI_FIN
);
// ===========================================================================
// Port Declarations
// ===========================================================================
input CLK;
input RST;
input SPI_EN;
input [7:0] SPI_DATA;
output SDO;
output SCLK;
output SPI_FIN;
// ===========================================================================
// Parameters, Regsiters, and Wires
// ===========================================================================
wire SDO, SCLK, SPI_FIN;
reg [39:0] current_state = "Idle"; // Signal for state machine
reg [7:0] shift_register = 8'h00; // Shift register to shift out SPI_DATA saved when SPI_EN was set
reg [3:0] shift_counter = 4'h0; // Keeps track how many bits were sent
wire clk_divided; // Used as SCLK
reg [4:0] counter = 5'b00000; // Count clocks to be used to divide CLK
reg temp_sdo = 1'b1; // Tied to SDO
reg falling = 1'b0; // signal indicating that the clk has just fell
// ===========================================================================
// Implementation
// ===========================================================================
assign clk_divided = ~counter[4];
assign SCLK = clk_divided;
assign SDO = temp_sdo;
assign SPI_FIN = (current_state == "Done") ? 1'b1 : 1'b0;
// State Machine
always @(posedge CLK) begin
if(RST == 1'b1) begin // Synchronous RST
current_state <= "Idle";
end
else begin
case(current_state)
// Wait for SPI_EN to go high
"Idle" : begin
if(SPI_EN == 1'b1) begin
current_state <= "Send";
end
end
// Start sending bits, transition out when all bits are sent and SCLK is high
"Send" : begin
if(shift_counter == 4'h8 && falling == 1'b0) begin
current_state <= "Done";
end
end
// Finish SPI transimission wait for SPI_EN to go low
"Done" : begin
if(SPI_EN == 1'b0) begin
current_state <= "Idle";
end
end
default : current_state <= "Idle";
endcase
end
end
// End of State Machine
// Clock Divider
always @(posedge CLK) begin
// start clock counter when in send state
if(current_state == "Send") begin
counter <= counter + 1'b1;
end
// reset clock counter when not in send state
else begin
counter <= 5'b00000;
end
end
// End Clock Divider
// SPI_SEND_BYTE, sends SPI data formatted SCLK active low with SDO changing on the falling edge
always @(posedge CLK) begin
if(current_state == "Idle") begin
shift_counter <= 4'h0;
// keeps placing SPI_DATA into shift_register so that when state goes to send it has the latest SPI_DATA
shift_register <= SPI_DATA;
temp_sdo <= 1'b1;
end
else if(current_state == "Send") begin
// if on the falling edge of Clk_divided
if(clk_divided == 1'b0 && falling == 1'b0) begin
// Indicate that it is passed the falling edge
falling <= 1'b1;
// send out the MSB
temp_sdo <= shift_register[7];
// Shift through SPI_DATA
shift_register <= {shift_register[6:0],1'b0};
// Keep track of what bit it is on
shift_counter <= shift_counter + 1'b1;
end
// on SCLK high reset the falling flag
else if(clk_divided == 1'b1) begin
falling <= 1'b0;
end
end
end
endmodule
|
`include "orpsoc-defines.v"
module sim_top
(
input wb_clk,
input wb_rst,
input [31:0] wb_adr_o,
input [3:0] wb_sel_o,
input [31:0] wb_dat_o,
input wb_we_o,
input wb_cyc_o,
input wb_stb_o,
input [2:0] wb_cti_o,
input [1:0] wb_bte_o,
output [31:0] wb_dat_i,
output wb_ack_i,
output wb_err_i,
output wb_rty_i
);
`include "orpsoc-params.v"
`include "sim_params.v"
// = Bus Wires =
wire [wb_aw-1:0] wbm_i_or12_adr_o;
wire [wb_dw-1:0] wbm_i_or12_dat_o;
wire [3:0] wbm_i_or12_sel_o;
wire wbm_i_or12_we_o;
wire wbm_i_or12_cyc_o;
wire wbm_i_or12_stb_o;
wire [2:0] wbm_i_or12_cti_o;
wire [1:0] wbm_i_or12_bte_o;
wire [wb_dw-1:0] wbm_i_or12_dat_i;
wire wbm_i_or12_ack_i;
wire wbm_i_or12_err_i;
wire wbm_i_or12_rty_i;
// OR1200 data bus wires
wire [wb_aw-1:0] wbm_d_or12_adr_o;
wire [wb_dw-1:0] wbm_d_or12_dat_o;
wire [3:0] wbm_d_or12_sel_o;
wire wbm_d_or12_we_o;
wire wbm_d_or12_cyc_o;
wire wbm_d_or12_stb_o;
wire [2:0] wbm_d_or12_cti_o;
wire [1:0] wbm_d_or12_bte_o;
wire [wb_dw-1:0] wbm_d_or12_dat_i;
wire wbm_d_or12_ack_i;
wire wbm_d_or12_err_i;
wire wbm_d_or12_rty_i;
// Debug interface bus wires
wire [wb_aw-1:0] wbm_d_dbg_adr_o;
wire [wb_dw-1:0] wbm_d_dbg_dat_o;
wire [3:0] wbm_d_dbg_sel_o;
wire wbm_d_dbg_we_o;
wire wbm_d_dbg_cyc_o;
wire wbm_d_dbg_stb_o;
wire [2:0] wbm_d_dbg_cti_o;
wire [1:0] wbm_d_dbg_bte_o;
wire [wb_dw-1:0] wbm_d_dbg_dat_i;
wire wbm_d_dbg_ack_i;
wire wbm_d_dbg_err_i;
wire wbm_d_dbg_rty_i;
// Byte bus bridge master signals
wire [wb_aw-1:0] wbm_b_d_adr_o;
wire [wb_dw-1:0] wbm_b_d_dat_o;
wire [3:0] wbm_b_d_sel_o;
wire wbm_b_d_we_o;
wire wbm_b_d_cyc_o;
wire wbm_b_d_stb_o;
wire [2:0] wbm_b_d_cti_o;
wire [1:0] wbm_b_d_bte_o;
wire [wb_dw-1:0] wbm_b_d_dat_i;
wire wbm_b_d_ack_i;
wire wbm_b_d_err_i;
wire wbm_b_d_rty_i;
// Instruction bus slave wires //
// rom0 instruction bus wires
wire [31:0] wbs_i_rom0_adr_i;
wire [wbs_i_rom0_data_width-1:0] wbs_i_rom0_dat_i;
wire [3:0] wbs_i_rom0_sel_i;
wire wbs_i_rom0_we_i;
wire wbs_i_rom0_cyc_i;
wire wbs_i_rom0_stb_i;
wire [2:0] wbs_i_rom0_cti_i;
wire [1:0] wbs_i_rom0_bte_i;
wire [wbs_i_rom0_data_width-1:0] wbs_i_rom0_dat_o;
wire wbs_i_rom0_ack_o;
wire wbs_i_rom0_err_o;
wire wbs_i_rom0_rty_o;
// mc0 instruction bus wires
wire [31:0] wbs_i_mc0_adr_i;
wire [wbs_i_mc0_data_width-1:0] wbs_i_mc0_dat_i;
wire [3:0] wbs_i_mc0_sel_i;
wire wbs_i_mc0_we_i;
wire wbs_i_mc0_cyc_i;
wire wbs_i_mc0_stb_i;
wire [2:0] wbs_i_mc0_cti_i;
wire [1:0] wbs_i_mc0_bte_i;
wire [wbs_i_mc0_data_width-1:0] wbs_i_mc0_dat_o;
wire wbs_i_mc0_ack_o;
wire wbs_i_mc0_err_o;
wire wbs_i_mc0_rty_o;
// Data bus slave wires //
// mc0 data bus wires
wire [31:0] wbs_d_mc0_adr_i;
wire [wbs_d_mc0_data_width-1:0] wbs_d_mc0_dat_i;
wire [3:0] wbs_d_mc0_sel_i;
wire wbs_d_mc0_we_i;
wire wbs_d_mc0_cyc_i;
wire wbs_d_mc0_stb_i;
wire [2:0] wbs_d_mc0_cti_i;
wire [1:0] wbs_d_mc0_bte_i;
wire [wbs_d_mc0_data_width-1:0] wbs_d_mc0_dat_o;
wire wbs_d_mc0_ack_o;
wire wbs_d_mc0_err_o;
wire wbs_d_mc0_rty_o;
// i2c0 wires
wire [31:0] wbs_d_i2c0_adr_i;
wire [wbs_d_i2c0_data_width-1:0] wbs_d_i2c0_dat_i;
wire [3:0] wbs_d_i2c0_sel_i;
wire wbs_d_i2c0_we_i;
wire wbs_d_i2c0_cyc_i;
wire wbs_d_i2c0_stb_i;
wire [2:0] wbs_d_i2c0_cti_i;
wire [1:0] wbs_d_i2c0_bte_i;
wire [wbs_d_i2c0_data_width-1:0] wbs_d_i2c0_dat_o;
wire wbs_d_i2c0_ack_o;
wire wbs_d_i2c0_err_o;
wire wbs_d_i2c0_rty_o;
// i2c1 wires
wire [31:0] wbs_d_i2c1_adr_i;
wire [wbs_d_i2c1_data_width-1:0] wbs_d_i2c1_dat_i;
wire [3:0] wbs_d_i2c1_sel_i;
wire wbs_d_i2c1_we_i;
wire wbs_d_i2c1_cyc_i;
wire wbs_d_i2c1_stb_i;
wire [2:0] wbs_d_i2c1_cti_i;
wire [1:0] wbs_d_i2c1_bte_i;
wire [wbs_d_i2c1_data_width-1:0] wbs_d_i2c1_dat_o;
wire wbs_d_i2c1_ack_o;
wire wbs_d_i2c1_err_o;
wire wbs_d_i2c1_rty_o;
// spi0 wires
wire [31:0] wbs_d_spi0_adr_i;
wire [wbs_d_spi0_data_width-1:0] wbs_d_spi0_dat_i;
wire [3:0] wbs_d_spi0_sel_i;
wire wbs_d_spi0_we_i;
wire wbs_d_spi0_cyc_i;
wire wbs_d_spi0_stb_i;
wire [2:0] wbs_d_spi0_cti_i;
wire [1:0] wbs_d_spi0_bte_i;
wire [wbs_d_spi0_data_width-1:0] wbs_d_spi0_dat_o;
wire wbs_d_spi0_ack_o;
wire wbs_d_spi0_err_o;
wire wbs_d_spi0_rty_o;
// uart0 wires
wire [31:0] wbs_d_uart0_adr_i;
wire [wbs_d_uart0_data_width-1:0] wbs_d_uart0_dat_i;
wire [3:0] wbs_d_uart0_sel_i;
wire wbs_d_uart0_we_i;
wire wbs_d_uart0_cyc_i;
wire wbs_d_uart0_stb_i;
wire [2:0] wbs_d_uart0_cti_i;
wire [1:0] wbs_d_uart0_bte_i;
wire [wbs_d_uart0_data_width-1:0] wbs_d_uart0_dat_o;
wire wbs_d_uart0_ack_o;
wire wbs_d_uart0_err_o;
wire wbs_d_uart0_rty_o;
// gpio0 wires
wire [31:0] wbs_d_gpio0_adr_i;
wire [wbs_d_gpio0_data_width-1:0] wbs_d_gpio0_dat_i;
wire [3:0] wbs_d_gpio0_sel_i;
wire wbs_d_gpio0_we_i;
wire wbs_d_gpio0_cyc_i;
wire wbs_d_gpio0_stb_i;
wire [2:0] wbs_d_gpio0_cti_i;
wire [1:0] wbs_d_gpio0_bte_i;
wire [wbs_d_gpio0_data_width-1:0] wbs_d_gpio0_dat_o;
wire wbs_d_gpio0_ack_o;
wire wbs_d_gpio0_err_o;
wire wbs_d_gpio0_rty_o;
// ps2_0 wires
wire [31:0] wbs_d_ps2_0_adr_i;
wire [wbs_d_ps2_0_data_width-1:0] wbs_d_ps2_0_dat_i;
wire [3:0] wbs_d_ps2_0_sel_i;
wire wbs_d_ps2_0_we_i;
wire wbs_d_ps2_0_cyc_i;
wire wbs_d_ps2_0_stb_i;
wire [2:0] wbs_d_ps2_0_cti_i;
wire [1:0] wbs_d_ps2_0_bte_i;
wire [wbs_d_ps2_0_data_width-1:0] wbs_d_ps2_0_dat_o;
wire wbs_d_ps2_0_ack_o;
wire wbs_d_ps2_0_err_o;
wire wbs_d_ps2_0_rty_o;
// ps2_1 wires
wire [31:0] wbs_d_ps2_1_adr_i;
wire [wbs_d_ps2_1_data_width-1:0] wbs_d_ps2_1_dat_i;
wire [3:0] wbs_d_ps2_1_sel_i;
wire wbs_d_ps2_1_we_i;
wire wbs_d_ps2_1_cyc_i;
wire wbs_d_ps2_1_stb_i;
wire [2:0] wbs_d_ps2_1_cti_i;
wire [1:0] wbs_d_ps2_1_bte_i;
wire [wbs_d_ps2_1_data_width-1:0] wbs_d_ps2_1_dat_o;
wire wbs_d_ps2_1_ack_o;
wire wbs_d_ps2_1_err_o;
wire wbs_d_ps2_1_rty_o;
// eth0 slave wires
wire [31:0] wbs_d_eth0_adr_i;
wire [wbs_d_eth0_data_width-1:0] wbs_d_eth0_dat_i;
wire [3:0] wbs_d_eth0_sel_i;
wire wbs_d_eth0_we_i;
wire wbs_d_eth0_cyc_i;
wire wbs_d_eth0_stb_i;
wire [2:0] wbs_d_eth0_cti_i;
wire [1:0] wbs_d_eth0_bte_i;
wire [wbs_d_eth0_data_width-1:0] wbs_d_eth0_dat_o;
wire wbs_d_eth0_ack_o;
wire wbs_d_eth0_err_o;
wire wbs_d_eth0_rty_o;
// eth0 master wires
wire [wbm_eth0_addr_width-1:0] wbm_eth0_adr_o;
wire [wbm_eth0_data_width-1:0] wbm_eth0_dat_o;
wire [3:0] wbm_eth0_sel_o;
wire wbm_eth0_we_o;
wire wbm_eth0_cyc_o;
wire wbm_eth0_stb_o;
wire [2:0] wbm_eth0_cti_o;
wire [1:0] wbm_eth0_bte_o;
wire [wbm_eth0_data_width-1:0] wbm_eth0_dat_i;
wire wbm_eth0_ack_i;
wire wbm_eth0_err_i;
wire wbm_eth0_rty_i;
// vga0 slave wires
wire [31:0] wbs_d_vga0_adr_i;
wire [wbs_d_vga0_data_width-1:0] wbs_d_vga0_dat_i;
wire [3:0] wbs_d_vga0_sel_i;
wire wbs_d_vga0_we_i;
wire wbs_d_vga0_cyc_i;
wire wbs_d_vga0_stb_i;
wire [2:0] wbs_d_vga0_cti_i;
wire [1:0] wbs_d_vga0_bte_i;
wire [wbs_d_vga0_data_width-1:0] wbs_d_vga0_dat_o;
wire wbs_d_vga0_ack_o;
wire wbs_d_vga0_err_o;
wire wbs_d_vga0_rty_o;
// vga0 master wires
wire [wbm_vga0_addr_width-1:0] wbm_vga0_adr_o;
wire [wbm_vga0_data_width-1:0] wbm_vga0_dat_o;
wire [3:0] wbm_vga0_sel_o;
wire wbm_vga0_we_o;
wire wbm_vga0_cyc_o;
wire wbm_vga0_stb_o;
wire [2:0] wbm_vga0_cti_o;
wire [1:0] wbm_vga0_bte_o;
wire [wbm_vga0_data_width-1:0] wbm_vga0_dat_i;
wire wbm_vga0_ack_i;
wire wbm_vga0_err_i;
wire wbm_vga0_rty_i;
// ac97 slave wires
wire [31:0] wbs_d_ac97_adr_i;
wire [wbs_d_ac97_data_width-1:0] wbs_d_ac97_dat_i;
wire [3:0] wbs_d_ac97_sel_i;
wire wbs_d_ac97_we_i;
wire wbs_d_ac97_cyc_i;
wire wbs_d_ac97_stb_i;
wire [2:0] wbs_d_ac97_cti_i;
wire [1:0] wbs_d_ac97_bte_i;
wire [wbs_d_ac97_data_width-1:0] wbs_d_ac97_dat_o;
wire wbs_d_ac97_ack_o;
wire wbs_d_ac97_err_o;
wire wbs_d_ac97_rty_o;
// dma0 slave wires
wire [31:0] wbs_d_dma0_adr_i;
wire [wbs_d_dma0_data_width-1:0] wbs_d_dma0_dat_i;
wire [3:0] wbs_d_dma0_sel_i;
wire wbs_d_dma0_we_i;
wire wbs_d_dma0_cyc_i;
wire wbs_d_dma0_stb_i;
wire [2:0] wbs_d_dma0_cti_i;
wire [1:0] wbs_d_dma0_bte_i;
wire [wbs_d_dma0_data_width-1:0] wbs_d_dma0_dat_o;
wire wbs_d_dma0_ack_o;
wire wbs_d_dma0_err_o;
wire wbs_d_dma0_rty_o;
// dma0 master wires
wire [wbm_dma0_addr_width-1:0] wbm_dma0_adr_o;
wire [wbm_dma0_data_width-1:0] wbm_dma0_dat_o;
wire [3:0] wbm_dma0_sel_o;
wire wbm_dma0_we_o;
wire wbm_dma0_cyc_o;
wire wbm_dma0_stb_o;
wire [2:0] wbm_dma0_cti_o;
wire [1:0] wbm_dma0_bte_o;
wire [wbm_dma0_data_width-1:0] wbm_dma0_dat_i;
wire wbm_dma0_ack_i;
wire wbm_dma0_err_i;
wire wbm_dma0_rty_i;
// fdt0 slave wires
wire [31:0] wbs_d_fdt0_adr_i;
wire [wbs_d_fdt0_data_width-1:0] wbs_d_fdt0_dat_i;
wire [3:0] wbs_d_fdt0_sel_i;
wire wbs_d_fdt0_we_i;
wire wbs_d_fdt0_cyc_i;
wire wbs_d_fdt0_stb_i;
wire [2:0] wbs_d_fdt0_cti_i;
wire [1:0] wbs_d_fdt0_bte_i;
wire [wbs_d_fdt0_data_width-1:0] wbs_d_fdt0_dat_o;
wire wbs_d_fdt0_ack_o;
wire wbs_d_fdt0_err_o;
wire wbs_d_fdt0_rty_o;
// orlink master wires
wire [wbm_orlink_addr_width-1:0] wbm_orlink_adr_o;
wire [wbm_orlink_data_width-1:0] wbm_orlink_dat_o;
wire [3:0] wbm_orlink_sel_o;
wire wbm_orlink_we_o;
wire wbm_orlink_cyc_o;
wire wbm_orlink_stb_o;
wire [2:0] wbm_orlink_cti_o;
wire [1:0] wbm_orlink_bte_o;
wire [wbm_orlink_data_width-1:0] wbm_orlink_dat_i;
wire wbm_orlink_ack_i;
wire wbm_orlink_err_i;
wire wbm_orlink_rty_i;
// rayc wires
wire [31:0] wbs_d_rayc_adr_i;
wire [wbs_d_rayc_data_width-1:0] wbs_d_rayc_dat_i;
wire [3:0] wbs_d_rayc_sel_i;
wire wbs_d_rayc_we_i;
wire wbs_d_rayc_cyc_i;
wire wbs_d_rayc_stb_i;
wire [2:0] wbs_d_rayc_cti_i;
wire [1:0] wbs_d_rayc_bte_i;
wire [wbs_d_rayc_data_width-1:0] wbs_d_rayc_dat_o;
wire wbs_d_rayc_ack_o;
wire wbs_d_rayc_err_o;
wire wbs_d_rayc_rty_o;
// rayc master wires
wire [wbm_rayc_addr_width-1:0] wbm_rayc_adr_o;
wire [wbm_rayc_data_width-1:0] wbm_rayc_dat_o;
wire [3:0] wbm_rayc_sel_o;
wire wbm_rayc_we_o;
wire wbm_rayc_cyc_o;
wire wbm_rayc_stb_o;
wire [2:0] wbm_rayc_cti_o;
wire [1:0] wbm_rayc_bte_o;
wire [wbm_rayc_data_width-1:0] wbm_rayc_dat_i;
wire wbm_rayc_ack_i;
wire wbm_rayc_err_i;
wire wbm_rayc_rty_i;
// --
// = Bus Wire Assignment =
// Hook up to testbench
assign wbm_d_or12_adr_o = wb_adr_o;
assign wbm_d_or12_dat_o = wb_dat_o;
assign wbm_d_or12_sel_o = wb_sel_o;
assign wbm_d_or12_we_o = wb_we_o;
assign wbm_d_or12_cyc_o = wb_cyc_o;
assign wbm_d_or12_stb_o = wb_stb_o;
assign wbm_d_or12_cti_o = wb_cti_o;
assign wbm_d_or12_bte_o = wb_bte_o;
assign wb_dat_i = wbm_d_or12_dat_i;
assign wb_ack_i = wbm_d_or12_ack_i;
assign wb_err_i = wbm_d_or12_err_i;
assign wb_rty_i = wbm_d_or12_rty_i;
assign wbm_d_dbg_adr_o = 0;
assign wbm_d_dbg_dat_o = 0;
assign wbm_d_dbg_sel_o = 0;
assign wbm_d_dbg_we_o = 0;
assign wbm_d_dbg_cyc_o = 0;
assign wbm_d_dbg_stb_o = 0;
assign wbm_d_dbg_cti_o = 0;
assign wbm_d_dbg_bte_o = 0;
// --
// = Wishbone data bus =
arbiter_dbus arbiter_dbus0
(
// Master 0
// Inputs to arbiter from master
.wbm0_adr_o (wbm_d_or12_adr_o),
.wbm0_dat_o (wbm_d_or12_dat_o),
.wbm0_sel_o (wbm_d_or12_sel_o),
.wbm0_we_o (wbm_d_or12_we_o),
.wbm0_cyc_o (wbm_d_or12_cyc_o),
.wbm0_stb_o (wbm_d_or12_stb_o),
.wbm0_cti_o (wbm_d_or12_cti_o),
.wbm0_bte_o (wbm_d_or12_bte_o),
// Outputs to master from arbiter
.wbm0_dat_i (wbm_d_or12_dat_i),
.wbm0_ack_i (wbm_d_or12_ack_i),
.wbm0_err_i (wbm_d_or12_err_i),
.wbm0_rty_i (wbm_d_or12_rty_i),
// Master 0
// Inputs to arbiter from master
.wbm1_adr_o (wbm_d_dbg_adr_o),
.wbm1_dat_o (wbm_d_dbg_dat_o),
.wbm1_we_o (wbm_d_dbg_we_o),
.wbm1_cyc_o (wbm_d_dbg_cyc_o),
.wbm1_sel_o (wbm_d_dbg_sel_o),
.wbm1_stb_o (wbm_d_dbg_stb_o),
.wbm1_cti_o (wbm_d_dbg_cti_o),
.wbm1_bte_o (wbm_d_dbg_bte_o),
// Outputs to master from arbiter
.wbm1_dat_i (wbm_d_dbg_dat_i),
.wbm1_ack_i (wbm_d_dbg_ack_i),
.wbm1_err_i (wbm_d_dbg_err_i),
.wbm1_rty_i (wbm_d_dbg_rty_i),
// Slaves
.wbs0_adr_i (wbs_d_mc0_adr_i),
.wbs0_dat_i (wbs_d_mc0_dat_i),
.wbs0_sel_i (wbs_d_mc0_sel_i),
.wbs0_we_i (wbs_d_mc0_we_i),
.wbs0_cyc_i (wbs_d_mc0_cyc_i),
.wbs0_stb_i (wbs_d_mc0_stb_i),
.wbs0_cti_i (wbs_d_mc0_cti_i),
.wbs0_bte_i (wbs_d_mc0_bte_i),
.wbs0_dat_o (wbs_d_mc0_dat_o),
.wbs0_ack_o (wbs_d_mc0_ack_o),
.wbs0_err_o (wbs_d_mc0_err_o),
.wbs0_rty_o (wbs_d_mc0_rty_o),
.wbs1_adr_i (wbs_d_eth0_adr_i),
.wbs1_dat_i (wbs_d_eth0_dat_i),
.wbs1_sel_i (wbs_d_eth0_sel_i),
.wbs1_we_i (wbs_d_eth0_we_i),
.wbs1_cyc_i (wbs_d_eth0_cyc_i),
.wbs1_stb_i (wbs_d_eth0_stb_i),
.wbs1_cti_i (wbs_d_eth0_cti_i),
.wbs1_bte_i (wbs_d_eth0_bte_i),
.wbs1_dat_o (wbs_d_eth0_dat_o),
.wbs1_ack_o (wbs_d_eth0_ack_o),
.wbs1_err_o (wbs_d_eth0_err_o),
.wbs1_rty_o (wbs_d_eth0_rty_o),
.wbs2_adr_i (wbm_b_d_adr_o),
.wbs2_dat_i (wbm_b_d_dat_o),
.wbs2_sel_i (wbm_b_d_sel_o),
.wbs2_we_i (wbm_b_d_we_o),
.wbs2_cyc_i (wbm_b_d_cyc_o),
.wbs2_stb_i (wbm_b_d_stb_o),
.wbs2_cti_i (wbm_b_d_cti_o),
.wbs2_bte_i (wbm_b_d_bte_o),
.wbs2_dat_o (wbm_b_d_dat_i),
.wbs2_ack_o (wbm_b_d_ack_i),
.wbs2_err_o (wbm_b_d_err_i),
.wbs2_rty_o (wbm_b_d_rty_i),
.wbs3_adr_i (wbs_d_vga0_adr_i),
.wbs3_dat_i (wbs_d_vga0_dat_i),
.wbs3_sel_i (wbs_d_vga0_sel_i),
.wbs3_we_i (wbs_d_vga0_we_i),
.wbs3_cyc_i (wbs_d_vga0_cyc_i),
.wbs3_stb_i (wbs_d_vga0_stb_i),
.wbs3_cti_i (wbs_d_vga0_cti_i),
.wbs3_bte_i (wbs_d_vga0_bte_i),
.wbs3_dat_o (wbs_d_vga0_dat_o),
.wbs3_ack_o (wbs_d_vga0_ack_o),
.wbs3_err_o (wbs_d_vga0_err_o),
.wbs3_rty_o (wbs_d_vga0_rty_o),
.wbs4_adr_i (wbs_d_ac97_adr_i),
.wbs4_dat_i (wbs_d_ac97_dat_i),
.wbs4_sel_i (wbs_d_ac97_sel_i),
.wbs4_we_i (wbs_d_ac97_we_i),
.wbs4_cyc_i (wbs_d_ac97_cyc_i),
.wbs4_stb_i (wbs_d_ac97_stb_i),
.wbs4_cti_i (wbs_d_ac97_cti_i),
.wbs4_bte_i (wbs_d_ac97_bte_i),
.wbs4_dat_o (wbs_d_ac97_dat_o),
.wbs4_ack_o (wbs_d_ac97_ack_o),
.wbs4_err_o (wbs_d_ac97_err_o),
.wbs4_rty_o (wbs_d_ac97_rty_o),
.wbs5_adr_i (wbs_d_dma0_adr_i),
.wbs5_dat_i (wbs_d_dma0_dat_i),
.wbs5_sel_i (wbs_d_dma0_sel_i),
.wbs5_we_i (wbs_d_dma0_we_i),
.wbs5_cyc_i (wbs_d_dma0_cyc_i),
.wbs5_stb_i (wbs_d_dma0_stb_i),
.wbs5_cti_i (wbs_d_dma0_cti_i),
.wbs5_bte_i (wbs_d_dma0_bte_i),
.wbs5_dat_o (wbs_d_dma0_dat_o),
.wbs5_ack_o (wbs_d_dma0_ack_o),
.wbs5_err_o (wbs_d_dma0_err_o),
.wbs5_rty_o (wbs_d_dma0_rty_o),
.wbs6_adr_i (wbs_d_fdt0_adr_i),
.wbs6_dat_i (wbs_d_fdt0_dat_i),
.wbs6_sel_i (wbs_d_fdt0_sel_i),
.wbs6_we_i (wbs_d_fdt0_we_i),
.wbs6_cyc_i (wbs_d_fdt0_cyc_i),
.wbs6_stb_i (wbs_d_fdt0_stb_i),
.wbs6_cti_i (wbs_d_fdt0_cti_i),
.wbs6_bte_i (wbs_d_fdt0_bte_i),
.wbs6_dat_o (wbs_d_fdt0_dat_o),
.wbs6_ack_o (wbs_d_fdt0_ack_o),
.wbs6_err_o (wbs_d_fdt0_err_o),
.wbs6_rty_o (wbs_d_fdt0_rty_o),
// Clock, reset inputs
.wb_clk (wb_clk),
.wb_rst (wb_rst));
// These settings are from top level params file
defparam arbiter_dbus0.wb_addr_match_width = dbus_arb_wb_addr_match_width;
defparam arbiter_dbus0.wb_num_slaves = dbus_arb_wb_num_slaves;
defparam arbiter_dbus0.slave0_adr = dbus_arb_slave0_adr;
defparam arbiter_dbus0.slave1_adr = dbus_arb_slave1_adr;
defparam arbiter_dbus0.slave3_adr = dbus_arb_slave3_adr;
defparam arbiter_dbus0.slave4_adr = dbus_arb_slave4_adr;
defparam arbiter_dbus0.slave5_adr = dbus_arb_slave5_adr;
defparam arbiter_dbus0.slave6_adr = dbus_arb_slave6_adr;
// --
// = Wishbone byte bus =
arbiter_bytebus arbiter_bytebus0
(
// Master 0
// Inputs to arbiter from master
.wbm0_adr_o (wbm_b_d_adr_o),
.wbm0_dat_o (wbm_b_d_dat_o),
.wbm0_sel_o (wbm_b_d_sel_o),
.wbm0_we_o (wbm_b_d_we_o),
.wbm0_cyc_o (wbm_b_d_cyc_o),
.wbm0_stb_o (wbm_b_d_stb_o),
.wbm0_cti_o (wbm_b_d_cti_o),
.wbm0_bte_o (wbm_b_d_bte_o),
// Outputs to master from arbiter
.wbm0_dat_i (wbm_b_d_dat_i),
.wbm0_ack_i (wbm_b_d_ack_i),
.wbm0_err_i (wbm_b_d_err_i),
.wbm0_rty_i (wbm_b_d_rty_i),
// Byte bus slaves
.wbs0_adr_i (wbs_d_uart0_adr_i),
.wbs0_dat_i (wbs_d_uart0_dat_i),
.wbs0_we_i (wbs_d_uart0_we_i),
.wbs0_cyc_i (wbs_d_uart0_cyc_i),
.wbs0_stb_i (wbs_d_uart0_stb_i),
.wbs0_cti_i (wbs_d_uart0_cti_i),
.wbs0_bte_i (wbs_d_uart0_bte_i),
.wbs0_dat_o (wbs_d_uart0_dat_o),
.wbs0_ack_o (wbs_d_uart0_ack_o),
.wbs0_err_o (wbs_d_uart0_err_o),
.wbs0_rty_o (wbs_d_uart0_rty_o),
.wbs1_adr_i (wbs_d_gpio0_adr_i),
.wbs1_dat_i (wbs_d_gpio0_dat_i),
.wbs1_we_i (wbs_d_gpio0_we_i),
.wbs1_cyc_i (wbs_d_gpio0_cyc_i),
.wbs1_stb_i (wbs_d_gpio0_stb_i),
.wbs1_cti_i (wbs_d_gpio0_cti_i),
.wbs1_bte_i (wbs_d_gpio0_bte_i),
.wbs1_dat_o (wbs_d_gpio0_dat_o),
.wbs1_ack_o (wbs_d_gpio0_ack_o),
.wbs1_err_o (wbs_d_gpio0_err_o),
.wbs1_rty_o (wbs_d_gpio0_rty_o),
.wbs2_adr_i (wbs_d_rayc_adr_i),
.wbs2_dat_i (wbs_d_rayc_dat_i),
.wbs2_we_i (wbs_d_rayc_we_i ),
.wbs2_cyc_i (wbs_d_rayc_cyc_i),
.wbs2_stb_i (wbs_d_rayc_stb_i),
.wbs2_cti_i (wbs_d_rayc_cti_i),
.wbs2_bte_i (wbs_d_rayc_bte_i),
.wbs2_dat_o (wbs_d_rayc_dat_o),
.wbs2_ack_o (wbs_d_rayc_ack_o),
.wbs2_err_o (wbs_d_rayc_err_o),
.wbs2_rty_o (wbs_d_rayc_rty_o),
.wbs3_adr_i (wbs_d_i2c1_adr_i),
.wbs3_dat_i (wbs_d_i2c1_dat_i),
.wbs3_we_i (wbs_d_i2c1_we_i ),
.wbs3_cyc_i (wbs_d_i2c1_cyc_i),
.wbs3_stb_i (wbs_d_i2c1_stb_i),
.wbs3_cti_i (wbs_d_i2c1_cti_i),
.wbs3_bte_i (wbs_d_i2c1_bte_i),
.wbs3_dat_o (wbs_d_i2c1_dat_o),
.wbs3_ack_o (wbs_d_i2c1_ack_o),
.wbs3_err_o (wbs_d_i2c1_err_o),
.wbs3_rty_o (wbs_d_i2c1_rty_o),
.wbs4_adr_i (wbs_d_spi0_adr_i),
.wbs4_dat_i (wbs_d_spi0_dat_i),
.wbs4_we_i (wbs_d_spi0_we_i ),
.wbs4_cyc_i (wbs_d_spi0_cyc_i),
.wbs4_stb_i (wbs_d_spi0_stb_i),
.wbs4_cti_i (wbs_d_spi0_cti_i),
.wbs4_bte_i (wbs_d_spi0_bte_i),
.wbs4_dat_o (wbs_d_spi0_dat_o),
.wbs4_ack_o (wbs_d_spi0_ack_o),
.wbs4_err_o (wbs_d_spi0_err_o),
.wbs4_rty_o (wbs_d_spi0_rty_o),
.wbs5_adr_i (wbs_d_ps2_0_adr_i),
.wbs5_dat_i (wbs_d_ps2_0_dat_i),
.wbs5_we_i (wbs_d_ps2_0_we_i ),
.wbs5_cyc_i (wbs_d_ps2_0_cyc_i),
.wbs5_stb_i (wbs_d_ps2_0_stb_i),
.wbs5_cti_i (wbs_d_ps2_0_cti_i),
.wbs5_bte_i (wbs_d_ps2_0_bte_i),
.wbs5_dat_o (wbs_d_ps2_0_dat_o),
.wbs5_ack_o (wbs_d_ps2_0_ack_o),
.wbs5_err_o (wbs_d_ps2_0_err_o),
.wbs5_rty_o (wbs_d_ps2_0_rty_o),
.wbs6_adr_i (wbs_d_ps2_1_adr_i),
.wbs6_dat_i (wbs_d_ps2_1_dat_i),
.wbs6_we_i (wbs_d_ps2_1_we_i ),
.wbs6_cyc_i (wbs_d_ps2_1_cyc_i),
.wbs6_stb_i (wbs_d_ps2_1_stb_i),
.wbs6_cti_i (wbs_d_ps2_1_cti_i),
.wbs6_bte_i (wbs_d_ps2_1_bte_i),
.wbs6_dat_o (wbs_d_ps2_1_dat_o),
.wbs6_ack_o (wbs_d_ps2_1_ack_o),
.wbs6_err_o (wbs_d_ps2_1_err_o),
.wbs6_rty_o (wbs_d_ps2_1_rty_o),
// Clock, reset inputs
.wb_clk (wb_clk),
.wb_rst (wb_rst));
defparam arbiter_bytebus0.wb_addr_match_width = bbus_arb_wb_addr_match_width;
defparam arbiter_bytebus0.wb_num_slaves = bbus_arb_wb_num_slaves;
defparam arbiter_bytebus0.slave0_adr = bbus_arb_slave0_adr;
defparam arbiter_bytebus0.slave1_adr = bbus_arb_slave1_adr;
defparam arbiter_bytebus0.slave2_adr = bbus_arb_slave2_adr;
defparam arbiter_bytebus0.slave3_adr = bbus_arb_slave3_adr;
defparam arbiter_bytebus0.slave4_adr = bbus_arb_slave4_adr;
defparam arbiter_bytebus0.slave5_adr = bbus_arb_slave5_adr;
defparam arbiter_bytebus0.slave6_adr = bbus_arb_slave6_adr;
// --
// = RAM =
ram_wb xilinx_ddr2_0
(
.wbm0_adr_i (wbm_rayc_adr_o),
.wbm0_bte_i (wbm_rayc_bte_o),
.wbm0_cti_i (wbm_rayc_cti_o),
.wbm0_cyc_i (wbm_rayc_cyc_o),
.wbm0_dat_i (wbm_rayc_dat_o),
.wbm0_sel_i (wbm_rayc_sel_o),
.wbm0_stb_i (wbm_rayc_stb_o),
.wbm0_we_i (wbm_rayc_we_o),
.wbm0_ack_o (wbm_rayc_ack_i),
.wbm0_err_o (wbm_rayc_err_i),
.wbm0_rty_o (wbm_rayc_rty_i),
.wbm0_dat_o (wbm_rayc_dat_i),
.wbm1_adr_i (wbs_d_mc0_adr_i),
.wbm1_bte_i (wbs_d_mc0_bte_i),
.wbm1_cti_i (wbs_d_mc0_cti_i),
.wbm1_cyc_i (wbs_d_mc0_cyc_i),
.wbm1_dat_i (wbs_d_mc0_dat_i),
.wbm1_sel_i (wbs_d_mc0_sel_i),
.wbm1_stb_i (wbs_d_mc0_stb_i),
.wbm1_we_i (wbs_d_mc0_we_i),
.wbm1_ack_o (wbs_d_mc0_ack_o),
.wbm1_err_o (wbs_d_mc0_err_o),
.wbm1_rty_o (wbs_d_mc0_rty_o),
.wbm1_dat_o (wbs_d_mc0_dat_o),
.wbm2_adr_i (wbs_i_mc0_adr_i),
.wbm2_bte_i (wbs_i_mc0_bte_i),
.wbm2_cti_i (wbs_i_mc0_cti_i),
.wbm2_cyc_i (wbs_i_mc0_cyc_i),
.wbm2_dat_i (wbs_i_mc0_dat_i),
.wbm2_sel_i (wbs_i_mc0_sel_i),
.wbm2_stb_i (wbs_i_mc0_stb_i),
.wbm2_we_i (wbs_i_mc0_we_i),
.wbm2_ack_o (wbs_i_mc0_ack_o),
.wbm2_err_o (wbs_i_mc0_err_o),
.wbm2_rty_o (wbs_i_mc0_rty_o),
.wbm2_dat_o (wbs_i_mc0_dat_o),
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst)
);
defparam xilinx_ddr2_0.mem_size_bytes = vmem_size;
defparam xilinx_ddr2_0.mem_adr_width = vmem_size_log2;
// --
raycaster rayc
(
// Wishbone slave interface
.wb_adr_i (wbs_d_rayc_adr_i[wbs_d_rayc_addr_width-1:0]),
.wb_dat_i (wbs_d_rayc_dat_i),
.wb_we_i (wbs_d_rayc_we_i),
.wb_cyc_i (wbs_d_rayc_cyc_i),
.wb_stb_i (wbs_d_rayc_stb_i),
.wb_cti_i (wbs_d_rayc_cti_i),
.wb_bte_i (wbs_d_rayc_bte_i),
.wb_dat_o (wbs_d_rayc_dat_o),
.wb_ack_o (wbs_d_rayc_ack_o),
.wb_err_o (wbs_d_rayc_err_o),
.wb_rty_o (wbs_d_rayc_rty_o),
// Wishbone Master Interface
.m_wb_adr_o (wbm_rayc_adr_o[31:0]),
.m_wb_sel_o (wbm_rayc_sel_o[3:0]),
.m_wb_we_o (wbm_rayc_we_o),
.m_wb_dat_o (wbm_rayc_dat_o[31:0]),
.m_wb_cyc_o (wbm_rayc_cyc_o),
.m_wb_stb_o (wbm_rayc_stb_o),
.m_wb_cti_o (wbm_rayc_cti_o[2:0]),
.m_wb_bte_o (wbm_rayc_bte_o[1:0]),
.m_wb_dat_i (wbm_rayc_dat_i[31:0]),
.m_wb_ack_i (wbm_rayc_ack_i),
.m_wb_err_i (wbm_rayc_err_i),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
endmodule |
module opicorv32_rv32_wrap (
irq,
pcpi_ready,
pcpi_wait,
pcpi_rd,
pcpi_wr,
mem_rdata,
mem_ready,
resetn,
clk,
trap,
mem_valid,
mem_instr,
mem_addr,
mem_wdata,
mem_wstrb,
mem_la_read,
mem_la_write,
mem_la_addr,
mem_la_wdata,
mem_la_wstrb,
pcpi_valid,
pcpi_insn,
pcpi_rs1,
pcpi_rs2,
eoi
);
input [31:0] irq;
input pcpi_ready;
input pcpi_wait;
input [31:0] pcpi_rd;
input pcpi_wr;
input [31:0] mem_rdata;
input mem_ready;
input resetn;
input clk;
output trap;
output mem_valid;
output mem_instr;
output [31:0] mem_addr;
output [31:0] mem_wdata;
output [3:0] mem_wstrb;
output mem_la_read;
output mem_la_write;
output [31:0] mem_la_addr;
output [31:0] mem_la_wdata;
output [3:0] mem_la_wstrb;
output pcpi_valid;
output [31:0] pcpi_insn;
output [31:0] pcpi_rs1;
output [31:0] pcpi_rs2;
output [31:0] eoi;
/* signal declarations */
wire [31:0] _9626;
wire [31:0] _9610;
wire [31:0] compare_eoi;
wire [31:0] _9628;
wire [31:0] _9629;
wire [31:0] _9611;
wire [31:0] compare_pcpi_rs2;
wire [31:0] _9631;
wire [31:0] _9632;
wire [31:0] _9612;
wire [31:0] compare_pcpi_rs1;
wire [31:0] _9634;
wire [31:0] _9635;
wire [31:0] _9613;
wire [31:0] compare_pcpi_insn;
wire [31:0] _9637;
wire _9638;
wire _9614;
wire compare_pcpi_valid;
wire _9640;
wire [3:0] _9641;
wire [3:0] _9615;
wire [3:0] compare_mem_la_wstrb;
wire [3:0] _9643;
wire [31:0] _9644;
wire [31:0] _9616;
wire [31:0] compare_mem_la_wdata;
wire [31:0] _9646;
wire [31:0] _9647;
wire [31:0] _9617;
wire [31:0] compare_mem_la_addr;
wire [31:0] _9649;
wire _9650;
wire _9618;
wire compare_mem_la_write;
wire _9652;
wire _9653;
wire _9619;
wire compare_mem_la_read;
wire _9655;
wire [3:0] _9656;
wire [3:0] _9620;
wire [3:0] compare_mem_wstrb;
wire [3:0] _9658;
wire [31:0] _9659;
wire [31:0] _9621;
wire [31:0] compare_mem_wdata;
wire [31:0] _9661;
wire [31:0] _9662;
wire [31:0] _9622;
wire [31:0] compare_mem_addr;
wire [31:0] _9664;
wire _9665;
wire _9623;
wire compare_mem_instr;
wire _9667;
wire _9668;
wire _9624;
wire compare_mem_valid;
wire _9670;
wire [269:0] _9607;
wire _9671;
wire [269:0] _9609;
wire _9625;
wire compare_trap;
wire _9673;
/* logic */
assign _9626 = _9607[269:238];
assign _9610 = _9609[269:238];
assign compare_eoi = _9610 ^ _9626;
assign _9628 = compare_eoi ^ _9626;
assign _9629 = _9607[237:206];
assign _9611 = _9609[237:206];
assign compare_pcpi_rs2 = _9611 ^ _9629;
assign _9631 = compare_pcpi_rs2 ^ _9629;
assign _9632 = _9607[205:174];
assign _9612 = _9609[205:174];
assign compare_pcpi_rs1 = _9612 ^ _9632;
assign _9634 = compare_pcpi_rs1 ^ _9632;
assign _9635 = _9607[173:142];
assign _9613 = _9609[173:142];
assign compare_pcpi_insn = _9613 ^ _9635;
assign _9637 = compare_pcpi_insn ^ _9635;
assign _9638 = _9607[141:141];
assign _9614 = _9609[141:141];
assign compare_pcpi_valid = _9614 ^ _9638;
assign _9640 = compare_pcpi_valid ^ _9638;
assign _9641 = _9607[140:137];
assign _9615 = _9609[140:137];
assign compare_mem_la_wstrb = _9615 ^ _9641;
assign _9643 = compare_mem_la_wstrb ^ _9641;
assign _9644 = _9607[136:105];
assign _9616 = _9609[136:105];
assign compare_mem_la_wdata = _9616 ^ _9644;
assign _9646 = compare_mem_la_wdata ^ _9644;
assign _9647 = _9607[104:73];
assign _9617 = _9609[104:73];
assign compare_mem_la_addr = _9617 ^ _9647;
assign _9649 = compare_mem_la_addr ^ _9647;
assign _9650 = _9607[72:72];
assign _9618 = _9609[72:72];
assign compare_mem_la_write = _9618 ^ _9650;
assign _9652 = compare_mem_la_write ^ _9650;
assign _9653 = _9607[71:71];
assign _9619 = _9609[71:71];
assign compare_mem_la_read = _9619 ^ _9653;
assign _9655 = compare_mem_la_read ^ _9653;
assign _9656 = _9607[70:67];
assign _9620 = _9609[70:67];
assign compare_mem_wstrb = _9620 ^ _9656;
assign _9658 = compare_mem_wstrb ^ _9656;
assign _9659 = _9607[66:35];
assign _9621 = _9609[66:35];
assign compare_mem_wdata = _9621 ^ _9659;
assign _9661 = compare_mem_wdata ^ _9659;
assign _9662 = _9607[34:3];
assign _9622 = _9609[34:3];
assign compare_mem_addr = _9622 ^ _9662;
assign _9664 = compare_mem_addr ^ _9662;
assign _9665 = _9607[2:2];
assign _9623 = _9609[2:2];
assign compare_mem_instr = _9623 ^ _9665;
assign _9667 = compare_mem_instr ^ _9665;
assign _9668 = _9607[1:1];
assign _9624 = _9609[1:1];
assign compare_mem_valid = _9624 ^ _9668;
assign _9670 = compare_mem_valid ^ _9668;
picorv32_rv32
the_picorv32_rv32
( .clk(clk), .resetn(resetn), .mem_ready(mem_ready), .mem_rdata(mem_rdata), .pcpi_wr(pcpi_wr), .pcpi_rd(pcpi_rd), .pcpi_wait(pcpi_wait), .pcpi_ready(pcpi_ready), .irq(irq), .eoi(_9607[269:238]), .pcpi_rs2(_9607[237:206]), .pcpi_rs1(_9607[205:174]), .pcpi_insn(_9607[173:142]), .pcpi_valid(_9607[141:141]), .mem_la_wstrb(_9607[140:137]), .mem_la_wdata(_9607[136:105]), .mem_la_addr(_9607[104:73]), .mem_la_write(_9607[72:72]), .mem_la_read(_9607[71:71]), .mem_wstrb(_9607[70:67]), .mem_wdata(_9607[66:35]), .mem_addr(_9607[34:3]), .mem_instr(_9607[2:2]), .mem_valid(_9607[1:1]), .trap(_9607[0:0]) );
assign _9671 = _9607[0:0];
opicorv32_rv32
the_opicorv32_rv32
( .clk(clk), .resetn(resetn), .mem_ready(mem_ready), .mem_rdata(mem_rdata), .pcpi_wr(pcpi_wr), .pcpi_rd(pcpi_rd), .pcpi_wait(pcpi_wait), .pcpi_ready(pcpi_ready), .irq(irq), .eoi(_9609[269:238]), .pcpi_rs2(_9609[237:206]), .pcpi_rs1(_9609[205:174]), .pcpi_insn(_9609[173:142]), .pcpi_valid(_9609[141:141]), .mem_la_wstrb(_9609[140:137]), .mem_la_wdata(_9609[136:105]), .mem_la_addr(_9609[104:73]), .mem_la_write(_9609[72:72]), .mem_la_read(_9609[71:71]), .mem_wstrb(_9609[70:67]), .mem_wdata(_9609[66:35]), .mem_addr(_9609[34:3]), .mem_instr(_9609[2:2]), .mem_valid(_9609[1:1]), .trap(_9609[0:0]) );
assign _9625 = _9609[0:0];
assign compare_trap = _9625 ^ _9671;
assign _9673 = compare_trap ^ _9671;
/* aliases */
/* output assignments */
assign trap = _9673;
assign mem_valid = _9670;
assign mem_instr = _9667;
assign mem_addr = _9664;
assign mem_wdata = _9661;
assign mem_wstrb = _9658;
assign mem_la_read = _9655;
assign mem_la_write = _9652;
assign mem_la_addr = _9649;
assign mem_la_wdata = _9646;
assign mem_la_wstrb = _9643;
assign pcpi_valid = _9640;
assign pcpi_insn = _9637;
assign pcpi_rs1 = _9634;
assign pcpi_rs2 = _9631;
assign eoi = _9628;
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_design_nios2_gen2_0_cpu_mult_cell (
// inputs:
E_src1,
E_src2,
M_en,
clk,
reset_n,
// outputs:
M_mul_cell_p1,
M_mul_cell_p2,
M_mul_cell_p3
)
;
output [ 31: 0] M_mul_cell_p1;
output [ 31: 0] M_mul_cell_p2;
output [ 31: 0] M_mul_cell_p3;
input [ 31: 0] E_src1;
input [ 31: 0] E_src2;
input M_en;
input clk;
input reset_n;
wire [ 31: 0] M_mul_cell_p1;
wire [ 31: 0] M_mul_cell_p2;
wire [ 31: 0] M_mul_cell_p3;
wire mul_clr;
wire [ 31: 0] mul_src1;
wire [ 31: 0] mul_src2;
assign mul_clr = ~reset_n;
assign mul_src1 = E_src1;
assign mul_src2 = E_src2;
altera_mult_add the_altmult_add_p1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p1)
);
defparam the_altmult_add_p1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p1.input_register_a0 = "UNREGISTERED",
the_altmult_add_p1.input_register_b0 = "UNREGISTERED",
the_altmult_add_p1.input_source_a0 = "DATAA",
the_altmult_add_p1.input_source_b0 = "DATAB",
the_altmult_add_p1.lpm_type = "altera_mult_add",
the_altmult_add_p1.multiplier1_direction = "ADD",
the_altmult_add_p1.multiplier_aclr0 = "ACLR0",
the_altmult_add_p1.multiplier_register0 = "CLOCK0",
the_altmult_add_p1.number_of_multipliers = 1,
the_altmult_add_p1.output_register = "UNREGISTERED",
the_altmult_add_p1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p1.representation_a = "UNSIGNED",
the_altmult_add_p1.representation_b = "UNSIGNED",
the_altmult_add_p1.selected_device_family = "CYCLONEV",
the_altmult_add_p1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p1.signed_register_a = "UNREGISTERED",
the_altmult_add_p1.signed_register_b = "UNREGISTERED",
the_altmult_add_p1.width_a = 16,
the_altmult_add_p1.width_b = 16,
the_altmult_add_p1.width_result = 32;
altera_mult_add the_altmult_add_p2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[31 : 16]),
.ena0 (M_en),
.result (M_mul_cell_p2)
);
defparam the_altmult_add_p2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p2.input_register_a0 = "UNREGISTERED",
the_altmult_add_p2.input_register_b0 = "UNREGISTERED",
the_altmult_add_p2.input_source_a0 = "DATAA",
the_altmult_add_p2.input_source_b0 = "DATAB",
the_altmult_add_p2.lpm_type = "altera_mult_add",
the_altmult_add_p2.multiplier1_direction = "ADD",
the_altmult_add_p2.multiplier_aclr0 = "ACLR0",
the_altmult_add_p2.multiplier_register0 = "CLOCK0",
the_altmult_add_p2.number_of_multipliers = 1,
the_altmult_add_p2.output_register = "UNREGISTERED",
the_altmult_add_p2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p2.representation_a = "UNSIGNED",
the_altmult_add_p2.representation_b = "UNSIGNED",
the_altmult_add_p2.selected_device_family = "CYCLONEV",
the_altmult_add_p2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p2.signed_register_a = "UNREGISTERED",
the_altmult_add_p2.signed_register_b = "UNREGISTERED",
the_altmult_add_p2.width_a = 16,
the_altmult_add_p2.width_b = 16,
the_altmult_add_p2.width_result = 32;
altera_mult_add the_altmult_add_p3
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[31 : 16]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p3)
);
defparam the_altmult_add_p3.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p3.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p3.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p3.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p3.input_register_a0 = "UNREGISTERED",
the_altmult_add_p3.input_register_b0 = "UNREGISTERED",
the_altmult_add_p3.input_source_a0 = "DATAA",
the_altmult_add_p3.input_source_b0 = "DATAB",
the_altmult_add_p3.lpm_type = "altera_mult_add",
the_altmult_add_p3.multiplier1_direction = "ADD",
the_altmult_add_p3.multiplier_aclr0 = "ACLR0",
the_altmult_add_p3.multiplier_register0 = "CLOCK0",
the_altmult_add_p3.number_of_multipliers = 1,
the_altmult_add_p3.output_register = "UNREGISTERED",
the_altmult_add_p3.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p3.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p3.representation_a = "UNSIGNED",
the_altmult_add_p3.representation_b = "UNSIGNED",
the_altmult_add_p3.selected_device_family = "CYCLONEV",
the_altmult_add_p3.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p3.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p3.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p3.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p3.signed_register_a = "UNREGISTERED",
the_altmult_add_p3.signed_register_b = "UNREGISTERED",
the_altmult_add_p3.width_a = 16,
the_altmult_add_p3.width_b = 16,
the_altmult_add_p3.width_result = 32;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTN_SYMBOL_V
`define SKY130_FD_SC_LP__SDFRTN_SYMBOL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTN_SYMBOL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_pcie_bram_7x.v
// Version : 1.11
// Description : single bram wrapper for the mb pcie block
// The bram A port is the write port
// the B port is the read port
//
//
//-----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_11_0_pcie_bram_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
parameter DOB_REG = 0, // 1 - use the output register;
// 0 - don't use the output register
parameter WIDTH = 0 // supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
// 72 - uses RAMB36SDP
)
(
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [12:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [12:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
(WIDTH == 9) ? 11 :
(WIDTH == 18) ? 10 :
(WIDTH == 36) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
(WIDTH == 36) ? 5 :
0 // for WIDTH 72 use RAMB36SDP
);
// map the data bits
localparam D_MSB = ((WIDTH == 4) ? 3 :
(WIDTH == 9) ? 7 :
(WIDTH == 18) ? 15 :
(WIDTH == 36) ? 31 :
63
);
// map the data parity bits
localparam DP_LSB = D_MSB + 1;
localparam DP_MSB = ((WIDTH == 4) ? 4 :
(WIDTH == 9) ? 8 :
(WIDTH == 18) ? 17 :
(WIDTH == 36) ? 35 :
71
);
localparam DPW = DP_MSB - DP_LSB + 1;
localparam WRITE_MODE = ((WIDTH == 72) && (!((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)))) ? "WRITE_FIRST" :
((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)) ? "WRITE_FIRST" : "NO_CHANGE";
localparam DEVICE = (IMPL_TARGET == "HARD") ? "7SERIES" : "VIRTEX6";
localparam BRAM_SIZE = "36Kb";
localparam WE_WIDTH =(DEVICE == "VIRTEX5" || DEVICE == "VIRTEX6" || DEVICE == "7SERIES") ?
((WIDTH <= 9) ? 1 :
(WIDTH > 9 && WIDTH <= 18) ? 2 :
(WIDTH > 18 && WIDTH <= 36) ? 4 :
(WIDTH > 36 && WIDTH <= 72) ? 8 :
(BRAM_SIZE == "18Kb") ? 4 : 8 ) : 8;
//synthesis translate_off
initial begin
//$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
// $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case (WIDTH)
4,9,18,36,72:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
generate
if ((LINK_CAP_MAX_LINK_WIDTH == 6'h08 && LINK_CAP_MAX_LINK_SPEED == 4'h2) || (WIDTH == 72)) begin : use_sdp
BRAM_SDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DO_REG (DOB_REG),
.READ_WIDTH (WIDTH),
.WRITE_WIDTH (WIDTH),
.WRITE_MODE (WRITE_MODE)
)
ramb36sdp(
.DO (rdata_o[WIDTH-1:0]),
.DI (wdata_i[WIDTH-1:0]),
.RDADDR (raddr_i[ADDR_MSB:0]),
.RDCLK (user_clk_i),
.RDEN (ren_i),
.REGCE (rce_i),
.RST (reset_i),
.WE ({WE_WIDTH{1'b1}}),
.WRADDR (waddr_i[ADDR_MSB:0]),
.WRCLK (user_clk_i),
.WREN (wen_i)
);
end // block: use_sdp
else if (WIDTH <= 36) begin : use_tdp
// use RAMB36's if the width is 4, 9, 18, or 36
BRAM_TDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (WIDTH),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (WIDTH),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.DOA (),
.DOB (rdata_o[WIDTH-1:0]),
.ADDRA (waddr_i[ADDR_MSB:0]),
.ADDRB (raddr_i[ADDR_MSB:0]),
.CLKA (user_clk_i),
.CLKB (user_clk_i),
.DIA (wdata_i[WIDTH-1:0]),
.DIB ({WIDTH{1'b0}}),
.ENA (wen_i),
.ENB (ren_i),
.REGCEA (1'b0),
.REGCEB (rce_i),
.RSTA (reset_i),
.RSTB (reset_i),
.WEA ({WE_WIDTH{1'b1}}),
.WEB ({WE_WIDTH{1'b0}})
);
end // block: use_tdp
endgenerate
endmodule // pcie_bram_7x
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_fg_burst_gen;
// Parameters
parameter FLOW_ADDR_WIDTH = 5;
parameter DEST_WIDTH = 8;
parameter RATE_SCALE = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg input_fd_valid = 0;
reg [7:0] input_fd_dest = 0;
reg [15:0] input_fd_rate_num = 0;
reg [15:0] input_fd_rate_denom = 0;
reg [31:0] input_fd_len = 0;
reg [31:0] input_fd_burst_len = 0;
reg output_bd_ready = 0;
// Outputs
wire input_fd_ready;
wire output_bd_valid;
wire [7:0] output_bd_dest;
wire [31:0] output_bd_burst_len;
wire busy;
wire [FLOW_ADDR_WIDTH-1:0] active_flows;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_fd_valid,
input_fd_dest,
input_fd_rate_num,
input_fd_rate_denom,
input_fd_len,
input_fd_burst_len,
output_bd_ready);
$to_myhdl(input_fd_ready,
output_bd_valid,
output_bd_dest,
output_bd_burst_len,
busy,
active_flows);
// dump file
$dumpfile("test_fg_burst_gen.lxt");
$dumpvars(0, test_fg_burst_gen);
end
fg_burst_gen #(
.FLOW_ADDR_WIDTH(FLOW_ADDR_WIDTH),
.DEST_WIDTH(DEST_WIDTH),
.RATE_SCALE(RATE_SCALE)
)
UUT (
.clk(clk),
.rst(rst),
// Flow descriptor input
.input_fd_valid(input_fd_valid),
.input_fd_ready(input_fd_ready),
.input_fd_dest(input_fd_dest),
.input_fd_rate_num(input_fd_rate_num),
.input_fd_rate_denom(input_fd_rate_denom),
.input_fd_len(input_fd_len),
.input_fd_burst_len(input_fd_burst_len),
// Burst descriptor output
.output_bd_valid(output_bd_valid),
.output_bd_ready(output_bd_ready),
.output_bd_dest(output_bd_dest),
.output_bd_burst_len(output_bd_burst_len),
// Status signals
.busy(busy),
// Configuration signals
.active_flows(active_flows)
);
endmodule
|
// megafunction wizard: %ALTFP_CONVERT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_CONVERT
// ============================================================
// File Name: int_to_fp.v
// Megafunction Name(s):
// ALTFP_CONVERT
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_convert CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" OPERATION="INT2FLOAT" ROUNDING="TO_NEAREST" WIDTH_DATA=32 WIDTH_EXP_INPUT=8 WIDTH_EXP_OUTPUT=11 WIDTH_INT=32 WIDTH_MAN_INPUT=23 WIDTH_MAN_OUTPUT=52 WIDTH_RESULT=64 clk_en clock dataa result
//VERSION_BEGIN 8.1 cbx_altbarrel_shift 2008:05:19:10:20:21:SJ cbx_altfp_convert 2008:09:12:02:26:36:SJ cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_altsyncram 2008:08:26:11:57:11:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_abs 2008:05:19:10:51:43:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_lpm_compare 2008:09:01:07:44:05:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_divide 2008:05:21:18:11:28:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_stratixiii 2008:07:11:13:32:02:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=2 SHIFTDIR="LEFT" SHIFTTYPE="LOGICAL" WIDTH=32 WIDTHDIST=5 aclr clk_en clock data distance result
//VERSION_BEGIN 8.1 cbx_altbarrel_shift 2008:05:19:10:20:21:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources = reg 66
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altbarrel_shift_brf
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [31:0] data;
input [4:0] distance;
output [31:0] result;
reg [31:0] pipe_wl1c;
reg [31:0] pipe_wl2c;
reg sel_pipel3d1c;
reg sel_pipel4d1c;
wire direction_w;
wire [15:0] pad_w;
wire [191:0] sbit_w;
wire [4:0] sel_w;
// synopsys translate_off
initial
pipe_wl1c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipe_wl1c <= 32'b0;
else if (clk_en == 1'b1) pipe_wl1c <= ((({32{(sel_w[2] & (~ direction_w))}} & {sbit_w[91:64], pad_w[3:0]}) | ({32{(sel_w[2] & direction_w)}} & {pad_w[3:0], sbit_w[95:68]})) | ({32{(~ sel_w[2])}} & sbit_w[95:64]));
// synopsys translate_off
initial
pipe_wl2c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipe_wl2c <= 32'b0;
else if (clk_en == 1'b1) pipe_wl2c <= ((({32{(sel_w[4] & (~ direction_w))}} & {sbit_w[143:128], pad_w[15:0]}) | ({32{(sel_w[4] & direction_w)}} & {pad_w[15:0], sbit_w[159:144]})) | ({32{(~ sel_w[4])}} & sbit_w[159:128]));
// synopsys translate_off
initial
sel_pipel3d1c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipel3d1c <= 1'b0;
else if (clk_en == 1'b1) sel_pipel3d1c <= distance[3];
// synopsys translate_off
initial
sel_pipel4d1c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipel4d1c <= 1'b0;
else if (clk_en == 1'b1) sel_pipel4d1c <= distance[4];
assign
direction_w = 1'b0,
pad_w = {16{1'b0}},
result = sbit_w[191:160],
sbit_w = {pipe_wl2c, ((({32{(sel_w[3] & (~ direction_w))}} & {sbit_w[119:96], pad_w[7:0]}) | ({32{(sel_w[3] & direction_w)}} & {pad_w[7:0], sbit_w[127:104]})) | ({32{(~ sel_w[3])}} & sbit_w[127:96])), pipe_wl1c, ((({32{(sel_w[1] & (~ direction_w))}} & {sbit_w[61:32], pad_w[1:0]}) | ({32{(sel_w[1] & direction_w)}} & {pad_w[1:0], sbit_w[63:34]})) | ({32{(~ sel_w[1])}} & sbit_w[63:32])), ((({32{(sel_w[0] & (~ direction_w))}} & {sbit_w[30:0], pad_w[0]}) | ({32{(sel_w[0] & direction_w)}} & {pad_w[0], sbit_w[31:1]})) | ({32{(~ sel_w[0])}} & sbit_w[31:0])), data},
sel_w = {sel_pipel4d1c, sel_pipel3d1c, distance[2:0]};
endmodule //int_to_fp_altbarrel_shift_brf
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //int_to_fp_altpriority_encoder_3v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //int_to_fp_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder12_q;
wire [0:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
int_to_fp_altpriority_encoder_3v7 altpriority_encoder12
(
.data(data[1:0]),
.q(wire_altpriority_encoder12_q));
int_to_fp_altpriority_encoder_3e8 altpriority_encoder13
(
.data(data[3:2]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
assign
q = {(~ wire_altpriority_encoder13_zero), ((wire_altpriority_encoder13_zero & wire_altpriority_encoder12_q) | ((~ wire_altpriority_encoder13_zero) & wire_altpriority_encoder13_q))};
endmodule //int_to_fp_altpriority_encoder_6v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
wire [0:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
int_to_fp_altpriority_encoder_3e8 altpriority_encoder14
(
.data(data[1:0]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
int_to_fp_altpriority_encoder_3e8 altpriority_encoder15
(
.data(data[3:2]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
assign
q = {(~ wire_altpriority_encoder15_zero), ((wire_altpriority_encoder15_zero & wire_altpriority_encoder14_q) | ((~ wire_altpriority_encoder15_zero) & wire_altpriority_encoder15_q))},
zero = (wire_altpriority_encoder14_zero & wire_altpriority_encoder15_zero);
endmodule //int_to_fp_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder10_q;
wire [1:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
int_to_fp_altpriority_encoder_6v7 altpriority_encoder10
(
.data(data[3:0]),
.q(wire_altpriority_encoder10_q));
int_to_fp_altpriority_encoder_6e8 altpriority_encoder11
(
.data(data[7:4]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
assign
q = {(~ wire_altpriority_encoder11_zero), (({2{wire_altpriority_encoder11_zero}} & wire_altpriority_encoder10_q) | ({2{(~ wire_altpriority_encoder11_zero)}} & wire_altpriority_encoder11_q))};
endmodule //int_to_fp_altpriority_encoder_bv7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
wire [1:0] wire_altpriority_encoder17_q;
wire wire_altpriority_encoder17_zero;
int_to_fp_altpriority_encoder_6e8 altpriority_encoder16
(
.data(data[3:0]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
int_to_fp_altpriority_encoder_6e8 altpriority_encoder17
(
.data(data[7:4]),
.q(wire_altpriority_encoder17_q),
.zero(wire_altpriority_encoder17_zero));
assign
q = {(~ wire_altpriority_encoder17_zero), (({2{wire_altpriority_encoder17_zero}} & wire_altpriority_encoder16_q) | ({2{(~ wire_altpriority_encoder17_zero)}} & wire_altpriority_encoder17_q))},
zero = (wire_altpriority_encoder16_zero & wire_altpriority_encoder17_zero);
endmodule //int_to_fp_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder8_q;
wire [2:0] wire_altpriority_encoder9_q;
wire wire_altpriority_encoder9_zero;
int_to_fp_altpriority_encoder_bv7 altpriority_encoder8
(
.data(data[7:0]),
.q(wire_altpriority_encoder8_q));
int_to_fp_altpriority_encoder_be8 altpriority_encoder9
(
.data(data[15:8]),
.q(wire_altpriority_encoder9_q),
.zero(wire_altpriority_encoder9_zero));
assign
q = {(~ wire_altpriority_encoder9_zero), (({3{wire_altpriority_encoder9_zero}} & wire_altpriority_encoder8_q) | ({3{(~ wire_altpriority_encoder9_zero)}} & wire_altpriority_encoder9_q))};
endmodule //int_to_fp_altpriority_encoder_r08
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
wire [2:0] wire_altpriority_encoder19_q;
wire wire_altpriority_encoder19_zero;
int_to_fp_altpriority_encoder_be8 altpriority_encoder18
(
.data(data[7:0]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
int_to_fp_altpriority_encoder_be8 altpriority_encoder19
(
.data(data[15:8]),
.q(wire_altpriority_encoder19_q),
.zero(wire_altpriority_encoder19_zero));
assign
q = {(~ wire_altpriority_encoder19_zero), (({3{wire_altpriority_encoder19_zero}} & wire_altpriority_encoder18_q) | ({3{(~ wire_altpriority_encoder19_zero)}} & wire_altpriority_encoder19_q))},
zero = (wire_altpriority_encoder18_zero & wire_altpriority_encoder19_zero);
endmodule //int_to_fp_altpriority_encoder_rf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_qb6
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder6_q;
wire [3:0] wire_altpriority_encoder7_q;
wire wire_altpriority_encoder7_zero;
int_to_fp_altpriority_encoder_r08 altpriority_encoder6
(
.data(data[15:0]),
.q(wire_altpriority_encoder6_q));
int_to_fp_altpriority_encoder_rf8 altpriority_encoder7
(
.data(data[31:16]),
.q(wire_altpriority_encoder7_q),
.zero(wire_altpriority_encoder7_zero));
assign
q = {(~ wire_altpriority_encoder7_zero), (({4{wire_altpriority_encoder7_zero}} & wire_altpriority_encoder6_q) | ({4{(~ wire_altpriority_encoder7_zero)}} & wire_altpriority_encoder7_q))};
endmodule //int_to_fp_altpriority_encoder_qb6
//synthesis_resources = lpm_add_sub 2 lpm_compare 1 reg 288
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altfp_convert_0jn
(
clk_en,
clock,
dataa,
result) ;
input clk_en;
input clock;
input [31:0] dataa;
output [63:0] result;
wire [31:0] wire_altbarrel_shift5_result;
wire [4:0] wire_altpriority_encoder2_q;
reg [10:0] exponent_bus_pre_reg;
reg [10:0] exponent_bus_pre_reg2;
reg [10:0] exponent_bus_pre_reg3;
reg [30:0] mag_int_a_reg;
reg [30:0] mag_int_a_reg2;
reg [52:0] mantissa_pre_round_reg;
reg [4:0] priority_encoder_reg;
reg [63:0] result_reg;
reg sign_int_a_reg1;
reg sign_int_a_reg2;
reg sign_int_a_reg3;
reg sign_int_a_reg4;
reg sign_int_a_reg5;
wire [30:0] wire_add_sub1_result;
wire [10:0] wire_add_sub3_result;
wire wire_cmpr4_alb;
wire aclr;
wire [10:0] bias_value_w;
wire [10:0] const_bias_value_add_width_int_w;
wire [10:0] exceptions_value;
wire [10:0] exponent_bus;
wire [10:0] exponent_bus_pre;
wire [10:0] exponent_output_w;
wire [10:0] exponent_rounded;
wire [10:0] exponent_zero_w;
wire [30:0] int_a;
wire [30:0] int_a_2s;
wire [30:0] invert_int_a;
wire [4:0] leading_zeroes;
wire [30:0] mag_int_a;
wire [51:0] mantissa_bus;
wire [52:0] mantissa_pre_round;
wire [52:0] mantissa_rounded;
wire max_neg_value_selector;
wire [10:0] max_neg_value_w;
wire [10:0] minus_leading_zero;
wire [31:0] prio_mag_int_a;
wire [63:0] result_w;
wire [30:0] shifted_mag_int_a;
wire sign_bus;
wire sign_int_a;
wire [5:0] zero_padding_w;
int_to_fp_altbarrel_shift_brf altbarrel_shift5
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({1'b0, mag_int_a_reg2}),
.distance(leading_zeroes),
.result(wire_altbarrel_shift5_result));
int_to_fp_altpriority_encoder_qb6 altpriority_encoder2
(
.data(prio_mag_int_a),
.q(wire_altpriority_encoder2_q));
// synopsys translate_off
initial
exponent_bus_pre_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg <= 11'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg <= exponent_bus_pre_reg2;
// synopsys translate_off
initial
exponent_bus_pre_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg2 <= 11'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg2 <= exponent_bus_pre_reg3;
// synopsys translate_off
initial
exponent_bus_pre_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg3 <= 11'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg3 <= exponent_bus_pre;
// synopsys translate_off
initial
mag_int_a_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg <= 31'b0;
else if (clk_en == 1'b1) mag_int_a_reg <= mag_int_a;
// synopsys translate_off
initial
mag_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg2 <= 31'b0;
else if (clk_en == 1'b1) mag_int_a_reg2 <= mag_int_a_reg;
// synopsys translate_off
initial
mantissa_pre_round_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissa_pre_round_reg <= 53'b0;
else if (clk_en == 1'b1) mantissa_pre_round_reg <= mantissa_pre_round;
// synopsys translate_off
initial
priority_encoder_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) priority_encoder_reg <= 5'b0;
else if (clk_en == 1'b1) priority_encoder_reg <= wire_altpriority_encoder2_q;
// synopsys translate_off
initial
result_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) result_reg <= 64'b0;
else if (clk_en == 1'b1) result_reg <= result_w;
// synopsys translate_off
initial
sign_int_a_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg1 <= sign_int_a;
// synopsys translate_off
initial
sign_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg2 <= sign_int_a_reg1;
// synopsys translate_off
initial
sign_int_a_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg3 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg3 <= sign_int_a_reg2;
// synopsys translate_off
initial
sign_int_a_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg4 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg4 <= sign_int_a_reg3;
// synopsys translate_off
initial
sign_int_a_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg5 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg5 <= sign_int_a_reg4;
lpm_add_sub add_sub1
(
.cout(),
.dataa(invert_int_a),
.datab(31'b0000000000000000000000000000001),
.overflow(),
.result(wire_add_sub1_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "ADD",
add_sub1.lpm_width = 31,
add_sub1.lpm_type = "lpm_add_sub",
add_sub1.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub3
(
.cout(),
.dataa(const_bias_value_add_width_int_w),
.datab(minus_leading_zero),
.overflow(),
.result(wire_add_sub3_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_width = 11,
add_sub3.lpm_type = "lpm_add_sub",
add_sub3.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_compare cmpr4
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr4_alb),
.aleb(),
.aneb(),
.dataa(exponent_output_w),
.datab(bias_value_w)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
cmpr4.lpm_representation = "UNSIGNED",
cmpr4.lpm_width = 11,
cmpr4.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
bias_value_w = 11'b01111111111,
const_bias_value_add_width_int_w = 11'b10000011101,
exceptions_value = (({11{(~ max_neg_value_selector)}} & exponent_zero_w) | ({11{max_neg_value_selector}} & max_neg_value_w)),
exponent_bus = exponent_rounded,
exponent_bus_pre = (({11{(~ wire_cmpr4_alb)}} & exponent_output_w) | ({11{wire_cmpr4_alb}} & exceptions_value)),
exponent_output_w = wire_add_sub3_result,
exponent_rounded = exponent_bus_pre_reg,
exponent_zero_w = {11{1'b0}},
int_a = dataa[30:0],
int_a_2s = wire_add_sub1_result,
invert_int_a = (~ int_a),
leading_zeroes = (~ priority_encoder_reg),
mag_int_a = (({31{(~ sign_int_a)}} & int_a) | ({31{sign_int_a}} & int_a_2s)),
mantissa_bus = mantissa_rounded[51:0],
mantissa_pre_round = {shifted_mag_int_a[30:0], 22'b0000000000000000000000},
mantissa_rounded = mantissa_pre_round_reg,
max_neg_value_selector = (wire_cmpr4_alb & sign_int_a_reg2),
max_neg_value_w = 11'b10000011110,
minus_leading_zero = {zero_padding_w, leading_zeroes},
prio_mag_int_a = {mag_int_a_reg, 1'b1},
result = result_reg,
result_w = {sign_bus, exponent_bus, mantissa_bus},
shifted_mag_int_a = wire_altbarrel_shift5_result[30:0],
sign_bus = sign_int_a_reg5,
sign_int_a = dataa[31],
zero_padding_w = {6{1'b0}};
endmodule //int_to_fp_altfp_convert_0jn
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module int_to_fp (
clk_en,
clock,
dataa,
result);
input clk_en;
input clock;
input [31:0] dataa;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
int_to_fp_altfp_convert_0jn int_to_fp_altfp_convert_0jn_component (
.dataa (dataa),
.clk_en (clk_en),
.clock (clock),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_convert"
// Retrieval info: CONSTANT: OPERATION STRING "INT2FLOAT"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_DATA NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_EXP_INPUT NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_EXP_OUTPUT NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_INT NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_MAN_INPUT NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH_MAN_OUTPUT NUMERIC "52"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "64"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT GND "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT GND "dataa[31..0]"
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT GND "result[63..0]"
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.cmp FALSE TRUE
// Retrieval info: LIB_FILE: lpm
|
//==================================================================================================
// Filename : musb_control_unit.v
// Created On : 2014-09-23 20:18:05
// Last Modified : 2015-05-28 20:31:01
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Instruction decode and control unit (no pipeline control)
//==================================================================================================
`include "musb_defines.v"
module musb_control_unit#(
parameter ENABLE_HW_MULT = 1, // Implement the multiplier
parameter ENABLE_HW_DIV = 1, // Implement the divider
parameter ENABLE_HW_CLO_Z = 1 // Implement the CLO/CLZ
)(
input [5:0] opcode, // The instruction opcode
input [5:0] op_function, // For RR-type instruction
input [4:0] op_rs, // For mtc0 and mfc0 instructions
input [4:0] op_rt, // For branch instructions
output id_imm_sign_ext, // sign extend the imm16
output id_movn, // MOVN instruction
output id_movz, // MOVZ instruction
output id_llsc, // LL/SC instructions
output id_syscall, // Syscall exception
output id_breakpoint, // Breakpoint exception
output id_reserved, // Reserved instruction exception
output id_mfc0, // Coprocessor 0 instruction
output id_mtc0, // Coprocessor 0 instruction
output id_eret, // Coprocessor 0 instruction
output id_cp1, // Coprocessor 1 instruction
output id_cp2, // Coprocessor 2 instruction
output id_cp3, // Coprocessor 3 instruction
output id_id_exception_source, // Instruction is a potential source of exception
output id_ex_exception_source, // Instruction is a potential source of exception
output id_mem_exception_source, // Instruction is a potential source of exception
output id_trap, // Trap instruction
output id_trap_condition, // Trap condition
output id_gpr_we, // write data from WB stage, to GPR
output id_mem_to_gpr_select, // Select GPR write data: MEM or ALU
output [4:0] id_alu_operation, // ALU function
output [1:0] id_alu_port_a_select, // Shift, jump and link
output [1:0] id_alu_port_b_select, // R-instruction, I-instruction or jump
output [1:0] id_gpr_wa_select, // Select GPR write address
output id_jump, // Jump instruction
output id_branch, // Branch instruction
output id_mem_write, // Write to Memory: 0 = read, 1 = write.
output id_mem_byte, // Read/Write one byte
output id_mem_halfword, // Read/Write halfword (16 bits)
output id_mem_data_sign_ext // Sign extend for byte/halfword memory operations
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [20:0] datapath; // all control signals
reg [2:0] exception_source; // exception source signals
//--------------------------------------------------------------------------
// Signal Declaration: wires
//--------------------------------------------------------------------------
wire no_mult;
wire no_div;
wire no_clo_clz;
//--------------------------------------------------------------------------
// assigments
//--------------------------------------------------------------------------
assign id_imm_sign_ext = (opcode != `OP_ANDI) & (opcode != `OP_ORI) & (opcode != `OP_XORI); // The only ones to use the zero ext
assign id_movn = (opcode == `OP_TYPE_R) & (op_function == `FUNCTION_OP_MOVN);
assign id_movz = (opcode == `OP_TYPE_R) & (op_function == `FUNCTION_OP_MOVZ);
assign id_llsc = (opcode == `OP_LL) | (opcode == `OP_SC);
assign id_syscall = (opcode == `OP_TYPE_R) & (op_function == `FUNCTION_OP_SYSCALL);
assign id_breakpoint = (opcode == `OP_TYPE_R) & (op_function == `FUNCTION_OP_BREAK);
assign id_mfc0 = (opcode == `OP_TYPE_CP0) & (op_rs == `RS_OP_MFC);
assign id_mtc0 = (opcode == `OP_TYPE_CP0) & (op_rs == `RS_OP_MTC);
assign id_eret = (opcode == `OP_TYPE_CP0) & (op_rs == `RS_OP_ERET) & (op_function == `FUNCTION_OP_ERET);
assign id_cp1 = (opcode == `OP_TYPE_CP1);
assign id_cp2 = (opcode == `OP_TYPE_CP2);
assign id_cp3 = (opcode == `OP_TYPE_CP3);
assign id_reserved = no_mult | no_div | no_clo_clz;
//--------------------------------------------------------------------------
// Check for mult instructions
//--------------------------------------------------------------------------
generate
if(ENABLE_HW_MULT) begin
assign no_mult = 1'b0;
end
else begin
assign no_mult = ((datapath[20:16] == `ALU_OP_MADD) | (datapath[20:16] == `ALU_OP_MADDU) |
(datapath[20:16] == `ALU_OP_MSUB) | (datapath[20:16] == `ALU_OP_MSUBU) |
(datapath[20:16] == `ALU_OP_MULS) | (datapath[20:16] == `ALU_OP_MULU));
end
endgenerate
//--------------------------------------------------------------------------
// Check for div instructions
//--------------------------------------------------------------------------
generate
if(ENABLE_HW_DIV) begin
assign no_div = 1'b0;
end
else begin
assign no_div = ((datapath[20:16] == `ALU_OP_DIV) | (datapath[20:16] == `ALU_OP_DIVU));
end
endgenerate
//--------------------------------------------------------------------------
// Check for CL0/CLZ instructions
//--------------------------------------------------------------------------
generate
if(ENABLE_HW_CLO_Z) begin
assign no_clo_clz = 1'b0;
end
else begin
assign no_clo_clz = ((datapath[20:16] == `ALU_OP_CLO) | (datapath[20:16] == `ALU_OP_CLZ));
end
endgenerate
/*
Exception.
All signals are active High.
----------------------------------------------------------------------------
Bit Meaning
----------------------------------------------------------------------------
2 : Instruction can cause exception @ ID
1 : Instruction can cause exception @ EX
0 : Instruction can cause exception @ MEM
----------------------------------------------------------------------------
*/
assign id_id_exception_source = exception_source[2];
assign id_ex_exception_source = exception_source[1];
assign id_mem_exception_source = exception_source[0];
/*
Datapath controls.
All signals are active High.
----------------------------------------------------------------------------
Bit Name Description
----------------------------------------------------------------------------
20 : id_alu_operation Operation to execute.
19 : .
18 : .
17 : .
16 : .
-------------------------------
15: id_trap Trap instruction
14: id_trap_condition Condition: ALU result = 0 (0), ALU result != 0 (1)
-------------------------------
13 : id_gpr_we Write enable (GPR)
12 : id_mem_to_gpr_select Select data: ALU(0), MEM(1)
-------------------------------
11 : id_alu_port_a_select Select: Rs(0), shamt(1), 0x04(2), 0x10(3)
10 : .
9 : id_alu_port_b_select Select: Rt(0), SImm16(1), PCAdd4(2), ZImm16(3)
8 : .
7 : id_gpr_wa_select Select register: Rd(0), Rt(1), 31(2)
6 : .
-------------------------------
5 : id_jump Jump instruction
4 : id_branch Branch instruction
-------------------------------
3 : id_mem_write Write to data memory
2 : id_mem_byte Enable read/write one byte
1 : id_mem_halfword Enable read/write 2 bytes (16 bits data)
0 : id_mem_data_sign_ext Zero extend data (0) or Sign extend data (1)
----------------------------------------------------------------------------
*/
assign id_alu_operation = datapath[20:16];
assign id_trap = datapath[15];
assign id_trap_condition = datapath[14];
assign id_gpr_we = datapath[13];
assign id_mem_to_gpr_select = datapath[12];
assign id_alu_port_a_select = datapath[11:10];
assign id_alu_port_b_select = datapath[9:8];
assign id_gpr_wa_select = datapath[7:6];
assign id_jump = datapath[5];
assign id_branch = datapath[4];
assign id_mem_write = datapath[3];
assign id_mem_byte = datapath[2];
assign id_mem_halfword = datapath[1];
assign id_mem_data_sign_ext = datapath[0];
//--------------------------------------------------------------------------
// set the control signals
//--------------------------------------------------------------------------
always @(*) begin
case(opcode)
`OP_TYPE_R : begin
case (op_function)
`FUNCTION_OP_ADD : begin datapath <= `DP_ADD; exception_source <= `EXC_ADD; end
`FUNCTION_OP_ADDU : begin datapath <= `DP_ADDU; exception_source <= `EXC_ADDU; end
`FUNCTION_OP_AND : begin datapath <= `DP_AND; exception_source <= `EXC_AND; end
`FUNCTION_OP_BREAK : begin datapath <= `DP_BREAK; exception_source <= `EXC_BREAK; end
`FUNCTION_OP_DIV : begin datapath <= `DP_DIV; exception_source <= `EXC_DIV; end
`FUNCTION_OP_DIVU : begin datapath <= `DP_DIVU; exception_source <= `EXC_DIVU; end
`FUNCTION_OP_JALR : begin datapath <= `DP_JALR; exception_source <= `EXC_JALR; end
`FUNCTION_OP_JR : begin datapath <= `DP_JR; exception_source <= `EXC_JR; end
`FUNCTION_OP_MFHI : begin datapath <= `DP_MFHI; exception_source <= `EXC_MFHI; end
`FUNCTION_OP_MFLO : begin datapath <= `DP_MFLO; exception_source <= `EXC_MFLO; end
`FUNCTION_OP_MOVN : begin datapath <= `DP_MOVN; exception_source <= `EXC_MOVN; end
`FUNCTION_OP_MOVZ : begin datapath <= `DP_MOVZ; exception_source <= `EXC_MOVZ; end
`FUNCTION_OP_MTHI : begin datapath <= `DP_MTHI; exception_source <= `EXC_MTHI; end
`FUNCTION_OP_MTLO : begin datapath <= `DP_MTLO; exception_source <= `EXC_MTLO; end
`FUNCTION_OP_MULT : begin datapath <= `DP_MULT; exception_source <= `EXC_MULT; end
`FUNCTION_OP_MULTU : begin datapath <= `DP_MULTU; exception_source <= `EXC_MULTU; end
`FUNCTION_OP_NOR : begin datapath <= `DP_NOR; exception_source <= `EXC_NOR; end
`FUNCTION_OP_OR : begin datapath <= `DP_OR; exception_source <= `EXC_OR; end
`FUNCTION_OP_SLL : begin datapath <= `DP_SLL; exception_source <= `EXC_SLL; end
`FUNCTION_OP_SLLV : begin datapath <= `DP_SLLV; exception_source <= `EXC_SLLV; end
`FUNCTION_OP_SLT : begin datapath <= `DP_SLT; exception_source <= `EXC_SLT; end
`FUNCTION_OP_SLTU : begin datapath <= `DP_SLTU; exception_source <= `EXC_SLTU; end
`FUNCTION_OP_SRA : begin datapath <= `DP_SRA; exception_source <= `EXC_SRA; end
`FUNCTION_OP_SRAV : begin datapath <= `DP_SRAV; exception_source <= `EXC_SRAV; end
`FUNCTION_OP_SRL : begin datapath <= `DP_SRL; exception_source <= `EXC_SRL; end
`FUNCTION_OP_SRLV : begin datapath <= `DP_SRLV; exception_source <= `EXC_SRLV; end
`FUNCTION_OP_SUB : begin datapath <= `DP_SUB; exception_source <= `EXC_SUB; end
`FUNCTION_OP_SUBU : begin datapath <= `DP_SUBU; exception_source <= `EXC_SUBU; end
`FUNCTION_OP_SYSCALL : begin datapath <= `DP_SYSCALL; exception_source <= `EXC_SYSCALL; end
`FUNCTION_OP_TEQ : begin datapath <= `DP_TEQ; exception_source <= `EXC_TEQ; end
`FUNCTION_OP_TGE : begin datapath <= `DP_TGE; exception_source <= `EXC_TGE; end
`FUNCTION_OP_TGEU : begin datapath <= `DP_TGEU; exception_source <= `EXC_TGEU; end
`FUNCTION_OP_TLT : begin datapath <= `DP_TLT; exception_source <= `EXC_TLT; end
`FUNCTION_OP_TLTU : begin datapath <= `DP_TLTU; exception_source <= `EXC_TLTU; end
`FUNCTION_OP_TNE : begin datapath <= `DP_TNE; exception_source <= `EXC_TNE; end
`FUNCTION_OP_XOR : begin datapath <= `DP_XOR; exception_source <= `EXC_XOR; end
default : begin datapath <= `DP_NONE; exception_source <= `EXC_ADDU; end
endcase
end
`OP_TYPE_R2 : begin
case (op_function)
`FUNCTION_OP_CLO : begin datapath <= `DP_CLO; exception_source <= `EXC_CLO; end
`FUNCTION_OP_CLZ : begin datapath <= `DP_CLZ; exception_source <= `EXC_CLZ; end
`FUNCTION_OP_MADD : begin datapath <= `DP_MADD; exception_source <= `EXC_MADD; end
`FUNCTION_OP_MADDU : begin datapath <= `DP_MADDU; exception_source <= `EXC_MADDU; end
`FUNCTION_OP_MSUB : begin datapath <= `DP_MSUB; exception_source <= `EXC_MSUB; end
`FUNCTION_OP_MSUBU : begin datapath <= `DP_MSUBU; exception_source <= `EXC_MSUBU; end
default : begin datapath <= `DP_NONE; exception_source <= `EXC_ADDU; end
endcase
end
`OP_TYPE_REGIMM : begin
case (op_rt)
`RT_OP_BGEZ : begin datapath <= `DP_BGEZ; exception_source <= `EXC_BGEZ; end
`RT_OP_BGEZAL : begin datapath <= `DP_BGEZAL; exception_source <= `EXC_BGEZAL; end
`RT_OP_BLTZ : begin datapath <= `DP_BLTZ; exception_source <= `EXC_BLTZ; end
`RT_OP_BLTZAL : begin datapath <= `DP_BLTZAL; exception_source <= `EXC_BLTZAL; end
`RT_OP_TEQI : begin datapath <= `DP_TEQI; exception_source <= `EXC_TEQI; end
`RT_OP_TGEI : begin datapath <= `DP_TGEI; exception_source <= `EXC_TGEI; end
`RT_OP_TGEIU : begin datapath <= `DP_TGEIU; exception_source <= `EXC_TGEIU; end
`RT_OP_TLTI : begin datapath <= `DP_TLTI; exception_source <= `EXC_TLTI; end
`RT_OP_TLTIU : begin datapath <= `DP_TLTIU; exception_source <= `EXC_TLTIU; end
`RT_OP_TNEI : begin datapath <= `DP_TNEI; exception_source <= `EXC_TNEI; end
default : begin datapath <= `DP_NONE; exception_source <= `EXC_ADDU; end
endcase
end
`OP_TYPE_CP0 : begin
case (op_rs)
`RS_OP_MFC : begin datapath <= `DP_MFC0; exception_source <= `EXC_MFC0; end
`RS_OP_MTC : begin datapath <= `DP_MTC0; exception_source <= `EXC_MTC0; end
`RS_OP_ERET : begin datapath <= `DP_ERET; exception_source <= `EXC_ERET; end
default : begin datapath <= `DP_NONE; exception_source <= `EXC_ADDU; end
endcase
end
`OP_ADDI : begin datapath <= `DP_ADDI; exception_source <= `EXC_ADDI; end
`OP_ADDIU : begin datapath <= `DP_ADDIU; exception_source <= `EXC_ADDIU; end
`OP_ANDI : begin datapath <= `DP_ANDI; exception_source <= `EXC_ANDI; end
`OP_BEQ : begin datapath <= `DP_BEQ; exception_source <= `EXC_BEQ; end
`OP_BGTZ : begin datapath <= `DP_BGTZ; exception_source <= `EXC_BGTZ; end
`OP_BLEZ : begin datapath <= `DP_BLEZ; exception_source <= `EXC_BLEZ; end
`OP_BNE : begin datapath <= `DP_BNE; exception_source <= `EXC_BNE; end
`OP_J : begin datapath <= `DP_J; exception_source <= `EXC_J; end
`OP_JAL : begin datapath <= `DP_JAL; exception_source <= `EXC_JAL; end
`OP_LB : begin datapath <= `DP_LB; exception_source <= `EXC_LB; end
`OP_LBU : begin datapath <= `DP_LBU; exception_source <= `EXC_LBU; end
`OP_LH : begin datapath <= `DP_LH; exception_source <= `EXC_LH; end
`OP_LHU : begin datapath <= `DP_LHU; exception_source <= `EXC_LHU; end
`OP_LL : begin datapath <= `DP_LL; exception_source <= `EXC_LL; end
`OP_LUI : begin datapath <= `DP_LUI; exception_source <= `EXC_LUI; end
`OP_LW : begin datapath <= `DP_LW; exception_source <= `EXC_LW; end
`OP_ORI : begin datapath <= `DP_ORI; exception_source <= `EXC_ORI; end
`OP_SB : begin datapath <= `DP_SB; exception_source <= `EXC_SB; end
`OP_SC : begin datapath <= `DP_SC; exception_source <= `EXC_SC; end
`OP_SH : begin datapath <= `DP_SH; exception_source <= `EXC_SH; end
`OP_SLTI : begin datapath <= `DP_SLTI; exception_source <= `EXC_SLTI; end
`OP_SLTIU : begin datapath <= `DP_SLTIU; exception_source <= `EXC_SLTIU; end
`OP_SW : begin datapath <= `DP_SW; exception_source <= `EXC_SW; end
`OP_XORI : begin datapath <= `DP_XORI; exception_source <= `EXC_XORI; end
default : begin datapath <= `DP_NONE; exception_source <= `EXC_ADDU; end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__clkinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V |
/*
_______________________________________________________________________________
Copyright (c) 2012 TU Dresden, Chair for Embedded Systems
(http://www.mr.inf.tu-dresden.de) All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this software
must display the following acknowledgement: "This product includes
software developed by the TU Dresden Chair for Embedded Systems and
its contributors."
4. Neither the name of the TU Dresden Chair for Embedded Systems nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY TU DRESDEN CHAIR FOR EMBEDDED SYSTEMS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
_______________________________________________________________________________
*/
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 13:45:33 09/20/2011
// Module Name: uart_light_rx
//////////////////////////////////////////////////////////////////////////////////
module uart_light_rx
#(
parameter SAMPLING_COUNT = 15,
parameter SC_SIZE = 4,
parameter WORD_SIZE = 8,
parameter FIFO_ADDR_BITS = 5
)(
input wire reset,
input wire clk_peri,
input wire clk_rx,
input wire read_ready,
input wire rx,
output wire [WORD_SIZE-1:0] word_rx,
output wire fifo_rx_empty,
output wire fifo_rx_full
);
wire fifo_full,fifo_empty,bit_eq_0,sc_full,frame_done,sc_halb,sc_inc,sc_clr,bc_inc,bc_clr,shift,fifo_write_enable,fifo_read_enable;
uart_light_rx_ctrl
rx_ctrl0
(
.reset(reset),
.clk_rx(clk_rx),
.read_ready(read_ready),
.fifo_rx_full(fifo_rx_full),
.fifo_rx_empty(fifo_rx_empty),
.fifo_full(fifo_full),
.fifo_empty(fifo_empty),
.bit_eq_0(bit_eq_0),
.sc_halb(sc_halb),
.sc_full(sc_full),
.frame_done(frame_done),
.sc_inc(sc_inc),
.sc_clr(sc_clr),
.bc_inc(bc_inc),
.bc_clr(bc_clr),
.shift(shift),
.fifo_write_enable(fifo_write_enable),
.fifo_read_enable(fifo_read_enable)
);
uart_light_rx_dp
#(
.SAMPLING_COUNT(SAMPLING_COUNT),
.SC_SIZE(SC_SIZE),
.FIFO_ADDR_BITS(FIFO_ADDR_BITS)
)
rx_dp0
(
.reset(reset),
.clk_peri(clk_peri),
.clk_rx(clk_rx),
.rx(rx),
.word_rx(word_rx),
.sc_inc(sc_inc),
.sc_clr(sc_clr),
.bc_inc(bc_inc),
.bc_clr(bc_clr),
.shift(shift),
.fifo_write_enable(fifo_write_enable),
.bit_eq_0(bit_eq_0),
.sc_halb(sc_halb),
.sc_full(sc_full),
.frame_done(frame_done),
.fifo_read_enable(fifo_read_enable),
.fifo_full(fifo_full),
.fifo_empty(fifo_empty)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_wb.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core WISHBONE interface. ////
//// ////
//// Known problems (limits): ////
//// Inserts one wait state on all transfers. ////
//// Note affected signals and the way they are affected. ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.16 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.15 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.12 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.11 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.10 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.9 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.8 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/21 19:12:01 gorban
// Corrected some Linter messages.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:13+02 jacob
// Initial revision
//
//
// UART core WISHBONE interface
//
// Author: Jacob Gorban ([email protected])
// Company: Flextronics Semiconductor
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_wb (clk, wb_rst_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
we_o, re_o // Write and read enable output for the core
);
input clk;
// WISHBONE interface
input wb_rst_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
input [`UART_ADDR_WIDTH-1:0] wb_adr_i; //WISHBONE address line
`ifdef DATA_BUS_WIDTH_8
input [7:0] wb_dat_i; //input WISHBONE bus
output [7:0] wb_dat_o;
reg [7:0] wb_dat_o;
wire [7:0] wb_dat_i;
reg [7:0] wb_dat_is;
`else // for 32 data bus mode
input [31:0] wb_dat_i; //input WISHBONE bus
output [31:0] wb_dat_o;
reg [31:0] wb_dat_o;
wire [31:0] wb_dat_i;
reg [31:0] wb_dat_is;
`endif // !`ifdef DATA_BUS_WIDTH_8
output [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
output [7:0] wb_dat8_i;
input [31:0] wb_dat32_o; // 32 bit data output (for debug interface)
output wb_ack_o;
output we_o;
output re_o;
wire we_o;
reg wb_ack_o;
reg [7:0] wb_dat8_i;
wire [7:0] wb_dat8_o;
wire [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
reg [`UART_ADDR_WIDTH-1:0] wb_adr_is;
reg wb_we_is;
reg wb_cyc_is;
reg wb_stb_is;
reg [3:0] wb_sel_is;
wire [3:0] wb_sel_i;
reg wre ;// timing control signal for write or read enable
// wb_ack_o FSM
reg [1:0] wbstate;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_ack_o <= 1'b0;
wbstate <= 0;
wre <= 1'b1;
end else
case (wbstate)
0: begin
if (wb_stb_is & wb_cyc_is) begin
wre <= 0;
wbstate <= 1;
wb_ack_o <= 1;
end else begin
wre <= 1;
wb_ack_o <= 0;
end
end
1: begin
wb_ack_o <= 0;
wbstate <= 2;
wre <= 0;
end
2: begin
wb_ack_o <= 0;
wbstate <= 3;
wre <= 0;
end
3: begin
wb_ack_o <= 0;
wbstate <= 0;
wre <= 1;
end
endcase
assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers
assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers
// Sample input signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_adr_is <= 0;
wb_we_is <= 0;
wb_cyc_is <= 0;
wb_stb_is <= 0;
wb_dat_is <= 0;
wb_sel_is <= 0;
end else begin
wb_adr_is <= wb_adr_i;
wb_we_is <= wb_we_i;
wb_cyc_is <= wb_cyc_i;
wb_stb_is <= wb_stb_i;
wb_dat_is <= wb_dat_i;
wb_sel_is <= wb_sel_i;
end
`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= 0;
else
wb_dat_o <= wb_dat8_o;
always @(wb_dat_is)
wb_dat8_i = wb_dat_is;
assign wb_adr_int = wb_adr_is;
`else // 32-bit bus
// put output to the correct byte in 32 bits using select line
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= 0;
else if (re_o)
case (wb_sel_is)
4'b0001: wb_dat_o <= {24'b0, wb_dat8_o};
4'b0010: wb_dat_o <= {16'b0, wb_dat8_o, 8'b0};
4'b0100: wb_dat_o <= {8'b0, wb_dat8_o, 16'b0};
4'b1000: wb_dat_o <= {wb_dat8_o, 24'b0};
4'b1111: wb_dat_o <= wb_dat32_o; // debug interface output
default: wb_dat_o <= 0;
endcase // case(wb_sel_i)
reg [1:0] wb_adr_int_lsb;
always @(wb_sel_is or wb_dat_is)
begin
case (wb_sel_is)
4'b0001 : wb_dat8_i = wb_dat_is[7:0];
4'b0010 : wb_dat8_i = wb_dat_is[15:8];
4'b0100 : wb_dat8_i = wb_dat_is[23:16];
4'b1000 : wb_dat8_i = wb_dat_is[31:24];
default : wb_dat8_i = wb_dat_is[7:0];
endcase // case(wb_sel_i)
`ifdef LITLE_ENDIAN
case (wb_sel_is)
4'b0001 : wb_adr_int_lsb = 2'h0;
4'b0010 : wb_adr_int_lsb = 2'h1;
4'b0100 : wb_adr_int_lsb = 2'h2;
4'b1000 : wb_adr_int_lsb = 2'h3;
default : wb_adr_int_lsb = 2'h0;
endcase // case(wb_sel_i)
`else
case (wb_sel_is)
4'b0001 : wb_adr_int_lsb = 2'h3;
4'b0010 : wb_adr_int_lsb = 2'h2;
4'b0100 : wb_adr_int_lsb = 2'h1;
4'b1000 : wb_adr_int_lsb = 2'h0;
default : wb_adr_int_lsb = 2'h0;
endcase // case(wb_sel_i)
`endif
end
`ifdef WISHBONE_CPU_OR1200
assign wb_adr_int = {2'b00,wb_adr_is[`UART_ADDR_WIDTH-1:2]};
`else
assign wb_adr_int = {wb_adr_is[`UART_ADDR_WIDTH-1:2], wb_adr_int_lsb};
`endif
`endif // !`ifdef DATA_BUS_WIDTH_8
endmodule
|
module top(clk, rst_, abus, dbus, mem_re_, mem_we_);
input clk;
input rst_;
output[7:0] abus;
output[7:0] dbus;
output mem_re_, mem_we_;
tri1 mem_re_, mem_we_;
wire[7:0] abus;
wire[7:0] dbus;
memory memory(
.clk(clk), .rst_(rst_),
.re_(mem_re_), .we_(mem_we_),
.abus(abus),
.dbus(dbus)
);
wire[7:0] r_din[5:0], r_dout[5:0];
tri1 r_we_[5:0];
generate
genvar i;
for(i = 0; i < 6; i = i+1) begin : r
register r(
.rst_(rst_),
.din(r_din[i]), .dout(r_dout[i]),
.we_(r_we_[i])
);
end
endgenerate
wire[7:0] fl_din, fl_dout;
tri1 fl_we_;
register fl(
.rst_(rst_),
.din(fl_din), .dout(fl_dout),
.we_(fl_we_)
);
wire[7:0] pc_din, pc_dout;
tri1 pc_we_;
register pc(
.rst_(rst_),
.din(pc_din), .dout(pc_dout),
.we_(pc_we_)
);
tri1 step_if_ena_;
bootstrap bootstrap(
.clk(clk), .rst_(rst_),
.rdy_(step_if_ena_)
);
wire step_id_ena_;
wire[7:0] step_id_inst;
step_if step_if(
.clk(clk), .rst_(rst_),
.ena_(step_if_ena_), .rdy_(step_id_ena_),
.mem_re_(mem_re_), .abus(abus), .dbus(dbus),
.pc_din(pc_din), .pc_dout(pc_dout), .pc_we_(pc_we_),
.inst(step_id_inst)
);
wire step_ex_nop_, step_ex_cpf_, step_ex_cpt_, step_ex_ld_, step_ex_st_;
wire step_ex_clr_, step_ex_im_, step_ex_tce_, step_ex_ts_, step_ex_add_;
wire step_ex_sub_;
step_id step_id(
.inst(step_id_inst), .ena_(step_id_ena_),
.cond_dout(fl_dout[0]),
.rdy_nop_(step_ex_nop_),
.rdy_cpf_(step_ex_cpf_),
.rdy_cpt_(step_ex_cpt_),
.rdy_ld_(step_ex_ld_),
.rdy_st_(step_ex_st_),
.rdy_clr_(step_ex_clr_),
.rdy_im_(step_ex_im_),
.rdy_tce_(step_ex_tce_),
.rdy_ts_(step_ex_ts_),
.rdy_add_(step_ex_add_),
.rdy_sub_(step_ex_sub_)
);
step_ex_nop step_ex_nop(
.clk(clk), .rst_(rst_),
.ena_(step_ex_nop_), .rdy_(step_if_ena_)
);
step_ex_cpf step_ex_cpf(
.clk(clk), .rst_(rst_),
.ena_(step_ex_cpf_), .rdy_(step_if_ena_),
.reg_id(step_id_inst[3:0]),
.r0_din(r_din[0]), .r0_we_(r_we_[0]),
.r0_dout(r_dout[0]), .r1_dout(r_dout[1]), .r2_dout(r_dout[2]), .r3_dout(r_dout[3]),
.r4_dout(r_dout[4]), .r5_dout(r_dout[5]), .fl_dout(fl_dout), .pc_dout(pc_dout)
);
step_ex_cpt step_ex_cpt(
.clk(clk), .rst_(rst_),
.ena_(step_ex_cpt_), .rdy_(step_if_ena_),
.reg_id(step_id_inst[3:0]),
.r0_dout(r_dout[0]),
.r0_din(r_din[0]), .r1_din(r_din[1]), .r2_din(r_din[2]), .r3_din(r_din[3]),
.r4_din(r_din[4]), .r5_din(r_din[5]), .fl_din(fl_din), .pc_din(pc_din),
.r0_we_(r_we_[0]), .r1_we_(r_we_[1]), .r2_we_(r_we_[2]), .r3_we_(r_we_[3]),
.r4_we_(r_we_[4]), .r5_we_(r_we_[5]), .fl_we_(fl_we_), .pc_we_(pc_we_)
);
step_ex_ld step_ex_ld(
.clk(clk), .rst_(rst_),
.ena_(step_ex_ld_), .rdy_(step_if_ena_),
.mem_re_(mem_re_), .abus(abus), .dbus(dbus),
.r1_dout(r_dout[1]), .r0_din(r_din[0]), .r0_we_(r_we_[0])
);
step_ex_st step_ex_st(
.clk(clk), .rst_(rst_),
.ena_(step_ex_st_), .rdy_(step_if_ena_),
.mem_we_(mem_we_), .abus(abus), .dbus(dbus),
.r0_dout(r_dout[0]), .r1_dout(r_dout[1])
);
step_ex_clr step_ex_clr(
.clk(clk), .rst_(rst_),
.ena_(step_ex_clr_), .rdy_(step_if_ena_),
.r0_din(r_din[0]), .r0_we_(r_we_[0])
);
step_ex_im step_ex_im(
.clk(clk), .rst_(rst_),
.ena_(step_ex_im_), .rdy_(step_if_ena_),
.r0_din(r_din[0]), .r0_dout(r_dout[0]), .r0_we_(r_we_[0]),
.immed(step_id_inst[3:0]), .high(step_id_inst[4])
);
step_ex_tce step_ex_tce(
.clk(clk), .rst_(rst_),
.ena_(step_ex_tce_), .rdy_(step_if_ena_),
.fl_din(fl_din), .fl_dout(fl_dout), .fl_we_(fl_we_)
);
step_ex_ts step_ex_ts(
.clk(clk), .rst_(rst_),
.ena_(step_ex_ts_), .rdy_(step_if_ena_),
.mode(step_id_inst[5:4]), .r0_dout(r_dout[0]),
.fl_din(fl_din), .fl_dout(fl_dout), .fl_we_(fl_we_)
);
step_ex_add step_ex_add(
.clk(clk), .rst_(rst_),
.ena_(step_ex_add_), .rdy_(step_if_ena_),
.r0_dout(r_dout[0]), .r1_dout(r_dout[1]),
.r0_din(r_din[0]), .r0_we_(r_we_[0])
);
step_ex_sub step_ex_sub(
.clk(clk), .rst_(rst_),
.ena_(step_ex_sub_), .rdy_(step_if_ena_),
.r0_dout(r_dout[0]), .r1_dout(r_dout[1]),
.r0_din(r_din[0]), .r0_we_(r_we_[0])
);
endmodule
|
/*
A simplistic test for OBUFDS. Two of them are instanciated and their outpus
are connected to LEDs. Data inputs are controlled by switches.
Truth tables:
SW8 | LED3 LED2
0 | 1 0
1 | 0 1
SW10 | LED8 LED7
0 | 0 1
0 | 1 0
Couldn't use all switches and buttons at the same time as the differential
IOs use different IOSTANDARD than the single ended ones and have to be in
a separate bank.
*/
`default_nettype none
// ============================================================================
module top
(
input wire [11:8] sw,
output wire [1:0] diff_p,
output wire [1:0] diff_n
);
// ============================================================================
// OBUFTDS
wire [1:0] buf_i;
OBUFDS # (
.IOSTANDARD("DIFF_SSTL135"),
.SLEW("FAST")
) obuftds_0 (
.I(buf_i[0]),
.O(diff_p[0]), // LED2
.OB(diff_n[0]) // LED3
);
OBUFDS # (
.IOSTANDARD("DIFF_SSTL135"),
.SLEW("FAST")
) obuftds_1 (
.I(buf_i[1]),
.O(diff_p[1]), // LED8
.OB(diff_n[1]) // LED7
);
// ============================================================================
assign buf_i[0] = sw[ 8];
assign buf_i[1] = sw[10];
endmodule
|
`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH UST
// Engineer: Wojciech Gredel, Hubert Górowski
//
// Create Date:
// Design Name:
// Module Name: Change2Negedge
// Project Name: DOS_Mario
// Target Devices: Basys3
// Tool versions: Vivado 2016.1
// Description:
// A module which is used to put input data out on negedge of clock
//
// Dependencies:
//
// Revision:
// Revision 0.01 - Module created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Change2Negedge
(
input wire hsync_in,
input wire vsync_in,
input wire blnk_in,
input wire [23:0] rgb_in,
input wire clk,
input wire rst,
output reg hsync_out,
output reg vsync_out,
output reg blnk_out,
output reg [23:0] rgb_out
);
always @(negedge clk or posedge rst) begin
if(rst) begin
hsync_out <= #1 0;
vsync_out <= #1 0;
blnk_out <= #1 0;
rgb_out <= #1 0;
end
else begin
hsync_out <= #1 hsync_in;
vsync_out <= #1 vsync_in;
blnk_out <= #1 blnk_in;
rgb_out <= #1 rgb_in;
end
end
endmodule
|
//==================================================================================================
// Filename : musb_cpzero.v
// Created On : 2015-02-23 20:51:58
// Last Modified : 2015-05-31 21:01:38
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : The Co-processor 0 (CP0).
// This module allows interrupts, traps, system calls and other exceptions.
// No Virtual Memory management
// Only a subset of CP0 (MIPS32 compliant).
//==================================================================================================
`include "musb_defines.v"
module musb_cpzero(
input clk,
// CP0
input mfc0, // mfc0 instruction
input mtc0, // mtc0 instruction
input eret, // eret instruction
input cp1_instruction, // Instruction for co-processor 1 (invalid for now)
input cp2_instruction, // Instruction for co-processor 2 (invalid for now)
input cp3_instruction, // Instruction for co-processor 3 (invalid for now)
input [4:0] register_address, // CP0 Register
input [2:0] select, // Select register
input [31:0] data_input, // Input data (write)
input if_stall, // Can not write to CP0 if IF/ID is stalled
input id_stall, // Can not write to CP0 if IF/ID is stalled
output reg [31:0] data_output, // Output data (read)
output kernel_mode, // Kernel mode: 0 Kernel, 1 User
// Hardware/External Interrupts
input [4:0] interrupts, // Up to 5 external interrupts
// exceptions
input rst, // External reset
input exc_nmi, // Non-maskable interrupt
input exc_address_if, // Address error: IF stage
input exc_address_l_mem, // Address error: MEM stage, load instruction
input exc_address_s_mem, // Address error: MEM stage, store instruction
input exc_ibus_error, // Instruction Bus Error
input exc_dbus_error, // Data Bus Error
input exc_overflow, // Integer overflow: EX stage
input exc_trap, // Trap exception
input exc_syscall, // System call
input exc_breakpoint, // Breakpoint
input exc_reserved, // Reserved Instruction
// exception data
input [31:0] id_exception_pc, // Exception PC @ ID stage
input [31:0] ex_exception_pc, // Exception PC @ EX stage
input [31:0] mem_exception_pc, // Exception PC @ MEM stage
input [31:0] bad_address_if, // Bad address that caused the exception
input [31:0] bad_address_mem, // Bad address that caused the exception
input id_exception_source, // Instruction @ ID stage is a potential source of exception
input ex_exception_source, // Instruction @ EX stage is a potential source of exception
input mem_exception_source, // Instruction @ MEM stage is a potential source of exception
input id_is_flushed, // BDS for ERET instruction
input if_is_bds, // Instruction at this stage is a Branch Delay Slot
input id_is_bds, // Instruction at this stage is a Branch Delay Slot
input ex_is_bds, // Instruction at this stage is a Branch Delay Slot
input mem_is_bds, // Instruction at this stage is a Branch Delay Slot
// pipeline control
output halt, // Halt the processor.
output if_exception_stall, // Stall pipeline: exception and wait for a clean pipeline
output id_exception_stall, // Stall pipeline: exception and wait for a clean pipeline
output ex_exception_stall, // Stall pipeline: exception and wait for a clean pipeline
output mem_exception_stall, // Stall pipeline: exception and wait for a clean pipeline
output if_exception_flush, // Flush the pipeline: exception.
output id_exception_flush, // Flush the pipeline: exception.
output ex_exception_flush, // Flush the pipeline: exception.
output mem_exception_flush, // Flush the pipeline: exception.
output exception_ready,
output exception_pc_select, // Select the PC from CP0
output reg [31:0] pc_exception // Address for the new PC (exception/return from exception)
);
//--------------------------------------------------------------------------
// Internal wires/registers
//--------------------------------------------------------------------------
wire exception_cp; // Unusable co-processor
wire interrupt_5; // Hardware interrupt #5: Count/Compare (timer)
wire interrupt_enabled; // Interrupt?
wire exception_interrupt; // The interrupt is OK to process.
wire cp0_enable_write; // Write to CP0 is OK (no hazards)
wire exception_no_interrupts; // All exceptions, but Interrupts, Reset, Soft-Reset, NMI
reg [4:0] cause_ExcCode_aux; // Hold the ExcCode (?)
wire if_exception; // exceptions by stage
wire id_exception; // exceptions by stage
wire ex_exception; // exceptions by stage
wire mem_exception; // exceptions by stage
wire if_exception_mask; // enable exception at this stage
wire id_exception_mask; // enable exception at this stage
wire ex_exception_mask; // enable exception at this stage
wire mem_exception_mask; // enable exception at this stage
wire if_exception_ready; // ready to process
wire id_exception_ready; // ready to process
wire ex_exception_ready; // ready to process
wire mem_exception_ready; // ready to process
//--------------------------------------------------------------------------
// CP0 Registers
// Defined in "MIPS32 Architecture for Programmers Volume III:
// The MIPS32 Privileged Resource Architecture" by Imagination Technologies, LTD.
// Only a subset.
//--------------------------------------------------------------------------
// Status Register:
wire [2:0] Status_CU_321 = 3'b000; // Access Control to CPs, [2]->Cp3, ... [0]->Cp1
reg Status_CU_0; // Access Control to CP0
wire Status_RP = 0;
wire Status_FR = 0;
wire Status_RE = 0; // Reverse Endian Memory for User Mode
wire Status_MX = 0;
wire Status_PX = 0;
reg Status_BEV; // Exception vector locations (0->Norm, 1->Bootstrap)
wire Status_TS = 0;
wire Status_SR = 0; // Soft reset (Not implemented)
reg Status_NMI; // Non-Maskable Interrupt
wire [1:0] Status_RES = 0; // Reserved.
reg Status_HALT; // Stop processor
reg [7:0] Status_IM; // Interrupt mask
wire Status_KX = 0; // 64-bits mode. (Not implemented)
wire Status_SX = 0; // 64-bits mode. (Not implemented)
wire Status_UX = 0; // 64-bits mode. (Not implemented)
reg [1:0] Status_KSU; // CPU privileged level: 0 -> kernel, 1 -> supervisor, 2 -> user
reg Status_ERL; // Error Level (0->Normal, 1->Error (reset, NMI))
reg Status_EXL; // Exception level (0->Normal, 1->Exception)
reg Status_IE; // Interrupt Enable
wire [31:0] Status; // Status Register (Register 12, Select 0)
// Cause Register:
reg Cause_BD; // Exception at BDS
reg [1:0] Cause_CE; // Co-processor error: Unusable co-processor
reg Cause_IV; // Special exception entry point
wire Cause_WP = 0; // Enable watchpoint exception mode.
reg [7:0] Cause_IP; // Pending hardware interrupts
reg [4:0] Cause_ExcCode; // Exception code.
wire [31:0] Cause; // Cause Register (Register 13, Select 0)
// Processor Identification:
wire [7:0] ID_Options = 8'b0000_0000; // Company Options -> to define
wire [7:0] ID_CID = 8'b0000_0000; // Company ID -> to zero
wire [7:0] ID_PID = 8'b0000_0000; // CPU ID
wire [7:0] ID_Rev = 8'b0000_0001; // Revision
wire [31:0] PRId; // Processor ID (Register 15, Select 0)
// Configuration Register:
wire Config_M = 1; // Continuation bit. 1-> if another config register is available
wire [14:0] Config_Impl = 15'b000_0000_0000_0000; // Implementation-dependent configuration flags.
wire Config_BE = `MUSB_LITTLE_ENDIAN; // Endiannes
wire [1:0] Config_AT = 2'b00; // MIPS32
wire [2:0] Config_AR = 3'b000; // MIPS32 Release 1
wire [2:0] Config_MT = 3'b000; // MMU -> none
wire Config_VI = 1'b0; // L1 I-cache do not use virtual address
wire [2:0] Config_K0 = 3'b000; // Fixed kseg0 region is cached or uncached? behavior?
wire [31:0] Config; // Config Register (Register 16, Select 0)
// Configuration Register 1:
wire Config1_M = 0; // Continuation bit
wire [5:0] Config1_MMU = 6'b000000; // MMU size
wire [2:0] Config1_IS = 3'b000; // Number of index positions: 64 x 2^S
wire [2:0] Config1_IL = 3'b000; // 0 -> no cache. Else: 2^(L + 1)
wire [2:0] Config1_IA = 3'b000; // Associativity -> (A + 1)
wire [2:0] Config1_DS = 3'b000; // Number of index positions: 64 x 2^S
wire [2:0] Config1_DL = 3'b000; // 0 -> no cache. Else: 2^(L + 1)
wire [2:0] Config1_DA = 3'b000; // Associativity -> (A + 1)
wire Config1_C2 = 0; // Co-processor 2?
wire Config1_MD = 0; // MDMX ASE?
wire Config1_PC = 0; // Performance Counters ?
wire Config1_WR = 0; // Watch Registers ?
wire Config1_CA = 0; // MIPS16?
wire Config1_EP = 0; // EJTAG?
wire Config1_FP = 0; // Floating-point?
wire [31:0] Config1; // Config Register (Register 16, Select 1)
reg [31:0] BadVAddr; // BadVAddr Register (Register 8, Select 0)
reg [31:0] Count; // Count Register (Register 9, Select 0)
reg [31:0] Compare; // Compare Register (Register 11, Select 0)
reg [31:0] EPC; // Exception Program Counter (Register 14, Select 0)
reg [31:0] ErrorEPC; // Error Register (Register 30, Select 0)
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign Status = {Status_CU_321, Status_CU_0, Status_RP, Status_FR, Status_RE, Status_MX, // bits 31-24
Status_PX, Status_BEV, Status_TS, Status_SR, Status_NMI, Status_RES, Status_HALT, // bits 23-16
Status_IM, // bits 15-8
Status_KX, Status_SX, Status_UX, Status_KSU, Status_ERL, Status_EXL, Status_IE}; // bits 7-0
assign Cause = {Cause_BD, 1'b0, Cause_CE, 4'b0000, // bits 31-24
Cause_IV, Cause_WP, 6'b000000, // bits 23-16
Cause_IP, // bits 15-8
1'b0, Cause_ExcCode, 2'b0}; // bits 7-0
assign PRId = {ID_Options, // bits 31-24
ID_CID, // bits 23-16
ID_PID, // bits 15-8
ID_Rev}; // bits 7-0
assign Config = {Config_M, Config_Impl, // bits 31-16
Config_BE, Config_AT, Config_AR, Config_MT, // bits 15-7
3'b000, Config_VI, Config_K0}; // bits 6-0
assign Config1 = {Config1_M, Config1_MMU,
Config1_IS, Config1_IL, Config1_IA,
Config1_DS, Config1_DL, Config1_DA,
Config1_C2, Config1_MD, Config1_PC, Config1_WR, Config1_CA, Config1_EP, Config1_FP};
assign exception_cp = cp1_instruction | cp2_instruction | cp3_instruction | // Check if the co-processor instruction is valid.
( (mtc0 | mfc0 | eret) & ~(Status_CU_0 | kernel_mode) ); // For CP0 : only if it has been enabled, or in kernel mode.
// For CP3-1 : Always trap.
assign exception_no_interrupts = exc_address_if | exc_ibus_error | exc_syscall | exc_breakpoint | exc_reserved | // All exceptions, but interrupts, reset, soft-reset and nmi
exception_cp | exc_overflow | exc_address_l_mem | exc_address_s_mem | //
exc_dbus_error | exc_trap; //
assign kernel_mode = (Status_KSU != 2'b10) | Status_EXL | Status_ERL; // Kernel mode if mode != user, Exception level or Error level. To inhibit new exceptions/interrupts
assign interrupt_5 = (Count == Compare); // Counter interrupt (#5)
assign interrupt_enabled = exc_nmi | ( Status_IE & ( (Cause_IP[7:0] & Status_IM[7:0]) != 8'b0 ) ); // Interrupt if NMI, Interrupts are enabled (global) and the individual interrupt is enable.
assign exception_interrupt = interrupt_enabled & ~Status_EXL & ~Status_ERL & ~id_is_flushed; // Interrupt is OK to process if: no exception level and no error level.
assign cp0_enable_write = mtc0 & ~id_stall & (Status_CU_0 | kernel_mode) &
(~mem_exception & ~ex_exception & ~id_exception & ~if_exception); // Write to CP0 if ID is not stalled, CP0 is enabled or in kernel mode, and no exceptions
assign halt = Status_HALT;
//--------------------------------------------------------------------------
// Hazards
// Rules:
// - In case of exception, the stage could be stalled if:
// - A forward stage is capable of causing an exception, AND
// - A forward stage is not causing and exception.
// - An exception is ready to process if not stalled.
//
// In case of exception: clear commits, convert to NOP (a.k.a. flush the stage).
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Exceptions by stage
//--------------------------------------------------------------------------
assign mem_exception = exc_address_l_mem | exc_address_s_mem | exc_dbus_error | exc_trap; // Error on load, store, data read, or trap
assign ex_exception = exc_overflow; // overflow
assign id_exception = exc_syscall | exc_breakpoint | exc_reserved | exception_cp | exception_interrupt; // Syscall, breakpoint, reserved instruction, Co-processor or interrupt
assign if_exception = exc_address_if | exc_ibus_error; // Error on load or bus
//--------------------------------------------------------------------------
// Mask exception: assert in case of possible exceptions in forward stages,
// or if being stalled.
// Can not process the exception if IF is stalled (unable to commit the new PC)
//
// NOTE: Abort IF operation in case of exception
//--------------------------------------------------------------------------
assign mem_exception_mask = 0;
assign ex_exception_mask = mem_exception_source;
assign id_exception_mask = mem_exception_source | ex_exception_source;
assign if_exception_mask = mem_exception_source | ex_exception_source | id_exception_source | exception_interrupt; // In case of interrupt, abort this
//--------------------------------------------------------------------------
// Generate the stall signals
// No writes to CP0 until a clean state (no stalls).
//--------------------------------------------------------------------------
assign mem_exception_stall = mem_exception & mem_exception_mask; //
assign ex_exception_stall = ex_exception & ex_exception_mask & ~mem_exception; //
assign id_exception_stall = (id_exception | eret | mtc0) & id_exception_mask & ~(mem_exception | ex_exception); //
assign if_exception_stall = if_exception & if_exception_mask & ~(mem_exception | ex_exception | id_exception); //
//--------------------------------------------------------------------------
// Signal the valid exception to process
//--------------------------------------------------------------------------
assign mem_exception_ready = mem_exception & ~mem_exception_mask; //
assign ex_exception_ready = ex_exception & ~ex_exception_mask; //
assign id_exception_ready = id_exception & ~id_exception_mask; //
assign if_exception_ready = if_exception & ~if_exception_mask; //
//--------------------------------------------------------------------------
// Flush the stages in case of exception
//--------------------------------------------------------------------------
assign mem_exception_flush = mem_exception;
assign ex_exception_flush = mem_exception | ex_exception;
assign id_exception_flush = mem_exception | ex_exception | id_exception;
assign if_exception_flush = mem_exception | ex_exception | id_exception | if_exception | (eret & ~id_stall); // ERET doest not execute the next instruction!!
//--------------------------------------------------------------------------
// Read CP0 registers
//--------------------------------------------------------------------------
always @(*) begin
if(mfc0 & (Status_CU_0 | kernel_mode)) begin
case (register_address)
5'd8 : data_output <= BadVAddr;
5'd9 : data_output <= Count;
5'd11 : data_output <= Compare;
5'd12 : data_output <= Status;
5'd13 : data_output <= Cause;
5'd14 : data_output <= EPC;
5'd15 : data_output <= PRId;
5'd16 : data_output <= (select == 3'b000) ? Config : Config1;
5'd30 : data_output <= ErrorEPC;
default: data_output <= 32'h0000_0000;
endcase
end
else begin
data_output <= 32'h0000_0000;
end
end
//--------------------------------------------------------------------------
// Write CP0 registers.
// Reset, soft-reset, NMI.
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
Status_BEV <= 1'b1;
Status_NMI <= 1'b0;
Status_ERL <= 1'b1;
ErrorEPC <= 32'b0;
end
else if (id_exception_ready & exc_nmi) begin
Status_BEV <= 1'b1;
Status_NMI <= 1'b1;
Status_ERL <= 1'b1;
ErrorEPC <= id_exception_pc;
end
else begin
Status_BEV <= (cp0_enable_write & (register_address == 5'd12) & (select == 3'b000)) ? data_input[22] : Status_BEV;
Status_NMI <= (cp0_enable_write & (register_address == 5'd12) & (select == 3'b000)) ? data_input[19] : Status_NMI;
Status_ERL <= (cp0_enable_write & (register_address == 5'd12) & (select == 3'b000)) ? data_input[2] : ((Status_ERL & eret & ~id_stall) ? 1'b0 : Status_ERL);
ErrorEPC <= (cp0_enable_write & (register_address == 5'd30) & (select == 3'b000)) ? data_input : ErrorEPC;
end
end
//--------------------------------------------------------------------------
// Write CP0 registers.
// Other registers
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
Count <= 32'b0;
Compare <= 32'b0;
Status_HALT <= 1'b0;
Status_CU_0 <= 1'b0;
//Status_RE <= 1'b0;
Status_IM <= 8'b0;
Status_KSU <= 2'b0;
Status_IE <= 1'b0;
Cause_IV <= 1'b0;
Cause_IP <= 8'b0;
end
else begin
Count <= (cp0_enable_write & (register_address == 5'd9 ) & (select == 3'b000)) ? data_input : ((Count == Compare) ? 32'b0 : Count + 1'b1); // check the 1'b1. Count range: Compare + 1
Compare <= (cp0_enable_write & (register_address == 5'd11) & (select == 3'b000)) ? data_input : Compare;
Status_HALT <= (cp0_enable_write & (register_address == 5'd12) & (select == 3'b000)) ? data_input[16] : Status_HALT;
Status_CU_0 <= (cp0_enable_write & (register_address == 5'd12) & (select == 3'b000)) ? data_input[28] : Status_CU_0;
//Status_RE <= (cp0_enable_write & (register_address == 5'd12) & (select == 3'b000)) ? data_input[25] : Status_RE;
Status_IM <= (cp0_enable_write & (register_address == 5'd12) & (select == 3'b000)) ? data_input[15:8] : Status_IM;
Status_KSU <= (cp0_enable_write & (register_address == 5'd12) & (select == 3'b000)) ? data_input[4:3] : Status_KSU;
Status_IE <= (cp0_enable_write & (register_address == 5'd12) & (select == 3'b000)) ? data_input[0] : Status_IE;
Cause_IV <= (cp0_enable_write & (register_address == 5'd13) & (select == 3'b000)) ? data_input[23] : Cause_IV;
/* Cause_IP indicates 8 interrupts:
[7] is set by the timer comparison, and cleared by reading 'Count' (hardware interrupt #5).
[6:2] are set and cleared by external hardware.
[1:0] are set and cleared by software.
*/
Cause_IP[7] <= ((Status_CU_0 | kernel_mode) & mfc0 & (register_address == 5'd9) & (select == 3'b000)) ? 1'b0 : ((Cause_IP[7] == 0) ? interrupt_5 : Cause_IP[7]); // If reading -> 0, Otherwise if 0 -> interrupt_5.
Cause_IP[6:2] <= interrupts[4:0];
Cause_IP[1:0] <= (cp0_enable_write & (register_address == 5'd13) & (select == 3'b000)) ? data_input[9:8] : Cause_IP[1:0];
end
end
//--------------------------------------------------------------------------
// Write CP0 registers.
// Exception and Interrupt Processing
// Ignore if EXL or ERL is asserted
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
Cause_BD <= 1'b0;
Cause_CE <= 2'b00;
Cause_ExcCode <= 4'b0000;
Status_EXL <= 1'b0;
EPC <= 32'h0;
BadVAddr <= 32'h0;
end
else begin
// MEM stage
if (mem_exception_ready) begin
Cause_BD <= (Status_EXL) ? Cause_BD : mem_is_bds;
Cause_CE <= (cp3_instruction) ? 2'b11 : ((cp2_instruction) ? 2'b10 : ((cp1_instruction) ? 2'b01 : 2'b00));
Cause_ExcCode <= cause_ExcCode_aux;
Status_EXL <= 1'b1;
EPC <= (Status_EXL) ? EPC : mem_exception_pc;
BadVAddr <= bad_address_mem;
end
// EX stage
else if (ex_exception_ready) begin
Cause_BD <= (Status_EXL) ? Cause_BD : ex_is_bds;
Cause_CE <= (cp3_instruction) ? 2'b11 : ((cp2_instruction) ? 2'b10 : ((cp1_instruction) ? 2'b01 : 2'b00));
Cause_ExcCode <= cause_ExcCode_aux;
Status_EXL <= 1'b1;
EPC <= (Status_EXL) ? EPC : ex_exception_pc;
BadVAddr <= BadVAddr;
end
// ID stage
else if (id_exception_ready) begin
Cause_BD <= (Status_EXL) ? Cause_BD : id_is_bds;
Cause_CE <= (cp3_instruction) ? 2'b11 : ((cp2_instruction) ? 2'b10 : ((cp1_instruction) ? 2'b01 : 2'b00));
Cause_ExcCode <= cause_ExcCode_aux;
Status_EXL <= 1'b1;
EPC <= (Status_EXL) ? EPC : id_exception_pc;
BadVAddr <= BadVAddr;
end
// IF stage
else if (if_exception_ready) begin
Cause_BD <= (Status_EXL) ? Cause_BD : if_is_bds;
Cause_CE <= (cp3_instruction) ? 2'b11 : ((cp2_instruction) ? 2'b10 : ((cp1_instruction) ? 2'b01 : 2'b00));
Cause_ExcCode <= cause_ExcCode_aux;
Status_EXL <= 1'b1;
EPC <= (Status_EXL) ? EPC : bad_address_if;
BadVAddr <= bad_address_if;
end
// No exceptions this cycle
else begin
Cause_BD <= 1'b0;
Cause_CE <= Cause_CE;
Cause_ExcCode <= Cause_ExcCode;
// Without new exceptions, 'Status_EXL' is set by software or cleared by ERET.
Status_EXL <= (cp0_enable_write & (register_address == 5'd12) & (select == 3'b000)) ? data_input[1] : ((Status_EXL & eret & ~id_stall) ? 1'b0 : Status_EXL);
// The EPC is also writable by software
EPC <= (cp0_enable_write & (register_address == 5'd14) & (select == 3'b000)) ? data_input : EPC;
BadVAddr <= BadVAddr;
end
end
end
//--------------------------------------------------------------------------
// Set the program counter
// The PC register handles the reset scenario.
//--------------------------------------------------------------------------
always @(*) begin
if (rst) begin
pc_exception <= `MUSB_VECTOR_BASE_RESET;
end
if (eret & ~id_stall) begin
pc_exception <= (Status_ERL) ? ErrorEPC : EPC;
end
else if (exception_no_interrupts) begin
pc_exception <= (Status_BEV) ? (`MUSB_VECTOR_BASE_BOOT + `MUSB_VECTOR_OFFSET_GENERAL) : (`MUSB_VECTOR_BASE_NO_BOOT + `MUSB_VECTOR_OFFSET_GENERAL);
end
else if (exc_nmi) begin
pc_exception <= `MUSB_VECTOR_BASE_RESET;
end
else if (exception_interrupt & Cause_IV) begin
pc_exception <= (Status_BEV) ? (`MUSB_VECTOR_BASE_BOOT + `MUSB_VECTOR_OFFSET_SPECIAL) : (`MUSB_VECTOR_BASE_NO_BOOT + `MUSB_VECTOR_OFFSET_SPECIAL);
end
else begin
pc_exception <= (Status_BEV) ? (`MUSB_VECTOR_BASE_BOOT + `MUSB_VECTOR_OFFSET_GENERAL) : (`MUSB_VECTOR_BASE_NO_BOOT + `MUSB_VECTOR_OFFSET_GENERAL);
end
end
assign exception_ready = if_exception_ready | id_exception_ready | ex_exception_ready | mem_exception_ready;
assign exception_pc_select = rst | (eret & ~id_stall) | exception_ready;
//--------------------------------------------------------------------------
// Set the Cause register
// Ordered by Pipeline Stage with Interrupts last
//--------------------------------------------------------------------------
always @(*) begin
if (exc_address_l_mem) cause_ExcCode_aux <= 4'h4; // 00100 (EXC_AdEL)
else if (exc_address_s_mem) cause_ExcCode_aux <= 4'h5; // 00101 (EXC_AdES)
else if (exc_dbus_error) cause_ExcCode_aux <= 4'h7; // 00111 (EXC_DBE)
else if (exc_trap) cause_ExcCode_aux <= 4'hd; // 01101 (EXC_Tr)
else if (exc_overflow) cause_ExcCode_aux <= 4'hc; // 01100 (EXC_Ov)
else if (exc_syscall) cause_ExcCode_aux <= 4'h8; // 01000 (EXC_Sys)
else if (exc_breakpoint) cause_ExcCode_aux <= 4'h9; // 01001 (EXC_Bp)
else if (exc_reserved) cause_ExcCode_aux <= 4'ha; // 01010 (EXC_RI)
else if (exception_cp) cause_ExcCode_aux <= 4'hb; // 01011 (EXC_CpU)
else if (exc_address_if) cause_ExcCode_aux <= 4'h4; // 00100 (EXC_AdIF)
else if (exc_ibus_error) cause_ExcCode_aux <= 4'h6; // 00110 (EXC_IBE)
else if (exception_interrupt) cause_ExcCode_aux <= 4'h0; // 00000 (EXC_Int)
else cause_ExcCode_aux <= 4'bxxxx; // What the hell?
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Sat Sep 23 13:25:27 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_bram_ctrl,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [15:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input s_axi_awlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [15:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input s_axi_arlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *) output bram_rst_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) output bram_clk_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) output bram_en_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) output [3:0]bram_we_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) output [15:0]bram_addr_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) output [31:0]bram_wrdata_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) input [31:0]bram_rddata_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *) output bram_rst_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) output bram_clk_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) output bram_en_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) output [3:0]bram_we_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) output [15:0]bram_addr_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) output [31:0]bram_wrdata_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) input [31:0]bram_rddata_b;
wire [15:0]bram_addr_a;
wire [15:0]bram_addr_b;
wire bram_clk_a;
wire bram_clk_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_a;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire bram_rst_b;
wire [3:0]bram_we_a;
wire [3:0]bram_we_b;
wire [31:0]bram_wrdata_a;
wire [31:0]bram_wrdata_b;
wire s_axi_aclk;
wire [15:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire s_axi_aresetn;
wire [7:0]s_axi_arlen;
wire s_axi_arlock;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [15:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [7:0]s_axi_awlen;
wire s_axi_awlock;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ecc_interrupt_UNCONNECTED;
wire NLW_U0_ecc_ue_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_arready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_awready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_wready_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_bresp_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_ctrl_rdata_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
(* C_BRAM_ADDR_WIDTH = "14" *)
(* C_BRAM_INST_MODE = "EXTERNAL" *)
(* C_ECC = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "0" *)
(* C_ECC_TYPE = "0" *)
(* C_FAMILY = "zynq" *)
(* C_FAULT_INJECT = "0" *)
(* C_MEMORY_DEPTH = "16384" *)
(* C_SELECT_XPM = "0" *)
(* C_SINGLE_PORT_BRAM = "0" *)
(* C_S_AXI_ADDR_WIDTH = "16" *)
(* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_S_AXI_ID_WIDTH = "1" *)
(* C_S_AXI_PROTOCOL = "AXI4" *)
(* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl U0
(.bram_addr_a(bram_addr_a),
.bram_addr_b(bram_addr_b),
.bram_clk_a(bram_clk_a),
.bram_clk_b(bram_clk_b),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_a(bram_rddata_a),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_rst_b(bram_rst_b),
.bram_we_a(bram_we_a),
.bram_we_b(bram_we_b),
.bram_wrdata_a(bram_wrdata_a),
.bram_wrdata_b(bram_wrdata_b),
.ecc_interrupt(NLW_U0_ecc_interrupt_UNCONNECTED),
.ecc_ue(NLW_U0_ecc_ue_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(1'b0),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(1'b0),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_ctrl_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_arready(NLW_U0_s_axi_ctrl_arready_UNCONNECTED),
.s_axi_ctrl_arvalid(1'b0),
.s_axi_ctrl_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_awready(NLW_U0_s_axi_ctrl_awready_UNCONNECTED),
.s_axi_ctrl_awvalid(1'b0),
.s_axi_ctrl_bready(1'b0),
.s_axi_ctrl_bresp(NLW_U0_s_axi_ctrl_bresp_UNCONNECTED[1:0]),
.s_axi_ctrl_bvalid(NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED),
.s_axi_ctrl_rdata(NLW_U0_s_axi_ctrl_rdata_UNCONNECTED[31:0]),
.s_axi_ctrl_rready(1'b0),
.s_axi_ctrl_rresp(NLW_U0_s_axi_ctrl_rresp_UNCONNECTED[1:0]),
.s_axi_ctrl_rvalid(NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED),
.s_axi_ctrl_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_wready(NLW_U0_s_axi_ctrl_wready_UNCONNECTED),
.s_axi_ctrl_wvalid(1'b0),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "SRL_FIFO" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO
(bvalid_cnt_inc,
bid_gets_fifo_load_d1_reg,
bid_gets_fifo_load,
axi_wdata_full_cmb114_out,
\axi_bid_int_reg[0] ,
s_axi_aresetn,
s_axi_aclk,
\bvalid_cnt_reg[2] ,
wr_addr_sm_cs,
\bvalid_cnt_reg[2]_0 ,
\GEN_AWREADY.axi_aresetn_d2_reg ,
axi_awaddr_full,
bram_addr_ld_en,
bid_gets_fifo_load_d1,
s_axi_bready,
axi_bvalid_int_reg,
bvalid_cnt,
\bvalid_cnt_reg[1] ,
aw_active,
s_axi_awready,
s_axi_awvalid,
curr_awlen_reg_1_or_2,
axi_awlen_pipe_1_or_2,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ,
last_data_ack_mod,
axi_awid_pipe,
s_axi_awid,
s_axi_bid,
out,
axi_wr_burst,
s_axi_wvalid,
s_axi_wlast);
output bvalid_cnt_inc;
output bid_gets_fifo_load_d1_reg;
output bid_gets_fifo_load;
output axi_wdata_full_cmb114_out;
output \axi_bid_int_reg[0] ;
input s_axi_aresetn;
input s_axi_aclk;
input \bvalid_cnt_reg[2] ;
input wr_addr_sm_cs;
input \bvalid_cnt_reg[2]_0 ;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input axi_awaddr_full;
input bram_addr_ld_en;
input bid_gets_fifo_load_d1;
input s_axi_bready;
input axi_bvalid_int_reg;
input [2:0]bvalid_cnt;
input \bvalid_cnt_reg[1] ;
input aw_active;
input s_axi_awready;
input s_axi_awvalid;
input curr_awlen_reg_1_or_2;
input axi_awlen_pipe_1_or_2;
input \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
input last_data_ack_mod;
input axi_awid_pipe;
input [0:0]s_axi_awid;
input [0:0]s_axi_bid;
input [2:0]out;
input axi_wr_burst;
input s_axi_wvalid;
input s_axi_wlast;
wire \Addr_Counters[0].FDRE_I_n_0 ;
wire \Addr_Counters[1].FDRE_I_n_0 ;
wire \Addr_Counters[2].FDRE_I_n_0 ;
wire \Addr_Counters[3].FDRE_I_n_0 ;
wire \Addr_Counters[3].XORCY_I_i_1_n_0 ;
wire CI;
wire D;
wire Data_Exists_DFF_i_2_n_0;
wire Data_Exists_DFF_i_3_n_0;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
wire S;
wire S0_out;
wire S1_out;
wire addr_cy_1;
wire addr_cy_2;
wire addr_cy_3;
wire aw_active;
wire axi_awaddr_full;
wire axi_awid_pipe;
wire axi_awlen_pipe_1_or_2;
wire \axi_bid_int[0]_i_2_n_0 ;
wire \axi_bid_int_reg[0] ;
wire axi_bvalid_int_i_4_n_0;
wire axi_bvalid_int_i_5_n_0;
wire axi_bvalid_int_i_6_n_0;
wire axi_bvalid_int_reg;
wire axi_wdata_full_cmb114_out;
wire axi_wr_burst;
wire bid_fifo_ld;
wire bid_fifo_not_empty;
wire bid_fifo_rd;
wire bid_gets_fifo_load;
wire bid_gets_fifo_load_d1;
wire bid_gets_fifo_load_d1_i_3_n_0;
wire bid_gets_fifo_load_d1_reg;
wire bram_addr_ld_en;
wire [2:0]bvalid_cnt;
wire bvalid_cnt_inc;
wire \bvalid_cnt_reg[1] ;
wire \bvalid_cnt_reg[2] ;
wire \bvalid_cnt_reg[2]_0 ;
wire curr_awlen_reg_1_or_2;
wire last_data_ack_mod;
wire [2:0]out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [0:0]s_axi_awid;
wire s_axi_awready;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_wlast;
wire s_axi_wvalid;
wire sum_A_0;
wire sum_A_1;
wire sum_A_2;
wire sum_A_3;
wire wr_addr_sm_cs;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[0].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_3),
.Q(\Addr_Counters[0].FDRE_I_n_0 ),
.R(s_axi_aresetn));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \Addr_Counters[0].MUXCY_L_I_CARRY4
(.CI(1'b0),
.CO({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED [3],addr_cy_1,addr_cy_2,addr_cy_3}),
.CYINIT(CI),
.DI({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED [3],\Addr_Counters[2].FDRE_I_n_0 ,\Addr_Counters[1].FDRE_I_n_0 ,\Addr_Counters[0].FDRE_I_n_0 }),
.O({sum_A_0,sum_A_1,sum_A_2,sum_A_3}),
.S({\Addr_Counters[3].XORCY_I_i_1_n_0 ,S0_out,S1_out,S}));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[0].MUXCY_L_I_i_1
(.I0(\Addr_Counters[1].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[0]_i_2_n_0 ),
.I5(\Addr_Counters[0].FDRE_I_n_0 ),
.O(S));
LUT6 #(
.INIT(64'h8AAAAAAAAAAAAAAA))
\Addr_Counters[0].MUXCY_L_I_i_2
(.I0(bram_addr_ld_en),
.I1(\axi_bid_int[0]_i_2_n_0 ),
.I2(\Addr_Counters[0].FDRE_I_n_0 ),
.I3(\Addr_Counters[1].FDRE_I_n_0 ),
.I4(\Addr_Counters[3].FDRE_I_n_0 ),
.I5(\Addr_Counters[2].FDRE_I_n_0 ),
.O(CI));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[1].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_2),
.Q(\Addr_Counters[1].FDRE_I_n_0 ),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[1].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[0]_i_2_n_0 ),
.I5(\Addr_Counters[1].FDRE_I_n_0 ),
.O(S1_out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[2].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_1),
.Q(\Addr_Counters[2].FDRE_I_n_0 ),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[2].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[0]_i_2_n_0 ),
.I5(\Addr_Counters[2].FDRE_I_n_0 ),
.O(S0_out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[3].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_0),
.Q(\Addr_Counters[3].FDRE_I_n_0 ),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[3].XORCY_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[0]_i_2_n_0 ),
.I5(\Addr_Counters[3].FDRE_I_n_0 ),
.O(\Addr_Counters[3].XORCY_I_i_1_n_0 ));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
Data_Exists_DFF
(.C(s_axi_aclk),
.CE(1'b1),
.D(D),
.Q(bid_fifo_not_empty),
.R(s_axi_aresetn));
LUT4 #(
.INIT(16'hFE0A))
Data_Exists_DFF_i_1
(.I0(bram_addr_ld_en),
.I1(Data_Exists_DFF_i_2_n_0),
.I2(Data_Exists_DFF_i_3_n_0),
.I3(bid_fifo_not_empty),
.O(D));
LUT6 #(
.INIT(64'h000000000000FFFD))
Data_Exists_DFF_i_2
(.I0(bvalid_cnt_inc),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.I3(bvalid_cnt[1]),
.I4(bid_gets_fifo_load_d1_reg),
.I5(bid_gets_fifo_load_d1),
.O(Data_Exists_DFF_i_2_n_0));
LUT4 #(
.INIT(16'hFFFE))
Data_Exists_DFF_i_3
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(\Addr_Counters[2].FDRE_I_n_0 ),
.O(Data_Exists_DFF_i_3_n_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[0].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld),
.Q(bid_fifo_rd));
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[0].SRL16E_I_i_1
(.I0(axi_awid_pipe),
.I1(axi_awaddr_full),
.I2(s_axi_awid),
.O(bid_fifo_ld));
LUT5 #(
.INIT(32'hACAFACA0))
\axi_bid_int[0]_i_1
(.I0(bid_fifo_ld),
.I1(bid_fifo_rd),
.I2(bid_gets_fifo_load),
.I3(\axi_bid_int[0]_i_2_n_0 ),
.I4(s_axi_bid),
.O(\axi_bid_int_reg[0] ));
LUT6 #(
.INIT(64'hA888AAAAA8888888))
\axi_bid_int[0]_i_2
(.I0(bid_fifo_not_empty),
.I1(bid_gets_fifo_load_d1),
.I2(s_axi_bready),
.I3(axi_bvalid_int_reg),
.I4(bid_gets_fifo_load_d1_i_3_n_0),
.I5(bvalid_cnt_inc),
.O(\axi_bid_int[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000055FD00000000))
axi_bvalid_int_i_2
(.I0(out[2]),
.I1(axi_wdata_full_cmb114_out),
.I2(axi_bvalid_int_i_4_n_0),
.I3(axi_wr_burst),
.I4(out[1]),
.I5(axi_bvalid_int_i_5_n_0),
.O(bvalid_cnt_inc));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hFE000000))
axi_bvalid_int_i_3
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.I3(axi_bvalid_int_reg),
.I4(s_axi_bready),
.O(bid_gets_fifo_load_d1_reg));
LUT6 #(
.INIT(64'h1F11000000000000))
axi_bvalid_int_i_4
(.I0(axi_bvalid_int_i_6_n_0),
.I1(\bvalid_cnt_reg[2] ),
.I2(wr_addr_sm_cs),
.I3(\bvalid_cnt_reg[2]_0 ),
.I4(\GEN_AWREADY.axi_aresetn_d2_reg ),
.I5(axi_awaddr_full),
.O(axi_bvalid_int_i_4_n_0));
LUT5 #(
.INIT(32'h74446444))
axi_bvalid_int_i_5
(.I0(out[0]),
.I1(out[2]),
.I2(s_axi_wvalid),
.I3(s_axi_wlast),
.I4(axi_wdata_full_cmb114_out),
.O(axi_bvalid_int_i_5_n_0));
LUT5 #(
.INIT(32'hFEFFFFFF))
axi_bvalid_int_i_6
(.I0(curr_awlen_reg_1_or_2),
.I1(axi_awlen_pipe_1_or_2),
.I2(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ),
.I3(axi_awaddr_full),
.I4(last_data_ack_mod),
.O(axi_bvalid_int_i_6_n_0));
LUT6 #(
.INIT(64'h7F7F7F007F007F00))
axi_wready_int_mod_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.I3(aw_active),
.I4(s_axi_awready),
.I5(s_axi_awvalid),
.O(axi_wdata_full_cmb114_out));
LUT6 #(
.INIT(64'h00000800AA00AA00))
bid_gets_fifo_load_d1_i_1
(.I0(bram_addr_ld_en),
.I1(bid_gets_fifo_load_d1_reg),
.I2(bid_fifo_not_empty),
.I3(bvalid_cnt_inc),
.I4(\bvalid_cnt_reg[1] ),
.I5(bid_gets_fifo_load_d1_i_3_n_0),
.O(bid_gets_fifo_load));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hFE))
bid_gets_fifo_load_d1_i_3
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.O(bid_gets_fifo_load_d1_i_3_n_0));
endmodule
(* C_BRAM_ADDR_WIDTH = "14" *) (* C_BRAM_INST_MODE = "EXTERNAL" *) (* C_ECC = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "0" *) (* C_ECC_TYPE = "0" *) (* C_FAMILY = "zynq" *)
(* C_FAULT_INJECT = "0" *) (* C_MEMORY_DEPTH = "16384" *) (* C_SELECT_XPM = "0" *)
(* C_SINGLE_PORT_BRAM = "0" *) (* C_S_AXI_ADDR_WIDTH = "16" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_S_AXI_DATA_WIDTH = "32" *) (* C_S_AXI_ID_WIDTH = "1" *)
(* C_S_AXI_PROTOCOL = "AXI4" *) (* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *) (* ORIG_REF_NAME = "axi_bram_ctrl" *)
(* downgradeipidentifiedwarnings = "yes" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl
(s_axi_aclk,
s_axi_aresetn,
ecc_interrupt,
ecc_ue,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_ctrl_awvalid,
s_axi_ctrl_awready,
s_axi_ctrl_awaddr,
s_axi_ctrl_wdata,
s_axi_ctrl_wvalid,
s_axi_ctrl_wready,
s_axi_ctrl_bresp,
s_axi_ctrl_bvalid,
s_axi_ctrl_bready,
s_axi_ctrl_araddr,
s_axi_ctrl_arvalid,
s_axi_ctrl_arready,
s_axi_ctrl_rdata,
s_axi_ctrl_rresp,
s_axi_ctrl_rvalid,
s_axi_ctrl_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
input s_axi_aclk;
input s_axi_aresetn;
output ecc_interrupt;
output ecc_ue;
input [0:0]s_axi_awid;
input [15:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [0:0]s_axi_arid;
input [15:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_ctrl_awvalid;
output s_axi_ctrl_awready;
input [31:0]s_axi_ctrl_awaddr;
input [31:0]s_axi_ctrl_wdata;
input s_axi_ctrl_wvalid;
output s_axi_ctrl_wready;
output [1:0]s_axi_ctrl_bresp;
output s_axi_ctrl_bvalid;
input s_axi_ctrl_bready;
input [31:0]s_axi_ctrl_araddr;
input s_axi_ctrl_arvalid;
output s_axi_ctrl_arready;
output [31:0]s_axi_ctrl_rdata;
output [1:0]s_axi_ctrl_rresp;
output s_axi_ctrl_rvalid;
input s_axi_ctrl_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [15:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
wire \<const0> ;
wire [15:2]\^bram_addr_a ;
wire [15:2]\^bram_addr_b ;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [15:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [15:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign bram_addr_a[15:2] = \^bram_addr_a [15:2];
assign bram_addr_a[1] = \<const0> ;
assign bram_addr_a[0] = \<const0> ;
assign bram_addr_b[15:2] = \^bram_addr_b [15:2];
assign bram_addr_b[1] = \<const0> ;
assign bram_addr_b[0] = \<const0> ;
assign bram_clk_a = s_axi_aclk;
assign bram_clk_b = s_axi_aclk;
assign bram_rst_b = bram_rst_a;
assign bram_we_b[3] = \<const0> ;
assign bram_we_b[2] = \<const0> ;
assign bram_we_b[1] = \<const0> ;
assign bram_we_b[0] = \<const0> ;
assign bram_wrdata_b[31] = \<const0> ;
assign bram_wrdata_b[30] = \<const0> ;
assign bram_wrdata_b[29] = \<const0> ;
assign bram_wrdata_b[28] = \<const0> ;
assign bram_wrdata_b[27] = \<const0> ;
assign bram_wrdata_b[26] = \<const0> ;
assign bram_wrdata_b[25] = \<const0> ;
assign bram_wrdata_b[24] = \<const0> ;
assign bram_wrdata_b[23] = \<const0> ;
assign bram_wrdata_b[22] = \<const0> ;
assign bram_wrdata_b[21] = \<const0> ;
assign bram_wrdata_b[20] = \<const0> ;
assign bram_wrdata_b[19] = \<const0> ;
assign bram_wrdata_b[18] = \<const0> ;
assign bram_wrdata_b[17] = \<const0> ;
assign bram_wrdata_b[16] = \<const0> ;
assign bram_wrdata_b[15] = \<const0> ;
assign bram_wrdata_b[14] = \<const0> ;
assign bram_wrdata_b[13] = \<const0> ;
assign bram_wrdata_b[12] = \<const0> ;
assign bram_wrdata_b[11] = \<const0> ;
assign bram_wrdata_b[10] = \<const0> ;
assign bram_wrdata_b[9] = \<const0> ;
assign bram_wrdata_b[8] = \<const0> ;
assign bram_wrdata_b[7] = \<const0> ;
assign bram_wrdata_b[6] = \<const0> ;
assign bram_wrdata_b[5] = \<const0> ;
assign bram_wrdata_b[4] = \<const0> ;
assign bram_wrdata_b[3] = \<const0> ;
assign bram_wrdata_b[2] = \<const0> ;
assign bram_wrdata_b[1] = \<const0> ;
assign bram_wrdata_b[0] = \<const0> ;
assign ecc_interrupt = \<const0> ;
assign ecc_ue = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_ctrl_arready = \<const0> ;
assign s_axi_ctrl_awready = \<const0> ;
assign s_axi_ctrl_bresp[1] = \<const0> ;
assign s_axi_ctrl_bresp[0] = \<const0> ;
assign s_axi_ctrl_bvalid = \<const0> ;
assign s_axi_ctrl_rdata[31] = \<const0> ;
assign s_axi_ctrl_rdata[30] = \<const0> ;
assign s_axi_ctrl_rdata[29] = \<const0> ;
assign s_axi_ctrl_rdata[28] = \<const0> ;
assign s_axi_ctrl_rdata[27] = \<const0> ;
assign s_axi_ctrl_rdata[26] = \<const0> ;
assign s_axi_ctrl_rdata[25] = \<const0> ;
assign s_axi_ctrl_rdata[24] = \<const0> ;
assign s_axi_ctrl_rdata[23] = \<const0> ;
assign s_axi_ctrl_rdata[22] = \<const0> ;
assign s_axi_ctrl_rdata[21] = \<const0> ;
assign s_axi_ctrl_rdata[20] = \<const0> ;
assign s_axi_ctrl_rdata[19] = \<const0> ;
assign s_axi_ctrl_rdata[18] = \<const0> ;
assign s_axi_ctrl_rdata[17] = \<const0> ;
assign s_axi_ctrl_rdata[16] = \<const0> ;
assign s_axi_ctrl_rdata[15] = \<const0> ;
assign s_axi_ctrl_rdata[14] = \<const0> ;
assign s_axi_ctrl_rdata[13] = \<const0> ;
assign s_axi_ctrl_rdata[12] = \<const0> ;
assign s_axi_ctrl_rdata[11] = \<const0> ;
assign s_axi_ctrl_rdata[10] = \<const0> ;
assign s_axi_ctrl_rdata[9] = \<const0> ;
assign s_axi_ctrl_rdata[8] = \<const0> ;
assign s_axi_ctrl_rdata[7] = \<const0> ;
assign s_axi_ctrl_rdata[6] = \<const0> ;
assign s_axi_ctrl_rdata[5] = \<const0> ;
assign s_axi_ctrl_rdata[4] = \<const0> ;
assign s_axi_ctrl_rdata[3] = \<const0> ;
assign s_axi_ctrl_rdata[2] = \<const0> ;
assign s_axi_ctrl_rdata[1] = \<const0> ;
assign s_axi_ctrl_rdata[0] = \<const0> ;
assign s_axi_ctrl_rresp[1] = \<const0> ;
assign s_axi_ctrl_rresp[0] = \<const0> ;
assign s_axi_ctrl_rvalid = \<const0> ;
assign s_axi_ctrl_wready = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
GND GND
(.G(\<const0> ));
zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top \gext_inst.abcv4_0_ext_inst
(.bram_addr_a(\^bram_addr_a ),
.bram_addr_b(\^bram_addr_b ),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[15:2]),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[15:2]),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi_bram_ctrl_top" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top
(s_axi_rvalid,
s_axi_rlast,
s_axi_bvalid,
s_axi_awready,
bram_rst_a,
bram_addr_a,
bram_en_a,
bram_we_a,
bram_wrdata_a,
bram_addr_b,
s_axi_rdata,
s_axi_wready,
s_axi_arready,
s_axi_bid,
s_axi_rid,
bram_en_b,
s_axi_aresetn,
s_axi_wvalid,
s_axi_wlast,
s_axi_rready,
s_axi_bready,
s_axi_awburst,
s_axi_aclk,
s_axi_awlen,
s_axi_awaddr,
s_axi_awid,
s_axi_wstrb,
s_axi_wdata,
s_axi_arlen,
s_axi_araddr,
s_axi_arid,
bram_rddata_b,
s_axi_arburst,
s_axi_awvalid,
s_axi_arvalid);
output s_axi_rvalid;
output s_axi_rlast;
output s_axi_bvalid;
output s_axi_awready;
output bram_rst_a;
output [13:0]bram_addr_a;
output bram_en_a;
output [3:0]bram_we_a;
output [31:0]bram_wrdata_a;
output [13:0]bram_addr_b;
output [31:0]s_axi_rdata;
output s_axi_wready;
output s_axi_arready;
output [0:0]s_axi_bid;
output [0:0]s_axi_rid;
output bram_en_b;
input s_axi_aresetn;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_aclk;
input [7:0]s_axi_awlen;
input [13:0]s_axi_awaddr;
input [0:0]s_axi_awid;
input [3:0]s_axi_wstrb;
input [31:0]s_axi_wdata;
input [7:0]s_axi_arlen;
input [13:0]s_axi_araddr;
input [0:0]s_axi_arid;
input [31:0]bram_rddata_b;
input [1:0]s_axi_arburst;
input s_axi_awvalid;
input s_axi_arvalid;
wire [13:0]bram_addr_a;
wire [13:0]bram_addr_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [13:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi \GEN_AXI4.I_FULL_AXI
(.bram_addr_a(bram_addr_a),
.bram_addr_b(bram_addr_b),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "full_axi" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi
(s_axi_rvalid,
s_axi_rlast,
s_axi_bvalid,
s_axi_awready,
bram_rst_a,
bram_addr_a,
bram_en_a,
bram_we_a,
bram_wrdata_a,
bram_addr_b,
s_axi_rdata,
s_axi_wready,
s_axi_arready,
s_axi_bid,
s_axi_rid,
bram_en_b,
s_axi_aresetn,
s_axi_wvalid,
s_axi_wlast,
s_axi_rready,
s_axi_bready,
s_axi_awburst,
s_axi_aclk,
s_axi_awlen,
s_axi_awaddr,
s_axi_awid,
s_axi_wstrb,
s_axi_wdata,
s_axi_arlen,
s_axi_araddr,
s_axi_arid,
bram_rddata_b,
s_axi_arburst,
s_axi_awvalid,
s_axi_arvalid);
output s_axi_rvalid;
output s_axi_rlast;
output s_axi_bvalid;
output s_axi_awready;
output bram_rst_a;
output [13:0]bram_addr_a;
output bram_en_a;
output [3:0]bram_we_a;
output [31:0]bram_wrdata_a;
output [13:0]bram_addr_b;
output [31:0]s_axi_rdata;
output s_axi_wready;
output s_axi_arready;
output [0:0]s_axi_bid;
output [0:0]s_axi_rid;
output bram_en_b;
input s_axi_aresetn;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_aclk;
input [7:0]s_axi_awlen;
input [13:0]s_axi_awaddr;
input [0:0]s_axi_awid;
input [3:0]s_axi_wstrb;
input [31:0]s_axi_wdata;
input [7:0]s_axi_arlen;
input [13:0]s_axi_araddr;
input [0:0]s_axi_arid;
input [31:0]bram_rddata_b;
input [1:0]s_axi_arburst;
input s_axi_awvalid;
input s_axi_arvalid;
wire I_WR_CHNL_n_36;
wire axi_aresetn_d2;
wire axi_aresetn_re_reg;
wire [13:0]bram_addr_a;
wire [13:0]bram_addr_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [13:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl I_RD_CHNL
(.\GEN_AWREADY.axi_aresetn_d2_reg (I_WR_CHNL_n_36),
.Q(bram_addr_b),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_aresetn_re_reg(axi_aresetn_re_reg),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl I_WR_CHNL
(.\GEN_AW_DUAL.aw_active_reg_0 (I_WR_CHNL_n_36),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_aresetn_re_reg(axi_aresetn_re_reg),
.bram_addr_a(bram_addr_a),
.bram_en_a(bram_en_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_aresetn_0(bram_rst_a),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "rd_chnl" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl
(bram_rst_a,
s_axi_rdata,
s_axi_rlast,
s_axi_rvalid,
s_axi_rid,
bram_en_b,
Q,
s_axi_arready,
s_axi_araddr,
s_axi_aclk,
s_axi_arid,
\GEN_AWREADY.axi_aresetn_d2_reg ,
s_axi_aresetn,
s_axi_rready,
s_axi_arlen,
axi_aresetn_d2,
s_axi_arvalid,
axi_aresetn_re_reg,
s_axi_arburst,
bram_rddata_b);
output bram_rst_a;
output [31:0]s_axi_rdata;
output s_axi_rlast;
output s_axi_rvalid;
output [0:0]s_axi_rid;
output bram_en_b;
output [13:0]Q;
output s_axi_arready;
input [13:0]s_axi_araddr;
input s_axi_aclk;
input [0:0]s_axi_arid;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input s_axi_aresetn;
input s_axi_rready;
input [7:0]s_axi_arlen;
input axi_aresetn_d2;
input s_axi_arvalid;
input axi_aresetn_re_reg;
input [1:0]s_axi_arburst;
input [31:0]bram_rddata_b;
wire \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ;
wire \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ;
wire \/i__n_0 ;
wire \FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ;
wire \FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ;
wire \FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ;
wire \GEN_ARREADY.axi_arready_int_i_1_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_2_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_3_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_4_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_1_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_2_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_3_n_0 ;
wire \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ;
wire \GEN_RID.axi_rid_int[0]_i_1_n_0 ;
wire \GEN_RID.axi_rid_int[0]_i_2_n_0 ;
wire \GEN_RID.axi_rid_temp2[0]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp2_full_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp2_reg_n_0_[0] ;
wire \GEN_RID.axi_rid_temp[0]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[0]_i_3_n_0 ;
wire \GEN_RID.axi_rid_temp_full_i_1_n_0 ;
wire I_WRAP_BRST_n_0;
wire I_WRAP_BRST_n_10;
wire I_WRAP_BRST_n_11;
wire I_WRAP_BRST_n_12;
wire I_WRAP_BRST_n_13;
wire I_WRAP_BRST_n_14;
wire I_WRAP_BRST_n_15;
wire I_WRAP_BRST_n_16;
wire I_WRAP_BRST_n_17;
wire I_WRAP_BRST_n_18;
wire I_WRAP_BRST_n_19;
wire I_WRAP_BRST_n_2;
wire I_WRAP_BRST_n_20;
wire I_WRAP_BRST_n_21;
wire I_WRAP_BRST_n_22;
wire I_WRAP_BRST_n_24;
wire I_WRAP_BRST_n_25;
wire I_WRAP_BRST_n_26;
wire I_WRAP_BRST_n_27;
wire I_WRAP_BRST_n_3;
wire I_WRAP_BRST_n_4;
wire I_WRAP_BRST_n_5;
wire I_WRAP_BRST_n_7;
wire I_WRAP_BRST_n_8;
wire I_WRAP_BRST_n_9;
wire [13:0]Q;
wire act_rd_burst;
wire act_rd_burst_i_1_n_0;
wire act_rd_burst_i_3_n_0;
wire act_rd_burst_i_4_n_0;
wire act_rd_burst_i_5_n_0;
wire act_rd_burst_set;
wire act_rd_burst_two;
wire act_rd_burst_two_i_1_n_0;
wire ar_active;
wire araddr_pipe_ld43_out;
wire axi_araddr_full;
wire [1:0]axi_arburst_pipe;
wire axi_aresetn_d2;
wire axi_aresetn_re_reg;
wire axi_arid_pipe;
wire [7:0]axi_arlen_pipe;
wire axi_arlen_pipe_1_or_2;
wire axi_arready_int;
wire [1:1]axi_arsize_pipe;
wire axi_arsize_pipe_max;
wire axi_arsize_pipe_max_i_1_n_0;
wire axi_b2b_brst;
wire axi_b2b_brst_i_1_n_0;
wire axi_b2b_brst_i_2_n_0;
wire axi_early_arready_int;
wire axi_rd_burst;
wire axi_rd_burst_i_1_n_0;
wire axi_rd_burst_i_2_n_0;
wire axi_rd_burst_i_3_n_0;
wire axi_rd_burst_two;
wire axi_rd_burst_two_i_1_n_0;
wire axi_rd_burst_two_reg_n_0;
wire axi_rid_temp;
wire axi_rid_temp2;
wire axi_rid_temp2_full;
wire axi_rid_temp_full;
wire axi_rid_temp_full_d1;
wire axi_rlast_int_i_1_n_0;
wire axi_rlast_set;
wire axi_rvalid_clr_ok;
wire axi_rvalid_clr_ok_i_1_n_0;
wire axi_rvalid_clr_ok_i_2_n_0;
wire axi_rvalid_clr_ok_i_3_n_0;
wire axi_rvalid_int_i_1_n_0;
wire axi_rvalid_set;
wire axi_rvalid_set_cmb;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_en_b;
wire bram_en_int_i_10_n_0;
wire bram_en_int_i_11_n_0;
wire bram_en_int_i_12_n_0;
wire bram_en_int_i_13_n_0;
wire bram_en_int_i_1_n_0;
wire bram_en_int_i_2_n_0;
wire bram_en_int_i_3_n_0;
wire bram_en_int_i_4_n_0;
wire bram_en_int_i_5_n_0;
wire bram_en_int_i_6_n_0;
wire bram_en_int_i_7_n_0;
wire bram_en_int_i_9_n_0;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [7:0]brst_cnt;
wire \brst_cnt[0]_i_1_n_0 ;
wire \brst_cnt[1]_i_1_n_0 ;
wire \brst_cnt[2]_i_1_n_0 ;
wire \brst_cnt[3]_i_1_n_0 ;
wire \brst_cnt[4]_i_1_n_0 ;
wire \brst_cnt[4]_i_2_n_0 ;
wire \brst_cnt[5]_i_1_n_0 ;
wire \brst_cnt[6]_i_1_n_0 ;
wire \brst_cnt[6]_i_2_n_0 ;
wire \brst_cnt[7]_i_1_n_0 ;
wire \brst_cnt[7]_i_2_n_0 ;
wire \brst_cnt[7]_i_3_n_0 ;
wire \brst_cnt[7]_i_4_n_0 ;
wire brst_cnt_max;
wire brst_cnt_max_d1;
wire brst_one;
wire brst_one_i_1_n_0;
wire brst_one_i_2_n_0;
wire brst_zero;
wire brst_zero_i_1_n_0;
wire brst_zero_i_2_n_0;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire disable_b2b_brst;
wire disable_b2b_brst_cmb;
wire disable_b2b_brst_i_2_n_0;
wire disable_b2b_brst_i_3_n_0;
wire disable_b2b_brst_i_4_n_0;
wire end_brst_rd;
wire end_brst_rd_clr;
wire end_brst_rd_clr_i_1_n_0;
wire end_brst_rd_i_1_n_0;
wire last_bram_addr;
wire last_bram_addr0;
wire last_bram_addr_i_2_n_0;
wire last_bram_addr_i_3_n_0;
wire last_bram_addr_i_4_n_0;
wire last_bram_addr_i_5_n_0;
wire last_bram_addr_i_6_n_0;
wire last_bram_addr_i_7_n_0;
wire last_bram_addr_i_8_n_0;
wire last_bram_addr_i_9_n_0;
wire no_ar_ack;
wire no_ar_ack_i_1_n_0;
wire p_0_in13_in;
wire p_13_out;
wire p_48_out;
wire p_4_out;
wire p_9_out;
wire pend_rd_op;
wire pend_rd_op_i_1_n_0;
wire pend_rd_op_i_2_n_0;
wire pend_rd_op_i_3_n_0;
wire pend_rd_op_i_4_n_0;
wire pend_rd_op_i_5_n_0;
wire pend_rd_op_i_6_n_0;
wire pend_rd_op_i_7_n_0;
wire pend_rd_op_i_8_n_0;
wire rd_addr_sm_cs;
wire rd_adv_buf67_out;
wire [3:0]rd_data_sm_cs;
wire \rd_data_sm_cs[0]_i_1_n_0 ;
wire \rd_data_sm_cs[0]_i_2_n_0 ;
wire \rd_data_sm_cs[0]_i_3_n_0 ;
wire \rd_data_sm_cs[0]_i_4_n_0 ;
wire \rd_data_sm_cs[1]_i_1_n_0 ;
wire \rd_data_sm_cs[1]_i_2_n_0 ;
wire \rd_data_sm_cs[2]_i_1_n_0 ;
wire \rd_data_sm_cs[2]_i_2_n_0 ;
wire \rd_data_sm_cs[2]_i_3_n_0 ;
wire \rd_data_sm_cs[2]_i_4_n_0 ;
wire \rd_data_sm_cs[2]_i_5_n_0 ;
wire \rd_data_sm_cs[3]_i_2_n_0 ;
wire \rd_data_sm_cs[3]_i_3_n_0 ;
wire \rd_data_sm_cs[3]_i_4_n_0 ;
wire \rd_data_sm_cs[3]_i_5_n_0 ;
wire \rd_data_sm_cs[3]_i_6_n_0 ;
wire \rd_data_sm_cs[3]_i_7_n_0 ;
wire rd_data_sm_ns;
wire [31:0]rd_skid_buf;
wire rd_skid_buf_ld;
wire rd_skid_buf_ld_cmb;
wire rd_skid_buf_ld_reg;
wire rddata_mux_sel;
wire rddata_mux_sel_cmb;
wire rddata_mux_sel_i_1_n_0;
wire rddata_mux_sel_i_3_n_0;
(* RTL_KEEP = "yes" *) wire [2:0]rlast_sm_cs;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
LUT6 #(
.INIT(64'h0011001300130013))
\/FSM_sequential_rlast_sm_cs[0]_i_2
(.I0(axi_rd_burst),
.I1(rlast_sm_cs[1]),
.I2(act_rd_burst_two),
.I3(axi_rd_burst_two_reg_n_0),
.I4(s_axi_rvalid),
.I5(s_axi_rready),
.O(\/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h003F007F003F0055))
\/FSM_sequential_rlast_sm_cs[1]_i_2
(.I0(axi_rd_burst),
.I1(s_axi_rready),
.I2(s_axi_rvalid),
.I3(rlast_sm_cs[1]),
.I4(axi_rd_burst_two_reg_n_0),
.I5(act_rd_burst_two),
.O(\/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF000F111F000E000))
\/i_
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[1]),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(rlast_sm_cs[0]),
.I5(last_bram_addr),
.O(\/i__n_0 ));
LUT6 #(
.INIT(64'h00008080000F8080))
\/i___0
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(rlast_sm_cs[0]),
.I3(rlast_sm_cs[1]),
.I4(rlast_sm_cs[2]),
.I5(s_axi_rlast),
.O(axi_rlast_set));
LUT5 #(
.INIT(32'h01FF0100))
\FSM_sequential_rlast_sm_cs[0]_i_1
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[0]),
.I2(\/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ),
.I3(\/i__n_0 ),
.I4(rlast_sm_cs[0]),
.O(\FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h01FF0100))
\FSM_sequential_rlast_sm_cs[1]_i_1
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[0]),
.I2(\/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ),
.I3(\/i__n_0 ),
.I4(rlast_sm_cs[1]),
.O(\FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00A4FFFF00A40000))
\FSM_sequential_rlast_sm_cs[2]_i_1
(.I0(rlast_sm_cs[1]),
.I1(p_0_in13_in),
.I2(rlast_sm_cs[0]),
.I3(rlast_sm_cs[2]),
.I4(\/i__n_0 ),
.I5(rlast_sm_cs[2]),
.O(\FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h1))
\FSM_sequential_rlast_sm_cs[2]_i_2
(.I0(axi_rd_burst_two_reg_n_0),
.I1(axi_rd_burst),
.O(p_0_in13_in));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ),
.Q(rlast_sm_cs[0]),
.R(bram_rst_a));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ),
.Q(rlast_sm_cs[1]),
.R(bram_rst_a));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ),
.Q(rlast_sm_cs[2]),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hAAAAAEEE))
\GEN_ARREADY.axi_arready_int_i_1
(.I0(p_9_out),
.I1(axi_arready_int),
.I2(s_axi_arvalid),
.I3(axi_araddr_full),
.I4(araddr_pipe_ld43_out),
.O(\GEN_ARREADY.axi_arready_int_i_1_n_0 ));
LUT4 #(
.INIT(16'hBAAA))
\GEN_ARREADY.axi_arready_int_i_2
(.I0(axi_aresetn_re_reg),
.I1(axi_early_arready_int),
.I2(axi_araddr_full),
.I3(bram_addr_ld_en),
.O(p_9_out));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_ARREADY.axi_arready_int_i_1_n_0 ),
.Q(axi_arready_int),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h0000000000000200))
\GEN_ARREADY.axi_early_arready_int_i_1
(.I0(\GEN_ARREADY.axi_early_arready_int_i_2_n_0 ),
.I1(\GEN_ARREADY.axi_early_arready_int_i_3_n_0 ),
.I2(rd_data_sm_cs[3]),
.I3(brst_one),
.I4(axi_arready_int),
.I5(\GEN_ARREADY.axi_early_arready_int_i_4_n_0 ),
.O(p_48_out));
LUT6 #(
.INIT(64'h03C4000400C40004))
\GEN_ARREADY.axi_early_arready_int_i_2
(.I0(axi_rd_burst_two_reg_n_0),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_adv_buf67_out),
.I5(bram_en_int_i_9_n_0),
.O(\GEN_ARREADY.axi_early_arready_int_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h7))
\GEN_ARREADY.axi_early_arready_int_i_3
(.I0(axi_araddr_full),
.I1(s_axi_arvalid),
.O(\GEN_ARREADY.axi_early_arready_int_i_3_n_0 ));
LUT6 #(
.INIT(64'hAAEAAAEAFFFFAAEA))
\GEN_ARREADY.axi_early_arready_int_i_4
(.I0(I_WRAP_BRST_n_27),
.I1(\rd_data_sm_cs[3]_i_6_n_0 ),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(brst_zero),
.I5(rd_adv_buf67_out),
.O(\GEN_ARREADY.axi_early_arready_int_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_early_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_48_out),
.Q(axi_early_arready_int),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hF0FBFBFBF0F0F0F0))
\GEN_AR_DUAL.ar_active_i_1
(.I0(\GEN_AR_DUAL.ar_active_i_2_n_0 ),
.I1(\rd_data_sm_cs[2]_i_3_n_0 ),
.I2(bram_addr_ld_en),
.I3(\rd_data_sm_cs[2]_i_5_n_0 ),
.I4(rd_adv_buf67_out),
.I5(ar_active),
.O(\GEN_AR_DUAL.ar_active_i_1_n_0 ));
LUT6 #(
.INIT(64'hB0FFBFFFB0FFBF0F))
\GEN_AR_DUAL.ar_active_i_2
(.I0(\GEN_AR_DUAL.ar_active_i_3_n_0 ),
.I1(I_WRAP_BRST_n_27),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[1]),
.I4(axi_rd_burst_two_reg_n_0),
.I5(axi_rd_burst),
.O(\GEN_AR_DUAL.ar_active_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'h0DFFFFFF))
\GEN_AR_DUAL.ar_active_i_3
(.I0(end_brst_rd),
.I1(axi_b2b_brst),
.I2(brst_zero),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(\GEN_AR_DUAL.ar_active_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_DUAL.ar_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_DUAL.ar_active_i_1_n_0 ),
.Q(ar_active),
.R(\GEN_AWREADY.axi_aresetn_d2_reg ));
LUT6 #(
.INIT(64'h10001000F0F01000))
\GEN_AR_DUAL.rd_addr_sm_cs_i_1
(.I0(rd_addr_sm_cs),
.I1(axi_araddr_full),
.I2(s_axi_arvalid),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ),
.I4(last_bram_addr),
.I5(\GEN_ARREADY.axi_early_arready_int_i_4_n_0 ),
.O(\GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ));
FDRE \GEN_AR_DUAL.rd_addr_sm_cs_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ),
.Q(rd_addr_sm_cs),
.R(\GEN_AWREADY.axi_aresetn_d2_reg ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[8]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[9]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[10]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[11]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[12]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[13]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[0]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[1]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[2]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[3]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[4]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[5]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[6]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[7]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.R(1'b0));
LUT6 #(
.INIT(64'h00C08888CCCC8888))
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1
(.I0(araddr_pipe_ld43_out),
.I1(s_axi_aresetn),
.I2(s_axi_arvalid),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ),
.I4(axi_araddr_full),
.I5(bram_addr_ld_en),
.O(\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ),
.Q(axi_araddr_full),
.R(1'b0));
LUT4 #(
.INIT(16'h03AA))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1
(.I0(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.I1(s_axi_arburst[0]),
.I2(s_axi_arburst[1]),
.I3(araddr_pipe_ld43_out),
.O(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ),
.Q(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arburst[0]),
.Q(axi_arburst_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arburst[1]),
.Q(axi_arburst_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid),
.Q(axi_arid_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h220022002A002200))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1
(.I0(axi_aresetn_d2),
.I1(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ),
.I2(rd_addr_sm_cs),
.I3(s_axi_arvalid),
.I4(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ),
.I5(axi_araddr_full),
.O(araddr_pipe_ld43_out));
LUT6 #(
.INIT(64'hFFFFFF70FFFFFFFF))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(brst_zero),
.I3(I_WRAP_BRST_n_26),
.I4(I_WRAP_BRST_n_27),
.I5(last_bram_addr),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hFE))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3
(.I0(no_ar_ack),
.I1(pend_rd_op),
.I2(ar_active),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ));
LUT4 #(
.INIT(16'h0001))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1
(.I0(s_axi_arlen[1]),
.I1(s_axi_arlen[7]),
.I2(s_axi_arlen[4]),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ),
.O(p_13_out));
LUT4 #(
.INIT(16'hFFFE))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2
(.I0(s_axi_arlen[6]),
.I1(s_axi_arlen[2]),
.I2(s_axi_arlen[5]),
.I3(s_axi_arlen[3]),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(p_13_out),
.Q(axi_arlen_pipe_1_or_2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[0]),
.Q(axi_arlen_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[1]),
.Q(axi_arlen_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[2]),
.Q(axi_arlen_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[3]),
.Q(axi_arlen_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[4]),
.Q(axi_arlen_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[5]),
.Q(axi_arlen_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[6]),
.Q(axi_arlen_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[7]),
.Q(axi_arlen_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(1'b1),
.Q(axi_arsize_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000BAAA0000))
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1
(.I0(brst_cnt_max),
.I1(pend_rd_op),
.I2(ar_active),
.I3(brst_zero),
.I4(s_axi_aresetn),
.I5(bram_addr_ld_en),
.O(\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ),
.Q(brst_cnt_max),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2
(.I0(Q[4]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[3]),
.I5(Q[5]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'hF7FFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4
(.I0(Q[6]),
.I1(Q[4]),
.I2(I_WRAP_BRST_n_24),
.I3(Q[5]),
.I4(Q[7]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_14),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_13),
.Q(Q[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_12),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_11),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_10),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_9),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_22),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_21),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_20),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_19),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_18),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_17),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_16),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_15),
.Q(Q[7]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1
(.I0(rd_skid_buf[0]),
.I1(bram_rddata_b[0]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ),
.Q(s_axi_rdata[0]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1
(.I0(rd_skid_buf[10]),
.I1(bram_rddata_b[10]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ),
.Q(s_axi_rdata[10]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1
(.I0(rd_skid_buf[11]),
.I1(bram_rddata_b[11]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ),
.Q(s_axi_rdata[11]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1
(.I0(rd_skid_buf[12]),
.I1(bram_rddata_b[12]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ),
.Q(s_axi_rdata[12]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1
(.I0(rd_skid_buf[13]),
.I1(bram_rddata_b[13]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ),
.Q(s_axi_rdata[13]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1
(.I0(rd_skid_buf[14]),
.I1(bram_rddata_b[14]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ),
.Q(s_axi_rdata[14]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1
(.I0(rd_skid_buf[15]),
.I1(bram_rddata_b[15]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ),
.Q(s_axi_rdata[15]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1
(.I0(rd_skid_buf[16]),
.I1(bram_rddata_b[16]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ),
.Q(s_axi_rdata[16]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1
(.I0(rd_skid_buf[17]),
.I1(bram_rddata_b[17]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ),
.Q(s_axi_rdata[17]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1
(.I0(rd_skid_buf[18]),
.I1(bram_rddata_b[18]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ),
.Q(s_axi_rdata[18]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1
(.I0(rd_skid_buf[19]),
.I1(bram_rddata_b[19]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ),
.Q(s_axi_rdata[19]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1
(.I0(rd_skid_buf[1]),
.I1(bram_rddata_b[1]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ),
.Q(s_axi_rdata[1]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1
(.I0(rd_skid_buf[20]),
.I1(bram_rddata_b[20]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ),
.Q(s_axi_rdata[20]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1
(.I0(rd_skid_buf[21]),
.I1(bram_rddata_b[21]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ),
.Q(s_axi_rdata[21]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1
(.I0(rd_skid_buf[22]),
.I1(bram_rddata_b[22]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ),
.Q(s_axi_rdata[22]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1
(.I0(rd_skid_buf[23]),
.I1(bram_rddata_b[23]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ),
.Q(s_axi_rdata[23]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1
(.I0(rd_skid_buf[24]),
.I1(bram_rddata_b[24]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ),
.Q(s_axi_rdata[24]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1
(.I0(rd_skid_buf[25]),
.I1(bram_rddata_b[25]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ),
.Q(s_axi_rdata[25]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1
(.I0(rd_skid_buf[26]),
.I1(bram_rddata_b[26]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ),
.Q(s_axi_rdata[26]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1
(.I0(rd_skid_buf[27]),
.I1(bram_rddata_b[27]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ),
.Q(s_axi_rdata[27]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1
(.I0(rd_skid_buf[28]),
.I1(bram_rddata_b[28]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ),
.Q(s_axi_rdata[28]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1
(.I0(rd_skid_buf[29]),
.I1(bram_rddata_b[29]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ),
.Q(s_axi_rdata[29]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1
(.I0(rd_skid_buf[2]),
.I1(bram_rddata_b[2]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ),
.Q(s_axi_rdata[2]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1
(.I0(rd_skid_buf[30]),
.I1(bram_rddata_b[30]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ),
.Q(s_axi_rdata[30]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
LUT4 #(
.INIT(16'h08FF))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rlast),
.I2(axi_b2b_brst),
.I3(s_axi_aresetn),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
LUT6 #(
.INIT(64'h1414545410000404))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0 ),
.I4(rd_data_sm_cs[0]),
.I5(rd_adv_buf67_out),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3
(.I0(rd_skid_buf[31]),
.I1(bram_rddata_b[31]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ));
LUT2 #(
.INIT(4'h1))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4
(.I0(act_rd_burst),
.I1(act_rd_burst_two),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h8))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_5
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.O(rd_adv_buf67_out));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ),
.Q(s_axi_rdata[31]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1
(.I0(rd_skid_buf[3]),
.I1(bram_rddata_b[3]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ),
.Q(s_axi_rdata[3]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1
(.I0(rd_skid_buf[4]),
.I1(bram_rddata_b[4]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ),
.Q(s_axi_rdata[4]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1
(.I0(rd_skid_buf[5]),
.I1(bram_rddata_b[5]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ),
.Q(s_axi_rdata[5]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1
(.I0(rd_skid_buf[6]),
.I1(bram_rddata_b[6]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ),
.Q(s_axi_rdata[6]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1
(.I0(rd_skid_buf[7]),
.I1(bram_rddata_b[7]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ),
.Q(s_axi_rdata[7]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1
(.I0(rd_skid_buf[8]),
.I1(bram_rddata_b[8]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ),
.Q(s_axi_rdata[8]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1
(.I0(rd_skid_buf[9]),
.I1(bram_rddata_b[9]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ),
.Q(s_axi_rdata[9]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAABAAAAAA))
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1
(.I0(rd_skid_buf_ld_reg),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[3]),
.I3(rd_adv_buf67_out),
.I4(rd_data_sm_cs[2]),
.I5(rd_data_sm_cs[0]),
.O(rd_skid_buf_ld));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[0]),
.Q(rd_skid_buf[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[10]),
.Q(rd_skid_buf[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[11]),
.Q(rd_skid_buf[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[12]),
.Q(rd_skid_buf[12]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[13]),
.Q(rd_skid_buf[13]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[14]),
.Q(rd_skid_buf[14]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[15]),
.Q(rd_skid_buf[15]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[16]),
.Q(rd_skid_buf[16]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[17]),
.Q(rd_skid_buf[17]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[18]),
.Q(rd_skid_buf[18]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[19]),
.Q(rd_skid_buf[19]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[1]),
.Q(rd_skid_buf[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[20]),
.Q(rd_skid_buf[20]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[21]),
.Q(rd_skid_buf[21]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[22]),
.Q(rd_skid_buf[22]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[23]),
.Q(rd_skid_buf[23]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[24]),
.Q(rd_skid_buf[24]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[25]),
.Q(rd_skid_buf[25]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[26]),
.Q(rd_skid_buf[26]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[27]),
.Q(rd_skid_buf[27]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[28]),
.Q(rd_skid_buf[28]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[29]),
.Q(rd_skid_buf[29]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[2]),
.Q(rd_skid_buf[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[30]),
.Q(rd_skid_buf[30]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[31]),
.Q(rd_skid_buf[31]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[3]),
.Q(rd_skid_buf[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[4]),
.Q(rd_skid_buf[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[5]),
.Q(rd_skid_buf[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[6]),
.Q(rd_skid_buf[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[7]),
.Q(rd_skid_buf[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[8]),
.Q(rd_skid_buf[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[9]),
.Q(rd_skid_buf[9]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hE200E200F0000000))
\GEN_RID.axi_rid_int[0]_i_1
(.I0(s_axi_rid),
.I1(axi_rvalid_set),
.I2(axi_rid_temp),
.I3(s_axi_aresetn),
.I4(axi_b2b_brst),
.I5(\GEN_RID.axi_rid_int[0]_i_2_n_0 ),
.O(\GEN_RID.axi_rid_int[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h7))
\GEN_RID.axi_rid_int[0]_i_2
(.I0(s_axi_rready),
.I1(s_axi_rlast),
.O(\GEN_RID.axi_rid_int[0]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_int[0]_i_1_n_0 ),
.Q(s_axi_rid),
.R(1'b0));
LUT6 #(
.INIT(64'hB8FFFFFFB8000000))
\GEN_RID.axi_rid_temp2[0]_i_1
(.I0(axi_arid_pipe),
.I1(axi_araddr_full),
.I2(s_axi_arid),
.I3(axi_rid_temp_full),
.I4(bram_addr_ld_en),
.I5(\GEN_RID.axi_rid_temp2_reg_n_0_[0] ),
.O(\GEN_RID.axi_rid_temp2[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h08080000C8C800C0))
\GEN_RID.axi_rid_temp2_full_i_1
(.I0(bram_addr_ld_en),
.I1(s_axi_aresetn),
.I2(axi_rid_temp2_full),
.I3(axi_rid_temp_full_d1),
.I4(axi_rid_temp_full),
.I5(p_4_out),
.O(\GEN_RID.axi_rid_temp2_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp2_full_i_1_n_0 ),
.Q(axi_rid_temp2_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp2[0]_i_1_n_0 ),
.Q(\GEN_RID.axi_rid_temp2_reg_n_0_[0] ),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hCFAACFCFC0AAC0C0))
\GEN_RID.axi_rid_temp[0]_i_1
(.I0(axi_rid_temp2),
.I1(\GEN_RID.axi_rid_temp2_reg_n_0_[0] ),
.I2(\GEN_RID.axi_rid_temp[0]_i_3_n_0 ),
.I3(axi_rid_temp_full),
.I4(bram_addr_ld_en),
.I5(axi_rid_temp),
.O(\GEN_RID.axi_rid_temp[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp[0]_i_2
(.I0(axi_arid_pipe),
.I1(axi_araddr_full),
.I2(s_axi_arid),
.O(axi_rid_temp2));
LUT6 #(
.INIT(64'hAA08AAAAAA08AA08))
\GEN_RID.axi_rid_temp[0]_i_3
(.I0(axi_rid_temp2_full),
.I1(axi_rid_temp_full_d1),
.I2(axi_rid_temp_full),
.I3(axi_rvalid_set),
.I4(\GEN_RID.axi_rid_int[0]_i_2_n_0 ),
.I5(axi_b2b_brst),
.O(\GEN_RID.axi_rid_temp[0]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_full_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rid_temp_full),
.Q(axi_rid_temp_full_d1),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hF0F0F0E000F0A0A0))
\GEN_RID.axi_rid_temp_full_i_1
(.I0(bram_addr_ld_en),
.I1(axi_rid_temp_full_d1),
.I2(s_axi_aresetn),
.I3(p_4_out),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2_full),
.O(\GEN_RID.axi_rid_temp_full_i_1_n_0 ));
LUT4 #(
.INIT(16'hEAAA))
\GEN_RID.axi_rid_temp_full_i_2
(.I0(axi_rvalid_set),
.I1(s_axi_rready),
.I2(s_axi_rlast),
.I3(axi_b2b_brst),
.O(p_4_out));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp_full_i_1_n_0 ),
.Q(axi_rid_temp_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp[0]_i_1_n_0 ),
.Q(axi_rid_temp),
.R(bram_rst_a));
zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 I_WRAP_BRST
(.D({I_WRAP_BRST_n_9,I_WRAP_BRST_n_10,I_WRAP_BRST_n_11,I_WRAP_BRST_n_12,I_WRAP_BRST_n_13,I_WRAP_BRST_n_14,I_WRAP_BRST_n_15,I_WRAP_BRST_n_16,I_WRAP_BRST_n_17,I_WRAP_BRST_n_18,I_WRAP_BRST_n_19,I_WRAP_BRST_n_20,I_WRAP_BRST_n_21,I_WRAP_BRST_n_22}),
.E({bram_addr_ld_en_mod,I_WRAP_BRST_n_7}),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg (\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] (axi_arlen_pipe[3:0]),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] (I_WRAP_BRST_n_0),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 (I_WRAP_BRST_n_8),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 (Q[9:0]),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] (I_WRAP_BRST_n_24),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 (\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] (\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0 ),
.Q(rd_data_sm_cs),
.SR(bram_rst_a),
.ar_active(ar_active),
.axi_araddr_full(axi_araddr_full),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_arlen_pipe_1_or_2(axi_arlen_pipe_1_or_2),
.axi_arsize_pipe(axi_arsize_pipe),
.axi_arsize_pipe_max(axi_arsize_pipe_max),
.axi_b2b_brst(axi_b2b_brst),
.axi_rd_burst(axi_rd_burst),
.axi_rd_burst_two_reg(axi_rd_burst_two_reg_n_0),
.axi_rvalid_int_reg(s_axi_rvalid),
.bram_addr_ld_en(bram_addr_ld_en),
.brst_zero(brst_zero),
.curr_fixed_burst_reg(curr_fixed_burst_reg),
.curr_wrap_burst_reg(curr_wrap_burst_reg),
.disable_b2b_brst(disable_b2b_brst),
.end_brst_rd(end_brst_rd),
.last_bram_addr(last_bram_addr),
.no_ar_ack(no_ar_ack),
.pend_rd_op(pend_rd_op),
.rd_addr_sm_cs(rd_addr_sm_cs),
.\rd_data_sm_cs_reg[1] (I_WRAP_BRST_n_25),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arlen(s_axi_arlen[3:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rready(s_axi_rready),
.\save_init_bram_addr_ld_reg[15]_0 (I_WRAP_BRST_n_26),
.\save_init_bram_addr_ld_reg[15]_1 (I_WRAP_BRST_n_27),
.\wrap_burst_total_reg[0]_0 (I_WRAP_BRST_n_2),
.\wrap_burst_total_reg[0]_1 (I_WRAP_BRST_n_3),
.\wrap_burst_total_reg[0]_2 (I_WRAP_BRST_n_4),
.\wrap_burst_total_reg[0]_3 (I_WRAP_BRST_n_5));
LUT6 #(
.INIT(64'h000000002EEE22E2))
act_rd_burst_i_1
(.I0(act_rd_burst),
.I1(act_rd_burst_set),
.I2(bram_addr_ld_en),
.I3(axi_rd_burst_two),
.I4(axi_rd_burst),
.I5(act_rd_burst_i_3_n_0),
.O(act_rd_burst_i_1_n_0));
LUT6 #(
.INIT(64'hA8A888A888888888))
act_rd_burst_i_2
(.I0(\rd_data_sm_cs[2]_i_3_n_0 ),
.I1(act_rd_burst_i_4_n_0),
.I2(act_rd_burst_i_5_n_0),
.I3(axi_rd_burst_i_2_n_0),
.I4(I_WRAP_BRST_n_4),
.I5(bram_addr_ld_en),
.O(act_rd_burst_set));
LUT6 #(
.INIT(64'h20000040FFFFFFFF))
act_rd_burst_i_3
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(\rd_data_sm_cs[3]_i_7_n_0 ),
.I3(rd_data_sm_cs[1]),
.I4(rd_data_sm_cs[0]),
.I5(s_axi_aresetn),
.O(act_rd_burst_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h5500FC00))
act_rd_burst_i_4
(.I0(bram_en_int_i_12_n_0),
.I1(axi_rd_burst_two_reg_n_0),
.I2(axi_rd_burst),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.O(act_rd_burst_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT2 #(
.INIT(4'h1))
act_rd_burst_i_5
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.O(act_rd_burst_i_5_n_0));
FDRE #(
.INIT(1'b0))
act_rd_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(act_rd_burst_i_1_n_0),
.Q(act_rd_burst),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000E2EEE222))
act_rd_burst_two_i_1
(.I0(act_rd_burst_two),
.I1(act_rd_burst_set),
.I2(axi_rd_burst_two),
.I3(bram_addr_ld_en),
.I4(axi_rd_burst_two_reg_n_0),
.I5(act_rd_burst_i_3_n_0),
.O(act_rd_burst_two_i_1_n_0));
FDRE #(
.INIT(1'b0))
act_rd_burst_two_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(act_rd_burst_two_i_1_n_0),
.Q(act_rd_burst_two),
.R(1'b0));
LUT2 #(
.INIT(4'hE))
axi_arsize_pipe_max_i_1
(.I0(araddr_pipe_ld43_out),
.I1(axi_arsize_pipe_max),
.O(axi_arsize_pipe_max_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_arsize_pipe_max_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_arsize_pipe_max_i_1_n_0),
.Q(axi_arsize_pipe_max),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hF000F074F0F0F074))
axi_b2b_brst_i_1
(.I0(I_WRAP_BRST_n_27),
.I1(axi_b2b_brst_i_2_n_0),
.I2(axi_b2b_brst),
.I3(rd_data_sm_cs[3]),
.I4(rd_data_sm_cs[2]),
.I5(disable_b2b_brst_i_2_n_0),
.O(axi_b2b_brst_i_1_n_0));
LUT6 #(
.INIT(64'h00000000AA080000))
axi_b2b_brst_i_2
(.I0(\rd_data_sm_cs[0]_i_3_n_0 ),
.I1(end_brst_rd),
.I2(axi_b2b_brst),
.I3(brst_zero),
.I4(rd_adv_buf67_out),
.I5(I_WRAP_BRST_n_27),
.O(axi_b2b_brst_i_2_n_0));
FDRE #(
.INIT(1'b0))
axi_b2b_brst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_b2b_brst_i_1_n_0),
.Q(axi_b2b_brst),
.R(bram_rst_a));
LUT5 #(
.INIT(32'h303000A0))
axi_rd_burst_i_1
(.I0(axi_rd_burst),
.I1(axi_rd_burst_i_2_n_0),
.I2(s_axi_aresetn),
.I3(brst_zero),
.I4(bram_addr_ld_en),
.O(axi_rd_burst_i_1_n_0));
LUT6 #(
.INIT(64'h0000000001000111))
axi_rd_burst_i_2
(.I0(I_WRAP_BRST_n_2),
.I1(I_WRAP_BRST_n_5),
.I2(axi_arlen_pipe[1]),
.I3(axi_araddr_full),
.I4(s_axi_arlen[1]),
.I5(axi_rd_burst_i_3_n_0),
.O(axi_rd_burst_i_2_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFBBFCB8))
axi_rd_burst_i_3
(.I0(axi_arlen_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[5]),
.I3(axi_arlen_pipe[4]),
.I4(s_axi_arlen[4]),
.I5(last_bram_addr_i_9_n_0),
.O(axi_rd_burst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_rd_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rd_burst_i_1_n_0),
.Q(axi_rd_burst),
.R(1'b0));
LUT5 #(
.INIT(32'hC0C000A0))
axi_rd_burst_two_i_1
(.I0(axi_rd_burst_two_reg_n_0),
.I1(axi_rd_burst_two),
.I2(s_axi_aresetn),
.I3(brst_zero),
.I4(bram_addr_ld_en),
.O(axi_rd_burst_two_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hA808))
axi_rd_burst_two_i_2
(.I0(axi_rd_burst_i_2_n_0),
.I1(s_axi_arlen[0]),
.I2(axi_araddr_full),
.I3(axi_arlen_pipe[0]),
.O(axi_rd_burst_two));
FDRE #(
.INIT(1'b0))
axi_rd_burst_two_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rd_burst_two_i_1_n_0),
.Q(axi_rd_burst_two_reg_n_0),
.R(1'b0));
LUT4 #(
.INIT(16'h88A8))
axi_rlast_int_i_1
(.I0(s_axi_aresetn),
.I1(axi_rlast_set),
.I2(s_axi_rlast),
.I3(s_axi_rready),
.O(axi_rlast_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_rlast_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rlast_int_i_1_n_0),
.Q(s_axi_rlast),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000FFFFEEEA))
axi_rvalid_clr_ok_i_1
(.I0(axi_rvalid_clr_ok),
.I1(last_bram_addr),
.I2(disable_b2b_brst),
.I3(disable_b2b_brst_cmb),
.I4(axi_rvalid_clr_ok_i_2_n_0),
.I5(axi_rvalid_clr_ok_i_3_n_0),
.O(axi_rvalid_clr_ok_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'hAAAAAEAA))
axi_rvalid_clr_ok_i_2
(.I0(bram_addr_ld_en),
.I1(rd_data_sm_cs[0]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[3]),
.O(axi_rvalid_clr_ok_i_2_n_0));
LUT3 #(
.INIT(8'h4F))
axi_rvalid_clr_ok_i_3
(.I0(\GEN_ARREADY.axi_early_arready_int_i_4_n_0 ),
.I1(bram_addr_ld_en),
.I2(s_axi_aresetn),
.O(axi_rvalid_clr_ok_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_rvalid_clr_ok_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_clr_ok_i_1_n_0),
.Q(axi_rvalid_clr_ok),
.R(1'b0));
LUT6 #(
.INIT(64'h00E0E0E0E0E0E0E0))
axi_rvalid_int_i_1
(.I0(s_axi_rvalid),
.I1(axi_rvalid_set),
.I2(s_axi_aresetn),
.I3(axi_rvalid_clr_ok),
.I4(s_axi_rlast),
.I5(s_axi_rready),
.O(axi_rvalid_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_rvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_int_i_1_n_0),
.Q(s_axi_rvalid),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h0100))
axi_rvalid_set_i_1
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.O(axi_rvalid_set_cmb));
FDRE #(
.INIT(1'b0))
axi_rvalid_set_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_set_cmb),
.Q(axi_rvalid_set),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFEEFFFA0022000A))
bram_en_int_i_1
(.I0(bram_en_int_i_2_n_0),
.I1(bram_en_int_i_3_n_0),
.I2(bram_en_int_i_4_n_0),
.I3(rd_data_sm_cs[3]),
.I4(rd_data_sm_cs[2]),
.I5(bram_en_b),
.O(bram_en_int_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'hE0000000))
bram_en_int_i_10
(.I0(act_rd_burst),
.I1(act_rd_burst_two),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(bram_addr_ld_en),
.O(bram_en_int_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h0111))
bram_en_int_i_11
(.I0(end_brst_rd),
.I1(brst_zero),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(bram_en_int_i_11_n_0));
LUT6 #(
.INIT(64'hBFFFBFBFBFFFBFFF))
bram_en_int_i_12
(.I0(I_WRAP_BRST_n_27),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(brst_zero),
.I4(axi_b2b_brst),
.I5(end_brst_rd),
.O(bram_en_int_i_12_n_0));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'h45))
bram_en_int_i_13
(.I0(brst_zero),
.I1(axi_b2b_brst),
.I2(end_brst_rd),
.O(bram_en_int_i_13_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF4044))
bram_en_int_i_2
(.I0(bram_en_int_i_5_n_0),
.I1(rd_data_sm_cs[1]),
.I2(bram_en_int_i_6_n_0),
.I3(rd_data_sm_cs[2]),
.I4(bram_en_int_i_7_n_0),
.I5(I_WRAP_BRST_n_0),
.O(bram_en_int_i_2_n_0));
LUT6 #(
.INIT(64'h707370707C7F7C7C))
bram_en_int_i_3
(.I0(bram_en_int_i_6_n_0),
.I1(rd_data_sm_cs[0]),
.I2(rd_data_sm_cs[1]),
.I3(rd_adv_buf67_out),
.I4(bram_en_int_i_9_n_0),
.I5(bram_en_int_i_10_n_0),
.O(bram_en_int_i_3_n_0));
LUT6 #(
.INIT(64'hA0001111AAAA1111))
bram_en_int_i_4
(.I0(rd_data_sm_cs[0]),
.I1(bram_addr_ld_en),
.I2(bram_en_int_i_11_n_0),
.I3(brst_one),
.I4(rd_data_sm_cs[1]),
.I5(bram_en_int_i_12_n_0),
.O(bram_en_int_i_4_n_0));
LUT6 #(
.INIT(64'h0044054455440544))
bram_en_int_i_5
(.I0(rd_data_sm_cs[2]),
.I1(axi_rd_burst_two_reg_n_0),
.I2(bram_en_int_i_9_n_0),
.I3(rd_data_sm_cs[0]),
.I4(rd_adv_buf67_out),
.I5(bram_en_int_i_13_n_0),
.O(bram_en_int_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hECCC))
bram_en_int_i_6
(.I0(pend_rd_op),
.I1(bram_addr_ld_en),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.O(bram_en_int_i_6_n_0));
LUT6 #(
.INIT(64'h5554005500540000))
bram_en_int_i_7
(.I0(rd_data_sm_cs[1]),
.I1(axi_rd_burst_two_reg_n_0),
.I2(axi_rd_burst),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[0]),
.I5(bram_addr_ld_en),
.O(bram_en_int_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h1))
bram_en_int_i_9
(.I0(brst_zero),
.I1(end_brst_rd),
.O(bram_en_int_i_9_n_0));
FDRE #(
.INIT(1'b0))
bram_en_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bram_en_int_i_1_n_0),
.Q(bram_en_b),
.R(bram_rst_a));
LUT5 #(
.INIT(32'hD1DDD111))
\brst_cnt[0]_i_1
(.I0(brst_cnt[0]),
.I1(bram_addr_ld_en),
.I2(axi_arlen_pipe[0]),
.I3(axi_araddr_full),
.I4(s_axi_arlen[0]),
.O(\brst_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8FFB800B800B8FF))
\brst_cnt[1]_i_1
(.I0(axi_arlen_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[1]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[0]),
.I5(brst_cnt[1]),
.O(\brst_cnt[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8B8B88B))
\brst_cnt[2]_i_1
(.I0(I_WRAP_BRST_n_2),
.I1(bram_addr_ld_en),
.I2(brst_cnt[2]),
.I3(brst_cnt[1]),
.I4(brst_cnt[0]),
.O(\brst_cnt[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8B8B8B8B88B))
\brst_cnt[3]_i_1
(.I0(I_WRAP_BRST_n_5),
.I1(bram_addr_ld_en),
.I2(brst_cnt[3]),
.I3(brst_cnt[2]),
.I4(brst_cnt[0]),
.I5(brst_cnt[1]),
.O(\brst_cnt[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8FFB800B800B8FF))
\brst_cnt[4]_i_1
(.I0(axi_arlen_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[4]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[4]),
.I5(\brst_cnt[4]_i_2_n_0 ),
.O(\brst_cnt[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hFFFE))
\brst_cnt[4]_i_2
(.I0(brst_cnt[3]),
.I1(brst_cnt[2]),
.I2(brst_cnt[0]),
.I3(brst_cnt[1]),
.O(\brst_cnt[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\brst_cnt[5]_i_1
(.I0(axi_arlen_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[5]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[5]),
.I5(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hB88BB8B8))
\brst_cnt[6]_i_1
(.I0(\brst_cnt[6]_i_2_n_0 ),
.I1(bram_addr_ld_en),
.I2(brst_cnt[6]),
.I3(brst_cnt[5]),
.I4(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\brst_cnt[6]_i_2
(.I0(axi_arlen_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[6]),
.O(\brst_cnt[6]_i_2_n_0 ));
LUT2 #(
.INIT(4'hE))
\brst_cnt[7]_i_1
(.I0(bram_addr_ld_en),
.I1(I_WRAP_BRST_n_8),
.O(\brst_cnt[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B88BB8B8B8B8))
\brst_cnt[7]_i_2
(.I0(\brst_cnt[7]_i_3_n_0 ),
.I1(bram_addr_ld_en),
.I2(brst_cnt[7]),
.I3(brst_cnt[6]),
.I4(brst_cnt[5]),
.I5(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\brst_cnt[7]_i_3
(.I0(axi_arlen_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[7]),
.O(\brst_cnt[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h00000001))
\brst_cnt[7]_i_4
(.I0(brst_cnt[4]),
.I1(brst_cnt[1]),
.I2(brst_cnt[0]),
.I3(brst_cnt[2]),
.I4(brst_cnt[3]),
.O(\brst_cnt[7]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
brst_cnt_max_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_cnt_max),
.Q(brst_cnt_max_d1),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[0]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[0]_i_1_n_0 ),
.Q(brst_cnt[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[1]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[1]_i_1_n_0 ),
.Q(brst_cnt[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[2]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[2]_i_1_n_0 ),
.Q(brst_cnt[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[3]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[3]_i_1_n_0 ),
.Q(brst_cnt[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[4]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[4]_i_1_n_0 ),
.Q(brst_cnt[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[5]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[5]_i_1_n_0 ),
.Q(brst_cnt[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[6]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[6]_i_1_n_0 ),
.Q(brst_cnt[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[7]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[7]_i_2_n_0 ),
.Q(brst_cnt[7]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h00000000F0EE0000))
brst_one_i_1
(.I0(brst_one),
.I1(brst_one_i_2_n_0),
.I2(axi_rd_burst_two),
.I3(bram_addr_ld_en),
.I4(s_axi_aresetn),
.I5(last_bram_addr_i_2_n_0),
.O(brst_one_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'h08))
brst_one_i_2
(.I0(last_bram_addr_i_5_n_0),
.I1(brst_cnt[1]),
.I2(brst_cnt[0]),
.O(brst_one_i_2_n_0));
FDRE #(
.INIT(1'b0))
brst_one_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_one_i_1_n_0),
.Q(brst_one),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h00E0))
brst_zero_i_1
(.I0(brst_zero),
.I1(last_bram_addr_i_2_n_0),
.I2(s_axi_aresetn),
.I3(brst_zero_i_2_n_0),
.O(brst_zero_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h8A80AAAA))
brst_zero_i_2
(.I0(bram_addr_ld_en),
.I1(axi_arlen_pipe[0]),
.I2(axi_araddr_full),
.I3(s_axi_arlen[0]),
.I4(axi_rd_burst_i_2_n_0),
.O(brst_zero_i_2_n_0));
FDRE #(
.INIT(1'b0))
brst_zero_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_zero_i_1_n_0),
.Q(brst_zero),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00053305))
curr_fixed_burst_reg_i_1
(.I0(s_axi_arburst[0]),
.I1(axi_arburst_pipe[0]),
.I2(s_axi_arburst[1]),
.I3(axi_araddr_full),
.I4(axi_arburst_pipe[1]),
.O(curr_fixed_burst));
FDRE #(
.INIT(1'b0))
curr_fixed_burst_reg_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_fixed_burst),
.Q(curr_fixed_burst_reg),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h000ACC0A))
curr_wrap_burst_reg_i_1
(.I0(s_axi_arburst[1]),
.I1(axi_arburst_pipe[1]),
.I2(s_axi_arburst[0]),
.I3(axi_araddr_full),
.I4(axi_arburst_pipe[0]),
.O(curr_wrap_burst));
FDRE #(
.INIT(1'b0))
curr_wrap_burst_reg_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_wrap_burst),
.Q(curr_wrap_burst_reg),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFFF000D0000))
disable_b2b_brst_i_1
(.I0(axi_rd_burst),
.I1(axi_rd_burst_two_reg_n_0),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[3]),
.I4(disable_b2b_brst_i_2_n_0),
.I5(disable_b2b_brst_i_3_n_0),
.O(disable_b2b_brst_cmb));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT2 #(
.INIT(4'h2))
disable_b2b_brst_i_2
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.O(disable_b2b_brst_i_2_n_0));
LUT6 #(
.INIT(64'hEEEEEEE00EE0EEEE))
disable_b2b_brst_i_3
(.I0(disable_b2b_brst_i_4_n_0),
.I1(disable_b2b_brst),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[1]),
.I4(rd_data_sm_cs[0]),
.I5(rd_data_sm_cs[3]),
.O(disable_b2b_brst_i_3_n_0));
LUT6 #(
.INIT(64'h0000FE0000000000))
disable_b2b_brst_i_4
(.I0(brst_zero),
.I1(end_brst_rd),
.I2(brst_one),
.I3(rd_data_sm_cs[0]),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[2]_i_3_n_0 ),
.O(disable_b2b_brst_i_4_n_0));
FDRE #(
.INIT(1'b0))
disable_b2b_brst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(disable_b2b_brst_cmb),
.Q(disable_b2b_brst),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFCD00002200))
end_brst_rd_clr_i_1
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.I2(bram_addr_ld_en),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[3]),
.I5(end_brst_rd_clr),
.O(end_brst_rd_clr_i_1_n_0));
FDRE #(
.INIT(1'b0))
end_brst_rd_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(end_brst_rd_clr_i_1_n_0),
.Q(end_brst_rd_clr),
.R(bram_rst_a));
LUT5 #(
.INIT(32'h0020F020))
end_brst_rd_i_1
(.I0(brst_cnt_max),
.I1(brst_cnt_max_d1),
.I2(s_axi_aresetn),
.I3(end_brst_rd),
.I4(end_brst_rd_clr),
.O(end_brst_rd_i_1_n_0));
FDRE #(
.INIT(1'b0))
end_brst_rd_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(end_brst_rd_i_1_n_0),
.Q(end_brst_rd),
.R(1'b0));
LUT6 #(
.INIT(64'hFAAAAAAAAAAAAFAB))
last_bram_addr_i_1
(.I0(last_bram_addr_i_2_n_0),
.I1(last_bram_addr_i_3_n_0),
.I2(rd_data_sm_cs[2]),
.I3(last_bram_addr_i_4_n_0),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(last_bram_addr0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'h08))
last_bram_addr_i_2
(.I0(last_bram_addr_i_5_n_0),
.I1(brst_cnt[0]),
.I2(brst_cnt[1]),
.O(last_bram_addr_i_2_n_0));
LUT6 #(
.INIT(64'h7F7F707F7F7F7F7F))
last_bram_addr_i_3
(.I0(p_0_in13_in),
.I1(rd_adv_buf67_out),
.I2(rd_data_sm_cs[3]),
.I3(bram_addr_ld_en),
.I4(I_WRAP_BRST_n_4),
.I5(axi_rd_burst_i_2_n_0),
.O(last_bram_addr_i_3_n_0));
LUT6 #(
.INIT(64'hA888200000000000))
last_bram_addr_i_4
(.I0(rd_adv_buf67_out),
.I1(bram_addr_ld_en),
.I2(pend_rd_op),
.I3(p_0_in13_in),
.I4(last_bram_addr_i_6_n_0),
.I5(\rd_data_sm_cs[3]_i_6_n_0 ),
.O(last_bram_addr_i_4_n_0));
LUT6 #(
.INIT(64'h0000000000000002))
last_bram_addr_i_5
(.I0(I_WRAP_BRST_n_8),
.I1(brst_cnt[7]),
.I2(brst_cnt[3]),
.I3(brst_cnt[4]),
.I4(brst_cnt[2]),
.I5(last_bram_addr_i_7_n_0),
.O(last_bram_addr_i_5_n_0));
LUT6 #(
.INIT(64'h0000000000000001))
last_bram_addr_i_6
(.I0(last_bram_addr_i_8_n_0),
.I1(last_bram_addr_i_9_n_0),
.I2(I_WRAP_BRST_n_3),
.I3(I_WRAP_BRST_n_5),
.I4(I_WRAP_BRST_n_2),
.I5(I_WRAP_BRST_n_4),
.O(last_bram_addr_i_6_n_0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'hE))
last_bram_addr_i_7
(.I0(brst_cnt[6]),
.I1(brst_cnt[5]),
.O(last_bram_addr_i_7_n_0));
LUT5 #(
.INIT(32'hFFFACCFA))
last_bram_addr_i_8
(.I0(s_axi_arlen[4]),
.I1(axi_arlen_pipe[4]),
.I2(s_axi_arlen[5]),
.I3(axi_araddr_full),
.I4(axi_arlen_pipe[5]),
.O(last_bram_addr_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hFFFACCFA))
last_bram_addr_i_9
(.I0(s_axi_arlen[6]),
.I1(axi_arlen_pipe[6]),
.I2(s_axi_arlen[7]),
.I3(axi_araddr_full),
.I4(axi_arlen_pipe[7]),
.O(last_bram_addr_i_9_n_0));
FDRE #(
.INIT(1'b0))
last_bram_addr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(last_bram_addr0),
.Q(last_bram_addr),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h88C8AAAAAAAAAAAA))
no_ar_ack_i_1
(.I0(no_ar_ack),
.I1(rd_data_sm_cs[1]),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(\rd_data_sm_cs[3]_i_6_n_0 ),
.I5(rd_data_sm_cs[0]),
.O(no_ar_ack_i_1_n_0));
FDRE #(
.INIT(1'b0))
no_ar_ack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(no_ar_ack_i_1_n_0),
.Q(no_ar_ack),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hAAAAFFFEAAAA0002))
pend_rd_op_i_1
(.I0(pend_rd_op_i_2_n_0),
.I1(pend_rd_op_i_3_n_0),
.I2(rd_data_sm_cs[3]),
.I3(rd_data_sm_cs[2]),
.I4(pend_rd_op_i_4_n_0),
.I5(pend_rd_op),
.O(pend_rd_op_i_1_n_0));
LUT6 #(
.INIT(64'h0FFCC8C80CCCC8C8))
pend_rd_op_i_2
(.I0(p_0_in13_in),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[2]),
.I5(pend_rd_op_i_5_n_0),
.O(pend_rd_op_i_2_n_0));
LUT6 #(
.INIT(64'h0303070733F3FFFF))
pend_rd_op_i_3
(.I0(p_0_in13_in),
.I1(rd_data_sm_cs[0]),
.I2(rd_data_sm_cs[1]),
.I3(s_axi_rlast),
.I4(pend_rd_op),
.I5(bram_addr_ld_en),
.O(pend_rd_op_i_3_n_0));
LUT6 #(
.INIT(64'h0000000080FFD5FF))
pend_rd_op_i_4
(.I0(rd_data_sm_cs[0]),
.I1(rd_adv_buf67_out),
.I2(pend_rd_op),
.I3(rd_data_sm_cs[1]),
.I4(pend_rd_op_i_6_n_0),
.I5(pend_rd_op_i_7_n_0),
.O(pend_rd_op_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
pend_rd_op_i_5
(.I0(ar_active),
.I1(end_brst_rd),
.O(pend_rd_op_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'h15))
pend_rd_op_i_6
(.I0(bram_addr_ld_en),
.I1(end_brst_rd),
.I2(ar_active),
.O(pend_rd_op_i_6_n_0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'hF1FF))
pend_rd_op_i_7
(.I0(pend_rd_op_i_8_n_0),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[3]),
.I3(rd_data_sm_cs[2]),
.O(pend_rd_op_i_7_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFF0008888))
pend_rd_op_i_8
(.I0(pend_rd_op),
.I1(s_axi_rlast),
.I2(ar_active),
.I3(end_brst_rd),
.I4(rd_data_sm_cs[0]),
.I5(rd_data_sm_cs[1]),
.O(pend_rd_op_i_8_n_0));
FDRE #(
.INIT(1'b0))
pend_rd_op_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(pend_rd_op_i_1_n_0),
.Q(pend_rd_op),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFFF54005555))
\rd_data_sm_cs[0]_i_1
(.I0(\rd_data_sm_cs[0]_i_2_n_0 ),
.I1(pend_rd_op),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(\rd_data_sm_cs[0]_i_3_n_0 ),
.I5(\rd_data_sm_cs[0]_i_4_n_0 ),
.O(\rd_data_sm_cs[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hE000E0E0FFFFFFFF))
\rd_data_sm_cs[0]_i_2
(.I0(act_rd_burst_two),
.I1(act_rd_burst),
.I2(disable_b2b_brst_i_2_n_0),
.I3(bram_addr_ld_en),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[3]_i_6_n_0 ),
.O(\rd_data_sm_cs[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\rd_data_sm_cs[0]_i_3
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h001100F7001100D5))
\rd_data_sm_cs[0]_i_4
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.I2(rd_adv_buf67_out),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[3]),
.I5(p_0_in13_in),
.O(\rd_data_sm_cs[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAAAEAAAEFFFFAAAE))
\rd_data_sm_cs[1]_i_1
(.I0(\rd_data_sm_cs[2]_i_2_n_0 ),
.I1(\rd_data_sm_cs[1]_i_2_n_0 ),
.I2(end_brst_rd),
.I3(brst_zero),
.I4(I_WRAP_BRST_n_25),
.I5(\rd_data_sm_cs[2]_i_4_n_0 ),
.O(\rd_data_sm_cs[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'h04))
\rd_data_sm_cs[1]_i_2
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFEEEAEAEA))
\rd_data_sm_cs[2]_i_1
(.I0(\rd_data_sm_cs[2]_i_2_n_0 ),
.I1(\rd_data_sm_cs[2]_i_3_n_0 ),
.I2(\rd_data_sm_cs[2]_i_4_n_0 ),
.I3(p_0_in13_in),
.I4(disable_b2b_brst_i_2_n_0),
.I5(\rd_data_sm_cs[2]_i_5_n_0 ),
.O(\rd_data_sm_cs[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000007000F000000))
\rd_data_sm_cs[2]_i_2
(.I0(\rd_data_sm_cs[3]_i_7_n_0 ),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[3]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h1))
\rd_data_sm_cs[2]_i_3
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.O(\rd_data_sm_cs[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hC8C8C8C808C8C8C8))
\rd_data_sm_cs[2]_i_4
(.I0(axi_rd_burst_two_reg_n_0),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[0]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.I5(I_WRAP_BRST_n_27),
.O(\rd_data_sm_cs[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0004000400040000))
\rd_data_sm_cs[2]_i_5
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(brst_zero),
.I5(end_brst_rd),
.O(\rd_data_sm_cs[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'h7444777730007444))
\rd_data_sm_cs[3]_i_1
(.I0(\rd_data_sm_cs[3]_i_3_n_0 ),
.I1(\rd_data_sm_cs[3]_i_4_n_0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.I4(\rd_data_sm_cs[3]_i_5_n_0 ),
.I5(bram_addr_ld_en),
.O(rd_data_sm_ns));
LUT6 #(
.INIT(64'h00800000AA800000))
\rd_data_sm_cs[3]_i_2
(.I0(\rd_data_sm_cs[3]_i_6_n_0 ),
.I1(bram_addr_ld_en),
.I2(\rd_data_sm_cs[3]_i_7_n_0 ),
.I3(rd_data_sm_cs[1]),
.I4(rd_data_sm_cs[0]),
.I5(rd_adv_buf67_out),
.O(\rd_data_sm_cs[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000D0000000000))
\rd_data_sm_cs[3]_i_3
(.I0(end_brst_rd),
.I1(axi_b2b_brst),
.I2(brst_zero),
.I3(rd_adv_buf67_out),
.I4(rd_data_sm_cs[3]),
.I5(\rd_data_sm_cs[0]_i_3_n_0 ),
.O(\rd_data_sm_cs[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hBFAD))
\rd_data_sm_cs[3]_i_4
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[3]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h0053))
\rd_data_sm_cs[3]_i_5
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h2))
\rd_data_sm_cs[3]_i_6
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.O(\rd_data_sm_cs[3]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h8880))
\rd_data_sm_cs[3]_i_7
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(act_rd_burst_two),
.I3(act_rd_burst),
.O(\rd_data_sm_cs[3]_i_7_n_0 ));
FDRE \rd_data_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[0]_i_1_n_0 ),
.Q(rd_data_sm_cs[0]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[1]_i_1_n_0 ),
.Q(rd_data_sm_cs[1]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[2]_i_1_n_0 ),
.Q(rd_data_sm_cs[2]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[3]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[3]_i_2_n_0 ),
.Q(rd_data_sm_cs[3]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h1000111111110000))
rd_skid_buf_ld_reg_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(rd_skid_buf_ld_cmb));
FDRE #(
.INIT(1'b0))
rd_skid_buf_ld_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rd_skid_buf_ld_cmb),
.Q(rd_skid_buf_ld_reg),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'hFE02))
rddata_mux_sel_i_1
(.I0(rddata_mux_sel_cmb),
.I1(rd_data_sm_cs[3]),
.I2(rddata_mux_sel_i_3_n_0),
.I3(rddata_mux_sel),
.O(rddata_mux_sel_i_1_n_0));
LUT6 #(
.INIT(64'hD208D208D208F208))
rddata_mux_sel_i_2
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.I2(rd_adv_buf67_out),
.I3(rd_data_sm_cs[2]),
.I4(act_rd_burst),
.I5(act_rd_burst_two),
.O(rddata_mux_sel_cmb));
LUT6 #(
.INIT(64'hA007AF07AF07AF07))
rddata_mux_sel_i_3
(.I0(rd_data_sm_cs[1]),
.I1(axi_rd_burst_two_reg_n_0),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(s_axi_rvalid),
.I5(s_axi_rready),
.O(rddata_mux_sel_i_3_n_0));
FDRE #(
.INIT(1'b0))
rddata_mux_sel_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rddata_mux_sel_i_1_n_0),
.Q(rddata_mux_sel),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'hEAAA))
s_axi_arready_INST_0
(.I0(axi_arready_int),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(axi_early_arready_int),
.O(s_axi_arready));
endmodule
(* ORIG_REF_NAME = "wr_chnl" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl
(axi_aresetn_d2,
axi_aresetn_re_reg,
bram_en_a,
bram_wrdata_a,
s_axi_bvalid,
\GEN_AW_DUAL.aw_active_reg_0 ,
s_axi_wready,
s_axi_awready,
s_axi_bid,
bram_addr_a,
bram_we_a,
s_axi_aresetn_0,
s_axi_aclk,
s_axi_awaddr,
s_axi_aresetn,
s_axi_awid,
s_axi_wdata,
s_axi_wvalid,
s_axi_wlast,
s_axi_bready,
s_axi_awburst,
s_axi_awvalid,
s_axi_awlen,
s_axi_wstrb);
output axi_aresetn_d2;
output axi_aresetn_re_reg;
output bram_en_a;
output [31:0]bram_wrdata_a;
output s_axi_bvalid;
output \GEN_AW_DUAL.aw_active_reg_0 ;
output s_axi_wready;
output s_axi_awready;
output [0:0]s_axi_bid;
output [13:0]bram_addr_a;
output [3:0]bram_we_a;
input s_axi_aresetn_0;
input s_axi_aclk;
input [13:0]s_axi_awaddr;
input s_axi_aresetn;
input [0:0]s_axi_awid;
input [31:0]s_axi_wdata;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
input [7:0]s_axi_awlen;
input [3:0]s_axi_wstrb;
wire BID_FIFO_n_1;
wire BID_FIFO_n_4;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_1_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_2_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_3_n_0 ;
wire \GEN_AW_DUAL.aw_active_i_2_n_0 ;
wire \GEN_AW_DUAL.aw_active_reg_0 ;
wire \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ;
wire \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ;
wire \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ;
wire \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ;
wire \I_RD_CHNL/axi_aresetn_d1 ;
wire I_WRAP_BRST_n_0;
wire I_WRAP_BRST_n_10;
wire I_WRAP_BRST_n_11;
wire I_WRAP_BRST_n_12;
wire I_WRAP_BRST_n_13;
wire I_WRAP_BRST_n_14;
wire I_WRAP_BRST_n_15;
wire I_WRAP_BRST_n_16;
wire I_WRAP_BRST_n_17;
wire I_WRAP_BRST_n_19;
wire I_WRAP_BRST_n_2;
wire I_WRAP_BRST_n_20;
wire I_WRAP_BRST_n_21;
wire I_WRAP_BRST_n_22;
wire I_WRAP_BRST_n_23;
wire I_WRAP_BRST_n_24;
wire I_WRAP_BRST_n_25;
wire I_WRAP_BRST_n_7;
wire I_WRAP_BRST_n_8;
wire I_WRAP_BRST_n_9;
wire aw_active;
wire axi_aresetn_d2;
wire axi_aresetn_re;
wire axi_aresetn_re_reg;
wire axi_awaddr_full;
wire [1:0]axi_awburst_pipe;
wire axi_awid_pipe;
wire [7:0]axi_awlen_pipe;
wire axi_awlen_pipe_1_or_2;
wire [1:1]axi_awsize_pipe;
wire axi_bvalid_int_i_1_n_0;
wire axi_wdata_full_cmb;
wire axi_wdata_full_cmb114_out;
wire axi_wdata_full_reg;
wire axi_wr_burst;
wire axi_wr_burst_cmb;
wire axi_wr_burst_cmb0;
wire axi_wr_burst_i_1_n_0;
wire axi_wr_burst_i_3_n_0;
wire axi_wready_int_mod_i_1_n_0;
wire axi_wready_int_mod_i_3_n_0;
wire bid_gets_fifo_load;
wire bid_gets_fifo_load_d1;
wire bid_gets_fifo_load_d1_i_2_n_0;
wire [13:0]bram_addr_a;
wire bram_addr_inc;
wire [13:10]bram_addr_ld;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_addr_rst_cmb;
wire bram_en_a;
wire bram_en_cmb;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire [2:0]bvalid_cnt;
wire \bvalid_cnt[0]_i_1_n_0 ;
wire \bvalid_cnt[1]_i_1_n_0 ;
wire \bvalid_cnt[2]_i_1_n_0 ;
wire bvalid_cnt_inc;
wire bvalid_cnt_inc11_out;
wire clr_bram_we;
wire clr_bram_we_cmb;
wire curr_awlen_reg_1_or_2;
wire curr_awlen_reg_1_or_20;
wire curr_awlen_reg_1_or_2_i_2_n_0;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire delay_aw_active_clr;
wire last_data_ack_mod;
wire p_18_out;
wire p_9_out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_aresetn_0;
wire [13:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire wr_addr_sm_cs;
(* RTL_KEEP = "yes" *) wire [2:0]wr_data_sm_cs;
zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO BID_FIFO
(.\GEN_AWREADY.axi_aresetn_d2_reg (axi_aresetn_d2),
.\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg (\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.aw_active(aw_active),
.axi_awaddr_full(axi_awaddr_full),
.axi_awid_pipe(axi_awid_pipe),
.axi_awlen_pipe_1_or_2(axi_awlen_pipe_1_or_2),
.\axi_bid_int_reg[0] (BID_FIFO_n_4),
.axi_bvalid_int_reg(s_axi_bvalid),
.axi_wdata_full_cmb114_out(axi_wdata_full_cmb114_out),
.axi_wr_burst(axi_wr_burst),
.bid_gets_fifo_load(bid_gets_fifo_load),
.bid_gets_fifo_load_d1(bid_gets_fifo_load_d1),
.bid_gets_fifo_load_d1_reg(BID_FIFO_n_1),
.bram_addr_ld_en(bram_addr_ld_en),
.bvalid_cnt(bvalid_cnt),
.bvalid_cnt_inc(bvalid_cnt_inc),
.\bvalid_cnt_reg[1] (bid_gets_fifo_load_d1_i_2_n_0),
.\bvalid_cnt_reg[2] (I_WRAP_BRST_n_20),
.\bvalid_cnt_reg[2]_0 (I_WRAP_BRST_n_19),
.curr_awlen_reg_1_or_2(curr_awlen_reg_1_or_2),
.last_data_ack_mod(last_data_ack_mod),
.out(wr_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn_0),
.s_axi_awid(s_axi_awid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.wr_addr_sm_cs(wr_addr_sm_cs));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[0]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h05051F1A))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2
(.I0(wr_data_sm_cs[1]),
.I1(axi_wr_burst_cmb0),
.I2(wr_data_sm_cs[0]),
.I3(axi_wdata_full_cmb114_out),
.I4(wr_data_sm_cs[2]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT4 #(
.INIT(16'h5515))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3
(.I0(I_WRAP_BRST_n_21),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.O(axi_wr_burst_cmb0));
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[1]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000554000555540))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2
(.I0(wr_data_sm_cs[1]),
.I1(s_axi_wlast),
.I2(axi_wdata_full_cmb114_out),
.I3(wr_data_sm_cs[0]),
.I4(wr_data_sm_cs[2]),
.I5(axi_wr_burst),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[2]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h44010001))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2
(.I0(wr_data_sm_cs[2]),
.I1(wr_data_sm_cs[1]),
.I2(axi_wdata_full_cmb114_out),
.I3(wr_data_sm_cs[0]),
.I4(s_axi_wvalid),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h7774777774744444))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[1]),
.I3(s_axi_wlast),
.I4(wr_data_sm_cs[0]),
.I5(s_axi_wvalid),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ),
.Q(wr_data_sm_cs[0]),
.R(s_axi_aresetn_0));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ),
.Q(wr_data_sm_cs[1]),
.R(s_axi_aresetn_0));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ),
.Q(wr_data_sm_cs[2]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_aresetn),
.Q(\I_RD_CHNL/axi_aresetn_d1 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\I_RD_CHNL/axi_aresetn_d1 ),
.Q(axi_aresetn_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\GEN_AWREADY.axi_aresetn_re_reg_i_1
(.I0(s_axi_aresetn),
.I1(\I_RD_CHNL/axi_aresetn_d1 ),
.O(axi_aresetn_re));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_re_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_aresetn_re),
.Q(axi_aresetn_re_reg),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFBFBFFFFFAA00))
\GEN_AWREADY.axi_awready_int_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(bram_addr_ld_en),
.I4(axi_aresetn_re_reg),
.I5(s_axi_awready),
.O(\GEN_AWREADY.axi_awready_int_i_1_n_0 ));
LUT6 #(
.INIT(64'h5444444400000000))
\GEN_AWREADY.axi_awready_int_i_2
(.I0(\GEN_AWREADY.axi_awready_int_i_3_n_0 ),
.I1(aw_active),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[2]),
.I5(s_axi_awvalid),
.O(\GEN_AWREADY.axi_awready_int_i_2_n_0 ));
LUT6 #(
.INIT(64'hAABABABABABABABA))
\GEN_AWREADY.axi_awready_int_i_3
(.I0(wr_addr_sm_cs),
.I1(I_WRAP_BRST_n_21),
.I2(last_data_ack_mod),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\GEN_AWREADY.axi_awready_int_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_awready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AWREADY.axi_awready_int_i_1_n_0 ),
.Q(s_axi_awready),
.R(s_axi_aresetn_0));
LUT1 #(
.INIT(2'h1))
\GEN_AW_DUAL.aw_active_i_1
(.I0(axi_aresetn_d2),
.O(\GEN_AW_DUAL.aw_active_reg_0 ));
LUT6 #(
.INIT(64'hFFFFF7FFFFFF0000))
\GEN_AW_DUAL.aw_active_i_2
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[0]),
.I2(wr_data_sm_cs[2]),
.I3(delay_aw_active_clr),
.I4(bram_addr_ld_en),
.I5(aw_active),
.O(\GEN_AW_DUAL.aw_active_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_DUAL.aw_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_DUAL.aw_active_i_2_n_0 ),
.Q(aw_active),
.R(\GEN_AW_DUAL.aw_active_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h80))
\GEN_AW_DUAL.last_data_ack_mod_i_1
(.I0(s_axi_wready),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.O(p_18_out));
FDRE #(
.INIT(1'b0))
\GEN_AW_DUAL.last_data_ack_mod_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_18_out),
.Q(last_data_ack_mod),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'h0010001000100000))
\GEN_AW_DUAL.wr_addr_sm_cs_i_1
(.I0(\GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ),
.I1(wr_addr_sm_cs),
.I2(s_axi_awvalid),
.I3(axi_awaddr_full),
.I4(I_WRAP_BRST_n_20),
.I5(aw_active),
.O(\GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000040))
\GEN_AW_DUAL.wr_addr_sm_cs_i_2
(.I0(I_WRAP_BRST_n_20),
.I1(last_data_ack_mod),
.I2(axi_awaddr_full),
.I3(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.I4(axi_awlen_pipe_1_or_2),
.I5(curr_awlen_reg_1_or_2),
.O(\GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ));
FDRE \GEN_AW_DUAL.wr_addr_sm_cs_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ),
.Q(wr_addr_sm_cs),
.R(\GEN_AW_DUAL.aw_active_reg_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[8]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[9]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[10]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[11]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[12]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[13]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[0]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[1]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[2]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[3]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[4]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[5]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[6]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[7]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.R(1'b0));
LUT5 #(
.INIT(32'h4000EA00))
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(s_axi_aresetn),
.I4(bram_addr_ld_en),
.O(\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ),
.Q(axi_awaddr_full),
.R(1'b0));
LUT6 #(
.INIT(64'hBF00BF00BF00FF40))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.I4(s_axi_awburst[0]),
.I5(s_axi_awburst[1]),
.O(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ),
.Q(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awburst[0]),
.Q(axi_awburst_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awburst[1]),
.Q(axi_awburst_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid),
.Q(axi_awid_pipe),
.R(1'b0));
LUT3 #(
.INIT(8'h40))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.O(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0002))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1
(.I0(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ),
.I1(s_axi_awlen[3]),
.I2(s_axi_awlen[2]),
.I3(s_axi_awlen[1]),
.O(p_9_out));
LUT4 #(
.INIT(16'h0001))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2
(.I0(s_axi_awlen[4]),
.I1(s_axi_awlen[6]),
.I2(s_axi_awlen[7]),
.I3(s_axi_awlen[5]),
.O(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(p_9_out),
.Q(axi_awlen_pipe_1_or_2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[0]),
.Q(axi_awlen_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[1]),
.Q(axi_awlen_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[2]),
.Q(axi_awlen_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[3]),
.Q(axi_awlen_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[4]),
.Q(axi_awlen_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[5]),
.Q(axi_awlen_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[6]),
.Q(axi_awlen_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[7]),
.Q(axi_awlen_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(1'b1),
.Q(axi_awsize_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0
(.I0(bram_addr_a[4]),
.I1(bram_addr_a[1]),
.I2(bram_addr_a[0]),
.I3(bram_addr_a[2]),
.I4(bram_addr_a[3]),
.I5(bram_addr_a[5]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hF7FFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0
(.I0(bram_addr_a[6]),
.I1(bram_addr_a[4]),
.I2(I_WRAP_BRST_n_17),
.I3(bram_addr_a[5]),
.I4(bram_addr_a[7]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'h1000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[0]),
.I3(s_axi_wvalid),
.O(bram_addr_inc));
LUT4 #(
.INIT(16'h1000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[0]),
.I3(wr_data_sm_cs[1]),
.O(bram_addr_rst_cmb));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_8),
.Q(bram_addr_a[8]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_7),
.Q(bram_addr_a[9]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[10]),
.Q(bram_addr_a[10]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[11]),
.Q(bram_addr_a[11]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[12]),
.Q(bram_addr_a[12]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[13]),
.Q(bram_addr_a[13]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_16),
.Q(bram_addr_a[0]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_15),
.Q(bram_addr_a[1]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_14),
.Q(bram_addr_a[2]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_13),
.Q(bram_addr_a[3]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_12),
.Q(bram_addr_a[4]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_11),
.Q(bram_addr_a[5]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_10),
.Q(bram_addr_a[6]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_9),
.Q(bram_addr_a[7]),
.R(I_WRAP_BRST_n_0));
LUT5 #(
.INIT(32'h15FF1500))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.I3(wr_data_sm_cs[2]),
.I4(axi_wready_int_mod_i_3_n_0),
.O(axi_wdata_full_cmb));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wdata_full_cmb),
.Q(axi_wdata_full_reg),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'h4777477444444444))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[1]),
.I3(wr_data_sm_cs[0]),
.I4(axi_wdata_full_cmb114_out),
.I5(s_axi_wvalid),
.O(bram_en_cmb));
LUT3 #(
.INIT(8'h15))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bram_en_cmb),
.Q(bram_en_a),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'h0010001000101110))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1
(.I0(wr_data_sm_cs[0]),
.I1(wr_data_sm_cs[1]),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ),
.I3(wr_data_sm_cs[2]),
.I4(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I5(axi_wr_burst),
.O(clr_bram_we_cmb));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h80))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2
(.I0(axi_wdata_full_cmb114_out),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(clr_bram_we_cmb),
.Q(clr_bram_we),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'hFEAAFEFF02AA0200))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ),
.I1(axi_wr_burst),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I3(wr_data_sm_cs[2]),
.I4(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ),
.I5(delay_aw_active_clr),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ));
LUT5 #(
.INIT(32'h0000222E))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2
(.I0(s_axi_wlast),
.I1(wr_data_sm_cs[2]),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I3(wr_data_sm_cs[0]),
.I4(wr_data_sm_cs[1]),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ));
LUT6 #(
.INIT(64'h8B338B0088008800))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3
(.I0(delay_aw_active_clr),
.I1(wr_data_sm_cs[1]),
.I2(axi_wr_burst_cmb0),
.I3(wr_data_sm_cs[0]),
.I4(axi_wdata_full_cmb114_out),
.I5(bvalid_cnt_inc11_out),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4
(.I0(s_axi_wvalid),
.I1(s_axi_wlast),
.O(bvalid_cnt_inc11_out));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ),
.Q(delay_aw_active_clr),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[0].bram_wrdata_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[0]),
.Q(bram_wrdata_a[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[10].bram_wrdata_int_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[10]),
.Q(bram_wrdata_a[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[11].bram_wrdata_int_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[11]),
.Q(bram_wrdata_a[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[12].bram_wrdata_int_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[12]),
.Q(bram_wrdata_a[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[13].bram_wrdata_int_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[13]),
.Q(bram_wrdata_a[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[14].bram_wrdata_int_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[14]),
.Q(bram_wrdata_a[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[15].bram_wrdata_int_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[15]),
.Q(bram_wrdata_a[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[16].bram_wrdata_int_reg[16]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[16]),
.Q(bram_wrdata_a[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[17].bram_wrdata_int_reg[17]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[17]),
.Q(bram_wrdata_a[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[18].bram_wrdata_int_reg[18]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[18]),
.Q(bram_wrdata_a[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[19].bram_wrdata_int_reg[19]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[19]),
.Q(bram_wrdata_a[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[1].bram_wrdata_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[1]),
.Q(bram_wrdata_a[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[20].bram_wrdata_int_reg[20]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[20]),
.Q(bram_wrdata_a[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[21].bram_wrdata_int_reg[21]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[21]),
.Q(bram_wrdata_a[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[22].bram_wrdata_int_reg[22]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[22]),
.Q(bram_wrdata_a[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[23].bram_wrdata_int_reg[23]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[23]),
.Q(bram_wrdata_a[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[24].bram_wrdata_int_reg[24]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[24]),
.Q(bram_wrdata_a[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[25].bram_wrdata_int_reg[25]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[25]),
.Q(bram_wrdata_a[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[26].bram_wrdata_int_reg[26]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[26]),
.Q(bram_wrdata_a[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[27].bram_wrdata_int_reg[27]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[27]),
.Q(bram_wrdata_a[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[28].bram_wrdata_int_reg[28]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[28]),
.Q(bram_wrdata_a[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[29].bram_wrdata_int_reg[29]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[29]),
.Q(bram_wrdata_a[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[2].bram_wrdata_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[2]),
.Q(bram_wrdata_a[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[30].bram_wrdata_int_reg[30]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[30]),
.Q(bram_wrdata_a[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[31].bram_wrdata_int_reg[31]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[31]),
.Q(bram_wrdata_a[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[3].bram_wrdata_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[3]),
.Q(bram_wrdata_a[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[4].bram_wrdata_int_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[4]),
.Q(bram_wrdata_a[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[5].bram_wrdata_int_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[5]),
.Q(bram_wrdata_a[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[6].bram_wrdata_int_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[6]),
.Q(bram_wrdata_a[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[7].bram_wrdata_int_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[7]),
.Q(bram_wrdata_a[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[8].bram_wrdata_int_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[8]),
.Q(bram_wrdata_a[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[9].bram_wrdata_int_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[9]),
.Q(bram_wrdata_a[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hD0FF))
\GEN_WR_NO_ECC.bram_we_int[3]_i_1
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.I2(clr_bram_we),
.I3(s_axi_aresetn),
.O(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\GEN_WR_NO_ECC.bram_we_int[3]_i_2
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.O(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[0]),
.Q(bram_we_a[0]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[1]),
.Q(bram_we_a[1]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[2]),
.Q(bram_we_a[2]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[3]),
.Q(bram_we_a[3]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst I_WRAP_BRST
(.D({bram_addr_ld,I_WRAP_BRST_n_7,I_WRAP_BRST_n_8,I_WRAP_BRST_n_9,I_WRAP_BRST_n_10,I_WRAP_BRST_n_11,I_WRAP_BRST_n_12,I_WRAP_BRST_n_13,I_WRAP_BRST_n_14,I_WRAP_BRST_n_15,I_WRAP_BRST_n_16}),
.E(I_WRAP_BRST_n_2),
.\GEN_AWREADY.axi_aresetn_d2_reg (axi_aresetn_d2),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg (\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] (\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] (I_WRAP_BRST_n_17),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 (\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0 ),
.Q(axi_awlen_pipe[3:0]),
.SR(I_WRAP_BRST_n_0),
.aw_active(aw_active),
.axi_awaddr_full(axi_awaddr_full),
.axi_awlen_pipe_1_or_2(axi_awlen_pipe_1_or_2),
.axi_awsize_pipe(axi_awsize_pipe),
.bram_addr_a(bram_addr_a[9:0]),
.bram_addr_inc(bram_addr_inc),
.bram_addr_ld_en(bram_addr_ld_en),
.bram_addr_ld_en_mod(bram_addr_ld_en_mod),
.bram_addr_rst_cmb(bram_addr_rst_cmb),
.bvalid_cnt(bvalid_cnt),
.curr_awlen_reg_1_or_2(curr_awlen_reg_1_or_2),
.curr_fixed_burst(curr_fixed_burst),
.curr_fixed_burst_reg(curr_fixed_burst_reg),
.curr_fixed_burst_reg_reg(I_WRAP_BRST_n_24),
.curr_wrap_burst(curr_wrap_burst),
.curr_wrap_burst_reg(curr_wrap_burst_reg),
.curr_wrap_burst_reg_reg(I_WRAP_BRST_n_25),
.last_data_ack_mod(last_data_ack_mod),
.out(wr_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_aresetn_0(s_axi_aresetn_0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen[3:0]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wvalid(s_axi_wvalid),
.\save_init_bram_addr_ld_reg[15]_0 (I_WRAP_BRST_n_19),
.\save_init_bram_addr_ld_reg[15]_1 (I_WRAP_BRST_n_20),
.\save_init_bram_addr_ld_reg[15]_2 (I_WRAP_BRST_n_21),
.wr_addr_sm_cs(wr_addr_sm_cs),
.\wrap_burst_total_reg[0]_0 (I_WRAP_BRST_n_22),
.\wrap_burst_total_reg[2]_0 (I_WRAP_BRST_n_23));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(BID_FIFO_n_4),
.Q(s_axi_bid),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'hAAAAAAAAAAAA8A88))
axi_bvalid_int_i_1
(.I0(s_axi_aresetn),
.I1(bvalid_cnt_inc),
.I2(BID_FIFO_n_1),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[2]),
.I5(bvalid_cnt[1]),
.O(axi_bvalid_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_bvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_bvalid_int_i_1_n_0),
.Q(s_axi_bvalid),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
axi_wr_burst_i_1
(.I0(axi_wr_burst_cmb),
.I1(axi_wr_burst_i_3_n_0),
.I2(axi_wr_burst),
.O(axi_wr_burst_i_1_n_0));
LUT5 #(
.INIT(32'h3088FCBB))
axi_wr_burst_i_2
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[1]),
.I2(axi_wr_burst_cmb0),
.I3(wr_data_sm_cs[0]),
.I4(s_axi_wlast),
.O(axi_wr_burst_cmb));
LUT6 #(
.INIT(64'h00000000AAAAA222))
axi_wr_burst_i_3
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[0]),
.I2(axi_wr_burst_cmb0),
.I3(s_axi_wlast),
.I4(wr_data_sm_cs[1]),
.I5(wr_data_sm_cs[2]),
.O(axi_wr_burst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_wr_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wr_burst_i_1_n_0),
.Q(axi_wr_burst),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'hEA00EAFF00000000))
axi_wready_int_mod_i_1
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.I3(wr_data_sm_cs[2]),
.I4(axi_wready_int_mod_i_3_n_0),
.I5(s_axi_aresetn),
.O(axi_wready_int_mod_i_1_n_0));
LUT5 #(
.INIT(32'hF8F9F0F0))
axi_wready_int_mod_i_3
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[0]),
.I2(axi_wdata_full_reg),
.I3(axi_wdata_full_cmb114_out),
.I4(s_axi_wvalid),
.O(axi_wready_int_mod_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_wready_int_mod_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wready_int_mod_i_1_n_0),
.Q(s_axi_wready),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hEF))
bid_gets_fifo_load_d1_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.O(bid_gets_fifo_load_d1_i_2_n_0));
FDRE #(
.INIT(1'b0))
bid_gets_fifo_load_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bid_gets_fifo_load),
.Q(bid_gets_fifo_load_d1),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'h95956A6A95956AAA))
\bvalid_cnt[0]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hD5D5BFBF2A2A4000))
\bvalid_cnt[1]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hD52AFF00FF00BF00))
\bvalid_cnt[2]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[0]_i_1_n_0 ),
.Q(bvalid_cnt[0]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[1]_i_1_n_0 ),
.Q(bvalid_cnt[1]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[2]_i_1_n_0 ),
.Q(bvalid_cnt[2]),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'h0000000000000151))
curr_awlen_reg_1_or_2_i_1
(.I0(I_WRAP_BRST_n_23),
.I1(s_axi_awlen[2]),
.I2(axi_awaddr_full),
.I3(axi_awlen_pipe[2]),
.I4(I_WRAP_BRST_n_22),
.I5(curr_awlen_reg_1_or_2_i_2_n_0),
.O(curr_awlen_reg_1_or_20));
LUT6 #(
.INIT(64'hF5F5F5F5F5F5F5C5))
curr_awlen_reg_1_or_2_i_2
(.I0(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ),
.I1(axi_awlen_pipe[5]),
.I2(axi_awaddr_full),
.I3(axi_awlen_pipe[6]),
.I4(axi_awlen_pipe[7]),
.I5(axi_awlen_pipe[4]),
.O(curr_awlen_reg_1_or_2_i_2_n_0));
FDRE #(
.INIT(1'b0))
curr_awlen_reg_1_or_2_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_awlen_reg_1_or_20),
.Q(curr_awlen_reg_1_or_2),
.R(s_axi_aresetn_0));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'h00053305))
curr_fixed_burst_reg_i_2
(.I0(s_axi_awburst[1]),
.I1(axi_awburst_pipe[1]),
.I2(s_axi_awburst[0]),
.I3(axi_awaddr_full),
.I4(axi_awburst_pipe[0]),
.O(curr_fixed_burst));
FDRE #(
.INIT(1'b0))
curr_fixed_burst_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_WRAP_BRST_n_24),
.Q(curr_fixed_burst_reg),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'h000ACC0A))
curr_wrap_burst_reg_i_2
(.I0(s_axi_awburst[1]),
.I1(axi_awburst_pipe[1]),
.I2(s_axi_awburst[0]),
.I3(axi_awaddr_full),
.I4(axi_awburst_pipe[0]),
.O(curr_wrap_burst));
FDRE #(
.INIT(1'b0))
curr_wrap_burst_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_WRAP_BRST_n_25),
.Q(curr_wrap_burst_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "wrap_brst" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst
(SR,
bram_addr_ld_en_mod,
E,
D,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ,
bram_addr_ld_en,
\save_init_bram_addr_ld_reg[15]_0 ,
\save_init_bram_addr_ld_reg[15]_1 ,
\save_init_bram_addr_ld_reg[15]_2 ,
\wrap_burst_total_reg[0]_0 ,
\wrap_burst_total_reg[2]_0 ,
curr_fixed_burst_reg_reg,
curr_wrap_burst_reg_reg,
curr_fixed_burst_reg,
bram_addr_inc,
bram_addr_rst_cmb,
s_axi_aresetn,
out,
s_axi_wvalid,
bram_addr_a,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ,
axi_awaddr_full,
s_axi_awaddr,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ,
\GEN_AWREADY.axi_aresetn_d2_reg ,
wr_addr_sm_cs,
last_data_ack_mod,
bvalid_cnt,
aw_active,
s_axi_awvalid,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ,
axi_awlen_pipe_1_or_2,
curr_awlen_reg_1_or_2,
curr_wrap_burst_reg,
Q,
s_axi_awlen,
axi_awsize_pipe,
curr_fixed_burst,
curr_wrap_burst,
s_axi_aresetn_0,
s_axi_aclk);
output [0:0]SR;
output bram_addr_ld_en_mod;
output [0:0]E;
output [13:0]D;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
output bram_addr_ld_en;
output \save_init_bram_addr_ld_reg[15]_0 ;
output \save_init_bram_addr_ld_reg[15]_1 ;
output \save_init_bram_addr_ld_reg[15]_2 ;
output \wrap_burst_total_reg[0]_0 ;
output \wrap_burst_total_reg[2]_0 ;
output curr_fixed_burst_reg_reg;
output curr_wrap_burst_reg_reg;
input curr_fixed_burst_reg;
input bram_addr_inc;
input bram_addr_rst_cmb;
input s_axi_aresetn;
input [2:0]out;
input s_axi_wvalid;
input [9:0]bram_addr_a;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
input axi_awaddr_full;
input [13:0]s_axi_awaddr;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input wr_addr_sm_cs;
input last_data_ack_mod;
input [2:0]bvalid_cnt;
input aw_active;
input s_axi_awvalid;
input \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
input axi_awlen_pipe_1_or_2;
input curr_awlen_reg_1_or_2;
input curr_wrap_burst_reg;
input [3:0]Q;
input [3:0]s_axi_awlen;
input [0:0]axi_awsize_pipe;
input curr_fixed_burst;
input curr_wrap_burst;
input s_axi_aresetn_0;
input s_axi_aclk;
wire [13:0]D;
wire [0:0]E;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ;
wire [3:0]Q;
wire [0:0]SR;
wire aw_active;
wire axi_awaddr_full;
wire axi_awlen_pipe_1_or_2;
wire [0:0]axi_awsize_pipe;
wire [9:0]bram_addr_a;
wire bram_addr_inc;
wire [9:1]bram_addr_ld;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_addr_rst_cmb;
wire [2:0]bvalid_cnt;
wire curr_awlen_reg_1_or_2;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_fixed_burst_reg_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire curr_wrap_burst_reg_reg;
wire last_data_ack_mod;
wire [2:0]out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_aresetn_0;
wire [13:0]s_axi_awaddr;
wire [3:0]s_axi_awlen;
wire s_axi_awvalid;
wire s_axi_wvalid;
wire [15:3]save_init_bram_addr_ld;
wire \save_init_bram_addr_ld[3]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[4]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[5]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld_reg[15]_0 ;
wire \save_init_bram_addr_ld_reg[15]_1 ;
wire \save_init_bram_addr_ld_reg[15]_2 ;
wire wr_addr_sm_cs;
wire [2:0]wrap_burst_total;
wire \wrap_burst_total[0]_i_1__0_n_0 ;
wire \wrap_burst_total[0]_i_2__0_n_0 ;
wire \wrap_burst_total[0]_i_4__0_n_0 ;
wire \wrap_burst_total[0]_i_5_n_0 ;
wire \wrap_burst_total[1]_i_1__0_n_0 ;
wire \wrap_burst_total[2]_i_1__0_n_0 ;
wire \wrap_burst_total[2]_i_2__0_n_0 ;
wire \wrap_burst_total_reg[0]_0 ;
wire \wrap_burst_total_reg[2]_0 ;
LUT6 #(
.INIT(64'hBB8BBBBB88B88888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1
(.I0(bram_addr_ld[8]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[6]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(bram_addr_a[7]),
.I5(bram_addr_a[8]),
.O(D[8]));
LUT6 #(
.INIT(64'hAAABAAAAAAAAAAAA))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1
(.I0(bram_addr_ld_en_mod),
.I1(curr_fixed_burst_reg),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(s_axi_wvalid),
.O(E));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2
(.I0(bram_addr_ld[9]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[9]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ),
.I4(bram_addr_a[8]),
.O(D[9]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1
(.I0(save_init_bram_addr_ld[12]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[10]),
.O(D[10]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1
(.I0(save_init_bram_addr_ld[13]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[11]),
.O(D[11]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1
(.I0(save_init_bram_addr_ld[14]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[12]),
.O(D[12]));
LUT5 #(
.INIT(32'h4500FFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0
(.I0(bram_addr_ld_en_mod),
.I1(curr_fixed_burst_reg),
.I2(bram_addr_inc),
.I3(bram_addr_rst_cmb),
.I4(s_axi_aresetn),
.O(SR));
LUT6 #(
.INIT(64'hAAABAAAAAAAAAAAA))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(s_axi_wvalid),
.O(bram_addr_ld_en_mod));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3
(.I0(save_init_bram_addr_ld[15]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[13]),
.O(D[13]));
LUT6 #(
.INIT(64'h55555555FFFFFFDF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6
(.I0(curr_wrap_burst_reg),
.I1(wrap_burst_total[1]),
.I2(wrap_burst_total[2]),
.I3(wrap_burst_total[0]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ));
LUT6 #(
.INIT(64'h000000008F00C000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8
(.I0(bram_addr_a[2]),
.I1(bram_addr_a[1]),
.I2(wrap_burst_total[1]),
.I3(bram_addr_a[0]),
.I4(wrap_burst_total[0]),
.I5(wrap_burst_total[2]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0 ));
LUT6 #(
.INIT(64'hB800B800B800FFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1
(.I0(\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.I1(axi_awaddr_full),
.I2(s_axi_awaddr[0]),
.I3(bram_addr_ld_en),
.I4(bram_addr_ld_en_mod),
.I5(bram_addr_a[0]),
.O(D[0]));
LUT4 #(
.INIT(16'h8BB8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1
(.I0(bram_addr_ld[1]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[1]),
.I3(bram_addr_a[0]),
.O(D[1]));
LUT5 #(
.INIT(32'h8BB8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1
(.I0(bram_addr_ld[2]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[2]),
.I3(bram_addr_a[0]),
.I4(bram_addr_a[1]),
.O(D[2]));
LUT6 #(
.INIT(64'h8BB8B8B8B8B8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1
(.I0(bram_addr_ld[3]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[3]),
.I3(bram_addr_a[2]),
.I4(bram_addr_a[0]),
.I5(bram_addr_a[1]),
.O(D[3]));
LUT4 #(
.INIT(16'hB88B))
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1
(.I0(bram_addr_ld[4]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[4]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.O(D[4]));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1
(.I0(bram_addr_ld[5]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[5]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I4(bram_addr_a[4]),
.O(D[5]));
LUT6 #(
.INIT(64'hB8B88BB8B8B8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1
(.I0(bram_addr_ld[6]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[6]),
.I3(bram_addr_a[4]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I5(bram_addr_a[5]),
.O(D[6]));
LUT4 #(
.INIT(16'h7FFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0
(.I0(bram_addr_a[1]),
.I1(bram_addr_a[0]),
.I2(bram_addr_a[2]),
.I3(bram_addr_a[3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1
(.I0(bram_addr_ld[7]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[7]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(bram_addr_a[6]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT4 #(
.INIT(16'h00E2))
curr_fixed_burst_reg_i_1__0
(.I0(curr_fixed_burst_reg),
.I1(bram_addr_ld_en),
.I2(curr_fixed_burst),
.I3(SR),
.O(curr_fixed_burst_reg_reg));
LUT4 #(
.INIT(16'h00E2))
curr_wrap_burst_reg_i_1__0
(.I0(curr_wrap_burst_reg),
.I1(bram_addr_ld_en),
.I2(curr_wrap_burst),
.I3(SR),
.O(curr_wrap_burst_reg_reg));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[10]_i_1
(.I0(save_init_bram_addr_ld[10]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[8]),
.O(bram_addr_ld[8]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[11]_i_1
(.I0(save_init_bram_addr_ld[11]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[9]),
.O(bram_addr_ld[9]));
LUT6 #(
.INIT(64'h0808080808AA0808))
\save_init_bram_addr_ld[15]_i_1
(.I0(\GEN_AWREADY.axi_aresetn_d2_reg ),
.I1(\save_init_bram_addr_ld_reg[15]_0 ),
.I2(wr_addr_sm_cs),
.I3(\save_init_bram_addr_ld_reg[15]_1 ),
.I4(last_data_ack_mod),
.I5(\save_init_bram_addr_ld_reg[15]_2 ),
.O(bram_addr_ld_en));
LUT6 #(
.INIT(64'h007F007F007F0000))
\save_init_bram_addr_ld[15]_i_2
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.I3(aw_active),
.I4(axi_awaddr_full),
.I5(s_axi_awvalid),
.O(\save_init_bram_addr_ld_reg[15]_0 ));
LUT3 #(
.INIT(8'h80))
\save_init_bram_addr_ld[15]_i_3
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.O(\save_init_bram_addr_ld_reg[15]_1 ));
LUT4 #(
.INIT(16'hFFFD))
\save_init_bram_addr_ld[15]_i_4
(.I0(axi_awaddr_full),
.I1(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ),
.I2(axi_awlen_pipe_1_or_2),
.I3(curr_awlen_reg_1_or_2),
.O(\save_init_bram_addr_ld_reg[15]_2 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[3]_i_1
(.I0(\save_init_bram_addr_ld[3]_i_2__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[1]),
.O(bram_addr_ld[1]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT4 #(
.INIT(16'hC80C))
\save_init_bram_addr_ld[3]_i_2__0
(.I0(wrap_burst_total[0]),
.I1(save_init_bram_addr_ld[3]),
.I2(wrap_burst_total[1]),
.I3(wrap_burst_total[2]),
.O(\save_init_bram_addr_ld[3]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[4]_i_1
(.I0(\save_init_bram_addr_ld[4]_i_2__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[2]),
.O(bram_addr_ld[2]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT4 #(
.INIT(16'hA28A))
\save_init_bram_addr_ld[4]_i_2__0
(.I0(save_init_bram_addr_ld[4]),
.I1(wrap_burst_total[0]),
.I2(wrap_burst_total[2]),
.I3(wrap_burst_total[1]),
.O(\save_init_bram_addr_ld[4]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h8F808F8F8F808080))
\save_init_bram_addr_ld[5]_i_1
(.I0(save_init_bram_addr_ld[5]),
.I1(\save_init_bram_addr_ld[5]_i_2__0_n_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I3(\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.I4(axi_awaddr_full),
.I5(s_axi_awaddr[3]),
.O(bram_addr_ld[3]));
LUT3 #(
.INIT(8'hFB))
\save_init_bram_addr_ld[5]_i_2__0
(.I0(wrap_burst_total[0]),
.I1(wrap_burst_total[2]),
.I2(wrap_burst_total[1]),
.O(\save_init_bram_addr_ld[5]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[6]_i_1
(.I0(save_init_bram_addr_ld[6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[4]),
.O(bram_addr_ld[4]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[7]_i_1
(.I0(save_init_bram_addr_ld[7]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[5]),
.O(bram_addr_ld[5]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[8]_i_1
(.I0(save_init_bram_addr_ld[8]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[6]),
.O(bram_addr_ld[6]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[9]_i_1
(.I0(save_init_bram_addr_ld[9]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[7]),
.O(bram_addr_ld[7]));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[10]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[8]),
.Q(save_init_bram_addr_ld[10]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[11]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[9]),
.Q(save_init_bram_addr_ld[11]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[10]),
.Q(save_init_bram_addr_ld[12]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[11]),
.Q(save_init_bram_addr_ld[13]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[12]),
.Q(save_init_bram_addr_ld[14]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[13]),
.Q(save_init_bram_addr_ld[15]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[3]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[1]),
.Q(save_init_bram_addr_ld[3]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[4]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[2]),
.Q(save_init_bram_addr_ld[4]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[5]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[3]),
.Q(save_init_bram_addr_ld[5]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[6]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[4]),
.Q(save_init_bram_addr_ld[6]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[7]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[5]),
.Q(save_init_bram_addr_ld[7]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[8]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[6]),
.Q(save_init_bram_addr_ld[8]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[9]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[7]),
.Q(save_init_bram_addr_ld[9]),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'hF909090900000000))
\wrap_burst_total[0]_i_1__0
(.I0(\wrap_burst_total[0]_i_2__0_n_0 ),
.I1(\wrap_burst_total_reg[0]_0 ),
.I2(\wrap_burst_total[0]_i_4__0_n_0 ),
.I3(Q[1]),
.I4(Q[2]),
.I5(\wrap_burst_total[0]_i_5_n_0 ),
.O(\wrap_burst_total[0]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_2__0
(.I0(Q[2]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[2]),
.O(\wrap_burst_total[0]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_3__0
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[1]),
.O(\wrap_burst_total_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT2 #(
.INIT(4'h2))
\wrap_burst_total[0]_i_4__0
(.I0(axi_awaddr_full),
.I1(axi_awsize_pipe),
.O(\wrap_burst_total[0]_i_4__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT5 #(
.INIT(32'h000ACC0A))
\wrap_burst_total[0]_i_5
(.I0(s_axi_awlen[0]),
.I1(Q[0]),
.I2(s_axi_awlen[3]),
.I3(axi_awaddr_full),
.I4(Q[3]),
.O(\wrap_burst_total[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'h000008F3))
\wrap_burst_total[1]_i_1__0
(.I0(Q[2]),
.I1(axi_awaddr_full),
.I2(axi_awsize_pipe),
.I3(\wrap_burst_total_reg[2]_0 ),
.I4(\wrap_burst_total[2]_i_2__0_n_0 ),
.O(\wrap_burst_total[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h5000000044004400))
\wrap_burst_total[2]_i_1__0
(.I0(\wrap_burst_total[2]_i_2__0_n_0 ),
.I1(s_axi_awlen[2]),
.I2(Q[2]),
.I3(\wrap_burst_total_reg[2]_0 ),
.I4(axi_awsize_pipe),
.I5(axi_awaddr_full),
.O(\wrap_burst_total[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'h335FFF5F))
\wrap_burst_total[2]_i_2__0
(.I0(s_axi_awlen[1]),
.I1(Q[1]),
.I2(s_axi_awlen[0]),
.I3(axi_awaddr_full),
.I4(Q[0]),
.O(\wrap_burst_total[2]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[2]_i_3__0
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[3]),
.O(\wrap_burst_total_reg[2]_0 ));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[0]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[0]_i_1__0_n_0 ),
.Q(wrap_burst_total[0]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[1]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[1]_i_1__0_n_0 ),
.Q(wrap_burst_total[1]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[2]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[2]_i_1__0_n_0 ),
.Q(wrap_burst_total[2]),
.R(s_axi_aresetn_0));
endmodule
(* ORIG_REF_NAME = "wrap_brst" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0
(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ,
SR,
\wrap_burst_total_reg[0]_0 ,
\wrap_burst_total_reg[0]_1 ,
\wrap_burst_total_reg[0]_2 ,
\wrap_burst_total_reg[0]_3 ,
E,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ,
D,
bram_addr_ld_en,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ,
\rd_data_sm_cs_reg[1] ,
\save_init_bram_addr_ld_reg[15]_0 ,
\save_init_bram_addr_ld_reg[15]_1 ,
Q,
axi_rvalid_int_reg,
s_axi_rready,
end_brst_rd,
brst_zero,
s_axi_aresetn,
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ,
axi_arsize_pipe,
s_axi_arlen,
axi_araddr_full,
curr_fixed_burst_reg,
s_axi_araddr,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ,
curr_wrap_burst_reg,
axi_rd_burst_two_reg,
axi_rd_burst,
axi_aresetn_d2,
last_bram_addr,
rd_addr_sm_cs,
s_axi_arvalid,
no_ar_ack,
pend_rd_op,
ar_active,
axi_b2b_brst,
axi_arsize_pipe_max,
disable_b2b_brst,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ,
axi_arlen_pipe_1_or_2,
s_axi_aclk);
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
output [0:0]SR;
output \wrap_burst_total_reg[0]_0 ;
output \wrap_burst_total_reg[0]_1 ;
output \wrap_burst_total_reg[0]_2 ;
output \wrap_burst_total_reg[0]_3 ;
output [1:0]E;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ;
output [13:0]D;
output bram_addr_ld_en;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
output \rd_data_sm_cs_reg[1] ;
output \save_init_bram_addr_ld_reg[15]_0 ;
output \save_init_bram_addr_ld_reg[15]_1 ;
input [3:0]Q;
input axi_rvalid_int_reg;
input s_axi_rready;
input end_brst_rd;
input brst_zero;
input s_axi_aresetn;
input [3:0]\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ;
input [0:0]axi_arsize_pipe;
input [3:0]s_axi_arlen;
input axi_araddr_full;
input curr_fixed_burst_reg;
input [13:0]s_axi_araddr;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
input [9:0]\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ;
input curr_wrap_burst_reg;
input axi_rd_burst_two_reg;
input axi_rd_burst;
input axi_aresetn_d2;
input last_bram_addr;
input rd_addr_sm_cs;
input s_axi_arvalid;
input no_ar_ack;
input pend_rd_op;
input ar_active;
input axi_b2b_brst;
input axi_arsize_pipe_max;
input disable_b2b_brst;
input \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ;
input axi_arlen_pipe_1_or_2;
input s_axi_aclk;
wire [13:0]D;
wire [1:0]E;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ;
wire [3:0]\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ;
wire [9:0]\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
wire [3:0]Q;
wire [0:0]SR;
wire ar_active;
wire axi_araddr_full;
wire axi_aresetn_d2;
wire axi_arlen_pipe_1_or_2;
wire [0:0]axi_arsize_pipe;
wire axi_arsize_pipe_max;
wire axi_b2b_brst;
wire axi_rd_burst;
wire axi_rd_burst_two_reg;
wire axi_rvalid_int_reg;
wire bram_addr_ld_en;
wire brst_zero;
wire curr_fixed_burst_reg;
wire curr_wrap_burst_reg;
wire disable_b2b_brst;
wire end_brst_rd;
wire last_bram_addr;
wire no_ar_ack;
wire pend_rd_op;
wire rd_addr_sm_cs;
wire \rd_data_sm_cs_reg[1] ;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire s_axi_aresetn;
wire [3:0]s_axi_arlen;
wire s_axi_arvalid;
wire s_axi_rready;
wire \save_init_bram_addr_ld[10]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[11]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[15]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[15]_i_3__0_n_0 ;
wire \save_init_bram_addr_ld[3]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[3]_i_2_n_0 ;
wire \save_init_bram_addr_ld[4]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[4]_i_2_n_0 ;
wire \save_init_bram_addr_ld[5]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[5]_i_2_n_0 ;
wire \save_init_bram_addr_ld[6]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[7]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[8]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[9]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld_reg[15]_0 ;
wire \save_init_bram_addr_ld_reg[15]_1 ;
wire \save_init_bram_addr_ld_reg_n_0_[10] ;
wire \save_init_bram_addr_ld_reg_n_0_[11] ;
wire \save_init_bram_addr_ld_reg_n_0_[12] ;
wire \save_init_bram_addr_ld_reg_n_0_[13] ;
wire \save_init_bram_addr_ld_reg_n_0_[14] ;
wire \save_init_bram_addr_ld_reg_n_0_[15] ;
wire \save_init_bram_addr_ld_reg_n_0_[3] ;
wire \save_init_bram_addr_ld_reg_n_0_[4] ;
wire \save_init_bram_addr_ld_reg_n_0_[5] ;
wire \save_init_bram_addr_ld_reg_n_0_[6] ;
wire \save_init_bram_addr_ld_reg_n_0_[7] ;
wire \save_init_bram_addr_ld_reg_n_0_[8] ;
wire \save_init_bram_addr_ld_reg_n_0_[9] ;
wire \wrap_burst_total[0]_i_1_n_0 ;
wire \wrap_burst_total[0]_i_5__0_n_0 ;
wire \wrap_burst_total[1]_i_1_n_0 ;
wire \wrap_burst_total[2]_i_1_n_0 ;
wire \wrap_burst_total[2]_i_2_n_0 ;
wire \wrap_burst_total_reg[0]_0 ;
wire \wrap_burst_total_reg[0]_1 ;
wire \wrap_burst_total_reg[0]_2 ;
wire \wrap_burst_total_reg[0]_3 ;
wire \wrap_burst_total_reg_n_0_[0] ;
wire \wrap_burst_total_reg_n_0_[1] ;
wire \wrap_burst_total_reg_n_0_[2] ;
LUT6 #(
.INIT(64'hDF20FFFFDF200000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [7]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [8]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I5(\save_init_bram_addr_ld[10]_i_1__0_n_0 ),
.O(D[8]));
LUT3 #(
.INIT(8'h5D))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I2(curr_fixed_burst_reg),
.O(E[0]));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [9]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [8]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[11]_i_1__0_n_0 ),
.O(D[9]));
LUT6 #(
.INIT(64'hE0F0E0FFE0F0E0F0))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ),
.I2(\rd_data_sm_cs_reg[1] ),
.I3(Q[1]),
.I4(Q[3]),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5
(.I0(axi_rd_burst_two_reg),
.I1(Q[0]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0D00000000000000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6
(.I0(end_brst_rd),
.I1(axi_b2b_brst),
.I2(brst_zero),
.I3(axi_rvalid_int_reg),
.I4(s_axi_rready),
.I5(Q[0]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[12] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[10]),
.O(D[10]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[13] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[11]),
.O(D[11]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[14] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[12]),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT1 #(
.INIT(2'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.O(E[1]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[15] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[13]),
.O(D[13]));
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ));
LUT5 #(
.INIT(32'h88A80000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0 ),
.I2(\save_init_bram_addr_ld[5]_i_2_n_0 ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(curr_wrap_burst_reg),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'h000000008F00A000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I2(\wrap_burst_total_reg_n_0_[1] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I4(\wrap_burst_total_reg_n_0_[0] ),
.I5(\wrap_burst_total_reg_n_0_[2] ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h00000000A808FD5D))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0
(.I0(bram_addr_ld_en),
.I1(s_axi_araddr[0]),
.I2(axi_araddr_full),
.I3(\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.O(D[0]));
LUT4 #(
.INIT(16'h6F60))
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I3(\save_init_bram_addr_ld[3]_i_1__0_n_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h6AFF6A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[4]_i_1__0_n_0 ),
.O(D[2]));
LUT6 #(
.INIT(64'h6AAAFFFF6AAA0000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [3]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I5(\save_init_bram_addr_ld[5]_i_1__0_n_0 ),
.O(D[3]));
LUT4 #(
.INIT(16'h9F90))
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [4]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I3(\save_init_bram_addr_ld[6]_i_1__0_n_0 ),
.O(D[4]));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [5]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [4]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[7]_i_1__0_n_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hA6AAFFFFA6AA0000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [4]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [5]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I5(\save_init_bram_addr_ld[8]_i_1__0_n_0 ),
.O(D[6]));
LUT4 #(
.INIT(16'h7FFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [7]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [6]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[9]_i_1__0_n_0 ),
.O(D[7]));
LUT6 #(
.INIT(64'h0000000000004000))
bram_en_int_i_8
(.I0(Q[0]),
.I1(Q[2]),
.I2(axi_rvalid_int_reg),
.I3(s_axi_rready),
.I4(end_brst_rd),
.I5(brst_zero),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ));
LUT1 #(
.INIT(2'h1))
bram_rst_b_INST_0
(.I0(s_axi_aresetn),
.O(SR));
LUT6 #(
.INIT(64'h0302030203020300))
\rd_data_sm_cs[1]_i_3
(.I0(Q[0]),
.I1(Q[3]),
.I2(Q[2]),
.I3(Q[1]),
.I4(axi_rd_burst_two_reg),
.I5(axi_rd_burst),
.O(\rd_data_sm_cs_reg[1] ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[10]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[10] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[8]),
.O(\save_init_bram_addr_ld[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[11]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[11] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[9]),
.O(\save_init_bram_addr_ld[11]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h8888888A88888888))
\save_init_bram_addr_ld[15]_i_1__0
(.I0(axi_aresetn_d2),
.I1(\save_init_bram_addr_ld[15]_i_2__0_n_0 ),
.I2(\save_init_bram_addr_ld[15]_i_3__0_n_0 ),
.I3(\save_init_bram_addr_ld_reg[15]_0 ),
.I4(\save_init_bram_addr_ld_reg[15]_1 ),
.I5(last_bram_addr),
.O(bram_addr_ld_en));
LUT6 #(
.INIT(64'h0000000000000054))
\save_init_bram_addr_ld[15]_i_2__0
(.I0(rd_addr_sm_cs),
.I1(axi_araddr_full),
.I2(s_axi_arvalid),
.I3(no_ar_ack),
.I4(pend_rd_op),
.I5(ar_active),
.O(\save_init_bram_addr_ld[15]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'h2A))
\save_init_bram_addr_ld[15]_i_3__0
(.I0(brst_zero),
.I1(s_axi_rready),
.I2(axi_rvalid_int_reg),
.O(\save_init_bram_addr_ld[15]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0040))
\save_init_bram_addr_ld[15]_i_4__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.O(\save_init_bram_addr_ld_reg[15]_0 ));
LUT5 #(
.INIT(32'hFFFDFFFF))
\save_init_bram_addr_ld[15]_i_5
(.I0(axi_arsize_pipe_max),
.I1(disable_b2b_brst),
.I2(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ),
.I3(axi_arlen_pipe_1_or_2),
.I4(axi_araddr_full),
.O(\save_init_bram_addr_ld_reg[15]_1 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[3]_i_1__0
(.I0(\save_init_bram_addr_ld[3]_i_2_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[1]),
.O(\save_init_bram_addr_ld[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hA282))
\save_init_bram_addr_ld[3]_i_2
(.I0(\save_init_bram_addr_ld_reg_n_0_[3] ),
.I1(\wrap_burst_total_reg_n_0_[1] ),
.I2(\wrap_burst_total_reg_n_0_[2] ),
.I3(\wrap_burst_total_reg_n_0_[0] ),
.O(\save_init_bram_addr_ld[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[4]_i_1__0
(.I0(\save_init_bram_addr_ld[4]_i_2_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[2]),
.O(\save_init_bram_addr_ld[4]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'hA28A))
\save_init_bram_addr_ld[4]_i_2
(.I0(\save_init_bram_addr_ld_reg_n_0_[4] ),
.I1(\wrap_burst_total_reg_n_0_[0] ),
.I2(\wrap_burst_total_reg_n_0_[2] ),
.I3(\wrap_burst_total_reg_n_0_[1] ),
.O(\save_init_bram_addr_ld[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h2F202F2F2F202020))
\save_init_bram_addr_ld[5]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[5] ),
.I1(\save_init_bram_addr_ld[5]_i_2_n_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I3(\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.I4(axi_araddr_full),
.I5(s_axi_araddr[3]),
.O(\save_init_bram_addr_ld[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h04))
\save_init_bram_addr_ld[5]_i_2
(.I0(\wrap_burst_total_reg_n_0_[0] ),
.I1(\wrap_burst_total_reg_n_0_[2] ),
.I2(\wrap_burst_total_reg_n_0_[1] ),
.O(\save_init_bram_addr_ld[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[6]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[6] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[4]),
.O(\save_init_bram_addr_ld[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[7]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[7] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[5]),
.O(\save_init_bram_addr_ld[7]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[8]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[8] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[6]),
.O(\save_init_bram_addr_ld[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[9]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[9] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[7]),
.O(\save_init_bram_addr_ld[9]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[10]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[10]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[10] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[11]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[11]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[11] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[10]),
.Q(\save_init_bram_addr_ld_reg_n_0_[12] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[11]),
.Q(\save_init_bram_addr_ld_reg_n_0_[13] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[12]),
.Q(\save_init_bram_addr_ld_reg_n_0_[14] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[13]),
.Q(\save_init_bram_addr_ld_reg_n_0_[15] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[3]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[3]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[3] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[4]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[4]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[4] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[5]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[5]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[5] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[6]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[6]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[6] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[7]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[7]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[7] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[8]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[8]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[8] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[9]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[9]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[9] ),
.R(SR));
LUT6 #(
.INIT(64'h00000000A000C300))
\wrap_burst_total[0]_i_1
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I1(\wrap_burst_total_reg[0]_0 ),
.I2(\wrap_burst_total_reg[0]_1 ),
.I3(\wrap_burst_total_reg[0]_2 ),
.I4(\wrap_burst_total[0]_i_5__0_n_0 ),
.I5(\wrap_burst_total_reg[0]_3 ),
.O(\wrap_burst_total[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_2
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[2]),
.O(\wrap_burst_total_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_3
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [1]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[1]),
.O(\wrap_burst_total_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_4
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [0]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[0]),
.O(\wrap_burst_total_reg[0]_2 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
\wrap_burst_total[0]_i_5__0
(.I0(axi_araddr_full),
.I1(axi_arsize_pipe),
.O(\wrap_burst_total[0]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h220A880A000A880A))
\wrap_burst_total[1]_i_1
(.I0(\wrap_burst_total[2]_i_2_n_0 ),
.I1(axi_arsize_pipe),
.I2(s_axi_arlen[3]),
.I3(axi_araddr_full),
.I4(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [3]),
.I5(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.O(\wrap_burst_total[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hA000888800000000))
\wrap_burst_total[2]_i_1
(.I0(\wrap_burst_total[2]_i_2_n_0 ),
.I1(s_axi_arlen[2]),
.I2(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I3(axi_arsize_pipe),
.I4(axi_araddr_full),
.I5(\wrap_burst_total_reg[0]_3 ),
.O(\wrap_burst_total[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hCCA000A0))
\wrap_burst_total[2]_i_2
(.I0(s_axi_arlen[1]),
.I1(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [1]),
.I2(s_axi_arlen[0]),
.I3(axi_araddr_full),
.I4(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [0]),
.O(\wrap_burst_total[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[2]_i_3
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [3]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[3]),
.O(\wrap_burst_total_reg[0]_3 ));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[0]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[0]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[1]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[1]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[1] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[2]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[2]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[2] ),
.R(SR));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:51:06 09/06/2013
// Design Name:
// Module Name: time_parameters
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module time_parameters(clk, rst, reprogram, time_param_sel, new_time_value, interval, tiempo_espera);
input clk;
input rst;
input reprogram;
input [1:0] time_param_sel;
input [3:0] new_time_value;
input [1:0] interval;
output [3:0] tiempo_espera;
reg [3:0] t_base, t_ext, t_yel;
initial
begin
t_base <= 4'b0110;
t_ext <= 4'b0011;
t_yel <= 4'b0010;
end
always @ (posedge clk or posedge rst)
begin
if(rst)
begin
t_base <= 4'b0110;
t_ext <= 4'b0011;
t_yel <= 4'b0010;
end
else
if(reprogram)
begin
case(time_param_sel)
2'b00 : t_base <= new_time_value;
2'b01 : t_ext <= new_time_value;
2'b10 : t_yel <= new_time_value;
default : t_base <= 4'bxxxx;
endcase
end
end
//Se hace un muy con el interval
mux_tiempos selector_tiempo(t_base, t_ext, t_yel, interval, tiempo_espera);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NAND4BB_BEHAVIORAL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out;
wire or0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, D, C );
or or0 (or0_out_Y, B_N, A_N, nand0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4BB_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:57:50 08/25/2009
// Design Name:
// Module Name: mcu_cmd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
output mcu_rrq,
output mcu_write,
output mcu_wrq,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [10:0] SD_DMA_PARTIAL_START,
output [10:0] SD_DMA_PARTIAL_END,
output reg SD_DMA_START_MID_BLOCK,
output reg SD_DMA_END_MID_BLOCK,
// DAC
output [10:0] dac_addr_out,
input DAC_STATUS,
output reg dac_play_out = 0,
output reg dac_reset_out = 0,
output reg [2:0] dac_vol_select_out = 3'b000,
output reg dac_palmode_out = 0,
// MSU data
output [13:0] msu_addr_out,
input [7:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
// feature enable
output reg [7:0] featurebits_out,
// cx4
output reg cx4_reset_out,
output reg region_out,
// SNES sync/clk
input snes_sysclk,
// snes cmd interface
input [7:0] snescmd_data_in,
output reg [7:0] snescmd_data_out,
output reg [8:0] snescmd_addr_out,
output reg snescmd_we_out,
// cheat configuration
output reg [7:0] cheat_pgm_idx_out,
output reg [31:0] cheat_pgm_data_out,
output reg cheat_pgm_we_out,
// DSP core features
output reg [15:0] dsp_feat_out = 16'h0000
);
initial begin
cx4_reset_out = 1'b1;
region_out = 0;
SD_DMA_START_MID_BLOCK = 0;
SD_DMA_END_MID_BLOCK = 0;
end
wire [31:0] snes_sysclk_freq;
clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
reg [2:0] MAPPER_BUF;
reg [23:0] ADDR_OUT_BUF;
reg [10:0] DAC_ADDR_OUT_BUF;
reg [7:0] DAC_VOL_OUT_BUF;
reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
reg msu_status_reset_we_buf;
reg MSU_RESET_OUT_BUF;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
reg [7:0] MCU_DATA_OUT_BUF;
reg [7:0] MCU_DATA_IN_BUF;
reg [2:0] mcu_nextaddr_buf;
reg [7:0] dsp_feat_tmp;
wire mcu_nextaddr;
reg DAC_STATUSr;
reg SD_DMA_STATUSr;
reg [7:0] MSU_STATUSr;
always @(posedge clk) begin
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
end
reg SD_DMA_PARTIALr;
assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
reg SD_DMA_ENr;
assign SD_DMA_EN = SD_DMA_ENr;
reg [1:0] SD_DMA_TGTr;
assign SD_DMA_TGT = SD_DMA_TGTr;
reg [10:0] SD_DMA_PARTIAL_STARTr;
reg [10:0] SD_DMA_PARTIAL_ENDr;
assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
reg [23:0] SAVERAM_MASK;
reg [23:0] ROM_MASK;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
SD_DMA_ENr = 0;
SD_DMA_PARTIALr = 0;
end
// command interpretation
always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
dac_reset_out <= 1'b0;
if (cmd_ready) begin
case (cmd_data[7:4])
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= 2'b00; // cmd_data[1:0]; // not implemented
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
8'h6x:
case (spi_byte_cnt)
32'h2: begin
SD_DMA_START_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
end
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4: begin
SD_DMA_END_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
end
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'hd0:
case (spi_byte_cnt)
32'h2:
snescmd_addr_out[7:0] <= param_data;
32'h3:
snescmd_addr_out[8] <= param_data[0];
endcase
8'hd1:
snescmd_addr_out <= snescmd_addr_out + 1;
8'hd2: begin
case (spi_byte_cnt)
32'h2:
snescmd_we_out <= 1'b1;
32'h3:
snescmd_addr_out <= snescmd_addr_out + 1;
endcase
snescmd_data_out <= param_data;
end
8'hd3: begin
case (spi_byte_cnt)
32'h2:
cheat_pgm_idx_out <= param_data[2:0];
32'h3:
cheat_pgm_data_out[31:24] <= param_data;
32'h4:
cheat_pgm_data_out[23:16] <= param_data;
32'h5:
cheat_pgm_data_out[15:8] <= param_data;
32'h6: begin
cheat_pgm_data_out[7:0] <= param_data;
cheat_pgm_we_out <= 1'b1;
end
endcase
end
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
8'he1: // pause DAC
dac_play_out <= 1'b0;
8'he2: // resume DAC
dac_play_out <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
dac_reset_out <= 1'b1; // reset by default value, see above
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
32'h4:
MSU_RESET_OUT_BUF <= 1'b0;
endcase
8'heb: // put cx4 into reset
cx4_reset_out <= param_data[0];
8'hec: // set DAC properties
begin
dac_vol_select_out <= param_data[2:0];
dac_palmode_out <= param_data[7];
end
8'hed:
featurebits_out <= param_data;
8'hee:
region_out <= param_data[0];
8'hef:
case (spi_byte_cnt)
32'h2: dsp_feat_tmp <= param_data[7:0];
32'h3: begin
dsp_feat_out <= {dsp_feat_tmp, param_data[7:0]};
end
endcase
endcase
end
end
always @(posedge clk) begin
if(param_ready && cmd_data[7:4] == 4'h0) begin
case (cmd_data[1:0])
2'b01: begin
case (spi_byte_cnt)
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
2'b10: begin
case (spi_byte_cnt)
32'h2: begin
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
MSU_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
) begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
endcase
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
MCU_DATA_IN_BUF <= mcu_data_in;
else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
if (cmd_data[7:4] == 4'hA)
MCU_DATA_IN_BUF <= snescmd_data_in;
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[7], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {1'b0, MSU_STATUSr[6:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:0] == 8'hD1)
MCU_DATA_IN_BUF <= snescmd_data_in;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
parameter ST_RQ = 2'b01;
parameter ST_IDLE = 2'b10;
reg [1:0] rrq_state;
initial rrq_state = ST_IDLE;
reg mcu_rrq_r;
reg [1:0] wrq_state;
initial wrq_state = ST_IDLE;
reg mcu_wrq_r;
always @(posedge clk) begin
case(rrq_state)
ST_IDLE: begin
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
mcu_rrq_r <= 1'b1;
rrq_state <= ST_RQ;
end else
rrq_state <= ST_IDLE;
end
ST_RQ: begin
mcu_rrq_r <= 1'b0;
rrq_state <= ST_IDLE;
end
endcase
end
always @(posedge clk) begin
case(wrq_state)
ST_IDLE: begin
if(param_ready && cmd_data[7:4] == 4'h9) begin
mcu_wrq_r <= 1'b1;
wrq_state <= ST_RQ;
end else
wrq_state <= ST_IDLE;
end
ST_RQ: begin
mcu_wrq_r <= 1'b0;
wrq_state <= ST_IDLE;
end
endcase
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_rrq = mcu_rrq_r;
assign mcu_wrq = mcu_wrq_r;
assign mcu_write = SD_DMA_STATUS
?(SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
: 1'b1
)
: 1'b1;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;
assign msu_status_reset_we = msu_status_reset_we_buf;
assign msu_status_reset_out = msu_status_reset_out_buf;
assign msu_status_set_out = msu_status_set_out_buf;
assign msu_reset_out = MSU_RESET_OUT_BUF;
assign msu_ptr_out = MSU_PTR_OUT_BUF;
assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:19:44 10/07/2014
// Design Name:
// Module Name: pwm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pwm #(parameter MAX_WAVE = 24) (
input clk,
input rst,
input [MAX_WAVE-1:0] period,
input [MAX_WAVE-1:0] compare,
output pwm
);
reg pwm_d, pwm_q;
reg [MAX_WAVE-1:0] ctr_d, ctr_q;
assign pwm = pwm_q;
always@(ctr_q) begin
// reset ctr when we get to period, else increment
if (ctr_q > period) begin
ctr_d = 1'b0;
end else begin
ctr_d = ctr_q + 1'b1;
end
// set pwm based on ctr and compare threshold
if (compare > ctr_d) begin
pwm_d = 1'b0;
end else begin
pwm_d = 1'b1;
end
end
always@(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
pwm_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
pwm_q <= pwm_d;
end
end
endmodule
|
//*******************************************************************************************
//Author: Yejoong Kim
//Last Modified: Jul 26 2017
//Description: MBus Member Controller
// Structural verilog netlist using sc_x_hvt_tsmc90
//Update History: Jul 26 2017 - First added in MBus r04p2
//*******************************************************************************************
module flpv3l_mbus_member_ctrl (
input RESETn,
// MBus Clock & Data
input CIN,
input DIN,
input COUT_FROM_BUS,
input DOUT_FROM_BUS,
output COUT,
output DOUT,
// Sleep & Wakeup Requests
input SLEEP_REQ,
input WAKEUP_REQ,
// Power-Gating Signals
output MBC_ISOLATE,
output MBC_ISOLATE_B,
output MBC_RESET,
output MBC_RESET_B,
output MBC_SLEEP,
output MBC_SLEEP_B,
// Handshaking with MBus Ctrl
input CLR_EXT_INT,
output EXTERNAL_INT,
// Short-Prefix
input ADDR_WR_EN,
input ADDR_CLR_B,
input [3:0] ADDR_IN,
output [3:0] ADDR_OUT,
output ADDR_VALID,
// Misc
input LRC_SLEEP,
input MBUS_BUSY
);
//****************************************************************************
// Internal Wire Declaration
//****************************************************************************
wire cin_b;
wire cin_buf;
wire mbc_sleep_b_int;
wire mbc_isolate_b_int;
wire mbc_reset_b_int;
wire next_mbc_isolate;
wire next_mbc_isolate_b;
wire sleep_req_isol;
wire sleep_req_b_isol;
wire mbc_isolate_int;
wire mbc_sleep_int;
wire goingsleep;
wire mbc_reset_int;
wire clr_ext_int_iso;
wire clr_ext_int_b;
wire RESETn_local;
wire RESETn_local2;
wire mbus_busy_b_isol;
wire int_busy;
wire int_busy_b;
wire ext_int_dout;
wire cout_from_bus_iso;
wire cout_int;
wire cout_unbuf;
wire dout_from_bus_iso;
wire dout_int_1;
wire dout_int_0;
wire dout_unbuf;
wire addr_clr_b_iso;
wire [3:0] addr_in_iso;
wire RESETn_local3;
wire addr_update;
// ---------------------------------------------
// NOTE: Functional Relationship:
// ---------------------------------------------
// MBC_ISOLATE = mbc_isolate_int
// MBC_ISOLATE_B = mbc_isolate_b_int
// MBC_RESET = mbc_reset_int
// MBC_RESET_B = mbc_reset_b_int
// MBC_SLEEP = mbc_sleep_int
// MBC_SLEEP_B = mbc_sleep_b_int
// ---------------------------------------------
// clr_ext_int_b = ~clr_ext_int_iso
// ---------------------------------------------
//****************************************************************************
// GLOBAL
//****************************************************************************
// CIN Buffer
INVX1HVT_TSMC90 INV_cin_b (.Y(cin_b), .A(CIN));
INVX2HVT_TSMC90 INV_cin_buf (.Y(cin_buf), .A(cin_b));
//****************************************************************************
// SLEEP CONTROLLER
//****************************************************************************
//assign MBC_SLEEP_B = ~MBC_SLEEP;
INVX1HVT_TSMC90 INV_mbc_sleep_b_int (.Y(mbc_sleep_b_int), .A(mbc_sleep_int));
INVX8HVT_TSMC90 INV_MBC_SLEEP (.Y(MBC_SLEEP), .A(mbc_sleep_b_int));
INVX8HVT_TSMC90 INV_MBC_SLEEP_B (.Y(MBC_SLEEP_B), .A(mbc_sleep_int));
//assign MBC_ISOLATE_B = ~MBC_ISOLATE;
INVX1HVT_TSMC90 INV_mbc_isolate_b_int (.Y(mbc_isolate_b_int), .A(mbc_isolate_int));
INVX8HVT_TSMC90 INV_MBC_ISOLATE (.Y(MBC_ISOLATE), .A(mbc_isolate_b_int));
INVX8HVT_TSMC90 INV_MBC_ISOLATE_B (.Y(MBC_ISOLATE_B), .A(mbc_isolate_int));
//assign MBC_RESET_B = ~MBC_RESET;
INVX1HVT_TSMC90 INV_mbc_reset_b_int (.Y(mbc_reset_b_int), .A(mbc_reset_int));
INVX8HVT_TSMC90 INV_MBC_RESET (.Y(MBC_RESET), .A(mbc_reset_b_int));
INVX8HVT_TSMC90 INV_MBC_RESET_B (.Y(MBC_RESET_B), .A(mbc_reset_int));
//assign next_mbc_isolate = goingsleep | sleep_req_isol | MBC_SLEEP;
INVX1HVT_TSMC90 INV_next_mbc_isolate (.Y(next_mbc_isolate), .A(next_mbc_isolate_b));
NOR3X1HVT_TSMC90 NOR3_next_mbc_isolate_b (.C(goingsleep), .B(sleep_req_isol), .A(mbc_sleep_int), .Y(next_mbc_isolate_b));
//assign sleep_req_isol = SLEEP_REQ & MBC_ISOLATE_B;
INVX1HVT_TSMC90 INV_next_goingsleep (.Y(sleep_req_isol), .A(sleep_req_b_isol));
NAND2X1HVT_TSMC90 NAND2_next_goingsleep_b (.Y(sleep_req_b_isol), .A(SLEEP_REQ), .B(mbc_isolate_b_int));
// goingsleep, mbc_sleep_int, mbc_isolate_int, mbc_reset_int
DFFRNSNX1HVT_TSMC90 DFFSR_mbc_isolate_int (.SN(RESETn), .RN(1'b1), .CLK(cin_buf), .Q(mbc_isolate_int), .QN(), .D(next_mbc_isolate));
DFFRNSNX1HVT_TSMC90 DFFSR_mbc_sleep_int (.SN(RESETn), .RN(1'b1), .CLK(cin_buf), .Q(mbc_sleep_int), .QN(), .D(goingsleep));
DFFRNSNX1HVT_TSMC90 DFFSR_goingsleep (.SN(1'b1), .RN(RESETn), .CLK(cin_buf), .Q(goingsleep), .QN(), .D(sleep_req_isol));
DFFRNSNX1HVT_TSMC90 DFFSR_mbc_reset_int (.SN(RESETn), .RN(1'b1), .CLK(cin_b), .Q(mbc_reset_int), .QN(), .D(mbc_isolate_int));
//****************************************************************************
// INTERRUPT CONTROLLER
//****************************************************************************
//wire clr_ext_int_b = ~(MBC_ISOLATE_B & CLR_EXT_INT);
AND2X1HVT_TSMC90 AND2_clr_ext_int_iso (.Y(clr_ext_int_iso), .A(MBC_ISOLATE_B), .B(CLR_EXT_INT));
INVX1HVT_TSMC90 INV_clr_ext_int_b (.Y(clr_ext_int_b), .A(clr_ext_int_iso));
//wire RESETn_local = RESETn & CIN;
AND2X1HVT_TSMC90 AND2_RESETn_local (.Y(RESETn_local), .A(CIN), .B(RESETn));
//wire RESETn_local2 = RESETn & clr_ext_int_b;
AND2X1HVT_TSMC90 AND2_RESETn_local2 (.Y(RESETn_local2), .A(clr_ext_int_b), .B(RESETn));
//wire mbus_busy_b_isol = ~(MBUS_BUSY & MBC_RESET_B);
NAND2X1HVT_TSMC90 NAND2_mbus_busy_b_isol (.A(MBUS_BUSY), .B(mbc_reset_b_int), .Y(mbus_busy_b_isol));
//wire int_busy = (WAKEUP_REQ & mbus_busy_b_isol & LRC_SLEEP)
NAND3X1HVT_TSMC90 NAND3_int_busy_b (.A(WAKEUP_REQ), .B(mbus_busy_b_isol), .C(LRC_SLEEP), .Y(int_busy_b));
INVX2HVT_TSMC90 INV_int_busy (.Y(int_busy), .A(int_busy_b));
// ext_int_dout
DFFRNX1HVT_TSMC90 DFFR_ext_int_dout (.RN(RESETn_local), .CLK(int_busy), .Q(ext_int_dout), .QN(), .D(1'b1));
// EXTERNAL_INT
DFFRNX1HVT_TSMC90 DFFR_EXTERNAL_INT (.RN(RESETn_local2), .CLK(int_busy), .Q(EXTERNAL_INT), .QN(), .D(1'b1));
//****************************************************************************
// WIRE CONTROLLER
//****************************************************************************
// COUT
OR2X1HVT_TSMC90 OR2_cout_from_bus_iso (.Y(cout_from_bus_iso), .A(COUT_FROM_BUS), .B(MBC_ISOLATE));
MUX2X1HVT_TSMC90 MUX2_cout_int (.S0(MBC_ISOLATE), .A(cout_from_bus_iso), .Y(cout_int), .B(CIN));
MUX2X1HVT_TSMC90 MUX2_cout_unbuf (.S0(RESETn), .A(1'b1), .Y(cout_unbuf), .B(cout_int));
BUFX4HVT_TSMC90 BUF_COUT (.A(cout_unbuf), .Y(COUT));
// DOUT
OR2X1HVT_TSMC90 OR2_dout_from_bus_iso (.Y(dout_from_bus_iso), .A(DOUT_FROM_BUS), .B(MBC_ISOLATE));
MUX2X1HVT_TSMC90 MUX2_dout_int_1 (.S0(MBC_ISOLATE), .A(dout_from_bus_iso), .Y(dout_int_1), .B(DIN));
MUX2X1HVT_TSMC90 MUX2_dout_int_0 (.S0(ext_int_dout), .A(dout_int_1), .Y(dout_int_0), .B(1'b0));
MUX2X1HVT_TSMC90 MUX2_dout_unbuf (.S0(RESETn), .A(1'b1), .Y(dout_unbuf), .B(dout_int_0));
BUFX4HVT_TSMC90 BUF_DOUT (.A(dout_unbuf), .Y(DOUT));
//****************************************************************************
// SHORT-PREFIX ADDRESS REGISTER
//****************************************************************************
// Isolation
OR2X1HVT_TSMC90 AND2_addr_clr_b_iso (.A(MBC_ISOLATE), .B(ADDR_CLR_B), .Y(addr_clr_b_iso));
AND2X1HVT_TSMC90 AND2_addr_in_iso_0 (.A(MBC_ISOLATE_B), .B(ADDR_IN[0]), .Y(addr_in_iso[0]));
AND2X1HVT_TSMC90 AND2_addr_in_iso_1 (.A(MBC_ISOLATE_B), .B(ADDR_IN[1]), .Y(addr_in_iso[1]));
AND2X1HVT_TSMC90 AND2_addr_in_iso_2 (.A(MBC_ISOLATE_B), .B(ADDR_IN[2]), .Y(addr_in_iso[2]));
AND2X1HVT_TSMC90 AND2_addr_in_iso_3 (.A(MBC_ISOLATE_B), .B(ADDR_IN[3]), .Y(addr_in_iso[3]));
//wire RESETn_local3 = (RESETn & ADDR_CLR_B);
AND2X1HVT_TSMC90 AND2_RESETn_local3 (.A(RESETn), .B(addr_clr_b_iso), .Y(RESETn_local3));
//wire addr_update = (ADDR_WR_EN & (~MBC_ISOLATE));
AND2X1HVT_TSMC90 AND2_addr_update (.A(MBC_ISOLATE_B), .B(ADDR_WR_EN), .Y(addr_update));
// ADDR_OUT, ADDR_VALID
DFFSNX1HVT_TSMC90 DFFS_ADDR_OUT_0 (.CLK(addr_update), .D(addr_in_iso[0]), .SN(RESETn_local3), .Q(ADDR_OUT[0]), .QN());
DFFSNX1HVT_TSMC90 DFFS_ADDR_OUT_1 (.CLK(addr_update), .D(addr_in_iso[1]), .SN(RESETn_local3), .Q(ADDR_OUT[1]), .QN());
DFFSNX1HVT_TSMC90 DFFS_ADDR_OUT_2 (.CLK(addr_update), .D(addr_in_iso[2]), .SN(RESETn_local3), .Q(ADDR_OUT[2]), .QN());
DFFSNX1HVT_TSMC90 DFFS_ADDR_OUT_3 (.CLK(addr_update), .D(addr_in_iso[3]), .SN(RESETn_local3), .Q(ADDR_OUT[3]), .QN());
DFFRNX1HVT_TSMC90 DFFR_ADDR_VALID (.CLK(addr_update), .D(1'b1), .RN(RESETn_local3), .Q(ADDR_VALID), .QN());
endmodule // flpv3l_mbus_member_ctrl
|
`timescale 1 ns / 1 ps
module apsk_modulator #
(
// block setup information
parameter integer SAMPLES_PER_SYMBOL = 4,
parameter integer NUMBER_TAPS = 40,
parameter integer DATA_WIDTH = 16,
parameter integer COEFFICIENT_WIDTH = 16,
// AXI buses parameters
parameter integer DATA_IN_TDATA_WIDTH = 32,
parameter integer DATA_OUT_TDATA_WIDTH = 32,
parameter integer LUT_DATA_LOAD_TDATA_WIDTH = 32,
parameter integer COEFFICIENTS_IN_TDATA_WIDTH = 32,
parameter integer CONTROL_DATA_WIDTH = 32,
parameter integer CONTROL_ADDR_WIDTH = 4
)
(
// data input AXI bus
input wire data_in_aclk,
input wire data_in_aresetn,
output wire data_in_tready,
input wire [DATA_IN_TDATA_WIDTH-1:0] data_in_tdata,
input wire data_in_tlast,
input wire data_in_tvalid,
// data output AXI bus
input wire data_out_aclk,
input wire data_out_aresetn,
input wire data_out_tready,
output wire [DATA_OUT_TDATA_WIDTH-1:0] data_out_tdata,
output wire data_out_tlast,
output wire data_out_tvalid,
// lookup table load AXI bus
input wire lut_data_load_aclk,
input wire lut_data_load_aresetn,
output wire lut_data_load_tready,
input wire [LUT_DATA_LOAD_TDATA_WIDTH-1:0] lut_data_load_tdata,
input wire lut_data_load_tlast,
input wire lut_data_load_tvalid,
// pulse shaping filter load AXI bus
input wire coefficients_in_aclk,
input wire coefficients_in_aresetn,
output wire coefficients_in_tready,
input wire [COEFFICIENTS_IN_TDATA_WIDTH-1:0] coefficients_in_tdata,
input wire coefficients_in_tlast,
input wire coefficients_in_tvalid,
// control signal AXI bus
input wire control_aclk,
input wire control_aresetn,
input wire [CONTROL_ADDR_WIDTH-1:0] control_awaddr,
input wire [2:0] control_awprot,
input wire control_awvalid,
output wire control_awready,
input wire [CONTROL_DATA_WIDTH-1:0] control_wdata,
input wire [(CONTROL_DATA_WIDTH/8)-1:0] control_wstrb,
input wire control_wvalid,
output wire control_wready,
output wire [1:0] control_bresp,
output wire control_bvalid,
input wire control_bready,
input wire [CONTROL_ADDR_WIDTH-1:0] control_araddr,
input wire [2:0] control_arprot,
input wire control_arvalid,
output wire control_arready,
output wire [CONTROL_DATA_WIDTH-1:0] control_rdata,
output wire [1:0] control_rresp,
output wire control_rvalid,
input wire control_rready
);
// define some constants
localparam integer ADDRESS_WIDTH = 8;
localparam integer DATA_LATCH_EXCESS = 8;
localparam integer DATA_LATCH_WIDTH = DATA_IN_TDATA_WIDTH + DATA_LATCH_EXCESS;
localparam integer BITS_PER_SYMBOL_WIDTH = $clog2(ADDRESS_WIDTH+1);
wire reset;
// data in signals
reg [$clog2(DATA_IN_TDATA_WIDTH):0] data_in_count;
reg [DATA_LATCH_WIDTH-1:0] data_in_latch;
reg [7:0] data_in_latch_mask;
reg data_in_tlast_latched;
// lookup table signals
wire lut_data_in_aclk;
wire lut_data_in_aresetn;
wire lut_data_in_tready;
wire [ADDRESS_WIDTH-1:0] lut_data_in_tdata;
reg lut_data_in_tlast;
reg lut_data_in_tvalid;
wire lut_data_out_aclk;
wire lut_data_out_aresetn;
wire lut_data_out_tready_i;
wire lut_data_out_tready_q;
wire [2*DATA_WIDTH-1:0] lut_data_out_tdata;
wire lut_data_out_tlast;
wire lut_data_out_tvalid;
// filter signals
wire filter_i_out_aclk;
wire filter_q_out_aclk;
wire filter_i_out_aresetn;
wire filter_q_out_aresetn;
wire filter_i_out_tready;
wire filter_q_out_tready;
wire [DATA_WIDTH-1:0] filter_i_out_tdata;
wire [DATA_WIDTH-1:0] filter_q_out_tdata;
wire filter_i_out_tlast;
wire filter_q_out_tlast;
wire filter_i_out_tvalid;
wire filter_q_out_tvalid;
wire coefficients_i_in_tready;
wire coefficients_q_in_tready;
// configuration signals
wire [3:0] bits_per_symbol;
wire offset_symbol_enable;
// form an internal reset signal which can be controled through external ports
// or reset at the end of a transaction
assign reset = !data_in_aresetn | data_out_tlast;
// map the clocks and resets
assign lut_data_in_aclk = data_in_aclk;
assign lut_data_out_aclk = data_in_aclk;
assign filter_i_out_aclk = data_in_aclk;
assign filter_q_out_aclk = data_in_aclk;
assign lut_data_in_aresetn = !reset;
assign lut_data_out_aresetn = !reset;
//assign lut_data_load_aresetn = data_in_aresetn;
assign filter_i_out_aresetn = !reset;
assign filter_q_out_aresetn = !reset;
// figure out if the input is currently valid
always @(posedge data_in_aclk) begin
if(reset) begin
lut_data_in_tvalid <= 0;
end
else begin
// valid input count and we're in the correct phase so the data into the
// lookup table is valid
if ((data_in_count > 0) | data_in_tvalid) begin
lut_data_in_tvalid <= 1;
end
// we're finished with the frame so removed valid flag
else if (lut_data_in_tlast & lut_data_in_tready & (data_in_count == 0)) begin
lut_data_in_tvalid <= 0;
end
// register the signal
else begin
lut_data_in_tvalid <= lut_data_in_tvalid;
end
end
end
// if the data input count has reached
assign data_in_tready = !(data_in_count > bits_per_symbol) ? lut_data_in_tready & !data_in_tlast_latched : 0;
// count how many bits are left in the input shift register
always @(posedge data_in_aclk) begin
if(reset) begin
data_in_count <= 0;
end
else begin
// new data, reset count
if ((data_in_count <= bits_per_symbol) & data_in_tready & data_in_tvalid) begin
data_in_count <= DATA_IN_TDATA_WIDTH - bits_per_symbol + data_in_count;
end
// need to keep clearing the current data
else if (lut_data_out_tready & lut_data_out_tvalid) begin
data_in_count <= data_in_count - bits_per_symbol;
end
// register the count
else begin
data_in_count <= data_in_count;
end
end
end
// handle the last sample signal
always @(posedge data_in_aclk) begin
if(reset) begin
lut_data_in_tlast <= 0;
data_in_tlast_latched <= 0;
end
else begin
// latch the tlast signal
data_in_tlast_latched = data_in_tlast_latched | (data_in_tlast & data_in_tvalid & data_in_tready);
// if at the end of the shifting out data then signal last sample
// and clear latch
if (!(data_in_count >= bits_per_symbol) & !data_in_tlast) begin
lut_data_in_tlast <= data_in_tlast_latched;
end
// reset the tlast latch once the transaction is complete
else if (data_out_tlast) begin
data_in_tlast_latched <= 0;
end
// register the signal
else begin
lut_data_in_tlast <= lut_data_in_tlast;
end
end
end
// latch in data and shift through it splitting into bit segments
always @(posedge data_in_aclk) begin
if(reset) begin
data_in_latch <= 0;
end
else begin
// new input so latch it into the shift register
if ((data_in_count <= bits_per_symbol) & data_in_tready & data_in_tvalid) begin
// blocking shift of the register before mapping - may not be a very good may to perform this
data_in_latch = data_in_latch >> bits_per_symbol;
// figure out how to keep the requried samples left over
case (data_in_count)
0 : data_in_latch <= {8'd0, data_in_tdata};
1 : data_in_latch <= {7'd0, data_in_tdata, data_in_latch[0]};
2 : data_in_latch <= {6'd0, data_in_tdata, data_in_latch[1:0]};
3 : data_in_latch <= {5'd0, data_in_tdata, data_in_latch[2:0]};
4 : data_in_latch <= {4'd0, data_in_tdata, data_in_latch[3:0]};
5 : data_in_latch <= {3'd0, data_in_tdata, data_in_latch[4:0]};
6 : data_in_latch <= {2'd0, data_in_tdata, data_in_latch[5:0]};
7 : data_in_latch <= {1'd0, data_in_tdata, data_in_latch[6:0]};
8 : data_in_latch <= {data_in_tdata, data_in_latch[7:0]};
default : data_in_latch <= {8'd0, data_in_tdata};
endcase
end
// shift the input register to obtain fresh information at the bottom
else if (lut_data_out_tready & lut_data_out_tvalid) begin
data_in_latch <= data_in_latch >> bits_per_symbol;
end
// register the signal
else begin
data_in_latch <= data_in_latch;
end
end
end
// select a bit mask depending on the number of bits of symbol
// TODO should be change from hardcoded
always @(*)
begin
case (bits_per_symbol)
0 : data_in_latch_mask <= 8'b00000001;
1 : data_in_latch_mask <= 8'b00000001;
2 : data_in_latch_mask <= 8'b00000011;
3 : data_in_latch_mask <= 8'b00000111;
4 : data_in_latch_mask <= 8'b00001111;
5 : data_in_latch_mask <= 8'b00011111;
6 : data_in_latch_mask <= 8'b00111111;
7 : data_in_latch_mask <= 8'b01111111;
8 : data_in_latch_mask <= 8'b11111111;
default : data_in_latch_mask <= 8'b00000001;
endcase
end
// interface to the lookup table
assign lut_data_in_tdata = data_in_latch[ADDRESS_WIDTH-1:0] & data_in_latch_mask;
// instantiate the modulation lookup table
lookup_table_behavioural #(
.TDATA_WIDTH(2*DATA_WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH)
) lookup_table_inst (
.data_in_aclk(lut_data_in_aclk),
.data_in_aresetn(lut_data_in_aresetn),
.data_in_tready(lut_data_in_tready),
.data_in_tdata(lut_data_in_tdata),
.data_in_tlast(lut_data_in_tlast),
.data_in_tvalid(lut_data_in_tvalid),
.data_out_aclk(lut_data_out_aclk),
.data_out_aresetn(lut_data_out_aresetn),
.data_out_tready(lut_data_out_tready),
.data_out_tdata(lut_data_out_tdata),
.data_out_tlast(lut_data_out_tlast),
.data_out_tvalid(lut_data_out_tvalid),
.data_load_aclk(lut_data_load_aclk),
.data_load_aresetn(lut_data_load_aresetn),
.data_load_tready(lut_data_load_tready),
.data_load_tdata(lut_data_load_tdata),
.data_load_tlast(lut_data_load_tlast),
.data_load_tvalid(lut_data_load_tvalid)
);
// both the pulse shaping filters need to be ready
assign lut_data_out_tready = lut_data_out_tready_i & lut_data_out_tready_q;
// combine the neccesary i and q signals
assign coefficients_in_tready = coefficients_i_in_tready & coefficients_i_in_tready;
assign filter_i_out_tready = data_out_tready;
assign filter_q_out_tready = data_out_tready;
// I channel polyphase pulse shaping filter
polyphase_filter #(
.NUMBER_TAPS(NUMBER_TAPS),
.DATA_IN_WIDTH(DATA_WIDTH),
.DATA_OUT_WIDTH(DATA_WIDTH),
.COEFFICIENT_WIDTH(COEFFICIENT_WIDTH),
.RATE_CHANGE(SAMPLES_PER_SYMBOL),
.DECIMATE_INTERPOLATE(1)
) pulse_shape_filter_i (
.data_in_aclk(lut_data_out_aclk),
.data_in_aresetn(lut_data_out_aresetn),
.data_in_tready(lut_data_out_tready_i),
.data_in_tdata(lut_data_out_tdata[2*DATA_WIDTH-1:DATA_WIDTH]),
.data_in_tlast(lut_data_out_tlast),
.data_in_tvalid(lut_data_out_tvalid),
.data_out_aclk(filter_i_out_aclk),
.data_out_aresetn(filter_i_out_aresetn),
.data_out_tready(filter_i_out_tready),
.data_out_tdata(filter_i_out_tdata),
.data_out_tlast(filter_i_out_tlast),
.data_out_tvalid(filter_i_out_tvalid),
.coefficients_in_aclk(coefficients_in_aclk),
.coefficients_in_aresetn(coefficients_in_aresetn),
.coefficients_in_tready(coefficients_i_in_tready),
.coefficients_in_tdata(coefficients_in_tdata[COEFFICIENT_WIDTH-1:0]),
.coefficients_in_tlast(coefficients_in_tlast),
.coefficients_in_tvalid(coefficients_in_tvalid)
);
// Q channel polyphase pulse shaping filter
polyphase_filter #(
.NUMBER_TAPS(NUMBER_TAPS),
.DATA_IN_WIDTH(DATA_WIDTH),
.DATA_OUT_WIDTH(DATA_WIDTH),
.COEFFICIENT_WIDTH(COEFFICIENT_WIDTH),
.RATE_CHANGE(SAMPLES_PER_SYMBOL),
.DECIMATE_INTERPOLATE(1)
) pulse_shape_filter_q (
.data_in_aclk(lut_data_out_aclk),
.data_in_aresetn(lut_data_out_aresetn),
.data_in_tready(lut_data_out_tready_q),
.data_in_tdata(lut_data_out_tdata[DATA_WIDTH-1:0]),
.data_in_tlast(lut_data_out_tlast),
.data_in_tvalid(lut_data_out_tvalid),
.data_out_aclk(filter_q_out_aclk),
.data_out_aresetn(filter_q_out_aresetn),
.data_out_tready(filter_q_out_tready),
.data_out_tdata(filter_q_out_tdata),
.data_out_tlast(filter_q_out_tlast),
.data_out_tvalid(filter_q_out_tvalid),
.coefficients_in_aclk(coefficients_in_aclk),
.coefficients_in_aresetn(coefficients_in_aresetn),
.coefficients_in_tready(coefficients_q_in_tready),
.coefficients_in_tdata(coefficients_in_tdata[COEFFICIENT_WIDTH-1:0]),
.coefficients_in_tlast(coefficients_in_tlast),
.coefficients_in_tvalid(coefficients_in_tvalid)
);
// connect the pulse shaping filter to the output
assign data_out_tdata = {filter_i_out_tdata, filter_q_out_tdata};
assign data_out_tvalid = filter_i_out_tvalid & filter_q_out_tvalid;
assign data_out_tlast = filter_i_out_tlast & filter_q_out_tlast;
// instantiation of axi bus interface control
apsk_modulator_control # (
.BITS_PER_SYMBOL_WIDTH(BITS_PER_SYMBOL_WIDTH),
.C_S_AXI_DATA_WIDTH(CONTROL_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(CONTROL_ADDR_WIDTH)
) apsk_modulator_control_inst (
.bits_per_symbol(bits_per_symbol),
.offset_symbol_enable(offset_symbol_enable),
.s_axi_aclk(control_aclk),
.s_axi_aresetn(control_aresetn),
.s_axi_awaddr(control_awaddr),
.s_axi_awprot(control_awprot),
.s_axi_awvalid(control_awvalid),
.s_axi_awready(control_awready),
.s_axi_wdata(control_wdata),
.s_axi_wstrb(control_wstrb),
.s_axi_wvalid(control_wvalid),
.s_axi_wready(control_wready),
.s_axi_bresp(control_bresp),
.s_axi_bvalid(control_bvalid),
.s_axi_bready(control_bready),
.s_axi_araddr(control_araddr),
.s_axi_arprot(control_arprot),
.s_axi_arvalid(control_arvalid),
.s_axi_arready(control_arready),
.s_axi_rdata(control_rdata),
.s_axi_rresp(control_rresp),
.s_axi_rvalid(control_rvalid),
.s_axi_rready(control_rready)
);
// used to create the GTKwave dump file
`ifdef COCOTB_SIM
initial begin
$dumpfile ("waveform.vcd");
$dumpvars (0, apsk_modulator);
#1;
end
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A221O_BEHAVIORAL_PP_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_BEHAVIORAL_PP_V |
// N64 controller module
//
// Inputs: clk_4M 4 MHz clock
// Input/Output: data Data line to send the request and receive the response
// Outputs: ctrl_state 32-bit register with controller state
// ctrl_clk Output clock, sample at negative edge
module n64_readcmd(input wire clk_4M,
inout data,
output wire [31:0] ctrl_state,
output wire ctrl_clk);
// Internal wires
wire read_start; // Trigger signal
wire output_en; // Active when transmitting data
// Our data line will be buffered through this SB_IO block.
// This manual I/O instance allows us to control
// output enable, and thus switch between input and
// output
wire data_o;
wire data_i;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin (
.PACKAGE_PIN(data),
.OUTPUT_ENABLE(output_en),
.D_OUT_0(data_o),
.D_IN_0(data_i)
);
// Generate 1 MHz clock (needed for tx block)
// from the 4 MHz clock
wire clk_1M;
divM #(.M(4))
div3 (
.clk_in(clk_4M),
.clk_out(clk_1M)
);
// Generator/transmission block, sends the
// read command over the data line when
// triggered
n64_readcmd_tx
n64_readcmd_tx_i (
.clk_1M(clk_1M),
.trigger(read_start),
.enable_o(output_en),
.dout(data_o)
);
// rx block enable signal (TODO: improve)
reg triggered = 0;
always @(posedge(read_start)) triggered = 1;
wire receive = ~output_en & triggered;
// Parser/reception block, must be enabled
// after transmission end. Reads the data
// line containing the controller reply.
n64_readcmd_rx
n64_readcmd_rx_i (
.clk_4M(clk_4M),
.din(data_i),
.enable(receive),
.ctrl_state(ctrl_state),
.ctrl_clk(ctrl_clk)
);
// Trigger generator, for periodically
// sending a read command
triggerM
trigger_read (
.clk(clk_1M),
.trigger(read_start)
);
endmodule
|
/*
* interrupt.v - Interrupt handler
*
* Manages the interrupt lines, requires a read to
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
module interrupt_manager (
// Fast clock input
input fast_clock_i,
// These are the individual interrupt lines
input [7:0] interrupt_lines_i,
// Read interrupt state
input rd_i,
// Interrupt line
output n_int_o,
// Interrupt register
output [7:0] dat_o
);
// Wire definitions ===========================================================================
wire [7:0] lines;
wire rd;
// Registers ==================================================================================
reg [2:0] track_rd;
// Assignments ================================================================================
assign n_int_o = (lines == 0); // Cause an interrupt if one line is active
assign dat_o = lines;
// Module connections =========================================================================
// Simulation branches and control ============================================================
always @(posedge fast_clock_i) track_rd <= {track_rd[1:0],rd_i};
assign rd = (track_rd[2:1] == 2'b10);
// Note that when RD cycle finishes then it resets all latches
SR sr1( .clock_i(fast_clock_i), .S( interrupt_lines_i[0]), .R(rd), .Q(lines[0]) );
SR sr2( .clock_i(fast_clock_i), .S( interrupt_lines_i[1]), .R(rd), .Q(lines[1]) );
SR sr3( .clock_i(fast_clock_i), .S( interrupt_lines_i[2]), .R(rd), .Q(lines[2]) );
SR sr4( .clock_i(fast_clock_i), .S( interrupt_lines_i[3]), .R(rd), .Q(lines[3]) );
SR sr5( .clock_i(fast_clock_i), .S( interrupt_lines_i[4]), .R(rd), .Q(lines[4]) );
SR sr6( .clock_i(fast_clock_i), .S( interrupt_lines_i[5]), .R(rd), .Q(lines[5]) );
SR sr7( .clock_i(fast_clock_i), .S( interrupt_lines_i[6]), .R(rd), .Q(lines[6]) );
SR sr8( .clock_i(fast_clock_i), .S( interrupt_lines_i[7]), .R(rd), .Q(lines[7]) );
// Other logic ================================================================================
endmodule
module SR(
input clock_i,
input S,
input R,
output Q
);
reg out; // Need to reset before use, default is powerup high
assign Q = out;
always @(negedge clock_i)
begin
if( S )
out <= 1'b1;
else
if( R )
out <= 1'b0;
end
endmodule
|
`include "enc_defines.v"
module tq_top(
clk ,
rst ,
type_i ,
qp_i ,
tq_en_i ,
tq_sel_i ,
tq_size_i ,
tq_idx_i ,
tq_res_i ,
rec_val_o ,
rec_idx_o ,
rec_data_o ,
cef_wen_o ,
cef_widx_o ,
cef_data_o ,
cef_ren_o ,
cef_ridx_o ,
cef_data_i
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk ;
input rst ;
input type_i ;
input [5:0] qp_i ;
input tq_en_i ;
input [1:0] tq_sel_i ;
input [1:0] tq_size_i ;
input [4:0] tq_idx_i ;
input [287:0] tq_res_i ;
input [511:0] cef_data_i ;
output rec_val_o ;
output [4:0] rec_idx_o ;
output [287:0] rec_data_o ;
output cef_wen_o ;
output [4:0] cef_widx_o ;
output [511:0] cef_data_o ;
output cef_ren_o ;
output [4:0] cef_ridx_o ;
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg counter_en;
reg counter_val_en;
reg [4:0] counter_val;
reg [5:0] counter;
reg [4:0] counter_rec;
reg [4:0] rec_idx_o;
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
wire i_val;
wire inverse;
wire signed [8:0] i_0 ;
wire signed [8:0] i_1 ;
wire signed [8:0] i_2 ;
wire signed [8:0] i_3 ;
wire signed [8:0] i_4 ;
wire signed [8:0] i_5 ;
wire signed [8:0] i_6 ;
wire signed [8:0] i_7 ;
wire signed [8:0] i_8 ;
wire signed [8:0] i_9 ;
wire signed [8:0] i_10;
wire signed [8:0] i_11;
wire signed [8:0] i_12;
wire signed [8:0] i_13;
wire signed [8:0] i_14;
wire signed [8:0] i_15;
wire signed [8:0] i_16;
wire signed [8:0] i_17;
wire signed [8:0] i_18;
wire signed [8:0] i_19;
wire signed [8:0] i_20;
wire signed [8:0] i_21;
wire signed [8:0] i_22;
wire signed [8:0] i_23;
wire signed [8:0] i_24;
wire signed [8:0] i_25;
wire signed [8:0] i_26;
wire signed [8:0] i_27;
wire signed [8:0] i_28;
wire signed [8:0] i_29;
wire signed [8:0] i_30;
wire signed [8:0] i_31;
wire i_d_valid;
wire signed [15:0] i_d_0 ;
wire signed [15:0] i_d_1 ;
wire signed [15:0] i_d_2 ;
wire signed [15:0] i_d_3 ;
wire signed [15:0] i_d_4 ;
wire signed [15:0] i_d_5 ;
wire signed [15:0] i_d_6 ;
wire signed [15:0] i_d_7 ;
wire signed [15:0] i_d_8 ;
wire signed [15:0] i_d_9 ;
wire signed [15:0] i_d_10;
wire signed [15:0] i_d_11;
wire signed [15:0] i_d_12;
wire signed [15:0] i_d_13;
wire signed [15:0] i_d_14;
wire signed [15:0] i_d_15;
wire signed [15:0] i_d_16;
wire signed [15:0] i_d_17;
wire signed [15:0] i_d_18;
wire signed [15:0] i_d_19;
wire signed [15:0] i_d_20;
wire signed [15:0] i_d_21;
wire signed [15:0] i_d_22;
wire signed [15:0] i_d_23;
wire signed [15:0] i_d_24;
wire signed [15:0] i_d_25;
wire signed [15:0] i_d_26;
wire signed [15:0] i_d_27;
wire signed [15:0] i_d_28;
wire signed [15:0] i_d_29;
wire signed [15:0] i_d_30;
wire signed [15:0] i_d_31;
wire o_d_valid;
wire signed [15:0] o_d_0 ;
wire signed [15:0] o_d_1 ;
wire signed [15:0] o_d_2 ;
wire signed [15:0] o_d_3 ;
wire signed [15:0] o_d_4 ;
wire signed [15:0] o_d_5 ;
wire signed [15:0] o_d_6 ;
wire signed [15:0] o_d_7 ;
wire signed [15:0] o_d_8 ;
wire signed [15:0] o_d_9 ;
wire signed [15:0] o_d_10;
wire signed [15:0] o_d_11;
wire signed [15:0] o_d_12;
wire signed [15:0] o_d_13;
wire signed [15:0] o_d_14;
wire signed [15:0] o_d_15;
wire signed [15:0] o_d_16;
wire signed [15:0] o_d_17;
wire signed [15:0] o_d_18;
wire signed [15:0] o_d_19;
wire signed [15:0] o_d_20;
wire signed [15:0] o_d_21;
wire signed [15:0] o_d_22;
wire signed [15:0] o_d_23;
wire signed [15:0] o_d_24;
wire signed [15:0] o_d_25;
wire signed [15:0] o_d_26;
wire signed [15:0] o_d_27;
wire signed [15:0] o_d_28;
wire signed [15:0] o_d_29;
wire signed [15:0] o_d_30;
wire signed [15:0] o_d_31;
wire i_q_valid;
wire signed [15:0] i_q_0 ;
wire signed [15:0] i_q_1 ;
wire signed [15:0] i_q_2 ;
wire signed [15:0] i_q_3 ;
wire signed [15:0] i_q_4 ;
wire signed [15:0] i_q_5 ;
wire signed [15:0] i_q_6 ;
wire signed [15:0] i_q_7 ;
wire signed [15:0] i_q_8 ;
wire signed [15:0] i_q_9 ;
wire signed [15:0] i_q_10;
wire signed [15:0] i_q_11;
wire signed [15:0] i_q_12;
wire signed [15:0] i_q_13;
wire signed [15:0] i_q_14;
wire signed [15:0] i_q_15;
wire signed [15:0] i_q_16;
wire signed [15:0] i_q_17;
wire signed [15:0] i_q_18;
wire signed [15:0] i_q_19;
wire signed [15:0] i_q_20;
wire signed [15:0] i_q_21;
wire signed [15:0] i_q_22;
wire signed [15:0] i_q_23;
wire signed [15:0] i_q_24;
wire signed [15:0] i_q_25;
wire signed [15:0] i_q_26;
wire signed [15:0] i_q_27;
wire signed [15:0] i_q_28;
wire signed [15:0] i_q_29;
wire signed [15:0] i_q_30;
wire signed [15:0] i_q_31;
wire o_q_valid;
wire signed [15:0] o_q_0 ;
wire signed [15:0] o_q_1 ;
wire signed [15:0] o_q_2 ;
wire signed [15:0] o_q_3 ;
wire signed [15:0] o_q_4 ;
wire signed [15:0] o_q_5 ;
wire signed [15:0] o_q_6 ;
wire signed [15:0] o_q_7 ;
wire signed [15:0] o_q_8 ;
wire signed [15:0] o_q_9 ;
wire signed [15:0] o_q_10;
wire signed [15:0] o_q_11;
wire signed [15:0] o_q_12;
wire signed [15:0] o_q_13;
wire signed [15:0] o_q_14;
wire signed [15:0] o_q_15;
wire signed [15:0] o_q_16;
wire signed [15:0] o_q_17;
wire signed [15:0] o_q_18;
wire signed [15:0] o_q_19;
wire signed [15:0] o_q_20;
wire signed [15:0] o_q_21;
wire signed [15:0] o_q_22;
wire signed [15:0] o_q_23;
wire signed [15:0] o_q_24;
wire signed [15:0] o_q_25;
wire signed [15:0] o_q_26;
wire signed [15:0] o_q_27;
wire signed [15:0] o_q_28;
wire signed [15:0] o_q_29;
wire signed [15:0] o_q_30;
wire signed [15:0] o_q_31;
wire signed [8:0] o_0 ;
wire signed [8:0] o_1 ;
wire signed [8:0] o_2 ;
wire signed [8:0] o_3 ;
wire signed [8:0] o_4 ;
wire signed [8:0] o_5 ;
wire signed [8:0] o_6 ;
wire signed [8:0] o_7 ;
wire signed [8:0] o_8 ;
wire signed [8:0] o_9 ;
wire signed [8:0] o_10;
wire signed [8:0] o_11;
wire signed [8:0] o_12;
wire signed [8:0] o_13;
wire signed [8:0] o_14;
wire signed [8:0] o_15;
wire signed [8:0] o_16;
wire signed [8:0] o_17;
wire signed [8:0] o_18;
wire signed [8:0] o_19;
wire signed [8:0] o_20;
wire signed [8:0] o_21;
wire signed [8:0] o_22;
wire signed [8:0] o_23;
wire signed [8:0] o_24;
wire signed [8:0] o_25;
wire signed [8:0] o_26;
wire signed [8:0] o_27;
wire signed [8:0] o_28;
wire signed [8:0] o_29;
wire signed [8:0] o_30;
wire signed [8:0] o_31;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign i_val=tq_en_i||counter_val_en;
assign inverse=~(i_val||counter_en);
assign i_0 =tq_res_i[8 :0 ];
assign i_1 =tq_res_i[17 :9 ];
assign i_2 =tq_res_i[26 :18 ];
assign i_3 =tq_res_i[35 :27 ];
assign i_4 =tq_res_i[44 :36 ];
assign i_5 =tq_res_i[53 :45 ];
assign i_6 =tq_res_i[62 :54 ];
assign i_7 =tq_res_i[71 :63 ];
assign i_8 =tq_res_i[80 :72 ];
assign i_9 =tq_res_i[89 :81 ];
assign i_10=tq_res_i[98 :90 ];
assign i_11=tq_res_i[107:99 ];
assign i_12=tq_res_i[116:108];
assign i_13=tq_res_i[125:117];
assign i_14=tq_res_i[134:126];
assign i_15=tq_res_i[143:135];
assign i_16=tq_res_i[152:144];
assign i_17=tq_res_i[161:153];
assign i_18=tq_res_i[170:162];
assign i_19=tq_res_i[179:171];
assign i_20=tq_res_i[188:180];
assign i_21=tq_res_i[197:189];
assign i_22=tq_res_i[206:198];
assign i_23=tq_res_i[215:207];
assign i_24=tq_res_i[224:216];
assign i_25=tq_res_i[233:225];
assign i_26=tq_res_i[242:234];
assign i_27=tq_res_i[251:243];
assign i_28=tq_res_i[260:252];
assign i_29=tq_res_i[269:261];
assign i_30=tq_res_i[278:270];
assign i_31=tq_res_i[287:279];
assign i_d_valid=inverse?o_q_valid:tq_en_i;
assign i_d_0 =inverse?o_q_0 :i_0 ;
assign i_d_1 =inverse?o_q_1 :i_1 ;
assign i_d_2 =inverse?o_q_2 :i_2 ;
assign i_d_3 =inverse?o_q_3 :i_3 ;
assign i_d_4 =inverse?o_q_4 :i_4 ;
assign i_d_5 =inverse?o_q_5 :i_5 ;
assign i_d_6 =inverse?o_q_6 :i_6 ;
assign i_d_7 =inverse?o_q_7 :i_7 ;
assign i_d_8 =inverse?o_q_8 :i_8 ;
assign i_d_9 =inverse?o_q_9 :i_9 ;
assign i_d_10=inverse?o_q_10:i_10;
assign i_d_11=inverse?o_q_11:i_11;
assign i_d_12=inverse?o_q_12:i_12;
assign i_d_13=inverse?o_q_13:i_13;
assign i_d_14=inverse?o_q_14:i_14;
assign i_d_15=inverse?o_q_15:i_15;
assign i_d_16=inverse?o_q_16:i_16;
assign i_d_17=inverse?o_q_17:i_17;
assign i_d_18=inverse?o_q_18:i_18;
assign i_d_19=inverse?o_q_19:i_19;
assign i_d_20=inverse?o_q_20:i_20;
assign i_d_21=inverse?o_q_21:i_21;
assign i_d_22=inverse?o_q_22:i_22;
assign i_d_23=inverse?o_q_23:i_23;
assign i_d_24=inverse?o_q_24:i_24;
assign i_d_25=inverse?o_q_25:i_25;
assign i_d_26=inverse?o_q_26:i_26;
assign i_d_27=inverse?o_q_27:i_27;
assign i_d_28=inverse?o_q_28:i_28;
assign i_d_29=inverse?o_q_29:i_29;
assign i_d_30=inverse?o_q_30:i_30;
assign i_d_31=inverse?o_q_31:i_31;
assign i_q_valid=inverse?1'b0:o_d_valid;
assign i_q_0 =inverse?16'd0:o_d_0 ;
assign i_q_1 =inverse?16'd0:o_d_1 ;
assign i_q_2 =inverse?16'd0:o_d_2 ;
assign i_q_3 =inverse?16'd0:o_d_3 ;
assign i_q_4 =inverse?16'd0:o_d_4 ;
assign i_q_5 =inverse?16'd0:o_d_5 ;
assign i_q_6 =inverse?16'd0:o_d_6 ;
assign i_q_7 =inverse?16'd0:o_d_7 ;
assign i_q_8 =inverse?16'd0:o_d_8 ;
assign i_q_9 =inverse?16'd0:o_d_9 ;
assign i_q_10=inverse?16'd0:o_d_10;
assign i_q_11=inverse?16'd0:o_d_11;
assign i_q_12=inverse?16'd0:o_d_12;
assign i_q_13=inverse?16'd0:o_d_13;
assign i_q_14=inverse?16'd0:o_d_14;
assign i_q_15=inverse?16'd0:o_d_15;
assign i_q_16=inverse?16'd0:o_d_16;
assign i_q_17=inverse?16'd0:o_d_17;
assign i_q_18=inverse?16'd0:o_d_18;
assign i_q_19=inverse?16'd0:o_d_19;
assign i_q_20=inverse?16'd0:o_d_20;
assign i_q_21=inverse?16'd0:o_d_21;
assign i_q_22=inverse?16'd0:o_d_22;
assign i_q_23=inverse?16'd0:o_d_23;
assign i_q_24=inverse?16'd0:o_d_24;
assign i_q_25=inverse?16'd0:o_d_25;
assign i_q_26=inverse?16'd0:o_d_26;
assign i_q_27=inverse?16'd0:o_d_27;
assign i_q_28=inverse?16'd0:o_d_28;
assign i_q_29=inverse?16'd0:o_d_29;
assign i_q_30=inverse?16'd0:o_d_30;
assign i_q_31=inverse?16'd0:o_d_31;
assign rec_val_o=inverse?o_d_valid:1'b0;
assign o_0 =inverse?o_d_0 :16'd0;
assign o_1 =inverse?o_d_1 :16'd0;
assign o_2 =inverse?o_d_2 :16'd0;
assign o_3 =inverse?o_d_3 :16'd0;
assign o_4 =inverse?o_d_4 :16'd0;
assign o_5 =inverse?o_d_5 :16'd0;
assign o_6 =inverse?o_d_6 :16'd0;
assign o_7 =inverse?o_d_7 :16'd0;
assign o_8 =inverse?o_d_8 :16'd0;
assign o_9 =inverse?o_d_9 :16'd0;
assign o_10=inverse?o_d_10:16'd0;
assign o_11=inverse?o_d_11:16'd0;
assign o_12=inverse?o_d_12:16'd0;
assign o_13=inverse?o_d_13:16'd0;
assign o_14=inverse?o_d_14:16'd0;
assign o_15=inverse?o_d_15:16'd0;
assign o_16=inverse?o_d_16:16'd0;
assign o_17=inverse?o_d_17:16'd0;
assign o_18=inverse?o_d_18:16'd0;
assign o_19=inverse?o_d_19:16'd0;
assign o_20=inverse?o_d_20:16'd0;
assign o_21=inverse?o_d_21:16'd0;
assign o_22=inverse?o_d_22:16'd0;
assign o_23=inverse?o_d_23:16'd0;
assign o_24=inverse?o_d_24:16'd0;
assign o_25=inverse?o_d_25:16'd0;
assign o_26=inverse?o_d_26:16'd0;
assign o_27=inverse?o_d_27:16'd0;
assign o_28=inverse?o_d_28:16'd0;
assign o_29=inverse?o_d_29:16'd0;
assign o_30=inverse?o_d_30:16'd0;
assign o_31=inverse?o_d_31:16'd0;
assign rec_data_o[8 :0 ]=o_0 ;
assign rec_data_o[17 :9 ]=o_1 ;
assign rec_data_o[26 :18 ]=o_2 ;
assign rec_data_o[35 :27 ]=o_3 ;
assign rec_data_o[44 :36 ]=o_4 ;
assign rec_data_o[53 :45 ]=o_5 ;
assign rec_data_o[62 :54 ]=o_6 ;
assign rec_data_o[71 :63 ]=o_7 ;
assign rec_data_o[80 :72 ]=o_8 ;
assign rec_data_o[89 :81 ]=o_9 ;
assign rec_data_o[98 :90 ]=o_10;
assign rec_data_o[107:99 ]=o_11;
assign rec_data_o[116:108]=o_12;
assign rec_data_o[125:117]=o_13;
assign rec_data_o[134:126]=o_14;
assign rec_data_o[143:135]=o_15;
assign rec_data_o[152:144]=o_16;
assign rec_data_o[161:153]=o_17;
assign rec_data_o[170:162]=o_18;
assign rec_data_o[179:171]=o_19;
assign rec_data_o[188:180]=o_20;
assign rec_data_o[197:189]=o_21;
assign rec_data_o[206:198]=o_22;
assign rec_data_o[215:207]=o_23;
assign rec_data_o[224:216]=o_24;
assign rec_data_o[233:225]=o_25;
assign rec_data_o[242:234]=o_26;
assign rec_data_o[251:243]=o_27;
assign rec_data_o[260:252]=o_28;
assign rec_data_o[269:261]=o_29;
assign rec_data_o[278:270]=o_30;
assign rec_data_o[287:279]=o_31;
always@(*)
case(tq_size_i)
2'b00:rec_idx_o=5'd0;
2'b01:rec_idx_o=(counter_rec<<2);
2'b10:rec_idx_o=(counter_rec<<1);
2'b11:rec_idx_o=counter_rec;
endcase
// ********************************************
//
// Sequential Logic
//
// ********************************************
always@(posedge clk or negedge rst)
if(!rst)
counter_val<=5'd0;
else
if(tq_en_i)
case(tq_size_i)
2'b00:
counter_val<=5'd0;
2'b01:
if(counter_val==5'd1)
counter_val<=5'd0;
else
counter_val<=counter_val+1'b1;
2'b10:
if(counter_val==5'd7)
counter_val<=5'd0;
else
counter_val<=counter_val+1'b1;
2'b11:
if(counter_val==5'd31)
counter_val<=5'd0;
else
counter_val<=counter_val+1'b1;
endcase
always@(posedge clk or negedge rst)
if(!rst)
counter_val_en<=1'b0;
else
case(tq_size_i)
2'b00:counter_val_en<=1'b0;
2'b01:begin
if((counter_val==5'd0)&&(tq_en_i))
counter_val_en<=1'b1;
else if((counter_val==5'd1)&&(tq_en_i))
counter_val_en<=1'b0;
end
2'b10:begin
if((counter_val==5'd0)&&(tq_en_i))
counter_val_en<=1'b1;
else if((counter_val==5'd7)&&(tq_en_i))
counter_val_en<=1'b0;
end
2'b11:begin
if((counter_val==5'd0)&&(tq_en_i))
counter_val_en<=1'b1;
else if((counter_val==5'd31)&&(tq_en_i))
counter_val_en<=1'b0;
end
endcase
always@(posedge clk or negedge rst)
if(!rst)
counter_en<=1'b0;
else
case(tq_size_i)
2'b00:begin
if(tq_en_i)
counter_en<=1'b1;
else if(counter==6'd12)
begin
counter_en<=1'b0;
end
end
2'b01:begin
if(tq_en_i&&(counter_val==5'd1))
counter_en<=1'b1;
else if(counter==6'd16)
begin
counter_en<=1'b0;
end
end
2'b10:begin
if(tq_en_i&&(counter_val==5'd7))
counter_en<=1'b1;
else if(counter==6'd22)
begin
counter_en<=1'b0;
end
end
2'b11:begin
if(tq_en_i&&(counter_val==5'd31))
counter_en<=1'b1;
else if(counter==6'd46)
begin
counter_en<=1'b0;
end
end
endcase
always@(posedge clk or negedge rst)
if(!rst)
counter<=6'd0;
else if(((tq_size_i=='d0)&&(counter==6'd12))||
((tq_size_i=='d1)&&(counter==6'd16))||
((tq_size_i=='d2)&&(counter==6'd22))||
((tq_size_i=='d3)&&(counter==6'd46)))
counter <= 6'b0;
else if(counter_en)
counter<=counter+1'b1;
else
counter<=6'd0;
always@(posedge clk or negedge rst)
if(!rst)
counter_rec<=5'd0;
else
if(rec_val_o)
case(tq_size_i)
2'b00:counter_rec<=5'd0;
2'b01:if(counter_rec==5'd1)
counter_rec<=5'd0;
else
counter_rec<=5'd1;
2'b10:if(counter_rec==5'd7)
counter_rec<=5'd0;
else
counter_rec<=counter_rec+1'b1;
2'b11:if(counter_rec==5'd31)
counter_rec<=5'd0;
else
counter_rec<=counter_rec+1'b1;
endcase
else
counter_rec<=5'd0;
// ********************************************
//
// Sub Modules
//
// ********************************************
dct_top_2d dct_2d(
clk,
rst,
inverse,
i_d_valid,
tq_size_i,
tq_sel_i,
i_d_0,
i_d_1,
i_d_2,
i_d_3,
i_d_4,
i_d_5,
i_d_6,
i_d_7,
i_d_8,
i_d_9,
i_d_10,
i_d_11,
i_d_12,
i_d_13,
i_d_14,
i_d_15,
i_d_16,
i_d_17,
i_d_18,
i_d_19,
i_d_20,
i_d_21,
i_d_22,
i_d_23,
i_d_24,
i_d_25,
i_d_26,
i_d_27,
i_d_28,
i_d_29,
i_d_30,
i_d_31,
o_d_valid,
o_d_0,
o_d_1,
o_d_2,
o_d_3,
o_d_4,
o_d_5,
o_d_6,
o_d_7,
o_d_8,
o_d_9,
o_d_10,
o_d_11,
o_d_12,
o_d_13,
o_d_14,
o_d_15,
o_d_16,
o_d_17,
o_d_18,
o_d_19,
o_d_20,
o_d_21,
o_d_22,
o_d_23,
o_d_24,
o_d_25,
o_d_26,
o_d_27,
o_d_28,
o_d_29,
o_d_30,
o_d_31
);
q_iq q_iq_0(
clk,
rst,
type_i,
qp_i,
tq_en_i,
inverse,
i_q_valid,
tq_size_i,
i_q_0 ,
i_q_1 ,
i_q_2 ,
i_q_3 ,
i_q_4 ,
i_q_5 ,
i_q_6 ,
i_q_7 ,
i_q_8 ,
i_q_9 ,
i_q_10,
i_q_11,
i_q_12,
i_q_13,
i_q_14,
i_q_15,
i_q_16,
i_q_17,
i_q_18,
i_q_19,
i_q_20,
i_q_21,
i_q_22,
i_q_23,
i_q_24,
i_q_25,
i_q_26,
i_q_27,
i_q_28,
i_q_29,
i_q_30,
i_q_31,
cef_data_i,
cef_wen_o,
cef_widx_o,
cef_data_o,
cef_ren_o,
cef_ridx_o,
o_q_valid,
o_q_0 ,
o_q_1 ,
o_q_2 ,
o_q_3 ,
o_q_4 ,
o_q_5 ,
o_q_6 ,
o_q_7 ,
o_q_8 ,
o_q_9 ,
o_q_10,
o_q_11,
o_q_12,
o_q_13,
o_q_14,
o_q_15,
o_q_16,
o_q_17,
o_q_18,
o_q_19,
o_q_20,
o_q_21,
o_q_22,
o_q_23,
o_q_24,
o_q_25,
o_q_26,
o_q_27,
o_q_28,
o_q_29,
o_q_30,
o_q_31
);
endmodule |
module SmallBsf_tb ();
parameter K0_SHIFT = 6; ///< K0 filter term = 2^-K0_SHIFT
parameter K1_SHIFT = 6; ///< K1 filter term = 2^-K1_SHIFT
parameter WIDTH = 16; ///< Width of data path
parameter CLAMP = 1; ///< Set to 1 to clamp the accumulators
parameter FREQ_RATE = 1000000;
reg clk;
reg rst;
reg en;
reg signed [WIDTH-1:0] dataIn;
wire signed [WIDTH-1:0] dataOut;
integer i;
initial begin
clk = 1'b0;
rst = 1'b1;
en = 1'b1;
dataIn = 'd0;
#2 rst = 1'b0;
for (i=1; i<2**16; i=i+1) begin
@(posedge clk) dataIn = $rtoi($sin($itor(i)**2*3.14159/FREQ_RATE)*(2**(WIDTH-2)-1));
end
for (i=1; i<2**16; i=i+1) begin
@(posedge clk) dataIn = $random();
end
$stop();
end
always #1 clk = ~clk;
SmallBsf #(
.K0_SHIFT(K0_SHIFT), ///< K0 filter term = 2^-K0_SHIFT
.K1_SHIFT(K1_SHIFT), ///< K1 filter term = 2^-K1_SHIFT
.WIDTH (WIDTH ), ///< Width of data path
.CLAMP (CLAMP ) ///< Set to 1 to clamp the accumulators
)
uut (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, active high and synchronous
.en(en), ///< Filter enable
.dataIn(dataIn), ///< [WIDTH-1:0] Filter input
.dataOut(dataOut) ///< [WIDTH-1:0] Filter output
);
endmodule
|
`timescale 1ns/1ns
/*
* Trial test bench for clock switching between two asynchronous clocks
*
* Enable the `define STOP_IN_PHI1_D to stop the clocks low for the handover, and omit it to stop in PHI2.
*
* When stopping in PHI1 the clock selection signal must only change in PHI1. Similarly if stopping in PHI2 the
* selection signal must change only in PHI2.
*
* ie for Beeb816 there's not much time to detect whether to switch to the low speed clock when running in a
* high speed mode if STOP_ON_PHI1 is selected - this is probably why we defaulted to stopping in PHI2 instead.
*
*/
//`define STOP_IN_PHI1_D 1
`ifdef STOP_IN_PHI1_D
// to stop in PHI1 enable must be asserted with clock low
`define CHANGEDGE negedge
`else
// to stop in PHI2 enable must be asserted with clock high
`define CHANGEDGE posedge
`endif
`define LSCLK_HALF_CYCLE 500
`define HSCLK_HALF_CYCLE 30
module retimer(clk, din, rst_b, dout);
input din;
input clk;
input rst_b;
output dout;
reg r1_q, r2_q;
assign dout = r2_q & din;
always @ ( `CHANGEDGE clk or negedge rst_b )
if ( !rst_b)
{ r1_q, r2_q} <= 0;
else
{ r1_q, r2_q} <= {din, r1_q};
endmodule
module clkctrl_tb ;
reg reset_b_r;
reg hsclk_by2_r;
reg hsclk_by4_r;
reg lsclk_r;
reg hsclk_r;
reg hienable_r;
wire clkout;
wire loselect_w;
wire hiselect_w;
wire cpuclk_w;
`ifdef STOP_IN_PHI1_D
assign clkout = (hiselect_w & hienable_r & hsclk_by4_r ) | (!hienable_r & loselect_w & lsclk_r);
`else
assign clkout = (!hiselect_w | !hienable_r | hsclk_by4_r ) & (hienable_r | !loselect_w | lsclk_r);
`endif
initial
begin
$dumpvars();
reset_b_r = 0;
lsclk_r = 0;
hsclk_r = 0;
hienable_r = 0;
#500 reset_b_r = 1;
#2500 @ ( `CHANGEDGE clkout);
#10 hienable_r = 1;
#2500 @ ( `CHANGEDGE clkout);
#10 hienable_r = 0;
#2500 @ ( `CHANGEDGE clkout);
#25 hienable_r = 1;
#10000 $finish();
end
always
#`LSCLK_HALF_CYCLE lsclk_r = !lsclk_r ;
always
#`HSCLK_HALF_CYCLE hsclk_r = !hsclk_r ;
always @ (negedge reset_b_r or posedge hsclk_r )
if ( !reset_b_r)
{ hsclk_by2_r, hsclk_by4_r } <= 0;
else
begin
hsclk_by2_r <= !hsclk_by2_r;
hsclk_by4_r <= hsclk_by2_r ^ hsclk_by4_r;
end
retimer ls_retime ( lsclk_r, !hienable_r & !hiselect_w, reset_b_r, loselect_w);
retimer hs_retime ( hsclk_by4_r, hienable_r & !loselect_w, reset_b_r, hiselect_w);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A222OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__A222OI_FUNCTIONAL_PP_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND );
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A222OI_FUNCTIONAL_PP_V |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 14
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_14_top,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_us_2,axi_dwidth_converter_v2_1_14_top,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_us_2,axi_dwidth_converter_v2_1_14_top,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C\
_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_us_2 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_14_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
//
// Paul Gao 06/2019
//
//
`include "bsg_noc_links.vh"
`include "bsg_wormhole_router.vh"
module bsg_wormhole_router_test_node_master
#(// Wormhole link parameters
parameter `BSG_INV_PARAM(flit_width_p )
,parameter dims_p = 2
,parameter int cord_markers_pos_p[dims_p:0] = '{5, 4, 0}
,parameter `BSG_INV_PARAM(len_width_p )
,parameter `BSG_INV_PARAM(num_channels_p )
,parameter `BSG_INV_PARAM(channel_width_p )
,localparam num_nets_lp = 2
,localparam bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(flit_width_p)
,localparam cord_width_lp = cord_markers_pos_p[dims_p]
)
(// Node side
input clk_i
,input reset_i
,input [num_nets_lp-1:0] en_i
,output logic [num_nets_lp-1:0] error_o
,output logic [num_nets_lp-1:0][31:0] sent_o
,output logic [num_nets_lp-1:0][31:0] received_o
// Wormhole side
,input [cord_width_lp-1:0] dest_cord_i
,input [num_nets_lp-1:0][bsg_ready_and_link_sif_width_lp-1:0] link_i
,output [num_nets_lp-1:0][bsg_ready_and_link_sif_width_lp-1:0] link_o
);
localparam width_lp = num_channels_p * channel_width_p;
genvar i;
/********************* Packet definition *********************/
`declare_bsg_wormhole_router_header_s(cord_width_lp,len_width_p,bsg_wormhole_router_header_s);
typedef struct packed {
logic [flit_width_p-$bits(bsg_wormhole_router_header_s)-1:0] data;
bsg_wormhole_router_header_s hdr;
} wormhole_network_header_flit_s;
// synopsys translate_off
initial
begin
assert ($bits(wormhole_network_header_flit_s)-$bits(bsg_wormhole_router_header_s) >= width_lp)
else $error("Packet data width %d is too narrow for data width %d.", $bits(wormhole_network_header_flit_s)-$bits(bsg_wormhole_router_header_s), width_lp);
end
// synopsys translate_on
/********************* Interfacing bsg_noc link *********************/
`declare_bsg_ready_and_link_sif_s(flit_width_p, bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s [num_nets_lp-1:0] link_i_cast, link_o_cast;
for (i = 0; i < num_nets_lp; i++)
begin: noc_cast
assign link_i_cast[i] = link_i[i];
assign link_o[i] = link_o_cast[i];
end
/********************* Master nodes (two of them) *********************/
// ATTENTION: This loopback node is not using fwd and rev networks as usual.
// fwd_link_o sends out fwd packets, rev_link_i receives loopback packets.
// rev_link_o also sends out fwd packets, fwd_link_i receives loopback packets.
for (i = 0; i < num_nets_lp; i++)
begin: mstr
logic resp_in_v;
wormhole_network_header_flit_s resp_in_data;
logic resp_in_yumi;
logic req_out_ready;
wormhole_network_header_flit_s req_out_data;
logic req_out_v;
bsg_one_fifo
#(.width_p(flit_width_p)
) resp_in_fifo
(.clk_i (clk_i)
,.reset_i(reset_i)
,.ready_o(link_o_cast[i].ready_and_rev)
,.v_i (link_i_cast[i].v)
,.data_i (link_i_cast[i].data)
,.v_o (resp_in_v)
,.data_o (resp_in_data)
,.yumi_i (resp_in_yumi)
);
bsg_one_fifo
#(.width_p(flit_width_p)
) req_out_fifo
(.clk_i (clk_i)
,.reset_i(reset_i)
,.ready_o(req_out_ready)
,.v_i (req_out_v)
,.data_i (req_out_data)
,.v_o (link_o_cast[i].v)
,.data_o (link_o_cast[i].data)
,.yumi_i (link_o_cast[i].v & link_i_cast[i].ready_and_rev)
);
logic [width_lp-1:0] data_gen, data_check;
test_bsg_data_gen
#(.channel_width_p(channel_width_p)
,.num_channels_p(num_channels_p)
) gen_out
(.clk_i (clk_i)
,.reset_i(reset_i)
,.yumi_i (req_out_v & req_out_ready)
,.o (data_gen)
);
assign req_out_v = en_i[i];
assign req_out_data.hdr.cord = dest_cord_i;
assign req_out_data.hdr.len = 0;
assign req_out_data.data = {'0, data_gen};
test_bsg_data_gen
#(.channel_width_p(channel_width_p)
,.num_channels_p(num_channels_p)
) gen_in
(.clk_i (clk_i)
,.reset_i(reset_i)
,.yumi_i (resp_in_v)
,.o (data_check)
);
assign resp_in_yumi = resp_in_v;
// Count sent and received packets
bsg_counter_clear_up
#(.max_val_p(1<<32-1)
,.init_val_p(0)
) sent_count
(.clk_i (clk_i)
,.reset_i(reset_i)
,.clear_i(1'b0)
,.up_i (req_out_v & req_out_ready)
,.count_o(sent_o[i])
);
bsg_counter_clear_up
#(.max_val_p(1<<32-1)
,.init_val_p(0)
) received_count
(.clk_i (clk_i)
,.reset_i(reset_i)
,.clear_i(1'b0)
,.up_i (resp_in_v)
,.count_o(received_o[i])
);
always_ff @(posedge clk_i)
if (reset_i)
error_o[i] <= 0;
else
if (resp_in_v && data_check != (width_lp'(resp_in_data.data)))
begin
$error("%m mismatched resp data %x %x",data_check, resp_in_data.data[width_lp-1:0]);
error_o[i] <= 1;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_wormhole_network_test_node_master)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.07.2016 12:23:24
// Design Name:
// Module Name: tb_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_top();
parameter DATA_W_IN_BYTES = 4;
parameter ADDR_W_IN_BITS = 10;
parameter DCADDR_LOW_BIT_W = 8;
parameter DCADDR_STROBE_MEM_SEG = 2;
parameter PERIOD = 1000;
// AXI interface control signals
reg [(ADDR_W_IN_BITS)-1 : 0] S_AXI_AWADDR; // Write channel Protection type. This signal indicates the // privilege and security level of the transaction; and whether // the transaction is a data access or an instruction access.
reg [2 : 0] S_AXI_AWPROT; // Write address valid. This signal indicates that the master signaling // valid write address and control information.
reg S_AXI_AWVALID; // Write address ready. This signal indicates that the slave is ready // to accept an address and associated control signals.
wire S_AXI_AWREADY; // Write data (issued by master; acceped by Slave)
reg [(DATA_W_IN_BYTES*8) - 1:0] S_AXI_WDATA; // Write strobes. This signal indicates which byte lanes hold // valid data. There is one write strobe bit for each eight // bits of the write data bus.
reg [DATA_W_IN_BYTES-1 : 0] S_AXI_WSTRB; // Write valid. This signal indicates that valid write // data and strobes are available.
reg S_AXI_WVALID; // Write ready. This signal indicates that the slave // can accept the write data.
wire S_AXI_WREADY; // Write response. This signal indicates the status // of the write transaction.
wire [1 : 0] S_AXI_BRESP; // Write response valid. This signal indicates that the channel // is signaling a valid write response.
wire S_AXI_BVALID; // Response ready. This signal indicates that the master // can accept a write response.
reg S_AXI_BREADY; // Read address (issued by master; acceped by Slave)
reg [(ADDR_W_IN_BITS)-1 : 0] S_AXI_ARADDR; // Protection type. This signal indicates the privilege // and security level of the transaction; and whether the // transaction is a data access or an instruction access.
reg [2 : 0] S_AXI_ARPROT; // Read address valid. This signal indicates that the channel // is signaling valid read address and control information.
reg S_AXI_ARVALID; // Read address ready. This signal indicates that the slave is // ready to accept an address and associated control signals.
wire S_AXI_ARREADY; // Read data (issued by slave)
wire [(DATA_W_IN_BYTES*8) - 1:0] S_AXI_RDATA; // Read response. This signal indicates the status of the // read transfer.
reg [(DATA_W_IN_BYTES*8) - 1:0] read_data; //
wire [1 : 0] S_AXI_RRESP; // Read valid. This signal indicates that the channel is signaling the required read data.
wire S_AXI_RVALID; // Read ready. This signal indicates that the master can accept the read data and response information.
reg S_AXI_RREADY; //
// Bank IP R/W control strobes
// wire [DCADDR_STROBE_MEM_SEG - 1:0] bank_rd_start; // read start strobe
// wire [DCADDR_STROBE_MEM_SEG - 1:0] bank_rd_done; // read done strobe
// wire [DCADDR_LOW_BIT_W - 1:0] bank_rd_addr; // read address bus
// reg [(DATA_W_IN_BYTES*8) - 1:0] bank_rd_data=0; // read data bus
// wire [DCADDR_STROBE_MEM_SEG - 1:0] bank_wr_start; // write start strobe
// wire [DCADDR_STROBE_MEM_SEG - 1:0] bank_wr_done; // write done strobe
// wire [DCADDR_LOW_BIT_W - 1:0] bank_wr_addr; // write address bus
// wire [(DATA_W_IN_BYTES*8) - 1:0] bank_wr_data; // write data bus
// Clock & reset for registers
reg ACLK; // Clock source
reg ARESETn; // Reset source
// wire [(DATA_W_IN_BYTES*8) - 1:0] bank_rd_data_bus[DCADDR_STROBE_MEM_SEG-1:0]; // read data bus
// wire [(ADDR_W_IN_BITS)-1:DCADDR_LOW_BIT_W] decode_rd_addr; // used external to the block to select the correct returning data
//------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
pc_ctrl #(
.DATA_W_IN_BYTES (DATA_W_IN_BYTES ),
.ADDR_W_IN_BITS (ADDR_W_IN_BITS ),
.DCADDR_LOW_BIT_W (DCADDR_LOW_BIT_W ),
.DCADDR_STROBE_MEM_SEG (DCADDR_STROBE_MEM_SEG )
) jjreg_top_ctrl_i (
.S_AXI_AWADDR (S_AXI_AWADDR ), // Write channel Protection type. This signal indicates the // privilege and security level of the transaction, and whether // the transaction is a data access or an instruction access.
.S_AXI_AWPROT (S_AXI_AWPROT ), // Write address valid. This signal indicates that the master signaling // valid write address and control information.
.S_AXI_AWVALID (S_AXI_AWVALID ), // Write address ready. This signal indicates that the slave is ready // to accept an address and associated control signals.
.S_AXI_AWREADY (S_AXI_AWREADY ), // Write data (issued by master, acceped by Slave)
.S_AXI_WDATA (S_AXI_WDATA ), // Write strobes. This signal indicates which byte lanes hold // valid data. There is one write strobe bit for each eight // bits of the write data bus.
.S_AXI_WSTRB (S_AXI_WSTRB ), // Write valid. This signal indicates that valid write // data and strobes are available.
.S_AXI_WVALID (S_AXI_WVALID ), // Write ready. This signal indicates that the slave // can accept the write data.
.S_AXI_WREADY (S_AXI_WREADY ), // Write response. This signal indicates the status // of the write transaction.
.S_AXI_BRESP (S_AXI_BRESP ), // Write response valid. This signal indicates that the channel // is signaling a valid write response.
.S_AXI_BVALID (S_AXI_BVALID ), // Response ready. This signal indicates that the master // can accept a write response.
.S_AXI_BREADY (S_AXI_BREADY ), // Read address (issued by master, acceped by Slave)
.S_AXI_ARADDR (S_AXI_ARADDR ), // Protection type. This signal indicates the privilege // and security level of the transaction, and whether the // transaction is a data access or an instruction access.
.S_AXI_ARPROT (S_AXI_ARPROT ), // Read address valid. This signal indicates that the channel // is signaling valid read address and control information.
.S_AXI_ARVALID (S_AXI_ARVALID ), // Read address ready. This signal indicates that the slave is // ready to accept an address and associated control signals.
.S_AXI_ARREADY (S_AXI_ARREADY ), // Read data (issued by slave)
.S_AXI_RDATA (S_AXI_RDATA ), // Read response. This signal indicates the status of the // read transfer.
.S_AXI_RRESP (S_AXI_RRESP ), // Read valid. This signal indicates that the channel is signaling the required read data.
.S_AXI_RVALID (S_AXI_RVALID ), // Read ready. This signal indicates that the master can accept the read data and response information.
.S_AXI_RREADY (S_AXI_RREADY ),
.ACLK (ACLK ), // Clock source
.ARESETn (ARESETn ) // Reset source
);
////------------------------------------------------------------------------------
////
////------------------------------------------------------------------------------
//jjreg_axi4lite_regif #(
// .DATA_W_IN_BYTES (DATA_W_IN_BYTES ),
// .ADDR_W_IN_BITS (ADDR_W_IN_BITS ),
// .DCADDR_LOW_BIT_W (DCADDR_LOW_BIT_W ),
// .DCADDR_STROBE_MEM_SEG (DCADDR_STROBE_MEM_SEG )
//) jjreg_axi4lite_regif_i (
// .S_AXI_AWADDR (S_AXI_AWADDR ), // Write channel Protection type. This signal indicates the // privilege and security level of the transaction, and whether // the transaction is a data access or an instruction access.
// .S_AXI_AWPROT (S_AXI_AWPROT ), // Write address valid. This signal indicates that the master signaling // valid write address and control information.
// .S_AXI_AWVALID (S_AXI_AWVALID ), // Write address ready. This signal indicates that the slave is ready // to accept an address and associated control signals.
// .S_AXI_AWREADY (S_AXI_AWREADY ), // Write data (issued by master, acceped by Slave)
// .S_AXI_WDATA (S_AXI_WDATA ), // Write strobes. This signal indicates which byte lanes hold // valid data. There is one write strobe bit for each eight // bits of the write data bus.
// .S_AXI_WSTRB (S_AXI_WSTRB ), // Write valid. This signal indicates that valid write // data and strobes are available.
// .S_AXI_WVALID (S_AXI_WVALID ), // Write ready. This signal indicates that the slave // can accept the write data.
// .S_AXI_WREADY (S_AXI_WREADY ), // Write response. This signal indicates the status // of the write transaction.
// .S_AXI_BRESP (S_AXI_BRESP ), // Write response valid. This signal indicates that the channel // is signaling a valid write response.
// .S_AXI_BVALID (S_AXI_BVALID ), // Response ready. This signal indicates that the master // can accept a write response.
// .S_AXI_BREADY (S_AXI_BREADY ), // Read address (issued by master, acceped by Slave)
// .S_AXI_ARADDR (S_AXI_ARADDR ), // Protection type. This signal indicates the privilege // and security level of the transaction, and whether the // transaction is a data access or an instruction access.
// .S_AXI_ARPROT (S_AXI_ARPROT ), // Read address valid. This signal indicates that the channel // is signaling valid read address and control information.
// .S_AXI_ARVALID (S_AXI_ARVALID ), // Read address ready. This signal indicates that the slave is // ready to accept an address and associated control signals.
// .S_AXI_ARREADY (S_AXI_ARREADY ), // Read data (issued by slave)
// .S_AXI_RDATA (S_AXI_RDATA ), // Read response. This signal indicates the status of the // read transfer.
// .S_AXI_RRESP (S_AXI_RRESP ), // Read valid. This signal indicates that the channel is signaling the required read data.
// .S_AXI_RVALID (S_AXI_RVALID ), // Read ready. This signal indicates that the master can accept the read data and response information.
// .S_AXI_RREADY (S_AXI_RREADY ),
// .reg_bank_rd_start (bank_rd_start ), // read start strobe
// .reg_bank_rd_done (bank_rd_done ), // read done strobe
// .reg_bank_rd_addr (bank_rd_addr ), // read address bus
// .reg_bank_rd_data (bank_rd_data ), // read data bus
// .decode_rd_addr (decode_rd_addr),
// .reg_bank_wr_start (bank_wr_start ), // write start strobe
// .reg_bank_wr_done (bank_wr_done ), // write done strobe
// .reg_bank_wr_addr (bank_wr_addr ), // write address bus
// .reg_bank_wr_data (bank_wr_data ), // write data bus
// .ACLK (ACLK ), // Clock source
// .ARESETn (ARESETn ) // Reset source
//);
//always @(*) begin
// case(decode_rd_addr)
// 0:bank_rd_data = bank_rd_data_bus[0];
// 1:bank_rd_data = bank_rd_data_bus[1];
// 2:bank_rd_data = bank_rd_data_bus[2];
// default:bank_rd_data = bank_rd_data_bus[0];
// endcase
//end
//jjreg_tmp_reg_basic #(
// .DATA_W_IN_BYTES (DATA_W_IN_BYTES ),
// .ADDR_W_IN_BITS (ADDR_W_IN_BITS ),
// .DCADDR_LOW_BIT_W (DCADDR_LOW_BIT_W )
//) jjreg_tmp_reg_basic_0_i (
// .reg_bank_rd_start (bank_rd_start[0] ), // read start strobe
// .reg_bank_rd_done (bank_rd_done[0] ), // read done strobe
// .reg_bank_rd_addr (bank_rd_addr ), // read address bus
// .reg_bank_rd_data (bank_rd_data_bus[0] ), // read data bus
// .reg_bank_wr_start (bank_wr_start[0] ), // write start strobe
// .reg_bank_wr_done (bank_wr_done[0] ), // write done strobe
// .reg_bank_wr_addr (bank_wr_addr ), // write address bus
// .reg_bank_wr_data (bank_wr_data ), // write data bus
// .ACLK (ACLK ), // Clock source
// .ARESETn (ARESETn ) // Reset source
//);
//jjreg_tmp_reg_basic #(
// .DATA_W_IN_BYTES (DATA_W_IN_BYTES ),
// .ADDR_W_IN_BITS (ADDR_W_IN_BITS ),
// .DCADDR_LOW_BIT_W (DCADDR_LOW_BIT_W )
//) jjreg_tmp_reg_basic_1_i (
// .reg_bank_rd_start (bank_rd_start[1] ), // read start strobe
// .reg_bank_rd_done (bank_rd_done[1] ), // read done strobe
// .reg_bank_rd_addr (bank_rd_addr ), // read address bus
// .reg_bank_rd_data (bank_rd_data_bus[1] ), // read data bus
// .reg_bank_wr_start (bank_wr_start[1] ), // write start strobe
// .reg_bank_wr_done (bank_wr_done[1] ), // write done strobe
// .reg_bank_wr_addr (bank_wr_addr ), // write address bus
// .reg_bank_wr_data (bank_wr_data ), // write data bus
// .ACLK (ACLK ), // Clock source
// .ARESETn (ARESETn ) // Reset source
//);
//jjreg_tmp_reg_basic #(
// .DATA_W_IN_BYTES (DATA_W_IN_BYTES ),
// .ADDR_W_IN_BITS (ADDR_W_IN_BITS ),
// .DCADDR_LOW_BIT_W (DCADDR_LOW_BIT_W )
//) jjreg_tmp_reg_basic_2_i (
// .reg_bank_rd_start (bank_rd_start[2] ), // read start strobe
// .reg_bank_rd_done (bank_rd_done[2] ), // read done strobe
// .reg_bank_rd_addr (bank_rd_addr ), // read address bus
// .reg_bank_rd_data (bank_rd_data_bus[2] ), // read data bus
// .reg_bank_wr_start (bank_wr_start[2] ), // write start strobe
// .reg_bank_wr_done (bank_wr_done[2] ), // write done strobe
// .reg_bank_wr_addr (bank_wr_addr ), // write address bus
// .reg_bank_wr_data (bank_wr_data ), // write data bus
// .ACLK (ACLK ), // Clock source
// .ARESETn (ARESETn ) // Reset source
//);
//------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
always begin
ACLK = 1'b0;
#(PERIOD/2) ACLK = 1'b1;
#(PERIOD/2);
end
//------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
initial begin
wait_aclk_cycles_for_to(200);
end
initial begin
ARESETn = 0;
initialise_axi_inputs();
wait_aclk_cycles(20);
ARESETn = 1;
wait_aclk_cycles(20);
// bank_rd_data = 44;
axi_read('h20,read_data);
axi_write('h20,33);
// bank_rd_data = 49;
axi_read('h20,read_data);
wait_aclk_cycles(20);
axi_write('h00_00,'h0);
axi_write('h00_00,'hff);
axi_write('h01_00,'h1);
axi_write('h02_00,'h2);
axi_read('h00_00,read_data);
axi_read('h01_00,read_data);
axi_read('h02_00,read_data);
axi_read('h04_00,read_data);
$stop;
end
task initialise_axi_inputs;
begin
S_AXI_AWADDR = 'd0;
S_AXI_AWPROT = 'd0;
S_AXI_AWVALID = 'd0;
S_AXI_WDATA = 'd0;
S_AXI_WSTRB = 'd0;
S_AXI_WVALID = 'd0;
S_AXI_BREADY = 'd0;
S_AXI_ARADDR = 'd0;
S_AXI_ARPROT = 'd0;
S_AXI_ARVALID = 'd0;
S_AXI_RREADY = 'd0;
end
endtask
//------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
task axi_read;
input [(ADDR_W_IN_BITS)-1 : 0] ADDR;
output [(DATA_W_IN_BYTES*8) - 1:0] DATA;
begin
@(posedge ACLK);
S_AXI_ARADDR <= ADDR;
S_AXI_ARPROT <= 'd0;
S_AXI_ARVALID <= 'd1;
S_AXI_RREADY <= 'd1; // This can be high as xfer starts
@(posedge ACLK);
while( S_AXI_ARREADY == 'd0 )
@(posedge ACLK);
S_AXI_ARVALID <= 'd0;
while( S_AXI_RVALID == 'd0 )
@(posedge ACLK);
S_AXI_RREADY <= 'd0;
DATA <= S_AXI_RDATA;
// S_AXI_RRESP
end
endtask
task axi_write;
input [(ADDR_W_IN_BITS)-1 : 0] ADDR;
input [(DATA_W_IN_BYTES*8) - 1:0] DATA;
begin
@(posedge ACLK);
S_AXI_AWADDR <= ADDR;
S_AXI_AWPROT <= 'd0;
S_AXI_AWVALID <= 'd1;
S_AXI_WVALID <= 'd1;
S_AXI_WDATA <= DATA;
@(posedge ACLK);
while( (S_AXI_AWREADY & S_AXI_WREADY) == 'd0 )
@(posedge ACLK);
S_AXI_AWVALID <= 'd0;
S_AXI_WVALID <= 'd0;
S_AXI_BREADY <= 'd1;
while( S_AXI_BVALID == 'd0 )
@(posedge ACLK);
S_AXI_BREADY <= 'd0;
// @(posedge ACLK);
// S_AXI_BREADY <= 'd0;
end
endtask
task wait_aclk_cycles_for_to;
input [31 : 0] cycles;
begin
while( cycles > 'd0 ) begin
@(posedge ACLK);
cycles = cycles - 'd1;
end
$display("---ERROR simulation timeout!");
$stop;
end
endtask
task wait_aclk_cycles;
input [31 : 0] cycles;
begin
while( cycles > 'd0 ) begin
@(posedge ACLK);
cycles = cycles - 'd1;
end
end
endtask
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// RxfifoBI.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
//`include "timescale.v"
`include "wishBoneBus_h.v"
module RxfifoBI (
address,
writeEn,
strobe_i,
busClk,
usbClk,
rstSyncToBusClk,
fifoSelect,
fifoDataIn,
busDataIn,
busDataOut,
fifoREn,
forceEmptySyncToUsbClk,
forceEmptySyncToBusClk,
numElementsInFifo
);
input [2:0] address;
input writeEn;
input strobe_i;
input busClk;
input usbClk;
input rstSyncToBusClk;
input [7:0] fifoDataIn;
input [7:0] busDataIn;
output [7:0] busDataOut;
output fifoREn;
output forceEmptySyncToUsbClk;
output forceEmptySyncToBusClk;
input [15:0] numElementsInFifo;
input fifoSelect;
wire [2:0] address;
wire writeEn;
wire strobe_i;
wire busClk;
wire usbClk;
wire rstSyncToBusClk;
wire [7:0] fifoDataIn;
wire [7:0] busDataIn;
reg [7:0] busDataOut;
reg fifoREn;
wire forceEmptySyncToUsbClk;
wire forceEmptySyncToBusClk;
wire [15:0] numElementsInFifo;
wire fifoSelect;
reg forceEmptyReg;
reg forceEmpty;
reg forceEmptyToggle;
reg [2:0] forceEmptyToggleSyncToUsbClk;
//sync write
always @(posedge busClk)
begin
if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
forceEmpty <= 1'b1;
else
forceEmpty <= 1'b0;
end
//detect rising edge of 'forceEmpty', and generate toggle signal
always @(posedge busClk) begin
if (rstSyncToBusClk == 1'b1) begin
forceEmptyReg <= 1'b0;
forceEmptyToggle <= 1'b0;
end
else begin
if (forceEmpty == 1'b1)
forceEmptyReg <= 1'b1;
else
forceEmptyReg <= 1'b0;
if (forceEmpty == 1'b1 && forceEmptyReg == 1'b0)
forceEmptyToggle <= ~forceEmptyToggle;
end
end
assign forceEmptySyncToBusClk = (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) ? 1'b1 : 1'b0;
// double sync across clock domains to generate 'forceEmptySyncToUsbClk'
always @(posedge usbClk) begin
forceEmptyToggleSyncToUsbClk <= {forceEmptyToggleSyncToUsbClk[1:0], forceEmptyToggle};
end
assign forceEmptySyncToUsbClk = forceEmptyToggleSyncToUsbClk[2] ^ forceEmptyToggleSyncToUsbClk[1];
// async read mux
always @(address or fifoDataIn or numElementsInFifo)
begin
case (address)
`FIFO_DATA_REG : busDataOut <= fifoDataIn;
`FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
`FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
default: busDataOut <= 8'h00;
endcase
end
//generate fifo read strobe
always @(address or writeEn or strobe_i or fifoSelect) begin
if (address == `FIFO_DATA_REG && writeEn == 1'b0 &&
strobe_i == 1'b1 && fifoSelect == 1'b1)
fifoREn <= 1'b1;
else
fifoREn <= 1'b0;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: demux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple demultiplexer
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module demux
#(
parameter C_OUTPUTS = 12,
parameter C_WIDTH = 1
)
(
input [C_WIDTH-1:0] WR_DATA,// Inputs
input [clog2s(C_OUTPUTS)-1:0] WR_SEL,// Selector
output [C_OUTPUTS*C_WIDTH-1:0] RD_DATA// Outputs
);
`include "functions.vh"
genvar i;
reg [C_OUTPUTS*C_WIDTH-1:0] _rOut;
assign RD_DATA = _rOut;
always @(*) begin
_rOut = 0;
_rOut[C_WIDTH*WR_SEL +: C_WIDTH] = WR_DATA;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_PP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_PP_V |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_sw (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 9: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 9: 0] d1_data_in;
reg [ 9: 0] d2_data_in;
wire [ 9: 0] data_in;
reg [ 9: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 9: 0] edge_detect;
wire irq;
reg [ 9: 0] irq_mask;
wire [ 9: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({10 {(address == 0)}} & data_in) |
({10 {(address == 2)}} & irq_mask) |
({10 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[9 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[4] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[4] <= 0;
else if (edge_detect[4])
edge_capture[4] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[5] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[5] <= 0;
else if (edge_detect[5])
edge_capture[5] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[6] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[6] <= 0;
else if (edge_detect[6])
edge_capture[6] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[7] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[7] <= 0;
else if (edge_detect[7])
edge_capture[7] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[8] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[8] <= 0;
else if (edge_detect[8])
edge_capture[8] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[9] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[9] <= 0;
else if (edge_detect[9])
edge_capture[9] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
`default_nettype none
// ============================================================================
module top
(
input wire clk,
input wire [7:0] sw,
output wire [7:0] led,
input wire jc1,
output wire jc2,
input wire jc3,
output wire jc4
);
// ============================================================================
// MMCM
wire clk_fb;
wire [3:0] oclk;
wire [3:0] gclk;
MMCME2_ADV #
(
.BANDWIDTH ("HIGH"),
.COMPENSATION ("INTERNAL"),
.CLKIN1_PERIOD (10.0),
.CLKIN2_PERIOD (10.0),
.CLKFBOUT_MULT_F (10.5),
.CLKFBOUT_PHASE (0),
.CLKOUT0_DIVIDE_F (12.5),
.CLKOUT0_DUTY_CYCLE (0.50),
.CLKOUT0_PHASE (45.0),
.CLKOUT1_DIVIDE (32),
.CLKOUT1_DUTY_CYCLE (0.53125),
.CLKOUT1_PHASE (90.0),
.CLKOUT2_DIVIDE (48),
.CLKOUT2_DUTY_CYCLE (0.50),
.CLKOUT2_PHASE (135.0),
.CLKOUT3_DIVIDE (64),
.CLKOUT3_DUTY_CYCLE (0.50),
.CLKOUT3_PHASE (45.0),
.STARTUP_WAIT ("FALSE")
)
mmcm
(
.CLKIN1 (clk),
.CLKIN2 (clk),
.CLKINSEL (1'b0),
.RST (sw[0]),
.PWRDWN (1'b0),
.CLKFBIN (clk_fb),
.CLKFBOUT (clk_fb),
.CLKOUT0 (oclk[0]),
.CLKOUT1 (oclk[1]),
.CLKOUT2 (oclk[2]),
.CLKOUT3 (oclk[3])
);
// ============================================================================
// Outputs
genvar i;
generate for (i=0; i<4; i=i+1) begin
BUFG bufg (.I(oclk[i]), .O(gclk[i]));
reg r;
always @(posedge gclk[i])
r <= ~r;
assign led[i] = r;
end endgenerate
// Unused
assign led[4] = 1'b0;
assign led[5] = 1'b0;
assign led[6] = 1'b0;
assign led[7] = |sw;
assign jc2 = jc1;
assign jc4 = jc3;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_OV2_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SDFRTP_OV2_BEHAVIORAL_V
/**
* sdfrtp_ov2: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfrtp_ov2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_OV2_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/03/2013 02:04:30 PM
// Design Name:
// Module Name: axi_read_controller
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module axi_read_controller # (
parameter TCQ = 1,
parameter M_AXI_TDATA_WIDTH = 32,
parameter M_AXI_ADDR_WIDTH = 32,
parameter OUTSTANDING_READS = 5,
parameter BAR0AXI = 64'h00000000,
parameter BAR1AXI = 64'h00000000,
parameter BAR2AXI = 64'h00000000,
parameter BAR3AXI = 64'h00000000,
parameter BAR4AXI = 64'h00000000,
parameter BAR5AXI = 64'h00000000,
parameter BAR0SIZE = 12,
parameter BAR1SIZE = 12,
parameter BAR2SIZE = 12,
parameter BAR3SIZE = 12,
parameter BAR4SIZE = 12,
parameter BAR5SIZE = 12
) (
input m_axi_aclk,
input m_axi_aresetn,
output [M_AXI_TDATA_WIDTH-1 : 0] m_axi_araddr,
output [2 : 0] m_axi_arprot,
output m_axi_arvalid,
input m_axi_arready,
input [M_AXI_TDATA_WIDTH-1 : 0] m_axi_rdata,
input [1 : 0] m_axi_rresp,
input m_axi_rvalid,
output m_axi_rready,
//Memory Request TLP Info
input mem_req_valid,
output mem_req_ready,
input [2:0] mem_req_bar_hit,
input [31:0] mem_req_pcie_address,
input [3:0] mem_req_byte_enable,
input mem_req_write_readn,
input mem_req_phys_func,
input [31:0] mem_req_write_data,
//Completion Data Coming back
output axi_cpld_valid,
input axi_cpld_ready,
output [31:0] axi_cpld_data
);
reg [31:0] m_axi_addr_c;
reg [31:0] m_axi_araddr_r;
reg m_axi_arvalid_r;
reg mem_req_ready_r;
localparam IDLE = 4'b0001;
localparam READ_REQ = 4'b0010;
//localparam <state3> = 4'b0100;
//localparam <state4> = 4'b1000;
reg [3:0] aximm_ar_sm = IDLE;
reg [3:0] aximm_rd_sm = IDLE;
always @(posedge m_axi_aclk)
if ( !m_axi_aresetn ) begin
aximm_ar_sm <= IDLE;
m_axi_araddr_r <= #TCQ 32'd0;
m_axi_arvalid_r <= #TCQ 1'b0;
mem_req_ready_r <= #TCQ 1'b0;
end else
case (aximm_ar_sm)
IDLE : begin
if ( mem_req_valid & !mem_req_write_readn ) begin
aximm_ar_sm <= #TCQ READ_REQ;
m_axi_araddr_r <= #TCQ m_axi_addr_c;
m_axi_arvalid_r <= #TCQ 1'b1;
mem_req_ready_r <= #TCQ 1'b0;
end else begin
m_axi_arvalid_r <= #TCQ 1'b0;
mem_req_ready_r <= #TCQ 1'b1;
end
end
READ_REQ : begin
if (m_axi_arready) begin
aximm_ar_sm <= #TCQ IDLE;
m_axi_arvalid_r <= #TCQ 1'b0;
mem_req_ready_r <= #TCQ 1'b1;
end
end
default : begin // Fault Recovery
aximm_ar_sm <= #TCQ IDLE;
end
endcase
assign m_axi_arvalid = m_axi_arvalid_r;
assign m_axi_arprot = 0;
assign m_axi_araddr = m_axi_araddr_r;
assign mem_req_ready = mem_req_ready_r;
assign axi_cpld_valid = m_axi_rvalid;
assign m_axi_rready = axi_cpld_ready;
assign axi_cpld_data = m_axi_rdata;
always @(mem_req_bar_hit, mem_req_pcie_address)
case (mem_req_bar_hit)
3'b000: m_axi_addr_c <= { BAR0AXI[M_AXI_ADDR_WIDTH-1:BAR0SIZE], mem_req_pcie_address[BAR0SIZE-1:2],2'b00};
3'b001: m_axi_addr_c <= { BAR1AXI[M_AXI_ADDR_WIDTH-1:BAR1SIZE], mem_req_pcie_address[BAR1SIZE-1:2],2'b00};
3'b010: m_axi_addr_c <= { BAR2AXI[M_AXI_ADDR_WIDTH-1:BAR2SIZE], mem_req_pcie_address[BAR2SIZE-1:2],2'b00};
3'b011: m_axi_addr_c <= { BAR3AXI[M_AXI_ADDR_WIDTH-1:BAR3SIZE], mem_req_pcie_address[BAR3SIZE-1:2],2'b00};
3'b100: m_axi_addr_c <= { BAR4AXI[M_AXI_ADDR_WIDTH-1:BAR4SIZE], mem_req_pcie_address[BAR4SIZE-1:2],2'b00};
3'b101: m_axi_addr_c <= { BAR5AXI[M_AXI_ADDR_WIDTH-1:BAR5SIZE], mem_req_pcie_address[BAR5SIZE-1:2],2'b00};
3'b110: m_axi_addr_c <= 32'd0;
3'b111: m_axi_addr_c <= 32'd0;
endcase
endmodule |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart #(
parameter csr_addr = 4'h0,
parameter clk_freq = 100000000,
parameter baud = 115200
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output rx_irq,
output tx_irq,
input uart_rxd,
output uart_txd
);
reg [15:0] divisor;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire tx_wr;
uart_transceiver transceiver(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
.divisor(divisor),
.rx_data(rx_data),
.rx_done(rx_irq),
.tx_data(tx_data),
.tx_wr(tx_wr),
.tx_done(tx_irq)
);
/* CSR interface */
wire csr_selected = csr_a[13:10] == csr_addr;
assign tx_data = csr_di[7:0];
assign tx_wr = csr_selected & csr_we & (csr_a[0] == 1'b0);
parameter default_divisor = clk_freq/baud/16;
always @(posedge sys_clk) begin
if(sys_rst) begin
divisor <= default_divisor;
csr_do <= 32'd0;
end else begin
csr_do <= 32'd0;
if(csr_selected) begin
case(csr_a[0])
1'b0: csr_do <= rx_data;
1'b1: csr_do <= divisor;
endcase
if(csr_we) begin
if(csr_a[0] == 1'b1)
divisor <= csr_di[15:0];
end
end
end
end
endmodule
|
Require Import Coq.ZArith.Zpower Coq.ZArith.ZArith.
Require Import Crypto.Util.ListUtil.
Require Import Crypto.Util.ZUtil.
Require Crypto.BaseSystem.
Require Import Coq.Lists.List.
Local Open Scope Z_scope.
Section Pow2Base.
Context (limb_widths : list Z).
Local Notation "w[ i ]" := (nth_default 0 limb_widths i).
Fixpoint base_from_limb_widths limb_widths :=
match limb_widths with
| nil => nil
| w :: lw => 1 :: map (Z.mul (two_p w)) (base_from_limb_widths lw)
end.
Local Notation base := (base_from_limb_widths limb_widths).
Definition bounded us := forall i, 0 <= nth_default 0 us i < 2 ^ w[i].
Definition upper_bound := 2 ^ (sum_firstn limb_widths (length limb_widths)).
Function decode_bitwise' us i acc :=
match i with
| O => acc
| S i' => decode_bitwise' us i' (Z.lor (nth_default 0 us i') (Z.shiftl acc w[i']))
end.
Definition decode_bitwise us := decode_bitwise' us (length us) 0.
(* i is current index, counts down *)
Fixpoint encode' z i :=
match i with
| O => nil
| S i' => let lw := sum_firstn limb_widths in
encode' z i' ++ (Z.shiftr (Z.land z (Z.ones (lw i))) (lw i')) :: nil
end.
Definition encodeZ x:= encode' x (length limb_widths).
(** ** Carrying *)
Section carrying.
(** Here we implement addition and multiplication with simple
carrying. *)
Notation log_cap i := (nth_default 0 limb_widths i).
Definition add_to_nth n (x:Z) xs :=
update_nth n (fun y => x + y) xs.
Definition carry_single i := fun di =>
(Z.pow2_mod di (log_cap i),
Z.shiftr di (log_cap i)).
(* [fi] is fed [length us] and [S i] and produces the index of
the digit to which value should be added;
[fc] modifies the carried value before adding it to that digit *)
Definition carry_gen fc fi i := fun us =>
let i := fi i in
let di := nth_default 0 us i in
let '(di', ci) := carry_single i di in
let us' := set_nth i di' us in
add_to_nth (fi (S i)) (fc ci) us'.
(* carry_simple does not modify the carried value, and always adds it
to the digit with index [S i] *)
Definition carry_simple := carry_gen (fun ci => ci) (fun i => i).
Definition carry_simple_sequence is us := fold_right carry_simple us is.
Fixpoint make_chain i :=
match i with
| O => nil
| S i' => i' :: make_chain i'
end.
Definition full_carry_chain := make_chain (length limb_widths).
Definition carry_simple_full := carry_simple_sequence full_carry_chain.
Definition carry_simple_add us vs := carry_simple_full (BaseSystem.add us vs).
Definition carry_simple_sub us vs := carry_simple_full (BaseSystem.sub us vs).
Definition carry_simple_mul out_base us vs := carry_simple_full (BaseSystem.mul out_base us vs).
End carrying.
End Pow2Base.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD1_BEHAVIORAL_PP_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD1_BEHAVIORAL_PP_V |
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2011, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// UART Transmitter with integral 16 byte FIFO buffer
//
// 8 bit, no parity, 1 stop bit
//
// This module was made for use with Spartan-6 Generation Devices and is also ideally
// suited for use with Virtex-6 and 7-Series devices.
//
// Version 1 - 8th July 2011.
// Derived from uart_tx6.vhd Version 1 (31st March 2011) by Nick Sawyer.
//
// Ken Chapman
// Xilinx Ltd
// Benchmark House
// 203 Brooklands Road
// Weybridge
// Surrey KT13 ORH
// United Kingdom
//
// [email protected]
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Format of this file.
//
// The module defines the implementation of the logic using Xilinx primitives.
// These ensure predictable synthesis results and maximise the density of the
// implementation. The Unisim Library is used to define Xilinx primitives. It is also
// used during simulation.
// The source can be viewed at %XILINX%\verilog\src\unisims\
//
///////////////////////////////////////////////////////////////////////////////////////////
//
`timescale 1 ps / 1ps
module uart_tx6 (
input [7:0] data_in,
input buffer_write,
input buffer_reset,
input en_16_x_baud,
output serial_out,
output buffer_data_present,
output buffer_half_full,
output buffer_full,
input clk );
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// wires used in uart_tx6
//
///////////////////////////////////////////////////////////////////////////////////////////
//
wire [7:0] store_data;
wire [7:0] data;
wire [3:0] pointer_value;
wire [3:0] pointer;
wire en_pointer;
wire zero;
wire full_int;
wire data_present_value;
wire data_present_int;
wire [3:0] sm_value;
wire [3:0] sm;
wire [3:0] div_value;
wire [3:0] div;
wire lsb_data;
wire msb_data;
wire last_bit;
wire serial_data;
wire next_value;
wire next_bit;
wire buffer_read_value;
wire buffer_read;
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Start of uart_tx6 circuit description
//
///////////////////////////////////////////////////////////////////////////////////////////
//
genvar i;
// SRL16E data storage
generate
for (i = 0 ; i <= 7 ; i = i+1)
begin : data_width_loop
(* HBLKNM = "uart_tx6_5" *)
SRL16E #(
.INIT (16'h0000))
storage_srl (
.D (data_in[i]),
.CE (buffer_write),
.CLK (clk),
.A0 (pointer[0]),
.A1 (pointer[1]),
.A2 (pointer[2]),
.A3 (pointer[3]),
.Q (store_data[i]));
(* HBLKNM = "uart_tx6_5" *)
FD storage_flop(
.D (store_data[i]),
.Q (data[i]),
.C (clk));
end //generate data_width_loop;
endgenerate
(* HBLKNM = "uart_tx6_1" *)
LUT6 #(
.INIT (64'hFF00FE00FF80FF00))
pointer3_lut(
.I0 (pointer[0]),
.I1 (pointer[1]),
.I2 (pointer[2]),
.I3 (pointer[3]),
.I4 (buffer_write),
.I5 (buffer_read),
.O (pointer_value[3]));
(* HBLKNM = "uart_tx6_1" *)
FDR pointer3_flop(
.D (pointer_value[3]),
.Q (pointer[3]),
.R (buffer_reset),
.C (clk));
(* HBLKNM = "uart_tx6_1" *)
LUT6 #(
.INIT (64'hF0F0E1E0F878F0F0))
pointer2_lut(
.I0 (pointer[0]),
.I1 (pointer[1]),
.I2 (pointer[2]),
.I3 (pointer[3]),
.I4 (buffer_write),
.I5 (buffer_read),
.O (pointer_value[2]));
(* HBLKNM = "uart_tx6_1" *)
FDR pointer2_flop(
.D (pointer_value[2]),
.Q (pointer[2]),
.R (buffer_reset),
.C (clk));
(* HBLKNM = "uart_tx6_1" *)
LUT6_2 #(
.INIT (64'hCC9060CCAA5050AA))
pointer01_lut(
.I0 (pointer[0]),
.I1 (pointer[1]),
.I2 (en_pointer),
.I3 (buffer_write),
.I4 (buffer_read),
.I5 (1'b1),
.O5 (pointer_value[0]),
.O6 (pointer_value[1]));
(* HBLKNM = "uart_tx6_1" *)
FDR pointer1_flop(
.D (pointer_value[1]),
.Q (pointer[1]),
.R (buffer_reset),
.C (clk));
(* HBLKNM = "uart_tx6_1" *)
FDR pointer0_flop(
.D (pointer_value[0]),
.Q (pointer[0]),
.R (buffer_reset),
.C (clk));
(* HBLKNM = "uart_tx6_1" *)
LUT6_2 #(
.INIT (64'hF4FCF4FC040004C0))
data_present_lut(
.I0 (zero),
.I1 (data_present_int),
.I2 (buffer_write),
.I3 (buffer_read),
.I4 (full_int),
.I5 (1'b1),
.O5 (en_pointer),
.O6 (data_present_value));
(* HBLKNM = "uart_tx6_1" *)
FDR data_present_flop(
.D (data_present_value),
.Q (data_present_int),
.R (buffer_reset),
.C (clk));
(* HBLKNM = "uart_tx6_4" *)
LUT6_2 #(
.INIT (64'h0001000080000000))
full_lut(
.I0 (pointer[0]),
.I1 (pointer[1]),
.I2 (pointer[2]),
.I3 (pointer[3]),
.I4 (1'b1),
.I5 (1'b1),
.O5 (full_int),
.O6 (zero));
(* HBLKNM = "uart_tx6_4" *)
LUT6 #(
.INIT (64'hFF00F0F0CCCCAAAA))
lsb_data_lut(
.I0 (data[0]),
.I1 (data[1]),
.I2 (data[2]),
.I3 (data[3]),
.I4 (sm[0]),
.I5 (sm[1]),
.O (lsb_data));
(* HBLKNM = "uart_tx6_4" *)
LUT6 #(
.INIT (64'hFF00F0F0CCCCAAAA))
msb_data_lut(
.I0 (data[4]),
.I1 (data[5]),
.I2 (data[6]),
.I3 (data[7]),
.I4 (sm[0]),
.I5 (sm[1]),
.O (msb_data));
(* HBLKNM = "uart_tx6_4" *)
LUT6_2 #(
.INIT (64'hCFAACC0F0FFFFFFF))
serial_lut(
.I0 (lsb_data),
.I1 (msb_data),
.I2 (sm[1]),
.I3 (sm[2]),
.I4 (sm[3]),
.I5 (1'b1),
.O5 (last_bit),
.O6 (serial_data));
(* HBLKNM = "uart_tx6_4" *)
FD serial_flop(
.D (serial_data),
.Q (serial_out),
.C (clk));
(* HBLKNM = "uart_tx6_2" *)
LUT6 #(
.INIT (64'h85500000AAAAAAAA))
sm0_lut(
.I0 (sm[0]),
.I1 (sm[1]),
.I2 (sm[2]),
.I3 (sm[3]),
.I4 (data_present_int),
.I5 (next_bit),
.O (sm_value[0]));
(* HBLKNM = "uart_tx6_2" *)
FD sm0_flop(
.D (sm_value[0]),
.Q (sm[0]),
.C (clk));
(* HBLKNM = "uart_tx6_2" *)
LUT6 #(
.INIT (64'h26610000CCCCCCCC))
sm1_lut(
.I0 (sm[0]),
.I1 (sm[1]),
.I2 (sm[2]),
.I3 (sm[3]),
.I4 (data_present_int),
.I5 (next_bit),
.O (sm_value[1]));
(* HBLKNM = "uart_tx6_2" *)
FD sm1_flop(
.D (sm_value[1]),
.Q (sm[1]),
.C (clk));
(* HBLKNM = "uart_tx6_2" *)
LUT6 #(
.INIT (64'h88700000F0F0F0F0))
sm2_lut(
.I0 (sm[0]),
.I1 (sm[1]),
.I2 (sm[2]),
.I3 (sm[3]),
.I4 (data_present_int),
.I5 (next_bit),
.O (sm_value[2]));
(* HBLKNM = "uart_tx6_2" *)
FD sm2_flop(
.D (sm_value[2]),
.Q (sm[2]),
.C (clk));
(* HBLKNM = "uart_tx6_2" *)
LUT6 #(
.INIT (64'h87440000FF00FF00))
sm3_lut(
.I0 (sm[0]),
.I1 (sm[1]),
.I2 (sm[2]),
.I3 (sm[3]),
.I4 (data_present_int),
.I5 (next_bit),
.O (sm_value[3]));
(* HBLKNM = "uart_tx6_2" *)
FD sm3_flop(
.D (sm_value[3]),
.Q (sm[3]),
.C (clk));
(* HBLKNM = "uart_tx6_3" *)
LUT6_2 #(
.INIT (64'h6C0000005A000000))
div01_lut(
.I0 (div[0]),
.I1 (div[1]),
.I2 (en_16_x_baud),
.I3 (1'b1),
.I4 (1'b1),
.I5 (1'b1),
.O5 (div_value[0]),
.O6 (div_value[1]));
(* HBLKNM = "uart_tx6_3" *)
FD div0_flop(
.D (div_value[0]),
.Q (div[0]),
.C (clk));
(* HBLKNM = "uart_tx6_3" *)
FD div1_flop(
.D (div_value[1]),
.Q (div[1]),
.C (clk));
(* HBLKNM = "uart_tx6_3" *)
LUT6_2 #(
.INIT (64'h7F80FF007878F0F0))
div23_lut(
.I0 (div[0]),
.I1 (div[1]),
.I2 (div[2]),
.I3 (div[3]),
.I4 (en_16_x_baud),
.I5 (1'b1),
.O5 (div_value[2]),
.O6 (div_value[3]));
(* HBLKNM = "uart_tx6_3" *)
FD div2_flop(
.D (div_value[2]),
.Q (div[2]),
.C (clk));
(* HBLKNM = "uart_tx6_3" *)
FD div3_flop(
.D (div_value[3]),
.Q (div[3]),
.C (clk));
(* HBLKNM = "uart_tx6_3" *)
LUT6_2 #(
.INIT (64'h0000000080000000))
next_lut(
.I0 (div[0]),
.I1 (div[1]),
.I2 (div[2]),
.I3 (div[3]),
.I4 (en_16_x_baud),
.I5 (last_bit),
.O5 (next_value),
.O6 (buffer_read_value));
(* HBLKNM = "uart_tx6_3" *)
FD next_flop(
.D (next_value),
.Q (next_bit),
.C (clk));
(* HBLKNM = "uart_tx6_3" *)
FD read_flop(
.D (buffer_read_value),
.Q (buffer_read),
.C (clk));
// assign internal wires to outputs
assign buffer_full = full_int;
assign buffer_half_full = pointer[3];
assign buffer_data_present = data_present_int;
endmodule
///////////////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE uart_tx6.v
//
///////////////////////////////////////////////////////////////////////////////////////////
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O311AI_FUNCTIONAL_PP_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o311ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311AI_FUNCTIONAL_PP_V |
// ------------------------------------------------------------------------ //
// Texas A&M University //
// CPSC350 Computer Architecture //
// //
// $Id: ALU_behav.v,v 1.3 2002/11/14 16:06:04 miket Exp miket $ //
// //
// ------------------------------------------------------------------------ //
// ------------------------------------------------------------------------ //
// Behavioral Verilog Module for a MIPS-like ALU //
// -- In continuous and procedure assignments Verilog extends the smaller //
// operands by replicating their MSB, if it is equal to x, z; otherwise //
// operends them with 0's. Arithmetic is interpreted as 2's C //
// -- regs are considered as unsigned bit-vectors but the all arithmetic //
// is done in 2's complement. //
// At ALU instatiation time parameter n determines the ALU bit-size //
// ------------------------------------------------------------------------ //
// repetoire of operations for ALU, selected by ALU_ctr (change at will)
`define ADD 4'b0111 // 2's compl add
`define ADDU 4'b0001 // unsigned add
`define SUB 4'b0010 // 2's compl subtract
`define SUBU 4'b0011 // unsigned subtract
`define AND 4'b0100 // bitwise AND
`define OR 4'b0101 // bitwise OR
`define XOR 4'b0110 // bitwise XOR
`define SLT 4'b1010 // set result=1 if less than 2's compl
`define SLTU 4'b1011 // set result=1 if less than unsigned
`define NOP 4'b0000 // do nothing
module ALU_behav( ADin, BDin, ALU_ctr, Result, Overflow, Carry_in, Carry_out, Zero );
parameter n = 32, Ctr_size = 4;
input Carry_in;
input [Ctr_size-1:0] ALU_ctr;
input [n-1:0] ADin, BDin;
output [n-1:0] Result;
reg [n-1:0] Result, tmp;
output Carry_out, Overflow, Zero;
reg Carry_out, Overflow, Zero;
always @(ALU_ctr or ADin or BDin or Carry_in)
begin
case(ALU_ctr)
`ADD: begin
{Carry_out, Result} = ADin + BDin + Carry_in;
Overflow = ADin[n-1] & BDin[n-1] & ~Result[n-1]
| ~ADin[n-1] & ~BDin[n-1] & Result[n-1];
end
`ADDU: {Overflow, Result} = ADin + BDin + Carry_in;
`SUB: begin
{Carry_out, Result} = ADin - BDin;
Overflow = ADin[n-1] & ~BDin[n-1] & Result[n-1]
| ~ADin[n-1] & BDin[n-1] & ~Result[n-1];
end
`SUBU: {Overflow, Result} = ADin - BDin;
`SLT: begin
{Carry_out, tmp} = ADin - BDin;
Overflow = ADin[n-1] & ~BDin[n-1] & ~tmp[n-1]
| ~ADin[n-1] & BDin[n-1] & tmp[n-1];
$display("SLT:- [%d] tmp = %d [%b]; Cout=%b, Ovf=%b; A=%d, B=%d",
$time, tmp, tmp, Carry_out, Overflow, ADin, BDin );
Result = tmp[n-1] ^ Overflow;
$display("SLT:+R=%d [%b]", Result, Result );
end
`SLTU: begin
{Carry_out, tmp} = ADin - BDin;
$display("SLTU:- [%d] tmp = %d [%b]; Cout=%b, Ovf=%b; A=%d, B=%d",
$time, tmp, tmp, Carry_out, Overflow, ADin, BDin );
Result = Carry_out;
$display("SLTU:+R=%d [%b]", Result, Result );
end
`OR : Result = ADin | BDin;
`AND: Result = ADin & BDin;
`XOR: Result = ADin ^ BDin;
`NOP: Result = ADin;
endcase
Zero = ~| Result; // Result = 32'b0
end
/* always @ (Result)
begin
$display("%0d\t ADin = %0d BDin = %0d; Result = %0d; Cout = %b Ovfl = %b Zero = %b OP = %b", $time, ADin, BDin, Result, Carry_out, Overflow, Zero, ALU_ctr );
end
*/
endmodule
// this is a test bench to test the ALU in isolation (without fetching instructions from instruction memory)
// uncomment it only when you are testing
// module TestALU;
// parameter n = 32, Ctr_size = 4;
// reg [n-1:0] A, B, T;
// wire [n-1:0] R, tt;
// reg Carry_in;
// wire Carry_out, Overflow, Zero;
// reg [Ctr_size-1:0] ALU_ctr;
// integer num;
// ALU_behav ALU( A, B, ALU_ctr, R, Overflow, Carry_in, Carry_out, Zero );
// always @( R or Carry_out or Overflow or Zero )
// begin
// $display("%0d\tA = %0d B = %0d; R = %0d; Cout = %b Ovfl = %b Zero = %b OP = %b n = %d", $time, A, B, R, Carry_out, Overflow, Zero, ALU_ctr, num );
// num = num + 1;
// end
// initial begin
// #0 num = 0; Carry_in = 0;
// #1 A = 101; B = 0; ALU_ctr = `NOP;
// #10 A = 10; B = 10; ALU_ctr = `ADD;
// #10 A = 10; B = 20; ALU_ctr = `ADDU;
// #10 A = 10; B = 20; ALU_ctr = `SLT;
// #10 A = 10; B = 20; ALU_ctr = `SLTU;
// #10 A = 32'hffffffff; B = 1; ALU_ctr = `ADDU;
// #10 A = 10; B = 10; ALU_ctr = `ADDU;
// #10 A = 10; B = 10; ALU_ctr = `SUB;
// #10 A = 1; B = 1; ALU_ctr = `SUBU;
// #10 A = 10; B = 10; ALU_ctr = `SUB;
// #10 A = 10; B = 10; ALU_ctr = `SUBU;
// #10 A = -13; B = -12; ALU_ctr = `SLT;
// #100 $finish;
// end
// endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVN_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__EINVN_PP_BLACKBOX_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVN_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2011 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001))
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer i;
reg [63:0] b;
real r, r2;
integer cyc=0;
realtime uninit;
initial if (uninit != 0.0) $stop;
sub_cast_bug374 sub (.cyc5(cyc[4:0]), .*);
initial begin
if (1_00_0.0_1 != 1000.01) $stop;
// rtoi truncates
if ($rtoi(36.7) != 36) $stop;
if ($rtoi(36.5) != 36) $stop;
if ($rtoi(36.4) != 36) $stop;
// casting rounds
if ((integer '(36.7)) != 37) $stop;
if ((integer '(36.5)) != 37) $stop;
if ((integer '(36.4)) != 36) $stop;
// assignment rounds
// verilator lint_off REALCVT
i = 36.7; if (i != 37) $stop;
i = 36.5; if (i != 37) $stop;
i = 36.4; if (i != 36) $stop;
r = 10'd38; if (r!=38.0) $stop;
// verilator lint_on REALCVT
// operators
if ((-(1.5)) != -1.5) $stop;
if ((+(1.5)) != 1.5) $stop;
if (((1.5)+(1.25)) != 2.75) $stop;
if (((1.5)-(1.25)) != 0.25) $stop;
if (((1.5)*(1.25)) != 1.875) $stop;
if (((1.5)/(1.25)) != 1.2) $stop;
//
if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0
if (((1.5)!=(2)) != 1'b1) $stop;
if (((1.5)> (2)) != 1'b0) $stop;
if (((1.5)>=(2)) != 1'b0) $stop;
if (((1.5)< (2)) != 1'b1) $stop;
if (((1.5)<=(2)) != 1'b1) $stop;
if (((1.5)==(1.5)) != 1'b1) $stop;
if (((1.5)!=(1.5)) != 1'b0) $stop;
if (((1.5)> (1.5)) != 1'b0) $stop;
if (((1.5)>=(1.5)) != 1'b1) $stop;
if (((1.5)< (1.5)) != 1'b0) $stop;
if (((1.5)<=(1.5)) != 1'b1) $stop;
if (((1.6)==(1.5)) != 1'b0) $stop;
if (((1.6)!=(1.5)) != 1'b1) $stop;
if (((1.6)> (1.5)) != 1'b1) $stop;
if (((1.6)>=(1.5)) != 1'b1) $stop;
if (((1.6)< (1.5)) != 1'b0) $stop;
if (((1.6)<=(1.5)) != 1'b0) $stop;
//
if (((0.0)?(2.0):(1.1)) != 1.1) $stop;
if (((1.5)?(2.0):(1.1)) != 2.0) $stop;
//
if (!1.7) $stop;
if (!(!0.0)) $stop;
if (1.8 && 0.0) $stop;
if (!(1.8 || 0.0)) $stop;
//
i=0;
for (r=1.0; r<2.0; r=r+0.1) i++;
if (i!=10) $stop;
// bug
r = $bitstoreal($realtobits(1.414));
if (r != 1.414) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
end
else if (cyc<90) begin
if ($time != {32'h0, $rtoi($realtime)}) $stop;
if ($itor(cyc) != cyc) $stop;
//Unsup: if ((real `($time)) != $realtime) $stop;
r = $itor(cyc*2);
i = $rtoi(r);
if (i!=cyc*2) $stop;
//
r = $itor(cyc)/1.5;
b = $realtobits(r);
r2 = $bitstoreal(b);
if (r != r2) $stop;
//
// Trust the integer math as a comparison
r = $itor(cyc);
if ($rtoi(-r) != -cyc) $stop;
if ($rtoi(+r) != cyc) $stop;
if ($rtoi(r+2.0) != (cyc+2)) $stop;
if ($rtoi(r-2.0) != (cyc-2)) $stop;
if ($rtoi(r*2.0) != (cyc*2)) $stop;
if ($rtoi(r/2.0) != (cyc/2)) $stop;
r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash
//
r2 = $itor(cyc);
case (r)
(r2-1.0): $stop;
r2: ;
default: $stop;
endcase
//
r = $itor(cyc);
if ((r==50.0) != (cyc==50)) $stop;
if ((r!=50.0) != (cyc!=50)) $stop;
if ((r> 50.0) != (cyc> 50)) $stop;
if ((r>=50.0) != (cyc>=50)) $stop;
if ((r< 50.0) != (cyc< 50)) $stop;
if ((r<=50.0) != (cyc<=50)) $stop;
//
if ($rtoi((r-50.0) ? 10.0 : 20.0)
!= (((cyc-50)!=0) ? 10 : 20)) $stop;
//
if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub_cast_bug374(input clk, input [4:0] cyc5);
integer i;
always @(posedge clk) begin
i <= integer'(cyc5);
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module cf_adc_wr (
// adc interface (clk, data, over-range)
adc_clk_in,
adc_data_in,
adc_or_in,
// interface outputs
adc_clk,
adc_valid,
adc_data,
adc_or,
adc_pn_oos,
adc_pn_err,
// processor control signals
up_pn_type,
up_delay_sel,
up_delay_rwn,
up_delay_addr,
up_delay_wdata,
// delay control signals
delay_clk,
delay_ack,
delay_rdata,
delay_locked,
// adc debug and monitor signals (for chipscope)
adc_mon_valid,
adc_mon_data);
// This parameter controls the buffer type based on the target device.
parameter C_CF_BUFTYPE = 0;
// adc interface (clk, data, over-range)
input adc_clk_in;
input [13:0] adc_data_in;
input adc_or_in;
// interface outputs
output adc_clk;
output adc_valid;
output [63:0] adc_data;
output adc_or;
output adc_pn_oos;
output adc_pn_err;
// processor control signals
input up_pn_type;
input up_delay_sel;
input up_delay_rwn;
input [ 3:0] up_delay_addr;
input [ 4:0] up_delay_wdata;
// delay control signals
input delay_clk;
output delay_ack;
output [ 4:0] delay_rdata;
output delay_locked;
// adc debug and monitor signals (for chipscope)
output adc_mon_valid;
output [15:0] adc_mon_data;
reg [ 1:0] adc_count = 'd0;
reg adc_valid = 'd0;
reg [63:0] adc_data = 'd0;
wire [13:0] adc_data_if_s;
assign adc_mon_valid = 1'b1;
assign adc_mon_data = {2'd0, adc_data_if_s};
always @(posedge adc_clk) begin
adc_count <= adc_count + 1'b1;
adc_valid <= adc_count[0] & adc_count[1];
adc_data <= {2'd0, adc_data_if_s, adc_data[63:16]};
end
// PN sequence monitor
cf_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data_if_s),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err),
.up_pn_type (up_pn_type));
// ADC data interface
cf_adc_if #(.C_CF_BUFTYPE (C_CF_BUFTYPE)) i_adc_if (
.adc_clk_in (adc_clk_in),
.adc_data_in (adc_data_in),
.adc_or_in (adc_or_in),
.adc_clk (adc_clk),
.adc_data (adc_data_if_s),
.adc_or (adc_or),
.up_delay_sel (up_delay_sel),
.up_delay_rwn (up_delay_rwn),
.up_delay_addr (up_delay_addr),
.up_delay_wdata (up_delay_wdata),
.delay_clk (delay_clk),
.delay_ack (delay_ack),
.delay_rdata (delay_rdata),
.delay_locked (delay_locked));
endmodule
// ***************************************************************************
// ***************************************************************************
|
module ibex_prefetch_buffer (
clk_i,
rst_ni,
req_i,
branch_i,
addr_i,
ready_i,
valid_o,
rdata_o,
addr_o,
err_o,
instr_req_o,
instr_gnt_i,
instr_addr_o,
instr_rdata_i,
instr_err_i,
instr_pmp_err_i,
instr_rvalid_i,
busy_o
);
input wire clk_i;
input wire rst_ni;
input wire req_i;
input wire branch_i;
input wire [31:0] addr_i;
input wire ready_i;
output wire valid_o;
output wire [31:0] rdata_o;
output wire [31:0] addr_o;
output wire err_o;
output wire instr_req_o;
input wire instr_gnt_i;
output wire [31:0] instr_addr_o;
input wire [31:0] instr_rdata_i;
input wire instr_err_i;
input wire instr_pmp_err_i;
input wire instr_rvalid_i;
output wire busy_o;
localparam [31:0] NUM_REQS = 2;
wire valid_new_req;
wire valid_req;
wire valid_req_d;
reg valid_req_q;
wire discard_req_d;
reg discard_req_q;
wire gnt_or_pmp_err;
wire rvalid_or_pmp_err;
wire [(NUM_REQS - 1):0] rdata_outstanding_n;
wire [(NUM_REQS - 1):0] rdata_outstanding_s;
reg [(NUM_REQS - 1):0] rdata_outstanding_q;
wire [(NUM_REQS - 1):0] branch_discard_n;
wire [(NUM_REQS - 1):0] branch_discard_s;
reg [(NUM_REQS - 1):0] branch_discard_q;
wire [(NUM_REQS - 1):0] rdata_pmp_err_n;
wire [(NUM_REQS - 1):0] rdata_pmp_err_s;
reg [(NUM_REQS - 1):0] rdata_pmp_err_q;
wire [31:0] stored_addr_d;
reg [31:0] stored_addr_q;
wire stored_addr_en;
wire [31:0] fetch_addr_d;
reg [31:0] fetch_addr_q;
wire fetch_addr_en;
wire [31:0] instr_addr;
wire [31:0] instr_addr_w_aligned;
wire instr_or_pmp_err;
wire fifo_valid;
wire fifo_ready;
wire fifo_clear;
assign busy_o = (|rdata_outstanding_q | instr_req_o);
assign instr_or_pmp_err = (instr_err_i | rdata_pmp_err_q[0]);
assign fifo_clear = branch_i;
ibex_fetch_fifo #(.NUM_REQS(NUM_REQS)) fifo_i(
.clk_i(clk_i),
.rst_ni(rst_ni),
.clear_i(fifo_clear),
.in_valid_i(fifo_valid),
.in_addr_i(addr_i),
.in_rdata_i(instr_rdata_i),
.in_err_i(instr_or_pmp_err),
.in_ready_o(fifo_ready),
.out_valid_o(valid_o),
.out_ready_i(ready_i),
.out_rdata_o(rdata_o),
.out_addr_o(addr_o),
.out_err_o(err_o)
);
assign valid_new_req = ((req_i & (fifo_ready | branch_i)) & ~rdata_outstanding_q[(NUM_REQS - 1)]);
assign valid_req = (valid_req_q | valid_new_req);
assign gnt_or_pmp_err = (instr_gnt_i | instr_pmp_err_i);
assign rvalid_or_pmp_err = (rdata_outstanding_q[0] & (instr_rvalid_i | rdata_pmp_err_q[0]));
assign valid_req_d = (valid_req & ~gnt_or_pmp_err);
assign discard_req_d = (valid_req_q & (branch_i | discard_req_q));
assign stored_addr_en = ((valid_new_req & ~valid_req_q) & ~gnt_or_pmp_err);
assign stored_addr_d = instr_addr;
always @(posedge clk_i)
if (stored_addr_en)
stored_addr_q <= stored_addr_d;
assign fetch_addr_en = (branch_i | (valid_new_req & ~valid_req_q));
assign fetch_addr_d = ((branch_i ? addr_i : {fetch_addr_q[31:2], 2'b00}) + {{29 {1'b0}}, (valid_new_req & ~valid_req_q), 2'b00});
always @(posedge clk_i)
if (fetch_addr_en)
fetch_addr_q <= fetch_addr_d;
assign instr_addr = (valid_req_q ? stored_addr_q : (branch_i ? addr_i : fetch_addr_q));
assign instr_addr_w_aligned = {instr_addr[31:2], 2'b00};
generate
genvar g_outstanding_reqs_i;
for (g_outstanding_reqs_i = 0; (g_outstanding_reqs_i < NUM_REQS); g_outstanding_reqs_i = (g_outstanding_reqs_i + 1)) begin : g_outstanding_reqs
if ((g_outstanding_reqs_i == 0)) begin : g_req0
assign rdata_outstanding_n[g_outstanding_reqs_i] = ((valid_req & gnt_or_pmp_err) | rdata_outstanding_q[g_outstanding_reqs_i]);
assign branch_discard_n[g_outstanding_reqs_i] = ((((valid_req & gnt_or_pmp_err) & discard_req_d) | (branch_i & rdata_outstanding_q[g_outstanding_reqs_i])) | branch_discard_q[g_outstanding_reqs_i]);
assign rdata_pmp_err_n[g_outstanding_reqs_i] = (((valid_req & ~rdata_outstanding_q[g_outstanding_reqs_i]) & instr_pmp_err_i) | rdata_pmp_err_q[g_outstanding_reqs_i]);
end
else begin : g_reqtop
assign rdata_outstanding_n[g_outstanding_reqs_i] = (((valid_req & gnt_or_pmp_err) & rdata_outstanding_q[(g_outstanding_reqs_i - 1)]) | rdata_outstanding_q[g_outstanding_reqs_i]);
assign branch_discard_n[g_outstanding_reqs_i] = (((((valid_req & gnt_or_pmp_err) & discard_req_d) & rdata_outstanding_q[(g_outstanding_reqs_i - 1)]) | (branch_i & rdata_outstanding_q[g_outstanding_reqs_i])) | branch_discard_q[g_outstanding_reqs_i]);
assign rdata_pmp_err_n[g_outstanding_reqs_i] = ((((valid_req & ~rdata_outstanding_q[g_outstanding_reqs_i]) & instr_pmp_err_i) & rdata_outstanding_q[(g_outstanding_reqs_i - 1)]) | rdata_pmp_err_q[g_outstanding_reqs_i]);
end
end
endgenerate
assign rdata_outstanding_s = (rvalid_or_pmp_err ? {1'b0, rdata_outstanding_n[(NUM_REQS - 1):1]} : rdata_outstanding_n);
assign branch_discard_s = (rvalid_or_pmp_err ? {1'b0, branch_discard_n[(NUM_REQS - 1):1]} : branch_discard_n);
assign rdata_pmp_err_s = (rvalid_or_pmp_err ? {1'b0, rdata_pmp_err_n[(NUM_REQS - 1):1]} : rdata_pmp_err_n);
assign fifo_valid = (rvalid_or_pmp_err & ~branch_discard_q[0]);
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
valid_req_q <= 1'b0;
discard_req_q <= 1'b0;
rdata_outstanding_q <= 'b0;
branch_discard_q <= 'b0;
rdata_pmp_err_q <= 'b0;
end
else begin
valid_req_q <= valid_req_d;
discard_req_q <= discard_req_d;
rdata_outstanding_q <= rdata_outstanding_s;
branch_discard_q <= branch_discard_s;
rdata_pmp_err_q <= rdata_pmp_err_s;
end
assign instr_req_o = valid_req;
assign instr_addr_o = instr_addr_w_aligned;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SDFBBP_FUNCTIONAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr/sky130_fd_sc_lp__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_lp__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBP_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DFXTP_PP_BLACKBOX_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXTP_PP_BLACKBOX_V
|
// DE0_NANO_SOC_QSYS.v
// Generated using ACDS version 14.0 209 at 2014.12.18.15:52:20
`timescale 1 ps / 1 ps
module DE0_NANO_SOC_QSYS (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
output wire adc_ltc2308_conduit_end_CONVST, // adc_ltc2308_conduit_end.CONVST
output wire adc_ltc2308_conduit_end_SCK, // .SCK
output wire adc_ltc2308_conduit_end_SDI, // .SDI
input wire adc_ltc2308_conduit_end_SDO, // .SDO
input wire [9:0] sw_external_connection_export, // sw_external_connection.export
output wire pll_sys_locked_export, // pll_sys_locked.export
output wire pll_sys_outclk2_clk // pll_sys_outclk2.clk
);
wire pll_sys_outclk0_clk; // pll_sys:outclk_0 -> [adc_ltc2308:slave_clk, irq_mapper:clk, jtag_uart:clk, mm_interconnect_0:pll_sys_outclk0_clk, nios2_qsys:clk, onchip_memory2:clk, rst_controller:clk, rst_controller_001:clk, sw:clk, sysid_qsys:clock]
wire pll_sys_outclk1_clk; // pll_sys:outclk_1 -> adc_ltc2308:adc_clk
wire nios2_qsys_instruction_master_waitrequest; // mm_interconnect_0:nios2_qsys_instruction_master_waitrequest -> nios2_qsys:i_waitrequest
wire [19:0] nios2_qsys_instruction_master_address; // nios2_qsys:i_address -> mm_interconnect_0:nios2_qsys_instruction_master_address
wire nios2_qsys_instruction_master_read; // nios2_qsys:i_read -> mm_interconnect_0:nios2_qsys_instruction_master_read
wire [31:0] nios2_qsys_instruction_master_readdata; // mm_interconnect_0:nios2_qsys_instruction_master_readdata -> nios2_qsys:i_readdata
wire nios2_qsys_instruction_master_readdatavalid; // mm_interconnect_0:nios2_qsys_instruction_master_readdatavalid -> nios2_qsys:i_readdatavalid
wire nios2_qsys_data_master_waitrequest; // mm_interconnect_0:nios2_qsys_data_master_waitrequest -> nios2_qsys:d_waitrequest
wire [31:0] nios2_qsys_data_master_writedata; // nios2_qsys:d_writedata -> mm_interconnect_0:nios2_qsys_data_master_writedata
wire [19:0] nios2_qsys_data_master_address; // nios2_qsys:d_address -> mm_interconnect_0:nios2_qsys_data_master_address
wire nios2_qsys_data_master_write; // nios2_qsys:d_write -> mm_interconnect_0:nios2_qsys_data_master_write
wire nios2_qsys_data_master_read; // nios2_qsys:d_read -> mm_interconnect_0:nios2_qsys_data_master_read
wire [31:0] nios2_qsys_data_master_readdata; // mm_interconnect_0:nios2_qsys_data_master_readdata -> nios2_qsys:d_readdata
wire nios2_qsys_data_master_debugaccess; // nios2_qsys:jtag_debug_module_debugaccess_to_roms -> mm_interconnect_0:nios2_qsys_data_master_debugaccess
wire nios2_qsys_data_master_readdatavalid; // mm_interconnect_0:nios2_qsys_data_master_readdatavalid -> nios2_qsys:d_readdatavalid
wire [3:0] nios2_qsys_data_master_byteenable; // nios2_qsys:d_byteenable -> mm_interconnect_0:nios2_qsys_data_master_byteenable
wire mm_interconnect_0_nios2_qsys_jtag_debug_module_waitrequest; // nios2_qsys:jtag_debug_module_waitrequest -> mm_interconnect_0:nios2_qsys_jtag_debug_module_waitrequest
wire [31:0] mm_interconnect_0_nios2_qsys_jtag_debug_module_writedata; // mm_interconnect_0:nios2_qsys_jtag_debug_module_writedata -> nios2_qsys:jtag_debug_module_writedata
wire [8:0] mm_interconnect_0_nios2_qsys_jtag_debug_module_address; // mm_interconnect_0:nios2_qsys_jtag_debug_module_address -> nios2_qsys:jtag_debug_module_address
wire mm_interconnect_0_nios2_qsys_jtag_debug_module_write; // mm_interconnect_0:nios2_qsys_jtag_debug_module_write -> nios2_qsys:jtag_debug_module_write
wire mm_interconnect_0_nios2_qsys_jtag_debug_module_read; // mm_interconnect_0:nios2_qsys_jtag_debug_module_read -> nios2_qsys:jtag_debug_module_read
wire [31:0] mm_interconnect_0_nios2_qsys_jtag_debug_module_readdata; // nios2_qsys:jtag_debug_module_readdata -> mm_interconnect_0:nios2_qsys_jtag_debug_module_readdata
wire mm_interconnect_0_nios2_qsys_jtag_debug_module_debugaccess; // mm_interconnect_0:nios2_qsys_jtag_debug_module_debugaccess -> nios2_qsys:jtag_debug_module_debugaccess
wire [3:0] mm_interconnect_0_nios2_qsys_jtag_debug_module_byteenable; // mm_interconnect_0:nios2_qsys_jtag_debug_module_byteenable -> nios2_qsys:jtag_debug_module_byteenable
wire [31:0] mm_interconnect_0_onchip_memory2_s1_writedata; // mm_interconnect_0:onchip_memory2_s1_writedata -> onchip_memory2:writedata
wire [15:0] mm_interconnect_0_onchip_memory2_s1_address; // mm_interconnect_0:onchip_memory2_s1_address -> onchip_memory2:address
wire mm_interconnect_0_onchip_memory2_s1_chipselect; // mm_interconnect_0:onchip_memory2_s1_chipselect -> onchip_memory2:chipselect
wire mm_interconnect_0_onchip_memory2_s1_clken; // mm_interconnect_0:onchip_memory2_s1_clken -> onchip_memory2:clken
wire mm_interconnect_0_onchip_memory2_s1_write; // mm_interconnect_0:onchip_memory2_s1_write -> onchip_memory2:write
wire [31:0] mm_interconnect_0_onchip_memory2_s1_readdata; // onchip_memory2:readdata -> mm_interconnect_0:onchip_memory2_s1_readdata
wire [3:0] mm_interconnect_0_onchip_memory2_s1_byteenable; // mm_interconnect_0:onchip_memory2_s1_byteenable -> onchip_memory2:byteenable
wire [0:0] mm_interconnect_0_sysid_qsys_control_slave_address; // mm_interconnect_0:sysid_qsys_control_slave_address -> sysid_qsys:address
wire [31:0] mm_interconnect_0_sysid_qsys_control_slave_readdata; // sysid_qsys:readdata -> mm_interconnect_0:sysid_qsys_control_slave_readdata
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
wire [15:0] mm_interconnect_0_adc_ltc2308_slave_writedata; // mm_interconnect_0:adc_ltc2308_slave_writedata -> adc_ltc2308:slave_wriredata
wire [0:0] mm_interconnect_0_adc_ltc2308_slave_address; // mm_interconnect_0:adc_ltc2308_slave_address -> adc_ltc2308:slave_addr
wire mm_interconnect_0_adc_ltc2308_slave_chipselect; // mm_interconnect_0:adc_ltc2308_slave_chipselect -> adc_ltc2308:slave_chipselect_n
wire mm_interconnect_0_adc_ltc2308_slave_write; // mm_interconnect_0:adc_ltc2308_slave_write -> adc_ltc2308:slave_wrtie_n
wire mm_interconnect_0_adc_ltc2308_slave_read; // mm_interconnect_0:adc_ltc2308_slave_read -> adc_ltc2308:slave_read_n
wire [15:0] mm_interconnect_0_adc_ltc2308_slave_readdata; // adc_ltc2308:slave_readdata -> mm_interconnect_0:adc_ltc2308_slave_readdata
wire [31:0] mm_interconnect_0_sw_s1_writedata; // mm_interconnect_0:sw_s1_writedata -> sw:writedata
wire [1:0] mm_interconnect_0_sw_s1_address; // mm_interconnect_0:sw_s1_address -> sw:address
wire mm_interconnect_0_sw_s1_chipselect; // mm_interconnect_0:sw_s1_chipselect -> sw:chipselect
wire mm_interconnect_0_sw_s1_write; // mm_interconnect_0:sw_s1_write -> sw:write_n
wire [31:0] mm_interconnect_0_sw_s1_readdata; // sw:readdata -> mm_interconnect_0:sw_s1_readdata
wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // sw:irq -> irq_mapper:receiver1_irq
wire [31:0] nios2_qsys_d_irq_irq; // irq_mapper:sender_irq -> nios2_qsys:d_irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [irq_mapper:reset, mm_interconnect_0:nios2_qsys_reset_n_reset_bridge_in_reset_reset, nios2_qsys:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [nios2_qsys:reset_req, rst_translator:reset_req_in]
wire nios2_qsys_jtag_debug_module_reset_reset; // nios2_qsys:jtag_debug_module_resetrequest -> rst_controller:reset_in1
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [adc_ltc2308:slave_reset_n, jtag_uart:rst_n, mm_interconnect_0:onchip_memory2_reset1_reset_bridge_in_reset_reset, onchip_memory2:reset, rst_translator_001:in_reset, sw:reset_n, sysid_qsys:reset_n]
wire rst_controller_001_reset_out_reset_req; // rst_controller_001:reset_req -> [onchip_memory2:reset_req, rst_translator_001:reset_req_in]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> pll_sys:rst
DE0_NANO_SOC_QSYS_nios2_qsys nios2_qsys (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (nios2_qsys_data_master_address), // data_master.address
.d_byteenable (nios2_qsys_data_master_byteenable), // .byteenable
.d_read (nios2_qsys_data_master_read), // .read
.d_readdata (nios2_qsys_data_master_readdata), // .readdata
.d_waitrequest (nios2_qsys_data_master_waitrequest), // .waitrequest
.d_write (nios2_qsys_data_master_write), // .write
.d_writedata (nios2_qsys_data_master_writedata), // .writedata
.d_readdatavalid (nios2_qsys_data_master_readdatavalid), // .readdatavalid
.jtag_debug_module_debugaccess_to_roms (nios2_qsys_data_master_debugaccess), // .debugaccess
.i_address (nios2_qsys_instruction_master_address), // instruction_master.address
.i_read (nios2_qsys_instruction_master_read), // .read
.i_readdata (nios2_qsys_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_qsys_instruction_master_waitrequest), // .waitrequest
.i_readdatavalid (nios2_qsys_instruction_master_readdatavalid), // .readdatavalid
.d_irq (nios2_qsys_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (nios2_qsys_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset
.jtag_debug_module_address (mm_interconnect_0_nios2_qsys_jtag_debug_module_address), // jtag_debug_module.address
.jtag_debug_module_byteenable (mm_interconnect_0_nios2_qsys_jtag_debug_module_byteenable), // .byteenable
.jtag_debug_module_debugaccess (mm_interconnect_0_nios2_qsys_jtag_debug_module_debugaccess), // .debugaccess
.jtag_debug_module_read (mm_interconnect_0_nios2_qsys_jtag_debug_module_read), // .read
.jtag_debug_module_readdata (mm_interconnect_0_nios2_qsys_jtag_debug_module_readdata), // .readdata
.jtag_debug_module_waitrequest (mm_interconnect_0_nios2_qsys_jtag_debug_module_waitrequest), // .waitrequest
.jtag_debug_module_write (mm_interconnect_0_nios2_qsys_jtag_debug_module_write), // .write
.jtag_debug_module_writedata (mm_interconnect_0_nios2_qsys_jtag_debug_module_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
DE0_NANO_SOC_QSYS_onchip_memory2 onchip_memory2 (
.clk (pll_sys_outclk0_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_s1_byteenable), // .byteenable
.reset (rst_controller_001_reset_out_reset), // reset1.reset
.reset_req (rst_controller_001_reset_out_reset_req) // .reset_req
);
DE0_NANO_SOC_QSYS_sysid_qsys sysid_qsys (
.clock (pll_sys_outclk0_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata), // control_slave.readdata
.address (mm_interconnect_0_sysid_qsys_control_slave_address) // .address
);
DE0_NANO_SOC_QSYS_jtag_uart jtag_uart (
.clk (pll_sys_outclk0_clk), // clk.clk
.rst_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
DE0_NANO_SOC_QSYS_pll_sys pll_sys (
.refclk (clk_clk), // refclk.clk
.rst (rst_controller_002_reset_out_reset), // reset.reset
.outclk_0 (pll_sys_outclk0_clk), // outclk0.clk
.outclk_1 (pll_sys_outclk1_clk), // outclk1.clk
.outclk_2 (pll_sys_outclk2_clk), // outclk2.clk
.locked (pll_sys_locked_export) // locked.export
);
adc_ltc2308_fifo adc_ltc2308 (
.slave_chipselect_n (~mm_interconnect_0_adc_ltc2308_slave_chipselect), // slave.chipselect_n
.slave_read_n (~mm_interconnect_0_adc_ltc2308_slave_read), // .read_n
.slave_readdata (mm_interconnect_0_adc_ltc2308_slave_readdata), // .readdata
.slave_addr (mm_interconnect_0_adc_ltc2308_slave_address), // .address
.slave_wrtie_n (~mm_interconnect_0_adc_ltc2308_slave_write), // .write_n
.slave_wriredata (mm_interconnect_0_adc_ltc2308_slave_writedata), // .writedata
.ADC_CONVST (adc_ltc2308_conduit_end_CONVST), // conduit_end.export
.ADC_SCK (adc_ltc2308_conduit_end_SCK), // .export
.ADC_SDI (adc_ltc2308_conduit_end_SDI), // .export
.ADC_SDO (adc_ltc2308_conduit_end_SDO), // .export
.slave_reset_n (~rst_controller_001_reset_out_reset), // reset_sink.reset_n
.slave_clk (pll_sys_outclk0_clk), // clock_sink.clk
.adc_clk (pll_sys_outclk1_clk) // clock_sink_adc.clk
);
DE0_NANO_SOC_QSYS_sw sw (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sw_s1_address), // s1.address
.write_n (~mm_interconnect_0_sw_s1_write), // .write_n
.writedata (mm_interconnect_0_sw_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sw_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sw_s1_readdata), // .readdata
.in_port (sw_external_connection_export), // external_connection.export
.irq (irq_mapper_receiver1_irq) // irq.irq
);
DE0_NANO_SOC_QSYS_mm_interconnect_0 mm_interconnect_0 (
.pll_sys_outclk0_clk (pll_sys_outclk0_clk), // pll_sys_outclk0.clk
.nios2_qsys_reset_n_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // nios2_qsys_reset_n_reset_bridge_in_reset.reset
.onchip_memory2_reset1_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // onchip_memory2_reset1_reset_bridge_in_reset.reset
.nios2_qsys_data_master_address (nios2_qsys_data_master_address), // nios2_qsys_data_master.address
.nios2_qsys_data_master_waitrequest (nios2_qsys_data_master_waitrequest), // .waitrequest
.nios2_qsys_data_master_byteenable (nios2_qsys_data_master_byteenable), // .byteenable
.nios2_qsys_data_master_read (nios2_qsys_data_master_read), // .read
.nios2_qsys_data_master_readdata (nios2_qsys_data_master_readdata), // .readdata
.nios2_qsys_data_master_readdatavalid (nios2_qsys_data_master_readdatavalid), // .readdatavalid
.nios2_qsys_data_master_write (nios2_qsys_data_master_write), // .write
.nios2_qsys_data_master_writedata (nios2_qsys_data_master_writedata), // .writedata
.nios2_qsys_data_master_debugaccess (nios2_qsys_data_master_debugaccess), // .debugaccess
.nios2_qsys_instruction_master_address (nios2_qsys_instruction_master_address), // nios2_qsys_instruction_master.address
.nios2_qsys_instruction_master_waitrequest (nios2_qsys_instruction_master_waitrequest), // .waitrequest
.nios2_qsys_instruction_master_read (nios2_qsys_instruction_master_read), // .read
.nios2_qsys_instruction_master_readdata (nios2_qsys_instruction_master_readdata), // .readdata
.nios2_qsys_instruction_master_readdatavalid (nios2_qsys_instruction_master_readdatavalid), // .readdatavalid
.adc_ltc2308_slave_address (mm_interconnect_0_adc_ltc2308_slave_address), // adc_ltc2308_slave.address
.adc_ltc2308_slave_write (mm_interconnect_0_adc_ltc2308_slave_write), // .write
.adc_ltc2308_slave_read (mm_interconnect_0_adc_ltc2308_slave_read), // .read
.adc_ltc2308_slave_readdata (mm_interconnect_0_adc_ltc2308_slave_readdata), // .readdata
.adc_ltc2308_slave_writedata (mm_interconnect_0_adc_ltc2308_slave_writedata), // .writedata
.adc_ltc2308_slave_chipselect (mm_interconnect_0_adc_ltc2308_slave_chipselect), // .chipselect
.jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
.jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write
.jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read
.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.nios2_qsys_jtag_debug_module_address (mm_interconnect_0_nios2_qsys_jtag_debug_module_address), // nios2_qsys_jtag_debug_module.address
.nios2_qsys_jtag_debug_module_write (mm_interconnect_0_nios2_qsys_jtag_debug_module_write), // .write
.nios2_qsys_jtag_debug_module_read (mm_interconnect_0_nios2_qsys_jtag_debug_module_read), // .read
.nios2_qsys_jtag_debug_module_readdata (mm_interconnect_0_nios2_qsys_jtag_debug_module_readdata), // .readdata
.nios2_qsys_jtag_debug_module_writedata (mm_interconnect_0_nios2_qsys_jtag_debug_module_writedata), // .writedata
.nios2_qsys_jtag_debug_module_byteenable (mm_interconnect_0_nios2_qsys_jtag_debug_module_byteenable), // .byteenable
.nios2_qsys_jtag_debug_module_waitrequest (mm_interconnect_0_nios2_qsys_jtag_debug_module_waitrequest), // .waitrequest
.nios2_qsys_jtag_debug_module_debugaccess (mm_interconnect_0_nios2_qsys_jtag_debug_module_debugaccess), // .debugaccess
.onchip_memory2_s1_address (mm_interconnect_0_onchip_memory2_s1_address), // onchip_memory2_s1.address
.onchip_memory2_s1_write (mm_interconnect_0_onchip_memory2_s1_write), // .write
.onchip_memory2_s1_readdata (mm_interconnect_0_onchip_memory2_s1_readdata), // .readdata
.onchip_memory2_s1_writedata (mm_interconnect_0_onchip_memory2_s1_writedata), // .writedata
.onchip_memory2_s1_byteenable (mm_interconnect_0_onchip_memory2_s1_byteenable), // .byteenable
.onchip_memory2_s1_chipselect (mm_interconnect_0_onchip_memory2_s1_chipselect), // .chipselect
.onchip_memory2_s1_clken (mm_interconnect_0_onchip_memory2_s1_clken), // .clken
.sw_s1_address (mm_interconnect_0_sw_s1_address), // sw_s1.address
.sw_s1_write (mm_interconnect_0_sw_s1_write), // .write
.sw_s1_readdata (mm_interconnect_0_sw_s1_readdata), // .readdata
.sw_s1_writedata (mm_interconnect_0_sw_s1_writedata), // .writedata
.sw_s1_chipselect (mm_interconnect_0_sw_s1_chipselect), // .chipselect
.sysid_qsys_control_slave_address (mm_interconnect_0_sysid_qsys_control_slave_address), // sysid_qsys_control_slave.address
.sysid_qsys_control_slave_readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata) // .readdata
);
DE0_NANO_SOC_QSYS_irq_mapper irq_mapper (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.sender_irq (nios2_qsys_d_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (nios2_qsys_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (pll_sys_outclk0_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (pll_sys_outclk0_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
module serial_rx #(
parameter CLK_PER_BIT = 50
)(
input clk,
input rst,
input rx,
output [7:0] data,
output new_data
);
// clog2 is 'ceiling of log base 2' which gives you the number of bits needed to store a value
parameter CTR_SIZE = $clog2(CLK_PER_BIT);
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0,
WAIT_HALF = 2'd1,
WAIT_FULL = 2'd2,
WAIT_HIGH = 2'd3;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [2:0] bit_ctr_d, bit_ctr_q;
reg [7:0] data_d, data_q;
reg new_data_d, new_data_q;
reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
reg rx_d, rx_q;
assign new_data = new_data_q;
assign data = data_q;
always @(*) begin
rx_d = rx;
state_d = state_q;
ctr_d = ctr_q;
bit_ctr_d = bit_ctr_q;
data_d = data_q;
new_data_d = 1'b0;
case (state_q)
IDLE: begin
bit_ctr_d = 3'b0;
ctr_d = 1'b0;
if (rx_q == 1'b0) begin
state_d = WAIT_HALF;
end
end
WAIT_HALF: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == (CLK_PER_BIT >> 1)) begin
ctr_d = 1'b0;
state_d = WAIT_FULL;
end
end
WAIT_FULL: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
data_d = {rx_q, data_q[7:1]};
bit_ctr_d = bit_ctr_q + 1'b1;
ctr_d = 1'b0;
if (bit_ctr_q == 3'd7) begin
state_d = WAIT_HIGH;
new_data_d = 1'b1;
end
end
end
WAIT_HIGH: begin
if (rx_q == 1'b1) begin
state_d = IDLE;
end
end
default: begin
state_d = IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
bit_ctr_q <= 3'b0;
new_data_q <= 1'b0;
state_q <= IDLE;
end else begin
ctr_q <= ctr_d;
bit_ctr_q <= bit_ctr_d;
new_data_q <= new_data_d;
state_q <= state_d;
end
rx_q <= rx_d;
data_q <= data_d;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKBUF_BLACKBOX_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_BLACKBOX_V
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: book.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module book (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/book.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/book.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL book.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL book.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL book.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL book.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL book_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL book_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:10:47 08/17/2015
// Design Name:
// Module Name: Register
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RegisterAdd
# (parameter W = 16)
(
input wire clk, //system clock
input wire rst, //system reset
input wire load, //load signal
input wire [W-1:0] D, //input signal
output reg [W-1:0] Q //output signal
);
always @(posedge clk, posedge rst)
if(rst)
Q <= 0;
else if(load)
Q <= D;
else
Q <= Q;
endmodule
module FFD_NoCE
# (parameter W = 16)
(
input wire clk, //system clock
input wire rst, //system reset
input wire [W-1:0] D, //input signal
output reg [W-1:0] Q //output signal
);
always @(posedge clk, posedge rst)
if(rst)
Q <= 0;
else
Q <= D;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 00:58:43 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_buffer_0_0/system_vga_buffer_0_0_stub.v
// Design : system_vga_buffer_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_buffer,Vivado 2016.4" *)
module system_vga_buffer_0_0(clk_w, clk_r, wen, x_addr_w, y_addr_w, x_addr_r,
y_addr_r, data_w, data_r)
/* synthesis syn_black_box black_box_pad_pin="clk_w,clk_r,wen,x_addr_w[9:0],y_addr_w[9:0],x_addr_r[9:0],y_addr_r[9:0],data_w[23:0],data_r[23:0]" */;
input clk_w;
input clk_r;
input wen;
input [9:0]x_addr_w;
input [9:0]y_addr_w;
input [9:0]x_addr_r;
input [9:0]y_addr_r;
input [23:0]data_w;
output [23:0]data_r;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32O_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A32O_BEHAVIORAL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a32o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B1 and0_out ;
wire B1 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32O_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211A_SYMBOL_V
`define SKY130_FD_SC_LS__O211A_SYMBOL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o211a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211A_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4_TB_V
`define SKY130_FD_SC_HS__NAND4_TB_V
/**
* nand4: 4-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 C = 1'b1;
#200 D = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 C = 1'b0;
#320 D = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 D = 1'b1;
#440 C = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 D = 1'bx;
#560 C = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hs__nand4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4_TB_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : xaw2verilog
// / / Filename : DCM_Scope.v
// /___/ /\ Timestamp : 10/02/2020 08:51:22
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle D:/prj/sd2snes/verilog/sd2snes_sdd1/ipcore_dir/DCM_Scope.xaw -st DCM_Scope.v
//Design Name: DCM_Scope
//Device: xc3s400-4pq208
//
// Module DCM_Scope
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_INST = 0.07 UI
// Period Jitter (Peak-to-Peak) for block DCM_INST = 0.75 ns
`timescale 1ns / 1ps
module DCM_Scope(CLKIN_IN,
RST_IN,
CLKDV_OUT,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT,
LOCKED_OUT);
input CLKIN_IN;
input RST_IN;
output CLKDV_OUT;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output LOCKED_OUT;
wire CLKDV_BUF;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(4.0), .CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(41.667), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'h8080), .PHASE_SHIFT(0), .STARTUP_WAIT("TRUE") )
DCM_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(RST_IN),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
endmodule
|
module Registers(
input wire Clk,
input wire [17:0] InBuffer,
input wire [15:0] iRAMBuffer,
output wire [11:0] outBuffer,
output wire RequestInBuffer,
// **************** Control for String *************************************
input wire StringLoadZero,
input wire StringLoadChar,
input wire StringLoadBuffer,
input wire ConcatenateChar,
input wire StringShiftRight,
input wire ConcatenateStringSize,
// **************** Control for Insert Pointer *************************
input wire LoadInsertPointer,
input wire UpdateInsertPointer,
// **************** Control for Code ***********************************
input wire CodeLoadZero,
input wire CodeIncrement,
// **************** Control for Found **********************************
input wire NotFound,
input wire Found,
// **************** Control for Char ***********************************
input wire CharLoadBuffer,
// **************** Control for Init Dictionary Pointer ****************
input wire BufferInitDicPointer,
// **************** Control for Dictionary Pointer *********************
input wire LoadDicPointer,
input wire DicPointerIncrement,
input wire LoadJumpAddress,
input wire DicPointerLoadInsert,
// **************** Control for StringRAM ******************************
input wire StringRAMLoad,
input wire StringRAMZero,
input wire StringRAMShift,
// **************** Control for Jumping Address ************************
input wire SetJumpAddress,
// ****************** Jump conditions **********************************
output wire DicPointerEqualsInsertPointer,
output wire StringRAMSizeEqualsStringSize,
output wire DicPointerEqualsJumpAddress,
output wire StringRAMSizeEqualsZero,
output wire StringRAMEqualsString,
output wire CodeBigger128,
output wire CodeEqualsZero,
output wire FoundStatus,
// ********************* Data to RAM ***********************************
output wire [7:0] ramCode,
output wire [15:0] ramString,
output wire [17:0] ramDicPointer
);
//**********************************************************************
//************************** Conditions *******************************
//**********************************************************************
assign DicPointerEqualsInsertPointer = (DicPointer == InsertPointer)? 1'b1:1'b0;
assign StringRAMSizeEqualsStringSize = (StringRAM[135:127] == StringSize)? 1'b1:1'b0;
assign DicPointerEqualsJumpAddress = (DicPointer == JumpAddress)? 1'b1:1'b0;
assign StringRAMSizeEqualsZero = (StringRAM[7:0] == 0)? 1'b1:1'b0;
assign StringRAMEqualsString = (StringRAM[135:7] == String)? 1'b1:1'b0;
assign CodeBigger128 = (Code > 12'd128)? 1'b1:1'b0;
assign CodeEqualsZero = (Code == 0)? 1'b1:1'b0;
assign FoundStatus = FoundRegister;
//**********************************************************************
//************************* Data to RAM *****************************
//**********************************************************************
assign ramCode = Code[7:0];
assign ramString = String[15:0];
assign ramDicPointer = DicPointer;
//**********************************************************************
//*********************** Data to Buffer ****************************
//**********************************************************************
assign outBuffer = Code;
assign RequestInBuffer = StringLoadBuffer | CharLoadBuffer | BufferInitDicPointer;
//**********************************************************************
//************************** Registers *******************************
//**********************************************************************
reg [17:0] JumpAddress;
reg [143:0] StringRAM;
reg [17:0] DicPointer;
reg [17:0] InitDicPointer;
reg [7:0] Char;
reg FoundRegister;
reg [11:0] Code;
reg [17:0] InsertPointer;
reg [3:0] StringSize;
reg [128:0] String;
// *************** String Size manage **********************************
always@(posedge Clk)
begin
if(StringLoadZero)
begin
StringSize = 4'b0;
end
else if (StringLoadChar || StringLoadBuffer)
begin
StringSize = 4'd1;
end
else if (ConcatenateChar)
begin
StringSize = StringSize+1;
end
else if (StringShiftRight)
begin
StringSize = StringSize-1;
end
end
//**********************************************************************
// *************** String manage ***************************************
always@(posedge Clk)
begin
if(StringLoadZero)
begin
String = 128'b0;
end
else if (StringLoadChar)
begin
String = {120'b0,Char};
end
else if (StringLoadBuffer)
begin
String = {120'b0, InBuffer[7:0]};
end
else if (ConcatenateChar)
begin
String = {String[119:0],Char};
end
else if (StringShiftRight)
begin
String = {8'b0,String[119:0]};
end
else if (ConcatenateStringSize)
begin
String = {String[119:0],StringSize};
end
end
//**********************************************************************
// *************** Insert Pointer manage *******************************
always@(posedge Clk)
begin
if(LoadInsertPointer)
begin
InsertPointer = DicPointer;
end
else if (UpdateInsertPointer)
begin
InsertPointer = InsertPointer+ StringSize/2 +1;
end
end
//**********************************************************************
// *************** Code Manage ****************************************
always@(posedge Clk)
begin
if(CodeLoadZero)
begin
Code = 12'b0;
end
else if (CodeIncrement)
begin
Code = Code +1;
end
end
//**********************************************************************
// *************** Found Manage ************************************
always@(posedge Clk)
begin
if(Found)
begin
FoundRegister = 1'b1;
end
else if (NotFound)
begin
FoundRegister = 1'b0;
end
end
//**********************************************************************
// *************** Char Manage ****************************************
always@(posedge Clk)
begin
if(CharLoadBuffer)
begin
Char = InBuffer[7:0];
end
end
//**********************************************************************
// *************** Init Dictionary Pointer Manage ********************
always@(posedge Clk)
begin
if(BufferInitDicPointer)
begin
InitDicPointer = InBuffer;
end
end
//**********************************************************************
// *************** Dictionary Pointer Manager **************************
always@(posedge Clk)
begin
if(LoadDicPointer)
begin
DicPointer = InitDicPointer;
end
else if (DicPointerIncrement)
begin
DicPointer = DicPointer + 1;
end
else if (LoadJumpAddress)
begin
DicPointer = JumpAddress;
end
else if (DicPointerLoadInsert)
DicPointer = InsertPointer;
end
//**********************************************************************
// *************** Jump Address Manage ********************************
always@(posedge Clk)
begin
if(SetJumpAddress)
begin
JumpAddress = DicPointer + 1 + StringRAM + StringRAM[135:127]/2;
end
end
//**********************************************************************
// *************** StringRAM Manager ***********************************
always@(posedge Clk)
begin
if(StringRAMLoad)
begin
StringRAM = {iRAMBuffer[17:0],StringRAM[135:15]};
end
else if (StringRAMZero)
begin
StringRAM = 144'b0;
end
else if (StringRAMShift)
begin
StringRAM = {16'b0,StringRAM[143:15]};
end
end
//**********************************************************************
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_request_arb (
input req_aclk,
input req_aresetn,
input req_valid,
output req_ready,
input [31:C_ADDR_ALIGN_BITS] req_dest_address,
input [31:C_ADDR_ALIGN_BITS] req_src_address,
input [C_DMA_LENGTH_WIDTH-1:0] req_length,
input req_sync_transfer_start,
output reg eot,
input enable,
input pause,
// Master AXI interface
input m_dest_axi_aclk,
input m_dest_axi_aresetn,
input m_src_axi_aclk,
input m_src_axi_aresetn,
// Write address
output [31:0] m_axi_awaddr,
output [ 7:0] m_axi_awlen,
output [ 2:0] m_axi_awsize,
output [ 1:0] m_axi_awburst,
output [ 2:0] m_axi_awprot,
output [ 3:0] m_axi_awcache,
output m_axi_awvalid,
input m_axi_awready,
// Write data
output [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [(C_M_AXI_DATA_WIDTH/8)-1:0] m_axi_wstrb,
input m_axi_wready,
output m_axi_wvalid,
output m_axi_wlast,
// Write response
input m_axi_bvalid,
input [ 1:0] m_axi_bresp,
output m_axi_bready,
// Read address
input m_axi_arready,
output m_axi_arvalid,
output [31:0] m_axi_araddr,
output [ 7:0] m_axi_arlen,
output [ 2:0] m_axi_arsize,
output [ 1:0] m_axi_arburst,
output [ 2:0] m_axi_arprot,
output [ 3:0] m_axi_arcache,
// Read data and response
input [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
output m_axi_rready,
input m_axi_rvalid,
input [ 1:0] m_axi_rresp,
// Slave streaming AXI interface
input s_axis_aclk,
output s_axis_ready,
input s_axis_valid,
input [C_M_AXI_DATA_WIDTH-1:0] s_axis_data,
input [0:0] s_axis_user,
// Master streaming AXI interface
input m_axis_aclk,
input m_axis_ready,
output m_axis_valid,
output [C_M_AXI_DATA_WIDTH-1:0] m_axis_data,
// Input FIFO interface
input fifo_wr_clk,
input fifo_wr_en,
input [C_M_AXI_DATA_WIDTH-1:0] fifo_wr_din,
output fifo_wr_overflow,
input fifo_wr_sync,
// Input FIFO interface
input fifo_rd_clk,
input fifo_rd_en,
output fifo_rd_valid,
output [C_M_AXI_DATA_WIDTH-1:0] fifo_rd_dout,
output fifo_rd_underflow,
output [C_ID_WIDTH-1:0] dbg_dest_request_id,
output [C_ID_WIDTH-1:0] dbg_dest_address_id,
output [C_ID_WIDTH-1:0] dbg_dest_data_id,
output [C_ID_WIDTH-1:0] dbg_dest_response_id,
output [C_ID_WIDTH-1:0] dbg_src_request_id,
output [C_ID_WIDTH-1:0] dbg_src_address_id,
output [C_ID_WIDTH-1:0] dbg_src_data_id,
output [C_ID_WIDTH-1:0] dbg_src_response_id,
output [7:0] dbg_status
);
parameter C_ID_WIDTH = 3;
parameter C_M_AXI_DATA_WIDTH = 64;
parameter C_DMA_LENGTH_WIDTH = 24;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_DMA_TYPE_DEST = DMA_TYPE_MM_AXI;
parameter C_DMA_TYPE_SRC = DMA_TYPE_FIFO;
parameter C_CLKS_ASYNC_REQ_SRC = 1;
parameter C_CLKS_ASYNC_SRC_DEST = 1;
parameter C_CLKS_ASYNC_DEST_REQ = 1;
parameter C_AXI_SLICE_DEST = 0;
parameter C_AXI_SLICE_SRC = 0;
localparam DMA_TYPE_MM_AXI = 0;
localparam DMA_TYPE_STREAM_AXI = 1;
localparam DMA_TYPE_FIFO = 2;
localparam DMA_ADDR_WIDTH = 32 - C_ADDR_ALIGN_BITS;
reg eot_mem_src[0:2**C_ID_WIDTH-1];
reg eot_mem_dest[0:2**C_ID_WIDTH-1];
wire request_eot;
wire [C_ID_WIDTH-1:0] request_id;
wire [C_ID_WIDTH-1:0] response_id;
wire [C_DMA_LENGTH_WIDTH-7:0] req_burst_count = req_length[C_DMA_LENGTH_WIDTH-1:7];
wire [3:0] req_last_burst_length = req_length[6:3];
wire [2:0] req_last_beat_bytes = req_length[2:0];
wire enabled_src;
wire enabled_dest;
wire sync_id;
wire sync_id_ret_dest;
wire sync_id_ret_src;
wire dest_enable;
wire dest_enabled;
wire dest_pause;
wire dest_sync_id;
wire dest_sync_id_ret;
wire src_enable;
wire src_enabled;
wire src_pause;
wire src_sync_id;
wire src_sync_id_ret;
wire req_dest_valid;
wire req_dest_ready;
wire req_dest_empty;
wire req_src_valid;
wire req_src_ready;
wire req_src_empty;
wire dest_clk;
wire dest_resetn;
wire dest_req_valid;
wire dest_req_ready;
wire [DMA_ADDR_WIDTH-1:0] dest_req_address;
wire [3:0] dest_req_last_burst_length;
wire [2:0] dest_req_last_beat_bytes;
wire dest_response_valid;
wire dest_response_ready;
wire dest_response_empty;
wire [1:0] dest_response_resp;
wire dest_response_resp_eot;
wire [C_ID_WIDTH-1:0] dest_request_id;
wire [C_ID_WIDTH-1:0] dest_response_id;
wire dest_valid;
wire dest_ready;
wire [C_M_AXI_DATA_WIDTH-1:0] dest_data;
wire dest_fifo_valid;
wire dest_fifo_ready;
wire [C_M_AXI_DATA_WIDTH-1:0] dest_fifo_data;
wire src_clk;
wire src_resetn;
wire src_req_valid;
wire src_req_ready;
wire [DMA_ADDR_WIDTH-1:0] src_req_address;
wire [3:0] src_req_last_burst_length;
wire [2:0] src_req_last_beat_bytes;
wire src_req_sync_transfer_start;
wire src_response_valid;
wire src_response_ready;
wire src_response_empty;
wire [1:0] src_response_resp;
wire [C_ID_WIDTH-1:0] src_request_id;
wire [C_ID_WIDTH-1:0] src_response_id;
wire src_valid;
wire src_ready;
wire [C_M_AXI_DATA_WIDTH-1:0] src_data;
wire src_fifo_valid;
wire src_fifo_ready;
wire [C_M_AXI_DATA_WIDTH-1:0] src_fifo_data;
wire src_fifo_empty;
wire fifo_empty;
wire response_dest_valid;
wire response_dest_ready = 1'b1;
wire [1:0] response_dest_resp;
wire response_dest_resp_eot;
wire response_src_valid;
wire response_src_ready = 1'b1;
wire [1:0] response_src_resp;
assign dbg_dest_request_id = dest_request_id;
assign dbg_dest_response_id = dest_response_id;
assign dbg_src_request_id = src_request_id;
assign dbg_src_response_id = src_response_id;
assign sync_id = ~enabled_dest && ~enabled_src && request_id != response_id;
reg enabled;
reg do_enable;
// Enable src and dest if we are in sync
always @(posedge req_aclk)
begin
if (req_aresetn == 1'b0) begin
do_enable <= 1'b0;
end else begin
if (enable) begin
// First make sure we are fully disabled
if (~sync_id_ret_dest && ~sync_id_ret_src &&
response_id == request_id && ~enabled_dest && ~enabled_src &&
req_dest_empty && req_src_empty && fifo_empty)
do_enable <= 1'b1;
end else begin
do_enable <= 1'b0;
end
end
end
// Flag enabled once both src and dest are enabled
always @(posedge req_aclk)
begin
if (req_aresetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (do_enable == 1'b0)
enabled <= 1'b0;
else if (enabled_dest && enabled_src)
enabled <= 1'b1;
end
end
assign dbg_status = {do_enable, enabled, enabled_dest, enabled_src, fifo_empty,
sync_id, sync_id_ret_dest, sync_id_ret_src};
always @(posedge req_aclk)
begin
eot_mem_src[request_id] <= request_eot;
eot_mem_dest[request_id] <= request_eot;
end
always @(posedge req_aclk)
begin
if (req_aresetn == 1'b0) begin
eot <= 1'b0;
end else begin
eot <= response_dest_valid & response_dest_ready & response_dest_resp_eot;
end
end
// Generate reset for reset-less interfaces
generate if (C_DMA_TYPE_SRC == DMA_TYPE_STREAM_AXI || C_DMA_TYPE_SRC == DMA_TYPE_FIFO) begin
reg [2:0] src_resetn_shift = 3'b0;
assign src_resetn = src_resetn_shift[2];
always @(negedge req_aresetn or posedge src_clk) begin
if (~req_aresetn)
src_resetn_shift <= 3'b000;
else
src_resetn_shift <= {src_resetn_shift[1:0], 1'b1};
end
end endgenerate
generate if (C_DMA_TYPE_DEST == DMA_TYPE_STREAM_AXI || C_DMA_TYPE_DEST == DMA_TYPE_FIFO) begin
reg [2:0] dest_resetn_shift = 3'b0;
assign dest_resetn = dest_resetn_shift[2];
always @(negedge req_aresetn or posedge dest_clk) begin
if (~req_aresetn)
dest_resetn_shift <= 3'b000;
else
dest_resetn_shift <= {dest_resetn_shift[1:0], 1'b1};
end
end endgenerate
generate if (C_DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin
assign dest_clk = m_dest_axi_aclk;
assign dest_resetn = m_dest_axi_aresetn;
wire [C_ID_WIDTH-1:0] dest_data_id;
wire [C_ID_WIDTH-1:0] dest_address_id;
wire dest_address_eot = eot_mem_dest[dest_address_id];
wire dest_data_eot = eot_mem_dest[dest_data_id];
wire dest_response_eot = eot_mem_dest[dest_response_id];
assign dbg_dest_address_id = dest_address_id;
assign dbg_dest_data_id = dest_data_id;
dmac_dest_mm_axi #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M_AXI_DATA_WIDTH),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH)
) i_dest_dma_mm (
.m_axi_aclk(m_dest_axi_aclk),
.m_axi_aresetn(m_dest_axi_aresetn),
.enable(dest_enable),
.enabled(dest_enabled),
.pause(dest_pause),
.req_valid(dest_req_valid),
.req_ready(dest_req_ready),
.req_address(dest_req_address),
.req_last_burst_length(dest_req_last_burst_length),
.req_last_beat_bytes(dest_req_last_beat_bytes),
.response_valid(dest_response_valid),
.response_ready(dest_response_ready),
.response_resp(dest_response_resp),
.response_resp_eot(dest_response_resp_eot),
.request_id(dest_request_id),
.response_id(dest_response_id),
.sync_id(dest_sync_id),
.sync_id_ret(dest_sync_id_ret),
.data_id(dest_data_id),
.address_id(dest_address_id),
.address_eot(dest_address_eot),
.data_eot(dest_data_eot),
.response_eot(dest_response_eot),
.fifo_valid(dest_valid),
.fifo_ready(dest_ready),
.fifo_data(dest_data),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awprot(m_axi_awprot),
.m_axi_awcache(m_axi_awcache),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bresp(m_axi_bresp),
.m_axi_bready(m_axi_bready)
);
end else if (C_DMA_TYPE_DEST == DMA_TYPE_STREAM_AXI) begin
assign dest_clk = m_axis_aclk;
wire [C_ID_WIDTH-1:0] data_id;
wire data_eot = eot_mem_dest[data_id];
wire response_eot = eot_mem_dest[dest_response_id];
assign dbg_dest_address_id = dest_request_id;
assign dbg_dest_data_id = data_id;
dmac_dest_axi_stream #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_S_AXIS_DATA_WIDTH(C_M_AXI_DATA_WIDTH)
) i_dest_dma_stream (
.s_axis_aclk(m_axis_aclk),
.s_axis_aresetn(dest_resetn),
.enable(dest_enable),
.enabled(dest_enabled),
.req_valid(dest_req_valid),
.req_ready(dest_req_ready),
.req_last_burst_length(dest_req_last_burst_length),
.response_valid(dest_response_valid),
.response_ready(dest_response_ready),
.response_resp(dest_response_resp),
.response_resp_eot(dest_response_resp_eot),
.request_id(dest_request_id),
.response_id(dest_response_id),
.data_id(data_id),
.sync_id(dest_sync_id),
.sync_id_ret(dest_sync_id_ret),
.data_eot(data_eot),
.response_eot(response_eot),
.fifo_valid(dest_valid),
.fifo_ready(dest_ready),
.fifo_data(dest_data),
.m_axis_valid(m_axis_valid),
.m_axis_ready(m_axis_ready),
.m_axis_data(m_axis_data)
);
end else /* if (C_DMA_TYPE_DEST == DMA_TYPE_FIFO) */ begin
assign dest_clk = fifo_rd_clk;
wire [C_ID_WIDTH-1:0] data_id;
wire data_eot = eot_mem_dest[data_id];
wire response_eot = eot_mem_dest[dest_response_id];
dmac_dest_fifo_inf #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_M_AXI_DATA_WIDTH)
) i_dest_dma_fifo (
.clk(fifo_rd_clk),
.resetn(dest_resetn),
.enable(dest_enable),
.enabled(dest_enabled),
.req_valid(dest_req_valid),
.req_ready(dest_req_ready),
.req_last_burst_length(dest_req_last_burst_length),
.response_valid(dest_response_valid),
.response_ready(dest_response_ready),
.response_resp(dest_response_resp),
.response_resp_eot(dest_response_resp_eot),
.request_id(dest_request_id),
.response_id(dest_response_id),
.data_id(data_id),
.sync_id(dest_sync_id),
.sync_id_ret(dest_sync_id_ret),
.data_eot(data_eot),
.response_eot(response_eot),
.fifo_valid(dest_valid),
.fifo_ready(dest_ready),
.fifo_data(dest_data),
.en(fifo_rd_en),
.valid(fifo_rd_valid),
.dout(fifo_rd_dout),
.underflow(fifo_rd_underflow)
);
end endgenerate
generate if (C_DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin
assign src_clk = m_src_axi_aclk;
assign src_resetn = m_src_axi_aresetn;
wire [C_ID_WIDTH-1:0] src_data_id;
wire [C_ID_WIDTH-1:0] src_address_id;
wire src_address_eot = eot_mem_src[src_address_id];
wire src_data_eot = eot_mem_src[src_data_id];
assign dbg_src_address_id = src_address_id;
assign dbg_src_data_id = src_data_id;
dmac_src_mm_axi #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M_AXI_DATA_WIDTH),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH)
) i_src_dma_mm (
.m_axi_aclk(m_src_axi_aclk),
.m_axi_aresetn(m_src_axi_aresetn),
.enable(src_enable),
.enabled(src_enabled),
.sync_id(src_sync_id),
.sync_id_ret(src_sync_id_ret),
.req_valid(src_req_valid),
.req_ready(src_req_ready),
.req_address(src_req_address),
.req_last_burst_length(src_req_last_burst_length),
.req_last_beat_bytes(src_req_last_beat_bytes),
.response_valid(src_response_valid),
.response_ready(src_response_ready),
.response_resp(src_response_resp),
.request_id(src_request_id),
.response_id(src_response_id),
.address_id(src_address_id),
.data_id(src_data_id),
.address_eot(src_address_eot),
.data_eot(src_data_eot),
.fifo_valid(src_valid),
.fifo_ready(src_ready),
.fifo_data(src_data),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arprot(m_axi_arprot),
.m_axi_arcache(m_axi_arcache),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp)
);
end else if (C_DMA_TYPE_SRC == DMA_TYPE_STREAM_AXI) begin
assign src_clk = s_axis_aclk;
wire src_eot = eot_mem_src[src_response_id];
dmac_src_axi_stream #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_S_AXIS_DATA_WIDTH(C_M_AXI_DATA_WIDTH)
) i_src_dma_stream (
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(src_resetn),
.enable(src_enable),
.enabled(src_enabled),
.sync_id(src_sync_id),
.sync_id_ret(src_sync_id_ret),
.req_valid(src_req_valid),
.req_ready(src_req_ready),
.req_last_burst_length(src_req_last_burst_length),
.req_sync_transfer_start(src_req_sync_transfer_start),
.request_id(src_request_id),
.response_id(src_response_id),
.eot(src_eot),
.fifo_valid(src_valid),
.fifo_ready(src_ready),
.fifo_data(src_data),
.s_axis_valid(s_axis_valid),
.s_axis_ready(s_axis_ready),
.s_axis_data(s_axis_data),
.s_axis_user(s_axis_user)
);
end else /* if (C_DMA_TYPE_SRC == DMA_TYPE_FIFO) */ begin
assign src_clk = fifo_wr_clk;
wire src_eot = eot_mem_src[src_response_id];
dmac_src_fifo_inf #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_M_AXI_DATA_WIDTH)
) i_src_dma_fifo (
.clk(fifo_wr_clk),
.resetn(src_resetn),
.enable(src_enable),
.enabled(src_enabled),
.sync_id(src_sync_id),
.sync_id_ret(src_sync_id_ret),
.req_valid(src_req_valid),
.req_ready(src_req_ready),
.req_last_burst_length(src_req_last_burst_length),
.req_sync_transfer_start(src_req_sync_transfer_start),
.request_id(src_request_id),
.response_id(src_response_id),
.eot(src_eot),
.fifo_valid(src_valid),
.fifo_ready(src_ready),
.fifo_data(src_data),
.en(fifo_wr_en),
.din(fifo_wr_din),
.overflow(fifo_wr_overflow),
.sync(fifo_wr_sync)
);
end endgenerate
sync_bits #(
.NUM_BITS(C_ID_WIDTH),
.CLK_ASYNC(C_CLKS_ASYNC_REQ_SRC)
) i_sync_src_request_id (
.out_clk(src_clk),
.out_resetn(src_resetn),
.in(request_id),
.out(src_request_id)
);
sync_bits #(
.NUM_BITS(C_ID_WIDTH),
.CLK_ASYNC(C_CLKS_ASYNC_SRC_DEST)
) i_sync_dest_request_id (
.out_clk(dest_clk),
.out_resetn(dest_resetn),
.in(src_response_id),
.out(dest_request_id)
);
sync_bits #(
.NUM_BITS(C_ID_WIDTH),
.CLK_ASYNC(C_CLKS_ASYNC_DEST_REQ)
) i_sync_req_response_id (
.out_clk(req_aclk),
.out_resetn(req_aresetn),
.in(dest_response_id),
.out(response_id)
);
axi_register_slice #(
.DATA_WIDTH(C_M_AXI_DATA_WIDTH),
.FORWARD_REGISTERED(C_AXI_SLICE_SRC),
.BACKWARD_REGISTERED(C_AXI_SLICE_SRC)
) i_src_slice (
.clk(src_clk),
.resetn(src_resetn),
.s_axi_valid(src_valid),
.s_axi_ready(src_ready),
.s_axi_data(src_data),
.m_axi_valid(src_fifo_valid),
.m_axi_ready(src_fifo_ready),
.m_axi_data(src_fifo_data)
);
axi_fifo #(
.C_DATA_WIDTH(C_M_AXI_DATA_WIDTH),
.C_ADDRESS_WIDTH(6),
.C_CLKS_ASYNC(C_CLKS_ASYNC_SRC_DEST)
) i_fifo (
.s_axis_aclk(src_clk),
.s_axis_aresetn(src_resetn),
.s_axis_valid(src_fifo_valid),
.s_axis_ready(src_fifo_ready),
.s_axis_data(src_fifo_data),
.s_axis_empty(src_fifo_empty),
.m_axis_aclk(dest_clk),
.m_axis_aresetn(dest_resetn),
.m_axis_valid(dest_fifo_valid),
.m_axis_ready(dest_fifo_ready),
.m_axis_data(dest_fifo_data)
);
wire _dest_valid;
wire _dest_ready;
wire [C_M_AXI_DATA_WIDTH-1:0] _dest_data;
axi_register_slice #(
.DATA_WIDTH(C_M_AXI_DATA_WIDTH),
.FORWARD_REGISTERED(C_AXI_SLICE_DEST)
) i_dest_slice2 (
.clk(dest_clk),
.resetn(dest_resetn),
.s_axi_valid(dest_fifo_valid),
.s_axi_ready(dest_fifo_ready),
.s_axi_data(dest_fifo_data),
.m_axi_valid(_dest_valid),
.m_axi_ready(_dest_ready),
.m_axi_data(_dest_data)
);
axi_register_slice #(
.DATA_WIDTH(C_M_AXI_DATA_WIDTH),
.FORWARD_REGISTERED(C_AXI_SLICE_DEST),
.BACKWARD_REGISTERED(C_AXI_SLICE_DEST)
) i_dest_slice (
.clk(dest_clk),
.resetn(dest_resetn),
.s_axi_valid(_dest_valid),
.s_axi_ready(_dest_ready),
.s_axi_data(_dest_data),
.m_axi_valid(dest_valid),
.m_axi_ready(dest_ready),
.m_axi_data(dest_data)
);
// We do not accept any requests until all components are enabled
wire _req_ready;
assign req_ready = _req_ready & enabled;
splitter #(
.C_NUM_M(3)
) i_req_splitter (
.clk(req_aclk),
.resetn(req_aresetn),
.s_valid(req_valid & enabled),
.s_ready(_req_ready),
.m_valid({
req_gen_valid,
req_dest_valid,
req_src_valid
}),
.m_ready({
req_gen_ready,
req_dest_ready,
req_src_ready
})
);
axi_fifo #(
.C_DATA_WIDTH(DMA_ADDR_WIDTH + 4 + 3),
.C_ADDRESS_WIDTH(0),
.C_CLKS_ASYNC(C_CLKS_ASYNC_DEST_REQ)
) i_dest_req_fifo (
.s_axis_aclk(req_aclk),
.s_axis_aresetn(req_aresetn),
.s_axis_valid(req_dest_valid),
.s_axis_ready(req_dest_ready),
.s_axis_empty(req_dest_empty),
.s_axis_data({
req_dest_address,
req_last_burst_length,
req_last_beat_bytes
}),
.m_axis_aclk(dest_clk),
.m_axis_aresetn(dest_resetn),
.m_axis_valid(dest_req_valid),
.m_axis_ready(dest_req_ready),
.m_axis_data({
dest_req_address,
dest_req_last_burst_length,
dest_req_last_beat_bytes
})
);
axi_fifo #(
.C_DATA_WIDTH(DMA_ADDR_WIDTH + 4 + 3 + 1),
.C_ADDRESS_WIDTH(0),
.C_CLKS_ASYNC(C_CLKS_ASYNC_REQ_SRC)
) i_src_req_fifo (
.s_axis_aclk(req_aclk),
.s_axis_aresetn(req_aresetn),
.s_axis_valid(req_src_valid),
.s_axis_ready(req_src_ready),
.s_axis_empty(req_src_empty),
.s_axis_data({
req_src_address,
req_last_burst_length,
req_last_beat_bytes,
req_sync_transfer_start
}),
.m_axis_aclk(src_clk),
.m_axis_aresetn(src_resetn),
.m_axis_valid(src_req_valid),
.m_axis_ready(src_req_ready),
.m_axis_data({
src_req_address,
src_req_last_burst_length,
src_req_last_beat_bytes,
src_req_sync_transfer_start
})
);
axi_fifo #(
.C_DATA_WIDTH(3),
.C_ADDRESS_WIDTH(0),
.C_CLKS_ASYNC(C_CLKS_ASYNC_DEST_REQ)
) i_dest_response_fifo (
.s_axis_aclk(dest_clk),
.s_axis_aresetn(dest_resetn),
.s_axis_valid(dest_response_valid),
.s_axis_ready(dest_response_ready),
.s_axis_empty(dest_response_empty),
.s_axis_data({
dest_response_resp,
dest_response_resp_eot
}),
.m_axis_aclk(req_aclk),
.m_axis_aresetn(req_aresetn),
.m_axis_valid(response_dest_valid),
.m_axis_ready(response_dest_ready),
.m_axis_data({
response_dest_resp,
response_dest_resp_eot
})
);
axi_fifo #(
.C_DATA_WIDTH(2),
.C_ADDRESS_WIDTH(0),
.C_CLKS_ASYNC(C_CLKS_ASYNC_REQ_SRC)
) i_src_response_fifo (
.s_axis_aclk(src_clk),
.s_axis_aresetn(src_resetn),
.s_axis_valid(src_response_valid),
.s_axis_ready(src_response_ready),
.s_axis_empty(src_response_empty),
.s_axis_data(src_response_resp),
.m_axis_aclk(req_aclk),
.m_axis_aresetn(req_aresetn),
.m_axis_valid(response_src_valid),
.m_axis_ready(response_src_ready),
.m_axis_data(response_src_resp)
);
dmac_request_generator #(
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_ID_WIDTH(C_ID_WIDTH)
) i_req_gen (
.req_aclk(req_aclk),
.req_aresetn(req_aresetn),
.request_id(request_id),
.response_id(response_id),
.req_valid(req_gen_valid),
.req_ready(req_gen_ready),
.req_burst_count(req_burst_count),
.enable(enable),
.pause(pause),
.eot(request_eot)
);
sync_bits #(
.NUM_BITS(3),
.CLK_ASYNC(C_CLKS_ASYNC_DEST_REQ)
) i_sync_control_dest (
.out_clk(dest_clk),
.out_resetn(dest_resetn),
.in({do_enable, pause, sync_id}),
.out({dest_enable, dest_pause, dest_sync_id})
);
sync_bits #(
.NUM_BITS(2),
.CLK_ASYNC(C_CLKS_ASYNC_DEST_REQ)
) i_sync_status_dest (
.out_clk(req_aclk),
.out_resetn(req_aresetn),
.in({dest_enabled | ~dest_response_empty, dest_sync_id_ret}),
.out({enabled_dest, sync_id_ret_dest})
);
sync_bits #(
.NUM_BITS(3),
.CLK_ASYNC(C_CLKS_ASYNC_REQ_SRC)
) i_sync_control_src (
.out_clk(src_clk),
.out_resetn(src_resetn),
.in({do_enable, pause, sync_id}),
.out({src_enable, src_pause, src_sync_id})
);
sync_bits #(
.NUM_BITS(3),
.CLK_ASYNC(C_CLKS_ASYNC_REQ_SRC)
) i_sync_status_src (
.out_clk(req_aclk),
.out_resetn(req_aresetn),
.in({src_enabled | ~src_response_empty, src_sync_id_ret, src_fifo_empty}),
.out({enabled_src, sync_id_ret_src, fifo_empty})
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DIODE_0_V
`define SKY130_FD_SC_LP__DIODE_0_V
/**
* diode: Antenna tie-down diode.
*
* Verilog wrapper for diode with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__diode_0 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__diode_0 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__diode base (
.DIODE(DIODE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DIODE_0_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_buf_pdr_even.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module cpx_buf_pdr_even(/*AUTOARG*/
// Outputs
arbcp0_cpxdp_grant_ca, arbcp0_cpxdp_q0_hold_ca_l,
arbcp0_cpxdp_qsel0_ca, arbcp0_cpxdp_qsel1_ca_l,
arbcp0_cpxdp_shift_cx, arbcp2_cpxdp_grant_ca,
arbcp2_cpxdp_q0_hold_ca_l, arbcp2_cpxdp_qsel0_ca,
arbcp2_cpxdp_qsel1_ca_l, arbcp2_cpxdp_shift_cx,
arbcp4_cpxdp_grant_ca, arbcp4_cpxdp_q0_hold_ca_l,
arbcp4_cpxdp_qsel0_ca, arbcp4_cpxdp_qsel1_ca_l,
arbcp4_cpxdp_shift_cx, arbcp6_cpxdp_grant_ca,
arbcp6_cpxdp_q0_hold_ca_l, arbcp6_cpxdp_qsel0_ca,
arbcp6_cpxdp_qsel1_ca_l, arbcp6_cpxdp_shift_cx,
// Inputs
arbcp0_cpxdp_grant_bufp3_ca, arbcp0_cpxdp_q0_hold_bufp3_ca_l,
arbcp0_cpxdp_qsel0_bufp3_ca, arbcp0_cpxdp_qsel1_bufp3_ca_l,
arbcp0_cpxdp_shift_bufp3_cx, arbcp2_cpxdp_grant_bufp3_ca,
arbcp2_cpxdp_q0_hold_bufp3_ca_l, arbcp2_cpxdp_qsel0_bufp3_ca,
arbcp2_cpxdp_qsel1_bufp3_ca_l, arbcp2_cpxdp_shift_bufp3_cx,
arbcp4_cpxdp_grant_bufp3_ca, arbcp4_cpxdp_q0_hold_bufp3_ca_l,
arbcp4_cpxdp_qsel0_bufp3_ca, arbcp4_cpxdp_qsel1_bufp3_ca_l,
arbcp4_cpxdp_shift_bufp3_cx, arbcp6_cpxdp_grant_bufp3_ca,
arbcp6_cpxdp_q0_hold_bufp3_ca_l, arbcp6_cpxdp_qsel0_bufp3_ca,
arbcp6_cpxdp_qsel1_bufp3_ca_l, arbcp6_cpxdp_shift_bufp3_cx
);
output arbcp0_cpxdp_grant_ca ;
output arbcp0_cpxdp_q0_hold_ca_l ;
output arbcp0_cpxdp_qsel0_ca ;
output arbcp0_cpxdp_qsel1_ca_l ;
output arbcp0_cpxdp_shift_cx ;
output arbcp2_cpxdp_grant_ca ;
output arbcp2_cpxdp_q0_hold_ca_l ;
output arbcp2_cpxdp_qsel0_ca ;
output arbcp2_cpxdp_qsel1_ca_l ;
output arbcp2_cpxdp_shift_cx ;
output arbcp4_cpxdp_grant_ca ;
output arbcp4_cpxdp_q0_hold_ca_l ;
output arbcp4_cpxdp_qsel0_ca ;
output arbcp4_cpxdp_qsel1_ca_l ;
output arbcp4_cpxdp_shift_cx ;
output arbcp6_cpxdp_grant_ca ;
output arbcp6_cpxdp_q0_hold_ca_l ;
output arbcp6_cpxdp_qsel0_ca ;
output arbcp6_cpxdp_qsel1_ca_l ;
output arbcp6_cpxdp_shift_cx ;
input arbcp0_cpxdp_grant_bufp3_ca;
input arbcp0_cpxdp_q0_hold_bufp3_ca_l;
input arbcp0_cpxdp_qsel0_bufp3_ca;
input arbcp0_cpxdp_qsel1_bufp3_ca_l;
input arbcp0_cpxdp_shift_bufp3_cx;
input arbcp2_cpxdp_grant_bufp3_ca;
input arbcp2_cpxdp_q0_hold_bufp3_ca_l;
input arbcp2_cpxdp_qsel0_bufp3_ca;
input arbcp2_cpxdp_qsel1_bufp3_ca_l;
input arbcp2_cpxdp_shift_bufp3_cx;
input arbcp4_cpxdp_grant_bufp3_ca;
input arbcp4_cpxdp_q0_hold_bufp3_ca_l;
input arbcp4_cpxdp_qsel0_bufp3_ca;
input arbcp4_cpxdp_qsel1_bufp3_ca_l;
input arbcp4_cpxdp_shift_bufp3_cx;
input arbcp6_cpxdp_grant_bufp3_ca;
input arbcp6_cpxdp_q0_hold_bufp3_ca_l;
input arbcp6_cpxdp_qsel0_bufp3_ca;
input arbcp6_cpxdp_qsel1_bufp3_ca_l;
input arbcp6_cpxdp_shift_bufp3_cx;
assign arbcp0_cpxdp_grant_ca = arbcp0_cpxdp_grant_bufp3_ca;
assign arbcp0_cpxdp_q0_hold_ca_l = arbcp0_cpxdp_q0_hold_bufp3_ca_l;
assign arbcp0_cpxdp_qsel0_ca = arbcp0_cpxdp_qsel0_bufp3_ca;
assign arbcp0_cpxdp_qsel1_ca_l = arbcp0_cpxdp_qsel1_bufp3_ca_l;
assign arbcp0_cpxdp_shift_cx = arbcp0_cpxdp_shift_bufp3_cx;
assign arbcp2_cpxdp_grant_ca = arbcp2_cpxdp_grant_bufp3_ca;
assign arbcp2_cpxdp_q0_hold_ca_l = arbcp2_cpxdp_q0_hold_bufp3_ca_l;
assign arbcp2_cpxdp_qsel0_ca = arbcp2_cpxdp_qsel0_bufp3_ca;
assign arbcp2_cpxdp_qsel1_ca_l = arbcp2_cpxdp_qsel1_bufp3_ca_l;
assign arbcp2_cpxdp_shift_cx = arbcp2_cpxdp_shift_bufp3_cx;
assign arbcp4_cpxdp_grant_ca = arbcp4_cpxdp_grant_bufp3_ca;
assign arbcp4_cpxdp_q0_hold_ca_l = arbcp4_cpxdp_q0_hold_bufp3_ca_l;
assign arbcp4_cpxdp_qsel0_ca = arbcp4_cpxdp_qsel0_bufp3_ca;
assign arbcp4_cpxdp_qsel1_ca_l = arbcp4_cpxdp_qsel1_bufp3_ca_l;
assign arbcp4_cpxdp_shift_cx = arbcp4_cpxdp_shift_bufp3_cx;
assign arbcp6_cpxdp_grant_ca = arbcp6_cpxdp_grant_bufp3_ca;
assign arbcp6_cpxdp_q0_hold_ca_l = arbcp6_cpxdp_q0_hold_bufp3_ca_l;
assign arbcp6_cpxdp_qsel0_ca = arbcp6_cpxdp_qsel0_bufp3_ca;
assign arbcp6_cpxdp_qsel1_ca_l = arbcp6_cpxdp_qsel1_bufp3_ca_l;
assign arbcp6_cpxdp_shift_cx = arbcp6_cpxdp_shift_bufp3_cx;
endmodule
|
module pipeline2(
clk_in, // clock_in
RST, // reset
pc_in, // entrada - contador de programa
instr, // instrucao
reg_addr, // endereco do registrador a ser gravado
reg_data, // dados a serem gravados no registrador reg_addr
reg_en, // habilita gravacao de reg_data em reg_addr no banco de registradores
A_addr, // endereco do registrador 1
B_addr, // endereco do registrador 2
A, // dados do registrador 1
B, // dados do registrador 2
imm, // immediato
pc_out, // saida - contador de programa
ctrl // saida - controller do processador,
);
// faz o include dos parameters das instrucoes
`include "params_proc.v"
// declaracao de entrada / saida
input clk_in, RST;
input [PC_WIDTH-1:0] pc_in;
input [INSTR_WIDTH-1:0] instr;
input [REG_ADDR_WIDTH-1:0] reg_addr;
input [DATA_WIDTH-1:0] reg_data;
input reg_en;
output reg signed [DATA_WIDTH-1:0] imm;
output reg [PC_WIDTH-1:0] pc_out;
output reg [REG_ADDR_WIDTH-1:0] A_addr, B_addr;
output signed [DATA_WIDTH-1:0] A, B;
output [CTRL_WIDTH-1:0] ctrl;
// variaveis auxiliares
reg [OPCODE_WIDTH-1:0] opcode;
wire clk_neg;
// instanciacao do controller e do banco de registradores
controller ctrl0(.opcode(opcode), .ctrl(ctrl));
regs regs0(.clk(clk_neg),
.en_write(reg_en), .addr_write(reg_addr), .data_write(reg_data),
.addr_read1(A_addr), .addr_read2(B_addr),
.data_read1(A), .data_read2(B));
assign clk_neg = ~clk_in;
// decodifique a instrucao e
// gera done indicando dados de saida estaveis
always @(posedge clk_in) begin
if (!RST) begin
// rotina de reset
opcode <= NOP;
A_addr <= 0;
B_addr <= 0;
imm <= 0;
// reset - PC vai pro valor inicial
pc_out <= PC_INITIAL + 1;
end else begin
opcode <= instr[OPCODE_WIDTH-1:0];
A_addr <= instr[OPCODE_WIDTH+REG_ADDR_WIDTH-1:OPCODE_WIDTH];
B_addr <= instr[OPCODE_WIDTH+REG_ADDR_WIDTH*2-1:OPCODE_WIDTH+REG_ADDR_WIDTH];
imm <= instr[INSTR_WIDTH-1:OPCODE_WIDTH+REG_ADDR_WIDTH*2];
// se opcode == RET, entao leia o registrador REG_FUNC_RET
if (instr[OPCODE_WIDTH-1:0] == RET) begin
A_addr <= REG_FUNC_RET;
end
// faca pc_out = pc_in (nao mexemos no pc no pipeline 2)
pc_out <= pc_in;
end
end
endmodule
|
module system ( input CLK,
//DE0 ADC
output ADC_CS,
output ADC_SCLK,
output ADC_SDO,
input ADC_SDI,
//DE0 USER IO
input [1:0] BTNS,
input [3:0] DIP_SW,
output [7:0] LEDS );
//==================WIRE DECLARATIONS============================//
wire CLK_CPU, CLK_MEM, CLK_1M, RESET, RUN, I_SOURCE;
wire [31:0] INST_RD, CPU_RD, CPU_WD, STACK_MEM_WD, STACK_MEM_RD,
INST_D_RD, INST_D_WD;
wire [29:0] INST_ADDR, CPU_ADDR, STACK_MEM_A, INST_D_A;
wire [3:0] CPU_BE, STACK_MEM_BE;
wire CPU_WE, STACK_MEM_WE, INST_D_WE;
//JTAG signals
wire JTAG_WE;
wire [31:0] JTAG_WD, JTAG_RD, DEBUG_INST, CPU_INSTRUCTION;
//ADC signals
wire ADC_WE;
wire [31:0] ADC_RD, ADC_WD;
//USER IO
wire [31:0] USER_IO;
//Led signals
wire [31:0] LEDS_WD;
wire LEDS_WE;
//===================SYSTEM CLOCK================================//
pll main_pll(CLK, CLK_CPU, CLK_MEM, CLK_1M);
//======================THE CPU==================================//
mcpu the_cpu (.CLK ( CLK_CPU ),
.CLK_MEM ( CLK_MEM ),
.RESET ( RESET ),
.RUN ( RUN ),
//External inst memory iface
.INST_ADDR ( INST_ADDR ),
.INST_RD ( CPU_INSTRUCTION ),
//External data memory iface
.DATA_WE ( CPU_WE ),
.DATA_BE ( CPU_BE ),
.DATA_ADDR ( CPU_ADDR ),
.DATA_WD ( CPU_WD ),
.DATA_RD ( CPU_RD ));
//===================INSTRUCTION MEMORY==========================//
imem instr_mem( .CLK ( CLK_MEM ),
.DATA_A ( INST_D_A ),
.DATA_WE ( INST_D_WE ),
.DATA_WD ( INST_D_WD ),
.DATA_RD ( INST_D_RD ),
.MAIN_A ( INST_ADDR ),
.MAIN_RD ( INST_RD ));
//======================STACK SPACE==============================//
dmem stack_mem( .CLK ( CLK_MEM ),
.WE ( STACK_MEM_WE ),
.BE ( STACK_MEM_BE ),
.ADDR ( STACK_MEM_A ),
.WD ( STACK_MEM_WD ),
.RD ( STACK_MEM_RD ));
jtag jtag_m ( .CPU_CLK ( CLK_CPU ),
//CPU controls
.RESET ( RESET ), //cpu reset, 1 -- reset;
.RUN ( RUN ), //cpu run. 0 - pause, 1 - run. Pulsed in step-by-step
.I_SOURCE ( I_SOURCE ), //cpu instruction source; 0 for normal mem
//32bit DEBUG DATA PORT
.WE ( JTAG_WE ),
.WD ( JTAG_WD ),
.RD ( JTAG_RD ),
//32bit DEBUG INSTR PORT
.DEBUG_INST ( DEBUG_INST ), //cpu instruction from jtag
.MEM_INST ( INST_RD ), //current instruction from main mem
.INST_ADDR ( INST_ADDR )); //cpu inst memory address
mux2 isrc_mux (I_SOURCE, INST_RD,
DEBUG_INST, CPU_INSTRUCTION );
//=====================BUS CONTROLLER============================//
bus_controller bc( .CPU_ADDR ( CPU_ADDR ),
.CPU_WE ( CPU_WE ),
.CPU_BE ( CPU_BE ),
.CPU_WD ( CPU_WD ),
.CPU_RD ( CPU_RD ),
.STACK_MEM_A ( STACK_MEM_A ),
.STACK_MEM_BE ( STACK_MEM_BE ),
.STACK_MEM_WE ( STACK_MEM_WE ),
.STACK_MEM_WD ( STACK_MEM_WD ),
.STACK_MEM_RD ( STACK_MEM_RD ),
.CODE_MEM_A ( INST_D_A ),
.CODE_MEM_WE ( INST_D_WE ),
.CODE_MEM_WD ( INST_D_WD ),
.CODE_MEM_RD ( INST_D_RD ),
.JTAG_WE ( JTAG_WE ),
.JTAG_WD ( JTAG_WD ),
.JTAG_RD ( JTAG_RD ),
.ADC_WE ( ADC_WE ),
.ADC_WD ( ADC_WD ),
.ADC_RD ( ADC_RD ),
.USER_IO ( USER_IO ),
.LEDS_WE ( LEDS_WE ),
.LEDS_WD ( LEDS_WD ));
//========================LEDS===================================//
io8 led_reg( .CLK ( CLK_CPU ),
.WE ( LEDS_WE ),
.DATA_IN ( LEDS_WD ),
.IO_OUT ( LEDS ));
//======================USER INPUT===============================//
io6 user_io( .CLK_IO ( CLK_1M ),
.BTNS ( BTNS ),
.DIP_SW ( DIP_SW ),
.IO_OUT ( USER_IO ));
//=========================ADC===================================//
adc_interface the_adc( .CLK ( CLK_CPU ),
.CLK_1M ( CLK_1M ),
//processor interface
.DATA_IN ( ADC_WD ),
.DATA_OUT ( ADC_RD ),
.WR ( ADC_WE ),
//device interface
.CS ( ADC_CS ),
.SCLK ( ADC_SCLK ),
.SDO ( ADC_SDO ),
.SDI ( ADC_SDI ));
endmodule
//===============================================================//
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_clkgn_ssiclk.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_clsp_clkgn_nstep
//
//-----------------------------------------------------------------------------
`include "sys.h"
module ctu_clsp_clkgn_ssiclk(/*AUTOARG*/
// Outputs
ctu_jbi_ssiclk,
// Inputs
io_pwron_rst_l, jbus_clk, ssiclk_enable
);
input io_pwron_rst_l;
input jbus_clk;
input ssiclk_enable;
output ctu_jbi_ssiclk;
wire jbus_clk_stage1_nxt;
wire jbus_clk_stage1;
wire ctu_jbi_ssiclk;
assign jbus_clk_stage1_nxt = jbus_clk_stage1 | ctu_jbi_ssiclk?
~ctu_jbi_ssiclk : (~ctu_jbi_ssiclk & ssiclk_enable);
dffrl_async_ns u_ctu_jbi_ssiclk_d1 (
.din (jbus_clk_stage1_nxt),
.clk (jbus_clk),
.rst_l(io_pwron_rst_l),
.q(jbus_clk_stage1));
dffrl_async_ns u_ctu_jbi_ssiclk_d2 (
.din (jbus_clk_stage1),
.clk (jbus_clk),
.rst_l(io_pwron_rst_l),
.q(ctu_jbi_ssiclk));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// verilog-library-files: ("../../common/rtl/swrvr_clib.v")
// verilog-auto-sense-defines-constant:t
// End:
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_t
//
// Generated
// by: wig
// on: Thu Jun 22 05:51:07 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../highlow.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_t.v,v 1.3 2006/06/22 07:20:00 wig Exp $
// $Date: 2006/06/22 07:20:00 $
// $Log: ent_t.v,v $
// Revision 1.3 2006/06/22 07:20:00 wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
//
// Generator: mix_0.pl Revision: 1.45 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_t
//
// No user `defines in this module
module ent_t
//
// Generated Module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire mix_logic0_0;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign mix_logic0_0 = 1'b0;
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
ent_a inst_a (
.low_bit_a(mix_logic0_0) // Ground bit port
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
ent_b inst_b (
);
// End of Generated Instance Port Map for inst_b
endmodule
//
// End of Generated Module rtl of ent_t
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:48:31 MST 2014
// Date : Tue Feb 10 12:36:17 2015
// Host : austin_workstation_1 running 64-bit Fedora release 20 (Heisenbug)
// Command : write_verilog -force -mode funcsim
// /home/luis/FIRMWARE/git/vhdl/ip_blocks/sip_capture_x4/src/fifo_64_in_out/fifo_64in_out_funcsim.v
// Design : fifo_64in_out
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7vx485tffg1157-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v12_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "fifo_64in_out,fifo_generator_v12_0,{}" *)
(* core_generation_info = "fifo_64in_out,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=12,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=1,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=4kx9,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=4093,C_PROG_FULL_THRESH_NEGATE_VAL=4092,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=12,C_RD_DEPTH=4096,C_RD_FREQ=1,C_RD_PNTR_WIDTH=12,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=12,C_WR_DEPTH=4096,C_WR_FREQ=1,C_WR_PNTR_WIDTH=12,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}" *)
(* NotValidForBitStream *)
module fifo_64in_out
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
valid,
rd_data_count);
input rst;
input wr_clk;
input rd_clk;
input [63:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
output [63:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
output valid;
output [11:0]rd_data_count;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_clk;
wire [11:0]rd_data_count;
wire rd_en;
wire rst;
wire valid;
wire wr_clk;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [11:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [11:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "12" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "64" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "virtex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "1" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "1" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "4kx9" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "4093" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "4092" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "12" *)
(* C_RD_DEPTH = "4096" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "12" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "12" *)
(* C_WR_DEPTH = "4096" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "12" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
fifo_64in_out_fifo_generator_v12_0__parameterized0 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[11:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(valid),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[11:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module fifo_64in_out_blk_mem_gen_generic_cstr
(dout,
wr_clk,
rd_clk,
I1,
tmp_ram_rd_en,
Q,
O2,
O1,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input I1;
input tmp_ram_rd_en;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [63:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [63:0]din;
wire [63:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_width \ramloop[0].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[3:0]),
.dout(dout[3:0]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[12:4]),
.dout(dout[12:4]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[21:13]),
.dout(dout[21:13]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[30:22]),
.dout(dout[30:22]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[39:31]),
.dout(dout[39:31]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[48:40]),
.dout(dout[48:40]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[57:49]),
.dout(dout[57:49]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din[63:58]),
.dout(dout[63:58]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_64in_out_blk_mem_gen_prim_width
(dout,
wr_clk,
rd_clk,
I1,
tmp_ram_rd_en,
Q,
O2,
O1,
din);
output [3:0]dout;
input wr_clk;
input rd_clk;
input I1;
input tmp_ram_rd_en;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [3:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [3:0]din;
wire [3:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_64in_out_blk_mem_gen_prim_width__parameterized0
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_64in_out_blk_mem_gen_prim_width__parameterized1
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_64in_out_blk_mem_gen_prim_width__parameterized2
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_64in_out_blk_mem_gen_prim_width__parameterized3
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_64in_out_blk_mem_gen_prim_width__parameterized4
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_64in_out_blk_mem_gen_prim_width__parameterized5
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_64in_out_blk_mem_gen_prim_width__parameterized6
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [5:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [5:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [5:0]din;
wire [5:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_64in_out_blk_mem_gen_prim_wrapper
(dout,
wr_clk,
rd_clk,
I1,
tmp_ram_rd_en,
Q,
O2,
O1,
din);
output [3:0]dout;
input wr_clk;
input rd_clk;
input I1;
input tmp_ram_rd_en;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [3:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [3:0]din;
wire [3:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({O2,1'b0,1'b0}),
.ADDRBWRADDR({O1,1'b0,1'b0}),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:4],dout}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized0
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O2,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({I1,I1,I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized1
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O2,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({I1,I1,I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized2
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O2,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({I1,I1,I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized3
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O2,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({I1,I1,I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized4
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O2,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({I1,I1,I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized5
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [8:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [8:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [8:0]din;
wire [8:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O2,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({I1,I1,I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_64in_out_blk_mem_gen_prim_wrapper__parameterized6
(dout,
I1,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O2,
O1,
din);
output [5:0]dout;
input I1;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [5:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [5:0]din;
wire [5:0]dout;
wire \n_60_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire \n_61_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O2,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\n_60_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,\n_61_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,dout}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(I1),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({I1,I1,I1,I1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module fifo_64in_out_blk_mem_gen_top
(dout,
wr_clk,
rd_clk,
I1,
tmp_ram_rd_en,
Q,
O2,
O1,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input I1;
input tmp_ram_rd_en;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [63:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [63:0]din;
wire [63:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_generic_cstr \valid.cstr
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *)
module fifo_64in_out_blk_mem_gen_v8_2__parameterized0
(dout,
wr_clk,
rd_clk,
I1,
tmp_ram_rd_en,
Q,
O2,
O1,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input I1;
input tmp_ram_rd_en;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [63:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [63:0]din;
wire [63:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module fifo_64in_out_blk_mem_gen_v8_2_synth
(dout,
wr_clk,
rd_clk,
I1,
tmp_ram_rd_en,
Q,
O2,
O1,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input I1;
input tmp_ram_rd_en;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [63:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [63:0]din;
wire [63:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module fifo_64in_out_clk_x_pntrs
(S,
WR_PNTR_RD,
O1,
O2,
RD_PNTR_WR,
Q,
I1,
wr_clk,
I2,
rd_clk,
I3);
output [3:0]S;
output [11:0]WR_PNTR_RD;
output [3:0]O1;
output [3:0]O2;
output [11:0]RD_PNTR_WR;
input [11:0]Q;
input [11:0]I1;
input wr_clk;
input [0:0]I2;
input rd_clk;
input [0:0]I3;
wire [11:0]I1;
wire [0:0]I2;
wire [0:0]I3;
wire [3:0]O1;
wire [3:0]O2;
wire [11:0]Q;
wire [11:0]Q_0;
wire [11:0]RD_PNTR_WR;
wire [3:0]S;
wire [11:0]WR_PNTR_RD;
wire \n_0_gsync_stage[1].wr_stg_inst ;
wire \n_0_gsync_stage[2].wr_stg_inst ;
wire \n_0_rd_pntr_gc[0]_i_1 ;
wire \n_0_rd_pntr_gc[10]_i_1 ;
wire \n_0_rd_pntr_gc[1]_i_1 ;
wire \n_0_rd_pntr_gc[2]_i_1 ;
wire \n_0_rd_pntr_gc[3]_i_1 ;
wire \n_0_rd_pntr_gc[4]_i_1 ;
wire \n_0_rd_pntr_gc[5]_i_1 ;
wire \n_0_rd_pntr_gc[6]_i_1 ;
wire \n_0_rd_pntr_gc[7]_i_1 ;
wire \n_0_rd_pntr_gc[8]_i_1 ;
wire \n_0_rd_pntr_gc[9]_i_1 ;
wire \n_10_gsync_stage[1].wr_stg_inst ;
wire \n_10_gsync_stage[2].wr_stg_inst ;
wire \n_11_gsync_stage[1].wr_stg_inst ;
wire \n_11_gsync_stage[2].wr_stg_inst ;
wire \n_1_gsync_stage[1].wr_stg_inst ;
wire \n_1_gsync_stage[2].wr_stg_inst ;
wire \n_2_gsync_stage[1].wr_stg_inst ;
wire \n_2_gsync_stage[2].wr_stg_inst ;
wire \n_3_gsync_stage[1].wr_stg_inst ;
wire \n_3_gsync_stage[2].wr_stg_inst ;
wire \n_4_gsync_stage[1].wr_stg_inst ;
wire \n_4_gsync_stage[2].wr_stg_inst ;
wire \n_5_gsync_stage[1].wr_stg_inst ;
wire \n_5_gsync_stage[2].wr_stg_inst ;
wire \n_6_gsync_stage[1].wr_stg_inst ;
wire \n_6_gsync_stage[2].wr_stg_inst ;
wire \n_7_gsync_stage[1].wr_stg_inst ;
wire \n_7_gsync_stage[2].wr_stg_inst ;
wire \n_8_gsync_stage[1].wr_stg_inst ;
wire \n_8_gsync_stage[2].wr_stg_inst ;
wire \n_9_gsync_stage[1].wr_stg_inst ;
wire \n_9_gsync_stage[2].wr_stg_inst ;
wire [11:0]p_0_in;
wire [10:0]p_0_in10_out;
wire rd_clk;
wire [11:0]rd_pntr_gc;
wire wr_clk;
wire [11:0]wr_pntr_gc;
fifo_64in_out_synchronizer_ff \gsync_stage[1].rd_stg_inst
(.I1(wr_pntr_gc),
.I3(I3),
.Q(Q_0),
.rd_clk(rd_clk));
fifo_64in_out_synchronizer_ff_3 \gsync_stage[1].wr_stg_inst
(.I1(rd_pntr_gc),
.I2(I2),
.Q({\n_0_gsync_stage[1].wr_stg_inst ,\n_1_gsync_stage[1].wr_stg_inst ,\n_2_gsync_stage[1].wr_stg_inst ,\n_3_gsync_stage[1].wr_stg_inst ,\n_4_gsync_stage[1].wr_stg_inst ,\n_5_gsync_stage[1].wr_stg_inst ,\n_6_gsync_stage[1].wr_stg_inst ,\n_7_gsync_stage[1].wr_stg_inst ,\n_8_gsync_stage[1].wr_stg_inst ,\n_9_gsync_stage[1].wr_stg_inst ,\n_10_gsync_stage[1].wr_stg_inst ,\n_11_gsync_stage[1].wr_stg_inst }),
.wr_clk(wr_clk));
fifo_64in_out_synchronizer_ff_4 \gsync_stage[2].rd_stg_inst
(.D(Q_0),
.I3(I3),
.p_0_in(p_0_in),
.rd_clk(rd_clk));
fifo_64in_out_synchronizer_ff_5 \gsync_stage[2].wr_stg_inst
(.D({\n_0_gsync_stage[1].wr_stg_inst ,\n_1_gsync_stage[1].wr_stg_inst ,\n_2_gsync_stage[1].wr_stg_inst ,\n_3_gsync_stage[1].wr_stg_inst ,\n_4_gsync_stage[1].wr_stg_inst ,\n_5_gsync_stage[1].wr_stg_inst ,\n_6_gsync_stage[1].wr_stg_inst ,\n_7_gsync_stage[1].wr_stg_inst ,\n_8_gsync_stage[1].wr_stg_inst ,\n_9_gsync_stage[1].wr_stg_inst ,\n_10_gsync_stage[1].wr_stg_inst ,\n_11_gsync_stage[1].wr_stg_inst }),
.I2(I2),
.O1({\n_1_gsync_stage[2].wr_stg_inst ,\n_2_gsync_stage[2].wr_stg_inst ,\n_3_gsync_stage[2].wr_stg_inst ,\n_4_gsync_stage[2].wr_stg_inst ,\n_5_gsync_stage[2].wr_stg_inst ,\n_6_gsync_stage[2].wr_stg_inst ,\n_7_gsync_stage[2].wr_stg_inst ,\n_8_gsync_stage[2].wr_stg_inst ,\n_9_gsync_stage[2].wr_stg_inst ,\n_10_gsync_stage[2].wr_stg_inst ,\n_11_gsync_stage[2].wr_stg_inst }),
.Q(\n_0_gsync_stage[2].wr_stg_inst ),
.wr_clk(wr_clk));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[11]_i_2
(.I0(WR_PNTR_RD[11]),
.I1(Q[11]),
.O(O2[3]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[11]_i_3
(.I0(WR_PNTR_RD[10]),
.I1(Q[10]),
.O(O2[2]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[11]_i_4
(.I0(WR_PNTR_RD[9]),
.I1(Q[9]),
.O(O2[1]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[11]_i_5
(.I0(WR_PNTR_RD[8]),
.I1(Q[8]),
.O(O2[0]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_2
(.I0(WR_PNTR_RD[3]),
.I1(Q[3]),
.O(S[3]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_3
(.I0(WR_PNTR_RD[2]),
.I1(Q[2]),
.O(S[2]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_4
(.I0(WR_PNTR_RD[1]),
.I1(Q[1]),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_5
(.I0(WR_PNTR_RD[0]),
.I1(Q[0]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_2
(.I0(WR_PNTR_RD[7]),
.I1(Q[7]),
.O(O1[3]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_3
(.I0(WR_PNTR_RD[6]),
.I1(Q[6]),
.O(O1[2]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_4
(.I0(WR_PNTR_RD[5]),
.I1(Q[5]),
.O(O1[1]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_5
(.I0(WR_PNTR_RD[4]),
.I1(Q[4]),
.O(O1[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_11_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_1_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[10]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[11]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_0_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[11]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_10_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_9_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_8_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_7_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_6_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_5_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_4_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[7]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_3_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[8]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_2_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[9]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[0]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(\n_0_rd_pntr_gc[0]_i_1 ));
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[10]_i_1
(.I0(Q[10]),
.I1(Q[11]),
.O(\n_0_rd_pntr_gc[10]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[1]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.O(\n_0_rd_pntr_gc[1]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[2]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.O(\n_0_rd_pntr_gc[2]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[3]_i_1
(.I0(Q[3]),
.I1(Q[4]),
.O(\n_0_rd_pntr_gc[3]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[4]_i_1
(.I0(Q[4]),
.I1(Q[5]),
.O(\n_0_rd_pntr_gc[4]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[5]_i_1
(.I0(Q[5]),
.I1(Q[6]),
.O(\n_0_rd_pntr_gc[5]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[6]_i_1
(.I0(Q[6]),
.I1(Q[7]),
.O(\n_0_rd_pntr_gc[6]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[7]_i_1
(.I0(Q[7]),
.I1(Q[8]),
.O(\n_0_rd_pntr_gc[7]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[8]_i_1
(.I0(Q[8]),
.I1(Q[9]),
.O(\n_0_rd_pntr_gc[8]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[9]_i_1
(.I0(Q[9]),
.I1(Q[10]),
.O(\n_0_rd_pntr_gc[9]_i_1 ));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[0]_i_1 ),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[10]_i_1 ),
.Q(rd_pntr_gc[10]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[11]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(Q[11]),
.Q(rd_pntr_gc[11]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[1]_i_1 ),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[2]_i_1 ),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[3]_i_1 ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[4]_i_1 ),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[5]_i_1 ),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[6]_i_1 ),
.Q(rd_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[7]_i_1 ),
.Q(rd_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[8]_i_1 ),
.Q(rd_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[9]_i_1 ),
.Q(rd_pntr_gc[9]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[0]),
.Q(WR_PNTR_RD[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[10]),
.Q(WR_PNTR_RD[10]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[11]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[11]),
.Q(WR_PNTR_RD[11]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[1]),
.Q(WR_PNTR_RD[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[2]),
.Q(WR_PNTR_RD[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[3]),
.Q(WR_PNTR_RD[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[4]),
.Q(WR_PNTR_RD[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[5]),
.Q(WR_PNTR_RD[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[6]),
.Q(WR_PNTR_RD[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[7]),
.Q(WR_PNTR_RD[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[8]),
.Q(WR_PNTR_RD[8]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[9]),
.Q(WR_PNTR_RD[9]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[0]_i_1
(.I0(I1[0]),
.I1(I1[1]),
.O(p_0_in10_out[0]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[10]_i_1
(.I0(I1[10]),
.I1(I1[11]),
.O(p_0_in10_out[10]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[1]_i_1
(.I0(I1[1]),
.I1(I1[2]),
.O(p_0_in10_out[1]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[2]_i_1
(.I0(I1[2]),
.I1(I1[3]),
.O(p_0_in10_out[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[3]_i_1
(.I0(I1[3]),
.I1(I1[4]),
.O(p_0_in10_out[3]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[4]_i_1
(.I0(I1[4]),
.I1(I1[5]),
.O(p_0_in10_out[4]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[5]_i_1
(.I0(I1[5]),
.I1(I1[6]),
.O(p_0_in10_out[5]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[6]_i_1
(.I0(I1[6]),
.I1(I1[7]),
.O(p_0_in10_out[6]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[7]_i_1
(.I0(I1[7]),
.I1(I1[8]),
.O(p_0_in10_out[7]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[8]_i_1
(.I0(I1[8]),
.I1(I1[9]),
.O(p_0_in10_out[8]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[9]_i_1
(.I0(I1[9]),
.I1(I1[10]),
.O(p_0_in10_out[9]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[10]),
.Q(wr_pntr_gc[10]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[11]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[11]),
.Q(wr_pntr_gc[11]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[5]),
.Q(wr_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[6]),
.Q(wr_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[7]),
.Q(wr_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[8]),
.Q(wr_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[9]),
.Q(wr_pntr_gc[9]));
endmodule
(* ORIG_REF_NAME = "compare" *)
module fifo_64in_out_compare
(comp1,
Q,
RD_PNTR_WR);
output comp1;
input [11:0]Q;
input [11:0]RD_PNTR_WR;
wire [11:0]Q;
wire [11:0]RD_PNTR_WR;
wire comp1;
wire \n_0_gmux.gm[3].gms.ms ;
wire [5:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(Q[0]),
.I1(RD_PNTR_WR[0]),
.I2(Q[1]),
.I3(RD_PNTR_WR[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(Q[2]),
.I1(RD_PNTR_WR[2]),
.I2(Q[3]),
.I3(RD_PNTR_WR[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(Q[4]),
.I1(RD_PNTR_WR[4]),
.I2(Q[5]),
.I3(RD_PNTR_WR[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(Q[6]),
.I1(RD_PNTR_WR[6]),
.I2(Q[7]),
.I3(RD_PNTR_WR[7]),
.O(v1_reg[3]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(Q[8]),
.I1(RD_PNTR_WR[8]),
.I2(Q[9]),
.I3(RD_PNTR_WR[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(Q[10]),
.I1(RD_PNTR_WR[10]),
.I2(Q[11]),
.I3(RD_PNTR_WR[11]),
.O(v1_reg[5]));
endmodule
(* ORIG_REF_NAME = "compare" *)
module fifo_64in_out_compare_0
(comp2,
out,
RD_PNTR_WR);
output comp2;
input [11:0]out;
input [11:0]RD_PNTR_WR;
wire [11:0]RD_PNTR_WR;
wire comp2;
wire \n_0_gmux.gm[3].gms.ms ;
wire [11:0]out;
wire [5:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(out[0]),
.I1(RD_PNTR_WR[0]),
.I2(out[1]),
.I3(RD_PNTR_WR[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(out[2]),
.I1(RD_PNTR_WR[2]),
.I2(out[3]),
.I3(RD_PNTR_WR[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(out[4]),
.I1(RD_PNTR_WR[4]),
.I2(out[5]),
.I3(RD_PNTR_WR[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(out[6]),
.I1(RD_PNTR_WR[6]),
.I2(out[7]),
.I3(RD_PNTR_WR[7]),
.O(v1_reg[3]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp2,\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(out[8]),
.I1(RD_PNTR_WR[8]),
.I2(out[9]),
.I3(RD_PNTR_WR[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(out[10]),
.I1(RD_PNTR_WR[10]),
.I2(out[11]),
.I3(RD_PNTR_WR[11]),
.O(v1_reg[5]));
endmodule
(* ORIG_REF_NAME = "compare" *)
module fifo_64in_out_compare_1
(comp0,
WR_PNTR_RD,
I1);
output comp0;
input [11:0]WR_PNTR_RD;
input [11:0]I1;
wire [11:0]I1;
wire [11:0]WR_PNTR_RD;
wire comp0;
wire \n_0_gmux.gm[3].gms.ms ;
wire [5:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(WR_PNTR_RD[0]),
.I1(I1[0]),
.I2(WR_PNTR_RD[1]),
.I3(I1[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(WR_PNTR_RD[2]),
.I1(I1[2]),
.I2(WR_PNTR_RD[3]),
.I3(I1[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(WR_PNTR_RD[4]),
.I1(I1[4]),
.I2(WR_PNTR_RD[5]),
.I3(I1[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(WR_PNTR_RD[6]),
.I1(I1[6]),
.I2(WR_PNTR_RD[7]),
.I3(I1[7]),
.O(v1_reg[3]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(WR_PNTR_RD[8]),
.I1(I1[8]),
.I2(WR_PNTR_RD[9]),
.I3(I1[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(WR_PNTR_RD[10]),
.I1(I1[10]),
.I2(WR_PNTR_RD[11]),
.I3(I1[11]),
.O(v1_reg[5]));
endmodule
(* ORIG_REF_NAME = "compare" *)
module fifo_64in_out_compare_2
(comp1,
WR_PNTR_RD,
out);
output comp1;
input [11:0]WR_PNTR_RD;
input [11:0]out;
wire [11:0]WR_PNTR_RD;
wire comp1;
wire \n_0_gmux.gm[3].gms.ms ;
wire [11:0]out;
wire [5:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(WR_PNTR_RD[0]),
.I1(out[0]),
.I2(WR_PNTR_RD[1]),
.I3(out[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(WR_PNTR_RD[2]),
.I1(out[2]),
.I2(WR_PNTR_RD[3]),
.I3(out[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(WR_PNTR_RD[4]),
.I1(out[4]),
.I2(WR_PNTR_RD[5]),
.I3(out[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(WR_PNTR_RD[6]),
.I1(out[6]),
.I2(WR_PNTR_RD[7]),
.I3(out[7]),
.O(v1_reg[3]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(WR_PNTR_RD[8]),
.I1(out[8]),
.I2(WR_PNTR_RD[9]),
.I3(out[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(WR_PNTR_RD[10]),
.I1(out[10]),
.I2(WR_PNTR_RD[11]),
.I3(out[11]),
.O(v1_reg[5]));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module fifo_64in_out_fifo_generator_ramfifo
(empty,
dout,
valid,
full,
rd_data_count,
rd_en,
wr_en,
wr_clk,
rd_clk,
din,
rst);
output empty;
output [63:0]dout;
output valid;
output full;
output [11:0]rd_data_count;
input rd_en;
input wr_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
wire RD_RST;
wire RST;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire \n_0_gntv_or_sync_fifo.gcx.clkx ;
wire \n_16_gntv_or_sync_fifo.gcx.clkx ;
wire \n_17_gntv_or_sync_fifo.gcx.clkx ;
wire \n_18_gntv_or_sync_fifo.gcx.clkx ;
wire \n_19_gntv_or_sync_fifo.gcx.clkx ;
wire \n_1_gntv_or_sync_fifo.gcx.clkx ;
wire \n_1_gntv_or_sync_fifo.gl0.wr ;
wire \n_20_gntv_or_sync_fifo.gcx.clkx ;
wire \n_21_gntv_or_sync_fifo.gcx.clkx ;
wire \n_22_gntv_or_sync_fifo.gcx.clkx ;
wire \n_23_gntv_or_sync_fifo.gcx.clkx ;
wire \n_2_gntv_or_sync_fifo.gcx.clkx ;
wire \n_3_gntv_or_sync_fifo.gcx.clkx ;
wire [11:0]p_0_out;
wire p_18_out;
wire [11:0]p_1_out;
wire [11:0]p_20_out;
wire [11:0]p_9_out;
wire rd_clk;
wire [11:0]rd_data_count;
wire rd_en;
wire [1:0]rd_rst_i;
wire rst;
wire rst_d2;
wire rst_full_gen_i;
wire tmp_ram_rd_en;
wire valid;
wire wr_clk;
wire wr_en;
wire [0:0]wr_rst_i;
fifo_64in_out_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.I1(p_9_out),
.I2(wr_rst_i),
.I3(rd_rst_i[1]),
.O1({\n_16_gntv_or_sync_fifo.gcx.clkx ,\n_17_gntv_or_sync_fifo.gcx.clkx ,\n_18_gntv_or_sync_fifo.gcx.clkx ,\n_19_gntv_or_sync_fifo.gcx.clkx }),
.O2({\n_20_gntv_or_sync_fifo.gcx.clkx ,\n_21_gntv_or_sync_fifo.gcx.clkx ,\n_22_gntv_or_sync_fifo.gcx.clkx ,\n_23_gntv_or_sync_fifo.gcx.clkx }),
.Q(p_20_out),
.RD_PNTR_WR(p_0_out),
.S({\n_0_gntv_or_sync_fifo.gcx.clkx ,\n_1_gntv_or_sync_fifo.gcx.clkx ,\n_2_gntv_or_sync_fifo.gcx.clkx ,\n_3_gntv_or_sync_fifo.gcx.clkx }),
.WR_PNTR_RD(p_1_out),
.rd_clk(rd_clk),
.wr_clk(wr_clk));
fifo_64in_out_rd_logic \gntv_or_sync_fifo.gl0.rd
(.I1({\n_16_gntv_or_sync_fifo.gcx.clkx ,\n_17_gntv_or_sync_fifo.gcx.clkx ,\n_18_gntv_or_sync_fifo.gcx.clkx ,\n_19_gntv_or_sync_fifo.gcx.clkx }),
.O1(p_20_out),
.O2({\n_20_gntv_or_sync_fifo.gcx.clkx ,\n_21_gntv_or_sync_fifo.gcx.clkx ,\n_22_gntv_or_sync_fifo.gcx.clkx ,\n_23_gntv_or_sync_fifo.gcx.clkx }),
.Q(RD_RST),
.S({\n_0_gntv_or_sync_fifo.gcx.clkx ,\n_1_gntv_or_sync_fifo.gcx.clkx ,\n_2_gntv_or_sync_fifo.gcx.clkx ,\n_3_gntv_or_sync_fifo.gcx.clkx }),
.WR_PNTR_RD(p_1_out),
.empty(empty),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.valid(valid));
fifo_64in_out_wr_logic \gntv_or_sync_fifo.gl0.wr
(.O1(\n_1_gntv_or_sync_fifo.gl0.wr ),
.O2(p_9_out),
.Q(RST),
.RD_PNTR_WR(p_0_out),
.full(full),
.rst_d2(rst_d2),
.rst_full_gen_i(rst_full_gen_i),
.wr_clk(wr_clk),
.wr_en(wr_en));
fifo_64in_out_memory \gntv_or_sync_fifo.mem
(.I1(\n_1_gntv_or_sync_fifo.gl0.wr ),
.O1(p_20_out),
.O2(p_9_out),
.Q(rd_rst_i[0]),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
fifo_64in_out_reset_blk_ramfifo rstblk
(.O1({RST,wr_rst_i}),
.Q({RD_RST,rd_rst_i}),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.rst_d2(rst_d2),
.rst_full_gen_i(rst_full_gen_i),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module fifo_64in_out_fifo_generator_top
(empty,
dout,
valid,
full,
rd_data_count,
rd_en,
wr_en,
wr_clk,
rd_clk,
din,
rst);
output empty;
output [63:0]dout;
output valid;
output full;
output [11:0]rd_data_count;
input rd_en;
input wr_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_clk;
wire [11:0]rd_data_count;
wire rd_en;
wire rst;
wire valid;
wire wr_clk;
wire wr_en;
fifo_64in_out_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.valid(valid),
.wr_clk(wr_clk),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v12_0" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "12" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "64" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "64" *) (* C_ENABLE_RLOCS = "0" *)
(* C_FAMILY = "virtex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_INT_CLK = "0" *) (* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *)
(* C_HAS_RD_DATA_COUNT = "1" *) (* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "1" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *) (* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "4kx9" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "4093" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "4092" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "12" *) (* C_RD_DEPTH = "4096" *) (* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "12" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_POWER_SAVING_MODE = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_VALID_LOW = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "12" *)
(* C_WR_DEPTH = "4096" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "12" *)
(* C_WR_RESPONSE_LATENCY = "1" *) (* C_MSGON_VAL = "1" *) (* C_ENABLE_RST_SYNC = "1" *)
(* C_ERROR_INJECTION_TYPE = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_INTERFACE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *) (* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_SLAVE_CE = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_AXI_ID_WIDTH = "1" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_RUSER = "0" *) (* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TKEEP = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TSTRB_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_AXIS_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) (* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *) (* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_AXIS = "1" *)
(* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_AXIS = "0" *)
module fifo_64in_out_fifo_generator_v12_0__parameterized0
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [63:0]din;
input wr_en;
input rd_en;
input [11:0]prog_empty_thresh;
input [11:0]prog_empty_thresh_assert;
input [11:0]prog_empty_thresh_negate;
input [11:0]prog_full_thresh;
input [11:0]prog_full_thresh_assert;
input [11:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [63:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [11:0]data_count;
output [11:0]rd_data_count;
output [11:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [11:0]prog_empty_thresh;
wire [11:0]prog_empty_thresh_assert;
wire [11:0]prog_empty_thresh_negate;
wire [11:0]prog_full_thresh;
wire [11:0]prog_full_thresh_assert;
wire [11:0]prog_full_thresh_negate;
wire rd_clk;
wire [11:0]rd_data_count;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire valid;
wire wr_clk;
wire wr_en;
wire wr_rst;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[11] = \<const0> ;
assign data_count[10] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[11] = \<const0> ;
assign wr_data_count[10] = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
fifo_64in_out_fifo_generator_v12_0_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.valid(valid),
.wr_clk(wr_clk),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v12_0_synth" *)
module fifo_64in_out_fifo_generator_v12_0_synth
(empty,
dout,
valid,
full,
rd_data_count,
rd_en,
wr_en,
wr_clk,
rd_clk,
din,
rst);
output empty;
output [63:0]dout;
output valid;
output full;
output [11:0]rd_data_count;
input rd_en;
input wr_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_clk;
wire [11:0]rd_data_count;
wire rd_en;
wire rst;
wire valid;
wire wr_clk;
wire wr_en;
fifo_64in_out_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.valid(valid),
.wr_clk(wr_clk),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "memory" *)
module fifo_64in_out_memory
(dout,
wr_clk,
rd_clk,
I1,
tmp_ram_rd_en,
Q,
O2,
O1,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input I1;
input tmp_ram_rd_en;
input [0:0]Q;
input [11:0]O2;
input [11:0]O1;
input [63:0]din;
wire I1;
wire [11:0]O1;
wire [11:0]O2;
wire [0:0]Q;
wire [63:0]din;
wire [63:0]dout;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
fifo_64in_out_blk_mem_gen_v8_2__parameterized0 \gbm.gbmg.gbmga.ngecc.bmg
(.I1(I1),
.O1(O1),
.O2(O2),
.Q(Q),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module fifo_64in_out_rd_bin_cntr
(out,
O1,
E,
rd_clk,
Q);
output [11:0]out;
output [11:0]O1;
input [0:0]E;
input rd_clk;
input [0:0]Q;
wire [0:0]E;
wire [11:0]O1;
wire [0:0]Q;
wire \n_0_gc0.count[0]_i_2 ;
wire \n_0_gc0.count_reg[0]_i_1 ;
wire \n_0_gc0.count_reg[10]_i_1 ;
wire \n_0_gc0.count_reg[10]_i_2 ;
wire \n_0_gc0.count_reg[11]_i_1 ;
wire \n_0_gc0.count_reg[1]_i_1 ;
wire \n_0_gc0.count_reg[1]_i_2 ;
wire \n_0_gc0.count_reg[2]_i_1 ;
wire \n_0_gc0.count_reg[2]_i_2 ;
wire \n_0_gc0.count_reg[3]_i_1 ;
wire \n_0_gc0.count_reg[3]_i_2 ;
wire \n_0_gc0.count_reg[4]_i_1 ;
wire \n_0_gc0.count_reg[4]_i_2 ;
wire \n_0_gc0.count_reg[5]_i_1 ;
wire \n_0_gc0.count_reg[5]_i_2 ;
wire \n_0_gc0.count_reg[6]_i_1 ;
wire \n_0_gc0.count_reg[6]_i_2 ;
wire \n_0_gc0.count_reg[7]_i_1 ;
wire \n_0_gc0.count_reg[7]_i_2 ;
wire \n_0_gc0.count_reg[8]_i_1 ;
wire \n_0_gc0.count_reg[8]_i_2 ;
wire \n_0_gc0.count_reg[9]_i_1 ;
wire \n_0_gc0.count_reg[9]_i_2 ;
wire [11:0]out;
wire rd_clk;
wire [3:2]\NLW_gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_2
(.I0(out[0]),
.O(\n_0_gc0.count[0]_i_2 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[0]),
.Q(O1[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[10]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[10]),
.Q(O1[10]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[11]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[11]),
.Q(O1[11]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[1]),
.Q(O1[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[2]),
.Q(O1[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[3]),
.Q(O1[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[4]),
.Q(O1[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[5]),
.Q(O1[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[6]),
.Q(O1[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[7]),
.Q(O1[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[8]),
.Q(O1[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(out[9]),
.Q(O1[9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(\n_0_gc0.count_reg[0]_i_1 ),
.PRE(Q),
.Q(out[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[10]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[10]_i_1 ),
.Q(out[10]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[11]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[11]_i_1 ),
.Q(out[11]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[1]_i_1 ),
.Q(out[1]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gc0.count_reg[1]_i_2_CARRY4
(.CI(1'b0),
.CO({\n_0_gc0.count_reg[4]_i_2 ,\n_0_gc0.count_reg[3]_i_2 ,\n_0_gc0.count_reg[2]_i_2 ,\n_0_gc0.count_reg[1]_i_2 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\n_0_gc0.count_reg[3]_i_1 ,\n_0_gc0.count_reg[2]_i_1 ,\n_0_gc0.count_reg[1]_i_1 ,\n_0_gc0.count_reg[0]_i_1 }),
.S({out[3:1],\n_0_gc0.count[0]_i_2 }));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[2]_i_1 ),
.Q(out[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[3]_i_1 ),
.Q(out[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[4]_i_1 ),
.Q(out[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[5]_i_1 ),
.Q(out[5]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gc0.count_reg[5]_i_2_CARRY4
(.CI(\n_0_gc0.count_reg[4]_i_2 ),
.CO({\n_0_gc0.count_reg[8]_i_2 ,\n_0_gc0.count_reg[7]_i_2 ,\n_0_gc0.count_reg[6]_i_2 ,\n_0_gc0.count_reg[5]_i_2 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\n_0_gc0.count_reg[7]_i_1 ,\n_0_gc0.count_reg[6]_i_1 ,\n_0_gc0.count_reg[5]_i_1 ,\n_0_gc0.count_reg[4]_i_1 }),
.S(out[7:4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[6]_i_1 ),
.Q(out[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[7]_i_1 ),
.Q(out[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[8]_i_1 ),
.Q(out[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(\n_0_gc0.count_reg[9]_i_1 ),
.Q(out[9]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gc0.count_reg[9]_i_2_CARRY4
(.CI(\n_0_gc0.count_reg[8]_i_2 ),
.CO({\NLW_gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED [3:2],\n_0_gc0.count_reg[10]_i_2 ,\n_0_gc0.count_reg[9]_i_2 }),
.CYINIT(1'b0),
.DI({\NLW_gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}),
.O({\n_0_gc0.count_reg[11]_i_1 ,\n_0_gc0.count_reg[10]_i_1 ,\n_0_gc0.count_reg[9]_i_1 ,\n_0_gc0.count_reg[8]_i_1 }),
.S(out[11:8]));
endmodule
(* ORIG_REF_NAME = "rd_dc_as" *)
module fifo_64in_out_rd_dc_as
(rd_data_count,
rd_clk,
Q,
WR_PNTR_RD,
S,
I1,
O2);
output [11:0]rd_data_count;
input rd_clk;
input [0:0]Q;
input [10:0]WR_PNTR_RD;
input [3:0]S;
input [3:0]I1;
input [3:0]O2;
wire [3:0]I1;
wire [3:0]O2;
wire [0:0]Q;
wire [3:0]S;
wire [10:0]WR_PNTR_RD;
wire [11:0]minusOp;
wire \n_0_rd_dc_i_reg[3]_i_1 ;
wire \n_0_rd_dc_i_reg[7]_i_1 ;
wire \n_1_rd_dc_i_reg[11]_i_1 ;
wire \n_1_rd_dc_i_reg[3]_i_1 ;
wire \n_1_rd_dc_i_reg[7]_i_1 ;
wire \n_2_rd_dc_i_reg[11]_i_1 ;
wire \n_2_rd_dc_i_reg[3]_i_1 ;
wire \n_2_rd_dc_i_reg[7]_i_1 ;
wire \n_3_rd_dc_i_reg[11]_i_1 ;
wire \n_3_rd_dc_i_reg[3]_i_1 ;
wire \n_3_rd_dc_i_reg[7]_i_1 ;
wire rd_clk;
wire [11:0]rd_data_count;
wire [3:3]\NLW_rd_dc_i_reg[11]_i_1_CO_UNCONNECTED ;
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[0]),
.Q(rd_data_count[0]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[10]),
.Q(rd_data_count[10]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[11]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[11]),
.Q(rd_data_count[11]));
CARRY4 \rd_dc_i_reg[11]_i_1
(.CI(\n_0_rd_dc_i_reg[7]_i_1 ),
.CO({\NLW_rd_dc_i_reg[11]_i_1_CO_UNCONNECTED [3],\n_1_rd_dc_i_reg[11]_i_1 ,\n_2_rd_dc_i_reg[11]_i_1 ,\n_3_rd_dc_i_reg[11]_i_1 }),
.CYINIT(1'b0),
.DI({1'b0,WR_PNTR_RD[10:8]}),
.O(minusOp[11:8]),
.S(O2));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[1]),
.Q(rd_data_count[1]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[2]),
.Q(rd_data_count[2]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[3]),
.Q(rd_data_count[3]));
CARRY4 \rd_dc_i_reg[3]_i_1
(.CI(1'b0),
.CO({\n_0_rd_dc_i_reg[3]_i_1 ,\n_1_rd_dc_i_reg[3]_i_1 ,\n_2_rd_dc_i_reg[3]_i_1 ,\n_3_rd_dc_i_reg[3]_i_1 }),
.CYINIT(1'b1),
.DI(WR_PNTR_RD[3:0]),
.O(minusOp[3:0]),
.S(S));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[4]),
.Q(rd_data_count[4]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[5]),
.Q(rd_data_count[5]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[6]),
.Q(rd_data_count[6]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[7]),
.Q(rd_data_count[7]));
CARRY4 \rd_dc_i_reg[7]_i_1
(.CI(\n_0_rd_dc_i_reg[3]_i_1 ),
.CO({\n_0_rd_dc_i_reg[7]_i_1 ,\n_1_rd_dc_i_reg[7]_i_1 ,\n_2_rd_dc_i_reg[7]_i_1 ,\n_3_rd_dc_i_reg[7]_i_1 }),
.CYINIT(1'b0),
.DI(WR_PNTR_RD[7:4]),
.O(minusOp[7:4]),
.S(I1));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[8]),
.Q(rd_data_count[8]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[9]),
.Q(rd_data_count[9]));
endmodule
(* ORIG_REF_NAME = "rd_handshaking_flags" *)
module fifo_64in_out_rd_handshaking_flags
(valid,
I1,
rd_clk,
Q);
output valid;
input I1;
input rd_clk;
input [0:0]Q;
wire I1;
wire [0:0]Q;
wire rd_clk;
wire valid;
FDCE #(
.INIT(1'b0))
\gv.ram_valid_d1_reg
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(I1),
.Q(valid));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module fifo_64in_out_rd_logic
(empty,
p_18_out,
valid,
O1,
rd_data_count,
rd_clk,
Q,
rd_en,
WR_PNTR_RD,
S,
I1,
O2);
output empty;
output p_18_out;
output valid;
output [11:0]O1;
output [11:0]rd_data_count;
input rd_clk;
input [0:0]Q;
input rd_en;
input [11:0]WR_PNTR_RD;
input [3:0]S;
input [3:0]I1;
input [3:0]O2;
wire [3:0]I1;
wire [11:0]O1;
wire [3:0]O2;
wire [0:0]Q;
wire [3:0]S;
wire [11:0]WR_PNTR_RD;
wire empty;
wire \n_2_gras.rsts ;
wire \n_3_gras.rsts ;
wire p_18_out;
wire rd_clk;
wire [11:0]rd_data_count;
wire rd_en;
wire [11:0]rd_pntr_plus1;
wire valid;
fifo_64in_out_rd_dc_as \gras.grdc1.rdc
(.I1(I1),
.O2(O2),
.Q(Q),
.S(S),
.WR_PNTR_RD(WR_PNTR_RD[10:0]),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count));
fifo_64in_out_rd_status_flags_as \gras.rsts
(.E(\n_2_gras.rsts ),
.I1(O1),
.O1(\n_3_gras.rsts ),
.Q(Q),
.WR_PNTR_RD(WR_PNTR_RD),
.empty(empty),
.out(rd_pntr_plus1),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en));
fifo_64in_out_rd_handshaking_flags \grhf.rhf
(.I1(\n_3_gras.rsts ),
.Q(Q),
.rd_clk(rd_clk),
.valid(valid));
fifo_64in_out_rd_bin_cntr rpntr
(.E(\n_2_gras.rsts ),
.O1(O1),
.Q(Q),
.out(rd_pntr_plus1),
.rd_clk(rd_clk));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module fifo_64in_out_rd_status_flags_as
(empty,
p_18_out,
E,
O1,
rd_clk,
Q,
rd_en,
WR_PNTR_RD,
I1,
out);
output empty;
output p_18_out;
output [0:0]E;
output O1;
input rd_clk;
input [0:0]Q;
input rd_en;
input [11:0]WR_PNTR_RD;
input [11:0]I1;
input [11:0]out;
wire [0:0]E;
wire [11:0]I1;
wire O1;
wire [0:0]Q;
wire [11:0]WR_PNTR_RD;
wire comp0;
wire comp1;
wire empty;
wire n_0_ram_empty_i_i_1;
wire [11:0]out;
wire p_18_out;
wire rd_clk;
wire rd_en;
fifo_64in_out_compare_1 c0
(.I1(I1),
.WR_PNTR_RD(WR_PNTR_RD),
.comp0(comp0));
fifo_64in_out_compare_2 c1
(.WR_PNTR_RD(WR_PNTR_RD),
.comp1(comp1),
.out(out));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[11]_i_1
(.I0(rd_en),
.I1(p_18_out),
.O(E));
LUT2 #(
.INIT(4'h2))
\gv.ram_valid_d1_i_1
(.I0(rd_en),
.I1(empty),
.O(O1));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(n_0_ram_empty_i_i_1),
.PRE(Q),
.Q(p_18_out));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'hAEAA))
ram_empty_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(p_18_out),
.I3(comp1),
.O(n_0_ram_empty_i_i_1));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(n_0_ram_empty_i_i_1),
.PRE(Q),
.Q(empty));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module fifo_64in_out_reset_blk_ramfifo
(rst_d2,
rst_full_gen_i,
tmp_ram_rd_en,
Q,
O1,
wr_clk,
rst,
rd_clk,
p_18_out,
rd_en);
output rst_d2;
output rst_full_gen_i;
output tmp_ram_rd_en;
output [2:0]Q;
output [1:0]O1;
input wr_clk;
input rst;
input rd_clk;
input p_18_out;
input rd_en;
wire [1:0]O1;
wire [2:0]Q;
wire \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ;
wire \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire rd_rst_asreg;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
wire rst;
wire rst_d1;
wire rst_d2;
wire rst_d3;
wire rst_full_gen_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_rst_asreg;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(Q[0]),
.I1(p_18_out),
.I2(rd_en),
.O(tmp_ram_rd_en));
FDCE #(
.INIT(1'b0))
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg
(.C(wr_clk),
.CE(1'b1),
.CLR(rst),
.D(rst_d3),
.Q(rst_full_gen_i));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_d1));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst),
.Q(rst_d2));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst),
.Q(rst_d3));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg),
.Q(rd_rst_asreg_d1),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg_d1),
.Q(rd_rst_asreg_d2),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(rd_rst_asreg_d1),
.D(1'b0),
.PRE(rst),
.Q(rd_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d2),
.O(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ),
.Q(Q[0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ),
.Q(Q[1]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ),
.Q(Q[2]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg),
.Q(wr_rst_asreg_d1),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg_d1),
.Q(wr_rst_asreg_d2),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(wr_rst_asreg_d1),
.D(1'b0),
.PRE(rst),
.Q(wr_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d2),
.O(\n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ),
.Q(O1[0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ),
.Q(O1[1]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_64in_out_synchronizer_ff
(Q,
I1,
rd_clk,
I3);
output [11:0]Q;
input [11:0]I1;
input rd_clk;
input [0:0]I3;
wire [11:0]I1;
wire [0:0]I3;
wire [11:0]Q;
wire rd_clk;
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[0]),
.Q(Q[0]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[10]),
.Q(Q[10]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[11]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[11]),
.Q(Q[11]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[1]),
.Q(Q[1]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[2]),
.Q(Q[2]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[3]),
.Q(Q[3]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[4]),
.Q(Q[4]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[5]),
.Q(Q[5]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[6]),
.Q(Q[6]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[7]),
.Q(Q[7]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[8]),
.Q(Q[8]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_64in_out_synchronizer_ff_3
(Q,
I1,
wr_clk,
I2);
output [11:0]Q;
input [11:0]I1;
input wr_clk;
input [0:0]I2;
wire [11:0]I1;
wire [0:0]I2;
wire [11:0]Q;
wire wr_clk;
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[0]),
.Q(Q[0]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[10]),
.Q(Q[10]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[11]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[11]),
.Q(Q[11]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[1]),
.Q(Q[1]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[2]),
.Q(Q[2]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[3]),
.Q(Q[3]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[4]),
.Q(Q[4]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[5]),
.Q(Q[5]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[6]),
.Q(Q[6]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[7]),
.Q(Q[7]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[8]),
.Q(Q[8]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_64in_out_synchronizer_ff_4
(p_0_in,
D,
rd_clk,
I3);
output [11:0]p_0_in;
input [11:0]D;
input rd_clk;
input [0:0]I3;
wire [11:0]D;
wire [0:0]I3;
wire \n_0_Q_reg_reg[0] ;
wire \n_0_Q_reg_reg[10] ;
wire \n_0_Q_reg_reg[1] ;
wire \n_0_Q_reg_reg[2] ;
wire \n_0_Q_reg_reg[3] ;
wire \n_0_Q_reg_reg[4] ;
wire \n_0_Q_reg_reg[5] ;
wire \n_0_Q_reg_reg[6] ;
wire \n_0_Q_reg_reg[7] ;
wire \n_0_Q_reg_reg[8] ;
wire \n_0_Q_reg_reg[9] ;
wire [11:0]p_0_in;
wire rd_clk;
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[0]),
.Q(\n_0_Q_reg_reg[0] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[10]),
.Q(\n_0_Q_reg_reg[10] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[11]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[11]),
.Q(p_0_in[11]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[1]),
.Q(\n_0_Q_reg_reg[1] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[2]),
.Q(\n_0_Q_reg_reg[2] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[3]),
.Q(\n_0_Q_reg_reg[3] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[4]),
.Q(\n_0_Q_reg_reg[4] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[5]),
.Q(\n_0_Q_reg_reg[5] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[6]),
.Q(\n_0_Q_reg_reg[6] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[7]),
.Q(\n_0_Q_reg_reg[7] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[8]),
.Q(\n_0_Q_reg_reg[8] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[9]),
.Q(\n_0_Q_reg_reg[9] ));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[0]_i_1
(.I0(\n_0_Q_reg_reg[2] ),
.I1(\n_0_Q_reg_reg[1] ),
.I2(\n_0_Q_reg_reg[0] ),
.I3(p_0_in[3]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[10]_i_1
(.I0(\n_0_Q_reg_reg[10] ),
.I1(p_0_in[11]),
.O(p_0_in[10]));
LUT6 #(
.INIT(64'h6996966996696996))
\wr_pntr_bin[1]_i_1
(.I0(\n_0_Q_reg_reg[2] ),
.I1(\n_0_Q_reg_reg[1] ),
.I2(\n_0_Q_reg_reg[3] ),
.I3(\n_0_Q_reg_reg[5] ),
.I4(p_0_in[6]),
.I5(\n_0_Q_reg_reg[4] ),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[2]_i_1
(.I0(\n_0_Q_reg_reg[3] ),
.I1(\n_0_Q_reg_reg[5] ),
.I2(p_0_in[6]),
.I3(\n_0_Q_reg_reg[4] ),
.I4(\n_0_Q_reg_reg[2] ),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[3]_i_1
(.I0(\n_0_Q_reg_reg[4] ),
.I1(p_0_in[6]),
.I2(\n_0_Q_reg_reg[5] ),
.I3(\n_0_Q_reg_reg[3] ),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[4]_i_1
(.I0(\n_0_Q_reg_reg[5] ),
.I1(p_0_in[6]),
.I2(\n_0_Q_reg_reg[4] ),
.O(p_0_in[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[5]_i_1
(.I0(p_0_in[6]),
.I1(\n_0_Q_reg_reg[5] ),
.O(p_0_in[5]));
LUT6 #(
.INIT(64'h6996966996696996))
\wr_pntr_bin[6]_i_1
(.I0(\n_0_Q_reg_reg[7] ),
.I1(p_0_in[11]),
.I2(\n_0_Q_reg_reg[9] ),
.I3(\n_0_Q_reg_reg[10] ),
.I4(\n_0_Q_reg_reg[8] ),
.I5(\n_0_Q_reg_reg[6] ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[7]_i_1
(.I0(\n_0_Q_reg_reg[8] ),
.I1(\n_0_Q_reg_reg[10] ),
.I2(\n_0_Q_reg_reg[9] ),
.I3(p_0_in[11]),
.I4(\n_0_Q_reg_reg[7] ),
.O(p_0_in[7]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[8]_i_1
(.I0(p_0_in[11]),
.I1(\n_0_Q_reg_reg[9] ),
.I2(\n_0_Q_reg_reg[10] ),
.I3(\n_0_Q_reg_reg[8] ),
.O(p_0_in[8]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[9]_i_1
(.I0(\n_0_Q_reg_reg[10] ),
.I1(\n_0_Q_reg_reg[9] ),
.I2(p_0_in[11]),
.O(p_0_in[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_64in_out_synchronizer_ff_5
(Q,
O1,
D,
wr_clk,
I2);
output [0:0]Q;
output [10:0]O1;
input [11:0]D;
input wr_clk;
input [0:0]I2;
wire [11:0]D;
wire [0:0]I2;
wire [10:0]O1;
wire [0:0]Q;
wire \n_0_Q_reg_reg[0] ;
wire \n_0_Q_reg_reg[10] ;
wire \n_0_Q_reg_reg[1] ;
wire \n_0_Q_reg_reg[2] ;
wire \n_0_Q_reg_reg[3] ;
wire \n_0_Q_reg_reg[4] ;
wire \n_0_Q_reg_reg[5] ;
wire \n_0_Q_reg_reg[6] ;
wire \n_0_Q_reg_reg[7] ;
wire \n_0_Q_reg_reg[8] ;
wire \n_0_Q_reg_reg[9] ;
wire wr_clk;
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[0]),
.Q(\n_0_Q_reg_reg[0] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[10]),
.Q(\n_0_Q_reg_reg[10] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[11]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[11]),
.Q(Q));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[1]),
.Q(\n_0_Q_reg_reg[1] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[2]),
.Q(\n_0_Q_reg_reg[2] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[3]),
.Q(\n_0_Q_reg_reg[3] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[4]),
.Q(\n_0_Q_reg_reg[4] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[5]),
.Q(\n_0_Q_reg_reg[5] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[6]),
.Q(\n_0_Q_reg_reg[6] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[7]),
.Q(\n_0_Q_reg_reg[7] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[8]),
.Q(\n_0_Q_reg_reg[8] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[9]),
.Q(\n_0_Q_reg_reg[9] ));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[0]_i_1
(.I0(\n_0_Q_reg_reg[2] ),
.I1(\n_0_Q_reg_reg[1] ),
.I2(\n_0_Q_reg_reg[0] ),
.I3(O1[3]),
.O(O1[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[10]_i_1
(.I0(\n_0_Q_reg_reg[10] ),
.I1(Q),
.O(O1[10]));
LUT6 #(
.INIT(64'h6996966996696996))
\rd_pntr_bin[1]_i_1
(.I0(\n_0_Q_reg_reg[2] ),
.I1(\n_0_Q_reg_reg[1] ),
.I2(\n_0_Q_reg_reg[3] ),
.I3(\n_0_Q_reg_reg[5] ),
.I4(O1[6]),
.I5(\n_0_Q_reg_reg[4] ),
.O(O1[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[2]_i_1
(.I0(\n_0_Q_reg_reg[3] ),
.I1(\n_0_Q_reg_reg[5] ),
.I2(O1[6]),
.I3(\n_0_Q_reg_reg[4] ),
.I4(\n_0_Q_reg_reg[2] ),
.O(O1[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[3]_i_1
(.I0(\n_0_Q_reg_reg[4] ),
.I1(O1[6]),
.I2(\n_0_Q_reg_reg[5] ),
.I3(\n_0_Q_reg_reg[3] ),
.O(O1[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[4]_i_1
(.I0(\n_0_Q_reg_reg[5] ),
.I1(O1[6]),
.I2(\n_0_Q_reg_reg[4] ),
.O(O1[4]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[5]_i_1
(.I0(O1[6]),
.I1(\n_0_Q_reg_reg[5] ),
.O(O1[5]));
LUT6 #(
.INIT(64'h6996966996696996))
\rd_pntr_bin[6]_i_1
(.I0(\n_0_Q_reg_reg[7] ),
.I1(Q),
.I2(\n_0_Q_reg_reg[9] ),
.I3(\n_0_Q_reg_reg[10] ),
.I4(\n_0_Q_reg_reg[8] ),
.I5(\n_0_Q_reg_reg[6] ),
.O(O1[6]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[7]_i_1
(.I0(\n_0_Q_reg_reg[8] ),
.I1(\n_0_Q_reg_reg[10] ),
.I2(\n_0_Q_reg_reg[9] ),
.I3(Q),
.I4(\n_0_Q_reg_reg[7] ),
.O(O1[7]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[8]_i_1
(.I0(Q),
.I1(\n_0_Q_reg_reg[9] ),
.I2(\n_0_Q_reg_reg[10] ),
.I3(\n_0_Q_reg_reg[8] ),
.O(O1[8]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[9]_i_1
(.I0(\n_0_Q_reg_reg[10] ),
.I1(\n_0_Q_reg_reg[9] ),
.I2(Q),
.O(O1[9]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module fifo_64in_out_wr_bin_cntr
(out,
Q,
O2,
sel,
wr_clk,
I1);
output [11:0]out;
output [11:0]Q;
output [11:0]O2;
input sel;
input wr_clk;
input [0:0]I1;
wire [0:0]I1;
wire [11:0]O2;
wire [11:0]Q;
wire \n_0_gic0.gc0.count[0]_i_2 ;
wire \n_0_gic0.gc0.count_reg[0]_i_1 ;
wire \n_0_gic0.gc0.count_reg[10]_i_1 ;
wire \n_0_gic0.gc0.count_reg[10]_i_2 ;
wire \n_0_gic0.gc0.count_reg[11]_i_1 ;
wire \n_0_gic0.gc0.count_reg[1]_i_1 ;
wire \n_0_gic0.gc0.count_reg[1]_i_2 ;
wire \n_0_gic0.gc0.count_reg[2]_i_1 ;
wire \n_0_gic0.gc0.count_reg[2]_i_2 ;
wire \n_0_gic0.gc0.count_reg[3]_i_1 ;
wire \n_0_gic0.gc0.count_reg[3]_i_2 ;
wire \n_0_gic0.gc0.count_reg[4]_i_1 ;
wire \n_0_gic0.gc0.count_reg[4]_i_2 ;
wire \n_0_gic0.gc0.count_reg[5]_i_1 ;
wire \n_0_gic0.gc0.count_reg[5]_i_2 ;
wire \n_0_gic0.gc0.count_reg[6]_i_1 ;
wire \n_0_gic0.gc0.count_reg[6]_i_2 ;
wire \n_0_gic0.gc0.count_reg[7]_i_1 ;
wire \n_0_gic0.gc0.count_reg[7]_i_2 ;
wire \n_0_gic0.gc0.count_reg[8]_i_1 ;
wire \n_0_gic0.gc0.count_reg[8]_i_2 ;
wire \n_0_gic0.gc0.count_reg[9]_i_1 ;
wire \n_0_gic0.gc0.count_reg[9]_i_2 ;
wire [11:0]out;
wire sel;
wire wr_clk;
wire [3:2]\NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_2
(.I0(out[0]),
.O(\n_0_gic0.gc0.count[0]_i_2 ));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(sel),
.D(out[0]),
.PRE(I1),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[10]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[11]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[6]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[7]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[8]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[9]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[9]),
.Q(Q[9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[0]),
.Q(O2[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[10]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[10]),
.Q(O2[10]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[11]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[11]),
.Q(O2[11]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[1]),
.Q(O2[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[2]),
.Q(O2[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[3]),
.Q(O2[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[4]),
.Q(O2[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[5]),
.Q(O2[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[6]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[6]),
.Q(O2[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[7]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[7]),
.Q(O2[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[8]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[8]),
.Q(O2[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[9]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[9]),
.Q(O2[9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[0]_i_1 ),
.Q(out[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[10]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[10]_i_1 ),
.Q(out[10]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[11]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[11]_i_1 ),
.Q(out[11]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(sel),
.D(\n_0_gic0.gc0.count_reg[1]_i_1 ),
.PRE(I1),
.Q(out[1]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gic0.gc0.count_reg[1]_i_2_CARRY4
(.CI(1'b0),
.CO({\n_0_gic0.gc0.count_reg[4]_i_2 ,\n_0_gic0.gc0.count_reg[3]_i_2 ,\n_0_gic0.gc0.count_reg[2]_i_2 ,\n_0_gic0.gc0.count_reg[1]_i_2 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\n_0_gic0.gc0.count_reg[3]_i_1 ,\n_0_gic0.gc0.count_reg[2]_i_1 ,\n_0_gic0.gc0.count_reg[1]_i_1 ,\n_0_gic0.gc0.count_reg[0]_i_1 }),
.S({out[3:1],\n_0_gic0.gc0.count[0]_i_2 }));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[2]_i_1 ),
.Q(out[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[3]_i_1 ),
.Q(out[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[4]_i_1 ),
.Q(out[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[5]_i_1 ),
.Q(out[5]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gic0.gc0.count_reg[5]_i_2_CARRY4
(.CI(\n_0_gic0.gc0.count_reg[4]_i_2 ),
.CO({\n_0_gic0.gc0.count_reg[8]_i_2 ,\n_0_gic0.gc0.count_reg[7]_i_2 ,\n_0_gic0.gc0.count_reg[6]_i_2 ,\n_0_gic0.gc0.count_reg[5]_i_2 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\n_0_gic0.gc0.count_reg[7]_i_1 ,\n_0_gic0.gc0.count_reg[6]_i_1 ,\n_0_gic0.gc0.count_reg[5]_i_1 ,\n_0_gic0.gc0.count_reg[4]_i_1 }),
.S(out[7:4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[6]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[6]_i_1 ),
.Q(out[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[7]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[7]_i_1 ),
.Q(out[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[8]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[8]_i_1 ),
.Q(out[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[9]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[9]_i_1 ),
.Q(out[9]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gic0.gc0.count_reg[9]_i_2_CARRY4
(.CI(\n_0_gic0.gc0.count_reg[8]_i_2 ),
.CO({\NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED [3:2],\n_0_gic0.gc0.count_reg[10]_i_2 ,\n_0_gic0.gc0.count_reg[9]_i_2 }),
.CYINIT(1'b0),
.DI({\NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}),
.O({\n_0_gic0.gc0.count_reg[11]_i_1 ,\n_0_gic0.gc0.count_reg[10]_i_1 ,\n_0_gic0.gc0.count_reg[9]_i_1 ,\n_0_gic0.gc0.count_reg[8]_i_1 }),
.S(out[11:8]));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module fifo_64in_out_wr_logic
(full,
O1,
O2,
wr_clk,
rst_d2,
wr_en,
Q,
RD_PNTR_WR,
rst_full_gen_i);
output full;
output O1;
output [11:0]O2;
input wr_clk;
input rst_d2;
input wr_en;
input [0:0]Q;
input [11:0]RD_PNTR_WR;
input rst_full_gen_i;
wire O1;
wire [11:0]O2;
wire [0:0]Q;
wire [11:0]RD_PNTR_WR;
wire full;
wire [11:0]p_8_out;
wire rst_d2;
wire rst_full_gen_i;
wire wr_clk;
wire wr_en;
wire [11:0]wr_pntr_plus2;
fifo_64in_out_wr_status_flags_as \gwas.wsts
(.Q(p_8_out),
.RD_PNTR_WR(RD_PNTR_WR),
.full(full),
.out(wr_pntr_plus2),
.rst_d2(rst_d2),
.rst_full_gen_i(rst_full_gen_i),
.sel(O1),
.wr_clk(wr_clk),
.wr_en(wr_en));
fifo_64in_out_wr_bin_cntr wpntr
(.I1(Q),
.O2(O2),
.Q(p_8_out),
.out(wr_pntr_plus2),
.sel(O1),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module fifo_64in_out_wr_status_flags_as
(full,
sel,
wr_clk,
rst_d2,
wr_en,
Q,
RD_PNTR_WR,
out,
rst_full_gen_i);
output full;
output sel;
input wr_clk;
input rst_d2;
input wr_en;
input [11:0]Q;
input [11:0]RD_PNTR_WR;
input [11:0]out;
input rst_full_gen_i;
wire [11:0]Q;
wire [11:0]RD_PNTR_WR;
wire comp1;
wire comp2;
wire full;
wire [11:0]out;
wire p_0_out;
wire ram_full_i;
wire rst_d2;
wire rst_full_gen_i;
wire sel;
wire wr_clk;
wire wr_en;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(p_0_out),
.O(sel));
fifo_64in_out_compare c1
(.Q(Q),
.RD_PNTR_WR(RD_PNTR_WR),
.comp1(comp1));
fifo_64in_out_compare_0 c2
(.RD_PNTR_WR(RD_PNTR_WR),
.comp2(comp2),
.out(out));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_d2),
.Q(p_0_out));
LUT5 #(
.INIT(32'h55550400))
ram_full_i_i_1
(.I0(rst_full_gen_i),
.I1(comp2),
.I2(p_0_out),
.I3(wr_en),
.I4(comp1),
.O(ram_full_i));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_d2),
.Q(full));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:22:20 06/28/2012
// Design Name:
// Module Name: rgb2hsv
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rgb2hsv(
clk,
clk_en,
rst,
RGB,
//xxx,
HSV
);
input clk, rst;
input[31:0] RGB ;//xxx;
output[31:0] HSV;
input clk_en ;
// h ranges from (0, 360] degrees
// s and v ranges from [0,255] hya bet range mn 0-1 bas for calculation han5aleha from 0-255
// h [31:24] , s [23:16], v[15:8]
reg[31:0] HSV ;
reg[7:0] v_delay_final[2:0]; // Delays v so that h, s, v data lines up correctly
reg[19:0] div ;
wire[7:0] diff;
reg[31:0] H_old ;
reg signed [9:0] h_int;//ba7ot feha el value mtzabtah bel shifts bta3tha 3ala 7asb el hue_select value
reg[15:0] sat_dividend, sat_divisor;
reg[15:0] hue_dividend, hue_divisor;
//wire[15:0] sat_remainder, hue_remainder;
wire[15:0] sat_quotient, hue_quotient;
reg[2:0] hue_select; // Used to correctly modify the output of the hue divider
reg[2:0] hue_select_delay; // Accounts for divider delay
wire[7:0] max1 ;
wire[7:0] max;
wire[7:0] min1 ;
wire[7:0] min ;
assign diff = max - min;
assign max1 = (RGB[15:8] > RGB[23:16]) ? RGB[15:8] : RGB[23:16];
assign max = (max1 > RGB[31:24]) ? max1 : RGB[31:24];
assign min1 = (RGB[15:8] < RGB[23:16]) ? RGB[15:8] : RGB[23:16];
assign min = (min1 < RGB[31:24]) ? min1 : RGB[31:24];
always @ (posedge clk )
begin
if(rst == 1'b1)
begin
HSV<=0;
end
else if(clk_en == 1'b1)
begin
HSV[15:8] = max ;
case (HSV[15:8])
8'd0 : div=20'd0;
8'd1 : div=20'd1044480;
8'd2 : div=20'd522240;
8'd3 : div=20'd348160;
8'd4 : div=20'd261120;
8'd5 : div=20'd208896;
8'd6 : div=20'd174080;
8'd7 : div=20'd149211;
8'd8 : div=20'd130560;
8'd9 : div=20'd116053;
8'd10 : div=20'd104448;
8'd11 : div=20'd94953;
8'd12 : div=20'd87040;
8'd13 : div=20'd80345;
8'd14 : div=20'd74606;
8'd15 : div=20'd69632;
8'd16 : div=20'd65280;
8'd17 : div=20'd61440;
8'd18 : div=20'd58027;
8'd19 : div=20'd54973;
8'd20 : div=20'd52224;
8'd21 : div=20'd49737;
8'd22 : div=20'd47476;
8'd23 : div=20'd45412;
8'd24 : div=20'd43520;
8'd25 : div=20'd41779;
8'd26 : div=20'd40172;
8'd27 : div=20'd38684;
8'd28 : div=20'd37303;
8'd29 : div=20'd36017;
8'd30 : div=20'd34816;
8'd31 : div=20'd33693;
8'd32 : div=20'd32640;
8'd33 : div=20'd31651;
8'd34 : div=20'd30720;
8'd35 : div=20'd29842;
8'd36 : div=20'd29013;
8'd37 : div=20'd28229;
8'd38 : div=20'd27486;
8'd39 : div=20'd26782;
8'd40 : div=20'd26112;
8'd41 : div=20'd25475;
8'd42 : div=20'd24869;
8'd43 : div=20'd24290;
8'd44 : div=20'd23738;
8'd45 : div=20'd23211;
8'd46 : div=20'd22706;
8'd47 : div=20'd22223;
8'd48 : div=20'd21760;
8'd49 : div=20'd21316;
8'd50 : div=20'd20890;
8'd51 : div=20'd20480;
8'd52 : div=20'd20086;
8'd53 : div=20'd19707;
8'd54 : div=20'd19342;
8'd55 : div=20'd18991;
8'd56 : div=20'd18651;
8'd57 : div=20'd18324;
8'd58 : div=20'd18008;
8'd59 : div=20'd17703;
8'd60 : div=20'd17408;
8'd61 : div=20'd17123;
8'd62 : div=20'd16846;
8'd63 : div=20'd16579;
8'd64 : div=20'd16320;
8'd65 : div=20'd16069;
8'd66 : div=20'd15825;
8'd67 : div=20'd15589;
8'd68 : div=20'd15360;
8'd69 : div=20'd15137;
8'd70 : div=20'd14921;
8'd71 : div=20'd14711;
8'd72 : div=20'd14507;
8'd73 : div=20'd14308;
8'd74 : div=20'd14115;
8'd75 : div=20'd13926;
8'd76 : div=20'd13743;
8'd77 : div=20'd13565;
8'd78 : div=20'd13391;
8'd79 : div=20'd13221;
8'd80 : div=20'd13056;
8'd81 : div=20'd12895;
8'd82 : div=20'd12738;
8'd83 : div=20'd12584;
8'd84 : div=20'd12434;
8'd85 : div=20'd12288;
8'd86 : div=20'd12145;
8'd87 : div=20'd12006;
8'd88 : div=20'd11869;
8'd89 : div=20'd11736;
8'd90 : div=20'd11605;
8'd91 : div=20'd11478;
8'd92 : div=20'd11353;
8'd93 : div=20'd11231;
8'd94 : div=20'd11111;
8'd95 : div=20'd10995;
8'd96 : div=20'd10880;
8'd97 : div=20'd10768;
8'd98 : div=20'd10658;
8'd99 : div=20'd10550;
8'd100 : div=20'd10445;
8'd101 : div=20'd10341;
8'd102 : div=20'd10240;
8'd103 : div=20'd10141;
8'd104 : div=20'd10043;
8'd105 : div=20'd9947;
8'd106 : div=20'd9854;
8'd107 : div=20'd9761;
8'd108 : div=20'd9671;
8'd109 : div=20'd9582;
8'd110 : div=20'd9495;
8'd111 : div=20'd9410;
8'd112 : div=20'd9326;
8'd113 : div=20'd9243;
8'd114 : div=20'd9162;
8'd115 : div=20'd9082;
8'd116 : div=20'd9004;
8'd117 : div=20'd8927;
8'd118 : div=20'd8852;
8'd119 : div=20'd8777;
8'd120 : div=20'd8704;
8'd121 : div=20'd8632;
8'd122 : div=20'd8561;
8'd123 : div=20'd8492;
8'd124 : div=20'd8423;
8'd125 : div=20'd8356;
8'd126 : div=20'd8290;
8'd127 : div=20'd8224;
8'd128 : div=20'd8160;
8'd129 : div=20'd8097;
8'd130 : div=20'd8034;
8'd131 : div=20'd7973;
8'd132 : div=20'd7913;
8'd133 : div=20'd7853;
8'd134 : div=20'd7795;
8'd135 : div=20'd7737;
8'd136 : div=20'd7680;
8'd137 : div=20'd7624;
8'd138 : div=20'd7569;
8'd139 : div=20'd7514;
8'd140 : div=20'd7461;
8'd141 : div=20'd7408;
8'd142 : div=20'd7355;
8'd143 : div=20'd7304;
8'd144 : div=20'd7253;
8'd145 : div=20'd7203;
8'd146 : div=20'd7154;
8'd147 : div=20'd7105;
8'd148 : div=20'd7057;
8'd149 : div=20'd7010;
8'd150 : div=20'd6963;
8'd151 : div=20'd6917;
8'd152 : div=20'd6872;
8'd153 : div=20'd6827;
8'd154 : div=20'd6782;
8'd155 : div=20'd6739;
8'd156 : div=20'd6695;
8'd157 : div=20'd6653;
8'd158 : div=20'd6611;
8'd159 : div=20'd6569;
8'd160 : div=20'd6528;
8'd161 : div=20'd6487;
8'd162 : div=20'd6447;
8'd163 : div=20'd6408;
8'd164 : div=20'd6369;
8'd165 : div=20'd6330;
8'd166 : div=20'd6292;
8'd167 : div=20'd6254;
8'd168 : div=20'd6217;
8'd169 : div=20'd6180;
8'd170 : div=20'd6144;
8'd171 : div=20'd6108;
8'd172 : div=20'd6073;
8'd173 : div=20'd6037;
8'd174 : div=20'd6003;
8'd175 : div=20'd5968;
8'd176 : div=20'd5935;
8'd177 : div=20'd5901;
8'd178 : div=20'd5868;
8'd179 : div=20'd5835;
8'd180 : div=20'd5803;
8'd181 : div=20'd5771;
8'd182 : div=20'd5739;
8'd183 : div=20'd5708;
8'd184 : div=20'd5677;
8'd185 : div=20'd5646;
8'd186 : div=20'd5615;
8'd187 : div=20'd5585;
8'd188 : div=20'd5556;
8'd189 : div=20'd5526;
8'd190 : div=20'd5497;
8'd191 : div=20'd5468;
8'd192 : div=20'd5440;
8'd193 : div=20'd5412;
8'd194 : div=20'd5384;
8'd195 : div=20'd5356;
8'd196 : div=20'd5329;
8'd197 : div=20'd5302;
8'd198 : div=20'd5275;
8'd199 : div=20'd5249;
8'd200 : div=20'd5222;
8'd201 : div=20'd5196;
8'd202 : div=20'd5171;
8'd203 : div=20'd5145;
8'd204 : div=20'd5120;
8'd205 : div=20'd5095;
8'd206 : div=20'd5070;
8'd207 : div=20'd5046;
8'd208 : div=20'd5022;
8'd209 : div=20'd4998;
8'd210 : div=20'd4974;
8'd211 : div=20'd4950;
8'd212 : div=20'd4927;
8'd213 : div=20'd4904;
8'd214 : div=20'd4881;
8'd215 : div=20'd4858;
8'd216 : div=20'd4836;
8'd217 : div=20'd4813;
8'd218 : div=20'd4791;
8'd219 : div=20'd4769;
8'd220 : div=20'd4748;
8'd221 : div=20'd4726;
8'd222 : div=20'd4705;
8'd223 : div=20'd4684;
8'd224 : div=20'd4663;
8'd225 : div=20'd4642;
8'd226 : div=20'd4622;
8'd227 : div=20'd4601;
8'd228 : div=20'd4581;
8'd229 : div=20'd4561;
8'd230 : div=20'd4541;
8'd231 : div=20'd4522;
8'd232 : div=20'd4502;
8'd233 : div=20'd4483;
8'd234 : div=20'd4464;
8'd235 : div=20'd4445;
8'd236 : div=20'd4426;
8'd237 : div=20'd4407;
8'd238 : div=20'd4389;
8'd239 : div=20'd4370;
8'd240 : div=20'd4352;
8'd241 : div=20'd4334;
8'd242 : div=20'd4316;
8'd243 : div=20'd4298;
8'd244 : div=20'd4281;
8'd245 : div=20'd4263;
8'd246 : div=20'd4246;
8'd247 : div=20'd4229;
8'd248 : div=20'd4212;
8'd249 : div=20'd4195;
8'd250 : div=20'd4178;
8'd251 : div=20'd4161;
8'd252 : div=20'd4145;
8'd253 : div=20'd4128;
8'd254 : div=20'd4112;
8'd255 : div=20'd4096;
endcase
HSV[23:16] = ((diff * div)>>12) ;
case (diff)
8'd0 : H_old=32'd0;
8'd1 : H_old=32'd1044480;
8'd2 : H_old=32'd522240;
8'd3 : H_old=32'd348160;
8'd4 : H_old=32'd261120;
8'd5 : H_old=32'd208896;
8'd6 : H_old=32'd174080;
8'd7 : H_old=32'd149211;
8'd8 : H_old=32'd130560;
8'd9 : H_old=32'd116053;
8'd10 : H_old=32'd104448;
8'd11 : H_old=32'd94953;
8'd12 : H_old=32'd87040;
8'd13 : H_old=32'd80345;
8'd14 : H_old=32'd74606;
8'd15 : H_old=32'd69632;
8'd16 : H_old=32'd65280;
8'd17 : H_old=32'd61440;
8'd18 : H_old=32'd58027;
8'd19 : H_old=32'd54973;
8'd20 : H_old=32'd52224;
8'd21 : H_old=32'd49737;
8'd22 : H_old=32'd47476;
8'd23 : H_old=32'd45412;
8'd24 : H_old=32'd43520;
8'd25 : H_old=32'd41779;
8'd26 : H_old=32'd40172;
8'd27 : H_old=32'd38684;
8'd28 : H_old=32'd37303;
8'd29 : H_old=32'd36017;
8'd30 : H_old=32'd34816;
8'd31 : H_old=32'd33693;
8'd32 : H_old=32'd32640;
8'd33 : H_old=32'd31651;
8'd34 : H_old=32'd30720;
8'd35 : H_old=32'd29842;
8'd36 : H_old=32'd29013;
8'd37 : H_old=32'd28229;
8'd38 : H_old=32'd27486;
8'd39 : H_old=32'd26782;
8'd40 : H_old=32'd26112;
8'd41 : H_old=32'd25475;
8'd42 : H_old=32'd24869;
8'd43 : H_old=32'd24290;
8'd44 : H_old=32'd23738;
8'd45 : H_old=32'd23211;
8'd46 : H_old=32'd22706;
8'd47 : H_old=32'd22223;
8'd48 : H_old=32'd21760;
8'd49 : H_old=32'd21316;
8'd50 : H_old=32'd20890;
8'd51 : H_old=32'd20480;
8'd52 : H_old=32'd20086;
8'd53 : H_old=32'd19707;
8'd54 : H_old=32'd19342;
8'd55 : H_old=32'd18991;
8'd56 : H_old=32'd18651;
8'd57 : H_old=32'd18324;
8'd58 : H_old=32'd18008;
8'd59 : H_old=32'd17703;
8'd60 : H_old=32'd17408;
8'd61 : H_old=32'd17123;
8'd62 : H_old=32'd16846;
8'd63 : H_old=32'd16579;
8'd64 : H_old=32'd16320;
8'd65 : H_old=32'd16069;
8'd66 : H_old=32'd15825;
8'd67 : H_old=32'd15589;
8'd68 : H_old=32'd15360;
8'd69 : H_old=32'd15137;
8'd70 : H_old=32'd14921;
8'd71 : H_old=32'd14711;
8'd72 : H_old=32'd14507;
8'd73 : H_old=32'd14308;
8'd74 : H_old=32'd14115;
8'd75 : H_old=32'd13926;
8'd76 : H_old=32'd13743;
8'd77 : H_old=32'd13565;
8'd78 : H_old=32'd13391;
8'd79 : H_old=32'd13221;
8'd80 : H_old=32'd13056;
8'd81 : H_old=32'd12895;
8'd82 : H_old=32'd12738;
8'd83 : H_old=32'd12584;
8'd84 : H_old=32'd12434;
8'd85 : H_old=32'd12288;
8'd86 : H_old=32'd12145;
8'd87 : H_old=32'd12006;
8'd88 : H_old=32'd11869;
8'd89 : H_old=32'd11736;
8'd90 : H_old=32'd11605;
8'd91 : H_old=32'd11478;
8'd92 : H_old=32'd11353;
8'd93 : H_old=32'd11231;
8'd94 : H_old=32'd11111;
8'd95 : H_old=32'd10995;
8'd96 : H_old=32'd10880;
8'd97 : H_old=32'd10768;
8'd98 : H_old=32'd10658;
8'd99 : H_old=32'd10550;
8'd100 : H_old=32'd10445;
8'd101 : H_old=32'd10341;
8'd102 : H_old=32'd10240;
8'd103 : H_old=32'd10141;
8'd104 : H_old=32'd10043;
8'd105 : H_old=32'd9947;
8'd106 : H_old=32'd9854;
8'd107 : H_old=32'd9761;
8'd108 : H_old=32'd9671;
8'd109 : H_old=32'd9582;
8'd110 : H_old=32'd9495;
8'd111 : H_old=32'd9410;
8'd112 : H_old=32'd9326;
8'd113 : H_old=32'd9243;
8'd114 : H_old=32'd9162;
8'd115 : H_old=32'd9082;
8'd116 : H_old=32'd9004;
8'd117 : H_old=32'd8927;
8'd118 : H_old=32'd8852;
8'd119 : H_old=32'd8777;
8'd120 : H_old=32'd8704;
8'd121 : H_old=32'd8632;
8'd122 : H_old=32'd8561;
8'd123 : H_old=32'd8492;
8'd124 : H_old=32'd8423;
8'd125 : H_old=32'd8356;
8'd126 : H_old=32'd8290;
8'd127 : H_old=32'd8224;
8'd128 : H_old=32'd8160;
8'd129 : H_old=32'd8097;
8'd130 : H_old=32'd8034;
8'd131 : H_old=32'd7973;
8'd132 : H_old=32'd7913;
8'd133 : H_old=32'd7853;
8'd134 : H_old=32'd7795;
8'd135 : H_old=32'd7737;
8'd136 : H_old=32'd7680;
8'd137 : H_old=32'd7624;
8'd138 : H_old=32'd7569;
8'd139 : H_old=32'd7514;
8'd140 : H_old=32'd7461;
8'd141 : H_old=32'd7408;
8'd142 : H_old=32'd7355;
8'd143 : H_old=32'd7304;
8'd144 : H_old=32'd7253;
8'd145 : H_old=32'd7203;
8'd146 : H_old=32'd7154;
8'd147 : H_old=32'd7105;
8'd148 : H_old=32'd7057;
8'd149 : H_old=32'd7010;
8'd150 : H_old=32'd6963;
8'd151 : H_old=32'd6917;
8'd152 : H_old=32'd6872;
8'd153 : H_old=32'd6827;
8'd154 : H_old=32'd6782;
8'd155 : H_old=32'd6739;
8'd156 : H_old=32'd6695;
8'd157 : H_old=32'd6653;
8'd158 : H_old=32'd6611;
8'd159 : H_old=32'd6569;
8'd160 : H_old=32'd6528;
8'd161 : H_old=32'd6487;
8'd162 : H_old=32'd6447;
8'd163 : H_old=32'd6408;
8'd164 : H_old=32'd6369;
8'd165 : H_old=32'd6330;
8'd166 : H_old=32'd6292;
8'd167 : H_old=32'd6254;
8'd168 : H_old=32'd6217;
8'd169 : H_old=32'd6180;
8'd170 : H_old=32'd6144;
8'd171 : H_old=32'd6108;
8'd172 : H_old=32'd6073;
8'd173 : H_old=32'd6037;
8'd174 : H_old=32'd6003;
8'd175 : H_old=32'd5968;
8'd176 : H_old=32'd5935;
8'd177 : H_old=32'd5901;
8'd178 : H_old=32'd5868;
8'd179 : H_old=32'd5835;
8'd180 : H_old=32'd5803;
8'd181 : H_old=32'd5771;
8'd182 : H_old=32'd5739;
8'd183 : H_old=32'd5708;
8'd184 : H_old=32'd5677;
8'd185 : H_old=32'd5646;
8'd186 : H_old=32'd5615;
8'd187 : H_old=32'd5585;
8'd188 : H_old=32'd5556;
8'd189 : H_old=32'd5526;
8'd190 : H_old=32'd5497;
8'd191 : H_old=32'd5468;
8'd192 : H_old=32'd5440;
8'd193 : H_old=32'd5412;
8'd194 : H_old=32'd5384;
8'd195 : H_old=32'd5356;
8'd196 : H_old=32'd5329;
8'd197 : H_old=32'd5302;
8'd198 : H_old=32'd5275;
8'd199 : H_old=32'd5249;
8'd200 : H_old=32'd5222;
8'd201 : H_old=32'd5196;
8'd202 : H_old=32'd5171;
8'd203 : H_old=32'd5145;
8'd204 : H_old=32'd5120;
8'd205 : H_old=32'd5095;
8'd206 : H_old=32'd5070;
8'd207 : H_old=32'd5046;
8'd208 : H_old=32'd5022;
8'd209 : H_old=32'd4998;
8'd210 : H_old=32'd4974;
8'd211 : H_old=32'd4950;
8'd212 : H_old=32'd4927;
8'd213 : H_old=32'd4904;
8'd214 : H_old=32'd4881;
8'd215 : H_old=32'd4858;
8'd216 : H_old=32'd4836;
8'd217 : H_old=32'd4813;
8'd218 : H_old=32'd4791;
8'd219 : H_old=32'd4769;
8'd220 : H_old=32'd4748;
8'd221 : H_old=32'd4726;
8'd222 : H_old=32'd4705;
8'd223 : H_old=32'd4684;
8'd224 : H_old=32'd4663;
8'd225 : H_old=32'd4642;
8'd226 : H_old=32'd4622;
8'd227 : H_old=32'd4601;
8'd228 : H_old=32'd4581;
8'd229 : H_old=32'd4561;
8'd230 : H_old=32'd4541;
8'd231 : H_old=32'd4522;
8'd232 : H_old=32'd4502;
8'd233 : H_old=32'd4483;
8'd234 : H_old=32'd4464;
8'd235 : H_old=32'd4445;
8'd236 : H_old=32'd4426;
8'd237 : H_old=32'd4407;
8'd238 : H_old=32'd4389;
8'd239 : H_old=32'd4370;
8'd240 : H_old=32'd4352;
8'd241 : H_old=32'd4334;
8'd242 : H_old=32'd4316;
8'd243 : H_old=32'd4298;
8'd244 : H_old=32'd4281;
8'd245 : H_old=32'd4263;
8'd246 : H_old=32'd4246;
8'd247 : H_old=32'd4229;
8'd248 : H_old=32'd4212;
8'd249 : H_old=32'd4195;
8'd250 : H_old=32'd4178;
8'd251 : H_old=32'd4161;
8'd252 : H_old=32'd4145;
8'd253 : H_old=32'd4128;
8'd254 : H_old=32'd4112;
8'd255 : H_old=32'd4096;
endcase
if (RGB[15:8] == max)
begin
if (RGB[23:16] >= RGB[31:24])
begin
hue_dividend <= {2'b0,((16'd60*(RGB[23:16] - RGB[31:24])*H_old)>>20)};
end
else
begin
hue_dividend <= 0- ((16'd60*(RGB[31:24] - RGB[23:16])*H_old)>>20);
end
end
else if (RGB[23:16] == max)
begin
if (RGB[31:24] >= RGB[15:8])
begin
hue_dividend <= (16'd120+((16'd60*(RGB[31:24] - RGB[15:8])*H_old)>>20));
end
else
begin
hue_dividend <= (16'd120-((16'd60*(RGB[15:8] - RGB[31:24])*H_old)>>20));
end
end
else
begin
if (RGB[15:8] >= RGB[23:16])
begin
hue_dividend <= (16'd240+((16'd60*(RGB[15:8] - RGB[23:16])*H_old)>>20));
end
else
begin
hue_dividend <= (16'd240-((16'd60*(RGB[23:16] - RGB[15:8])*H_old)>>20));
end
end
h_int = hue_dividend ;
if (h_int < 0)
begin
HSV[31:24] <= ((h_int >>1)+180);
HSV[7:0]<=0;
end
else
begin
HSV[31:24]<= (h_int>>1);
HSV[7:0]<=0;
end
end
// if (hue_dividend < 0)
// H <= ((hue_dividend >>1)+180);
// else
// H <= (hue_dividend>>1);
end
endmodule
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for lfsr_prbs_check
*/
module test_lfsr_prbs_check_prbs31_64;
// Parameters
parameter LFSR_WIDTH = 31;
parameter LFSR_POLY = 31'h10000001;
parameter LFSR_INIT = {LFSR_WIDTH{1'b1}};
parameter LFSR_CONFIG = "FIBONACCI";
parameter REVERSE = 0;
parameter INVERT = 1;
parameter DATA_WIDTH = 64;
parameter STYLE = "AUTO";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] data_in = 0;
reg data_in_valid = 0;
// Outputs
wire [DATA_WIDTH-1:0] data_out;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
data_in,
data_in_valid
);
$to_myhdl(
data_out
);
// dump file
$dumpfile("test_lfsr_prbs_check_prbs31_64.lxt");
$dumpvars(0, test_lfsr_prbs_check_prbs31_64);
end
lfsr_prbs_check #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_INIT(LFSR_INIT),
.LFSR_CONFIG(LFSR_CONFIG),
.REVERSE(REVERSE),
.INVERT(INVERT),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
UUT (
.clk(clk),
.rst(rst),
.data_in(data_in),
.data_in_valid(data_in_valid),
.data_out(data_out)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NOR2_BEHAVIORAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_BEHAVIORAL_V |
// Converts the 256-bit DMA master to the 64-bit PCIe slave
// Doesn't handle any special cases - the GUI validates that the parameters are consistant with our assumptions
module dma_pcie_bridge
(
clk,
reset,
// DMA interface (slave)
dma_address,
dma_read,
dma_readdata,
dma_readdatavalid,
dma_write,
dma_writedata,
dma_burstcount,
dma_byteenable,
dma_waitrequest,
// PCIe interface (master)
pcie_address,
pcie_read,
pcie_readdata,
pcie_readdatavalid,
pcie_write,
pcie_writedata,
pcie_burstcount,
pcie_byteenable,
pcie_waitrequest
);
// Parameters set from the GUI
parameter DMA_WIDTH = 256;
parameter PCIE_WIDTH = 64;
parameter DMA_BURSTCOUNT = 6;
parameter PCIE_BURSTCOUNT = 10;
parameter PCIE_ADDR_WIDTH = 30; // Byte-address width required
parameter ADDR_OFFSET = 0;
// Derived parameters
localparam DMA_WIDTH_BYTES = DMA_WIDTH / 8;
localparam PCIE_WIDTH_BYTES = PCIE_WIDTH / 8;
localparam WIDTH_RATIO = DMA_WIDTH / PCIE_WIDTH;
localparam ADDR_SHIFT = $clog2( WIDTH_RATIO );
localparam DMA_ADDR_WIDTH = PCIE_ADDR_WIDTH - $clog2( DMA_WIDTH_BYTES );
// Global ports
input clk;
input reset;
// DMA slave ports
input [DMA_ADDR_WIDTH-1:0] dma_address;
input dma_read;
output [DMA_WIDTH-1:0 ]dma_readdata;
output dma_readdatavalid;
input dma_write;
input [DMA_WIDTH-1:0] dma_writedata;
input [DMA_BURSTCOUNT-1:0] dma_burstcount;
input [DMA_WIDTH_BYTES-1:0] dma_byteenable;
output dma_waitrequest;
// PCIe master ports
output [31:0] pcie_address;
output pcie_read;
input [PCIE_WIDTH-1:0] pcie_readdata;
input pcie_readdatavalid;
output pcie_write;
output [PCIE_WIDTH-1:0] pcie_writedata;
output [PCIE_BURSTCOUNT-1:0] pcie_burstcount;
output [PCIE_WIDTH_BYTES-1:0] pcie_byteenable;
input pcie_waitrequest;
// Address decoding into byte-address
wire [31:0] dma_byte_address;
assign dma_byte_address = (dma_address * DMA_WIDTH_BYTES);
// Read logic - Buffer the pcie words into a full-sized dma word. The
// last word gets passed through, the first few words are stored
reg [DMA_WIDTH-1:0] r_buffer; // The last PCIE_WIDTH bits are not used and will be swept away
reg [$clog2(WIDTH_RATIO)-1:0] r_wc;
reg [DMA_WIDTH-1:0] r_demux;
wire [DMA_WIDTH-1:0] r_data;
wire r_full;
wire r_waitrequest;
// Full indicates that a full word is ready to be passed on to the DMA
// as soon as the next pcie-word arrives
assign r_full = &r_wc;
// True when a read request is being stalled (not a function of this unit)
assign r_waitrequest = pcie_waitrequest;
// Groups the previously stored words with the next read data on the pcie bus
assign r_data = {pcie_readdata, r_buffer[DMA_WIDTH-PCIE_WIDTH-1:0]};
// Store the first returned words in a buffer, keep track of which word
// we are waiting for in the word counter (r_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_wc <= {$clog2(DMA_WIDTH){1'b0}};
r_buffer <= {(DMA_WIDTH){1'b0}};
end
else
begin
r_wc <= pcie_readdatavalid ? (r_wc + 1) : r_wc;
if(pcie_readdatavalid)
r_buffer[ r_wc*PCIE_WIDTH +: PCIE_WIDTH ] <= pcie_readdata;
end
end
// Write logic - First word passes through, last words are registered
// and passed on to the fabric in order. Master is stalled until the
// full write has been completed (in PCIe word sized segments)
reg [$clog2(WIDTH_RATIO)-1:0] w_wc;
wire [PCIE_WIDTH_BYTES-1:0] w_byteenable;
wire [PCIE_WIDTH-1:0] w_writedata;
wire w_waitrequest;
wire w_sent;
// Indicates the successful transfer of a pcie-word to PCIe
assign w_sent = pcie_write && !pcie_waitrequest;
// Select the appropriate word to send downstream
assign w_writedata = dma_writedata[w_wc*PCIE_WIDTH +: PCIE_WIDTH];
assign w_byteenable = dma_byteenable[w_wc*PCIE_WIDTH_BYTES +: PCIE_WIDTH_BYTES];
// True when avalon is waiting, or the full word has not been written
assign w_waitrequest = (pcie_write && !(&w_wc)) || pcie_waitrequest;
// Keep track of which word segment we are sending in the word counter (w_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
w_wc <= {$clog2(DMA_WIDTH){1'b0}};
else
w_wc <= w_sent ? (w_wc + 1) : w_wc;
end
// Shared read/write logic
assign pcie_address = ADDR_OFFSET + dma_byte_address;
assign pcie_read = dma_read;
assign pcie_write = dma_write;
assign pcie_writedata = w_writedata;
assign pcie_burstcount = (dma_burstcount << ADDR_SHIFT);
assign pcie_byteenable = pcie_write ? w_byteenable : dma_byteenable;
assign dma_readdata = r_data;
assign dma_readdatavalid = r_full && pcie_readdatavalid;
assign dma_waitrequest = r_waitrequest || w_waitrequest;
endmodule
|
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: qram32.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.0.0 Build 614 04/24/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
module qram32 (
address,
byteena,
clock,
data,
wren,
q);
input [13:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../firmware/firmware.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "10240"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../firmware/firmware.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "10240"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
// Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL qram32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL qram32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL qram32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL qram32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL qram32_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL qram32_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
(****************************************************************************)
(* Copyright 2021 The Project Oak Authors *)
(* *)
(* Licensed under the Apache License, Version 2.0 (the "License") *)
(* you may not use this file except in compliance with the License. *)
(* You may obtain a copy of the License at *)
(* *)
(* http://www.apache.org/licenses/LICENSE-2.0 *)
(* *)
(* Unless required by applicable law or agreed to in writing, software *)
(* distributed under the License is distributed on an "AS IS" BASIS, *)
(* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *)
(* See the License for the specific language governing permissions and *)
(* limitations under the License. *)
(****************************************************************************)
Require Import Coq.Vectors.Vector.
Local Open Scope vector_scope.
Import VectorNotations.
Require Import ExtLib.Structures.Monads.
Import MonadNotation.
Local Open Scope monad_scope.
Require Import Cava.Core.Core.
Require Import Cava.Lib.Combinators.
(**** IMPORTANT: if you make changes to the API of these definitions, or add new
ones, make sure you update the reference at docs/reference.md! ****)
Section WithCava.
Context `{semantics:Cava}.
(* Constant signals. *)
(* This component always returns the value 0. *)
Definition zero : signal Bit := constant false.
(* This component always returns the value 1. *)
Definition one : signal Bit := constant true.
Definition all {n} (v : signal (Vec Bit n)) : cava (signal Bit) :=
match n with
| 0 => ret one
| _ => tree and2 v
end.
Definition any {n} (v : signal (Vec Bit n)) : cava (signal Bit) :=
match n with
| 0 => ret zero
| _ => tree or2 v
end.
Fixpoint eqb {t : SignalType} : signal t * signal t -> cava (signal Bit) :=
match t as t0 return signal t0 * signal t0 -> cava (signal Bit) with
| Void => fun _ => ret one
| Bit => xnor2
| ExternalType s => fun _ => ret one
| Vec a n => fun '(x,y) =>
eq_results <- Vec.map2 eqb (x, y) ;;
all eq_results
end.
End WithCava.
|
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