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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O2BB2AI_FUNCTIONAL_PP_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2AI_FUNCTIONAL_PP_V |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: diploma_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module diploma_new (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites-new/diploma_new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites-new/diploma_new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL diploma_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL diploma_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL diploma_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL diploma_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL diploma_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL diploma_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V |
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
/*
Filename: shiftreg.v
Version: 1.0
Verilog Standard: Verilog-2001
Description: A simple, single clock, simple dual port (SCSDP) ram
Notes: Any modifications to this file should meet the conditions set
forth in the "Trellis Style Guide"
Author: Dustin Richmond (@darichmond)
Co-Authors:
*/
`timescale 1ns/1ns
`include "functions.vh"
module scsdpram
#(
parameter C_WIDTH = 32,
parameter C_DEPTH = 1024
)
(
input CLK,
input RD1_EN,
input [clog2s(C_DEPTH)-1:0] RD1_ADDR,
output [C_WIDTH-1:0] RD1_DATA,
input WR1_EN,
input [clog2s(C_DEPTH)-1:0] WR1_ADDR,
input [C_WIDTH-1:0] WR1_DATA
);
reg [C_WIDTH-1:0] rMemory [C_DEPTH-1:0];
reg [C_WIDTH-1:0] rDataOut;
assign RD1_DATA = rDataOut;
always @(posedge CLK) begin
if (WR1_EN) begin
rMemory[WR1_ADDR] <= #1 WR1_DATA;
end
if(RD1_EN) begin
rDataOut <= #1 rMemory[RD1_ADDR];
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_crc8_d1 crc1.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_crc8_d1.v,v $
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.5 2001/12/06 10:01:57 mohor
// Warnings from synthesys tools fixed.
//
// Revision 1.4 2001/11/26 10:47:09 mohor
// Crc generation is different for read or write commands. Small synthesys fixes.
//
// Revision 1.3 2001/10/19 11:40:02 mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.2 2001/09/20 10:11:25 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
// Revision 1.3 2001/06/01 22:22:36 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2 2001/05/18 13:10:00 mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1 2001/05/18 06:35:03 mohor
// Initial release
//
//
///////////////////////////////////////////////////////////////////////
// File: CRC8_D1.v
// Date: Fri Apr 27 20:56:55 2001
//
// Copyright (C) 1999 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose: Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 2 8)
// * data width: 1
//
// Info: [email protected] (Jan Decaluwe)
// http://www.easics.com
///////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "rtl/verilog/bench_timescale.v"
// synopsys translate_on
`include "rtl/verilog/dbg_interface/dbg_defines.v"
module dbg_crc8_d1 (Data, EnableCrc, Reset, SyncResetCrc, CrcOut, Clk);
parameter Tp = 1;
input Data;
input EnableCrc;
input Reset;
input SyncResetCrc;
input Clk;
output [7:0] CrcOut;
reg [7:0] CrcOut;
// polynomial: (0 1 2 8)
// data width: 1
function [7:0] nextCRC8_D1;
input Data;
input [7:0] Crc;
reg [0:0] D;
reg [7:0] C;
reg [7:0] NewCRC;
begin
D[0] = Data;
C = Crc;
NewCRC[0] = D[0] ^ C[7];
NewCRC[1] = D[0] ^ C[0] ^ C[7];
NewCRC[2] = D[0] ^ C[1] ^ C[7];
NewCRC[3] = C[2];
NewCRC[4] = C[3];
NewCRC[5] = C[4];
NewCRC[6] = C[5];
NewCRC[7] = C[6];
nextCRC8_D1 = NewCRC;
end
endfunction
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
CrcOut[7:0] <= #Tp 0;
else
if(SyncResetCrc)
CrcOut[7:0] <= #Tp 0;
else
if(EnableCrc)
CrcOut[7:0] <= #Tp nextCRC8_D1(Data, CrcOut);
end
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ram.v
//
// *Module Description:
// Scalable RAM model
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module ram_16x1k_sp (
clka,
ena,
wea,
addra,
dina,
douta
);
input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
//============
// RAM
//============
ram_sp #(.ADDR_MSB(9), .MEM_SIZE(2048)) ram_sp_inst (
// OUTPUTs
.ram_dout ( douta), // RAM data output
// INPUTs
.ram_addr ( addra), // RAM address
.ram_cen (~ena), // RAM chip enable (low active)
.ram_clk ( clka), // RAM clock
.ram_din ( dina), // RAM data input
.ram_wen (~wea) // RAM write enable (low active)
);
endmodule // ram_16x1k_sp
|
`timescale 1ns / 10ps
module simple_test ();
reg [3:0] a_in;
reg [3:0] b_in;
reg [3:0] s_in;
reg M_in,Ci_inverse_in;
wire [3:0] Y_out;
wire P_out,Q_out,Co_inverse_out,AequalsB_out;
ALU alu(a_in,b_in,s_in,M_in,Ci_inverse_in,P_out,Q_out,Co_inverse_out,Y_out,AequalsB_out);
integer i,j,k,l,m;
initial begin
a_in = 4'b0110;
b_in = 4'b1011;
s_in = 4'b0000;
M_in = 1'b0;
Ci_inverse_in = 1'b0;
end
initial begin
for (i=0;i<2;i=i+1)
begin
for(j=0;j<2;j=j+1)
begin
for(k=0;k<16;k=k+1)
begin
#100 a_in = 4'b0110;
b_in = 4'b1011;
s_in = k;
M_in = j;
Ci_inverse_in = i;
#10 $display($time,,"a_in=%b,b_in=%b,s_in=%b,M_in=%b,Ci_inverse_in=%b Y_out=%b,P_out=%b,Q_out=%b,Co_inverse_out=%b,AequalsB_out=%b",a_in,b_in,s_in,M_in,Ci_inverse_in,Y_out,P_out,Q_out,Co_inverse_out,AequalsB_out);
end
end
end
end
endmodule // test
|
module module1(clk_, rst_, bar0, bar1, foo0, foo1);
input clk_;
input rst_;
input [1:0] bar0;
input [1:0] bar1;
output [1:0] foo0;
output [1:0] foo1;
parameter poser_tied = 1'b1;
parameter poser_width_in = 0+1-0+1+1-0+1;
parameter poser_width_out = 0+1-0+1+1-0+1;
parameter poser_grid_width = 2;
parameter poser_grid_depth = 2;
parameter [poser_grid_width-1:0] cellTypes [0:poser_grid_depth-1] = '{ 2'b11,2'b11 };
wire [poser_width_in-1:0] poser_inputs;
assign poser_inputs = { bar0,bar1 };
wire [poser_width_out-1:0] poser_outputs;
assign { foo0,foo1 } = poser_outputs;
wire [poser_grid_width-1:0] poser_grid_output [0:poser_grid_depth-1];
wire poser_clk;
assign poser_clk = clk_;
wire poser_rst;
assign poser_rst = rst_;
for (genvar D = 0; D < poser_grid_depth; D++) begin
for (genvar W = 0; W < poser_grid_width; W++) begin
if (D == 0) begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_tied ,
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D][W-1],
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end
end else begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D-1][poser_grid_depth-1] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D][W-1] }),
.o(poser_grid_output[D][W]));
end
end
end
end
generate
if (poser_width_out == 1) begin
poserMux #(.poser_mux_width_in(poser_grid_width)) pm (.i(poser_grid_output[poser_grid_depth-1]),
.o(poser_outputs));
end
else if (poser_grid_width == poser_width_out) begin
assign poser_outputs = poser_grid_output[poser_grid_depth-1];
end
else if (poser_grid_width > poser_width_out) begin
wire [poser_grid_width-1:0] poser_grid_output_last;
assign poser_grid_output_last = poser_grid_output[poser_grid_depth-1];
poserMux #(.poser_mux_width_in((poser_grid_width - poser_width_out) + 1)) pm (.i(poser_grid_output_last[poser_grid_width-1:poser_width_out-1]),
.o(poser_outputs[poser_width_out-1]));
assign poser_outputs[poser_width_out-2:0] = poser_grid_output_last[poser_width_out-2:0];
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BOI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__A21BOI_FUNCTIONAL_PP_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , b, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BOI_FUNCTIONAL_PP_V |
/**
MIPS32r1 CPU.
Conventional 5-stage MIPS32r1 implementation.
Optimized for ease of development and maintenance.
The 'architecture manual' referenced in the comments is revision 3.12 of
MIPS Technologies' 'MIPS® Architecture For Programmers' (MD00090).
UNFINISHED!
~~~~~~~~~~~
Major stuff remains to be done:
- COP0 & supervisor mode stuff partially implemented.
- Interrupt logic partially implemented.
- Many instructions missing.
- Buggy support for wait states in data bus...
- ...and support for code waits is shaky.
I started this module as a minimal riscv implementation. I've morphed it
into a MIPS32 but many riscv traces remain, mostly around COP0 registers
(called CSR here).
Signal naming convention
~~~~~~~~~~~~~~~~~~~~~~~~
Signals are prefixed according to the pipeline stage they belong to:
sX_* - Combinational signal within stage X.
sXYr_* - Register, input from stage X, output to stage Y.
co_* - Combinational signal, control logic outside pipeline.
cor_* - Register, control logic outside pipeline.
*/
module cpu
#(
parameter OPTION_RESET_ADDR = 32'hbfc00000,
parameter OPTION_TRAP_ADDR = 32'hbfc00180
)
(
input CLK,
input RESET_I,
output [31:0] CADDR_O,
output [1:0] CTRANS_O,
input [31:0] CRDATA_I,
input CREADY_I,
input [1:0] CRESP_I,
output [31:0] DADDR_O,
output [1:0] DTRANS_O,
output [2:0] DSIZE_O,
input [31:0] DRDATA_I,
output [31:0] DWDATA_O,
output DWRITE_O,
input DREADY_I,
input [1:0] DRESP_I,
input [4:0] HWIRQ_I,
input STALL_I
);
//==== Local parameters ====================================================
// Hardwired values of several CSR. Not really user-configurable.
localparam FEATURE_PRID = 32'h00000000;
localparam FEATURE_CONFIG0 = 32'h00000000;
localparam FEATURE_CONFIG1 = 32'h00000000;
// Translated indices of implemented, writeable CSRs.
// Smaller than spec index to save a few DFFs in the pipeline regs.
// (Read-only regs don't need their indices propagated to writeback stage.)
localparam
CSRB_MCOMPARE = 4'b0000, CSRB_MSTATUS = 4'b0001,
CSRB_MCAUSE = 4'b0010, CSRB_MEPC = 4'b0011,
CSRB_MCONFIG0 = 4'b0100, CSRB_MERROREPC = 4'b0101;
// Instruction formats. Used to decode position of instruction fields.
localparam
TYP_J = 4'b0000, TYP_B = 4'b0001, TYP_I = 4'b0010, TYP_M = 4'b0011,
TYP_S = 4'b0100, TYP_R = 4'b0101, TYP_P = 4'b0110, TYP_T = 4'b0111,
TYP_E = 4'b1000, TYP_IH =4'b1001, TYP_IU =4'b1010, TYP_BAD = 4'b1111;
// Selection mux control for ALU operand 0.
localparam
P0_0 = 3'b000, P0_RS1 = 3'b001, P0_PC = 3'b010,
P0_PCS = 3'b011, P0_IMM = 3'b100, P0_X = 3'b000;
// Selection mux control for ALU operand 1.
localparam
P1_0 = 2'b00, P1_RS2 = 2'b01, P1_CSR = 2'b10,
P1_IMM = 2'b11, P1_X = 2'b00;
// ALU operation selection.
localparam
OP_NOP = 5'b00000, OP_SLL = 5'b00100, OP_SRL = 5'b00110,
OP_SRA = 5'b00111, OP_ADD = 5'b10000, OP_SUB = 5'b10001,
OP_SLT = 5'b10101, OP_SLTU = 5'b10111, OP_OR = 5'b01000,
OP_AND = 5'b01001, OP_XOR = 5'b01010, OP_NOR = 5'b01011;
// Writeback selection ({R}egister bank, {C}SR or {N}one).
localparam
WB_R = 2'b10, WB_N = 2'b00, WB_C = 2'b01;
//==== Register macros -- all DFFs inferred using these ====================
// Pipeline reg. Input st is load enable for stalls.
`define PREG(st, name, resval, enable, loadval) \
always @(posedge CLK) \
if (RESET_I) /* enable ignored. */ \
name <= resval; \
else if(~st) \
name <= loadval;
// Same as PREG but gets RESET when the stage is bubbled -- even if stalled.
`define PREGC(st, name, resval, enable, loadval) \
always @(posedge CLK) \
if (RESET_I || ~enable) \
name <= resval; \
else if(~st) \
name <= loadval;
// COP0 reg. Load ports for MTC0 writebacks AND traps.
`define CSREGT(st, name, resval, trapen, trapval, loadval) \
always @(posedge CLK) \
if (RESET_I) \
s42r_csr_``name <= resval; \
else begin \
if (s4_en & ~st & trapen) \
s42r_csr_``name <= trapval; \
else if (s4_en & s34r_wb_csr_en & (s34r_csr_xindex==CSRB_``name)) \
s42r_csr_``name <= loadval; \
end
// COP0 reg. Load port for MTC0 only.
`define CSREG(st, name) \
always @(posedge CLK) \
if (RESET_I) \
s42r_csr_``name <= 32'h0; \
else if (s4_en & ~st & s34r_wb_csr_en & (s34r_csr_xindex==CSRB_``name)) \
s42r_csr_``name <= s34r_alu_res;
//==== Per-machine state registers =========================================
// COP0 registers. Note they are 'packed' (@note6).
reg [16:0] s42r_csr_MCAUSE;
reg [12:0] s42r_csr_MSTATUS;
reg [31:0] s42r_csr_MEPC;
reg [31:0] s42r_csr_MIP; // FIXME merge into CAUSE
reg [31:0] s42r_csr_MERROREPC;
reg [31:0] s42r_csr_MCOMPARE;
// Register bank.
reg [31:0] s42r_rbank [0:31];
// These macros unpack COP0 regs into useful names.
// Also define packed-to-32 and 32-to-packed macros.
`define STATUS_BEV s42r_csr_MSTATUS[12]
`define STATUS_IM s42r_csr_MSTATUS[11:4]
`define STATUS_UM s42r_csr_MSTATUS[3]
`define STATUS_ERL s42r_csr_MSTATUS[2]
`define STATUS_EXL s42r_csr_MSTATUS[1]
`define STATUS_IE s42r_csr_MSTATUS[0]
`define STATUS_PACK(w) {w[22],w[15:8],w[4],w[2],w[1],w[0]}
`define STATUS_UNPACK(p) {9'h0,p[12],6'h0,p[11:4],3'h0,p[3:0]}
`define CAUSE_BD s42r_csr_MCAUSE[16]
`define CAUSE_CE s42r_csr_MCAUSE[15:14]
`define CAUSE_IV s42r_csr_MCAUSE[13]
`define CAUSE_IPHW s42r_csr_MCAUSE[12:7]
`define CAUSE_IPSW s42r_csr_MCAUSE[6:5]
`define CAUSE_EXCODE s42r_csr_MCAUSE[4:0]
`define CAUSE_PACK(w) {w[31],w[29:28],w[23],w[15:8],w[6:2]}
`define CAUSE_UNPACK(p) {p[16],1'b0,p[15:14],4'b0,p[13],7'b0,p[12:5],1'b0,p[4:0],2'b0}
//==== Forward declaration of control signals ==============================
reg co_s0_bubble; // Insert bubble in FAddr stage.
reg co_s1_bubble; // Insert bubble in FData stage.
reg co_s2_bubble; // Insert bubble in Decode stage.
reg s0_st, s1_st, s2_st, s3_st, s4_st; // Per-stage stall controls.
//==== Pipeline stage 0 -- Fetch-Address ===================================
// Address phase of fetch cycle.
reg s0_en; // FAddr stage enable.
reg s01r_pending; // Cycle in progress in code bus.
reg s0_pending; //
reg [31:0] s0_pc_fetch; // Fetch address (PC of next instruction).
reg s01r_en; // FData stage enable carried from FAaddr.
reg [31:0] s01r_pc; // PC of instr in FData stage.
reg [31:0] s01r_pc_seq;
// Fetch address mux: sequential or non sequential.
always @(*) begin
s0_en = ~RESET_I & ~co_s0_bubble; // See @note11.
s0_pc_fetch = s2_go_seq? s01r_pc_seq : s2_pc_nonseq;
// A new cycle is started whenever this stage is enabled and it is
// terminated whenever CREADY comes high.
s0_pending = s0_en | (s01r_pending & ~CREADY_I);
end
// Drive code bus straight from stage control signals.
assign CADDR_O = s0_pc_fetch;
assign CTRANS_O = s0_en? 2'b10 : 2'b00;
// Remember if there's a bus cycle in progress.
`PREG (s0_st, s01r_pending, 0, 1, s0_pending)
// FA-FD pipeline registers.
`PREG (s0_st, s01r_en, 1'b1, 1'b1, s0_en)
`PREG (s0_st, s01r_pc, OPTION_RESET_ADDR-4, s0_en, s0_pc_fetch)
`PREG (s0_st, s01r_pc_seq, OPTION_RESET_ADDR, s0_en, s0_pc_fetch + 4)
//==== Pipeline stage 1 -- Fetch-Data ======================================
// Data phase of fetch cycle.
reg s1_en; // FD stage enable.
reg s1_mem_truncated; // Code cycle truncated by (non-code) stall.
reg s12r_mem_truncated; //
reg s12r_en; // Decode stage enable carried from FData.
reg [31:0] s12r_ir; // Instruction register (valid in stage DE).
reg [31:0] s12r_irs; // FIXME explain.
reg [31:0] s12r_pc; // PC of instruction in DE stage.
reg [31:0] s12r_pc_seq; // PC of instr following fdr_pc_de one.
reg [31:0] s1_ir; // Mux at input of IR reg.
always @(*) begin
s1_en = s01r_en & ~co_s1_bubble;
// If we have a word coming in on code bus but this stage is stalled,
// store it in s12r_irs and remember we've truncated a cycle.
s1_mem_truncated = s1_st & CREADY_I;
s1_ir = s12r_mem_truncated? s12r_irs : CRDATA_I; // @note1
end
// Load IR from code bus (if cycle complete) OR saved IR after a stall.
`PREGC(s1_st, s12r_ir, 32'h0, s1_en & CREADY_I, s1_ir) // @note9
// When stage 1 is stalled, save IR to be used after end of stall.
`PREG (1'b0, s12r_irs, 32'h0, s1_mem_truncated, CRDATA_I)
// Remember if we have saved a code word from a truncated code cycle.
`PREG (1'b0, s12r_mem_truncated, 1'b0, 1'b1, s1_mem_truncated)
// FD-DE pipeline registers.
`PREG (s1_st, s12r_en, 1'b1, 1'b1, s1_en)
`PREG (s1_st, s12r_pc, OPTION_RESET_ADDR, s1_en, s01r_pc)
`PREG (s1_st, s12r_pc_seq, OPTION_RESET_ADDR+4, s1_en, s01r_pc_seq)
//==== Pipeline stage Decode ===============================================
// Last stage of Fetch pipeline, first of Execute pipeline.
// PC flow logic / IR decoding / RBank read.
reg [31:0] s23r_arg0; // ALU arg0.
reg [31:0] s23r_arg1; // ALU arg1.
reg s23r_wb_en; // Writeback enable (main reg bank).
reg s23r_wb_csr_en; // Writeback enable (CSR reg bank).
reg [3:0] s23r_csr_xindex; // Index (translated) of target CSR if any.
reg [4:0] s23r_rd_index; // Index of target register if any.
reg [4:0] s23r_alu_op; // ALU operation.
reg [31:0] s23r_mem_addr; // MEM address.
reg [1:0] s23r_mem_trans; // MEM transaction type.
reg [1:0] s23r_mem_size; // MEM transaction size.
reg s23r_store_en; // Active for store MEM cycle.
reg s23r_load_en; // Active for load MEM cycle.
reg [31:0] s23r_mem_wdata; // MEM write data.
reg s23r_load_exz; // 1 if MEM subword load zero-extends to word.
reg s23r_trap; // TRAP event CSR control passed on to EX.
reg s23r_eret; // ERET event CSR control passed on to EX.
reg [4:0] s23r_excode; // Trap cause code passed on to EX.
reg [31:0] s23r_epc; // Next EPC to be passed on to next stages.
reg s2_en; // DE stage enable.
reg s23r_en; // Execute stage enable carried over from Dec.
reg [31:0] s2_pc_nonseq; // Next PC if any possible jump is taken.
reg [1:0] s2_opcode; // IR opcode field (2 bits used out of 6).
reg [4:0] s2_rs1_index; // Index for RS1 from IR.
reg [4:0] s2_rs2_index; // Index for RS2 from IR.
reg [4:0] s2_rd_index; // Index for RD from IR.
reg [7:0] s2_csr_index; // Index for CSR from IR (Reg index + sel).
reg [3:0] s2_csr_xindex; // Index for CSR translated.
reg [27:0] s2_m; // Concatenation of other signals for clarity.
reg [3:0] s2_type; // Format of instruction in IR.
reg s2_link; // Save PC to r31.
reg [2:0] s2_p0_sel; // ALU argument 0 selection.
reg [1:0] s2_p1_sel; // ALU argument 1 selection.
reg s2_wb_en; // Writeback enable for reg bank.
reg s2_wb_csr_en; // Writeback enable for CSR.
reg [1:0] s2_alu_sel; // Select ALU operation (hardwired/IR).
reg [4:0] s2_alu_op; // ALU operation fully decoded.
reg [4:0] s2_alu_op_f3; // ALU operation as encoded in func3 (IMM).
reg [4:0] s2_alu_op_csr; // ALU operation for CSR instructions.
reg s2_alu_en; // ALU operation is actually used.
reg s2_invalid; // IR is invalid;
reg [1:0] s2_flow_sel; // {00,01,10,11} = {seq/trap, JALR, JAL, Bxx}.
reg s2_cop0_access; // COP0 access instruction in IR.
reg s2_user_mode; // 1 -> user mode, 0 -> kernel mode.
reg [1:0] s2_break_syscall; // Trap caused by BREAK or SYSCALL instruction.
reg s2_trap_cop_unusable; // Trap caused by COP access in user mode.
reg s2_trap; // Take trap for any cause.
reg s2_eret; // ERET instruction.
reg s2_skip_seq_instr; // Skip instruction at stage 1 (traps/erets/etc.)
reg [4:0] s2_excode; // Trap cause code.
reg [31:0] s2_pc_branch; // Branch target;
reg [31:0] s2_pc_jump; // Jump (JAL) target;
reg [31:0] s2_pc_jalr; // Jump (JALR) target;
reg [31:0] s2_pc_trap_eret; // Trap/ERET PC target.
reg [31:0] s2_j_immediate; // Immediate value from J-type IR.
reg [31:0] s2_b_immediate; // Immediate value from B-type IR.
reg [31:0] s2_s_immediate; // Immediate value from S-type IR.
reg [31:0] s2_i_immediate; // Immediate value from I-type IR.
reg [31:0] s2_ih_immediate; // Immediate value from IH-type IR.
reg [31:0] s2_iu_immediate; // Immediate value from IU-type IR.
reg [31:0] s2_e_immediate; // Immediate value from E-type IR.
reg [31:0] s2_t_immediate; // Immediate value from T-type IR.
reg [31:0] s2_immediate; // Immediate value used in Execute stage.
reg [31:0] s2_cop_imm; // Immediate value for trap-related instructions.
reg [31:0] s2_csr; // CSR value read from CSR bank.
reg [31:0] s2_rs1_bank; // Register RS1 value read from bank.
reg [31:0] s2_rs2_bank; // Register RS2 value read from bank.
reg [31:0] s2_rs1; // Register RS1 value after FFWD mux.
reg [31:0] s2_rs2; // Register RS2 value after FFWD mux.
reg s2_rs12_equal; // RS1 == RS2.
reg s2_bxx_cond_val; // Set if Bxx condition is true.
reg [2:0] s2_bxx_cond_sel; // Selection of branch condition.
reg [31:0] s2_arg0; // ALU arg0 selection mux.
reg [31:0] s2_arg1; // ALU arg1 selection mux.
reg s2_3reg; // 1 in 3-reg formats, 0 in others.
reg [31:0] s2_mem_addr; // MEM address for load/store ops.
reg [31:0] s2_mem_addr_imm; // Immediate value used to compute mem address.
reg [1:0] s2_mem_trans; // MEM transaction type.
reg [1:0] s2_mem_size; // MEM transaction size.
reg s2_load_exz; // 1 if MEM subword load zero-extends to word.
reg s2_load_en; // MEM load.
reg s2_store_en; // MEM store.
reg [31:0] s2_mem_wdata; // MEM write data.
reg s2_ie; // Final irq enable.
reg [7:0] s2_masked_irq; // IRQ lines after masking.
reg s2_irq_final; // At least one pending IRQ enabled.
reg s2_hw_trap; // Any HW trap caught in stages 0..2.
reg s2_go_seq; // Sequential/Non-sequential PC selection.
// Pipeline bubble logic.
always @(*) begin
// The load hazard stalls & trap stalls inserts a bubble in stage 2 by
// clearing s2_en (in addition to stalling stages 0 to 2.)
s2_en = s12r_en & ~co_s2_bubble;
end
// Macros for several families of instruction binary pattern.
// Used as keys in the decoding table below.
// 'TA2' stands for "Table A-2" of the MIPS arch manual, vol. 2.
`define TA2(op) {op, 26'b?????_?????_????????????????}
`define TA2rt0(op) {op, 26'b?????_00000_????????????????}
`define TA2rs0(op) {op, 26'b00000_?????_????????????????}
`define TA3(fn) {26'b000000_?????_???????????????, fn}
`define TA3rs0(fn) {26'b000000_00000_???????????????, fn}
`define TA4(fn) {11'b000001_?????, fn, 16'b????????????????}
`define TA9(mt) {6'b010000, mt, 21'b?????_?????_00000000_???}
`define TA10(fn) {26'b010000_1_0000000000000000000, fn}
// Grouped control signals output by decoding table.
// Each macro is used for a bunch of alike instructions.
`define IN_B(sel) {3'b000, sel, 4'h0, 2'd3, TYP_B, P0_X, P1_X, WB_N, OP_NOP}
`define IN_BAL(sel) {3'b000, sel, 4'h0, 2'd3, TYP_B, P0_PCS, P1_0, WB_R, OP_ADD}
`define IN_IH(op) {3'b000, 3'b0, 4'h0, 2'b0, TYP_IH, P0_RS1, P1_IMM, WB_R, op}
`define IN_IU(op) {3'b000, 3'b0, 4'h0, 2'b0, TYP_IU, P0_RS1, P1_IMM, WB_R, op}
`define IN_Ilx {3'b000, 3'b0, 4'h8, 2'b0, TYP_I, P0_RS1, P1_IMM, WB_R, OP_NOP}
`define IN_Isx {3'b000, 3'b0, 4'h4, 2'b0, TYP_I, P0_RS1, P1_IMM, WB_N, OP_NOP}
`define IN_I(op) {3'b000, 3'b0, 4'h0, 2'b0, TYP_I, P0_RS1, P1_IMM, WB_R, op}
`define IN_J(link) {3'b000, 3'b0, 4'h0, 2'd2, TYP_J, P0_PCS, P1_0, link, OP_ADD}
`define IN_IS(op) {3'b000, 3'b0, 4'h0, 2'b0, TYP_S, P0_IMM, P1_RS2, WB_R, op}
`define IN_R(op) {3'b000, 3'b0, 4'h0, 2'b0, TYP_R, P0_RS1, P1_RS2, WB_R, op}
`define IN_JR {3'b000, 3'b0, 4'h0, 2'b1, TYP_I, P0_PCS, P1_0, WB_N, OP_ADD}
`define IN_CP0(r,w) {3'b001, 3'b0, 4'h0, 2'd0, TYP_I, P0_0, r, w, OP_OR}
`define SPEC(q,r) {q, 3'b0, 3'h0,r, 2'd0, TYP_I, P0_0, P1_X, WB_N, OP_NOP}
`define IN_BAD {3'b000, 3'b0, 4'h0, 2'b0, TYP_BAD, P0_X, P1_X, WB_N, OP_NOP}
// Decoding table.
// TODO A few bits of decoding still done outside this table (see @note7).
always @(*) begin
// FIXME Many instructions missing.
casez (s12r_ir)
`TA2 (6'b000100): s2_m = `IN_B(3'b000); // BEQ
`TA2 (6'b000101): s2_m = `IN_B(3'b001); // BNE
`TA2 (6'b000110): s2_m = `IN_B(3'b010); // BLEZ
`TA2 (6'b000111): s2_m = `IN_B(3'b011); // BGTZ
`TA4 (5'b00000): s2_m = `IN_B(3'b100); // BLTZ
`TA4 (5'b00001): s2_m = `IN_B(3'b101); // BGEZ
`TA4 (5'b10000): s2_m = `IN_BAL(3'b100); // BLTZAL
`TA4 (5'b10001): s2_m = `IN_BAL(3'b101); // BGEZAL
`TA2rs0 (6'b001111): s2_m = `IN_IH(OP_OR); // LUI
`TA2 (6'b001001): s2_m = `IN_I(OP_ADD); // ADDIU
`TA2 (6'b001000): s2_m = `IN_I(OP_ADD); // ADDI
`TA2 (6'b000011): s2_m = `IN_J(WB_R); // JAL
`TA2 (6'b000010): s2_m = `IN_J(WB_N); // J
`TA2 (6'b100000): s2_m = `IN_Ilx; // LB
`TA2 (6'b100100): s2_m = `IN_Ilx; // LBU
`TA2 (6'b100011): s2_m = `IN_Ilx; // LW
`TA2 (6'b100001): s2_m = `IN_Ilx; // LH
`TA2 (6'b100101): s2_m = `IN_Ilx; // LHU
`TA2 (6'b101000): s2_m = `IN_Isx; // SB
`TA2 (6'b101011): s2_m = `IN_Isx; // SW
`TA2 (6'b101001): s2_m = `IN_Isx; // SH
`TA3 (6'b001000): s2_m = `IN_JR; // JR
`TA3 (6'b100000): s2_m = `IN_R(OP_ADD); // ADD
`TA3 (6'b100001): s2_m = `IN_R(OP_ADD); // ADDU @note2
`TA3 (6'b100010): s2_m = `IN_R(OP_SUB); // SUB
`TA3 (6'b100011): s2_m = `IN_R(OP_SUB); // SUBU
`TA3 (6'b101010): s2_m = `IN_R(OP_SLT); // SLT
`TA3 (6'b101011): s2_m = `IN_R(OP_SLTU); // SLTU
`TA2 (6'b001010): s2_m = `IN_I(OP_SLT); // SLTI
`TA2 (6'b001011): s2_m = `IN_IU(OP_SLTU); // SLTIU
`TA3 (6'b100100): s2_m = `IN_R(OP_AND); // AND
`TA3 (6'b100101): s2_m = `IN_R(OP_OR); // OR
`TA3 (6'b100110): s2_m = `IN_R(OP_XOR); // XOR
`TA3 (6'b100111): s2_m = `IN_R(OP_NOR); // NOR
`TA2 (6'b001100): s2_m = `IN_IU(OP_AND); // ANDI
`TA2 (6'b001101): s2_m = `IN_IU(OP_OR); // ORI
`TA2 (6'b001110): s2_m = `IN_IU(OP_XOR); // XORI
`TA3rs0 (6'b000000): s2_m = `IN_IS(OP_SLL); // SLL
`TA3 (6'b000100): s2_m = `IN_R(OP_SLL); // SLLV
`TA3rs0 (6'b000010): s2_m = `IN_IS(OP_SRL); // SRL
`TA3 (6'b000110): s2_m = `IN_R(OP_SRL); // SRLV
`TA3rs0 (6'b000011): s2_m = `IN_IS(OP_SRA); // SRA
`TA3 (6'b000111): s2_m = `IN_R(OP_SRA); // SRAV
`TA9 (5'b00100): s2_m = `IN_CP0(P1_RS2,WB_C);// MTC0
`TA9 (5'b00000): s2_m = `IN_CP0(P1_CSR,WB_R);// MFC0
`TA10 (6'b011000): s2_m = `SPEC(3'b0,1'b1); // ERET
`TA3 (6'b001100): s2_m = `SPEC(3'b010,1'b0); // SYSCALL
`TA3 (6'b001101): s2_m = `SPEC(3'b100,1'b0); // BREAK
default: s2_m = `IN_BAD; // All others
endcase
// Unpack the control signals output by the table.
s2_break_syscall = s2_m[27:26];
s2_cop0_access = s2_m[25];
s2_bxx_cond_sel = s2_m[24:22];
{s2_load_en, s2_store_en} = s2_m[21:20];
{s2_eret, s2_flow_sel, s2_type} = s2_m[19:12];
{s2_p0_sel, s2_p1_sel} = s2_m[11:7];
{s2_wb_en, s2_wb_csr_en, s2_alu_op} = s2_m[6:0];
s2_alu_en = ~(s2_alu_op == OP_NOP);
s2_3reg = (s2_type==TYP_R) | (s2_type == TYP_P) | (s2_type == TYP_S);
s2_link = (s2_p0_sel==P0_PCS) & s2_wb_en;
end
// Extract some common instruction fields including immediate field.
always @(*) begin
s2_opcode = s12r_ir[27:26];
s2_rs1_index = s12r_ir[25:21];
s2_rs2_index = s12r_ir[20:16];
s2_rd_index = s2_link? 5'b11111 : s2_3reg? s12r_ir[15:11] : s12r_ir[20:16];
s2_csr_index = {s12r_ir[15:11], s12r_ir[2:0]};
// Decode immediate field.
s2_j_immediate = {s01r_pc[31:28], s12r_ir[25:0], 2'b00};
s2_b_immediate = {{14{s12r_ir[15]}}, s12r_ir[15:0], 2'b00};
s2_i_immediate = {{16{s12r_ir[15]}}, s12r_ir[15:0]};
s2_iu_immediate = {16'h0, s12r_ir[15:0]};
s2_ih_immediate = {s12r_ir[15:0], 16'h0};
s2_s_immediate = {27'h0, s12r_ir[10:6]};
s2_e_immediate = {12'h0, s12r_ir[25:6]};
s2_t_immediate = {22'h0, s12r_ir[15:6]};
case (s2_type)
TYP_M,
TYP_I: s2_immediate = s2_i_immediate;
TYP_S: s2_immediate = s2_s_immediate;
TYP_IH: s2_immediate = s2_ih_immediate;
TYP_IU: s2_immediate = s2_iu_immediate;
default: s2_immediate = s2_i_immediate;
endcase
case (s2_type)
TYP_E: s2_cop_imm = s2_e_immediate;
default: s2_cop_imm = s2_t_immediate;
endcase
end
// Register bank read ports.
always @(*) begin
s2_rs1_bank = (s2_rs1_index == 5'd0)? 32'd0 : s42r_rbank[s2_rs1_index];
s2_rs2_bank = (s2_rs2_index == 5'd0)? 32'd0 : s42r_rbank[s2_rs2_index];
end
// Feedforward mux.
always @(*) begin
s2_rs1 = co_dhaz_rs1_s3? s3_alu_res : co_dhaz_rs1_s4? s4_wb_data : s2_rs1_bank;
s2_rs2 = co_dhaz_rs2_s3? s3_alu_res : co_dhaz_rs2_s4? s4_wb_data : s2_rs2_bank;
end
// CSR bank multiplexors.
always @(*) begin
// Translation of CSR address to CSR implementation index for writeback.
// (We only need to translate indices of implemented writeable regs.)
case (s2_csr_index)
8'b01011_000: s2_csr_xindex = CSRB_MCOMPARE;
8'b01100_000: s2_csr_xindex = CSRB_MSTATUS;
8'b01101_000: s2_csr_xindex = CSRB_MCAUSE;
8'b01110_000: s2_csr_xindex = CSRB_MEPC;
8'b10000_000: s2_csr_xindex = CSRB_MCONFIG0;
8'b11110_000: s2_csr_xindex = CSRB_MERROREPC;
default: s2_csr_xindex = 4'b1111; // CSR WB does nothing.
endcase
// CSR read multiplexor.
case (s2_csr_index)
8'b01011_000: s2_csr = s42r_csr_MCOMPARE;
8'b01100_000: s2_csr = `STATUS_UNPACK(s42r_csr_MSTATUS);
8'b01101_000: s2_csr = `CAUSE_UNPACK(s42r_csr_MCAUSE);
8'b01110_000: s2_csr = s42r_csr_MEPC;
8'b01111_000: s2_csr = FEATURE_PRID;
8'b10000_000: s2_csr = FEATURE_CONFIG0;
8'b10000_001: s2_csr = FEATURE_CONFIG1;
8'b11110_000: s2_csr = s42r_csr_MERROREPC;
default: s2_csr = 32'h00000000; // Value for unimplemented CSRs.
endcase
end
// Branch condition logic.
always @(*) begin
s2_rs12_equal = (s2_rs1 == s2_rs2);
case (s2_bxx_cond_sel)
3'b000: s2_bxx_cond_val = s2_rs12_equal; // BEQ
3'b001: s2_bxx_cond_val = ~s2_rs12_equal; // BNE
3'b010: s2_bxx_cond_val = s2_rs1[31] | ~(|s2_rs1); // BLEZ
3'b011: s2_bxx_cond_val = ~s2_rs1[31] & (|s2_rs1); // BGTZ
3'b100: s2_bxx_cond_val = s2_rs1[31]; // BLTZ
3'b101: s2_bxx_cond_val = ~s2_rs1[31] | ~(|s2_rs1); // BGEZ
default:s2_bxx_cond_val = s2_rs12_equal; // Don't care case.
endcase
end
// Branch/sequential PC selection logic.
always @(*) begin
// Mux: either sequential or TRAP or ERET -- All SW driven.
s2_pc_trap_eret = (s2_trap|s2_hw_trap)? OPTION_TRAP_ADDR : s42r_csr_MEPC;
s2_pc_branch = s12r_pc_seq + s2_b_immediate;
s2_pc_jump = s2_j_immediate;
s2_pc_jalr = s2_rs1;
// Final PC change mux. Includes branch cond evaluation and HW-driven TRAPs.
s2_go_seq = 1'b0;
casez ({(s2_trap|s2_hw_trap|s2_eret),s2_bxx_cond_val,s2_flow_sel})
4'b1???: s2_pc_nonseq = s2_pc_trap_eret;
4'b0?01: s2_pc_nonseq = s2_pc_jalr;
4'b0?10: s2_pc_nonseq = s2_pc_jump;
4'b0111: s2_pc_nonseq = s2_pc_branch;
default: begin
s2_pc_nonseq = s2_pc_trap_eret;
s2_go_seq = 1'b1; // meaning no jump at all.
end
endcase
end
// ALU input & function code selection.
always @(*) begin
case (s2_p0_sel)
P0_0: s2_arg0 = 32'h0;
P0_RS1: s2_arg0 = s2_rs1;
P0_PCS: s2_arg0 = s01r_pc_seq; // JAL (-> instr after delay slot)
P0_PC: s2_arg0 = s12r_pc; // AUIPC
P0_IMM: s2_arg0 = s2_immediate; // Shift instructions
default: s2_arg0 = 32'h0;
endcase
case (s2_p1_sel)
P1_0: s2_arg1 = 32'h0;
P1_IMM: s2_arg1 = s2_immediate;
P1_RS2: s2_arg1 = s2_rs2;
P1_CSR: s2_arg1 = s2_csr;
default: s2_arg1 = 32'h0;
endcase
end
// Interrupt. (@note5)
always @(*) begin
s2_ie = `STATUS_IE & ~(`STATUS_ERL | `STATUS_EXL);
// TODO timer interrupt request missing.
s2_masked_irq = {1'b0, HWIRQ_I, `CAUSE_IPSW} & `STATUS_IM;
s2_irq_final = |(s2_masked_irq) & s2_ie;
s2_hw_trap = s2_irq_final; // Our only HW trap so far in stages 0..2.
end
// Trap logic.
always @(*) begin
s2_user_mode = {`STATUS_UM,`STATUS_ERL,`STATUS_EXL}==3'b100;
s2_trap_cop_unusable = s2_cop0_access & s2_user_mode;
// Encode trap cause as per table 9.31 in arch manual vol 3.
casez ({s2_irq_final,s2_trap_cop_unusable,s2_break_syscall})
4'b1???: s2_excode = 5'b00000; // Int -- Interrupt.
4'b01??: s2_excode = 5'b01011; // CpU -- Coprocessor unusable.
4'b0010: s2_excode = 5'b01001; // Bp -- Breakpoint.
4'b0001: s2_excode = 5'b01000; // Sys -- Syscall.
default: s2_excode = 5'b00000; // Don't care.
endcase
// Final trap OR.
s2_trap = (|s2_break_syscall) | s2_trap_cop_unusable | s2_irq_final;
// All the cases where we'll want to abort the 'next' instruction.
s2_skip_seq_instr = s2_trap | s2_hw_trap | s2_eret;
end
// MEM control logic.
always @(*) begin
s2_mem_addr_imm = s2_i_immediate;
s2_mem_addr = s2_rs1 + s2_mem_addr_imm;
s2_mem_trans = (s2_load_en | s2_store_en)? 2'b10 : 2'b00; // NONSEQ.
s2_load_exz = s12r_ir[28]; // @note7.
case (s2_opcode[1:0]) // @note7.
2'b00: s2_mem_size = 2'b00;
2'b01: s2_mem_size = 2'b01;
2'b10: s2_mem_size = 2'b10;
default: s2_mem_size = 2'b10;
endcase
case (s2_mem_size)
2'b00: s2_mem_wdata = {4{s2_rs2[ 7: 0]}};
2'b01: s2_mem_wdata = {2{s2_rs2[15: 0]}};
default: s2_mem_wdata = s2_rs2;
endcase
end
// DE-EX pipeline registers.
`PREG (s2_st, s23r_en, 1'b0, 1'b1, s2_en)
`PREG (s2_st, s23r_arg0, 32'h0, s2_en, s2_arg0)
`PREG (s2_st, s23r_arg1, 32'h0, s2_en, s2_arg1)
`PREGC(s2_st, s23r_wb_en, 1'b0, s2_en, s2_wb_en & ~s2_trap)
`PREG (s2_st, s23r_rd_index, 5'd0, s2_en & s2_wb_en, s2_rd_index)
`PREG (s2_st, s23r_alu_op, 5'd0, s2_en & s2_alu_en, s2_alu_op)
`PREG (s2_st, s23r_mem_addr, 32'h0, s2_en, s2_mem_addr)
`PREGC(s2_st, s23r_store_en, 1'b0, s2_en, s2_store_en /* & ~s2_trap*/)
`PREGC(s2_st, s23r_load_en, 1'b0, s2_en, s2_load_en & ~s2_trap)
`PREG (s2_st, s23r_mem_wdata, 32'h0, s2_en, s2_mem_wdata)
`PREG (s2_st, s23r_mem_size, 2'b0, s2_en, s2_mem_size)
`PREGC(s2_st, s23r_mem_trans, 2'b0, s2_en, s2_mem_trans)
`PREG (s2_st, s23r_load_exz, 1'b0, s2_en, s2_load_exz)
`PREG (s2_st, s23r_csr_xindex, 4'd0, s2_en & s2_wb_csr_en, s2_csr_xindex)
`PREGC(s2_st, s23r_wb_csr_en, 1'b0, s2_en, s2_wb_csr_en & ~s2_trap)
`PREGC(s2_st, s23r_trap, 1'd0, s2_en, s2_trap)
`PREGC(s2_st, s23r_eret, 1'd0, s2_en, s2_eret)
`PREG (s2_st, s23r_epc, 32'h0, s2_en & s2_trap, s12r_pc)
`PREG (s2_st, s23r_excode, 5'd0, s2_en & s2_trap, s2_excode)
//==== Pipeline stage Execute ==============================================
// Combinational ALU logic / address phase of MEM cycle.
reg s3_en; // EX stage enable.
reg s34r_en; // WB stage enable carried from EX stage.
reg [31:0] s3_alu_res; // Final ALU result.
reg [31:0] s34r_alu_res; // ALU result in WB stage.
reg s34r_wb_en; // Writeback enable for reg bank.
reg [4:0] s34r_rd_index; // Writeback register index.
reg s34r_load_en; // MEM load.
reg [31:0] s34r_mem_wdata; // MEM store data.
reg [1:0] s34r_mem_size; // 2 LSBs of MEM op size for LOAD data mux.
reg [1:0] s34r_mem_addr; // 2 LSBs of MEM address for LOAD data mux.
reg s34r_load_exz; // 1 if MEM subword load zero-extends to word.
reg s34r_wb_csr_en; // WB enable for CSR bank.
reg [3:0] s34r_csr_xindex; // CSR WB target (translated index).
reg s34r_trap; // TRAP event CSR control passed on to WB.
reg s34r_eret; // ERET event CSR control passed on to WB.
reg [4:0] s34r_excode; // Trap cause code passed on to WB.
reg [31:0] s34r_epc; // Next EPC to be passed on to next stages.
reg [32:0] s3_arg0_ext; // ALU arg0 extended for arith ops.
reg [32:0] s3_arg1_ext; // ALU arg1 extended for arith ops.
reg [32:0] s3_alu_addsub; // Add/sub intermediate result.
reg [31:0] s3_alu_arith; // Arith (+/-/SLT*) intermediate result.
reg [31:0] s3_alu_logic; // Logic intermediate result.
reg [31:0] s3_alu_shift; // Shift intermediate result.
reg [31:0] s3_alu_noarith; // Mux for shift/logic interm-results.
reg s3_mem_pending; // Data bus cycle pending.
reg s34r_mem_pending; // Data bus cycle pending.
// DATA AHB outputs driven directly by S2/3 pipeline registers.
assign DADDR_O = s23r_mem_addr;
assign DTRANS_O = s23r_mem_trans;
assign DSIZE_O = s23r_mem_size;
assign DWRITE_O = s23r_store_en;
// Stage bubble logic.
always @(*) begin
s3_en = s23r_en;
s3_mem_pending = (s23r_load_en | s23r_store_en) | (s34r_mem_pending & ~DREADY_I);
end
// Remember if there's a bus cycle in progress.
`PREG (1'b0, s34r_mem_pending, 0, 1, s3_mem_pending)
// ALU.
always @(*) begin
s3_arg0_ext[31:0] = s23r_arg0;
s3_arg0_ext[32] = s23r_alu_op[1]? 1'b0 : s23r_arg0[31];
s3_arg1_ext[31:0] = s23r_arg1;
s3_arg1_ext[32] = s23r_alu_op[1]? 1'b0 : s23r_arg1[31];
s3_alu_addsub = s23r_alu_op[0]?
s3_arg0_ext - s3_arg1_ext :
s3_arg0_ext + s3_arg1_ext;
case (s23r_alu_op[2:1])
2'b10,
2'b11: s3_alu_arith = {31'h0, s3_alu_addsub[32]};
default: s3_alu_arith = s3_alu_addsub[31:0];
endcase
case (s23r_alu_op[1:0])
2'b00: s3_alu_shift = s23r_arg1 << s23r_arg0[4:0];
2'b10: s3_alu_shift = s23r_arg1 >> s23r_arg0[4:0];
default: s3_alu_shift = $signed(s23r_arg1) >>> s23r_arg0[4:0];
endcase
case (s23r_alu_op[1:0])
2'b00: s3_alu_logic = s23r_arg0 | s23r_arg1;
2'b01: s3_alu_logic = s23r_arg0 & s23r_arg1;
2'b10: s3_alu_logic = s23r_arg0 ^ s23r_arg1;
default: s3_alu_logic = ~(s23r_arg0 | s23r_arg1);
endcase
s3_alu_noarith = s23r_alu_op[3]? s3_alu_logic : s3_alu_shift;
s3_alu_res = s23r_alu_op[4]? s3_alu_arith : s3_alu_noarith;
end
// EX-WB pipeline registers.
`PREG (1'b0, s34r_en, 1'b0, 1'b1, s3_en)
`PREG (s3_st, s34r_alu_res, 32'h0, s3_en, s3_alu_res)
`PREGC(s3_st, s34r_wb_en, 1'b0, s3_en, s23r_wb_en)
`PREG (s3_st, s34r_rd_index, 5'd0, s3_en, s23r_rd_index)
`PREGC(s3_st, s34r_load_en, 1'b0, s3_en, s23r_load_en)
`PREG (s3_st, s34r_mem_size, 2'b00, s3_en, s23r_mem_size)
`PREG (s3_st, s34r_mem_addr, 2'b00, s3_en, s23r_mem_addr[1:0])
`PREG (s3_st, s34r_load_exz, 1'b0, s3_en, s23r_load_exz)
`PREG (s3_st, s34r_csr_xindex, 4'd0, s3_en & s23r_wb_csr_en, s23r_csr_xindex)
`PREG (s3_st, s34r_wb_csr_en, 1'b0, s3_en, s23r_wb_csr_en)
`PREG (s3_st, s34r_mem_wdata, 32'h0, s3_en & s23r_store_en, s23r_mem_wdata)
`PREGC(s3_st, s34r_trap, 1'd0, s3_en, s23r_trap)
`PREGC(s3_st, s34r_eret, 1'd0, s3_en, s23r_eret)
`PREG (s3_st, s34r_epc, 32'h0, s3_en & s23r_trap, s23r_epc)
`PREG (s3_st, s34r_excode, 5'd0, s3_en & s23r_trap, s23r_excode)
//==== Pipeline stage Writeback ============================================
// Writeback selection logic / data phase of MEM cycle.
reg s4_en; // EX stage enable.
reg [31:0] s4_load_data; // Data from MEM load.
reg [31:0] s4_wb_data; // Writeback data (ALU or MEM).
reg [4:0] s4_excode; // Cause code to load in MCAUSE CSR.
reg [16:0] s4_cause_trap; // Value to load on packed CAUSE reg on traps.
reg [12:0] s4_status_trap; // Value to load on MSTATUS CSR on trap.
reg [31:0] s4r_drdata;
reg s4_mem_truncated;
reg s42r_mem_truncated;
assign DWDATA_O = s34r_mem_wdata;
always @(*) begin
s4_mem_truncated = s4_st & DREADY_I;
//s4r_drdata = s42r_mem_truncated? s12r_irs : DRDATA_I;
end
`PREG (1'b0, s4r_drdata, 32'h0, s4_mem_truncated & ~s42r_mem_truncated, DRDATA_I)
`PREG (1'b0, s42r_mem_truncated, 1'b0, 1'b1, s4_mem_truncated)
// Mux for load data byte lanes.
always @(*) begin
case ({s34r_mem_size, s34r_mem_addr})
4'b0011: s4_load_data = s4r_drdata[7:0];
4'b0010: s4_load_data = s4r_drdata[15:8];
4'b0001: s4_load_data = s4r_drdata[23:16];
4'b0000: s4_load_data = s4r_drdata[31:24];
4'b0110: s4_load_data = s4r_drdata[15:0];
4'b0100: s4_load_data = s4r_drdata[31:16];
default: s4_load_data = s4r_drdata;
endcase
if (~s34r_load_exz) begin
case (s34r_mem_size)
2'b00: s4_load_data[31:8] = {24{s4_load_data[7]}};
2'b01: s4_load_data[31:16] = {16{s4_load_data[15]}};
endcase
end
end
always @(*) begin
s4_en = s34r_en;
// FIXME ready/split ignored
s4_wb_data = s34r_load_en? s4_load_data : s34r_alu_res;
// TODO traps caught in WB stage missing.
s4_excode = s34r_excode;
end
// Register bank write port.
always @(posedge CLK) begin
if (s4_en & ~s4_st & s34r_wb_en) begin
s42r_rbank[s34r_rd_index] <= s4_wb_data;
end
end
// CSR input logic. These values are only used if the CSR is not loaded
// using MTC0, see macros CSREGT and CSREG.
always @(*) begin
// STATUS logic: flags modified by TRAP/ERET.
s4_status_trap = s42r_csr_MSTATUS;
casez ({s34r_trap, s34r_eret})
2'b1?: begin // TRAP | (TRAP & ERET)
s4_status_trap[1] = 1'b1; // EXL = 0
end
2'b01: begin // ERET
if (`STATUS_ERL) begin
s4_status_trap[2] = 1'b0; // ERL = 0
end
else begin
s4_status_trap[1] = 1'b0; // EXL = 0
end
end
default:; // No change to STATUS flags.
endcase
// FIXME Cause BC, CE, IV fields h-wired to zero.
// FIXME loading interrupts from stage 2!
s4_cause_trap = {1'b0,2'b00,1'b0, s2_masked_irq, s4_excode};
end
// CSR 'writeback ports'.
`CSREGT(s4_st, MCAUSE, 17'h0, s34r_trap, s4_cause_trap, `CAUSE_PACK(s34r_alu_res))
`CSREGT(s4_st, MEPC, 32'h0, s34r_trap, s34r_epc, s34r_alu_res)
`CSREGT(s4_st, MERROREPC, 32'h0, s34r_trap, s34r_epc, s34r_alu_res)
`CSREGT(s4_st, MSTATUS, 13'h1004, s34r_trap|s34r_eret, s4_status_trap, `STATUS_PACK(s34r_alu_res))
`CSREG (s4_st, MCOMPARE)
//==== Control logic =======================================================
reg co_dhaz_rs1_s3; // S3 wb matches rs1 read.
reg co_dhaz_rs2_s3; // S3 wb matches rs2 read.
reg co_dhaz_rs1_s4; // S4 wb matches rs1 read.
reg co_dhaz_rs2_s4; // S4 wb matches rs2 read.
reg co_dhaz_rs1_ld; // S3vload matches rs1 read.
reg co_dhaz_rs2_ld; // S3vload matches rs2 read.
reg co_s2_stall_load; // Decode stage stall, by load hazard.
reg co_s2_stall_trap; // Decode stage stall, SW trap.
reg co_s012_stall_eret; // Stages 0..2 stall, ERET.
reg co_sx_code_wait; // Code fetch stall.
reg co_sx_data_wait; // Data cycle stall.
// TODO this block will be tidied up when the logic is done.
always @(*) begin
// Data hazard: instr. on stage 3 will write on reg used in stage 2.
co_dhaz_rs1_s3 = (s3_en & s23r_wb_en & (s23r_rd_index==s2_rs1_index));
co_dhaz_rs2_s3 = (s3_en & s23r_wb_en & (s23r_rd_index==s2_rs2_index));
// Data hazard: instr on stage 4 will write on reg used in stage 2.
co_dhaz_rs1_s4 = (s4_en & s34r_wb_en & (s34r_rd_index==s2_rs1_index));
co_dhaz_rs2_s4 = (s4_en & s34r_wb_en & (s34r_rd_index==s2_rs2_index));
// Load data hazard: instr. on stage 3 will load data used in stage 2.
co_dhaz_rs1_ld = (s3_en & s23r_load_en & (s23r_rd_index==s2_rs1_index));
co_dhaz_rs2_ld = (s3_en & s23r_load_en & (s23r_rd_index==s2_rs2_index));
// Stall S0..2 while load data hazard is resolved.
co_s2_stall_load = (co_dhaz_rs1_ld | co_dhaz_rs2_ld);
// Stall S0..2 until trap bubble propagates from to S4. @note3.
co_s2_stall_trap = s23r_trap & s4_en;
// Stall S0..2 & bubble S3..4 until eret bubble propagates to S4. @note4.
co_s012_stall_eret = s23r_eret & s4_en;
// Stall S0..2 & bubble S3..4 while code bus is waited.
co_sx_code_wait = s01r_pending & ~CREADY_I;
co_sx_data_wait = s34r_mem_pending & ~DREADY_I;
// See @note11 on bubbles vs. stalls.
// S2 will bubble on load, trap and eret stalls, and on fetch waits.
co_s2_bubble = co_s2_stall_load | co_s2_stall_trap | co_s012_stall_eret | co_sx_code_wait;
// S1 will bubble on eret and trap stalls AND when the next seq instruction
// needs to be skipped for other reasons. @note8.
co_s1_bubble = co_s2_stall_trap | co_s012_stall_eret | s2_skip_seq_instr;
// S0 bubbles (won't initiate new code fetches) on data waits only.
co_s0_bubble = co_sx_data_wait; // @@@ IN-PROGRESS
// Stall logic. A bunch of OR gates whose truth table is declared
// procedurally, please note the order of the assignments. See @note10.
s4_st = 1'b0 | co_sx_data_wait;
s3_st = s4_st;
s2_st = s3_st | co_s012_stall_eret | co_s2_stall_load | co_s2_stall_trap | co_sx_code_wait;
s1_st = s2_st;
s0_st = s1_st;
end
endmodule // cpu
// FIXME extract notes to documentation & elaborate.
// @note1 -- The cycle after a load-hazard-stall we load IR with the value we
// saved during the stall cycle, NOT from the code bus.
// @note2 -- No traps on arith overflow implemented so ADD==ADDU.
// @note3 -- So that trap values have time to reach STATUS and CAUSE regs in
// stage 4 before 1st trap handler instruction is executed.
// This should work with MEM wait states and whatever's in stages
// 3 & 4 at the time of the trap.
// @note4 -- On ERET we stall the pipeline until the STATUS change reaches S4.
// So instruction after ERET lands on user mode.
// Also bubble stage 1 but not 0. This means that the instructions
// after ERET (sequential after ERET) will be fetched and will be
// dropped (not executed). Whereas the next one (at EPC) will be
// fetched and executed.
// @note5 -- EPC saved by IRQ is victim instruction, NOT the following one.
// @note6 -- COP0 regs 'packed': implemented bits registered, others h-wired.
// @note7 -- Bits of decoding outside decoding table.
// @note8 -- Which bubbles the instruction after ERET, SYSCALL or BREAK.
// @note9 -- Relies on the fact that 0x0 is a NOP opcode. So when stage 1 is
// bubbled, IR is cleared to NOP.
// @note10-- If stage N is stalled (sN_st==1), pipeline registers between N
// and N+1 are prevented from changing -- the stage keeps its state.
// Some regs are excepted, e.g. those dealing with AHB reads.
// @note11-- If stage N is disabled (sN_en==0) it work as if it had a NOP
// in it -- a bubble. AHB control signals are deasserted too.
// A stage can be stalled and not disabled and viceversa.
|
`include "macro.v"
module id_ex_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire[`ALU_OPERATOR_BUS] id_operator,
input wire[`ALU_CATEGORY_BUS] id_category,
input wire[`REGS_DATA_BUS] id_operand1,
input wire[`REGS_DATA_BUS] id_operand2,
input wire[`REGS_ADDR_BUS] id_write_addr,
input wire id_write_enable,
input wire[`REGS_DATA_BUS] id_return_target,
input wire id_is_curr_in_delayslot,
input wire input_is_next_in_delayslot,
input wire[`REGS_DATA_BUS] id_instruction,
output reg[`ALU_OPERATOR_BUS] ex_operator,
output reg[`ALU_CATEGORY_BUS] ex_category,
output reg[`REGS_DATA_BUS] ex_operand1,
output reg[`REGS_DATA_BUS] ex_operand2,
output reg[`REGS_ADDR_BUS] ex_write_addr,
output reg ex_write_enable,
output reg[`REGS_DATA_BUS] ex_return_target,
output reg ex_is_curr_in_delayslot,
output reg is_curr_in_delayslot,
output reg[`REGS_DATA_BUS] ex_instruction
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
ex_operator <= 0; // FIXME: EXE_NOP_OP should be used here, but I used 0
ex_category <= 0; // FIXME: EXE_RES_NOP should be used here, but I used 0
ex_operand1 <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
ex_operand2 <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
ex_write_addr <= 0; // FIXME: NOPRegAddr should be used here, but I used 0
ex_write_enable <= `DISABLE;
ex_return_target <= 0; // FIXME: NOPRegAddr should be used here, but I used 0
ex_is_curr_in_delayslot <= `FALSE;
is_curr_in_delayslot <= `FALSE;
ex_instruction <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
end else if (stall[2] == `ENABLE && stall[3] == `DISABLE) begin
ex_operator <= 0; // FIXME: EXE_NOP_OP should be used here, but I used 0
ex_category <= 0; // FIXME: EXE_RES_NOP should be used here, but I used 0
ex_operand1 <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
ex_operand2 <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
ex_write_addr <= 0; // FIXME: NOPRegAddr should be used here, but I used 0
ex_write_enable <= `DISABLE;
ex_return_target <= 0;
ex_is_curr_in_delayslot <= `FALSE;
ex_instruction <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
end else if (stall[2] == `DISABLE) begin
ex_operator <= id_operator;
ex_category <= id_category;
ex_operand1 <= id_operand1;
ex_operand2 <= id_operand2;
ex_write_addr <= id_write_addr;
ex_write_enable <= id_write_enable;
ex_return_target <= id_return_target;
ex_is_curr_in_delayslot <= id_is_curr_in_delayslot;
is_curr_in_delayslot <= input_is_next_in_delayslot;
ex_instruction <= id_instruction;
end
end
endmodule // id_ex_buffer
|
`timescale 1ns / 1ps
module Controlador_Menu_Editor(
clk,
reset,
boton_arriba_in,
boton_abajo_in,
boton_izq_in,
boton_der_in,
boton_elige_in,
//boton_arriba, boton_abajo, boton_izq, boton_der, boton_elige,
text_red,
text_green,
text_blue,
char_scale,
es_mayuscula,
text_red_temp,
text_green_temp,
text_blue_temp,
char_scale_temp,
es_mayuscula_temp,
nuevo,
guardar,
cerrar,
where_fila,
where_columna
);
input clk, reset;
input boton_arriba_in, boton_abajo_in, boton_izq_in, boton_der_in, boton_elige_in;
wire boton_arriba, boton_abajo, boton_izq, boton_der, boton_elige;
Navegador_PushButtons nav_pb(
.clk_100Mhz (clk),
.boton_arriba_in (boton_arriba_in),
.boton_abajo_in (boton_abajo_in),
.boton_izq_in (boton_izq_in),
.boton_der_in (boton_der_in),
.boton_elige_in (boton_elige_in),
.boton_arriba_out (boton_arriba),
.boton_abajo_out (boton_abajo),
.boton_izq_out (boton_izq),
.boton_der_out (boton_der),
.boton_elige_out (boton_elige)
);
output reg [2:0] where_fila;
output reg [2:0] where_columna;
output reg [9:0] char_scale;
output wire [9:0] char_scale_temp;
output reg text_red, text_green, text_blue, es_mayuscula;
output wire text_red_temp, text_green_temp, text_blue_temp, es_mayuscula_temp;
output reg nuevo, guardar, cerrar;
assign text_red_temp = (where_fila == 5 && where_columna == 1)? 0 :
(where_fila == 5 && where_columna == 2)? 0 :
(where_fila == 5 && where_columna == 3)? 0 :
(where_fila == 5 && where_columna == 4)? 1 :
(where_fila == 5 && where_columna == 5)? 1 :
(where_fila == 5 && where_columna == 6)? 1 : 0;
assign text_green_temp = (where_fila == 5 && where_columna == 1)? 0 :
(where_fila == 5 && where_columna == 2)? 1 :
(where_fila == 5 && where_columna == 3)? 1 :
(where_fila == 5 && where_columna == 4)? 0 :
(where_fila == 5 && where_columna == 5)? 0 :
(where_fila == 5 && where_columna == 6)? 1 : 0;
assign text_blue_temp = (where_fila == 5 && where_columna == 1)? 1 :
(where_fila == 5 && where_columna == 2)? 0 :
(where_fila == 5 && where_columna == 3)? 1 :
(where_fila == 5 && where_columna == 4)? 0 :
(where_fila == 5 && where_columna == 5)? 1 :
(where_fila == 5 && where_columna == 6)? 0 : 1;
assign es_mayuscula_temp = (where_fila == 4 && where_columna == 2)? 0 : 1;
assign char_scale_temp = (where_fila == 6 && where_columna == 1)? 10'd1 :
(where_fila == 6 && where_columna == 2)? 10'd2 :
(where_fila == 6 && where_columna == 3)? 10'd3 :
10'd2;
initial begin
where_fila <= 1;
where_columna <= 1;
char_scale <= 10'd2;
text_red <= 1'b0;
text_green <= 1'b0;
text_blue <= 1'b1;
es_mayuscula <= 1'b1;
nuevo <= 1'b0;
guardar <= 1'b0;
cerrar <= 1'b0;
end
wire temp_clk;
assign temp_clk = (boton_abajo || boton_izq || boton_arriba || boton_der || boton_elige);
reg [2:0] estado, sigEstado;
parameter inicio = 0;
parameter aumenta_fila = 1;
parameter disminuye_fila = 2;
parameter aumenta_columna = 3;
parameter disminuye_columna = 4;
parameter elige = 5;
always @(posedge clk or posedge reset) begin
if (reset)
estado <= inicio;
else
estado <= sigEstado;
end
always @(posedge temp_clk) begin
case (estado)
inicio:
begin
if (boton_arriba)
sigEstado = disminuye_columna;
else if (boton_abajo)
sigEstado = aumenta_columna;
else if (boton_izq)
sigEstado = disminuye_fila;
else if (boton_der)
sigEstado = aumenta_fila;
else if (boton_elige)
sigEstado = elige;
else
sigEstado = inicio;
end
aumenta_fila:
begin
nuevo = 0;
where_columna = 1;
where_fila = (where_fila < 6)? where_fila + 1 : where_fila;
sigEstado = inicio;
end
disminuye_fila:
begin
where_columna = 1;
where_fila = (where_fila > 1)? where_fila - 1 : where_fila;
sigEstado = inicio;
end
aumenta_columna:
begin
case (where_fila)
4:
where_columna = (where_columna < 2)? where_columna + 1: where_columna;
5:
where_columna = (where_columna < 6)? where_columna + 1: where_columna;
6:
where_columna = (where_columna < 3)? where_columna + 1: where_columna;
endcase
sigEstado = inicio;
end
disminuye_columna:
begin
where_columna = (where_columna > 1)? where_columna - 1 : where_columna;
sigEstado = inicio;
end
elige:
begin
case (where_fila)
1:
nuevo = 1;
2:
guardar = 1;
3:
cerrar = 1;
4:
begin
case (where_columna)
1:
es_mayuscula = 1;
2:
es_mayuscula = 0;
endcase
end
5:
begin
case (where_columna)
1:
begin
text_red = 0;
text_green = 0;
text_blue = 1;
end
2:
begin
text_red = 0;
text_green = 1;
text_blue = 0;
end
3:
begin
text_red = 0;
text_green = 1;
text_blue = 1;
end
4:
begin
text_red = 1;
text_green = 0;
text_blue = 0;
end
5:
begin
text_red = 1;
text_green = 0;
text_blue = 1;
end
6:
begin
text_red = 1;
text_green = 1;
text_blue = 0;
end
endcase
end
6:
begin
case (where_columna)
1:
char_scale = 10'd1;
2:
char_scale = 10'd2;
3:
char_scale = 10'd3;
endcase
end
endcase
sigEstado = inicio;
end
default: sigEstado = inicio;
endcase
end
endmodule
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsquare
// ============================================================
// File Name: MULT.v
// Megafunction Name(s):
// altsquare
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module MULT (
dataa,
result);
input [12:0] dataa;
output [25:0] result;
wire [25:0] sub_wire0;
wire [25:0] result = sub_wire0[25:0];
altsquare altsquare_component (
.data (dataa),
.result (sub_wire0),
.aclr (1'b0),
.clock (1'b1),
.ena (1'b1));
defparam
altsquare_component.data_width = 13,
altsquare_component.lpm_type = "ALTSQUARE",
altsquare_component.pipeline = 0,
altsquare_component.representation = "SIGNED",
altsquare_component.result_width = 26;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "0"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "13"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "26"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: DATA_WIDTH NUMERIC "13"
// Retrieval info: CONSTANT: LPM_TYPE STRING "ALTSQUARE"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "0"
// Retrieval info: CONSTANT: REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: RESULT_WIDTH NUMERIC "26"
// Retrieval info: USED_PORT: dataa 0 0 13 0 INPUT NODEFVAL "dataa[12..0]"
// Retrieval info: USED_PORT: result 0 0 26 0 OUTPUT NODEFVAL "result[25..0]"
// Retrieval info: CONNECT: @data 0 0 13 0 dataa 0 0 13 0
// Retrieval info: CONNECT: result 0 0 26 0 @result 0 0 26 0
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module latch_id_ex(
input clock ,
input reset ,
input [ 5:0] stall ,
input [31:0] id_instruction ,
output reg [31:0] ex_instruction ,
input [ 7:0] id_operator ,
output reg [ 7:0] ex_operator ,
input [ 2:0] id_category ,
output reg [ 2:0] ex_category ,
input [31:0] id_operand_a ,
output reg [31:0] ex_operand_a ,
input [31:0] id_operand_b ,
output reg [31:0] ex_operand_b ,
input id_register_write_enable ,
output reg ex_register_write_enable ,
input [ 4:0] id_register_write_address,
output reg [ 4:0] ex_register_write_address,
input [31:0] id_register_write_data ,
output reg [31:0] ex_register_write_data
);
always @ (posedge clock) begin
if (reset == `RESET_ENABLE || (stall[2] == `STALL_ENABLE && stall[3] == `STALL_DISABLE)) begin
ex_instruction <= 32'b0 ;
ex_operator <= `OPERATOR_NOP ;
ex_category <= `CATEGORY_NONE;
ex_operand_a <= 32'b0 ;
ex_operand_b <= 32'b0 ;
ex_register_write_enable <= `WRITE_DISABLE;
ex_register_write_address <= 32'b0 ;
ex_register_write_data <= 32'b0 ;
end
else if (stall[2] == `STALL_DISABLE) begin
ex_instruction <= id_instruction ;
ex_operator <= id_operator ;
ex_category <= id_category ;
ex_operand_a <= id_operand_a ;
ex_operand_b <= id_operand_b ;
ex_register_write_enable <= id_register_write_enable ;
ex_register_write_address <= id_register_write_address;
ex_register_write_data <= id_register_write_data ;
end
end
endmodule |
module lsuc_top (
clk,
reset_,
led,
switches,
segment_,
digit_enable_,
up_,
down_,
left_,
right_,
tx,
rx);
input clk;
input reset_;
output [7:0] led; // LogicSmart LEDs
input [6:0] switches; // LogicSmart toggle switches (first one is tied to reset)
output [6:0] segment_; // Seven segment display segments
output [3:0] digit_enable_; // Seven segment display digit enable
input up_; // D-pad up key
input down_; // D-pad down key
input left_; // D-pad left key
input right_; // D-pad right key
output tx; // UART transmit (to host computer)
input rx; // UART receive (from host computer)
// Top-level module for the LogicStart Microcontroller; instantiates all
// submodules and connects them together (provides no other logic).
wire clk;
wire reset_;
wire [31:0] mcs_addr;
wire mcs_ready;
wire [31:0] mcs_wr_data;
wire mcs_wr_enable;
wire [31:0] mcs_rd_data;
wire mcs_rd_enable;
wire [3:0] mcs_byte_enable;
wire [7:0] addr;
wire req;
wire [7:0] wr_data;
wire rnw;
wire gpio_cs;
wire [7:0] gpio_rd_data;
wire gpio_rdy;
wire disp_cs;
wire [7:0] disp_rd_data;
wire disp_rdy;
wire uart_cs;
wire [7:0] uart_rd_data;
wire uart_rdy;
// Bus controller instantiation ("distributes" MicroBlaze IO bus to local modules)
bus_arb bus_arb (
.clk(clk),
.reset_(reset_),
.mcs_addr(mcs_addr),
.mcs_ready(mcs_ready),
.mcs_wr_data(mcs_wr_data),
.mcs_wr_enable(mcs_wr_enable),
.mcs_rd_data(mcs_rd_data),
.mcs_rd_enable(mcs_rd_enable),
.mcs_byte_enable(mcs_byte_enable),
.addr(addr),
.req(req),
.rnw(rnw),
.wr_data(wr_data),
.gpio_cs(gpio_cs),
.gpio_rd_data(gpio_rd_data),
.gpio_rdy(gpio_rdy),
.disp_cs(disp_cs),
.disp_rd_data(disp_rd_data),
.disp_rdy(disp_rdy),
.uart_cs(uart_cs),
.uart_rd_data(uart_rd_data),
.uart_rdy(uart_rdy)
);
// GPIO control module (provides software interface to leds, switches and d-pad)
gpio_ctrl gpio_ctrl (
.clk(clk),
.reset_(reset_),
.leds(led),
.switches(switches),
.up(~up_),
.down(~down_),
.left(~left_),
.right(~right_),
.addr(addr),
.cs(gpio_cs),
.req(req),
.rnw(rnw),
.wr_data(wr_data),
.rd_data(gpio_rd_data),
.rdy(gpio_rdy)
);
// Display control module (provides software interface to 7-segment display)
disp_ctrl disp_ctrl (
.clk(clk),
.reset_(reset_),
.segments_(segment_),
.digit_enable_(digit_enable_),
.addr(addr),
.cs(disp_cs),
.req(req),
.rnw(rnw),
.wr_data(wr_data),
.rd_data(disp_rd_data),
.rdy(disp_rdy)
);
// UART control module (provides software interface to UART)
uart_ctrl uart_ctrl (
.clk(clk),
.reset_(reset_),
.tx(tx),
.rx(rx),
.addr(addr),
.cs(uart_cs),
.req(req),
.rnw(rnw),
.wr_data(wr_data),
.rd_data(uart_rd_data),
.rdy(uart_rdy)
);
// Xilinx MicroBlaze CPU core
microblaze_mcs_v1_4 mcs_0 (
.Clk(clk), // input Clk
.Reset(~reset_), // input Reset
.IO_Addr_Strobe(), // output IO_Addr_Strobe
.IO_Read_Strobe(mcs_rd_enable), // output IO_Read_Strobe
.IO_Write_Strobe(mcs_wr_enable), // output IO_Write_Strobe
.IO_Address(mcs_addr), // output [31 : 0] IO_Address
.IO_Byte_Enable(mcs_byte_enable), // output [3 : 0] IO_Byte_Enable
.IO_Write_Data(mcs_wr_data), // output [31 : 0] IO_Write_Data
.IO_Read_Data(mcs_rd_data), // input [31 : 0] IO_Read_Data
.IO_Ready(mcs_ready) // input IO_Ready
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFINV_8_V
`define SKY130_FD_SC_HD__BUFINV_8_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog wrapper for bufinv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__bufinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__bufinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__bufinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__bufinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFINV_8_V
|
`timescale 1ns / 100ps
`include "parameter.v"
module qrs_refinement1(q_begin_ref,s_end_ref,q_begin_l3_temp,s_end_l3_temp,q_begin_l3,s_end_l3,s_end_l3_flag,
count1,count2,clk,nReset,swindow1_full,qwindow1_full,
q_begin_l3_flag);
output [15:0] q_begin_ref,s_end_ref,q_begin_l3_temp
,s_end_l3_temp;
reg signed [15:0] q_begin_ref,s_end_ref,q_begin_l3_temp,
s_end_l3_temp;
input [15:0] q_begin_l3,s_end_l3;
input swindow1_full,qwindow1_full,s_end_l3_flag,q_begin_l3_flag;
input [3:0] count1;
input [8:0] count2;
input clk, nReset;
wire clk, nReset;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
q_begin_ref <= #20 0;
s_end_ref <= #20 0;
q_begin_l3_temp <= #20 0;
s_end_l3_temp <= #20 0;
end
else
begin
if (count1 == 2 && count2 == 1)
begin
if (qwindow1_full != 0)
begin
if (q_begin_l3_flag != 0)
q_begin_l3_temp <= #20 (q_begin_l3-(8*`rat));
else
q_begin_l3_temp <= #20 q_begin_l3_temp;
end
else
begin
q_begin_l3_temp <= #20 q_begin_l3_temp;
end
q_begin_ref <= #20 q_begin_l3_temp << `shift3;
if (swindow1_full != 0)
begin
if (s_end_l3_flag != 0)
s_end_l3_temp <= #20 (s_end_l3+(15*`rat));
else
s_end_l3_temp <= #20 s_end_l3_temp;
end
else
begin
s_end_l3_temp <= #20 s_end_l3_temp;
end
s_end_ref <= #20 s_end_l3_temp << `shift3;
end
else
begin
q_begin_ref <= #20 q_begin_ref;
s_end_ref <= #20 s_end_ref;
q_begin_l3_temp <= #20 q_begin_l3_temp;
s_end_l3_temp <= #20 s_end_l3_temp;
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:28:21 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533,
n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544,
n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566,
n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599,
n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610,
n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621,
n622, n623, n624, n625, n626, n627, n628, n629, n630, n631, n632,
n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731,
n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742,
n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753,
n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764,
n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786,
n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797,
n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808,
n809, n810, n811, n812, n813, n814, n815, n817, n818, n819, n820,
n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831,
n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842,
n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853,
n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864,
n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875,
n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n912, n913, n914, n915, n916, n917, n918, n919,
DP_OP_15J35_125_2314_n8, DP_OP_15J35_125_2314_n7,
DP_OP_15J35_125_2314_n6, DP_OP_15J35_125_2314_n5,
DP_OP_15J35_125_2314_n4, intadd_38_B_12_, intadd_38_B_11_,
intadd_38_B_10_, intadd_38_B_9_, intadd_38_B_8_, intadd_38_B_7_,
intadd_38_B_6_, intadd_38_B_5_, intadd_38_B_4_, intadd_38_B_3_,
intadd_38_B_2_, intadd_38_B_1_, intadd_38_B_0_, intadd_38_CI,
intadd_38_SUM_12_, intadd_38_SUM_11_, intadd_38_SUM_10_,
intadd_38_SUM_9_, intadd_38_SUM_8_, intadd_38_SUM_7_,
intadd_38_SUM_6_, intadd_38_SUM_5_, intadd_38_SUM_4_,
intadd_38_SUM_3_, intadd_38_SUM_2_, intadd_38_SUM_1_,
intadd_38_SUM_0_, intadd_38_n13, intadd_38_n12, intadd_38_n11,
intadd_38_n10, intadd_38_n9, intadd_38_n8, intadd_38_n7, intadd_38_n6,
intadd_38_n5, intadd_38_n4, intadd_38_n3, intadd_38_n2, intadd_38_n1,
intadd_39_A_1_, intadd_39_B_2_, intadd_39_B_1_, intadd_39_B_0_,
intadd_39_CI, intadd_39_SUM_2_, intadd_39_SUM_1_, intadd_39_SUM_0_,
intadd_39_n3, intadd_39_n2, intadd_39_n1, intadd_40_B_2_,
intadd_40_B_1_, intadd_40_B_0_, intadd_40_CI, intadd_40_SUM_2_,
intadd_40_SUM_1_, intadd_40_SUM_0_, intadd_40_n3, intadd_40_n2,
intadd_40_n1, n920, n921, n922, n923, n924, n925, n926, n927, n928,
n929, n930, n931, n932, n933, n934, n935, n936, n937, n938, n939,
n940, n941, n942, n943, n944, n945, n946, n947, n948, n949, n950,
n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961,
n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972,
n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983,
n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994,
n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1306,
n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326,
n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336,
n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346,
n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356,
n1357, n1358, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1392, n1393, n1394, n1395, n1396, n1397, n1398,
n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408,
n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418,
n1419, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480,
n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490,
n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500,
n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510,
n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520,
n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530,
n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540,
n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580,
n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590,
n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:1] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:1] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n914), .CK(clk), .RN(n1631), .QN(
n933) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n878), .CK(clk), .RN(n1632), .Q(
intAS) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n877), .CK(clk), .RN(n1634), .Q(
left_right_SHT2) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1633),
.Q(ready) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n813), .CK(clk), .RN(n1635),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n812), .CK(clk), .RN(n1638),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n811), .CK(clk), .RN(n1635),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n810), .CK(clk), .RN(n1634),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n809), .CK(clk), .RN(n943), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n808), .CK(clk), .RN(n1645), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n807), .CK(clk), .RN(n1658), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n806), .CK(clk), .RN(n1645), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n805), .CK(clk), .RN(n1658), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n804), .CK(clk), .RN(n1645), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n803), .CK(clk), .RN(n1658), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n802), .CK(clk), .RN(n1645), .Q(
final_result_ieee[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n801), .CK(clk), .RN(n1639), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n800), .CK(clk), .RN(n1636), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n799), .CK(clk), .RN(n1636), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n798), .CK(clk), .RN(n1638), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n797), .CK(clk), .RN(n1635), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n796), .CK(clk), .RN(n1639), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n795), .CK(clk), .RN(n1640), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n794), .CK(clk), .RN(n1636), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n793), .CK(clk), .RN(n1643), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n792), .CK(clk), .RN(n1634), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n791), .CK(clk), .RN(n1633), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n790), .CK(clk), .RN(n1640), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n789), .CK(clk), .RN(n1631), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n788), .CK(clk), .RN(n1637), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n787), .CK(clk), .RN(n1632), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1634), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n785), .CK(clk), .RN(n1633), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n784), .CK(clk), .RN(n1640), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n783), .CK(clk), .RN(n1631), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n782), .CK(clk), .RN(n1637), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n781), .CK(clk), .RN(n1640), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n780), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n779), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n774), .CK(clk), .RN(n1641), .QN(n934)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n773), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n772), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n771), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n770), .CK(clk), .RN(n1641), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n769), .CK(clk), .RN(n1641), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n768), .CK(clk), .RN(n1642), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n767), .CK(clk), .RN(n1642), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1642), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n764), .CK(clk), .RN(n1642), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n763), .CK(clk), .RN(n1642), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n761), .CK(clk), .RN(n1642), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n760), .CK(clk), .RN(n1642), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n759), .CK(clk), .RN(n1642), .Q(
DMP_SFG[2]), .QN(n1608) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n758), .CK(clk), .RN(n1642), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n757), .CK(clk), .RN(n1642), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n756), .CK(clk), .RN(n1646), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n755), .CK(clk), .RN(n1657), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n754), .CK(clk), .RN(n1658), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n752), .CK(clk), .RN(n1659), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n751), .CK(clk), .RN(n1646), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n749), .CK(clk), .RN(n1648), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n748), .CK(clk), .RN(n1648), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1659), .QN(n927)
);
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1654), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n745), .CK(clk), .RN(n1643), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n743), .CK(clk), .RN(n1643), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n742), .CK(clk), .RN(n943), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n740), .CK(clk), .RN(n1646), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n739), .CK(clk), .RN(n1659), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n737), .CK(clk), .RN(n1645), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n736), .CK(clk), .RN(n1659), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n735), .CK(clk), .RN(n1654), .Q(
DMP_SFG[10]), .QN(n1557) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n734), .CK(clk), .RN(n1643), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n733), .CK(clk), .RN(n943), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n732), .CK(clk), .RN(n1644), .Q(
DMP_SFG[11]), .QN(n1567) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n731), .CK(clk), .RN(n1644), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n730), .CK(clk), .RN(n1644), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n729), .CK(clk), .RN(n1644), .Q(
DMP_SFG[12]), .QN(n1566) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n728), .CK(clk), .RN(n1644), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n727), .CK(clk), .RN(n1644), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n726), .CK(clk), .RN(n1644), .Q(
DMP_SFG[13]), .QN(n1573) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n725), .CK(clk), .RN(n1644), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n724), .CK(clk), .RN(n1644), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n723), .CK(clk), .RN(n1644), .Q(
DMP_SFG[14]), .QN(n1572) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n722), .CK(clk), .RN(n1644), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n721), .CK(clk), .RN(n1644), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n720), .CK(clk), .RN(n1658), .Q(
DMP_SFG[15]), .QN(n1580) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n719), .CK(clk), .RN(n1645), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n718), .CK(clk), .RN(n1658), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n717), .CK(clk), .RN(n1645), .Q(
DMP_SFG[16]), .QN(n1603) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n716), .CK(clk), .RN(n1658), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n715), .CK(clk), .RN(n1645), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n714), .CK(clk), .RN(n1658), .Q(
DMP_SFG[17]), .QN(n1602) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n713), .CK(clk), .RN(n1645), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n712), .CK(clk), .RN(n1658), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n711), .CK(clk), .RN(n1645), .Q(
DMP_SFG[18]), .QN(n1611) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n710), .CK(clk), .RN(n1658), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n709), .CK(clk), .RN(n1645), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n708), .CK(clk), .RN(n1659), .Q(
DMP_SFG[19]), .QN(n1610) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n707), .CK(clk), .RN(n1646), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n706), .CK(clk), .RN(n1659), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n705), .CK(clk), .RN(n1646), .Q(
DMP_SFG[20]), .QN(n1624) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n704), .CK(clk), .RN(n1659), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n703), .CK(clk), .RN(n1654), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n702), .CK(clk), .RN(n1643), .Q(
DMP_SFG[21]), .QN(n1623) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n701), .CK(clk), .RN(n943), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n700), .CK(clk), .RN(n1646), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n699), .CK(clk), .RN(n1646), .Q(
DMP_SFG[22]), .QN(n1627) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n698), .CK(clk), .RN(n1644), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n697), .CK(clk), .RN(n1659), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n696), .CK(clk), .RN(n1654), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n695), .CK(clk), .RN(n1643), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n693), .CK(clk), .RN(n943), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n692), .CK(clk), .RN(n1646), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n691), .CK(clk), .RN(n1646), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n690), .CK(clk), .RN(n1659), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n688), .CK(clk), .RN(n1659), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n687), .CK(clk), .RN(n1646), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n686), .CK(clk), .RN(n1659), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n685), .CK(clk), .RN(n1641), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n683), .CK(clk), .RN(n1659), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n682), .CK(clk), .RN(n1654), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n681), .CK(clk), .RN(n1657), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n680), .CK(clk), .RN(n1653), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n678), .CK(clk), .RN(n1647), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n677), .CK(clk), .RN(n1651), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n676), .CK(clk), .RN(n1652), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n675), .CK(clk), .RN(n1632), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n673), .CK(clk), .RN(n1633), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n672), .CK(clk), .RN(n1640), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n671), .CK(clk), .RN(n1647), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n670), .CK(clk), .RN(n1651), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n668), .CK(clk), .RN(n1652), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n667), .CK(clk), .RN(n1644), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n666), .CK(clk), .RN(n1648), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n665), .CK(clk), .RN(n1648), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n663), .CK(clk), .RN(n1648), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n662), .CK(clk), .RN(n1648), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n661), .CK(clk), .RN(n1648), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n660), .CK(clk), .RN(n1648), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n658), .CK(clk), .RN(n1648), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n657), .CK(clk), .RN(n1648), .QN(
n936) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n656), .CK(clk), .RN(n1648), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n654), .CK(clk), .RN(n1648), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n652), .CK(clk), .RN(n1650), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n650), .CK(clk), .RN(n979), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n649), .CK(clk), .RN(n1655), .QN(
n941) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n648), .CK(clk), .RN(n1649), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n647), .CK(clk), .RN(n1653), .QN(
n942) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n646), .CK(clk), .RN(n1656), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n644), .CK(clk), .RN(n1650), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n642), .CK(clk), .RN(n1656), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n640), .CK(clk), .RN(n1650), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n639), .CK(clk), .RN(n1656), .QN(
n937) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n638), .CK(clk), .RN(n1655), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n636), .CK(clk), .RN(n979), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n635), .CK(clk), .RN(n1653),
.QN(n935) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n634), .CK(clk), .RN(n1649), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n632), .CK(clk), .RN(n1650), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n631), .CK(clk), .RN(n1656),
.QN(n938) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n630), .CK(clk), .RN(n1655), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n628), .CK(clk), .RN(n1652), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n627), .CK(clk), .RN(n1640),
.QN(n939) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n626), .CK(clk), .RN(n1634), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n624), .CK(clk), .RN(n1632), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n622), .CK(clk), .RN(n1647), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n620), .CK(clk), .RN(n1651), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n619), .CK(clk), .RN(n1652),
.QN(n940) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n618), .CK(clk), .RN(n1634), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n616), .CK(clk), .RN(n1650), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n614), .CK(clk), .RN(n1648), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1652), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1645), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n605), .CK(clk), .RN(n1642), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n604), .CK(clk), .RN(n1644), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n603), .CK(clk), .RN(n979), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n602), .CK(clk), .RN(n1653), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n601), .CK(clk), .RN(n1649), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n600), .CK(clk), .RN(n1650), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n599), .CK(clk), .RN(n1656), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n598), .CK(clk), .RN(n1655), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n596), .CK(clk), .RN(n979), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n595), .CK(clk), .RN(n1653), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n594), .CK(clk), .RN(n1649), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n593), .CK(clk), .RN(n1650), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n592), .CK(clk), .RN(n1656), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n591), .CK(clk), .RN(n1658), .Q(
final_result_ieee[31]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n574), .CK(clk), .RN(n1654), .Q(
LZD_output_NRM2_EW[4]), .QN(n1574) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n573), .CK(clk), .RN(n1647), .Q(
DmP_mant_SFG_SWR[1]), .QN(n966) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n571), .CK(clk), .RN(n1642), .Q(
LZD_output_NRM2_EW[2]), .QN(n1569) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n566), .CK(clk), .RN(n1646), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n564), .CK(clk), .RN(n1651), .QN(
n931) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n560), .CK(clk), .RN(n1659), .Q(
LZD_output_NRM2_EW[3]), .QN(n1575) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n559), .CK(clk), .RN(n1646), .Q(
LZD_output_NRM2_EW[1]), .QN(n1568) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n552), .CK(clk), .RN(n1652), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n551), .CK(clk), .RN(n1657), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n549), .CK(clk), .RN(n1656), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n548), .CK(clk), .RN(n1655), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n547), .CK(clk), .RN(n979), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n546), .CK(clk), .RN(n1653), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n544), .CK(clk), .RN(n1649), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n543), .CK(clk), .RN(n1650), .Q(
final_result_ieee[14]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n542), .CK(clk), .RN(n1656), .Q(
DmP_mant_SFG_SWR[5]), .QN(n971) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n541), .CK(clk), .RN(n1653), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n540), .CK(clk), .RN(n1655), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n539), .CK(clk), .RN(n979), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n538), .CK(clk), .RN(n1649), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n536), .CK(clk), .RN(n1655), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n535), .CK(clk), .RN(n979), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n533), .CK(clk), .RN(n1653), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n532), .CK(clk), .RN(n1649), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n531), .CK(clk), .RN(n1650), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n530), .CK(clk), .RN(n1656), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n529), .CK(clk), .RN(n979), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n528), .CK(clk), .RN(n1655), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n527), .CK(clk), .RN(n1653), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n526), .CK(clk), .RN(n1649), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n525), .CK(clk), .RN(n1657), .Q(
final_result_ieee[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n519), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[17]), .QN(n975) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n516), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[20]), .QN(n974) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n515), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[21]), .QN(n973) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n512), .CK(clk), .RN(n1645), .Q(
DmP_mant_SFG_SWR[24]), .QN(n972) );
CMPR32X2TS intadd_38_U14 ( .A(n1557), .B(intadd_38_B_0_), .C(intadd_38_CI),
.CO(intadd_38_n13), .S(intadd_38_SUM_0_) );
CMPR32X2TS intadd_38_U13 ( .A(n1567), .B(intadd_38_B_1_), .C(intadd_38_n13),
.CO(intadd_38_n12), .S(intadd_38_SUM_1_) );
CMPR32X2TS intadd_38_U12 ( .A(n1566), .B(intadd_38_B_2_), .C(intadd_38_n12),
.CO(intadd_38_n11), .S(intadd_38_SUM_2_) );
CMPR32X2TS intadd_38_U11 ( .A(n1573), .B(intadd_38_B_3_), .C(intadd_38_n11),
.CO(intadd_38_n10), .S(intadd_38_SUM_3_) );
CMPR32X2TS intadd_38_U10 ( .A(n1572), .B(intadd_38_B_4_), .C(intadd_38_n10),
.CO(intadd_38_n9), .S(intadd_38_SUM_4_) );
CMPR32X2TS intadd_38_U9 ( .A(n1580), .B(intadd_38_B_5_), .C(intadd_38_n9),
.CO(intadd_38_n8), .S(intadd_38_SUM_5_) );
CMPR32X2TS intadd_38_U8 ( .A(n1603), .B(intadd_38_B_6_), .C(intadd_38_n8),
.CO(intadd_38_n7), .S(intadd_38_SUM_6_) );
CMPR32X2TS intadd_38_U7 ( .A(n1602), .B(intadd_38_B_7_), .C(intadd_38_n7),
.CO(intadd_38_n6), .S(intadd_38_SUM_7_) );
CMPR32X2TS intadd_38_U6 ( .A(n1611), .B(intadd_38_B_8_), .C(intadd_38_n6),
.CO(intadd_38_n5), .S(intadd_38_SUM_8_) );
CMPR32X2TS intadd_38_U5 ( .A(n1610), .B(intadd_38_B_9_), .C(intadd_38_n5),
.CO(intadd_38_n4), .S(intadd_38_SUM_9_) );
CMPR32X2TS intadd_38_U4 ( .A(n1624), .B(intadd_38_B_10_), .C(intadd_38_n4),
.CO(intadd_38_n3), .S(intadd_38_SUM_10_) );
CMPR32X2TS intadd_38_U3 ( .A(n1623), .B(intadd_38_B_11_), .C(intadd_38_n3),
.CO(intadd_38_n2), .S(intadd_38_SUM_11_) );
CMPR32X2TS intadd_38_U2 ( .A(n1627), .B(intadd_38_B_12_), .C(intadd_38_n2),
.CO(intadd_38_n1), .S(intadd_38_SUM_12_) );
CMPR32X2TS intadd_39_U4 ( .A(n1608), .B(intadd_39_B_0_), .C(intadd_39_CI),
.CO(intadd_39_n3), .S(intadd_39_SUM_0_) );
CMPR32X2TS intadd_39_U3 ( .A(intadd_39_A_1_), .B(n964), .C(intadd_39_n3),
.CO(intadd_39_n2), .S(intadd_39_SUM_1_) );
CMPR32X2TS intadd_39_U2 ( .A(n1622), .B(intadd_39_B_2_), .C(intadd_39_n2),
.CO(intadd_39_n1), .S(intadd_39_SUM_2_) );
CMPR32X2TS intadd_40_U4 ( .A(n956), .B(intadd_40_B_0_), .C(intadd_40_CI),
.CO(intadd_40_n3), .S(intadd_40_SUM_0_) );
CMPR32X2TS intadd_40_U3 ( .A(DMP_SFG[7]), .B(intadd_40_B_1_), .C(
intadd_40_n3), .CO(intadd_40_n2), .S(intadd_40_SUM_1_) );
CMPR32X2TS intadd_40_U2 ( .A(DMP_SFG[8]), .B(intadd_40_B_2_), .C(
intadd_40_n2), .CO(intadd_40_n1), .S(intadd_40_SUM_2_) );
DFFRX1TS inst_ShiftRegister_Q_reg_4_ ( .D(n915), .CK(clk), .RN(n1632), .QN(
n1628) );
DFFSX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n967), .CK(clk), .SN(n1631), .Q(
n1660), .QN(Shift_reg_FLAGS_7[0]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1634), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1533) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n561), .CK(clk), .RN(n1640), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1604) );
DFFRX2TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n597), .CK(clk), .RN(n1650), .Q(
OP_FLAG_SFG), .QN(n1661) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n555), .CK(clk), .RN(n1647), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1558) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n568), .CK(clk), .RN(n1652), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1561) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n588), .CK(clk), .RN(n1659), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1548) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n575), .CK(clk), .RN(n1633), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1549) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n586), .CK(clk), .RN(n1654), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1606) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n853), .CK(clk), .RN(n1638),
.Q(intDY_EWSW[23]), .QN(n1597) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n854), .CK(clk), .RN(n1635),
.Q(intDY_EWSW[22]), .QN(n1538) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n855), .CK(clk), .RN(n1636),
.Q(intDY_EWSW[21]), .QN(n1586) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n856), .CK(clk), .RN(n1643),
.Q(intDY_EWSW[20]), .QN(n1594) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n862), .CK(clk), .RN(n1636),
.Q(intDY_EWSW[14]), .QN(n1592) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n863), .CK(clk), .RN(n1639),
.Q(intDY_EWSW[13]), .QN(n1585) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n864), .CK(clk), .RN(n1645),
.Q(intDY_EWSW[12]), .QN(n1591) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n858), .CK(clk), .RN(n1636),
.Q(intDY_EWSW[18]), .QN(n1599) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n859), .CK(clk), .RN(n1639),
.Q(intDY_EWSW[17]), .QN(n1583) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n868), .CK(clk), .RN(n1638), .Q(
intDY_EWSW[8]), .QN(n1588) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n873), .CK(clk), .RN(n1635), .Q(
intDY_EWSW[3]), .QN(n1582) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n875), .CK(clk), .RN(n1637), .Q(
intDY_EWSW[1]), .QN(n1587) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n882), .CK(clk), .RN(n1640),
.Q(intDX_EWSW[28]), .QN(n1598) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n884), .CK(clk), .RN(n1632),
.Q(intDX_EWSW[26]), .QN(n1545) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n885), .CK(clk), .RN(n1632),
.Q(intDX_EWSW[25]), .QN(n1544) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n886), .CK(clk), .RN(n1633),
.Q(intDX_EWSW[24]), .QN(n1618) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n894), .CK(clk), .RN(n1640),
.Q(intDX_EWSW[16]), .QN(n1559) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n903), .CK(clk), .RN(n1633), .Q(
intDX_EWSW[7]), .QN(n1530) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n904), .CK(clk), .RN(n1631), .Q(
intDX_EWSW[6]), .QN(n1560) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n905), .CK(clk), .RN(n1637), .Q(
intDX_EWSW[5]), .QN(n1555) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n906), .CK(clk), .RN(n1640), .Q(
intDX_EWSW[4]), .QN(n1529) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n815), .CK(clk), .RN(n1633), .Q(
shift_value_SHT2_EWR[4]), .QN(n1531) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n844), .CK(clk), .RN(n1631), .Q(
Data_array_SWR[25]), .QN(n1535) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n831), .CK(clk), .RN(n1638), .Q(
Data_array_SWR[12]), .QN(n1617) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n659), .CK(clk), .RN(n979), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1609) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n664), .CK(clk), .RN(n1650), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1601) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n669), .CK(clk), .RN(n1653), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1579) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n694), .CK(clk), .RN(n1659), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1556) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n562), .CK(clk), .RN(n1647), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1553) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n753), .CK(clk), .RN(n1646), .Q(
DMP_SFG[4]), .QN(n1622) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n741), .CK(clk), .RN(n1643), .Q(
DMP_SFG[8]), .QN(n1551) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n557), .CK(clk), .RN(n1651), .Q(
Raw_mant_NRM_SWR[4]), .QN(n1528) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n590), .CK(clk), .RN(n1646), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1550) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n554), .CK(clk), .RN(n1652), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1552) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n567), .CK(clk), .RN(n1650), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1554) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n585), .CK(clk), .RN(n1650), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1570) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n918), .CK(clk), .RN(
n1633), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1578) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n775), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[26]), .QN(n1620) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n776), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[25]), .QN(n1605) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n777), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[24]), .QN(n1543) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n609), .CK(clk), .RN(n1652), .Q(
DmP_EXP_EWSW[26]), .QN(n1616) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n610), .CK(clk), .RN(n1646), .Q(
DmP_EXP_EWSW[25]), .QN(n1621) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n611), .CK(clk), .RN(n1648), .Q(
DmP_EXP_EWSW[24]), .QN(n1542) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n846), .CK(clk), .RN(n1634),
.Q(intDY_EWSW[30]), .QN(n1532) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n581), .CK(clk), .RN(n1659), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1562) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n857), .CK(clk), .RN(n1639),
.Q(intDY_EWSW[19]), .QN(n1540) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n849), .CK(clk), .RN(n1631),
.Q(intDY_EWSW[27]), .QN(n1595) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n852), .CK(clk), .RN(n1658),
.Q(intDY_EWSW[24]), .QN(n1526) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n860), .CK(clk), .RN(n1636),
.Q(intDY_EWSW[16]), .QN(n1593) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n867), .CK(clk), .RN(n1643), .Q(
intDY_EWSW[9]), .QN(n1584) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n870), .CK(clk), .RN(n1636), .Q(
intDY_EWSW[6]), .QN(n1576) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n872), .CK(clk), .RN(n1639), .Q(
intDY_EWSW[4]), .QN(n1590) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n871), .CK(clk), .RN(n1645), .Q(
intDY_EWSW[5]), .QN(n1534) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n876), .CK(clk), .RN(n1632), .Q(
intDY_EWSW[0]), .QN(n1536) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n874), .CK(clk), .RN(n1634), .Q(
intDY_EWSW[2]), .QN(n1589) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n880), .CK(clk), .RN(n1633),
.Q(intDX_EWSW[30]), .QN(n1539) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n881), .CK(clk), .RN(n1637),
.Q(intDX_EWSW[29]), .QN(n1596) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n869), .CK(clk), .RN(n1638), .Q(
intDY_EWSW[7]), .QN(n1577) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n580), .CK(clk), .RN(n1643), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1525) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n847), .CK(clk), .RN(n1640),
.Q(intDY_EWSW[29]), .QN(n1564) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n578), .CK(clk), .RN(n1647), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1524) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n577), .CK(clk), .RN(n1651), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1547) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n817), .CK(clk), .RN(n1632), .Q(
shift_value_SHT2_EWR[3]), .QN(n1571) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n818), .CK(clk), .RN(n1633), .Q(
shift_value_SHT2_EWR[2]), .QN(n1563) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n829), .CK(clk), .RN(n1638), .Q(
Data_array_SWR[10]), .QN(n1607) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n826), .CK(clk), .RN(n1635), .Q(
Data_array_SWR[7]), .QN(n1615) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n839), .CK(clk), .RN(n1636), .Q(
Data_array_SWR[20]), .QN(n1625) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n825), .CK(clk), .RN(n1639), .Q(
Data_array_SWR[6]), .QN(n1614) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n841), .CK(clk), .RN(n1631), .Q(
Data_array_SWR[22]), .QN(n1612) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n833), .CK(clk), .RN(n1641), .Q(
Data_array_SWR[14]), .QN(n1541) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n840), .CK(clk), .RN(n1639), .Q(
Data_array_SWR[21]), .QN(n1600) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n842), .CK(clk), .RN(n1643), .Q(
Data_array_SWR[23]), .QN(n1613) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n828), .CK(clk), .RN(n1636), .Q(
Data_array_SWR[9]), .QN(n1619) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n907), .CK(clk), .RN(n1632), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n887), .CK(clk), .RN(n1632),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n895), .CK(clk), .RN(n1633),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n889), .CK(clk), .RN(n1631),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n897), .CK(clk), .RN(n1633),
.Q(intDX_EWSW[13]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n843), .CK(clk), .RN(n1634), .Q(
Data_array_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n582), .CK(clk), .RN(n1643), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n893), .CK(clk), .RN(n1631),
.Q(intDX_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n899), .CK(clk), .RN(n1631),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n901), .CK(clk), .RN(n1634), .Q(
intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n902), .CK(clk), .RN(n1637), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n883), .CK(clk), .RN(n1634),
.Q(intDX_EWSW[27]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n556), .CK(clk), .RN(n1651), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n832), .CK(clk), .RN(n1635), .Q(
Data_array_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n587), .CK(clk), .RN(n943), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n569), .CK(clk), .RN(n979), .Q(
Raw_mant_NRM_SWR[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n589), .CK(clk), .RN(n1654), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n583), .CK(clk), .RN(n1653), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n910), .CK(clk), .RN(n1637), .Q(
intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n892), .CK(clk), .RN(n1634),
.Q(intDX_EWSW[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n572), .CK(clk), .RN(n1633), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n834), .CK(clk), .RN(n1638), .Q(
Data_array_SWR[15]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n919), .CK(clk), .RN(
n1640), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n838), .CK(clk), .RN(n1635), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n827), .CK(clk), .RN(n1643), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n837), .CK(clk), .RN(n1636), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n835), .CK(clk), .RN(n1639), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n584), .CK(clk), .RN(n1649), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n738), .CK(clk), .RN(n979), .Q(
DMP_SFG[9]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n823), .CK(clk), .RN(n1639), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n824), .CK(clk), .RN(n1658), .Q(
Data_array_SWR[5]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n579), .CK(clk), .RN(n943), .Q(
Raw_mant_NRM_SWR[23]), .QN(n926) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n762), .CK(clk), .RN(n1642), .Q(
DMP_SFG[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n744), .CK(clk), .RN(n943), .Q(
DMP_SFG[7]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n879), .CK(clk), .RN(n1640),
.Q(intDX_EWSW[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n613), .CK(clk), .RN(n1647), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n623), .CK(clk), .RN(n1634), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n625), .CK(clk), .RN(n979), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n643), .CK(clk), .RN(n1655), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n651), .CK(clk), .RN(n979), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n621), .CK(clk), .RN(n1647), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n633), .CK(clk), .RN(n979), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n637), .CK(clk), .RN(n1655), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n641), .CK(clk), .RN(n1653), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n866), .CK(clk), .RN(n1635),
.Q(intDY_EWSW[10]), .QN(n930) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n617), .CK(clk), .RN(n1651), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n629), .CK(clk), .RN(n1653), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n615), .CK(clk), .RN(n1651), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n645), .CK(clk), .RN(n1649), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n653), .CK(clk), .RN(n1648), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n655), .CK(clk), .RN(n1648), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n750), .CK(clk), .RN(n1650), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n765), .CK(clk), .RN(n1642), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n534), .CK(clk), .RN(n1649), .Q(
DmP_mant_SFG_SWR[7]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n537), .CK(clk), .RN(n1656), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n545), .CK(clk), .RN(n1656), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n553), .CK(clk), .RN(n1644), .Q(
DmP_mant_SFG_SWR[6]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n558), .CK(clk), .RN(n1642), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n563), .CK(clk), .RN(n1632), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n576), .CK(clk), .RN(n1652), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n513), .CK(clk), .RN(n1658), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n514), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n517), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n518), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n520), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n521), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n522), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n523), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n524), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n814), .CK(clk), .RN(n1641),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n861), .CK(clk), .RN(n1635),
.Q(intDY_EWSW[15]), .QN(n1537) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n850), .CK(clk), .RN(n1638),
.Q(intDY_EWSW[26]), .QN(n1581) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n851), .CK(clk), .RN(n1658),
.Q(intDY_EWSW[25]), .QN(n1630) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n778), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n674), .CK(clk), .RN(n1646), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n679), .CK(clk), .RN(n1654), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n684), .CK(clk), .RN(n1643), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n689), .CK(clk), .RN(n943), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n821), .CK(clk), .RN(n1643), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n822), .CK(clk), .RN(n1636), .Q(
Data_array_SWR[3]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n865), .CK(clk), .RN(n1636),
.Q(intDY_EWSW[11]), .QN(n1565) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n845), .CK(clk), .RN(n1634),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n898), .CK(clk), .RN(n1640),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n890), .CK(clk), .RN(n1634),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n896), .CK(clk), .RN(n1631),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n888), .CK(clk), .RN(n1637),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n909), .CK(clk), .RN(n1632), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n908), .CK(clk), .RN(n1632), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n900), .CK(clk), .RN(n1633),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n848), .CK(clk), .RN(n1637),
.Q(intDY_EWSW[28]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n891), .CK(clk), .RN(n1640),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n836), .CK(clk), .RN(n1641), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n830), .CK(clk), .RN(n1636), .Q(
Data_array_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n570), .CK(clk), .RN(n1642), .Q(
DmP_mant_SFG_SWR[8]), .QN(n968) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n565), .CK(clk), .RN(n1657), .Q(
DmP_mant_SFG_SWR[0]), .QN(n969) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n612), .CK(clk), .RN(n1647), .Q(
DmP_EXP_EWSW[23]), .QN(n977) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n819), .CK(clk), .RN(n1631), .Q(
Data_array_SWR[0]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n820), .CK(clk), .RN(n1638), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n608), .CK(clk), .RN(n1651), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n550), .CK(clk), .RN(n1653), .Q(
DmP_mant_SFG_SWR[4]), .QN(n970) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n511), .CK(clk), .RN(n1658), .Q(
DmP_mant_SFG_SWR[25]), .QN(n976) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n916), .CK(clk), .RN(n1631), .Q(
n1527), .QN(n1626) );
ADDFX1TS DP_OP_15J35_125_2314_U8 ( .A(n1568), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J35_125_2314_n8), .CO(DP_OP_15J35_125_2314_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J35_125_2314_U7 ( .A(n1569), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J35_125_2314_n7), .CO(DP_OP_15J35_125_2314_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J35_125_2314_U6 ( .A(n1575), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J35_125_2314_n6), .CO(DP_OP_15J35_125_2314_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J35_125_2314_U5 ( .A(n1574), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J35_125_2314_n5), .CO(DP_OP_15J35_125_2314_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n912), .CK(clk), .RN(n1637), .Q(
Shift_reg_FLAGS_7[1]), .QN(n920) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n917), .CK(clk), .RN(n1640), .Q(
Shift_reg_FLAGS_7_6), .QN(n925) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n913), .CK(clk), .RN(n1632), .Q(
n1546), .QN(n1629) );
AOI222X4TS U927 ( .A0(Data_array_SWR[21]), .A1(n997), .B0(Data_array_SWR[17]), .B1(n998), .C0(Data_array_SWR[25]), .C1(n1001), .Y(n1462) );
NOR2X6TS U928 ( .A(n1082), .B(n1177), .Y(n1088) );
NOR2XLTS U929 ( .A(n1228), .B(n1345), .Y(n1213) );
AOI31XLTS U930 ( .A0(n1202), .A1(Raw_mant_NRM_SWR[8]), .A2(n1561), .B0(n1307), .Y(n1203) );
INVX3TS U931 ( .A(n1360), .Y(n923) );
CLKBUFX3TS U932 ( .A(n1324), .Y(n1325) );
CLKINVX6TS U933 ( .A(n1324), .Y(n921) );
NAND4X1TS U934 ( .A(n926), .B(n1525), .C(n1547), .D(n1524), .Y(n1301) );
CLKINVX6TS U935 ( .A(rst), .Y(n979) );
INVX3TS U936 ( .A(n1278), .Y(n1350) );
AOI222X1TS U937 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1331), .B0(n959), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1343), .C1(DmP_mant_SHT1_SW[17]), .Y(n1246) );
AOI222X1TS U938 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1331), .B0(n960), .B1(
DmP_mant_SHT1_SW[21]), .C0(n1343), .C1(DmP_mant_SHT1_SW[22]), .Y(n1249) );
INVX3TS U939 ( .A(n1335), .Y(n1331) );
INVX3TS U940 ( .A(n1335), .Y(n1353) );
CLKINVX6TS U941 ( .A(n1352), .Y(n1207) );
AND2X2TS U942 ( .A(n1208), .B(n1360), .Y(n1209) );
NOR2X1TS U943 ( .A(n1283), .B(n1315), .Y(n996) );
AO21X1TS U944 ( .A0(n1195), .A1(Raw_mant_NRM_SWR[18]), .B0(n1299), .Y(n1196)
);
AND2X4TS U945 ( .A(Shift_reg_FLAGS_7_6), .B(n1082), .Y(n1128) );
INVX4TS U946 ( .A(n1325), .Y(n922) );
NOR2X4TS U947 ( .A(n1456), .B(shift_value_SHT2_EWR[4]), .Y(n928) );
INVX4TS U948 ( .A(n1448), .Y(n997) );
AND2X4TS U949 ( .A(beg_OP), .B(n1322), .Y(n1324) );
BUFX6TS U950 ( .A(n1629), .Y(n1441) );
NOR2BX4TS U951 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1236) );
NAND2X4TS U952 ( .A(n946), .B(n1660), .Y(n980) );
NOR2X6TS U953 ( .A(shift_value_SHT2_EWR[4]), .B(n924), .Y(n998) );
INVX3TS U954 ( .A(n1427), .Y(n1001) );
BUFX6TS U955 ( .A(n1653), .Y(n1643) );
BUFX4TS U956 ( .A(n1661), .Y(n963) );
NAND2BXLTS U957 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n1031) );
NAND2BXLTS U958 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1065) );
NAND2BXLTS U959 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1019) );
NAND2BXLTS U960 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1044) );
NAND2BXLTS U961 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1040) );
NAND2BXLTS U962 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1059) );
CLKAND2X2TS U963 ( .A(n1293), .B(n1294), .Y(n1292) );
INVX2TS U964 ( .A(n944), .Y(n1456) );
OAI211XLTS U965 ( .A0(n1022), .A1(n1077), .B0(n1021), .C0(n1020), .Y(n1027)
);
NAND3XLTS U966 ( .A(n1581), .B(n1019), .C(intDX_EWSW[26]), .Y(n1021) );
NAND3BXLTS U967 ( .AN(n1063), .B(n1061), .C(n1060), .Y(n1080) );
AO22XLTS U968 ( .A0(DMP_SFG[7]), .A1(intadd_40_B_1_), .B0(intadd_40_CI),
.B1(n956), .Y(n1285) );
AOI31XLTS U969 ( .A0(n1550), .A1(Raw_mant_NRM_SWR[11]), .A2(n1199), .B0(
n1196), .Y(n1016) );
AOI222X4TS U970 ( .A0(Data_array_SWR[21]), .A1(n945), .B0(Data_array_SWR[17]), .B1(n944), .C0(Data_array_SWR[25]), .C1(n1412), .Y(n1419) );
OAI21XLTS U971 ( .A0(Raw_mant_NRM_SWR[7]), .A1(Raw_mant_NRM_SWR[6]), .B0(
n1008), .Y(n1009) );
NAND2BXLTS U972 ( .AN(n1205), .B(Raw_mant_NRM_SWR[5]), .Y(n1304) );
AOI222X1TS U973 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1353), .B0(n960), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1343), .C1(DmP_mant_SHT1_SW[3]), .Y(n1275)
);
AOI222X1TS U974 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1331), .B0(n960), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1343), .C1(DmP_mant_SHT1_SW[18]), .Y(n1259) );
AOI222X1TS U975 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1331), .B0(n960), .B1(n949),
.C0(n1343), .C1(DmP_mant_SHT1_SW[16]), .Y(n1243) );
AOI222X1TS U976 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1331), .B0(n960), .B1(n950), .C0(n1343), .C1(DmP_mant_SHT1_SW[14]), .Y(n1231) );
AOI222X1TS U977 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n1331), .B0(n960), .B1(n952), .C0(n1343), .C1(DmP_mant_SHT1_SW[10]), .Y(n1264) );
AOI222X1TS U978 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1331), .B0(
DmP_mant_SHT1_SW[20]), .B1(n1343), .C0(n960), .C1(n948), .Y(n1256) );
OAI21XLTS U979 ( .A0(n1561), .A1(n1335), .B0(n1244), .Y(n1245) );
AO22XLTS U980 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1331), .B0(n962), .B1(n1333),
.Y(n1332) );
OAI21XLTS U981 ( .A0(n1604), .A1(n1335), .B0(n1334), .Y(n1336) );
OAI21XLTS U982 ( .A0(n1528), .A1(n1345), .B0(n1237), .Y(n1238) );
AOI222X1TS U983 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n1331), .B0(n960), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1343), .C1(DmP_mant_SHT1_SW[8]), .Y(n1267)
);
AOI222X1TS U984 ( .A0(n1282), .A1(DMP_SFG[1]), .B0(n1282), .B1(n1434), .C0(
DMP_SFG[1]), .C1(n1434), .Y(intadd_39_B_0_) );
OAI21XLTS U985 ( .A0(n1554), .A1(n1345), .B0(n1340), .Y(n1341) );
OAI21XLTS U986 ( .A0(n1550), .A1(n1345), .B0(n1344), .Y(n1346) );
AOI222X1TS U987 ( .A0(n1493), .A1(n1520), .B0(Data_array_SWR[8]), .B1(n1492),
.C0(n1491), .C1(n1490), .Y(n1508) );
AOI222X1TS U988 ( .A0(n1493), .A1(n1496), .B0(n1521), .B1(Data_array_SWR[8]),
.C0(n1491), .C1(n1472), .Y(n1489) );
OAI21XLTS U989 ( .A0(n1302), .A1(n1301), .B0(n1300), .Y(n1308) );
NAND2BXLTS U990 ( .AN(n1311), .B(n986), .Y(n989) );
AOI2BB2XLTS U991 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n1350), .A0N(n1260), .A1N(
n1207), .Y(n1261) );
OAI211XLTS U992 ( .A0(n1243), .A1(n958), .B0(n1242), .C0(n1241), .Y(n836) );
AOI2BB2XLTS U993 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n1350), .A0N(n1259), .A1N(
n1207), .Y(n1241) );
AO22XLTS U994 ( .A0(n1323), .A1(Data_X[19]), .B0(n922), .B1(intDX_EWSW[19]),
.Y(n891) );
AO22XLTS U995 ( .A0(n1324), .A1(Data_Y[28]), .B0(n1328), .B1(intDY_EWSW[28]),
.Y(n848) );
AO22XLTS U996 ( .A0(n1327), .A1(Data_X[10]), .B0(n922), .B1(intDX_EWSW[10]),
.Y(n900) );
AO22XLTS U997 ( .A0(n1329), .A1(Data_Y[31]), .B0(n922), .B1(intDY_EWSW[31]),
.Y(n845) );
AO22XLTS U998 ( .A0(n961), .A1(n1403), .B0(n1507), .B1(DmP_mant_SFG_SWR[11]),
.Y(n576) );
AO22XLTS U999 ( .A0(n961), .A1(n1488), .B0(n1430), .B1(DmP_mant_SFG_SWR[2]),
.Y(n563) );
AO22XLTS U1000 ( .A0(n961), .A1(DMP_SHT2_EWSW[0]), .B0(n1430), .B1(
DMP_SFG[0]), .Y(n765) );
AO22XLTS U1001 ( .A0(n961), .A1(DMP_SHT2_EWSW[5]), .B0(n1517), .B1(
DMP_SFG[5]), .Y(n750) );
AO22XLTS U1002 ( .A0(n1527), .A1(DmP_EXP_EWSW[1]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[1]), .Y(n655) );
AO22XLTS U1003 ( .A0(n1527), .A1(DmP_EXP_EWSW[2]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[2]), .Y(n653) );
AO22XLTS U1004 ( .A0(n1527), .A1(DmP_EXP_EWSW[6]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[6]), .Y(n645) );
AO22XLTS U1005 ( .A0(n1396), .A1(DmP_EXP_EWSW[14]), .B0(n1386), .B1(
DmP_mant_SHT1_SW[14]), .Y(n629) );
AO22XLTS U1006 ( .A0(n1396), .A1(DmP_EXP_EWSW[20]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[20]), .Y(n617) );
AO22XLTS U1007 ( .A0(n1527), .A1(DmP_EXP_EWSW[8]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[8]), .Y(n641) );
AO22XLTS U1008 ( .A0(n1396), .A1(DmP_EXP_EWSW[10]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[10]), .Y(n637) );
AO22XLTS U1009 ( .A0(n1396), .A1(DmP_EXP_EWSW[12]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[12]), .Y(n633) );
AO22XLTS U1010 ( .A0(n1396), .A1(DmP_EXP_EWSW[18]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[18]), .Y(n621) );
AO22XLTS U1011 ( .A0(n1527), .A1(DmP_EXP_EWSW[3]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[3]), .Y(n651) );
AO22XLTS U1012 ( .A0(n1527), .A1(DmP_EXP_EWSW[7]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[7]), .Y(n643) );
AO22XLTS U1013 ( .A0(n1396), .A1(DmP_EXP_EWSW[22]), .B0(n1388), .B1(
DmP_mant_SHT1_SW[22]), .Y(n613) );
AO22XLTS U1014 ( .A0(n1323), .A1(Data_X[31]), .B0(n1326), .B1(intDX_EWSW[31]), .Y(n879) );
AO22XLTS U1015 ( .A0(n961), .A1(DMP_SHT2_EWSW[7]), .B0(n1517), .B1(
DMP_SFG[7]), .Y(n744) );
AO22XLTS U1016 ( .A0(n1516), .A1(DMP_SHT2_EWSW[1]), .B0(n1430), .B1(
DMP_SFG[1]), .Y(n762) );
OAI211XLTS U1017 ( .A0(n1271), .A1(n958), .B0(n1270), .C0(n1269), .Y(n824)
);
OAI211XLTS U1018 ( .A0(n1275), .A1(n958), .B0(n1274), .C0(n1273), .Y(n823)
);
AO22XLTS U1019 ( .A0(n1523), .A1(DMP_SHT2_EWSW[9]), .B0(n1517), .B1(
DMP_SFG[9]), .Y(n738) );
OAI21XLTS U1020 ( .A0(n1342), .A1(n958), .B0(n1248), .Y(n835) );
OAI21XLTS U1021 ( .A0(n1338), .A1(n1207), .B0(n1240), .Y(n837) );
OAI21XLTS U1022 ( .A0(n1348), .A1(n1207), .B0(n1281), .Y(n827) );
OAI211XLTS U1023 ( .A0(n1259), .A1(n958), .B0(n1258), .C0(n1257), .Y(n838)
);
AOI2BB2XLTS U1024 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n1350), .A0N(n1256), .A1N(
n1207), .Y(n1257) );
OAI211XLTS U1025 ( .A0(n1231), .A1(n958), .B0(n1230), .C0(n1229), .Y(n834)
);
AOI2BB2XLTS U1026 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n1350), .A0N(n1243), .A1N(
n1207), .Y(n1229) );
AO22XLTS U1027 ( .A0(n1325), .A1(Data_X[18]), .B0(n1328), .B1(intDX_EWSW[18]), .Y(n892) );
AO22XLTS U1028 ( .A0(n1329), .A1(Data_X[0]), .B0(n1328), .B1(intDX_EWSW[0]),
.Y(n910) );
AO22XLTS U1029 ( .A0(n1546), .A1(intadd_40_SUM_0_), .B0(n1629), .B1(
Raw_mant_NRM_SWR[8]), .Y(n569) );
AOI2BB2XLTS U1030 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n1350), .A0N(n1231),
.A1N(n1207), .Y(n1232) );
OAI211XLTS U1031 ( .A0(n1267), .A1(n958), .B0(n1266), .C0(n1265), .Y(n828)
);
AOI2BB2XLTS U1032 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1350), .A0N(n1264),
.A1N(n1207), .Y(n1265) );
OAI21XLTS U1033 ( .A0(n1330), .A1(n1207), .B0(n1251), .Y(n842) );
OAI211XLTS U1034 ( .A0(n1256), .A1(n958), .B0(n1235), .C0(n1234), .Y(n840)
);
AOI2BB2XLTS U1035 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n1350), .A0N(n1249), .A1N(
n1207), .Y(n1234) );
OAI211XLTS U1036 ( .A0(n1279), .A1(n1207), .B0(n1227), .C0(n1226), .Y(n825)
);
OAI211XLTS U1037 ( .A0(n1267), .A1(n1207), .B0(n1223), .C0(n1222), .Y(n826)
);
OAI21XLTS U1038 ( .A0(n1360), .A1(n1531), .B0(n1191), .Y(n815) );
AO22XLTS U1039 ( .A0(n1396), .A1(DmP_EXP_EWSW[15]), .B0(n1386), .B1(n949),
.Y(n627) );
AO22XLTS U1040 ( .A0(n1396), .A1(DmP_EXP_EWSW[13]), .B0(n1388), .B1(n950),
.Y(n631) );
AO22XLTS U1041 ( .A0(n1396), .A1(DmP_EXP_EWSW[11]), .B0(n1388), .B1(n951),
.Y(n635) );
AO22XLTS U1042 ( .A0(n1396), .A1(DmP_EXP_EWSW[9]), .B0(n1388), .B1(n952),
.Y(n639) );
AO22XLTS U1043 ( .A0(n1527), .A1(DmP_EXP_EWSW[5]), .B0(n1388), .B1(n953),
.Y(n647) );
AO22XLTS U1044 ( .A0(n1527), .A1(DmP_EXP_EWSW[4]), .B0(n1388), .B1(n947),
.Y(n649) );
AO22XLTS U1045 ( .A0(n1527), .A1(DmP_EXP_EWSW[0]), .B0(n1397), .B1(n954),
.Y(n657) );
AO22XLTS U1046 ( .A0(n961), .A1(DMP_SHT2_EWSW[6]), .B0(n1517), .B1(n956),
.Y(n747) );
AO22XLTS U1047 ( .A0(n1320), .A1(n1546), .B0(n1321), .B1(n946), .Y(n913) );
AO22XLTS U1048 ( .A0(n1321), .A1(busy), .B0(n1320), .B1(n946), .Y(n914) );
OR2X1TS U1049 ( .A(shift_value_SHT2_EWR[3]), .B(n1563), .Y(n924) );
OR2X1TS U1050 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n929) );
BUFX3TS U1051 ( .A(n923), .Y(n1358) );
OR2X1TS U1052 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n932) );
AOI211XLTS U1053 ( .A0(intDY_EWSW[16]), .A1(n1559), .B0(n1068), .C0(n1098),
.Y(n1060) );
OAI211XLTS U1054 ( .A0(n1255), .A1(n958), .B0(n1254), .C0(n1253), .Y(n820)
);
AOI31XLTS U1055 ( .A0(n1195), .A1(Raw_mant_NRM_SWR[16]), .A2(n1570), .B0(
n1194), .Y(n1204) );
NOR2BX2TS U1056 ( .AN(n1302), .B(n1301), .Y(n1195) );
BUFX4TS U1057 ( .A(n979), .Y(n1650) );
BUFX4TS U1058 ( .A(n979), .Y(n1653) );
BUFX4TS U1059 ( .A(n1651), .Y(n1644) );
BUFX4TS U1060 ( .A(n1645), .Y(n1648) );
BUFX4TS U1061 ( .A(n1652), .Y(n1642) );
BUFX4TS U1062 ( .A(n1631), .Y(n1641) );
BUFX4TS U1063 ( .A(n1631), .Y(n1658) );
BUFX4TS U1064 ( .A(n1637), .Y(n1645) );
BUFX3TS U1065 ( .A(n1626), .Y(n1387) );
BUFX4TS U1066 ( .A(n1647), .Y(n1657) );
BUFX4TS U1067 ( .A(n1638), .Y(n1640) );
BUFX3TS U1068 ( .A(n1653), .Y(n943) );
BUFX4TS U1069 ( .A(n1655), .Y(n1646) );
BUFX4TS U1070 ( .A(n1650), .Y(n1659) );
BUFX4TS U1071 ( .A(n1635), .Y(n1633) );
BUFX4TS U1072 ( .A(n1639), .Y(n1634) );
BUFX4TS U1073 ( .A(n1633), .Y(n1632) );
BUFX4TS U1074 ( .A(n1636), .Y(n1631) );
XNOR2X2TS U1075 ( .A(DMP_exp_NRM2_EW[7]), .B(n992), .Y(n1313) );
XNOR2X2TS U1076 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J35_125_2314_n4), .Y(
n1310) );
INVX2TS U1077 ( .A(n929), .Y(n944) );
INVX2TS U1078 ( .A(n924), .Y(n945) );
BUFX4TS U1079 ( .A(n1083), .Y(n1381) );
AOI222X1TS U1080 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1331), .B0(n960), .B1(
n951), .C0(n1343), .C1(DmP_mant_SHT1_SW[12]), .Y(n1260) );
INVX2TS U1081 ( .A(n933), .Y(n946) );
INVX2TS U1082 ( .A(n941), .Y(n947) );
INVX2TS U1083 ( .A(n940), .Y(n948) );
INVX2TS U1084 ( .A(n939), .Y(n949) );
INVX2TS U1085 ( .A(n938), .Y(n950) );
INVX2TS U1086 ( .A(n935), .Y(n951) );
INVX2TS U1087 ( .A(n937), .Y(n952) );
INVX2TS U1088 ( .A(n942), .Y(n953) );
INVX2TS U1089 ( .A(n936), .Y(n954) );
INVX2TS U1090 ( .A(n934), .Y(n955) );
INVX2TS U1091 ( .A(n927), .Y(n956) );
CLKINVX3TS U1092 ( .A(n1495), .Y(n1521) );
CLKINVX3TS U1093 ( .A(n1467), .Y(n1492) );
CLKINVX6TS U1094 ( .A(n1520), .Y(n1496) );
BUFX6TS U1095 ( .A(left_right_SHT2), .Y(n1520) );
BUFX4TS U1096 ( .A(n996), .Y(n1498) );
BUFX4TS U1097 ( .A(n1177), .Y(n1319) );
INVX2TS U1098 ( .A(n1209), .Y(n957) );
INVX4TS U1099 ( .A(n1209), .Y(n958) );
INVX2TS U1100 ( .A(n932), .Y(n959) );
INVX4TS U1101 ( .A(n932), .Y(n960) );
INVX4TS U1102 ( .A(n1517), .Y(n961) );
INVX2TS U1103 ( .A(n931), .Y(n962) );
OAI211XLTS U1104 ( .A0(n1264), .A1(n957), .B0(n1262), .C0(n1261), .Y(n830)
);
AOI32X1TS U1105 ( .A0(n1599), .A1(n1065), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1540), .Y(n1066) );
AOI221X1TS U1106 ( .A0(n1599), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1540), .C0(n1098), .Y(n1103) );
AOI221X1TS U1107 ( .A0(n1595), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n1598), .C0(n1091), .Y(n1095) );
AOI221X1TS U1108 ( .A0(n930), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]), .B1(
n1179), .C0(n1106), .Y(n1111) );
AOI221X1TS U1109 ( .A0(n1589), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1582), .C0(n1114), .Y(n1119) );
AOI221X1TS U1110 ( .A0(n1587), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n1583), .C0(n1097), .Y(n1104) );
AOI221X1TS U1111 ( .A0(n1538), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1597), .C0(n1100), .Y(n1101) );
AOI221X1TS U1112 ( .A0(n1592), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1184), .C0(n1108), .Y(n1109) );
OAI211X2TS U1113 ( .A0(intDX_EWSW[20]), .A1(n1594), .B0(n1073), .C0(n1059),
.Y(n1068) );
AOI221X1TS U1114 ( .A0(n1594), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1586), .C0(n1099), .Y(n1102) );
OAI211X2TS U1115 ( .A0(intDX_EWSW[12]), .A1(n1591), .B0(n1054), .C0(n1040),
.Y(n1056) );
AOI221X1TS U1116 ( .A0(n1591), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1585), .C0(n1107), .Y(n1110) );
INVX1TS U1117 ( .A(DMP_SFG[3]), .Y(intadd_39_A_1_) );
OAI211XLTS U1118 ( .A0(n1271), .A1(n1207), .B0(n1215), .C0(n1214), .Y(n822)
);
OAI211XLTS U1119 ( .A0(n1275), .A1(n1207), .B0(n1219), .C0(n1218), .Y(n821)
);
OAI31XLTS U1120 ( .A0(n1383), .A1(n1127), .A2(n1392), .B0(n1126), .Y(n768)
);
NOR2X2TS U1121 ( .A(n977), .B(DMP_EXP_EWSW[23]), .Y(n1367) );
NOR2X2TS U1122 ( .A(shift_value_SHT2_EWR[2]), .B(n1571), .Y(n1412) );
BUFX4TS U1123 ( .A(n1643), .Y(n1636) );
XNOR2X2TS U1124 ( .A(DMP_exp_NRM2_EW[6]), .B(n987), .Y(n1311) );
XNOR2X2TS U1125 ( .A(DMP_exp_NRM2_EW[0]), .B(n1289), .Y(n1309) );
OAI22X2TS U1126 ( .A0(n1600), .A1(n1456), .B0(n1535), .B1(n924), .Y(n1468)
);
AO22XLTS U1127 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n963), .B0(n1425), .B1(n971),
.Y(intadd_39_B_1_) );
INVX2TS U1128 ( .A(intadd_39_B_1_), .Y(n964) );
AOI222X4TS U1129 ( .A0(intadd_39_A_1_), .A1(n964), .B0(intadd_39_A_1_), .B1(
n1404), .C0(n964), .C1(n1404), .Y(n1405) );
AOI2BB2X2TS U1130 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n1425), .A0N(n1425),
.A1N(DmP_mant_SFG_SWR[11]), .Y(n1409) );
AOI2BB2X2TS U1131 ( .B0(DmP_mant_SFG_SWR[3]), .B1(n1425), .A0N(n1425), .A1N(
DmP_mant_SFG_SWR[3]), .Y(n1434) );
AOI2BB2X2TS U1132 ( .B0(DmP_mant_SFG_SWR[9]), .B1(n1425), .A0N(OP_FLAG_SFG),
.A1N(DmP_mant_SFG_SWR[9]), .Y(intadd_40_B_1_) );
AOI222X1TS U1133 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1353), .B0(n960), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1343), .C1(DmP_mant_SHT1_SW[7]), .Y(n1279)
);
NOR4BBX2TS U1134 ( .AN(n1193), .BN(n1016), .C(n1188), .D(n1015), .Y(n1228)
);
AOI31XLTS U1135 ( .A0(n1399), .A1(Shift_amount_SHT1_EWR[4]), .A2(n920), .B0(
n1291), .Y(n1191) );
CLKINVX6TS U1136 ( .A(n1385), .Y(n1399) );
INVX4TS U1137 ( .A(n1324), .Y(n1326) );
CLKINVX6TS U1138 ( .A(n1128), .Y(n1389) );
NAND2X4TS U1139 ( .A(n920), .B(n1385), .Y(n1360) );
BUFX4TS U1140 ( .A(n1628), .Y(n1385) );
AOI222X1TS U1141 ( .A0(n1475), .A1(n1496), .B0(n1521), .B1(Data_array_SWR[5]), .C0(n1474), .C1(n1472), .Y(n1473) );
AOI222X1TS U1142 ( .A0(n1475), .A1(n1520), .B0(Data_array_SWR[5]), .B1(n1492), .C0(n1474), .C1(n1490), .Y(n1512) );
AOI222X1TS U1143 ( .A0(n1458), .A1(n1496), .B0(n1521), .B1(Data_array_SWR[4]), .C0(n1468), .C1(n1472), .Y(n1457) );
AOI222X1TS U1144 ( .A0(n1458), .A1(n1520), .B0(Data_array_SWR[4]), .B1(n1492), .C0(n1468), .C1(n1490), .Y(n1513) );
INVX3TS U1145 ( .A(n1441), .Y(n1446) );
AOI222X4TS U1146 ( .A0(n1409), .A1(DMP_SFG[9]), .B0(n1409), .B1(n1288), .C0(
DMP_SFG[9]), .C1(n1288), .Y(intadd_38_B_0_) );
AOI222X4TS U1147 ( .A0(Data_array_SWR[20]), .A1(n997), .B0(
Data_array_SWR[24]), .B1(n1001), .C0(Data_array_SWR[16]), .C1(n998),
.Y(n1461) );
AOI222X4TS U1148 ( .A0(Data_array_SWR[20]), .A1(n945), .B0(
Data_array_SWR[24]), .B1(n1412), .C0(Data_array_SWR[16]), .C1(n944),
.Y(n1465) );
AOI22X2TS U1149 ( .A0(Data_array_SWR[22]), .A1(n945), .B0(Data_array_SWR[18]), .B1(n944), .Y(n1483) );
AOI222X4TS U1150 ( .A0(Data_array_SWR[22]), .A1(n1001), .B0(
Data_array_SWR[14]), .B1(n998), .C0(Data_array_SWR[18]), .C1(n997),
.Y(n1481) );
AOI222X4TS U1151 ( .A0(Data_array_SWR[23]), .A1(n1001), .B0(
Data_array_SWR[19]), .B1(n997), .C0(Data_array_SWR[15]), .C1(n998),
.Y(n1477) );
AOI22X2TS U1152 ( .A0(Data_array_SWR[23]), .A1(n945), .B0(Data_array_SWR[19]), .B1(n944), .Y(n1453) );
NOR2X2TS U1153 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1578), .Y(n1318) );
OAI21X2TS U1154 ( .A0(intDX_EWSW[18]), .A1(n1599), .B0(n1065), .Y(n1098) );
AOI32X1TS U1155 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1012), .A2(n1011), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1012), .Y(n1013) );
NOR3X1TS U1156 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1302) );
NOR2X2TS U1157 ( .A(Raw_mant_NRM_SWR[13]), .B(n1006), .Y(n1199) );
CLKINVX3TS U1158 ( .A(Shift_reg_FLAGS_7[0]), .Y(n965) );
AOI221X1TS U1159 ( .A0(n1588), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1576), .C0(n1116), .Y(n1117) );
AOI222X1TS U1160 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1331), .B0(n960), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1343), .C1(n947), .Y(n1271) );
AO22XLTS U1161 ( .A0(n1321), .A1(n920), .B0(n965), .B1(n1320), .Y(n967) );
NOR2XLTS U1162 ( .A(n1565), .B(intDX_EWSW[11]), .Y(n1042) );
OAI21XLTS U1163 ( .A0(intDX_EWSW[15]), .A1(n1537), .B0(intDX_EWSW[14]), .Y(
n1050) );
NOR2XLTS U1164 ( .A(n1063), .B(intDY_EWSW[16]), .Y(n1064) );
OAI21XLTS U1165 ( .A0(intDX_EWSW[21]), .A1(n1586), .B0(intDX_EWSW[20]), .Y(
n1062) );
OAI21XLTS U1166 ( .A0(DmP_EXP_EWSW[25]), .A1(n1605), .B0(n1371), .Y(n1368)
);
OAI21XLTS U1167 ( .A0(n1548), .A1(n1345), .B0(n1276), .Y(n1277) );
OAI21XLTS U1168 ( .A0(n1584), .A1(n1163), .B0(n1155), .Y(n640) );
OAI21XLTS U1169 ( .A0(n1589), .A1(n1389), .B0(n1156), .Y(n654) );
OAI21XLTS U1170 ( .A0(n1539), .A1(n1389), .B0(n1145), .Y(n771) );
OAI21XLTS U1171 ( .A0(n1585), .A1(n1183), .B0(n1180), .Y(n788) );
OAI211XLTS U1172 ( .A0(n1260), .A1(n957), .B0(n1233), .C0(n1232), .Y(n832)
);
NOR2XLTS U1173 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n978) );
AOI32X4TS U1174 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n978), .B1(n1578), .Y(n1321)
);
INVX2TS U1175 ( .A(n1321), .Y(n1320) );
INVX4TS U1176 ( .A(n1385), .Y(busy) );
BUFX3TS U1177 ( .A(n1643), .Y(n1651) );
BUFX3TS U1178 ( .A(n979), .Y(n1655) );
BUFX3TS U1179 ( .A(n943), .Y(n1647) );
BUFX3TS U1180 ( .A(n979), .Y(n1649) );
BUFX3TS U1181 ( .A(n943), .Y(n1635) );
BUFX3TS U1182 ( .A(n1654), .Y(n1652) );
BUFX3TS U1183 ( .A(n1654), .Y(n1639) );
BUFX3TS U1184 ( .A(n979), .Y(n1656) );
BUFX3TS U1185 ( .A(n943), .Y(n1638) );
BUFX3TS U1186 ( .A(n1650), .Y(n1654) );
BUFX3TS U1187 ( .A(n1636), .Y(n1637) );
AO22XLTS U1188 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n920),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n601) );
AO22XLTS U1189 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n920),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n592) );
BUFX3TS U1190 ( .A(n980), .Y(n1517) );
BUFX3TS U1191 ( .A(n1517), .Y(n1430) );
INVX4TS U1192 ( .A(n980), .Y(n1510) );
AO22XLTS U1193 ( .A0(n1430), .A1(DMP_SFG[20]), .B0(n1510), .B1(
DMP_SHT2_EWSW[20]), .Y(n705) );
AO22XLTS U1194 ( .A0(n1430), .A1(DMP_SFG[21]), .B0(n1510), .B1(
DMP_SHT2_EWSW[21]), .Y(n702) );
AO22XLTS U1195 ( .A0(n1430), .A1(DMP_SFG[18]), .B0(n1510), .B1(
DMP_SHT2_EWSW[18]), .Y(n711) );
AO22XLTS U1196 ( .A0(n1430), .A1(DMP_SFG[17]), .B0(n1510), .B1(
DMP_SHT2_EWSW[17]), .Y(n714) );
AO22XLTS U1197 ( .A0(n1430), .A1(DMP_SFG[16]), .B0(n1510), .B1(
DMP_SHT2_EWSW[16]), .Y(n717) );
AO22XLTS U1198 ( .A0(n1430), .A1(DMP_SFG[8]), .B0(n1510), .B1(
DMP_SHT2_EWSW[8]), .Y(n741) );
AO22XLTS U1199 ( .A0(n1441), .A1(Raw_mant_NRM_SWR[9]), .B0(n1546), .B1(
intadd_40_SUM_1_), .Y(n568) );
AO22XLTS U1200 ( .A0(n1441), .A1(Raw_mant_NRM_SWR[10]), .B0(n1546), .B1(
intadd_40_SUM_2_), .Y(n567) );
INVX2TS U1201 ( .A(DP_OP_15J35_125_2314_n4), .Y(n981) );
NAND2X1TS U1202 ( .A(n1579), .B(n981), .Y(n987) );
INVX1TS U1203 ( .A(LZD_output_NRM2_EW[0]), .Y(n1289) );
NOR2XLTS U1204 ( .A(n1309), .B(exp_rslt_NRM2_EW1[1]), .Y(n984) );
INVX2TS U1205 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n983) );
INVX2TS U1206 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n982) );
NAND4BXLTS U1207 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n984), .C(n983), .D(n982),
.Y(n985) );
NOR2XLTS U1208 ( .A(n985), .B(n1310), .Y(n986) );
INVX2TS U1209 ( .A(n987), .Y(n988) );
NAND2X1TS U1210 ( .A(n1601), .B(n988), .Y(n992) );
OR2X1TS U1211 ( .A(n989), .B(n1313), .Y(n1393) );
INVX2TS U1212 ( .A(n1393), .Y(n1283) );
AND4X1TS U1213 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1309), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n990) );
AND4X1TS U1214 ( .A(n1311), .B(n1310), .C(exp_rslt_NRM2_EW1[4]), .D(n990),
.Y(n991) );
CLKAND2X2TS U1215 ( .A(n1313), .B(n991), .Y(n995) );
INVX2TS U1216 ( .A(n992), .Y(n993) );
CLKAND2X2TS U1217 ( .A(n1609), .B(n993), .Y(n994) );
OAI2BB1X1TS U1218 ( .A0N(n995), .A1N(n994), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1315) );
NAND2X2TS U1219 ( .A(n1496), .B(n928), .Y(n1495) );
NOR2X2TS U1220 ( .A(n1531), .B(n1456), .Y(n1450) );
NAND3X1TS U1221 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n1531), .Y(n1427) );
NAND2X1TS U1222 ( .A(n1531), .B(n1412), .Y(n1448) );
AOI22X1TS U1223 ( .A0(Data_array_SWR[17]), .A1(n997), .B0(Data_array_SWR[13]), .B1(n998), .Y(n999) );
OAI21XLTS U1224 ( .A0(n1600), .A1(n1427), .B0(n999), .Y(n1000) );
AOI21X1TS U1225 ( .A0(Data_array_SWR[25]), .A1(n1450), .B0(n1000), .Y(n1464)
);
NOR2X2TS U1226 ( .A(shift_value_SHT2_EWR[4]), .B(n1496), .Y(n1472) );
INVX2TS U1227 ( .A(n1472), .Y(n1484) );
OAI222X1TS U1228 ( .A0(n1495), .A1(n1619), .B0(n1520), .B1(n1464), .C0(n1484), .C1(n1465), .Y(n1463) );
AO22XLTS U1229 ( .A0(n1498), .A1(n1463), .B0(final_result_ieee[7]), .B1(
n1660), .Y(n544) );
NAND2X2TS U1230 ( .A(n1520), .B(n928), .Y(n1467) );
NOR2X2TS U1231 ( .A(shift_value_SHT2_EWR[4]), .B(n1520), .Y(n1490) );
INVX2TS U1232 ( .A(n1490), .Y(n1466) );
AOI22X1TS U1233 ( .A0(Data_array_SWR[19]), .A1(n1001), .B0(
Data_array_SWR[11]), .B1(n998), .Y(n1002) );
OAI2BB1X1TS U1234 ( .A0N(Data_array_SWR[15]), .A1N(n997), .B0(n1002), .Y(
n1003) );
AOI21X1TS U1235 ( .A0(Data_array_SWR[23]), .A1(n1450), .B0(n1003), .Y(n1485)
);
OAI222X1TS U1236 ( .A0(n1467), .A1(n1615), .B0(n1466), .B1(n1483), .C0(n1496), .C1(n1485), .Y(n1509) );
AO22XLTS U1237 ( .A0(n1498), .A1(n1509), .B0(final_result_ieee[16]), .B1(
n1660), .Y(n532) );
AOI22X1TS U1238 ( .A0(Data_array_SWR[22]), .A1(n997), .B0(Data_array_SWR[18]), .B1(n998), .Y(n1478) );
AOI22X1TS U1239 ( .A0(Data_array_SWR[14]), .A1(n1492), .B0(
Data_array_SWR[11]), .B1(n1521), .Y(n1004) );
OAI221X1TS U1240 ( .A0(n1520), .A1(n1477), .B0(n1496), .B1(n1478), .C0(n1004), .Y(n1403) );
AO22XLTS U1241 ( .A0(n1498), .A1(n1403), .B0(final_result_ieee[9]), .B1(
n1660), .Y(n539) );
AOI22X1TS U1242 ( .A0(Data_array_SWR[23]), .A1(n997), .B0(Data_array_SWR[19]), .B1(n998), .Y(n1480) );
AOI22X1TS U1243 ( .A0(Data_array_SWR[10]), .A1(n1492), .B0(
Data_array_SWR[15]), .B1(n1521), .Y(n1005) );
OAI221X1TS U1244 ( .A0(n1520), .A1(n1480), .B0(n1496), .B1(n1481), .C0(n1005), .Y(n1504) );
AO22XLTS U1245 ( .A0(n1498), .A1(n1504), .B0(final_result_ieee[13]), .B1(
n1660), .Y(n535) );
NOR2BX1TS U1246 ( .AN(n1195), .B(Raw_mant_NRM_SWR[18]), .Y(n1293) );
NOR3X1TS U1247 ( .A(Raw_mant_NRM_SWR[15]), .B(Raw_mant_NRM_SWR[17]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1294) );
NAND2X1TS U1248 ( .A(Raw_mant_NRM_SWR[14]), .B(n1292), .Y(n1193) );
NAND2X1TS U1249 ( .A(n1292), .B(n1548), .Y(n1006) );
NAND2X1TS U1250 ( .A(n1199), .B(n1549), .Y(n1007) );
NOR3X1TS U1251 ( .A(Raw_mant_NRM_SWR[12]), .B(n1554), .C(n1007), .Y(n1299)
);
NOR2XLTS U1252 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .Y(n1010)
);
NOR2X1TS U1253 ( .A(Raw_mant_NRM_SWR[10]), .B(n1007), .Y(n1202) );
NAND2X1TS U1254 ( .A(n1202), .B(n1550), .Y(n1185) );
NOR3X1TS U1255 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1185),
.Y(n1008) );
NAND2X1TS U1256 ( .A(n1008), .B(n1552), .Y(n1205) );
NOR3X2TS U1257 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .C(n1205),
.Y(n1198) );
NAND2X1TS U1258 ( .A(n1198), .B(n1528), .Y(n1303) );
OAI21X1TS U1259 ( .A0(n1010), .A1(n1303), .B0(n1009), .Y(n1188) );
NOR2XLTS U1260 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1014) );
NOR2X1TS U1261 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1012) );
NOR2XLTS U1262 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1011) );
AOI211X1TS U1263 ( .A0(n1014), .A1(n1013), .B0(Raw_mant_NRM_SWR[25]), .C0(
Raw_mant_NRM_SWR[24]), .Y(n1015) );
NOR2X1TS U1264 ( .A(n1228), .B(n920), .Y(n1206) );
AO21XLTS U1265 ( .A0(LZD_output_NRM2_EW[1]), .A1(n920), .B0(n1206), .Y(n559)
);
OAI21XLTS U1266 ( .A0(n1399), .A1(n1496), .B0(n920), .Y(n877) );
AOI2BB2X1TS U1267 ( .B0(DmP_mant_SFG_SWR[6]), .B1(n1661), .A0N(n963), .A1N(
DmP_mant_SFG_SWR[6]), .Y(intadd_39_B_2_) );
AOI2BB2XLTS U1268 ( .B0(beg_OP), .B1(n1533), .A0N(n1533), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1017) );
NAND3XLTS U1269 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1533), .C(
n1578), .Y(n1316) );
OAI21XLTS U1270 ( .A0(n1318), .A1(n1017), .B0(n1316), .Y(n918) );
NOR2X1TS U1271 ( .A(n1630), .B(intDX_EWSW[25]), .Y(n1076) );
NOR2XLTS U1272 ( .A(n1076), .B(intDY_EWSW[24]), .Y(n1018) );
AOI22X1TS U1273 ( .A0(intDX_EWSW[25]), .A1(n1630), .B0(intDX_EWSW[24]), .B1(
n1018), .Y(n1022) );
OAI21X1TS U1274 ( .A0(intDX_EWSW[26]), .A1(n1581), .B0(n1019), .Y(n1077) );
NAND2BXLTS U1275 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1020) );
NOR2X1TS U1276 ( .A(n1532), .B(intDX_EWSW[30]), .Y(n1025) );
NOR2X1TS U1277 ( .A(n1564), .B(intDX_EWSW[29]), .Y(n1023) );
AOI211X1TS U1278 ( .A0(intDY_EWSW[28]), .A1(n1598), .B0(n1025), .C0(n1023),
.Y(n1075) );
NOR3X1TS U1279 ( .A(n1598), .B(n1023), .C(intDY_EWSW[28]), .Y(n1024) );
AOI221X1TS U1280 ( .A0(intDX_EWSW[30]), .A1(n1532), .B0(intDX_EWSW[29]),
.B1(n1564), .C0(n1024), .Y(n1026) );
AOI2BB2X1TS U1281 ( .B0(n1027), .B1(n1075), .A0N(n1026), .A1N(n1025), .Y(
n1081) );
NOR2X1TS U1282 ( .A(n1583), .B(intDX_EWSW[17]), .Y(n1063) );
INVX2TS U1283 ( .A(intDY_EWSW[11]), .Y(n1179) );
OAI22X1TS U1284 ( .A0(n930), .A1(intDX_EWSW[10]), .B0(n1179), .B1(
intDX_EWSW[11]), .Y(n1106) );
INVX2TS U1285 ( .A(n1106), .Y(n1047) );
OAI211XLTS U1286 ( .A0(intDX_EWSW[8]), .A1(n1588), .B0(n1044), .C0(n1047),
.Y(n1058) );
OAI2BB1X1TS U1287 ( .A0N(n1555), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1028) );
OAI22X1TS U1288 ( .A0(intDY_EWSW[4]), .A1(n1028), .B0(n1555), .B1(
intDY_EWSW[5]), .Y(n1039) );
OAI2BB1X1TS U1289 ( .A0N(n1530), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1029) );
OAI22X1TS U1290 ( .A0(intDY_EWSW[6]), .A1(n1029), .B0(n1530), .B1(
intDY_EWSW[7]), .Y(n1038) );
OAI21XLTS U1291 ( .A0(intDX_EWSW[1]), .A1(n1587), .B0(intDX_EWSW[0]), .Y(
n1030) );
OAI2BB2XLTS U1292 ( .B0(intDY_EWSW[0]), .B1(n1030), .A0N(intDX_EWSW[1]),
.A1N(n1587), .Y(n1032) );
OAI211XLTS U1293 ( .A0(n1582), .A1(intDX_EWSW[3]), .B0(n1032), .C0(n1031),
.Y(n1035) );
OAI21XLTS U1294 ( .A0(intDX_EWSW[3]), .A1(n1582), .B0(intDX_EWSW[2]), .Y(
n1033) );
AOI2BB2XLTS U1295 ( .B0(intDX_EWSW[3]), .B1(n1582), .A0N(intDY_EWSW[2]),
.A1N(n1033), .Y(n1034) );
AOI222X1TS U1296 ( .A0(intDY_EWSW[4]), .A1(n1529), .B0(n1035), .B1(n1034),
.C0(intDY_EWSW[5]), .C1(n1555), .Y(n1037) );
AOI22X1TS U1297 ( .A0(intDY_EWSW[7]), .A1(n1530), .B0(intDY_EWSW[6]), .B1(
n1560), .Y(n1036) );
OAI32X1TS U1298 ( .A0(n1039), .A1(n1038), .A2(n1037), .B0(n1036), .B1(n1038),
.Y(n1057) );
OA22X1TS U1299 ( .A0(n1592), .A1(intDX_EWSW[14]), .B0(n1537), .B1(
intDX_EWSW[15]), .Y(n1054) );
OAI21XLTS U1300 ( .A0(intDX_EWSW[13]), .A1(n1585), .B0(intDX_EWSW[12]), .Y(
n1041) );
OAI2BB2XLTS U1301 ( .B0(intDY_EWSW[12]), .B1(n1041), .A0N(intDX_EWSW[13]),
.A1N(n1585), .Y(n1053) );
NOR2XLTS U1302 ( .A(n1042), .B(intDY_EWSW[10]), .Y(n1043) );
AOI22X1TS U1303 ( .A0(intDX_EWSW[11]), .A1(n1565), .B0(intDX_EWSW[10]), .B1(
n1043), .Y(n1049) );
NAND2BXLTS U1304 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1046) );
NAND3XLTS U1305 ( .A(n1588), .B(n1044), .C(intDX_EWSW[8]), .Y(n1045) );
AOI21X1TS U1306 ( .A0(n1046), .A1(n1045), .B0(n1056), .Y(n1048) );
OAI2BB2XLTS U1307 ( .B0(n1049), .B1(n1056), .A0N(n1048), .A1N(n1047), .Y(
n1052) );
INVX2TS U1308 ( .A(intDY_EWSW[15]), .Y(n1184) );
OAI2BB2XLTS U1309 ( .B0(intDY_EWSW[14]), .B1(n1050), .A0N(intDX_EWSW[15]),
.A1N(n1184), .Y(n1051) );
AOI211X1TS U1310 ( .A0(n1054), .A1(n1053), .B0(n1052), .C0(n1051), .Y(n1055)
);
OAI31X1TS U1311 ( .A0(n1058), .A1(n1057), .A2(n1056), .B0(n1055), .Y(n1061)
);
OA22X1TS U1312 ( .A0(n1538), .A1(intDX_EWSW[22]), .B0(n1597), .B1(
intDX_EWSW[23]), .Y(n1073) );
OAI2BB2XLTS U1313 ( .B0(intDY_EWSW[20]), .B1(n1062), .A0N(intDX_EWSW[21]),
.A1N(n1586), .Y(n1072) );
AOI22X1TS U1314 ( .A0(intDX_EWSW[17]), .A1(n1583), .B0(intDX_EWSW[16]), .B1(
n1064), .Y(n1067) );
OAI32X1TS U1315 ( .A0(n1098), .A1(n1068), .A2(n1067), .B0(n1066), .B1(n1068),
.Y(n1071) );
OAI21XLTS U1316 ( .A0(intDX_EWSW[23]), .A1(n1597), .B0(intDX_EWSW[22]), .Y(
n1069) );
OAI2BB2XLTS U1317 ( .B0(intDY_EWSW[22]), .B1(n1069), .A0N(intDX_EWSW[23]),
.A1N(n1597), .Y(n1070) );
AOI211X1TS U1318 ( .A0(n1073), .A1(n1072), .B0(n1071), .C0(n1070), .Y(n1079)
);
NAND2BXLTS U1319 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1074) );
NAND4BBX1TS U1320 ( .AN(n1077), .BN(n1076), .C(n1075), .D(n1074), .Y(n1078)
);
AOI32X1TS U1321 ( .A0(n1081), .A1(n1080), .A2(n1079), .B0(n1078), .B1(n1081),
.Y(n1082) );
INVX2TS U1322 ( .A(Shift_reg_FLAGS_7_6), .Y(n1083) );
INVX4TS U1323 ( .A(n1088), .Y(n1183) );
BUFX4TS U1324 ( .A(n1083), .Y(n1177) );
AOI22X1TS U1325 ( .A0(intDX_EWSW[4]), .A1(n1128), .B0(DMP_EXP_EWSW[4]), .B1(
n1177), .Y(n1084) );
OAI21XLTS U1326 ( .A0(n1590), .A1(n1183), .B0(n1084), .Y(n797) );
AOI22X1TS U1327 ( .A0(intDX_EWSW[6]), .A1(n1128), .B0(DMP_EXP_EWSW[6]), .B1(
n1177), .Y(n1085) );
OAI21XLTS U1328 ( .A0(n1576), .A1(n1183), .B0(n1085), .Y(n795) );
AOI22X1TS U1329 ( .A0(intDX_EWSW[7]), .A1(n1128), .B0(DMP_EXP_EWSW[7]), .B1(
n1381), .Y(n1086) );
OAI21XLTS U1330 ( .A0(n1577), .A1(n1183), .B0(n1086), .Y(n794) );
AOI22X1TS U1331 ( .A0(intDX_EWSW[5]), .A1(n1128), .B0(DMP_EXP_EWSW[5]), .B1(
n1177), .Y(n1087) );
OAI21XLTS U1332 ( .A0(n1534), .A1(n1183), .B0(n1087), .Y(n796) );
INVX3TS U1333 ( .A(n1128), .Y(n1163) );
AOI22X1TS U1334 ( .A0(intDX_EWSW[16]), .A1(n1088), .B0(DmP_EXP_EWSW[16]),
.B1(n1319), .Y(n1089) );
OAI21XLTS U1335 ( .A0(n1593), .A1(n1163), .B0(n1089), .Y(n626) );
INVX2TS U1336 ( .A(intDY_EWSW[26]), .Y(n1390) );
OAI22X1TS U1337 ( .A0(n1630), .A1(intDX_EWSW[25]), .B0(n1390), .B1(
intDX_EWSW[26]), .Y(n1090) );
AOI221X1TS U1338 ( .A0(n1630), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n1390), .C0(n1090), .Y(n1096) );
OAI22X1TS U1339 ( .A0(n1595), .A1(intDX_EWSW[27]), .B0(n1598), .B1(
intDY_EWSW[28]), .Y(n1091) );
OAI22X1TS U1340 ( .A0(n1596), .A1(intDY_EWSW[29]), .B0(n1539), .B1(
intDY_EWSW[30]), .Y(n1092) );
AOI221X1TS U1341 ( .A0(n1596), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n1539), .C0(n1092), .Y(n1094) );
AOI2BB2XLTS U1342 ( .B0(intDX_EWSW[7]), .B1(n1577), .A0N(n1577), .A1N(
intDX_EWSW[7]), .Y(n1093) );
NAND4XLTS U1343 ( .A(n1096), .B(n1095), .C(n1094), .D(n1093), .Y(n1124) );
OAI22X1TS U1344 ( .A0(n1587), .A1(intDX_EWSW[1]), .B0(n1583), .B1(
intDX_EWSW[17]), .Y(n1097) );
OAI22X1TS U1345 ( .A0(n1594), .A1(intDX_EWSW[20]), .B0(n1586), .B1(
intDX_EWSW[21]), .Y(n1099) );
OAI22X1TS U1346 ( .A0(n1538), .A1(intDX_EWSW[22]), .B0(n1597), .B1(
intDX_EWSW[23]), .Y(n1100) );
NAND4XLTS U1347 ( .A(n1104), .B(n1103), .C(n1102), .D(n1101), .Y(n1123) );
OAI22X1TS U1348 ( .A0(n1526), .A1(intDX_EWSW[24]), .B0(n1584), .B1(
intDX_EWSW[9]), .Y(n1105) );
AOI221X1TS U1349 ( .A0(n1526), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1584), .C0(n1105), .Y(n1112) );
OAI22X1TS U1350 ( .A0(n1591), .A1(intDX_EWSW[12]), .B0(n1585), .B1(
intDX_EWSW[13]), .Y(n1107) );
OAI22X1TS U1351 ( .A0(n1592), .A1(intDX_EWSW[14]), .B0(n1184), .B1(
intDX_EWSW[15]), .Y(n1108) );
NAND4XLTS U1352 ( .A(n1112), .B(n1111), .C(n1110), .D(n1109), .Y(n1122) );
OAI22X1TS U1353 ( .A0(n1593), .A1(intDX_EWSW[16]), .B0(n1536), .B1(
intDX_EWSW[0]), .Y(n1113) );
AOI221X1TS U1354 ( .A0(n1593), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1536), .C0(n1113), .Y(n1120) );
OAI22X1TS U1355 ( .A0(n1589), .A1(intDX_EWSW[2]), .B0(n1582), .B1(
intDX_EWSW[3]), .Y(n1114) );
OAI22X1TS U1356 ( .A0(n1590), .A1(intDX_EWSW[4]), .B0(n1534), .B1(
intDX_EWSW[5]), .Y(n1115) );
AOI221X1TS U1357 ( .A0(n1590), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1534), .C0(n1115), .Y(n1118) );
OAI22X1TS U1358 ( .A0(n1588), .A1(intDX_EWSW[8]), .B0(n1576), .B1(
intDX_EWSW[6]), .Y(n1116) );
NAND4XLTS U1359 ( .A(n1120), .B(n1119), .C(n1118), .D(n1117), .Y(n1121) );
NOR4X1TS U1360 ( .A(n1124), .B(n1123), .C(n1122), .D(n1121), .Y(n1383) );
CLKXOR2X2TS U1361 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1380) );
INVX2TS U1362 ( .A(n1380), .Y(n1127) );
INVX4TS U1363 ( .A(n1088), .Y(n1392) );
OAI21XLTS U1364 ( .A0(n1127), .A1(n1177), .B0(n1163), .Y(n1125) );
AOI22X1TS U1365 ( .A0(intDX_EWSW[31]), .A1(n1125), .B0(SIGN_FLAG_EXP), .B1(
n925), .Y(n1126) );
AOI22X1TS U1366 ( .A0(intDY_EWSW[28]), .A1(n1088), .B0(DMP_EXP_EWSW[28]),
.B1(n1177), .Y(n1129) );
OAI21XLTS U1367 ( .A0(n1598), .A1(n1389), .B0(n1129), .Y(n773) );
AOI22X1TS U1368 ( .A0(intDX_EWSW[19]), .A1(n1088), .B0(DmP_EXP_EWSW[19]),
.B1(n1319), .Y(n1130) );
OAI21XLTS U1369 ( .A0(n1540), .A1(n1389), .B0(n1130), .Y(n620) );
AOI22X1TS U1370 ( .A0(intDX_EWSW[22]), .A1(n1088), .B0(DmP_EXP_EWSW[22]),
.B1(n1319), .Y(n1131) );
OAI21XLTS U1371 ( .A0(n1538), .A1(n1389), .B0(n1131), .Y(n614) );
AOI22X1TS U1372 ( .A0(intDX_EWSW[17]), .A1(n1088), .B0(DmP_EXP_EWSW[17]),
.B1(n1319), .Y(n1132) );
OAI21XLTS U1373 ( .A0(n1583), .A1(n1389), .B0(n1132), .Y(n624) );
AOI22X1TS U1374 ( .A0(intDX_EWSW[20]), .A1(n1088), .B0(DmP_EXP_EWSW[20]),
.B1(n1319), .Y(n1133) );
OAI21XLTS U1375 ( .A0(n1594), .A1(n1389), .B0(n1133), .Y(n618) );
AOI22X1TS U1376 ( .A0(intDX_EWSW[14]), .A1(n1088), .B0(DmP_EXP_EWSW[14]),
.B1(n1083), .Y(n1134) );
OAI21XLTS U1377 ( .A0(n1592), .A1(n1163), .B0(n1134), .Y(n630) );
AOI22X1TS U1378 ( .A0(intDX_EWSW[21]), .A1(n1088), .B0(DmP_EXP_EWSW[21]),
.B1(n1319), .Y(n1135) );
OAI21XLTS U1379 ( .A0(n1586), .A1(n1389), .B0(n1135), .Y(n616) );
AOI22X1TS U1380 ( .A0(intDX_EWSW[13]), .A1(n1088), .B0(DmP_EXP_EWSW[13]),
.B1(n1319), .Y(n1136) );
OAI21XLTS U1381 ( .A0(n1585), .A1(n1163), .B0(n1136), .Y(n632) );
AOI22X1TS U1382 ( .A0(intDX_EWSW[15]), .A1(n1088), .B0(DmP_EXP_EWSW[15]),
.B1(n1319), .Y(n1138) );
OAI21XLTS U1383 ( .A0(n1184), .A1(n1163), .B0(n1138), .Y(n628) );
AOI22X1TS U1384 ( .A0(intDX_EWSW[0]), .A1(n1128), .B0(DMP_EXP_EWSW[0]), .B1(
n1381), .Y(n1139) );
OAI21XLTS U1385 ( .A0(n1536), .A1(n1392), .B0(n1139), .Y(n801) );
AOI22X1TS U1386 ( .A0(intDX_EWSW[9]), .A1(n1128), .B0(DMP_EXP_EWSW[9]), .B1(
n1177), .Y(n1140) );
OAI21XLTS U1387 ( .A0(n1584), .A1(n1183), .B0(n1140), .Y(n792) );
AOI22X1TS U1388 ( .A0(intDX_EWSW[1]), .A1(n1128), .B0(DMP_EXP_EWSW[1]), .B1(
n1381), .Y(n1141) );
OAI21XLTS U1389 ( .A0(n1587), .A1(n1183), .B0(n1141), .Y(n800) );
AOI22X1TS U1390 ( .A0(intDX_EWSW[2]), .A1(n1128), .B0(DMP_EXP_EWSW[2]), .B1(
n1177), .Y(n1142) );
OAI21XLTS U1391 ( .A0(n1589), .A1(n1183), .B0(n1142), .Y(n799) );
AOI22X1TS U1392 ( .A0(intDX_EWSW[8]), .A1(n1128), .B0(DMP_EXP_EWSW[8]), .B1(
n1319), .Y(n1143) );
OAI21XLTS U1393 ( .A0(n1588), .A1(n1183), .B0(n1143), .Y(n793) );
AOI22X1TS U1394 ( .A0(intDX_EWSW[3]), .A1(n1128), .B0(DMP_EXP_EWSW[3]), .B1(
n1381), .Y(n1144) );
OAI21XLTS U1395 ( .A0(n1582), .A1(n1392), .B0(n1144), .Y(n798) );
BUFX4TS U1396 ( .A(n1088), .Y(n1161) );
AOI22X1TS U1397 ( .A0(intDY_EWSW[30]), .A1(n1161), .B0(DMP_EXP_EWSW[30]),
.B1(n1177), .Y(n1145) );
AOI22X1TS U1398 ( .A0(intDY_EWSW[29]), .A1(n1161), .B0(DMP_EXP_EWSW[29]),
.B1(n1177), .Y(n1146) );
OAI21XLTS U1399 ( .A0(n1596), .A1(n1389), .B0(n1146), .Y(n772) );
AOI22X1TS U1400 ( .A0(intDX_EWSW[4]), .A1(n1161), .B0(DmP_EXP_EWSW[4]), .B1(
n1381), .Y(n1147) );
OAI21XLTS U1401 ( .A0(n1590), .A1(n1389), .B0(n1147), .Y(n650) );
AOI22X1TS U1402 ( .A0(intDX_EWSW[5]), .A1(n1161), .B0(DmP_EXP_EWSW[5]), .B1(
n1381), .Y(n1148) );
OAI21XLTS U1403 ( .A0(n1534), .A1(n1163), .B0(n1148), .Y(n648) );
AOI22X1TS U1404 ( .A0(intDX_EWSW[7]), .A1(n1161), .B0(DmP_EXP_EWSW[7]), .B1(
n1381), .Y(n1149) );
OAI21XLTS U1405 ( .A0(n1577), .A1(n1163), .B0(n1149), .Y(n644) );
AOI22X1TS U1406 ( .A0(intDX_EWSW[6]), .A1(n1161), .B0(DmP_EXP_EWSW[6]), .B1(
n1381), .Y(n1150) );
OAI21XLTS U1407 ( .A0(n1576), .A1(n1163), .B0(n1150), .Y(n646) );
AOI22X1TS U1408 ( .A0(intDX_EWSW[18]), .A1(n1161), .B0(DmP_EXP_EWSW[18]),
.B1(n1319), .Y(n1151) );
OAI21XLTS U1409 ( .A0(n1599), .A1(n1389), .B0(n1151), .Y(n622) );
AOI22X1TS U1410 ( .A0(intDX_EWSW[0]), .A1(n1161), .B0(DmP_EXP_EWSW[0]), .B1(
n1177), .Y(n1152) );
OAI21XLTS U1411 ( .A0(n1536), .A1(n1389), .B0(n1152), .Y(n658) );
AOI22X1TS U1412 ( .A0(intDX_EWSW[10]), .A1(n1161), .B0(DmP_EXP_EWSW[10]),
.B1(n1177), .Y(n1153) );
OAI21XLTS U1413 ( .A0(n930), .A1(n1163), .B0(n1153), .Y(n638) );
AOI22X1TS U1414 ( .A0(intDX_EWSW[1]), .A1(n1161), .B0(DmP_EXP_EWSW[1]), .B1(
n1319), .Y(n1154) );
OAI21XLTS U1415 ( .A0(n1587), .A1(n1389), .B0(n1154), .Y(n656) );
AOI22X1TS U1416 ( .A0(intDX_EWSW[9]), .A1(n1161), .B0(DmP_EXP_EWSW[9]), .B1(
n1319), .Y(n1155) );
AOI22X1TS U1417 ( .A0(intDX_EWSW[2]), .A1(n1161), .B0(DmP_EXP_EWSW[2]), .B1(
n1177), .Y(n1156) );
AOI22X1TS U1418 ( .A0(intDX_EWSW[8]), .A1(n1161), .B0(DmP_EXP_EWSW[8]), .B1(
n1083), .Y(n1157) );
OAI21XLTS U1419 ( .A0(n1588), .A1(n1163), .B0(n1157), .Y(n642) );
AOI22X1TS U1420 ( .A0(intDX_EWSW[12]), .A1(n1161), .B0(DmP_EXP_EWSW[12]),
.B1(n1083), .Y(n1158) );
OAI21XLTS U1421 ( .A0(n1591), .A1(n1163), .B0(n1158), .Y(n634) );
AOI22X1TS U1422 ( .A0(intDX_EWSW[11]), .A1(n1161), .B0(DmP_EXP_EWSW[11]),
.B1(n1083), .Y(n1159) );
OAI21XLTS U1423 ( .A0(n1179), .A1(n1163), .B0(n1159), .Y(n636) );
AOI22X1TS U1424 ( .A0(intDX_EWSW[3]), .A1(n1161), .B0(DmP_EXP_EWSW[3]), .B1(
n1083), .Y(n1160) );
OAI21XLTS U1425 ( .A0(n1582), .A1(n1389), .B0(n1160), .Y(n652) );
AOI22X1TS U1426 ( .A0(DmP_EXP_EWSW[27]), .A1(n1319), .B0(intDX_EWSW[27]),
.B1(n1161), .Y(n1162) );
OAI21XLTS U1427 ( .A0(n1595), .A1(n1163), .B0(n1162), .Y(n608) );
BUFX3TS U1428 ( .A(n1128), .Y(n1181) );
AOI22X1TS U1429 ( .A0(intDX_EWSW[16]), .A1(n1181), .B0(DMP_EXP_EWSW[16]),
.B1(n1177), .Y(n1164) );
OAI21XLTS U1430 ( .A0(n1593), .A1(n1183), .B0(n1164), .Y(n785) );
AOI222X1TS U1431 ( .A0(n1088), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1381), .C0(intDY_EWSW[23]), .C1(n1181), .Y(n1165) );
INVX2TS U1432 ( .A(n1165), .Y(n612) );
AOI22X1TS U1433 ( .A0(intDX_EWSW[22]), .A1(n1128), .B0(DMP_EXP_EWSW[22]),
.B1(n1381), .Y(n1166) );
OAI21XLTS U1434 ( .A0(n1538), .A1(n1392), .B0(n1166), .Y(n779) );
AOI22X1TS U1435 ( .A0(n955), .A1(n1319), .B0(intDX_EWSW[27]), .B1(n1128),
.Y(n1167) );
OAI21XLTS U1436 ( .A0(n1595), .A1(n1392), .B0(n1167), .Y(n774) );
AOI22X1TS U1437 ( .A0(intDX_EWSW[20]), .A1(n1128), .B0(DMP_EXP_EWSW[20]),
.B1(n1381), .Y(n1168) );
OAI21XLTS U1438 ( .A0(n1594), .A1(n1392), .B0(n1168), .Y(n781) );
AOI22X1TS U1439 ( .A0(DMP_EXP_EWSW[23]), .A1(n1319), .B0(intDX_EWSW[23]),
.B1(n1128), .Y(n1169) );
OAI21XLTS U1440 ( .A0(n1597), .A1(n1183), .B0(n1169), .Y(n778) );
AOI22X1TS U1441 ( .A0(intDX_EWSW[21]), .A1(n1128), .B0(DMP_EXP_EWSW[21]),
.B1(n1177), .Y(n1170) );
OAI21XLTS U1442 ( .A0(n1586), .A1(n1392), .B0(n1170), .Y(n780) );
AOI22X1TS U1443 ( .A0(intDX_EWSW[19]), .A1(n1181), .B0(DMP_EXP_EWSW[19]),
.B1(n1177), .Y(n1171) );
OAI21XLTS U1444 ( .A0(n1540), .A1(n1392), .B0(n1171), .Y(n782) );
AOI22X1TS U1445 ( .A0(intDX_EWSW[18]), .A1(n1181), .B0(DMP_EXP_EWSW[18]),
.B1(n1381), .Y(n1172) );
OAI21XLTS U1446 ( .A0(n1599), .A1(n1183), .B0(n1172), .Y(n783) );
AOI22X1TS U1447 ( .A0(intDX_EWSW[10]), .A1(n1181), .B0(DMP_EXP_EWSW[10]),
.B1(n1177), .Y(n1173) );
OAI21XLTS U1448 ( .A0(n930), .A1(n1183), .B0(n1173), .Y(n791) );
AOI22X1TS U1449 ( .A0(intDX_EWSW[14]), .A1(n1181), .B0(DMP_EXP_EWSW[14]),
.B1(n1319), .Y(n1174) );
OAI21XLTS U1450 ( .A0(n1592), .A1(n1183), .B0(n1174), .Y(n787) );
AOI22X1TS U1451 ( .A0(intDX_EWSW[17]), .A1(n1181), .B0(DMP_EXP_EWSW[17]),
.B1(n1381), .Y(n1175) );
OAI21XLTS U1452 ( .A0(n1583), .A1(n1183), .B0(n1175), .Y(n784) );
AOI22X1TS U1453 ( .A0(intDX_EWSW[12]), .A1(n1181), .B0(DMP_EXP_EWSW[12]),
.B1(n1319), .Y(n1176) );
OAI21XLTS U1454 ( .A0(n1591), .A1(n1183), .B0(n1176), .Y(n789) );
AOI22X1TS U1455 ( .A0(intDX_EWSW[11]), .A1(n1181), .B0(DMP_EXP_EWSW[11]),
.B1(n1381), .Y(n1178) );
OAI21XLTS U1456 ( .A0(n1179), .A1(n1183), .B0(n1178), .Y(n790) );
AOI22X1TS U1457 ( .A0(intDX_EWSW[13]), .A1(n1181), .B0(DMP_EXP_EWSW[13]),
.B1(n1381), .Y(n1180) );
AOI22X1TS U1458 ( .A0(intDX_EWSW[15]), .A1(n1181), .B0(DMP_EXP_EWSW[15]),
.B1(n1381), .Y(n1182) );
OAI21XLTS U1459 ( .A0(n1184), .A1(n1183), .B0(n1182), .Y(n786) );
NOR2XLTS U1460 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1186)
);
OAI21XLTS U1461 ( .A0(n1186), .A1(n1185), .B0(n1304), .Y(n1187) );
AOI211X1TS U1462 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1198), .B0(n1188), .C0(
n1187), .Y(n1190) );
NOR3X1TS U1463 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .C(n1303),
.Y(n1189) );
NAND2X1TS U1464 ( .A(n1189), .B(n962), .Y(n1201) );
NAND2X1TS U1465 ( .A(Raw_mant_NRM_SWR[1]), .B(n1189), .Y(n1296) );
AOI31X1TS U1466 ( .A0(n1190), .A1(n1201), .A2(n1296), .B0(n920), .Y(n1291)
);
BUFX4TS U1467 ( .A(OP_FLAG_SFG), .Y(n1425) );
AOI2BB2X1TS U1468 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n1425), .A0N(n1425),
.A1N(DmP_mant_SFG_SWR[10]), .Y(intadd_40_B_2_) );
AOI32X1TS U1469 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n926), .A2(n1562), .B0(
Raw_mant_NRM_SWR[22]), .B1(n926), .Y(n1192) );
AOI32X1TS U1470 ( .A0(n1524), .A1(n1193), .A2(n1192), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1193), .Y(n1194) );
OAI21XLTS U1471 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1553), .B0(n1528), .Y(n1197) );
AOI21X1TS U1472 ( .A0(n1198), .A1(n1197), .B0(n1196), .Y(n1200) );
NAND2X1TS U1473 ( .A(Raw_mant_NRM_SWR[12]), .B(n1199), .Y(n1297) );
OAI211X1TS U1474 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1201), .B0(n1200), .C0(
n1297), .Y(n1307) );
OAI211X1TS U1475 ( .A0(n1558), .A1(n1205), .B0(n1204), .C0(n1203), .Y(n1210)
);
OR2X2TS U1476 ( .A(n920), .B(n1210), .Y(n1335) );
BUFX4TS U1477 ( .A(n1236), .Y(n1343) );
AOI21X1TS U1478 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n920), .B0(n1206), .Y(
n1208) );
NOR2X2TS U1479 ( .A(n923), .B(n1208), .Y(n1352) );
NAND2X2TS U1480 ( .A(n1210), .B(Shift_reg_FLAGS_7[1]), .Y(n1345) );
INVX2TS U1481 ( .A(n1345), .Y(n1333) );
AOI22X1TS U1482 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1333), .B0(n1236), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1212) );
AOI22X1TS U1483 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1353), .B0(n959), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1211) );
NAND2X1TS U1484 ( .A(n1212), .B(n1211), .Y(n1252) );
AOI22X1TS U1485 ( .A0(n1358), .A1(Data_array_SWR[3]), .B0(n1209), .B1(n1252),
.Y(n1215) );
BUFX3TS U1486 ( .A(n1213), .Y(n1263) );
NAND2X1TS U1487 ( .A(Raw_mant_NRM_SWR[19]), .B(n1263), .Y(n1214) );
AOI22X1TS U1488 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1333), .B0(n1343), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1217) );
AOI22X1TS U1489 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1353), .B0(n959), .B1(n954), .Y(n1216) );
NAND2X1TS U1490 ( .A(n1217), .B(n1216), .Y(n1351) );
AOI22X1TS U1491 ( .A0(n1358), .A1(Data_array_SWR[2]), .B0(n1209), .B1(n1351),
.Y(n1219) );
NAND2X1TS U1492 ( .A(Raw_mant_NRM_SWR[20]), .B(n1263), .Y(n1218) );
AOI22X1TS U1493 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1333), .B0(n1236), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1221) );
AOI22X1TS U1494 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1353), .B0(n959), .B1(n953), .Y(n1220) );
NAND2X1TS U1495 ( .A(n1221), .B(n1220), .Y(n1268) );
AOI22X1TS U1496 ( .A0(n923), .A1(Data_array_SWR[7]), .B0(n1209), .B1(n1268),
.Y(n1223) );
NAND2X1TS U1497 ( .A(Raw_mant_NRM_SWR[15]), .B(n1263), .Y(n1222) );
AOI22X1TS U1498 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1333), .B0(n1236), .B1(
n953), .Y(n1225) );
AOI22X1TS U1499 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1353), .B0(n959), .B1(n947), .Y(n1224) );
NAND2X1TS U1500 ( .A(n1225), .B(n1224), .Y(n1272) );
AOI22X1TS U1501 ( .A0(n1358), .A1(Data_array_SWR[6]), .B0(n1209), .B1(n1272),
.Y(n1227) );
NAND2X1TS U1502 ( .A(Raw_mant_NRM_SWR[16]), .B(n1263), .Y(n1226) );
AOI22X1TS U1503 ( .A0(n1358), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1263), .Y(n1230) );
NAND2X1TS U1504 ( .A(n1228), .B(n1333), .Y(n1278) );
AOI22X1TS U1505 ( .A0(n923), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1263), .Y(n1233) );
AOI22X1TS U1506 ( .A0(n1358), .A1(Data_array_SWR[21]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n1263), .Y(n1235) );
AOI22X1TS U1507 ( .A0(n959), .A1(DmP_mant_SHT1_SW[18]), .B0(n1236), .B1(n948), .Y(n1237) );
AOI21X1TS U1508 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n1353), .B0(n1238), .Y(n1338) );
OAI22X1TS U1509 ( .A0(n1246), .A1(n957), .B0(n1558), .B1(n1278), .Y(n1239)
);
AOI21X1TS U1510 ( .A0(n923), .A1(Data_array_SWR[18]), .B0(n1239), .Y(n1240)
);
AOI22X1TS U1511 ( .A0(n1358), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1263), .Y(n1242) );
AOI22X1TS U1512 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1333), .B0(n1236), .B1(n949), .Y(n1244) );
AOI21X1TS U1513 ( .A0(n960), .A1(DmP_mant_SHT1_SW[14]), .B0(n1245), .Y(n1342) );
OAI2BB2XLTS U1514 ( .B0(n1246), .B1(n1207), .A0N(Raw_mant_NRM_SWR[6]), .A1N(
n1263), .Y(n1247) );
AOI21X1TS U1515 ( .A0(n923), .A1(Data_array_SWR[16]), .B0(n1247), .Y(n1248)
);
AOI21X1TS U1516 ( .A0(n1353), .A1(n962), .B0(n960), .Y(n1330) );
OAI22X1TS U1517 ( .A0(n1249), .A1(n957), .B0(n1360), .B1(n1613), .Y(n1250)
);
AOI21X1TS U1518 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1350), .B0(n1250), .Y(n1251) );
AOI22X1TS U1519 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n1353), .B0(n1343), .B1(
n954), .Y(n1255) );
AOI22X1TS U1520 ( .A0(n1358), .A1(Data_array_SWR[1]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n1350), .Y(n1254) );
NAND2X1TS U1521 ( .A(n1352), .B(n1252), .Y(n1253) );
AOI22X1TS U1522 ( .A0(n1358), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1263), .Y(n1258) );
AOI22X1TS U1523 ( .A0(n923), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1263), .Y(n1262) );
AOI22X1TS U1524 ( .A0(n1358), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1263), .Y(n1266) );
AOI22X1TS U1525 ( .A0(n1358), .A1(Data_array_SWR[5]), .B0(n1352), .B1(n1268),
.Y(n1270) );
NAND2X1TS U1526 ( .A(Raw_mant_NRM_SWR[19]), .B(n1350), .Y(n1269) );
AOI22X1TS U1527 ( .A0(n1358), .A1(Data_array_SWR[4]), .B0(n1352), .B1(n1272),
.Y(n1274) );
NAND2X1TS U1528 ( .A(Raw_mant_NRM_SWR[20]), .B(n1350), .Y(n1273) );
AOI22X1TS U1529 ( .A0(n959), .A1(DmP_mant_SHT1_SW[8]), .B0(n1236), .B1(n952),
.Y(n1276) );
AOI21X1TS U1530 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1353), .B0(n1277), .Y(
n1348) );
OAI22X1TS U1531 ( .A0(n1279), .A1(n957), .B0(n1606), .B1(n1278), .Y(n1280)
);
AOI21X1TS U1532 ( .A0(n923), .A1(Data_array_SWR[8]), .B0(n1280), .Y(n1281)
);
AOI2BB2X1TS U1533 ( .B0(DmP_mant_SFG_SWR[2]), .B1(n1425), .A0N(n1425), .A1N(
DmP_mant_SFG_SWR[2]), .Y(n1431) );
NAND2X1TS U1534 ( .A(n1431), .B(DMP_SFG[0]), .Y(n1433) );
INVX2TS U1535 ( .A(n1433), .Y(n1282) );
NOR2XLTS U1536 ( .A(n1283), .B(SIGN_FLAG_SHT1SHT2), .Y(n1284) );
OAI2BB2XLTS U1537 ( .B0(n1284), .B1(n1315), .A0N(n1660), .A1N(
final_result_ieee[31]), .Y(n591) );
AOI22X1TS U1538 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n1425), .B0(n963), .B1(n968),
.Y(intadd_40_CI) );
INVX2TS U1539 ( .A(intadd_40_B_2_), .Y(n1287) );
OAI21X1TS U1540 ( .A0(DMP_SFG[7]), .A1(intadd_40_B_1_), .B0(n1285), .Y(n1286) );
AOI222X1TS U1541 ( .A0(n1551), .A1(n1287), .B0(n1551), .B1(n1286), .C0(n1287), .C1(n1286), .Y(n1288) );
INVX2TS U1542 ( .A(n1289), .Y(n1290) );
NAND2X1TS U1543 ( .A(n1556), .B(n1290), .Y(DP_OP_15J35_125_2314_n8) );
MX2X1TS U1544 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n659) );
MX2X1TS U1545 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n664) );
MX2X1TS U1546 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n669) );
MX2X1TS U1547 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n674) );
MX2X1TS U1548 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n679) );
MX2X1TS U1549 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n684) );
MX2X1TS U1550 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n689) );
MX2X1TS U1551 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n694) );
AO21XLTS U1552 ( .A0(LZD_output_NRM2_EW[4]), .A1(n920), .B0(n1291), .Y(n574)
);
OAI211X1TS U1553 ( .A0(Raw_mant_NRM_SWR[11]), .A1(Raw_mant_NRM_SWR[13]),
.B0(n1292), .C0(n1548), .Y(n1300) );
OAI2BB1X1TS U1554 ( .A0N(n1294), .A1N(n1548), .B0(n1293), .Y(n1295) );
NAND4XLTS U1555 ( .A(n1297), .B(n1300), .C(n1296), .D(n1295), .Y(n1298) );
OAI21X1TS U1556 ( .A0(n1299), .A1(n1298), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1361) );
OAI2BB1X1TS U1557 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n920), .B0(n1361), .Y(
n560) );
OAI22X1TS U1558 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1304), .B0(n1303), .B1(
n1604), .Y(n1306) );
OAI31X1TS U1559 ( .A0(n1308), .A1(n1307), .A2(n1306), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1356) );
OAI2BB1X1TS U1560 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n920), .B0(n1356), .Y(
n571) );
OAI2BB1X1TS U1561 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n920), .B0(n1345), .Y(
n566) );
NAND2X2TS U1562 ( .A(n1393), .B(Shift_reg_FLAGS_7[0]), .Y(n1312) );
OA22X1TS U1563 ( .A0(n1312), .A1(n1309), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[23]), .Y(n809) );
OA22X1TS U1564 ( .A0(n1312), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n808) );
OA22X1TS U1565 ( .A0(n1312), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n807) );
OA22X1TS U1566 ( .A0(n1312), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n806) );
OA22X1TS U1567 ( .A0(n1312), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n805) );
OA22X1TS U1568 ( .A0(n1312), .A1(n1310), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n804) );
OA22X1TS U1569 ( .A0(n1312), .A1(n1311), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n803) );
INVX2TS U1570 ( .A(n1315), .Y(n1314) );
AO22XLTS U1571 ( .A0(n1314), .A1(n1313), .B0(n965), .B1(
final_result_ieee[30]), .Y(n802) );
OA21XLTS U1572 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1315),
.Y(n606) );
INVX2TS U1573 ( .A(n1318), .Y(n1317) );
AOI22X1TS U1574 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1317), .B1(n1533), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1575 ( .A(n1317), .B(n1316), .Y(n919) );
AOI22X1TS U1576 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1318), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1533), .Y(n1322) );
AO22XLTS U1577 ( .A0(n1320), .A1(Shift_reg_FLAGS_7_6), .B0(n1321), .B1(n1322), .Y(n917) );
AOI22X1TS U1578 ( .A0(n1321), .A1(n1319), .B0(n1387), .B1(n1320), .Y(n916)
);
AOI22X1TS U1579 ( .A0(n1321), .A1(n1387), .B0(n1385), .B1(n1320), .Y(n915)
);
AOI22X1TS U1580 ( .A0(n1321), .A1(n1441), .B0(n920), .B1(n1320), .Y(n912) );
BUFX4TS U1581 ( .A(n1324), .Y(n1329) );
AO22XLTS U1582 ( .A0(n1329), .A1(Data_X[1]), .B0(n922), .B1(intDX_EWSW[1]),
.Y(n909) );
BUFX3TS U1583 ( .A(n1324), .Y(n1323) );
AO22XLTS U1584 ( .A0(n1323), .A1(Data_X[2]), .B0(n922), .B1(intDX_EWSW[2]),
.Y(n908) );
BUFX3TS U1585 ( .A(n1324), .Y(n1327) );
AO22XLTS U1586 ( .A0(n1327), .A1(Data_X[3]), .B0(n1328), .B1(intDX_EWSW[3]),
.Y(n907) );
AO22XLTS U1587 ( .A0(n1325), .A1(Data_X[4]), .B0(n922), .B1(intDX_EWSW[4]),
.Y(n906) );
AO22XLTS U1588 ( .A0(n1329), .A1(Data_X[5]), .B0(n922), .B1(intDX_EWSW[5]),
.Y(n905) );
AO22XLTS U1589 ( .A0(n1329), .A1(Data_X[6]), .B0(n1328), .B1(intDX_EWSW[6]),
.Y(n904) );
AO22XLTS U1590 ( .A0(n1324), .A1(Data_X[7]), .B0(n922), .B1(intDX_EWSW[7]),
.Y(n903) );
AO22XLTS U1591 ( .A0(n1327), .A1(Data_X[8]), .B0(n922), .B1(intDX_EWSW[8]),
.Y(n902) );
AO22XLTS U1592 ( .A0(n1327), .A1(Data_X[9]), .B0(n1328), .B1(intDX_EWSW[9]),
.Y(n901) );
AO22XLTS U1593 ( .A0(n1327), .A1(Data_X[11]), .B0(n922), .B1(intDX_EWSW[11]),
.Y(n899) );
INVX2TS U1594 ( .A(n1325), .Y(n1328) );
AO22XLTS U1595 ( .A0(n1329), .A1(Data_X[12]), .B0(n1328), .B1(intDX_EWSW[12]), .Y(n898) );
AO22XLTS U1596 ( .A0(n1325), .A1(Data_X[13]), .B0(n922), .B1(intDX_EWSW[13]),
.Y(n897) );
AO22XLTS U1597 ( .A0(n1324), .A1(Data_X[14]), .B0(n922), .B1(intDX_EWSW[14]),
.Y(n896) );
AO22XLTS U1598 ( .A0(n1329), .A1(Data_X[15]), .B0(n1328), .B1(intDX_EWSW[15]), .Y(n895) );
AO22XLTS U1599 ( .A0(n1323), .A1(Data_X[16]), .B0(n922), .B1(intDX_EWSW[16]),
.Y(n894) );
AO22XLTS U1600 ( .A0(n1329), .A1(Data_X[17]), .B0(n922), .B1(intDX_EWSW[17]),
.Y(n893) );
AO22XLTS U1601 ( .A0(n1324), .A1(Data_X[20]), .B0(n1328), .B1(intDX_EWSW[20]), .Y(n890) );
AO22XLTS U1602 ( .A0(n1325), .A1(Data_X[21]), .B0(n922), .B1(intDX_EWSW[21]),
.Y(n889) );
AO22XLTS U1603 ( .A0(n1325), .A1(Data_X[22]), .B0(n922), .B1(intDX_EWSW[22]),
.Y(n888) );
AO22XLTS U1604 ( .A0(n1323), .A1(Data_X[23]), .B0(n1328), .B1(intDX_EWSW[23]), .Y(n887) );
AO22XLTS U1605 ( .A0(n921), .A1(intDX_EWSW[24]), .B0(n1324), .B1(Data_X[24]),
.Y(n886) );
AO22XLTS U1606 ( .A0(n921), .A1(intDX_EWSW[25]), .B0(n1327), .B1(Data_X[25]),
.Y(n885) );
AO22XLTS U1607 ( .A0(n921), .A1(intDX_EWSW[26]), .B0(n1323), .B1(Data_X[26]),
.Y(n884) );
AO22XLTS U1608 ( .A0(n1327), .A1(Data_X[27]), .B0(n921), .B1(intDX_EWSW[27]),
.Y(n883) );
AO22XLTS U1609 ( .A0(n921), .A1(intDX_EWSW[28]), .B0(n1327), .B1(Data_X[28]),
.Y(n882) );
AO22XLTS U1610 ( .A0(n921), .A1(intDX_EWSW[29]), .B0(n1323), .B1(Data_X[29]),
.Y(n881) );
AO22XLTS U1611 ( .A0(n921), .A1(intDX_EWSW[30]), .B0(n1323), .B1(Data_X[30]),
.Y(n880) );
AO22XLTS U1612 ( .A0(n1327), .A1(add_subt), .B0(n921), .B1(intAS), .Y(n878)
);
AO22XLTS U1613 ( .A0(n921), .A1(intDY_EWSW[0]), .B0(n1323), .B1(Data_Y[0]),
.Y(n876) );
AO22XLTS U1614 ( .A0(n921), .A1(intDY_EWSW[1]), .B0(n1323), .B1(Data_Y[1]),
.Y(n875) );
AO22XLTS U1615 ( .A0(n1326), .A1(intDY_EWSW[2]), .B0(n1323), .B1(Data_Y[2]),
.Y(n874) );
AO22XLTS U1616 ( .A0(n1326), .A1(intDY_EWSW[3]), .B0(n1323), .B1(Data_Y[3]),
.Y(n873) );
AO22XLTS U1617 ( .A0(n1326), .A1(intDY_EWSW[4]), .B0(n1323), .B1(Data_Y[4]),
.Y(n872) );
AO22XLTS U1618 ( .A0(n1326), .A1(intDY_EWSW[5]), .B0(n1323), .B1(Data_Y[5]),
.Y(n871) );
AO22XLTS U1619 ( .A0(n921), .A1(intDY_EWSW[6]), .B0(n1324), .B1(Data_Y[6]),
.Y(n870) );
AO22XLTS U1620 ( .A0(n921), .A1(intDY_EWSW[7]), .B0(n1329), .B1(Data_Y[7]),
.Y(n869) );
AO22XLTS U1621 ( .A0(n921), .A1(intDY_EWSW[8]), .B0(n1329), .B1(Data_Y[8]),
.Y(n868) );
AO22XLTS U1622 ( .A0(n1326), .A1(intDY_EWSW[9]), .B0(n1324), .B1(Data_Y[9]),
.Y(n867) );
AO22XLTS U1623 ( .A0(n921), .A1(intDY_EWSW[10]), .B0(n1329), .B1(Data_Y[10]),
.Y(n866) );
AO22XLTS U1624 ( .A0(n1326), .A1(intDY_EWSW[11]), .B0(n1329), .B1(Data_Y[11]), .Y(n865) );
AO22XLTS U1625 ( .A0(n1326), .A1(intDY_EWSW[12]), .B0(n1329), .B1(Data_Y[12]), .Y(n864) );
AO22XLTS U1626 ( .A0(n1326), .A1(intDY_EWSW[13]), .B0(n1329), .B1(Data_Y[13]), .Y(n863) );
AO22XLTS U1627 ( .A0(n921), .A1(intDY_EWSW[14]), .B0(n1329), .B1(Data_Y[14]),
.Y(n862) );
AO22XLTS U1628 ( .A0(n1326), .A1(intDY_EWSW[15]), .B0(n1329), .B1(Data_Y[15]), .Y(n861) );
AO22XLTS U1629 ( .A0(n1326), .A1(intDY_EWSW[16]), .B0(n1329), .B1(Data_Y[16]), .Y(n860) );
AO22XLTS U1630 ( .A0(n921), .A1(intDY_EWSW[17]), .B0(n1329), .B1(Data_Y[17]),
.Y(n859) );
AO22XLTS U1631 ( .A0(n1326), .A1(intDY_EWSW[18]), .B0(n1329), .B1(Data_Y[18]), .Y(n858) );
AO22XLTS U1632 ( .A0(n1326), .A1(intDY_EWSW[19]), .B0(n1329), .B1(Data_Y[19]), .Y(n857) );
AO22XLTS U1633 ( .A0(n1326), .A1(intDY_EWSW[20]), .B0(n1327), .B1(Data_Y[20]), .Y(n856) );
AO22XLTS U1634 ( .A0(n921), .A1(intDY_EWSW[21]), .B0(n1327), .B1(Data_Y[21]),
.Y(n855) );
AO22XLTS U1635 ( .A0(n1326), .A1(intDY_EWSW[22]), .B0(n1327), .B1(Data_Y[22]), .Y(n854) );
AO22XLTS U1636 ( .A0(n1326), .A1(intDY_EWSW[23]), .B0(n1325), .B1(Data_Y[23]), .Y(n853) );
AO22XLTS U1637 ( .A0(n921), .A1(intDY_EWSW[24]), .B0(n1324), .B1(Data_Y[24]),
.Y(n852) );
AO22XLTS U1638 ( .A0(n921), .A1(intDY_EWSW[25]), .B0(n1324), .B1(Data_Y[25]),
.Y(n851) );
AO22XLTS U1639 ( .A0(n1326), .A1(intDY_EWSW[26]), .B0(n1324), .B1(Data_Y[26]), .Y(n850) );
AO22XLTS U1640 ( .A0(n1326), .A1(intDY_EWSW[27]), .B0(n1325), .B1(Data_Y[27]), .Y(n849) );
AO22XLTS U1641 ( .A0(n1327), .A1(Data_Y[29]), .B0(n922), .B1(intDY_EWSW[29]),
.Y(n847) );
AO22XLTS U1642 ( .A0(n1327), .A1(Data_Y[30]), .B0(n922), .B1(intDY_EWSW[30]),
.Y(n846) );
OAI22X1TS U1643 ( .A0(n1330), .A1(n958), .B0(n1360), .B1(n1535), .Y(n844) );
AOI211X1TS U1644 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n920), .B0(n1343), .C0(
n1332), .Y(n1337) );
OAI2BB2XLTS U1645 ( .B0(n1337), .B1(n957), .A0N(n923), .A1N(
Data_array_SWR[24]), .Y(n843) );
AOI22X1TS U1646 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1333), .B0(
DmP_mant_SHT1_SW[21]), .B1(n1343), .Y(n1334) );
AOI21X1TS U1647 ( .A0(DmP_mant_SHT1_SW[20]), .A1(n960), .B0(n1336), .Y(n1339) );
OAI222X1TS U1648 ( .A0(n1360), .A1(n1612), .B0(n1207), .B1(n1337), .C0(n957),
.C1(n1339), .Y(n841) );
OAI222X1TS U1649 ( .A0(n1625), .A1(n1360), .B0(n1207), .B1(n1339), .C0(n958),
.C1(n1338), .Y(n839) );
AOI22X1TS U1650 ( .A0(n959), .A1(DmP_mant_SHT1_SW[12]), .B0(n1343), .B1(n950), .Y(n1340) );
AOI21X1TS U1651 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n1353), .B0(n1341), .Y(
n1347) );
OAI222X1TS U1652 ( .A0(n1541), .A1(n1360), .B0(n1207), .B1(n1342), .C0(n958),
.C1(n1347), .Y(n833) );
AOI22X1TS U1653 ( .A0(n959), .A1(DmP_mant_SHT1_SW[10]), .B0(n1343), .B1(n951), .Y(n1344) );
AOI21X1TS U1654 ( .A0(Raw_mant_NRM_SWR[13]), .A1(n1353), .B0(n1346), .Y(
n1349) );
OAI222X1TS U1655 ( .A0(n1617), .A1(n1360), .B0(n1207), .B1(n1347), .C0(n958),
.C1(n1349), .Y(n831) );
OAI222X1TS U1656 ( .A0(n1607), .A1(n1360), .B0(n1207), .B1(n1349), .C0(n958),
.C1(n1348), .Y(n829) );
AOI22X1TS U1657 ( .A0(n923), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1350), .Y(n1355) );
AOI22X1TS U1658 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1353), .B0(n1352), .B1(
n1351), .Y(n1354) );
NAND2X1TS U1659 ( .A(n1355), .B(n1354), .Y(n819) );
AOI32X1TS U1660 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1360), .A2(n920), .B0(
shift_value_SHT2_EWR[2]), .B1(n923), .Y(n1357) );
NAND2X1TS U1661 ( .A(n1357), .B(n1356), .Y(n818) );
AOI32X1TS U1662 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n1360), .A2(n920), .B0(
shift_value_SHT2_EWR[3]), .B1(n923), .Y(n1362) );
NAND2X1TS U1663 ( .A(n1362), .B(n1361), .Y(n817) );
INVX4TS U1664 ( .A(n1387), .Y(n1396) );
AOI21X1TS U1665 ( .A0(DMP_EXP_EWSW[23]), .A1(n977), .B0(n1367), .Y(n1363) );
INVX4TS U1666 ( .A(n1387), .Y(n1398) );
AOI2BB2XLTS U1667 ( .B0(n1396), .B1(n1363), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1398), .Y(n814) );
NOR2X1TS U1668 ( .A(n1542), .B(DMP_EXP_EWSW[24]), .Y(n1366) );
AOI21X1TS U1669 ( .A0(DMP_EXP_EWSW[24]), .A1(n1542), .B0(n1366), .Y(n1364)
);
XNOR2X1TS U1670 ( .A(n1367), .B(n1364), .Y(n1365) );
AO22XLTS U1671 ( .A0(n1398), .A1(n1365), .B0(n1387), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n813) );
INVX4TS U1672 ( .A(n1387), .Y(n1384) );
OAI22X1TS U1673 ( .A0(n1367), .A1(n1366), .B0(DmP_EXP_EWSW[24]), .B1(n1543),
.Y(n1370) );
NAND2X1TS U1674 ( .A(DmP_EXP_EWSW[25]), .B(n1605), .Y(n1371) );
XNOR2X1TS U1675 ( .A(n1370), .B(n1368), .Y(n1369) );
AO22XLTS U1676 ( .A0(n1384), .A1(n1369), .B0(n1626), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n812) );
AOI22X1TS U1677 ( .A0(DMP_EXP_EWSW[25]), .A1(n1621), .B0(n1371), .B1(n1370),
.Y(n1374) );
NOR2X1TS U1678 ( .A(n1616), .B(DMP_EXP_EWSW[26]), .Y(n1375) );
AOI21X1TS U1679 ( .A0(DMP_EXP_EWSW[26]), .A1(n1616), .B0(n1375), .Y(n1372)
);
XNOR2X1TS U1680 ( .A(n1374), .B(n1372), .Y(n1373) );
AO22XLTS U1681 ( .A0(n1398), .A1(n1373), .B0(n1626), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n811) );
OAI22X1TS U1682 ( .A0(n1375), .A1(n1374), .B0(DmP_EXP_EWSW[26]), .B1(n1620),
.Y(n1377) );
XNOR2X1TS U1683 ( .A(DmP_EXP_EWSW[27]), .B(n955), .Y(n1376) );
XOR2XLTS U1684 ( .A(n1377), .B(n1376), .Y(n1378) );
BUFX3TS U1685 ( .A(n1626), .Y(n1386) );
AO22XLTS U1686 ( .A0(n1384), .A1(n1378), .B0(n1386), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n810) );
OAI222X1TS U1687 ( .A0(n1389), .A1(n1618), .B0(n1543), .B1(
Shift_reg_FLAGS_7_6), .C0(n1526), .C1(n1392), .Y(n777) );
OAI222X1TS U1688 ( .A0(n1389), .A1(n1544), .B0(n1605), .B1(
Shift_reg_FLAGS_7_6), .C0(n1630), .C1(n1392), .Y(n776) );
OAI222X1TS U1689 ( .A0(n1389), .A1(n1545), .B0(n1620), .B1(
Shift_reg_FLAGS_7_6), .C0(n1390), .C1(n1392), .Y(n775) );
OAI21XLTS U1690 ( .A0(n1380), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1379) );
AOI21X1TS U1691 ( .A0(n1380), .A1(intDX_EWSW[31]), .B0(n1379), .Y(n1382) );
AO21XLTS U1692 ( .A0(OP_FLAG_EXP), .A1(n1381), .B0(n1382), .Y(n770) );
AO22XLTS U1693 ( .A0(n1383), .A1(n1382), .B0(ZERO_FLAG_EXP), .B1(n1381), .Y(
n769) );
AO22XLTS U1694 ( .A0(n1384), .A1(DMP_EXP_EWSW[0]), .B0(n1386), .B1(
DMP_SHT1_EWSW[0]), .Y(n767) );
AO22XLTS U1695 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1628), .B1(
DMP_SHT2_EWSW[0]), .Y(n766) );
INVX2TS U1696 ( .A(n1517), .Y(n1523) );
AO22XLTS U1697 ( .A0(n1398), .A1(DMP_EXP_EWSW[1]), .B0(n1386), .B1(
DMP_SHT1_EWSW[1]), .Y(n764) );
AO22XLTS U1698 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1385), .B1(
DMP_SHT2_EWSW[1]), .Y(n763) );
INVX4TS U1699 ( .A(n980), .Y(n1516) );
AO22XLTS U1700 ( .A0(n1384), .A1(DMP_EXP_EWSW[2]), .B0(n1386), .B1(
DMP_SHT1_EWSW[2]), .Y(n761) );
AO22XLTS U1701 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1385), .B1(
DMP_SHT2_EWSW[2]), .Y(n760) );
BUFX3TS U1702 ( .A(n980), .Y(n1507) );
AO22XLTS U1703 ( .A0(n1507), .A1(DMP_SFG[2]), .B0(n1516), .B1(
DMP_SHT2_EWSW[2]), .Y(n759) );
AO22XLTS U1704 ( .A0(n1384), .A1(DMP_EXP_EWSW[3]), .B0(n1386), .B1(
DMP_SHT1_EWSW[3]), .Y(n758) );
AO22XLTS U1705 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1385), .B1(
DMP_SHT2_EWSW[3]), .Y(n757) );
AO22XLTS U1706 ( .A0(n1507), .A1(DMP_SFG[3]), .B0(n1516), .B1(
DMP_SHT2_EWSW[3]), .Y(n756) );
AO22XLTS U1707 ( .A0(n1384), .A1(DMP_EXP_EWSW[4]), .B0(n1386), .B1(
DMP_SHT1_EWSW[4]), .Y(n755) );
AO22XLTS U1708 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1385), .B1(
DMP_SHT2_EWSW[4]), .Y(n754) );
AO22XLTS U1709 ( .A0(n1507), .A1(DMP_SFG[4]), .B0(n1510), .B1(
DMP_SHT2_EWSW[4]), .Y(n753) );
AO22XLTS U1710 ( .A0(n1384), .A1(DMP_EXP_EWSW[5]), .B0(n1386), .B1(
DMP_SHT1_EWSW[5]), .Y(n752) );
AO22XLTS U1711 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1385), .B1(
DMP_SHT2_EWSW[5]), .Y(n751) );
AO22XLTS U1712 ( .A0(n1384), .A1(DMP_EXP_EWSW[6]), .B0(n1386), .B1(
DMP_SHT1_EWSW[6]), .Y(n749) );
AO22XLTS U1713 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1385), .B1(
DMP_SHT2_EWSW[6]), .Y(n748) );
AO22XLTS U1714 ( .A0(n1384), .A1(DMP_EXP_EWSW[7]), .B0(n1386), .B1(
DMP_SHT1_EWSW[7]), .Y(n746) );
AO22XLTS U1715 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1385), .B1(
DMP_SHT2_EWSW[7]), .Y(n745) );
AO22XLTS U1716 ( .A0(n1384), .A1(DMP_EXP_EWSW[8]), .B0(n1386), .B1(
DMP_SHT1_EWSW[8]), .Y(n743) );
AO22XLTS U1717 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1385), .B1(
DMP_SHT2_EWSW[8]), .Y(n742) );
AO22XLTS U1718 ( .A0(n1384), .A1(DMP_EXP_EWSW[9]), .B0(n1386), .B1(
DMP_SHT1_EWSW[9]), .Y(n740) );
AO22XLTS U1719 ( .A0(n1399), .A1(DMP_SHT1_EWSW[9]), .B0(n1385), .B1(
DMP_SHT2_EWSW[9]), .Y(n739) );
AO22XLTS U1720 ( .A0(n1384), .A1(DMP_EXP_EWSW[10]), .B0(n1386), .B1(
DMP_SHT1_EWSW[10]), .Y(n737) );
BUFX4TS U1721 ( .A(n1385), .Y(n1395) );
AO22XLTS U1722 ( .A0(n1399), .A1(DMP_SHT1_EWSW[10]), .B0(n1395), .B1(
DMP_SHT2_EWSW[10]), .Y(n736) );
AO22XLTS U1723 ( .A0(n1430), .A1(DMP_SFG[10]), .B0(n1516), .B1(
DMP_SHT2_EWSW[10]), .Y(n735) );
AO22XLTS U1724 ( .A0(n1384), .A1(DMP_EXP_EWSW[11]), .B0(n1626), .B1(
DMP_SHT1_EWSW[11]), .Y(n734) );
AO22XLTS U1725 ( .A0(n1399), .A1(DMP_SHT1_EWSW[11]), .B0(n1395), .B1(
DMP_SHT2_EWSW[11]), .Y(n733) );
BUFX3TS U1726 ( .A(n980), .Y(n1506) );
AO22XLTS U1727 ( .A0(n1506), .A1(DMP_SFG[11]), .B0(n1516), .B1(
DMP_SHT2_EWSW[11]), .Y(n732) );
BUFX4TS U1728 ( .A(n1626), .Y(n1388) );
AO22XLTS U1729 ( .A0(n1384), .A1(DMP_EXP_EWSW[12]), .B0(n1388), .B1(
DMP_SHT1_EWSW[12]), .Y(n731) );
AO22XLTS U1730 ( .A0(n1399), .A1(DMP_SHT1_EWSW[12]), .B0(n1395), .B1(
DMP_SHT2_EWSW[12]), .Y(n730) );
AO22XLTS U1731 ( .A0(n1507), .A1(DMP_SFG[12]), .B0(n1516), .B1(
DMP_SHT2_EWSW[12]), .Y(n729) );
BUFX3TS U1732 ( .A(n1626), .Y(n1397) );
AO22XLTS U1733 ( .A0(n1384), .A1(DMP_EXP_EWSW[13]), .B0(n1397), .B1(
DMP_SHT1_EWSW[13]), .Y(n728) );
AO22XLTS U1734 ( .A0(n1399), .A1(DMP_SHT1_EWSW[13]), .B0(n1395), .B1(
DMP_SHT2_EWSW[13]), .Y(n727) );
AO22XLTS U1735 ( .A0(n1430), .A1(DMP_SFG[13]), .B0(n1516), .B1(
DMP_SHT2_EWSW[13]), .Y(n726) );
AO22XLTS U1736 ( .A0(n1384), .A1(DMP_EXP_EWSW[14]), .B0(n1626), .B1(
DMP_SHT1_EWSW[14]), .Y(n725) );
AO22XLTS U1737 ( .A0(n1399), .A1(DMP_SHT1_EWSW[14]), .B0(n1395), .B1(
DMP_SHT2_EWSW[14]), .Y(n724) );
AO22XLTS U1738 ( .A0(n1507), .A1(DMP_SFG[14]), .B0(n1516), .B1(
DMP_SHT2_EWSW[14]), .Y(n723) );
AO22XLTS U1739 ( .A0(n1384), .A1(DMP_EXP_EWSW[15]), .B0(n1388), .B1(
DMP_SHT1_EWSW[15]), .Y(n722) );
AO22XLTS U1740 ( .A0(n1399), .A1(DMP_SHT1_EWSW[15]), .B0(n1395), .B1(
DMP_SHT2_EWSW[15]), .Y(n721) );
AO22XLTS U1741 ( .A0(n1430), .A1(DMP_SFG[15]), .B0(n1516), .B1(
DMP_SHT2_EWSW[15]), .Y(n720) );
AO22XLTS U1742 ( .A0(n1384), .A1(DMP_EXP_EWSW[16]), .B0(n1397), .B1(
DMP_SHT1_EWSW[16]), .Y(n719) );
AO22XLTS U1743 ( .A0(busy), .A1(DMP_SHT1_EWSW[16]), .B0(n1395), .B1(
DMP_SHT2_EWSW[16]), .Y(n718) );
AO22XLTS U1744 ( .A0(n1398), .A1(DMP_EXP_EWSW[17]), .B0(n1387), .B1(
DMP_SHT1_EWSW[17]), .Y(n716) );
AO22XLTS U1745 ( .A0(busy), .A1(DMP_SHT1_EWSW[17]), .B0(n1395), .B1(
DMP_SHT2_EWSW[17]), .Y(n715) );
AO22XLTS U1746 ( .A0(n1398), .A1(DMP_EXP_EWSW[18]), .B0(n1388), .B1(
DMP_SHT1_EWSW[18]), .Y(n713) );
AO22XLTS U1747 ( .A0(busy), .A1(DMP_SHT1_EWSW[18]), .B0(n1395), .B1(
DMP_SHT2_EWSW[18]), .Y(n712) );
AO22XLTS U1748 ( .A0(n1398), .A1(DMP_EXP_EWSW[19]), .B0(n1397), .B1(
DMP_SHT1_EWSW[19]), .Y(n710) );
AO22XLTS U1749 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1395), .B1(
DMP_SHT2_EWSW[19]), .Y(n709) );
AO22XLTS U1750 ( .A0(n1430), .A1(DMP_SFG[19]), .B0(n1516), .B1(
DMP_SHT2_EWSW[19]), .Y(n708) );
AO22XLTS U1751 ( .A0(n1398), .A1(DMP_EXP_EWSW[20]), .B0(n1387), .B1(
DMP_SHT1_EWSW[20]), .Y(n707) );
AO22XLTS U1752 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n1395), .B1(
DMP_SHT2_EWSW[20]), .Y(n706) );
AO22XLTS U1753 ( .A0(n1398), .A1(DMP_EXP_EWSW[21]), .B0(n1388), .B1(
DMP_SHT1_EWSW[21]), .Y(n704) );
AO22XLTS U1754 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n1395), .B1(
DMP_SHT2_EWSW[21]), .Y(n703) );
AO22XLTS U1755 ( .A0(n1398), .A1(DMP_EXP_EWSW[22]), .B0(n1397), .B1(
DMP_SHT1_EWSW[22]), .Y(n701) );
AO22XLTS U1756 ( .A0(n1399), .A1(DMP_SHT1_EWSW[22]), .B0(n1385), .B1(
DMP_SHT2_EWSW[22]), .Y(n700) );
AO22XLTS U1757 ( .A0(n1430), .A1(DMP_SFG[22]), .B0(n1516), .B1(
DMP_SHT2_EWSW[22]), .Y(n699) );
AO22XLTS U1758 ( .A0(n1398), .A1(DMP_EXP_EWSW[23]), .B0(n1397), .B1(
DMP_SHT1_EWSW[23]), .Y(n698) );
AO22XLTS U1759 ( .A0(n1399), .A1(DMP_SHT1_EWSW[23]), .B0(n1385), .B1(
DMP_SHT2_EWSW[23]), .Y(n697) );
AO22XLTS U1760 ( .A0(n1523), .A1(DMP_SHT2_EWSW[23]), .B0(n1507), .B1(
DMP_SFG[23]), .Y(n696) );
AO22XLTS U1761 ( .A0(n1546), .A1(DMP_SFG[23]), .B0(n1629), .B1(
DMP_exp_NRM_EW[0]), .Y(n695) );
AO22XLTS U1762 ( .A0(n1398), .A1(DMP_EXP_EWSW[24]), .B0(n1397), .B1(
DMP_SHT1_EWSW[24]), .Y(n693) );
AO22XLTS U1763 ( .A0(n1399), .A1(DMP_SHT1_EWSW[24]), .B0(n1395), .B1(
DMP_SHT2_EWSW[24]), .Y(n692) );
AO22XLTS U1764 ( .A0(n1510), .A1(DMP_SHT2_EWSW[24]), .B0(n1507), .B1(
DMP_SFG[24]), .Y(n691) );
AO22XLTS U1765 ( .A0(n1546), .A1(DMP_SFG[24]), .B0(n1629), .B1(
DMP_exp_NRM_EW[1]), .Y(n690) );
AO22XLTS U1766 ( .A0(n1398), .A1(DMP_EXP_EWSW[25]), .B0(n1397), .B1(
DMP_SHT1_EWSW[25]), .Y(n688) );
AO22XLTS U1767 ( .A0(n1399), .A1(DMP_SHT1_EWSW[25]), .B0(n1395), .B1(
DMP_SHT2_EWSW[25]), .Y(n687) );
AO22XLTS U1768 ( .A0(n1516), .A1(DMP_SHT2_EWSW[25]), .B0(n1507), .B1(
DMP_SFG[25]), .Y(n686) );
AO22XLTS U1769 ( .A0(n1546), .A1(DMP_SFG[25]), .B0(n1629), .B1(
DMP_exp_NRM_EW[2]), .Y(n685) );
AO22XLTS U1770 ( .A0(n1398), .A1(DMP_EXP_EWSW[26]), .B0(n1397), .B1(
DMP_SHT1_EWSW[26]), .Y(n683) );
AO22XLTS U1771 ( .A0(busy), .A1(DMP_SHT1_EWSW[26]), .B0(n1395), .B1(
DMP_SHT2_EWSW[26]), .Y(n682) );
AO22XLTS U1772 ( .A0(n1523), .A1(DMP_SHT2_EWSW[26]), .B0(n1507), .B1(
DMP_SFG[26]), .Y(n681) );
AO22XLTS U1773 ( .A0(n1546), .A1(DMP_SFG[26]), .B0(n1629), .B1(
DMP_exp_NRM_EW[3]), .Y(n680) );
AO22XLTS U1774 ( .A0(n1398), .A1(n955), .B0(n1397), .B1(DMP_SHT1_EWSW[27]),
.Y(n678) );
AO22XLTS U1775 ( .A0(n1399), .A1(DMP_SHT1_EWSW[27]), .B0(n1395), .B1(
DMP_SHT2_EWSW[27]), .Y(n677) );
AO22XLTS U1776 ( .A0(n1516), .A1(DMP_SHT2_EWSW[27]), .B0(n980), .B1(
DMP_SFG[27]), .Y(n676) );
AO22XLTS U1777 ( .A0(n1546), .A1(DMP_SFG[27]), .B0(n1629), .B1(
DMP_exp_NRM_EW[4]), .Y(n675) );
AO22XLTS U1778 ( .A0(n1398), .A1(DMP_EXP_EWSW[28]), .B0(n1397), .B1(
DMP_SHT1_EWSW[28]), .Y(n673) );
AO22XLTS U1779 ( .A0(n1399), .A1(DMP_SHT1_EWSW[28]), .B0(n1395), .B1(
DMP_SHT2_EWSW[28]), .Y(n672) );
AO22XLTS U1780 ( .A0(n1523), .A1(DMP_SHT2_EWSW[28]), .B0(n1507), .B1(
DMP_SFG[28]), .Y(n671) );
INVX4TS U1781 ( .A(n1441), .Y(n1440) );
AO22XLTS U1782 ( .A0(n1440), .A1(DMP_SFG[28]), .B0(n1629), .B1(
DMP_exp_NRM_EW[5]), .Y(n670) );
AO22XLTS U1783 ( .A0(n1398), .A1(DMP_EXP_EWSW[29]), .B0(n1397), .B1(
DMP_SHT1_EWSW[29]), .Y(n668) );
AO22XLTS U1784 ( .A0(n1399), .A1(DMP_SHT1_EWSW[29]), .B0(n1395), .B1(
DMP_SHT2_EWSW[29]), .Y(n667) );
AO22XLTS U1785 ( .A0(n1523), .A1(DMP_SHT2_EWSW[29]), .B0(n1507), .B1(
DMP_SFG[29]), .Y(n666) );
AO22XLTS U1786 ( .A0(n1546), .A1(DMP_SFG[29]), .B0(n1629), .B1(
DMP_exp_NRM_EW[6]), .Y(n665) );
AO22XLTS U1787 ( .A0(n1527), .A1(DMP_EXP_EWSW[30]), .B0(n1397), .B1(
DMP_SHT1_EWSW[30]), .Y(n663) );
AO22XLTS U1788 ( .A0(n1399), .A1(DMP_SHT1_EWSW[30]), .B0(n1395), .B1(
DMP_SHT2_EWSW[30]), .Y(n662) );
AO22XLTS U1789 ( .A0(n1523), .A1(DMP_SHT2_EWSW[30]), .B0(n1507), .B1(
DMP_SFG[30]), .Y(n661) );
AO22XLTS U1790 ( .A0(n1440), .A1(DMP_SFG[30]), .B0(n1629), .B1(
DMP_exp_NRM_EW[7]), .Y(n660) );
AO22XLTS U1791 ( .A0(n1396), .A1(DmP_EXP_EWSW[16]), .B0(n1626), .B1(
DmP_mant_SHT1_SW[16]), .Y(n625) );
AO22XLTS U1792 ( .A0(n1396), .A1(DmP_EXP_EWSW[17]), .B0(n1387), .B1(
DmP_mant_SHT1_SW[17]), .Y(n623) );
AO22XLTS U1793 ( .A0(n1396), .A1(DmP_EXP_EWSW[19]), .B0(n1387), .B1(n948),
.Y(n619) );
AO22XLTS U1794 ( .A0(n1396), .A1(DmP_EXP_EWSW[21]), .B0(n1387), .B1(
DmP_mant_SHT1_SW[21]), .Y(n615) );
OAI222X1TS U1795 ( .A0(n1392), .A1(n1618), .B0(n1542), .B1(
Shift_reg_FLAGS_7_6), .C0(n1526), .C1(n1389), .Y(n611) );
OAI222X1TS U1796 ( .A0(n1392), .A1(n1544), .B0(n1621), .B1(
Shift_reg_FLAGS_7_6), .C0(n1630), .C1(n1389), .Y(n610) );
OAI222X1TS U1797 ( .A0(n1392), .A1(n1545), .B0(n1616), .B1(
Shift_reg_FLAGS_7_6), .C0(n1390), .C1(n1389), .Y(n609) );
NOR2XLTS U1798 ( .A(n1393), .B(n1660), .Y(n1394) );
AO21XLTS U1799 ( .A0(underflow_flag), .A1(n965), .B0(n1394), .Y(n607) );
AO22XLTS U1800 ( .A0(n1396), .A1(ZERO_FLAG_EXP), .B0(n1387), .B1(
ZERO_FLAG_SHT1), .Y(n605) );
AO22XLTS U1801 ( .A0(n1399), .A1(ZERO_FLAG_SHT1), .B0(n1395), .B1(
ZERO_FLAG_SHT2), .Y(n604) );
AO22XLTS U1802 ( .A0(n1523), .A1(ZERO_FLAG_SHT2), .B0(n1517), .B1(
ZERO_FLAG_SFG), .Y(n603) );
AO22XLTS U1803 ( .A0(n1546), .A1(ZERO_FLAG_SFG), .B0(n1629), .B1(
ZERO_FLAG_NRM), .Y(n602) );
AO22XLTS U1804 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n965), .B1(zero_flag), .Y(n600) );
AO22XLTS U1805 ( .A0(n1396), .A1(OP_FLAG_EXP), .B0(OP_FLAG_SHT1), .B1(n1626),
.Y(n599) );
AO22XLTS U1806 ( .A0(n1399), .A1(OP_FLAG_SHT1), .B0(n1628), .B1(OP_FLAG_SHT2), .Y(n598) );
AO22XLTS U1807 ( .A0(n1506), .A1(OP_FLAG_SFG), .B0(n1516), .B1(OP_FLAG_SHT2),
.Y(n597) );
AO22XLTS U1808 ( .A0(n1398), .A1(SIGN_FLAG_EXP), .B0(n1397), .B1(
SIGN_FLAG_SHT1), .Y(n596) );
AO22XLTS U1809 ( .A0(n1399), .A1(SIGN_FLAG_SHT1), .B0(n1628), .B1(
SIGN_FLAG_SHT2), .Y(n595) );
AO22XLTS U1810 ( .A0(n1523), .A1(SIGN_FLAG_SHT2), .B0(n1517), .B1(
SIGN_FLAG_SFG), .Y(n594) );
AO22XLTS U1811 ( .A0(n1440), .A1(SIGN_FLAG_SFG), .B0(n1629), .B1(
SIGN_FLAG_NRM), .Y(n593) );
INVX2TS U1812 ( .A(OP_FLAG_SFG), .Y(n1400) );
AOI2BB2XLTS U1813 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n963), .A0N(n1400), .A1N(
DmP_mant_SFG_SWR[12]), .Y(intadd_38_CI) );
AOI22X1TS U1814 ( .A0(n1440), .A1(intadd_38_SUM_0_), .B0(n1550), .B1(n1441),
.Y(n590) );
AOI2BB2XLTS U1815 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n963), .A0N(n1400), .A1N(
DmP_mant_SFG_SWR[13]), .Y(intadd_38_B_1_) );
AOI2BB2XLTS U1816 ( .B0(n1440), .B1(intadd_38_SUM_1_), .A0N(
Raw_mant_NRM_SWR[13]), .A1N(n1546), .Y(n589) );
AOI2BB2XLTS U1817 ( .B0(DmP_mant_SFG_SWR[14]), .B1(n963), .A0N(n1400), .A1N(
DmP_mant_SFG_SWR[14]), .Y(intadd_38_B_2_) );
AOI22X1TS U1818 ( .A0(n1446), .A1(intadd_38_SUM_2_), .B0(n1548), .B1(n1441),
.Y(n588) );
AOI2BB2XLTS U1819 ( .B0(DmP_mant_SFG_SWR[15]), .B1(n963), .A0N(n963), .A1N(
DmP_mant_SFG_SWR[15]), .Y(intadd_38_B_3_) );
AOI2BB2XLTS U1820 ( .B0(n1440), .B1(intadd_38_SUM_3_), .A0N(
Raw_mant_NRM_SWR[15]), .A1N(n1546), .Y(n587) );
AOI2BB2XLTS U1821 ( .B0(DmP_mant_SFG_SWR[16]), .B1(n1400), .A0N(n1400),
.A1N(DmP_mant_SFG_SWR[16]), .Y(intadd_38_B_4_) );
AOI22X1TS U1822 ( .A0(n1446), .A1(intadd_38_SUM_4_), .B0(n1606), .B1(n1441),
.Y(n586) );
AOI22X1TS U1823 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n1400), .B0(n1425), .B1(
n975), .Y(intadd_38_B_5_) );
AOI22X1TS U1824 ( .A0(n1446), .A1(intadd_38_SUM_5_), .B0(n1570), .B1(n1441),
.Y(n585) );
AOI2BB2XLTS U1825 ( .B0(DmP_mant_SFG_SWR[18]), .B1(n1400), .A0N(n963), .A1N(
DmP_mant_SFG_SWR[18]), .Y(intadd_38_B_6_) );
AOI2BB2XLTS U1826 ( .B0(n1440), .B1(intadd_38_SUM_6_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1546), .Y(n584) );
AOI2BB2XLTS U1827 ( .B0(DmP_mant_SFG_SWR[19]), .B1(n963), .A0N(n963), .A1N(
DmP_mant_SFG_SWR[19]), .Y(intadd_38_B_7_) );
AOI2BB2XLTS U1828 ( .B0(n1440), .B1(intadd_38_SUM_7_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1546), .Y(n583) );
AOI22X1TS U1829 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n1661), .B0(OP_FLAG_SFG),
.B1(n974), .Y(intadd_38_B_8_) );
AOI2BB2XLTS U1830 ( .B0(n1440), .B1(intadd_38_SUM_8_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1546), .Y(n582) );
AOI22X1TS U1831 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n963), .B0(n1425), .B1(n973), .Y(intadd_38_B_9_) );
AOI22X1TS U1832 ( .A0(n1446), .A1(intadd_38_SUM_9_), .B0(n1562), .B1(n1441),
.Y(n581) );
AOI2BB2XLTS U1833 ( .B0(DmP_mant_SFG_SWR[22]), .B1(n1400), .A0N(n1661),
.A1N(DmP_mant_SFG_SWR[22]), .Y(intadd_38_B_10_) );
AOI22X1TS U1834 ( .A0(n1446), .A1(intadd_38_SUM_10_), .B0(n1525), .B1(n1441),
.Y(n580) );
AOI2BB2XLTS U1835 ( .B0(DmP_mant_SFG_SWR[23]), .B1(n963), .A0N(n963), .A1N(
DmP_mant_SFG_SWR[23]), .Y(intadd_38_B_11_) );
AOI22X1TS U1836 ( .A0(n1440), .A1(intadd_38_SUM_11_), .B0(n926), .B1(n1441),
.Y(n579) );
AOI22X1TS U1837 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1400), .B0(n1425), .B1(
n972), .Y(intadd_38_B_12_) );
AOI22X1TS U1838 ( .A0(n1446), .A1(intadd_38_SUM_12_), .B0(n1524), .B1(n1441),
.Y(n578) );
AOI22X1TS U1839 ( .A0(DmP_mant_SFG_SWR[25]), .A1(OP_FLAG_SFG), .B0(n1661),
.B1(n976), .Y(n1401) );
XNOR2X1TS U1840 ( .A(intadd_38_n1), .B(n1401), .Y(n1402) );
AOI22X1TS U1841 ( .A0(n1446), .A1(n1402), .B0(n1547), .B1(n1441), .Y(n577)
);
AOI22X1TS U1842 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n963), .B0(n1425), .B1(n970),
.Y(intadd_39_CI) );
INVX2TS U1843 ( .A(intadd_39_B_2_), .Y(n1406) );
NAND2BXLTS U1844 ( .AN(intadd_39_CI), .B(DMP_SFG[2]), .Y(n1404) );
AOI222X1TS U1845 ( .A0(DMP_SFG[4]), .A1(n1406), .B0(DMP_SFG[4]), .B1(n1405),
.C0(n1406), .C1(n1405), .Y(n1408) );
AOI2BB2X1TS U1846 ( .B0(DmP_mant_SFG_SWR[7]), .B1(OP_FLAG_SFG), .A0N(n1425),
.A1N(DmP_mant_SFG_SWR[7]), .Y(n1407) );
NAND2X1TS U1847 ( .A(n1407), .B(DMP_SFG[5]), .Y(n1442) );
NOR2X1TS U1848 ( .A(n1407), .B(DMP_SFG[5]), .Y(n1443) );
AOI21X1TS U1849 ( .A0(n1408), .A1(n1442), .B0(n1443), .Y(intadd_40_B_0_) );
AOI2BB2XLTS U1850 ( .B0(n1409), .B1(DMP_SFG[9]), .A0N(DMP_SFG[9]), .A1N(
n1409), .Y(n1410) );
XNOR2X1TS U1851 ( .A(intadd_40_n1), .B(n1410), .Y(n1411) );
AOI22X1TS U1852 ( .A0(n1446), .A1(n1411), .B0(n1549), .B1(n1441), .Y(n575)
);
AOI22X1TS U1853 ( .A0(Data_array_SWR[13]), .A1(n1001), .B0(Data_array_SWR[9]), .B1(n997), .Y(n1414) );
AOI22X1TS U1854 ( .A0(Data_array_SWR[5]), .A1(n998), .B0(Data_array_SWR[1]),
.B1(n928), .Y(n1413) );
OAI211X1TS U1855 ( .A0(n1419), .A1(n1531), .B0(n1414), .C0(n1413), .Y(n1499)
);
AOI22X1TS U1856 ( .A0(Data_array_SWR[24]), .A1(n1492), .B0(n1496), .B1(n1499), .Y(n1415) );
AOI22X1TS U1857 ( .A0(n961), .A1(n1415), .B0(n1506), .B1(n966), .Y(n573) );
AOI22X1TS U1858 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1661), .B0(n1425), .B1(n966), .Y(n1416) );
AOI2BB2XLTS U1859 ( .B0(n1440), .B1(n1416), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n1440), .Y(n572) );
AOI22X1TS U1860 ( .A0(Data_array_SWR[12]), .A1(n998), .B0(Data_array_SWR[16]), .B1(n997), .Y(n1418) );
AOI22X1TS U1861 ( .A0(Data_array_SWR[20]), .A1(n1001), .B0(
Data_array_SWR[24]), .B1(n1450), .Y(n1417) );
NAND2X1TS U1862 ( .A(n1418), .B(n1417), .Y(n1493) );
INVX2TS U1863 ( .A(n1419), .Y(n1491) );
AOI22X1TS U1864 ( .A0(n961), .A1(n1489), .B0(n968), .B1(n1506), .Y(n570) );
AOI22X1TS U1865 ( .A0(Data_array_SWR[12]), .A1(n1001), .B0(Data_array_SWR[8]), .B1(n997), .Y(n1423) );
AOI22X1TS U1866 ( .A0(Data_array_SWR[4]), .A1(n998), .B0(Data_array_SWR[0]),
.B1(n928), .Y(n1422) );
OAI211X1TS U1867 ( .A0(n1465), .A1(n1531), .B0(n1423), .C0(n1422), .Y(n1519)
);
AOI22X1TS U1868 ( .A0(Data_array_SWR[25]), .A1(n1492), .B0(n1496), .B1(n1519), .Y(n1424) );
AOI22X1TS U1869 ( .A0(n961), .A1(n1424), .B0(n969), .B1(n980), .Y(n565) );
AOI22X1TS U1870 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n963), .B0(n1425), .B1(n969),
.Y(n1426) );
AOI2BB2XLTS U1871 ( .B0(n1440), .B1(n1426), .A0N(n962), .A1N(n1440), .Y(n564) );
OAI22X1TS U1872 ( .A0(n1541), .A1(n1427), .B0(n1607), .B1(n1448), .Y(n1429)
);
INVX2TS U1873 ( .A(n998), .Y(n1437) );
OAI22X1TS U1874 ( .A0(n1483), .A1(n1531), .B0(n1614), .B1(n1437), .Y(n1428)
);
AOI211X1TS U1875 ( .A0(Data_array_SWR[2]), .A1(n928), .B0(n1429), .C0(n1428),
.Y(n1497) );
OAI22X1TS U1876 ( .A0(n1520), .A1(n1497), .B0(n1613), .B1(n1467), .Y(n1488)
);
OAI21XLTS U1877 ( .A0(n1431), .A1(DMP_SFG[0]), .B0(n1433), .Y(n1432) );
AOI22X1TS U1878 ( .A0(n1446), .A1(n1432), .B0(n1553), .B1(n1441), .Y(n562)
);
XNOR2X1TS U1879 ( .A(DMP_SFG[1]), .B(n1433), .Y(n1435) );
XNOR2X1TS U1880 ( .A(n1435), .B(n1434), .Y(n1436) );
AOI22X1TS U1881 ( .A0(n1446), .A1(n1436), .B0(n1604), .B1(n1441), .Y(n561)
);
AO22XLTS U1882 ( .A0(Data_array_SWR[15]), .A1(n1001), .B0(Data_array_SWR[11]), .B1(n997), .Y(n1439) );
OAI22X1TS U1883 ( .A0(n1453), .A1(n1531), .B0(n1615), .B1(n1437), .Y(n1438)
);
AOI211X1TS U1884 ( .A0(Data_array_SWR[3]), .A1(n928), .B0(n1439), .C0(n1438),
.Y(n1494) );
OAI22X1TS U1885 ( .A0(n1520), .A1(n1494), .B0(n1612), .B1(n1467), .Y(n1487)
);
AO22XLTS U1886 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[3]), .B0(n1510), .B1(n1487), .Y(n558) );
AOI22X1TS U1887 ( .A0(n1446), .A1(intadd_39_SUM_0_), .B0(n1528), .B1(n1441),
.Y(n557) );
AOI2BB2XLTS U1888 ( .B0(n1440), .B1(intadd_39_SUM_1_), .A0N(
Raw_mant_NRM_SWR[5]), .A1N(n1546), .Y(n556) );
AOI22X1TS U1889 ( .A0(n1446), .A1(intadd_39_SUM_2_), .B0(n1558), .B1(n1441),
.Y(n555) );
NAND2BXLTS U1890 ( .AN(n1443), .B(n1442), .Y(n1444) );
XNOR2X1TS U1891 ( .A(intadd_39_n1), .B(n1444), .Y(n1445) );
AOI22X1TS U1892 ( .A0(n1446), .A1(n1445), .B0(n1552), .B1(n1441), .Y(n554)
);
AOI22X1TS U1893 ( .A0(Data_array_SWR[10]), .A1(n998), .B0(Data_array_SWR[18]), .B1(n1001), .Y(n1447) );
OAI21XLTS U1894 ( .A0(n1541), .A1(n1448), .B0(n1447), .Y(n1449) );
AOI21X1TS U1895 ( .A0(Data_array_SWR[22]), .A1(n1450), .B0(n1449), .Y(n1452)
);
OAI222X1TS U1896 ( .A0(n1495), .A1(n1614), .B0(n1520), .B1(n1452), .C0(n1484), .C1(n1453), .Y(n1451) );
AO22XLTS U1897 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[6]), .B0(n1510), .B1(n1451), .Y(n553) );
AO22XLTS U1898 ( .A0(n1498), .A1(n1451), .B0(final_result_ieee[4]), .B1(
n1660), .Y(n552) );
OAI222X1TS U1899 ( .A0(n1467), .A1(n1614), .B0(n1466), .B1(n1453), .C0(n1496), .C1(n1452), .Y(n1511) );
AO22XLTS U1900 ( .A0(n1498), .A1(n1511), .B0(final_result_ieee[17]), .B1(
n1660), .Y(n551) );
AOI22X1TS U1901 ( .A0(Data_array_SWR[20]), .A1(n944), .B0(Data_array_SWR[24]), .B1(n945), .Y(n1471) );
AOI22X1TS U1902 ( .A0(Data_array_SWR[12]), .A1(n997), .B0(Data_array_SWR[8]),
.B1(n998), .Y(n1455) );
NAND2X1TS U1903 ( .A(Data_array_SWR[16]), .B(n1001), .Y(n1454) );
OAI211X1TS U1904 ( .A0(n1471), .A1(n1531), .B0(n1455), .C0(n1454), .Y(n1458)
);
AOI22X1TS U1905 ( .A0(n961), .A1(n1457), .B0(n970), .B1(n980), .Y(n550) );
INVX2TS U1906 ( .A(n1498), .Y(n1500) );
OAI2BB2XLTS U1907 ( .B0(n1457), .B1(n1500), .A0N(final_result_ieee[2]),
.A1N(n1660), .Y(n549) );
OAI2BB2XLTS U1908 ( .B0(n1513), .B1(n1500), .A0N(final_result_ieee[19]),
.A1N(n1660), .Y(n548) );
AOI22X1TS U1909 ( .A0(Data_array_SWR[12]), .A1(n1521), .B0(
Data_array_SWR[13]), .B1(n1492), .Y(n1459) );
OAI221X1TS U1910 ( .A0(n1520), .A1(n1461), .B0(n1496), .B1(n1462), .C0(n1459), .Y(n1501) );
AO22XLTS U1911 ( .A0(n1498), .A1(n1501), .B0(final_result_ieee[10]), .B1(
n1660), .Y(n547) );
AOI22X1TS U1912 ( .A0(Data_array_SWR[12]), .A1(n1492), .B0(
Data_array_SWR[13]), .B1(n1521), .Y(n1460) );
OAI221X1TS U1913 ( .A0(n1520), .A1(n1462), .B0(n1496), .B1(n1461), .C0(n1460), .Y(n1502) );
AO22XLTS U1914 ( .A0(n1498), .A1(n1502), .B0(final_result_ieee[11]), .B1(
n1660), .Y(n546) );
AO22XLTS U1915 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[9]), .B0(n1510), .B1(n1463), .Y(n545) );
OAI222X1TS U1916 ( .A0(n1467), .A1(n1619), .B0(n1466), .B1(n1465), .C0(n1496), .C1(n1464), .Y(n1505) );
AO22XLTS U1917 ( .A0(n1498), .A1(n1505), .B0(final_result_ieee[14]), .B1(
n965), .Y(n543) );
AOI22X1TS U1918 ( .A0(Data_array_SWR[13]), .A1(n997), .B0(Data_array_SWR[9]),
.B1(n998), .Y(n1470) );
AOI22X1TS U1919 ( .A0(Data_array_SWR[17]), .A1(n1001), .B0(
shift_value_SHT2_EWR[4]), .B1(n1468), .Y(n1469) );
NAND2X1TS U1920 ( .A(n1470), .B(n1469), .Y(n1475) );
INVX2TS U1921 ( .A(n1471), .Y(n1474) );
AOI22X1TS U1922 ( .A0(n961), .A1(n1473), .B0(n971), .B1(n1517), .Y(n542) );
OAI2BB2XLTS U1923 ( .B0(n1473), .B1(n1500), .A0N(final_result_ieee[3]),
.A1N(n1660), .Y(n541) );
OAI2BB2XLTS U1924 ( .B0(n1512), .B1(n1500), .A0N(final_result_ieee[18]),
.A1N(n1660), .Y(n540) );
AOI22X1TS U1925 ( .A0(Data_array_SWR[14]), .A1(n1521), .B0(
Data_array_SWR[11]), .B1(n1492), .Y(n1476) );
OAI221X1TS U1926 ( .A0(n1520), .A1(n1478), .B0(n1496), .B1(n1477), .C0(n1476), .Y(n1503) );
AO22XLTS U1927 ( .A0(n1498), .A1(n1503), .B0(final_result_ieee[12]), .B1(
n965), .Y(n538) );
AOI22X1TS U1928 ( .A0(Data_array_SWR[10]), .A1(n1521), .B0(
Data_array_SWR[15]), .B1(n1492), .Y(n1479) );
OAI221X1TS U1929 ( .A0(n1520), .A1(n1481), .B0(n1496), .B1(n1480), .C0(n1479), .Y(n1482) );
AO22XLTS U1930 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[10]), .B0(n1510), .B1(
n1482), .Y(n537) );
AO22XLTS U1931 ( .A0(n1498), .A1(n1482), .B0(final_result_ieee[8]), .B1(n965), .Y(n536) );
OAI222X1TS U1932 ( .A0(n1495), .A1(n1615), .B0(n1520), .B1(n1485), .C0(n1484), .C1(n1483), .Y(n1486) );
AO22XLTS U1933 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[7]), .B0(n1510), .B1(n1486), .Y(n534) );
AO22XLTS U1934 ( .A0(n1498), .A1(n1486), .B0(final_result_ieee[5]), .B1(n965), .Y(n533) );
AO22XLTS U1935 ( .A0(n1498), .A1(n1487), .B0(final_result_ieee[1]), .B1(n965), .Y(n531) );
AO22XLTS U1936 ( .A0(n1498), .A1(n1488), .B0(final_result_ieee[0]), .B1(n965), .Y(n530) );
OAI2BB2XLTS U1937 ( .B0(n1489), .B1(n1500), .A0N(final_result_ieee[6]),
.A1N(n1660), .Y(n529) );
OAI2BB2XLTS U1938 ( .B0(n1508), .B1(n1500), .A0N(final_result_ieee[15]),
.A1N(n1660), .Y(n528) );
OAI22X1TS U1939 ( .A0(n1494), .A1(n1496), .B0(n1612), .B1(n1495), .Y(n1514)
);
AO22XLTS U1940 ( .A0(n1498), .A1(n1514), .B0(final_result_ieee[20]), .B1(
n965), .Y(n527) );
OAI22X1TS U1941 ( .A0(n1497), .A1(n1496), .B0(n1613), .B1(n1495), .Y(n1515)
);
AO22XLTS U1942 ( .A0(n1498), .A1(n1515), .B0(final_result_ieee[21]), .B1(
n965), .Y(n526) );
AOI22X1TS U1943 ( .A0(Data_array_SWR[24]), .A1(n1521), .B0(n1520), .B1(n1499), .Y(n1518) );
OAI2BB2XLTS U1944 ( .B0(n1518), .B1(n1500), .A0N(final_result_ieee[22]),
.A1N(n1660), .Y(n525) );
AO22XLTS U1945 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[12]), .B0(n1510), .B1(
n1501), .Y(n524) );
AO22XLTS U1946 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[13]), .B0(n1510), .B1(
n1502), .Y(n523) );
AO22XLTS U1947 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[14]), .B0(n1510), .B1(
n1503), .Y(n522) );
AO22XLTS U1948 ( .A0(n980), .A1(DmP_mant_SFG_SWR[15]), .B0(n1516), .B1(n1504), .Y(n521) );
AO22XLTS U1949 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[16]), .B0(n1510), .B1(
n1505), .Y(n520) );
AOI22X1TS U1950 ( .A0(n961), .A1(n1508), .B0(n1507), .B1(n975), .Y(n519) );
AO22XLTS U1951 ( .A0(n980), .A1(DmP_mant_SFG_SWR[18]), .B0(n1510), .B1(n1509), .Y(n518) );
AO22XLTS U1952 ( .A0(n980), .A1(DmP_mant_SFG_SWR[19]), .B0(n1516), .B1(n1511), .Y(n517) );
AOI22X1TS U1953 ( .A0(n961), .A1(n1512), .B0(n1517), .B1(n974), .Y(n516) );
AOI22X1TS U1954 ( .A0(n961), .A1(n1513), .B0(n1517), .B1(n973), .Y(n515) );
AO22XLTS U1955 ( .A0(n980), .A1(DmP_mant_SFG_SWR[22]), .B0(n1516), .B1(n1514), .Y(n514) );
AO22XLTS U1956 ( .A0(n980), .A1(DmP_mant_SFG_SWR[23]), .B0(n1516), .B1(n1515), .Y(n513) );
AOI22X1TS U1957 ( .A0(n961), .A1(n1518), .B0(n1517), .B1(n972), .Y(n512) );
AOI22X1TS U1958 ( .A0(Data_array_SWR[25]), .A1(n1521), .B0(n1520), .B1(n1519), .Y(n1522) );
AOI22X1TS U1959 ( .A0(n961), .A1(n1522), .B0(n976), .B1(n980), .Y(n511) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk30.tcl_GDAN16M4P4_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD2_1_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD2_1_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog wrapper for dlygate4sd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlygate4sd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlygate4sd2_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dlygate4sd2 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlygate4sd2_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlygate4sd2 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD2_1_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:13:33 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57,
n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110,
n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132,
n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148;
OAI21X2TS U46 ( .A0(n113), .A1(n112), .B0(n46), .Y(res[16]) );
NAND2XLTS U47 ( .A(n68), .B(n117), .Y(n119) );
NAND2XLTS U48 ( .A(n39), .B(n114), .Y(n116) );
NAND2X4TS U49 ( .A(n113), .B(n71), .Y(n46) );
CLKBUFX2TS U50 ( .A(n137), .Y(n33) );
OR2X2TS U51 ( .A(n78), .B(in1[14]), .Y(n39) );
OAI21X1TS U52 ( .A0(n76), .A1(in2[14]), .B0(add_sub), .Y(n74) );
INVX4TS U53 ( .A(n34), .Y(n48) );
NAND2X1TS U54 ( .A(n76), .B(add_sub), .Y(n77) );
CLKXOR2X2TS U55 ( .A(n80), .B(in2[13]), .Y(n81) );
NOR2XLTS U56 ( .A(n79), .B(n101), .Y(n80) );
NAND2XLTS U57 ( .A(n82), .B(add_sub), .Y(n83) );
NAND2BX2TS U58 ( .AN(in2[13]), .B(n79), .Y(n76) );
NOR2X2TS U59 ( .A(n82), .B(in2[12]), .Y(n79) );
NAND2X1TS U60 ( .A(n86), .B(add_sub), .Y(n87) );
NAND2X2TS U61 ( .A(in1[8]), .B(n70), .Y(n31) );
NAND2BX2TS U62 ( .AN(in2[9]), .B(n102), .Y(n86) );
NOR2X4TS U63 ( .A(n99), .B(in2[8]), .Y(n102) );
NAND2X1TS U64 ( .A(n99), .B(add_sub), .Y(n100) );
NAND2X4TS U65 ( .A(n127), .B(in1[6]), .Y(n97) );
NOR2X6TS U66 ( .A(n95), .B(in2[6]), .Y(n88) );
OR2X6TS U67 ( .A(n137), .B(in1[5]), .Y(n69) );
NAND2X4TS U68 ( .A(n95), .B(add_sub), .Y(n96) );
INVX3TS U69 ( .A(n67), .Y(n54) );
INVX6TS U70 ( .A(n133), .Y(n94) );
INVX8TS U71 ( .A(in2[3]), .Y(n62) );
INVX6TS U72 ( .A(in2[2]), .Y(n63) );
INVX6TS U73 ( .A(in2[1]), .Y(n64) );
INVX6TS U74 ( .A(in2[0]), .Y(n65) );
NOR2XLTS U75 ( .A(n102), .B(n101), .Y(n103) );
NAND2X1TS U76 ( .A(add_sub), .B(in2[0]), .Y(n130) );
OR2X4TS U77 ( .A(n92), .B(n101), .Y(n93) );
NOR2XLTS U78 ( .A(n84), .B(n101), .Y(n85) );
ADDHXLTS U79 ( .A(in2[0]), .B(in1[0]), .CO(n140), .S(res[0]) );
NAND2X4TS U80 ( .A(n50), .B(n48), .Y(n47) );
XNOR2X2TS U81 ( .A(n83), .B(in2[12]), .Y(n109) );
NAND2BX4TS U82 ( .AN(in2[11]), .B(n84), .Y(n82) );
XNOR2X2TS U83 ( .A(n87), .B(in2[10]), .Y(n111) );
NOR2X4TS U84 ( .A(n86), .B(in2[10]), .Y(n84) );
NOR2X4TS U85 ( .A(in2[4]), .B(in2[3]), .Y(n72) );
XOR2X1TS U86 ( .A(n116), .B(n115), .Y(res[14]) );
AND2X2TS U87 ( .A(n71), .B(n112), .Y(n38) );
OR2X4TS U88 ( .A(n75), .B(in1[15]), .Y(n71) );
NAND2X2TS U89 ( .A(n75), .B(in1[15]), .Y(n112) );
OR2X4TS U90 ( .A(n81), .B(in1[13]), .Y(n68) );
XOR2X1TS U91 ( .A(n129), .B(n128), .Y(res[6]) );
XOR2X1TS U92 ( .A(n139), .B(n138), .Y(res[5]) );
OAI21X1TS U93 ( .A0(n33), .A1(in1[5]), .B0(n126), .Y(n129) );
NAND2BX1TS U94 ( .AN(n132), .B(n131), .Y(n134) );
OAI211X1TS U95 ( .A0(in1[2]), .A1(n143), .B0(in1[1]), .C0(n141), .Y(n132) );
OAI21X1TS U96 ( .A0(in2[0]), .A1(in2[1]), .B0(add_sub), .Y(n124) );
NAND2X8TS U97 ( .A(n47), .B(n49), .Y(n113) );
NAND2X8TS U98 ( .A(n44), .B(n121), .Y(n70) );
XOR3X1TS U99 ( .A(n70), .B(in1[8]), .C(n120), .Y(res[8]) );
NAND2X2TS U100 ( .A(n120), .B(n70), .Y(n30) );
NAND2X2TS U101 ( .A(in1[8]), .B(n120), .Y(n32) );
NAND3X6TS U102 ( .A(n31), .B(n30), .C(n32), .Y(n105) );
XNOR2X4TS U103 ( .A(n100), .B(in2[8]), .Y(n120) );
NOR2X4TS U104 ( .A(n101), .B(in2[4]), .Y(n60) );
AND2X8TS U105 ( .A(n145), .B(in1[3]), .Y(n66) );
NAND2X8TS U106 ( .A(n90), .B(n73), .Y(n95) );
AND2X6TS U107 ( .A(n92), .B(n72), .Y(n90) );
NOR2X2TS U108 ( .A(n88), .B(n101), .Y(n89) );
XNOR2X2TS U109 ( .A(n74), .B(in2[15]), .Y(n75) );
NOR2X4TS U110 ( .A(n51), .B(n114), .Y(n50) );
NAND2BX4TS U111 ( .AN(in2[7]), .B(n88), .Y(n99) );
NAND2X2TS U112 ( .A(n101), .B(in2[4]), .Y(n59) );
NAND2X6TS U113 ( .A(n58), .B(in2[4]), .Y(n57) );
NAND2X4TS U114 ( .A(n61), .B(n60), .Y(n56) );
AO22XLTS U115 ( .A0(n148), .A1(in1[4]), .B0(n145), .B1(in1[3]), .Y(n125) );
INVX4TS U116 ( .A(n61), .Y(n58) );
XNOR2X2TS U117 ( .A(n77), .B(in2[14]), .Y(n78) );
INVX12TS U118 ( .A(add_sub), .Y(n101) );
NAND2X2TS U119 ( .A(n78), .B(in1[14]), .Y(n114) );
XOR2XLTS U120 ( .A(n148), .B(n147), .Y(res[4]) );
XNOR2X1TS U121 ( .A(n127), .B(in1[6]), .Y(n128) );
NAND2X1TS U122 ( .A(n35), .B(n121), .Y(n123) );
INVX2TS U123 ( .A(in1[9]), .Y(n43) );
XNOR2X1TS U124 ( .A(n33), .B(n136), .Y(n138) );
OR2X1TS U125 ( .A(n145), .B(in1[3]), .Y(n131) );
NOR2X2TS U126 ( .A(n34), .B(n51), .Y(n115) );
NOR2X4TS U127 ( .A(n101), .B(n90), .Y(n91) );
XNOR2X1TS U128 ( .A(n105), .B(n42), .Y(res[9]) );
AND2X8TS U129 ( .A(n118), .B(n68), .Y(n34) );
OR2X4TS U130 ( .A(in1[7]), .B(n98), .Y(n35) );
NAND2X2TS U131 ( .A(n81), .B(in1[13]), .Y(n117) );
OR2X4TS U132 ( .A(n127), .B(in1[6]), .Y(n36) );
NAND2X2TS U133 ( .A(n137), .B(in1[5]), .Y(n37) );
NAND2X2TS U134 ( .A(n98), .B(in1[7]), .Y(n121) );
XOR2X1TS U135 ( .A(n104), .B(n43), .Y(n42) );
CLKXOR2X2TS U136 ( .A(n103), .B(in2[9]), .Y(n104) );
AOI31X1TS U137 ( .A0(n143), .A1(in1[2]), .A2(n131), .B0(n125), .Y(n135) );
XNOR2X2TS U138 ( .A(n124), .B(in2[2]), .Y(n143) );
NAND2X8TS U139 ( .A(n40), .B(n37), .Y(n52) );
NAND2X8TS U140 ( .A(n69), .B(n53), .Y(n40) );
XOR2X2TS U141 ( .A(n113), .B(n38), .Y(res[15]) );
OAI2BB1X4TS U142 ( .A0N(in1[9]), .A1N(n105), .B0(n41), .Y(n110) );
OAI21X4TS U143 ( .A0(n105), .A1(in1[9]), .B0(n104), .Y(n41) );
NAND2X8TS U144 ( .A(n122), .B(n35), .Y(n44) );
XOR2X4TS U145 ( .A(n89), .B(in2[7]), .Y(n98) );
NAND2X8TS U146 ( .A(n45), .B(n97), .Y(n122) );
NAND2X8TS U147 ( .A(n52), .B(n36), .Y(n45) );
NOR3X8TS U148 ( .A(in2[1]), .B(in2[0]), .C(in2[2]), .Y(n92) );
NOR2X8TS U149 ( .A(n118), .B(n117), .Y(n51) );
OAI21X4TS U150 ( .A0(n34), .A1(n51), .B0(n39), .Y(n49) );
NAND2X8TS U151 ( .A(n55), .B(n54), .Y(n53) );
NAND2X8TS U152 ( .A(n66), .B(n94), .Y(n55) );
NAND3X8TS U153 ( .A(n57), .B(n56), .C(n59), .Y(n148) );
NOR2X8TS U154 ( .A(n148), .B(in1[4]), .Y(n133) );
NAND4X8TS U155 ( .A(n65), .B(n64), .C(n63), .D(n62), .Y(n61) );
XNOR2X1TS U156 ( .A(n119), .B(n118), .Y(res[13]) );
XNOR2X1TS U157 ( .A(n123), .B(n122), .Y(res[7]) );
XNOR2X4TS U158 ( .A(n93), .B(in2[3]), .Y(n145) );
XNOR2X4TS U159 ( .A(n96), .B(in2[6]), .Y(n127) );
AND2X4TS U160 ( .A(n148), .B(in1[4]), .Y(n67) );
INVX2TS U161 ( .A(in2[5]), .Y(n73) );
CLKXOR2X2TS U162 ( .A(n85), .B(in2[11]), .Y(n107) );
XOR2X4TS U163 ( .A(n91), .B(in2[5]), .Y(n137) );
ADDFHX4TS U164 ( .A(n107), .B(in1[11]), .CI(n106), .CO(n108), .S(res[11]) );
ADDFHX4TS U165 ( .A(n109), .B(in1[12]), .CI(n108), .CO(n118), .S(res[12]) );
ADDFHX4TS U166 ( .A(n111), .B(in1[10]), .CI(n110), .CO(n106), .S(res[10]) );
OAI2BB2XLTS U167 ( .B0(n135), .B1(n133), .A0N(n137), .A1N(in1[5]), .Y(n126)
);
XNOR2X1TS U168 ( .A(n130), .B(in2[1]), .Y(n141) );
AOI21X1TS U169 ( .A0(n135), .A1(n134), .B0(n133), .Y(n139) );
INVX2TS U170 ( .A(in1[5]), .Y(n136) );
CMPR32X2TS U171 ( .A(in1[1]), .B(n141), .C(n140), .CO(n142), .S(res[1]) );
CMPR32X2TS U172 ( .A(in1[2]), .B(n143), .C(n142), .CO(n144), .S(res[2]) );
CMPR32X2TS U173 ( .A(in1[3]), .B(n145), .C(n144), .CO(n146), .S(res[3]) );
XOR2X1TS U174 ( .A(in1[4]), .B(n146), .Y(n147) );
initial $sdf_annotate("Approx_adder_GeArN8R1P4_syn.sdf");
endmodule
|
/*
* i2s_audio - Convert PCM to i2s
*
* Converts PCM to i2s
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
module i2s_audio (
input clk_i,
input [15:0] left_i,
input [15:0] right_i,
output reg [3:0] i2s_o,
output reg lrclk_o,
output sclk_o
);
// Wire definitions ===========================================================================
// Registers ==================================================================================
reg [5:0] bit_cntr = 0;
reg [3:0] i2s = 0;
reg [63:0] shift_reg = 64'd0;
reg delayed_out = 0;
// Synchronizer chain
reg [15:0] left_buffer[0:2];
reg [15:0] right_buffer[0:2];
// Assignments ================================================================================
assign sclk_o = clk_i;
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Update output lines on negative edge because HDMI chip reads on posedge
always @(negedge clk_i)
begin
lrclk_o <= bit_cntr[5];
i2s_o[0] <= i2s[0];
i2s_o[1] <= i2s[1];
i2s_o[2] <= i2s[2];
i2s_o[3] <= i2s[3];
end
// Repeatedly counts 0-63 bits out
always @(posedge clk_i)
bit_cntr <= bit_cntr + 1'b1;
// Shift the bits out
always @(negedge clk_i)
begin
if( bit_cntr == 6'd63 )
{delayed_out, shift_reg} <= {shift_reg[63],left_buffer[0],16'd0,right_buffer[0],16'd0};
else
{delayed_out,shift_reg} <= {shift_reg,1'b0};
end
// Send MSB to output, note this delays the data by one clock as required for the LRCLK
always @(posedge clk_i)
begin
i2s[0] <= delayed_out;
i2s[1] <= delayed_out;
i2s[2] <= delayed_out;
i2s[3] <= delayed_out;
end
// Synchronizer for input
always @(posedge clk_i)
begin
{left_buffer[0],left_buffer[1],left_buffer[2]} <= {left_buffer[1],left_buffer[2],left_i};
{right_buffer[0],right_buffer[1],right_buffer[2]} <= {right_buffer[1],right_buffer[2],right_i};
end
// Other logic ================================================================================
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3_2_V
`define SKY130_FD_SC_LP__OR3_2_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_TB_V
`define SKY130_FD_SC_HDLL__O2BB2A_TB_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o2bb2a.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_hdll__o2bb2a dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_TB_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg.v
//
// *Module Description:
// Debug interface
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 53 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2010-01-27 19:17:14 +0100 (Mi, 27 Jan 2010) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
module omsp_dbg (
// OUTPUTs
dbg_freeze, // Freeze peripherals
dbg_halt_cmd, // Halt CPU command
dbg_mem_addr, // Debug address for rd/wr access
dbg_mem_dout, // Debug unit data output
dbg_mem_en, // Debug unit memory enable
dbg_mem_wr, // Debug unit memory write
dbg_reg_wr, // Debug unit CPU register write
dbg_reset, // Reset CPU from debug interface
dbg_uart_txd, // Debug interface: UART TXD
// INPUTs
dbg_halt_st, // Halt/Run status from CPU
dbg_mem_din, // Debug unit Memory data input
dbg_reg_din, // Debug unit CPU register data input
dbg_uart_rxd, // Debug interface: UART RXD
decode_noirq, // Frontend decode instruction
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
eu_mdb_in, // Memory data bus input
eu_mdb_out, // Memory data bus output
exec_done, // Execution completed
fe_mb_en, // Frontend Memory bus enable
fe_mdb_in, // Frontend Memory data bus input
mclk, // Main system clock
pc, // Program counter
por, // Power on reset
puc // Main system reset
);
// OUTPUTs
//=========
output dbg_freeze; // Freeze peripherals
output dbg_halt_cmd; // Halt CPU command
output [15:0] dbg_mem_addr; // Debug address for rd/wr access
output [15:0] dbg_mem_dout; // Debug unit data output
output dbg_mem_en; // Debug unit memory enable
output [1:0] dbg_mem_wr; // Debug unit memory write
output dbg_reg_wr; // Debug unit CPU register write
output dbg_reset; // Reset CPU from debug interface
output dbg_uart_txd; // Debug interface: UART TXD
// INPUTs
//=========
input dbg_halt_st; // Halt/Run status from CPU
input [15:0] dbg_mem_din; // Debug unit Memory data input
input [15:0] dbg_reg_din; // Debug unit CPU register data input
input dbg_uart_rxd; // Debug interface: UART RXD
input decode_noirq; // Frontend decode instruction
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
input [15:0] eu_mdb_in; // Memory data bus input
input [15:0] eu_mdb_out; // Memory data bus output
input exec_done; // Execution completed
input fe_mb_en; // Frontend Memory bus enable
input [15:0] fe_mdb_in; // Frontend Memory data bus input
input mclk; // Main system clock
input [15:0] pc; // Program counter
input por; // Power on reset
input puc; // Main system reset
//=============================================================================
// 1) WIRE & PARAMETER DECLARATION
//=============================================================================
// Diverse wires and registers
wire [5:0] dbg_addr;
wire [15:0] dbg_din;
wire dbg_wr;
reg mem_burst;
wire dbg_reg_rd;
wire dbg_mem_rd;
reg dbg_mem_rd_dly;
wire dbg_swbrk;
wire dbg_rd;
reg dbg_rd_rdy;
wire mem_burst_rd;
wire mem_burst_wr;
wire brk0_halt;
wire brk0_pnd;
wire [15:0] brk0_dout;
wire brk1_halt;
wire brk1_pnd;
wire [15:0] brk1_dout;
wire brk2_halt;
wire brk2_pnd;
wire [15:0] brk2_dout;
wire brk3_halt;
wire brk3_pnd;
wire [15:0] brk3_dout;
// Register addresses
parameter CPU_ID_LO = 6'h00;
parameter CPU_ID_HI = 6'h01;
parameter CPU_CTL = 6'h02;
parameter CPU_STAT = 6'h03;
parameter MEM_CTL = 6'h04;
parameter MEM_ADDR = 6'h05;
parameter MEM_DATA = 6'h06;
parameter MEM_CNT = 6'h07;
`ifdef DBG_HWBRK_0
parameter BRK0_CTL = 6'h08;
parameter BRK0_STAT = 6'h09;
parameter BRK0_ADDR0 = 6'h0A;
parameter BRK0_ADDR1 = 6'h0B;
`endif
`ifdef DBG_HWBRK_1
parameter BRK1_CTL = 6'h0C;
parameter BRK1_STAT = 6'h0D;
parameter BRK1_ADDR0 = 6'h0E;
parameter BRK1_ADDR1 = 6'h0F;
`endif
`ifdef DBG_HWBRK_2
parameter BRK2_CTL = 6'h10;
parameter BRK2_STAT = 6'h11;
parameter BRK2_ADDR0 = 6'h12;
parameter BRK2_ADDR1 = 6'h13;
`endif
`ifdef DBG_HWBRK_3
parameter BRK3_CTL = 6'h14;
parameter BRK3_STAT = 6'h15;
parameter BRK3_ADDR0 = 6'h16;
parameter BRK3_ADDR1 = 6'h17;
`endif
// Register one-hot decoder
parameter CPU_ID_LO_D = (64'h1 << CPU_ID_LO);
parameter CPU_ID_HI_D = (64'h1 << CPU_ID_HI);
parameter CPU_CTL_D = (64'h1 << CPU_CTL);
parameter CPU_STAT_D = (64'h1 << CPU_STAT);
parameter MEM_CTL_D = (64'h1 << MEM_CTL);
parameter MEM_ADDR_D = (64'h1 << MEM_ADDR);
parameter MEM_DATA_D = (64'h1 << MEM_DATA);
parameter MEM_CNT_D = (64'h1 << MEM_CNT);
`ifdef DBG_HWBRK_0
parameter BRK0_CTL_D = (64'h1 << BRK0_CTL);
parameter BRK0_STAT_D = (64'h1 << BRK0_STAT);
parameter BRK0_ADDR0_D = (64'h1 << BRK0_ADDR0);
parameter BRK0_ADDR1_D = (64'h1 << BRK0_ADDR1);
`endif
`ifdef DBG_HWBRK_1
parameter BRK1_CTL_D = (64'h1 << BRK1_CTL);
parameter BRK1_STAT_D = (64'h1 << BRK1_STAT);
parameter BRK1_ADDR0_D = (64'h1 << BRK1_ADDR0);
parameter BRK1_ADDR1_D = (64'h1 << BRK1_ADDR1);
`endif
`ifdef DBG_HWBRK_2
parameter BRK2_CTL_D = (64'h1 << BRK2_CTL);
parameter BRK2_STAT_D = (64'h1 << BRK2_STAT);
parameter BRK2_ADDR0_D = (64'h1 << BRK2_ADDR0);
parameter BRK2_ADDR1_D = (64'h1 << BRK2_ADDR1);
`endif
`ifdef DBG_HWBRK_3
parameter BRK3_CTL_D = (64'h1 << BRK3_CTL);
parameter BRK3_STAT_D = (64'h1 << BRK3_STAT);
parameter BRK3_ADDR0_D = (64'h1 << BRK3_ADDR0);
parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1);
`endif
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Select Data register during a burst
wire [5:0] dbg_addr_in = mem_burst ? MEM_DATA : dbg_addr;
// Register address decode
reg [63:0] reg_dec;
always @(dbg_addr_in)
case (dbg_addr_in)
CPU_ID_LO : reg_dec = CPU_ID_LO_D;
CPU_ID_HI : reg_dec = CPU_ID_HI_D;
CPU_CTL : reg_dec = CPU_CTL_D;
CPU_STAT : reg_dec = CPU_STAT_D;
MEM_CTL : reg_dec = MEM_CTL_D;
MEM_ADDR : reg_dec = MEM_ADDR_D;
MEM_DATA : reg_dec = MEM_DATA_D;
MEM_CNT : reg_dec = MEM_CNT_D;
`ifdef DBG_HWBRK_0
BRK0_CTL : reg_dec = BRK0_CTL_D;
BRK0_STAT : reg_dec = BRK0_STAT_D;
BRK0_ADDR0: reg_dec = BRK0_ADDR0_D;
BRK0_ADDR1: reg_dec = BRK0_ADDR1_D;
`endif
`ifdef DBG_HWBRK_1
BRK1_CTL : reg_dec = BRK1_CTL_D;
BRK1_STAT : reg_dec = BRK1_STAT_D;
BRK1_ADDR0: reg_dec = BRK1_ADDR0_D;
BRK1_ADDR1: reg_dec = BRK1_ADDR1_D;
`endif
`ifdef DBG_HWBRK_2
BRK2_CTL : reg_dec = BRK2_CTL_D;
BRK2_STAT : reg_dec = BRK2_STAT_D;
BRK2_ADDR0: reg_dec = BRK2_ADDR0_D;
BRK2_ADDR1: reg_dec = BRK2_ADDR1_D;
`endif
`ifdef DBG_HWBRK_3
BRK3_CTL : reg_dec = BRK3_CTL_D;
BRK3_STAT : reg_dec = BRK3_STAT_D;
BRK3_ADDR0: reg_dec = BRK3_ADDR0_D;
BRK3_ADDR1: reg_dec = BRK3_ADDR1_D;
`endif
default: reg_dec = {64{1'b0}};
endcase
// Read/Write probes
wire reg_write = dbg_wr;
wire reg_read = 1'b1;
// Read/Write vectors
wire [511:0] reg_wr = reg_dec & {64{reg_write}};
wire [511:0] reg_rd = reg_dec & {64{reg_read}};
//=============================================================================
// 3) REGISTER: CORE INTERFACE
//=============================================================================
// CPU_ID Register
//-----------------
wire [3:0] cpu_id_pmem = `PMEM_AWIDTH;
wire [3:0] cpu_id_dmem = `DMEM_AWIDTH;
wire [31:0] cpu_id = {`DBG_ID, cpu_id_pmem, cpu_id_dmem};
// CPU_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved CPU_RST RST_BRK_EN FRZ_BRK_EN SW_BRK_EN ISTEP RUN HALT
//-----------------------------------------------------------------------------
reg [6:3] cpu_ctl;
wire cpu_ctl_wr = reg_wr[CPU_CTL];
always @ (posedge mclk or posedge por)
if (por) cpu_ctl <= 4'h0;
else if (cpu_ctl_wr) cpu_ctl <= dbg_din[6:3];
wire [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000};
wire halt_cpu = cpu_ctl_wr & dbg_din[`HALT] & ~dbg_halt_st;
wire run_cpu = cpu_ctl_wr & dbg_din[`RUN] & dbg_halt_st;
wire istep = cpu_ctl_wr & dbg_din[`ISTEP] & dbg_halt_st;
// CPU_STAT Register
//------------------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
//------------------------------------------------------------------------------------
reg [3:2] cpu_stat;
wire cpu_stat_wr = reg_wr[CPU_STAT];
wire [3:2] cpu_stat_set = {dbg_swbrk, puc};
wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
always @ (posedge mclk or posedge por)
if (por) cpu_stat <= 2'b00;
else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
else cpu_stat <= (cpu_stat | cpu_stat_set);
wire [7:0] cpu_stat_full = {brk3_pnd, brk2_pnd, brk1_pnd, brk0_pnd,
cpu_stat, 1'b0, dbg_halt_st};
//=============================================================================
// 4) REGISTER: MEMORY INTERFACE
//=============================================================================
// MEM_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved B/W MEM/REG RD/WR START
//
// START : - 0 : Do nothing.
// - 1 : Initiate memory transfer.
//
// RD/WR : - 0 : Read access.
// - 1 : Write access.
//
// MEM/REG: - 0 : Memory access.
// - 1 : CPU Register access.
//
// B/W : - 0 : 16 bit access.
// - 1 : 8 bit access (not valid for CPU Registers).
//
//-----------------------------------------------------------------------------
reg [3:1] mem_ctl;
wire mem_ctl_wr = reg_wr[MEM_CTL];
always @ (posedge mclk or posedge por)
if (por) mem_ctl <= 3'h0;
else if (mem_ctl_wr) mem_ctl <= dbg_din[3:1];
wire [7:0] mem_ctl_full = {4'b0000, mem_ctl, 1'b0};
reg mem_start;
always @ (posedge mclk or posedge por)
if (por) mem_start <= 1'b0;
else mem_start <= mem_ctl_wr & dbg_din[0];
wire mem_bw = mem_ctl[3];
// MEM_DATA Register
//------------------
reg [15:0] mem_data;
reg [15:0] mem_addr;
wire mem_access;
wire mem_data_wr = reg_wr[MEM_DATA];
wire [15:0] dbg_mem_din_bw = ~mem_bw ? dbg_mem_din :
mem_addr[0] ? {8'h00, dbg_mem_din[15:8]} :
{8'h00, dbg_mem_din[7:0]};
always @ (posedge mclk or posedge por)
if (por) mem_data <= 16'h0000;
else if (mem_data_wr) mem_data <= dbg_din;
else if (dbg_reg_rd) mem_data <= dbg_reg_din;
else if (dbg_mem_rd_dly) mem_data <= dbg_mem_din_bw;
// MEM_ADDR Register
//------------------
reg [15:0] mem_cnt;
wire mem_addr_wr = reg_wr[MEM_ADDR];
wire dbg_mem_acc = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2]));
wire dbg_reg_acc = ( dbg_reg_wr | (dbg_rd_rdy & mem_ctl[2]));
wire [15:0] mem_addr_inc = (mem_cnt==16'h0000) ? 16'h0000 :
(dbg_mem_acc & ~mem_bw) ? 16'h0002 :
(dbg_mem_acc | dbg_reg_acc) ? 16'h0001 : 16'h0000;
always @ (posedge mclk or posedge por)
if (por) mem_addr <= 16'h0000;
else if (mem_addr_wr) mem_addr <= dbg_din;
else mem_addr <= mem_addr + mem_addr_inc;
// MEM_CNT Register
//------------------
wire mem_cnt_wr = reg_wr[MEM_CNT];
wire [15:0] mem_cnt_dec = (mem_cnt==16'h0000) ? 16'h0000 :
(dbg_mem_acc | dbg_reg_acc) ? 16'hffff : 16'h0000;
always @ (posedge mclk or posedge por)
if (por) mem_cnt <= 16'h0000;
else if (mem_cnt_wr) mem_cnt <= dbg_din;
else mem_cnt <= mem_cnt + mem_cnt_dec;
//=============================================================================
// 5) BREAKPOINTS / WATCHPOINTS
//=============================================================================
`ifdef DBG_HWBRK_0
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk0_reg_rd = {reg_rd[BRK0_ADDR1],
reg_rd[BRK0_ADDR0],
reg_rd[BRK0_STAT],
reg_rd[BRK0_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk0_reg_wr = {reg_wr[BRK0_ADDR1],
reg_wr[BRK0_ADDR0],
reg_wr[BRK0_STAT],
reg_wr[BRK0_CTL]};
omsp_dbg_hwbrk dbg_hwbr_0 (
// OUTPUTs
.brk_halt (brk0_halt), // Hardware breakpoint command
.brk_pnd (brk0_pnd), // Hardware break/watch-point pending
.brk_dout (brk0_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select
.dbg_din (dbg_din), // Debug register data input
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.eu_mdb_in (eu_mdb_in), // Memory data bus input
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
);
`else
assign brk0_halt = 1'b0;
assign brk0_pnd = 1'b0;
assign brk0_dout = 16'h0000;
`endif
`ifdef DBG_HWBRK_1
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1],
reg_rd[BRK1_ADDR0],
reg_rd[BRK1_STAT],
reg_rd[BRK1_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk1_reg_wr = {reg_wr[BRK1_ADDR1],
reg_wr[BRK1_ADDR0],
reg_wr[BRK1_STAT],
reg_wr[BRK1_CTL]};
omsp_dbg_hwbrk dbg_hwbr_1 (
// OUTPUTs
.brk_halt (brk1_halt), // Hardware breakpoint command
.brk_pnd (brk1_pnd), // Hardware break/watch-point pending
.brk_dout (brk1_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select
.dbg_din (dbg_din), // Debug register data input
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.eu_mdb_in (eu_mdb_in), // Memory data bus input
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
);
`else
assign brk1_halt = 1'b0;
assign brk1_pnd = 1'b0;
assign brk1_dout = 16'h0000;
`endif
`ifdef DBG_HWBRK_2
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk2_reg_rd = {reg_rd[BRK2_ADDR1],
reg_rd[BRK2_ADDR0],
reg_rd[BRK2_STAT],
reg_rd[BRK2_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk2_reg_wr = {reg_wr[BRK2_ADDR1],
reg_wr[BRK2_ADDR0],
reg_wr[BRK2_STAT],
reg_wr[BRK2_CTL]};
omsp_dbg_hwbrk dbg_hwbr_2 (
// OUTPUTs
.brk_halt (brk2_halt), // Hardware breakpoint command
.brk_pnd (brk2_pnd), // Hardware break/watch-point pending
.brk_dout (brk2_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select
.dbg_din (dbg_din), // Debug register data input
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.eu_mdb_in (eu_mdb_in), // Memory data bus input
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
);
`else
assign brk2_halt = 1'b0;
assign brk2_pnd = 1'b0;
assign brk2_dout = 16'h0000;
`endif
`ifdef DBG_HWBRK_3
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk3_reg_rd = {reg_rd[BRK3_ADDR1],
reg_rd[BRK3_ADDR0],
reg_rd[BRK3_STAT],
reg_rd[BRK3_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk3_reg_wr = {reg_wr[BRK3_ADDR1],
reg_wr[BRK3_ADDR0],
reg_wr[BRK3_STAT],
reg_wr[BRK3_CTL]};
omsp_dbg_hwbrk dbg_hwbr_3 (
// OUTPUTs
.brk_halt (brk3_halt), // Hardware breakpoint command
.brk_pnd (brk3_pnd), // Hardware break/watch-point pending
.brk_dout (brk3_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select
.dbg_din (dbg_din), // Debug register data input
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.eu_mdb_in (eu_mdb_in), // Memory data bus input
.eu_mdb_out (eu_mdb_out), // Memory data bus output
.exec_done (exec_done), // Execution completed
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.pc (pc), // Program counter
.por (por) // Power on reset
);
`else
assign brk3_halt = 1'b0;
assign brk3_pnd = 1'b0;
assign brk3_dout = 16'h0000;
`endif
//============================================================================
// 6) DATA OUTPUT GENERATION
//============================================================================
wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}};
wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}};
wire [15:0] cpu_ctl_rd = {8'h00, cpu_ctl_full} & {16{reg_rd[CPU_CTL]}};
wire [15:0] cpu_stat_rd = {8'h00, cpu_stat_full} & {16{reg_rd[CPU_STAT]}};
wire [15:0] mem_ctl_rd = {8'h00, mem_ctl_full} & {16{reg_rd[MEM_CTL]}};
wire [15:0] mem_data_rd = mem_data & {16{reg_rd[MEM_DATA]}};
wire [15:0] mem_addr_rd = mem_addr & {16{reg_rd[MEM_ADDR]}};
wire [15:0] mem_cnt_rd = mem_cnt & {16{reg_rd[MEM_CNT]}};
wire [15:0] dbg_dout = cpu_id_lo_rd |
cpu_id_hi_rd |
cpu_ctl_rd |
cpu_stat_rd |
mem_ctl_rd |
mem_data_rd |
mem_addr_rd |
mem_cnt_rd |
brk0_dout |
brk1_dout |
brk2_dout |
brk3_dout;
// Tell UART/JTAG interface that the data is ready to be read
always @ (posedge mclk or posedge por)
if (por) dbg_rd_rdy <= 1'b0;
else if (mem_burst | mem_burst_rd) dbg_rd_rdy <= (dbg_reg_rd | dbg_mem_rd_dly);
else dbg_rd_rdy <= dbg_rd;
//============================================================================
// 7) CPU CONTROL
//============================================================================
// Reset CPU
//--------------------------
wire dbg_reset = cpu_ctl[`CPU_RST];
// Break after reset
//--------------------------
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc;
// Freeze peripherals
//--------------------------
wire dbg_freeze = dbg_halt_st & cpu_ctl[`FRZ_BRK_EN];
// Software break
//--------------------------
assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode_noirq & cpu_ctl[`SW_BRK_EN];
// Single step
//--------------------------
reg [1:0] inc_step;
always @(posedge mclk or posedge por)
if (por) inc_step <= 2'b00;
else if (istep) inc_step <= 2'b11;
else inc_step <= {inc_step[0], 1'b0};
// Run / Halt
//--------------------------
reg halt_flag;
wire mem_halt_cpu;
wire mem_run_cpu;
wire halt_flag_clr = run_cpu | mem_run_cpu;
wire halt_flag_set = halt_cpu | halt_rst | dbg_swbrk | mem_halt_cpu |
brk0_halt | brk1_halt | brk2_halt | brk3_halt;
always @(posedge mclk or posedge por)
if (por) halt_flag <= 1'b0;
else if (halt_flag_clr) halt_flag <= 1'b0;
else if (halt_flag_set) halt_flag <= 1'b1;
wire dbg_halt_cmd = (halt_flag | halt_flag_set) & ~inc_step[1];
//============================================================================
// 8) MEMORY CONTROL
//============================================================================
// Control Memory bursts
//------------------------------
wire mem_burst_start = (mem_start & |mem_cnt);
wire mem_burst_end = ((dbg_wr | dbg_rd_rdy) & ~|mem_cnt);
// Detect when burst is on going
always @(posedge mclk or posedge por)
if (por) mem_burst <= 1'b0;
else if (mem_burst_start) mem_burst <= 1'b1;
else if (mem_burst_end) mem_burst <= 1'b0;
// Control signals for UART/JTAG interface
assign mem_burst_rd = (mem_burst_start & ~mem_ctl[1]);
assign mem_burst_wr = (mem_burst_start & mem_ctl[1]);
// Trigger CPU Register or memory access during a burst
reg mem_startb;
always @(posedge mclk or posedge por)
if (por) mem_startb <= 1'b0;
else mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd;
// Combine single and burst memory start of sequence
wire mem_seq_start = ((mem_start & ~|mem_cnt) | mem_startb);
// Memory access state machine
//------------------------------
reg [1:0] mem_state;
reg [1:0] mem_state_nxt;
// State machine definition
parameter M_IDLE = 2'h0;
parameter M_SET_BRK = 2'h1;
parameter M_ACCESS_BRK = 2'h2;
parameter M_ACCESS = 2'h3;
// State transition
always @(mem_state or mem_seq_start or dbg_halt_st)
case (mem_state)
M_IDLE : mem_state_nxt = ~mem_seq_start ? M_IDLE :
dbg_halt_st ? M_ACCESS : M_SET_BRK;
M_SET_BRK : mem_state_nxt = dbg_halt_st ? M_ACCESS_BRK : M_SET_BRK;
M_ACCESS_BRK : mem_state_nxt = M_IDLE;
M_ACCESS : mem_state_nxt = M_IDLE;
default : mem_state_nxt = M_IDLE;
endcase
// State machine
always @(posedge mclk or posedge por)
if (por) mem_state <= M_IDLE;
else mem_state <= mem_state_nxt;
// Utility signals
assign mem_halt_cpu = (mem_state==M_IDLE) & (mem_state_nxt==M_SET_BRK);
assign mem_run_cpu = (mem_state==M_ACCESS_BRK) & (mem_state_nxt==M_IDLE);
assign mem_access = (mem_state==M_ACCESS) | (mem_state==M_ACCESS_BRK);
// Interface to CPU Registers and Memory bacbkone
//------------------------------------------------
assign dbg_mem_addr = mem_addr;
assign dbg_mem_dout = ~mem_bw ? mem_data :
mem_addr[0] ? {mem_data[7:0], 8'h00} :
{8'h00, mem_data[7:0]};
assign dbg_reg_wr = mem_access & mem_ctl[1] & mem_ctl[2];
assign dbg_reg_rd = mem_access & ~mem_ctl[1] & mem_ctl[2];
assign dbg_mem_en = mem_access & ~mem_ctl[2];
assign dbg_mem_rd = dbg_mem_en & ~mem_ctl[1];
wire [1:0] dbg_mem_wr_msk = ~mem_bw ? 2'b11 :
mem_addr[0] ? 2'b10 : 2'b01;
assign dbg_mem_wr = {2{dbg_mem_en & mem_ctl[1]}} & dbg_mem_wr_msk;
// It takes one additional cycle to read from Memory as from registers
always @(posedge mclk or posedge por)
if (por) dbg_mem_rd_dly <= 1'b0;
else dbg_mem_rd_dly <= dbg_mem_rd;
//=============================================================================
// 9) UART COMMUNICATION
//=============================================================================
`ifdef DBG_UART
omsp_dbg_uart dbg_uart_0 (
// OUTPUTs
.dbg_addr (dbg_addr), // Debug register address
.dbg_din (dbg_din), // Debug register data input
.dbg_rd (dbg_rd), // Debug register data read
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dbg_wr (dbg_wr), // Debug register data write
// INPUTs
.dbg_dout (dbg_dout), // Debug register data output
.dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.mclk (mclk), // Main system clock
.mem_burst (mem_burst), // Burst on going
.mem_burst_end(mem_burst_end), // End TX/RX burst
.mem_burst_rd (mem_burst_rd), // Start TX burst
.mem_burst_wr (mem_burst_wr), // Start RX burst
.mem_bw (mem_bw), // Burst byte width
.por (por) // Power on reset
);
`else
assign dbg_addr = 6'h00;
assign dbg_din = 16'h0000;
assign dbg_rd = 1'b0;
assign dbg_uart_txd = 1'b0;
assign dbg_wr = 1'b0;
`endif
//=============================================================================
// 10) JTAG COMMUNICATION
//=============================================================================
`ifdef DBG_JTAG
JTAG INTERFACE IS NOT SUPPORTED YET
`else
`endif
endmodule // dbg
`include "openMSP430_undefines.v"
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.8 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.4.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.4 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.3 2002/10/28 15:03:50 mohor
// Signal scanb_sen renamed to scanb_en.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_2048x32(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 11;
parameter dw = 32;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hdsp_2048x32 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x32_bist artisan_ssp(
`else
art_hssp_2048x32 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_2048x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x32_bist vs_ssp(
`else
vs_hdsp_2048x32 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[1:0]),
.EN(ce),
.WE(we),
.DO(doq[1:0])
);
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:2]),
.EN(ce),
.WE(we),
.DO(doq[3:2])
);
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[5:4]),
.EN(ce),
.WE(we),
.DO(doq[5:4])
);
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:6]),
.EN(ce),
.WE(we),
.DO(doq[7:6])
);
//
// Block 4
//
RAMB4_S2 ramb4_s2_4(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[9:8]),
.EN(ce),
.WE(we),
.DO(doq[9:8])
);
//
// Block 5
//
RAMB4_S2 ramb4_s2_5(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[11:10]),
.EN(ce),
.WE(we),
.DO(doq[11:10])
);
//
// Block 6
//
RAMB4_S2 ramb4_s2_6(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[13:12]),
.EN(ce),
.WE(we),
.DO(doq[13:12])
);
//
// Block 7
//
RAMB4_S2 ramb4_s2_7(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[15:14]),
.EN(ce),
.WE(we),
.DO(doq[15:14])
);
//
// Block 8
//
RAMB4_S2 ramb4_s2_8(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[17:16]),
.EN(ce),
.WE(we),
.DO(doq[17:16])
);
//
// Block 9
//
RAMB4_S2 ramb4_s2_9(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[19:18]),
.EN(ce),
.WE(we),
.DO(doq[19:18])
);
//
// Block 10
//
RAMB4_S2 ramb4_s2_10(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[21:20]),
.EN(ce),
.WE(we),
.DO(doq[21:20])
);
//
// Block 11
//
RAMB4_S2 ramb4_s2_11(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[23:22]),
.EN(ce),
.WE(we),
.DO(doq[23:22])
);
//
// Block 12
//
RAMB4_S2 ramb4_s2_12(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[25:24]),
.EN(ce),
.WE(we),
.DO(doq[25:24])
);
//
// Block 13
//
RAMB4_S2 ramb4_s2_13(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[27:26]),
.EN(ce),
.WE(we),
.DO(doq[27:26])
);
//
// Block 14
//
RAMB4_S2 ramb4_s2_14(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[29:28]),
.EN(ce),
.WE(we),
.DO(doq[29:28])
);
//
// Block 15
//
RAMB4_S2 ramb4_s2_15(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[31:30]),
.EN(ce),
.WE(we),
.DO(doq[31:30])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
//
// Block 0
//
RAMB16_S9 ramb16_s9_0(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[7:0]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[7:0]),
.DOP()
);
//
// Block 1
//
RAMB16_S9 ramb16_s9_1(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[15:8]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[15:8]),
.DOP()
);
//
// Block 2
//
RAMB16_S9 ramb16_s9_2(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[23:16]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[23:16]),
.DOP()
);
//
// Block 3
//
RAMB16_S9 ramb16_s9_3(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[31:24]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[31:24]),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
//*******************************************************************************************
//Author: Yejoong Kim, Ye-sheng Kuo
//Last Modified: May 24 2017
//Description: MBus Node Control for Master Layer
//Update History: Apr 08 2013 - Added glitch reset (Ye-sheng Kuo)
// May 25 2015 - Added double latch for DIN (Ye-sheng Kuo, Yejoong Kim)
// May 21 2016 - Updated for MBus r03 (Yejoong Kim)
// Added "BUS_SWITCH_ROLE: DOUT=1" in "case (bus_state_neg)"
// Changed module name:
// lname_mbus_master_ctrl -> lname_mbus_master_node_ctrl
// Added MBus Watchdog Counter
// Dec 16 2016 - Updated for MBus r04 (Yejoong Kim)
// Added MBus Flag (MSG_INTERRUPTED)
// May 24 2017 - Updated for MBus r04p1 (Yejoong Kim)
// Added FORCE_IDLE_WHEN_DONE to fix DIN sync issue between
// master layer and member layer at the end of message
// that requires a reply.
//*******************************************************************************************
`include "include/lname_mbus_def.v"
module lname_mbus_master_node_ctrl (
//Input
input CLK_EXT,
input RESETn,
input CIN,
input DIN,
input [`MBUS_BITS_WD_WIDTH-1:0] NUM_BITS_THRESHOLD,
input [`MBUS_IDLE_WD_WIDTH-1:0] WATCHDOG_THRESHOLD,
input WATCHDOG_RESET,
input WATCHDOG_RESET_REQ,
output reg WATCHDOG_RESET_ACK,
//Output
output COUT,
output reg DOUT,
//MBus Watchdog
input [`MBUS_ADDR_WIDTH-1:0] TX_ADDR_IN,
input [`MBUS_DATA_WIDTH-1:0] TX_DATA_IN,
input TX_PRIORITY_IN,
input TX_ACK_IN,
input TX_SUCC_IN,
input TX_FAIL_IN,
input TX_REQ_IN,
input TX_PEND_IN,
input TX_RESP_ACK_IN,
output [`MBUS_ADDR_WIDTH-1:0] TX_ADDR_OUT,
output [`MBUS_DATA_WIDTH-1:0] TX_DATA_OUT,
output TX_PRIORITY_OUT,
output TX_ACK_OUT,
output TX_SUCC_OUT,
output TX_FAIL_OUT,
output TX_REQ_OUT,
output TX_PEND_OUT,
output TX_RESP_ACK_OUT,
// FSM Configuration
input FORCE_IDLE_WHEN_DONE,
// MBus Msg Interrupted Flag
input MBC_IN_FWD,
input GOCEP_ACTIVE,
input CLEAR_FLAG,
output reg MSG_INTERRUPTED
);
`include "include/lname_mbus_func.v"
parameter BUS_IDLE = 0;
parameter BUS_WAIT_START = 3;
parameter BUS_START = 4;
parameter BUS_ARBITRATE = 1;
parameter BUS_PRIO = 2;
parameter BUS_ACTIVE = 5;
parameter BUS_INTERRUPT = 7;
parameter BUS_SWITCH_ROLE = 6;
parameter BUS_CONTROL0 = 8;
parameter BUS_CONTROL1 = 9;
parameter BUS_BACK_TO_IDLE = 10;
parameter NUM_OF_BUS_STATE = 11;
parameter START_CYCLES = 10;
parameter GUARD_BAND_NUM_CYCLES = 20;
parameter BUS_INTERRUPT_COUNTER = 6;
reg [log2(START_CYCLES-1)-1:0] start_cycle_cnt, next_start_cycle_cnt;
reg [log2(NUM_OF_BUS_STATE-1)-1:0] bus_state, next_bus_state, bus_state_neg;
reg [log2(BUS_INTERRUPT_COUNTER-1)-1:0] bus_interrupt_cnt, next_bus_interrupt_cnt;
reg clk_en, next_clk_en;
reg clkin_sampled;
reg [2:0] din_sampled_neg, din_sampled_pos;
reg [`MBUS_BITS_WD_WIDTH-1:0] num_bits_threshold_cnt, next_num_bits_threshold_cnt;
reg din_dly_1, din_dly_2;
// DIN double-latch
always @(posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
din_dly_1 <= `SD 1'b1;
din_dly_2 <= `SD 1'b1;
end
else if (FORCE_IDLE_WHEN_DONE) begin
if ((bus_state == BUS_IDLE) | (bus_state == BUS_WAIT_START)) begin
din_dly_1 <= `SD DIN;
din_dly_2 <= `SD din_dly_1;
end
else begin
din_dly_1 <= `SD 1'b1;
din_dly_2 <= `SD 1'b1;
end
end
else begin
din_dly_1 <= `SD DIN;
din_dly_2 <= `SD din_dly_1;
end
end
wire [1:0] CONTROL_BITS = `MBUS_CONTROL_SEQ; // EOM?, ~ACK?
//---------------------- Watch-Dog Implementation ----------------------------------//
reg WATCHDOG_RESET_REQ_DL1, WATCHDOG_RESET_REQ_DL2;
reg next_watchdog_reset_ack;
reg WATCHDOG_RESET_DL1, WATCHDOG_RESET_DL2;
reg [`MBUS_IDLE_WD_WIDTH-1:0] watchdog_cnt, next_watchdog_cnt;
reg watchdog_tx_req, next_watchdog_tx_req;
reg watchdog_tx_resp_ack, next_watchdog_tx_resp_ack;
reg watchdog_expired, next_watchdog_expired;
always @ (posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
watchdog_cnt <= `SD 0;
watchdog_tx_req <= `SD 0;
watchdog_tx_resp_ack <= `SD 0;
watchdog_expired <= `SD 0;
WATCHDOG_RESET_ACK <= `SD 0;
WATCHDOG_RESET_REQ_DL1 <= `SD 0;
WATCHDOG_RESET_REQ_DL2 <= `SD 0;
WATCHDOG_RESET_DL1 <= `SD 0;
WATCHDOG_RESET_DL2 <= `SD 0;
end
else begin
watchdog_cnt <= `SD next_watchdog_cnt;
watchdog_tx_req <= `SD next_watchdog_tx_req;
watchdog_tx_resp_ack <= `SD next_watchdog_tx_resp_ack;
watchdog_expired <= `SD next_watchdog_expired;
WATCHDOG_RESET_ACK <= `SD next_watchdog_reset_ack;
WATCHDOG_RESET_REQ_DL1 <= `SD WATCHDOG_RESET_REQ;
WATCHDOG_RESET_REQ_DL2 <= `SD WATCHDOG_RESET_REQ_DL1;
WATCHDOG_RESET_DL1 <= `SD WATCHDOG_RESET;
WATCHDOG_RESET_DL2 <= `SD WATCHDOG_RESET_DL1;
end
end
always @* begin
next_watchdog_cnt = watchdog_cnt;
next_watchdog_tx_req = watchdog_tx_req;
next_watchdog_tx_resp_ack = watchdog_tx_resp_ack;
next_watchdog_expired = watchdog_expired;
next_watchdog_reset_ack = WATCHDOG_RESET_ACK;
if (watchdog_expired) begin
if (watchdog_tx_req) begin
if (TX_ACK_IN)
next_watchdog_tx_req = 0;
if (TX_FAIL_IN & (~watchdog_tx_resp_ack))
next_watchdog_tx_req = 0;
end
if (TX_SUCC_IN | TX_FAIL_IN)
next_watchdog_tx_resp_ack = 1;
if ((~(TX_SUCC_IN | TX_FAIL_IN)) & watchdog_tx_resp_ack)
next_watchdog_tx_resp_ack = 0;
end
if (WATCHDOG_RESET_REQ_DL2 & (~WATCHDOG_RESET_ACK)) next_watchdog_reset_ack = 1;
if ((~WATCHDOG_RESET_REQ_DL2) & WATCHDOG_RESET_ACK) next_watchdog_reset_ack = 0;
if (WATCHDOG_RESET_REQ_DL2 & (~WATCHDOG_RESET_ACK)) // Reset requested by CPU
next_watchdog_cnt = 0;
else if (WATCHDOG_RESET_DL2) // Pause Watchdog
next_watchdog_cnt = 0;
else if ((bus_state != BUS_IDLE) | (bus_state != BUS_IDLE)) // Reset due to non-idle state
next_watchdog_cnt = 0;
else
next_watchdog_cnt = watchdog_cnt + 1'b1;
if ((bus_state == BUS_IDLE) & (next_bus_state == BUS_IDLE)) begin
if ((WATCHDOG_THRESHOLD != 0) & (watchdog_cnt == WATCHDOG_THRESHOLD)) begin
if (~watchdog_expired) next_watchdog_tx_req = 1;
next_watchdog_expired = 1;
end
end
end
// Watch-Dog: Layer Ctrl --> MBus Node
assign TX_REQ_OUT = (watchdog_expired) ? watchdog_tx_req : TX_REQ_IN;
assign TX_PEND_OUT = (watchdog_expired) ? 1'b0 : TX_PEND_IN;
assign TX_ADDR_OUT = (watchdog_expired) ? 32'h0000_0001 : TX_ADDR_IN; // All Selective Sleep msg if watchdog expires
assign TX_DATA_OUT = (watchdog_expired) ? 32'h2FFF_F000 : TX_DATA_IN; // All Selective Sleep msg if watchdog expires
assign TX_RESP_ACK_OUT = (watchdog_expired) ? watchdog_tx_resp_ack : TX_RESP_ACK_IN;
assign TX_PRIORITY_OUT = (watchdog_expired) ? 1'b0 : TX_PRIORITY_IN;
// Watch-Dog: MBus Node --> Layer Ctrl
assign TX_ACK_OUT = (watchdog_expired) ? 1'b0 : TX_ACK_IN;
assign TX_FAIL_OUT = (watchdog_expired) ? 1'b0 : TX_FAIL_IN;
assign TX_SUCC_OUT = (watchdog_expired) ? 1'b0 : TX_SUCC_IN;
//--------------- End of Watch-Dog Implementation ----------------------------------//
//--------------- Start of MBus Message Interrupted Flag ---------------//
reg gocep_active_dl1, gocep_active_dl2;
reg tx_req_in_dl1, tx_req_in_dl2;
reg [4:0] guard_band_cnt, next_guard_band_cnt;
reg very_first_msg, next_very_first_msg;
always @ (posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
gocep_active_dl1 <= `SD 0;
gocep_active_dl2 <= `SD 0;
tx_req_in_dl1 <= `SD 0;
tx_req_in_dl2 <= `SD 0;
guard_band_cnt <= `SD 0;
very_first_msg <= `SD 1;
end
else begin
gocep_active_dl1 <= `SD GOCEP_ACTIVE;
gocep_active_dl2 <= `SD gocep_active_dl1;
tx_req_in_dl1 <= `SD TX_REQ_IN;
tx_req_in_dl2 <= `SD tx_req_in_dl1;
guard_band_cnt <= `SD next_guard_band_cnt;
very_first_msg <= `SD next_very_first_msg;
end
end
always @* begin
next_guard_band_cnt = guard_band_cnt;
if ((bus_state != BUS_IDLE) & (next_bus_state == BUS_IDLE))
next_guard_band_cnt = GUARD_BAND_NUM_CYCLES;
else if (guard_band_cnt > 0) next_guard_band_cnt = guard_band_cnt - 1;
end
always @* begin
next_very_first_msg = very_first_msg;
if ((guard_band_cnt > 0) & (next_guard_band_cnt == 0))
next_very_first_msg = 0;
end
wire RESETn_FLAG = RESETn & ~CLEAR_FLAG;
// MSG_INTERRUPTED is set when GOC becomes activated while there is an on-going MBus message only if:
// - The MBus message is NOT the first message (usually this is a wake-up message)
// - The MBus message is either Tx or Rx for PRC/PRE
// If it is a forwarding message, the flag is not set.
// However, since the 'forward' message cannot be identified until it
// receives the whole MBus ADDR section, it is possible that the
// flag becomes set even if the MBus message is a forwarding message.
// This could happen if GOC becomes activated while PRC/PRE is receiving
// the ADDR section of the forwarding message.
// - The MBus message finishes, but the Guard Band counter (guard_band_cnt) is not zero.
// This is to provide some margin to cover the last RX_REQ/RX_ACK in
// a long MBus message.
// - There is an un-cleared TX_REQ
always @ (posedge CLK_EXT or negedge RESETn_FLAG) begin
if (~RESETn_FLAG) MSG_INTERRUPTED <= `SD 0;
else if (gocep_active_dl1 & ~gocep_active_dl2) begin
if (~very_first_msg & ~MBC_IN_FWD) begin
if ((bus_state != BUS_IDLE) | (guard_band_cnt > 0)) MSG_INTERRUPTED <= `SD 1;
end
else if (tx_req_in_dl2 & ~TX_ACK_IN) MSG_INTERRUPTED <= `SD 1;
end
end
//--------------- End of MBus Message Interrupted Flag ---------------//
always @ (posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
bus_state <= `SD BUS_IDLE;
start_cycle_cnt <= `SD START_CYCLES - 1'b1;
clk_en <= `SD 0;
bus_interrupt_cnt <= `SD BUS_INTERRUPT_COUNTER - 1'b1;
num_bits_threshold_cnt <= `SD 0;
end
else begin
bus_state <= `SD next_bus_state;
start_cycle_cnt <= `SD next_start_cycle_cnt;
clk_en <= `SD next_clk_en;
bus_interrupt_cnt <= `SD next_bus_interrupt_cnt;
num_bits_threshold_cnt <= `SD next_num_bits_threshold_cnt;
end
end
always @* begin
next_bus_state = bus_state;
next_start_cycle_cnt = start_cycle_cnt;
next_clk_en = clk_en;
next_bus_interrupt_cnt = bus_interrupt_cnt;
next_num_bits_threshold_cnt = num_bits_threshold_cnt;
case (bus_state)
BUS_IDLE: begin
if (FORCE_IDLE_WHEN_DONE) begin
if (~din_dly_2) begin
next_bus_state = BUS_WAIT_START;
if (watchdog_cnt < 4) next_start_cycle_cnt = 0;
else next_start_cycle_cnt = START_CYCLES - 1'b1;
end
end
else begin
if (~din_dly_2) next_bus_state = BUS_WAIT_START;
next_start_cycle_cnt = START_CYCLES - 1'b1;
end
end
BUS_WAIT_START: begin
next_num_bits_threshold_cnt = 0;
if (start_cycle_cnt) next_start_cycle_cnt = start_cycle_cnt - 1'b1;
else begin
if (~din_dly_2) begin
next_clk_en = 1;
next_bus_state = BUS_START;
end
else next_bus_state = BUS_IDLE;
end
end
BUS_START: next_bus_state = BUS_ARBITRATE;
BUS_ARBITRATE: begin
next_bus_state = BUS_PRIO;
if (DIN) next_num_bits_threshold_cnt = NUM_BITS_THRESHOLD; // Glitch, reset bus immediately
end
BUS_PRIO: next_bus_state = BUS_ACTIVE;
BUS_ACTIVE: begin
if ((num_bits_threshold_cnt<NUM_BITS_THRESHOLD)&&(~clkin_sampled))
next_num_bits_threshold_cnt = num_bits_threshold_cnt + 1'b1;
else begin
next_clk_en = 0;
next_bus_state = BUS_INTERRUPT;
end
next_bus_interrupt_cnt = BUS_INTERRUPT_COUNTER - 1'b1;
end
BUS_INTERRUPT: begin
if (bus_interrupt_cnt) next_bus_interrupt_cnt = bus_interrupt_cnt - 1'b1;
else begin
if ({din_sampled_neg, din_sampled_pos}==6'b111_000) begin
next_bus_state = BUS_SWITCH_ROLE;
next_clk_en = 1;
end
end
end
BUS_SWITCH_ROLE: next_bus_state = BUS_CONTROL0;
BUS_CONTROL0: next_bus_state = BUS_CONTROL1;
BUS_CONTROL1: next_bus_state = BUS_BACK_TO_IDLE;
BUS_BACK_TO_IDLE: begin
if (FORCE_IDLE_WHEN_DONE) begin
next_bus_state = BUS_IDLE;
next_clk_en = 0;
end
else begin
if (~DIN) begin
next_bus_state = BUS_WAIT_START;
next_start_cycle_cnt = 1;
end
else begin
next_bus_state = BUS_IDLE;
end
next_clk_en = 0;
end
end
endcase
end
always @ (negedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
din_sampled_neg <= `SD 0;
bus_state_neg <= `SD BUS_IDLE;
end
else begin
if (bus_state==BUS_INTERRUPT) din_sampled_neg <= `SD {din_sampled_neg[1:0], DIN};
bus_state_neg <= `SD bus_state;
end
end
always @ (posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
din_sampled_pos <= `SD 0;
clkin_sampled <= `SD 0;
end
else begin
if (bus_state==BUS_INTERRUPT) din_sampled_pos <= `SD {din_sampled_pos[1:0], DIN};
clkin_sampled <= `SD CIN;
end
end
assign COUT = (clk_en)? CLK_EXT : 1'b1;
always @* begin
DOUT = DIN;
case (bus_state_neg)
BUS_IDLE: DOUT = 1;
BUS_WAIT_START: DOUT = 1;
BUS_START: DOUT = 1;
BUS_INTERRUPT: DOUT = CLK_EXT;
BUS_SWITCH_ROLE: DOUT = 1;
BUS_CONTROL0: if (num_bits_threshold_cnt==NUM_BITS_THRESHOLD) DOUT = (~CONTROL_BITS[1]);
BUS_BACK_TO_IDLE: DOUT = 1;
endcase
end
endmodule // lname_mbus_master_node_ctrl
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTN_2_V
`define SKY130_FD_SC_HS__DLRTN_2_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrtn_2 (
RESET_B,
D ,
GATE_N ,
Q ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE_N ;
output Q ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlrtn base (
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.Q(Q),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrtn_2 (
RESET_B,
D ,
GATE_N ,
Q
);
input RESET_B;
input D ;
input GATE_N ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlrtn base (
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.Q(Q)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTN_2_V
|
`define bsg_inv_macro(bits) \
if (harden_p && (width_p==bits) && vertical_p) \
begin: macro \
bsg_rp_tsmc_250_INVX8_b``bits inv_gate (.i0(i),.o); \
end \
else \
if (harden_p && (width_p==bits) && ~vertical_p) \
begin: macro \
bsg_rp_tsmc_250_INVX8_horiz_b``bits inv_gate (.i0(i),.o); \
end
module bsg_inv #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=1
, parameter vertical_p=1
)
(input [width_p-1:0] i
, output [width_p-1:0] o
);
`bsg_inv_macro(85) else
`bsg_inv_macro(84) else
`bsg_inv_macro(83) else
`bsg_inv_macro(82) else
`bsg_inv_macro(81) else
`bsg_inv_macro(80) else
`bsg_inv_macro(79) else
`bsg_inv_macro(78) else
`bsg_inv_macro(77) else
`bsg_inv_macro(76) else
`bsg_inv_macro(75) else
`bsg_inv_macro(74) else
`bsg_inv_macro(73) else
`bsg_inv_macro(72) else
`bsg_inv_macro(71) else
`bsg_inv_macro(70) else
`bsg_inv_macro(69) else
`bsg_inv_macro(68) else
`bsg_inv_macro(67) else
`bsg_inv_macro(66) else
`bsg_inv_macro(65) else
`bsg_inv_macro(64) else
`bsg_inv_macro(63) else
`bsg_inv_macro(62) else
`bsg_inv_macro(61) else
`bsg_inv_macro(60) else
`bsg_inv_macro(59) else
`bsg_inv_macro(58) else
`bsg_inv_macro(57) else
`bsg_inv_macro(56) else
`bsg_inv_macro(55) else
`bsg_inv_macro(54) else
`bsg_inv_macro(53) else
`bsg_inv_macro(52) else
`bsg_inv_macro(51) else
`bsg_inv_macro(50) else
`bsg_inv_macro(49) else
`bsg_inv_macro(48) else
`bsg_inv_macro(47) else
`bsg_inv_macro(46) else
`bsg_inv_macro(45) else
`bsg_inv_macro(44) else
`bsg_inv_macro(43) else
`bsg_inv_macro(42) else
`bsg_inv_macro(41) else
`bsg_inv_macro(40) else
`bsg_inv_macro(39) else
`bsg_inv_macro(38) else
`bsg_inv_macro(37) else
`bsg_inv_macro(36) else
`bsg_inv_macro(35) else
`bsg_inv_macro(34) else
`bsg_inv_macro(33) else
`bsg_inv_macro(32) else
`bsg_inv_macro(31) else
`bsg_inv_macro(30) else
`bsg_inv_macro(29) else
`bsg_inv_macro(28) else
`bsg_inv_macro(27) else
`bsg_inv_macro(26) else
`bsg_inv_macro(25) else
`bsg_inv_macro(24) else
`bsg_inv_macro(23) else
`bsg_inv_macro(22) else
`bsg_inv_macro(21) else
`bsg_inv_macro(20) else
`bsg_inv_macro(19) else
`bsg_inv_macro(18) else
`bsg_inv_macro(17) else
`bsg_inv_macro(16) else
`bsg_inv_macro(15) else
`bsg_inv_macro(14) else
`bsg_inv_macro(13) else
`bsg_inv_macro(12) else
`bsg_inv_macro(11) else
`bsg_inv_macro(10) else
`bsg_inv_macro(9) else
`bsg_inv_macro(8) else
`bsg_inv_macro(7) else
`bsg_inv_macro(6) else
`bsg_inv_macro(5) else
`bsg_inv_macro(4) else
`bsg_inv_macro(3) else
`bsg_inv_macro(2) else
`bsg_inv_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_inv)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4BB_4_V
`define SKY130_FD_SC_LP__NAND4BB_4_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4bb_4 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4bb_4 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4BB_4_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module gen_pipe_1
#(
parameter PIPE_WIDTH = 9'd32,
PIPE_DEPTH = 5'd4
)
(
input clk,
input [PIPE_WIDTH -1 :0] din,
output [PIPE_WIDTH -1 :0] dout_1,
output [PIPE_WIDTH -1 :0] dout
);
reg [PIPE_WIDTH - 1:0] pipe_reg [PIPE_DEPTH - 1:0];
reg [9:0] n;
always @(posedge clk) begin
for(n=(PIPE_DEPTH[9:0] - 10'h1); n!=10'h0; n=n-10'h1)
pipe_reg[n] <= pipe_reg[n-1];
pipe_reg[0] <= din;;
end
assign dout = pipe_reg[PIPE_DEPTH - 1];
assign dout_1 = pipe_reg[PIPE_DEPTH - 2];
endmodule
|
module top(
input CLOCK_50,
input [3:0] KEY,
input [17:0] SW,
output [8:0] LEDG,
output [17:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
inout [35:0] GPIO
);
wire wClock;
clock clock0(
.iStateClock(KEY[1]),
.iState(SW[9:8]),
.iMaxClock(CLOCK_50),
.iManualClock(KEY[0]),
.iLimit(SW[7:0]),
.oClock(wClock)
);
wire [2:0] wcounter;
wire [31:0] wIP;
wire [31:0] wA;
wire [31:0] wB;
wire [31:0] wJ;
wire [31:0] wq;
wire [31:0] wsub;
wire wleq;
subleq cpu(
.iClock(wClock),
.iReset(~KEY[3]),
.ocounter(wcounter),
.oIP(wIP),
.oA(wA),
.oB(wB),
.oJ(wJ),
.oq(wq),
.osub(wsub),
.oleq(wleq)
);
wire [31:0] decoder7_num;
always @(SW[15:13], wcounter, wIP, wA, wB, wJ, wq, wsub, wleq) begin
case (SW[15:13])
3'd0: decoder7_num <= {29'b0, wcounter};
3'd1: decoder7_num <= wIP;
3'd2: decoder7_num <= wA;
3'd3: decoder7_num <= wB;
3'd4: decoder7_num <= wJ;
3'd5: decoder7_num <= wq;
3'd6: decoder7_num <= wsub;
3'd7: decoder7_num <= {31'b0, wleq};
endcase
end
decoder7 dec0(.in(decoder7_num[3:0]), .out(HEX0));
decoder7 dec1(.in(decoder7_num[7:4]), .out(HEX1));
decoder7 dec2(.in(decoder7_num[11:8]), .out(HEX2));
decoder7 dec3(.in(decoder7_num[15:12]), .out(HEX3));
decoder7 dec4(.in(decoder7_num[19:16]), .out(HEX4));
decoder7 dec5(.in(decoder7_num[23:20]), .out(HEX5));
decoder7 dec6(.in(decoder7_num[27:24]), .out(HEX6));
decoder7 dec7(.in(decoder7_num[31:28]), .out(HEX7));
assign GPIO[0] = (wcounter == 3'd0);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:53:58 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_rst_ps7_0_100M_0_sim_netlist.v
// Design : design_1_rst_ps7_0_100M_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
(lpf_asr_reg,
scndry_out,
aux_reset_in,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
slowest_sync_clk);
output lpf_asr_reg;
output scndry_out;
input aux_reset_in;
input lpf_asr;
input [0:0]asr_lpf;
input p_1_in;
input p_2_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(asr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
(.I0(aux_reset_in),
.O(asr_d1));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_asr_i_1
(.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O(lpf_asr_reg));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
(lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0]p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0]p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
(.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_exr_i_1
(.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O(lpf_exr_reg));
endmodule
(* CHECK_LICENSE_TYPE = "design_1_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2016.4" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "zynq" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
(lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0]p_3_out;
wire slowest_sync_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
(.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
(.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
\AUX_LPF[1].asr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_in1_in),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[2].asr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_2_in),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[3].asr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_1_in),
.Q(asr_lpf),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[1].exr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[3]),
.Q(p_3_out[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[2].exr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(p_3_out[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[3].exr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[1]),
.Q(p_3_out[0]),
.R(1'b0));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "SRL16" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF))
POR_SRL_I
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(slowest_sync_clk),
.D(1'b0),
.Q(Q));
FDRE #(
.INIT(1'b0))
lpf_asr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q(lpf_asr),
.R(1'b0));
FDRE #(
.INIT(1'b0))
lpf_exr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q(lpf_exr),
.R(1'b0));
LUT4 #(
.INIT(16'hFFEF))
lpf_int0
(.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O(lpf_int0__0));
FDRE #(
.INIT(1'b0))
lpf_int_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(lpf_int0__0),
.Q(lpf_int),
.R(1'b0));
endmodule
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn;
wire Core;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire bsr;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire pr;
wire slowest_sync_clk;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_3),
.Q(interconnect_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_4),
.Q(peripheral_aresetn),
.R(1'b0));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr),
.Q(bus_struct_reset),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf EXT_LPF
(.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\PR_OUT_DFF[0].peripheral_reset_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr),
.Q(peripheral_reset),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr SEQ
(.\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] (SEQ_n_4),
.Core(Core),
.bsr(bsr),
.lpf_int(lpf_int),
.pr(pr),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
mb_reset_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core),
.Q(mb_reset),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
(Core,
bsr,
pr,
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ,
lpf_int,
slowest_sync_clk);
output Core;
output bsr;
output pr;
output \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
output \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
input lpf_int;
input slowest_sync_clk;
wire \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ;
wire \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ;
wire Core;
wire Core_i_1_n_0;
wire bsr;
wire \bsr_dec_reg_n_0_[0] ;
wire \bsr_dec_reg_n_0_[2] ;
wire bsr_i_1_n_0;
wire \core_dec[0]_i_1_n_0 ;
wire \core_dec[2]_i_1_n_0 ;
wire \core_dec_reg_n_0_[0] ;
wire \core_dec_reg_n_0_[1] ;
wire from_sys_i_1_n_0;
wire lpf_int;
wire p_0_in;
wire [2:0]p_3_out;
wire [2:0]p_5_out;
wire pr;
wire pr_dec0__0;
wire \pr_dec_reg_n_0_[0] ;
wire \pr_dec_reg_n_0_[2] ;
wire pr_i_1_n_0;
wire seq_clr;
wire [5:0]seq_cnt;
wire seq_cnt_en;
wire slowest_sync_clk;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1
(.I0(bsr),
.O(\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1
(.I0(pr),
.O(\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
Core_i_1
(.I0(Core),
.I1(p_0_in),
.O(Core_i_1_n_0));
FDSE #(
.INIT(1'b0))
Core_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core_i_1_n_0),
.Q(Core),
.S(lpf_int));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n SEQ_COUNTER
(.Q(seq_cnt),
.seq_clr(seq_clr),
.seq_cnt_en(seq_cnt_en),
.slowest_sync_clk(slowest_sync_clk));
LUT4 #(
.INIT(16'h0804))
\bsr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt[4]),
.O(p_5_out[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\bsr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\bsr_dec_reg_n_0_[0] ),
.O(p_5_out[2]));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[0]),
.Q(\bsr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[2]),
.Q(\bsr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
bsr_i_1
(.I0(bsr),
.I1(\bsr_dec_reg_n_0_[2] ),
.O(bsr_i_1_n_0));
FDSE #(
.INIT(1'b0))
bsr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr_i_1_n_0),
.Q(bsr),
.S(lpf_int));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8040))
\core_dec[0]_i_1
(.I0(seq_cnt[4]),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt_en),
.O(\core_dec[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\core_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\core_dec_reg_n_0_[0] ),
.O(\core_dec[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\core_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[0]_i_1_n_0 ),
.Q(\core_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_dec0__0),
.Q(\core_dec_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[2]_i_1_n_0 ),
.Q(p_0_in),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
from_sys_i_1
(.I0(Core),
.I1(seq_cnt_en),
.O(from_sys_i_1_n_0));
FDSE #(
.INIT(1'b0))
from_sys_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(from_sys_i_1_n_0),
.Q(seq_cnt_en),
.S(lpf_int));
LUT4 #(
.INIT(16'h0210))
pr_dec0
(.I0(seq_cnt[0]),
.I1(seq_cnt[1]),
.I2(seq_cnt[2]),
.I3(seq_cnt_en),
.O(pr_dec0__0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h1080))
\pr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[5]),
.I2(seq_cnt[3]),
.I3(seq_cnt[4]),
.O(p_3_out[0]));
LUT2 #(
.INIT(4'h8))
\pr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\pr_dec_reg_n_0_[0] ),
.O(p_3_out[2]));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[0]),
.Q(\pr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(\pr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
pr_i_1
(.I0(pr),
.I1(\pr_dec_reg_n_0_[2] ),
.O(pr_i_1_n_0));
FDSE #(
.INIT(1'b0))
pr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_i_1_n_0),
.Q(pr),
.S(lpf_int));
FDRE #(
.INIT(1'b0))
seq_clr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(1'b1),
.Q(seq_clr),
.R(lpf_int));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
(Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk);
output [5:0]Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0]Q;
wire clear;
wire [5:0]q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1))
\q_int[0]_i_1
(.I0(Q[0]),
.O(q_int0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\q_int[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(q_int0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\q_int[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(q_int0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\q_int[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(q_int0[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\q_int[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(q_int0[4]));
LUT1 #(
.INIT(2'h1))
\q_int[5]_i_1
(.I0(seq_clr),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\q_int[5]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(q_int0[5]));
FDRE #(
.INIT(1'b1))
\q_int_reg[0]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[0]),
.Q(Q[0]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[1]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[1]),
.Q(Q[1]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[2]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[2]),
.Q(Q[2]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[3]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[3]),
.Q(Q[3]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[4]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[4]),
.Q(Q[4]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[5]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[5]),
.Q(Q[5]),
.R(clear));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// soc_system.v
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_system (
input wire [3:0] button_pio_external_connection_export, // button_pio_external_connection.export
input wire clk_clk, // clk.clk
output wire [7:0] custom_leds_0_leds_leds, // custom_leds_0_leds.leds
input wire [3:0] dipsw_pio_external_connection_export, // dipsw_pio_external_connection.export
output wire hps_0_h2f_reset_reset_n, // hps_0_h2f_reset.reset_n
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CLK, // hps_0_hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_0_hps_io_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_0_hps_io_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_0_hps_io_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_0_hps_io_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_0_hps_io_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_0_hps_io_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_0_hps_io_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_0_hps_io_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_0_hps_io_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_0_hps_io_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_0_hps_io_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_0_hps_io_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_0_hps_io_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_0_hps_io_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_0_hps_io_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_0_hps_io_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_0_hps_io_hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_0_hps_io_hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_0_hps_io_hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_0_hps_io_hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_0_hps_io_hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_0_hps_io_hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_0_hps_io_hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_0_hps_io_hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_0_hps_io_hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_0_hps_io_hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_0_hps_io_hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_0_hps_io_hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_0_hps_io_hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_0_hps_io_hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_0_hps_io_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_0_hps_io_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_0_hps_io_hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_0_hps_io_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
input wire reset_reset_n // reset.reset_n
);
wire [1:0] hps_0_h2f_axi_master_awburst; // hps_0:h2f_AWBURST -> mm_interconnect_0:hps_0_h2f_axi_master_awburst
wire [3:0] hps_0_h2f_axi_master_arlen; // hps_0:h2f_ARLEN -> mm_interconnect_0:hps_0_h2f_axi_master_arlen
wire [7:0] hps_0_h2f_axi_master_wstrb; // hps_0:h2f_WSTRB -> mm_interconnect_0:hps_0_h2f_axi_master_wstrb
wire hps_0_h2f_axi_master_wready; // mm_interconnect_0:hps_0_h2f_axi_master_wready -> hps_0:h2f_WREADY
wire [11:0] hps_0_h2f_axi_master_rid; // mm_interconnect_0:hps_0_h2f_axi_master_rid -> hps_0:h2f_RID
wire hps_0_h2f_axi_master_rready; // hps_0:h2f_RREADY -> mm_interconnect_0:hps_0_h2f_axi_master_rready
wire [3:0] hps_0_h2f_axi_master_awlen; // hps_0:h2f_AWLEN -> mm_interconnect_0:hps_0_h2f_axi_master_awlen
wire [11:0] hps_0_h2f_axi_master_wid; // hps_0:h2f_WID -> mm_interconnect_0:hps_0_h2f_axi_master_wid
wire [3:0] hps_0_h2f_axi_master_arcache; // hps_0:h2f_ARCACHE -> mm_interconnect_0:hps_0_h2f_axi_master_arcache
wire hps_0_h2f_axi_master_wvalid; // hps_0:h2f_WVALID -> mm_interconnect_0:hps_0_h2f_axi_master_wvalid
wire [29:0] hps_0_h2f_axi_master_araddr; // hps_0:h2f_ARADDR -> mm_interconnect_0:hps_0_h2f_axi_master_araddr
wire [2:0] hps_0_h2f_axi_master_arprot; // hps_0:h2f_ARPROT -> mm_interconnect_0:hps_0_h2f_axi_master_arprot
wire [2:0] hps_0_h2f_axi_master_awprot; // hps_0:h2f_AWPROT -> mm_interconnect_0:hps_0_h2f_axi_master_awprot
wire [63:0] hps_0_h2f_axi_master_wdata; // hps_0:h2f_WDATA -> mm_interconnect_0:hps_0_h2f_axi_master_wdata
wire hps_0_h2f_axi_master_arvalid; // hps_0:h2f_ARVALID -> mm_interconnect_0:hps_0_h2f_axi_master_arvalid
wire [3:0] hps_0_h2f_axi_master_awcache; // hps_0:h2f_AWCACHE -> mm_interconnect_0:hps_0_h2f_axi_master_awcache
wire [11:0] hps_0_h2f_axi_master_arid; // hps_0:h2f_ARID -> mm_interconnect_0:hps_0_h2f_axi_master_arid
wire [1:0] hps_0_h2f_axi_master_arlock; // hps_0:h2f_ARLOCK -> mm_interconnect_0:hps_0_h2f_axi_master_arlock
wire [1:0] hps_0_h2f_axi_master_awlock; // hps_0:h2f_AWLOCK -> mm_interconnect_0:hps_0_h2f_axi_master_awlock
wire [29:0] hps_0_h2f_axi_master_awaddr; // hps_0:h2f_AWADDR -> mm_interconnect_0:hps_0_h2f_axi_master_awaddr
wire [1:0] hps_0_h2f_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_axi_master_bresp -> hps_0:h2f_BRESP
wire hps_0_h2f_axi_master_arready; // mm_interconnect_0:hps_0_h2f_axi_master_arready -> hps_0:h2f_ARREADY
wire [63:0] hps_0_h2f_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_axi_master_rdata -> hps_0:h2f_RDATA
wire hps_0_h2f_axi_master_awready; // mm_interconnect_0:hps_0_h2f_axi_master_awready -> hps_0:h2f_AWREADY
wire [1:0] hps_0_h2f_axi_master_arburst; // hps_0:h2f_ARBURST -> mm_interconnect_0:hps_0_h2f_axi_master_arburst
wire [2:0] hps_0_h2f_axi_master_arsize; // hps_0:h2f_ARSIZE -> mm_interconnect_0:hps_0_h2f_axi_master_arsize
wire hps_0_h2f_axi_master_bready; // hps_0:h2f_BREADY -> mm_interconnect_0:hps_0_h2f_axi_master_bready
wire hps_0_h2f_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_axi_master_rlast -> hps_0:h2f_RLAST
wire hps_0_h2f_axi_master_wlast; // hps_0:h2f_WLAST -> mm_interconnect_0:hps_0_h2f_axi_master_wlast
wire [1:0] hps_0_h2f_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_axi_master_rresp -> hps_0:h2f_RRESP
wire [11:0] hps_0_h2f_axi_master_awid; // hps_0:h2f_AWID -> mm_interconnect_0:hps_0_h2f_axi_master_awid
wire [11:0] hps_0_h2f_axi_master_bid; // mm_interconnect_0:hps_0_h2f_axi_master_bid -> hps_0:h2f_BID
wire hps_0_h2f_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_axi_master_bvalid -> hps_0:h2f_BVALID
wire [2:0] hps_0_h2f_axi_master_awsize; // hps_0:h2f_AWSIZE -> mm_interconnect_0:hps_0_h2f_axi_master_awsize
wire hps_0_h2f_axi_master_awvalid; // hps_0:h2f_AWVALID -> mm_interconnect_0:hps_0_h2f_axi_master_awvalid
wire hps_0_h2f_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_axi_master_rvalid -> hps_0:h2f_RVALID
wire [31:0] fpga_only_master_master_readdata; // mm_interconnect_0:fpga_only_master_master_readdata -> fpga_only_master:master_readdata
wire fpga_only_master_master_waitrequest; // mm_interconnect_0:fpga_only_master_master_waitrequest -> fpga_only_master:master_waitrequest
wire [31:0] fpga_only_master_master_address; // fpga_only_master:master_address -> mm_interconnect_0:fpga_only_master_master_address
wire fpga_only_master_master_read; // fpga_only_master:master_read -> mm_interconnect_0:fpga_only_master_master_read
wire [3:0] fpga_only_master_master_byteenable; // fpga_only_master:master_byteenable -> mm_interconnect_0:fpga_only_master_master_byteenable
wire fpga_only_master_master_readdatavalid; // mm_interconnect_0:fpga_only_master_master_readdatavalid -> fpga_only_master:master_readdatavalid
wire fpga_only_master_master_write; // fpga_only_master:master_write -> mm_interconnect_0:fpga_only_master_master_write
wire [31:0] fpga_only_master_master_writedata; // fpga_only_master:master_writedata -> mm_interconnect_0:fpga_only_master_master_writedata
wire [1:0] hps_0_h2f_lw_axi_master_awburst; // hps_0:h2f_lw_AWBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awburst
wire [3:0] hps_0_h2f_lw_axi_master_arlen; // hps_0:h2f_lw_ARLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlen
wire [3:0] hps_0_h2f_lw_axi_master_wstrb; // hps_0:h2f_lw_WSTRB -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wstrb
wire hps_0_h2f_lw_axi_master_wready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_wready -> hps_0:h2f_lw_WREADY
wire [11:0] hps_0_h2f_lw_axi_master_rid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rid -> hps_0:h2f_lw_RID
wire hps_0_h2f_lw_axi_master_rready; // hps_0:h2f_lw_RREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_rready
wire [3:0] hps_0_h2f_lw_axi_master_awlen; // hps_0:h2f_lw_AWLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlen
wire [11:0] hps_0_h2f_lw_axi_master_wid; // hps_0:h2f_lw_WID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wid
wire [3:0] hps_0_h2f_lw_axi_master_arcache; // hps_0:h2f_lw_ARCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arcache
wire hps_0_h2f_lw_axi_master_wvalid; // hps_0:h2f_lw_WVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wvalid
wire [20:0] hps_0_h2f_lw_axi_master_araddr; // hps_0:h2f_lw_ARADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_araddr
wire [2:0] hps_0_h2f_lw_axi_master_arprot; // hps_0:h2f_lw_ARPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arprot
wire [2:0] hps_0_h2f_lw_axi_master_awprot; // hps_0:h2f_lw_AWPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awprot
wire [31:0] hps_0_h2f_lw_axi_master_wdata; // hps_0:h2f_lw_WDATA -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wdata
wire hps_0_h2f_lw_axi_master_arvalid; // hps_0:h2f_lw_ARVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arvalid
wire [3:0] hps_0_h2f_lw_axi_master_awcache; // hps_0:h2f_lw_AWCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awcache
wire [11:0] hps_0_h2f_lw_axi_master_arid; // hps_0:h2f_lw_ARID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arid
wire [1:0] hps_0_h2f_lw_axi_master_arlock; // hps_0:h2f_lw_ARLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlock
wire [1:0] hps_0_h2f_lw_axi_master_awlock; // hps_0:h2f_lw_AWLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlock
wire [20:0] hps_0_h2f_lw_axi_master_awaddr; // hps_0:h2f_lw_AWADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awaddr
wire [1:0] hps_0_h2f_lw_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bresp -> hps_0:h2f_lw_BRESP
wire hps_0_h2f_lw_axi_master_arready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_arready -> hps_0:h2f_lw_ARREADY
wire [31:0] hps_0_h2f_lw_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rdata -> hps_0:h2f_lw_RDATA
wire hps_0_h2f_lw_axi_master_awready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_awready -> hps_0:h2f_lw_AWREADY
wire [1:0] hps_0_h2f_lw_axi_master_arburst; // hps_0:h2f_lw_ARBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arburst
wire [2:0] hps_0_h2f_lw_axi_master_arsize; // hps_0:h2f_lw_ARSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arsize
wire hps_0_h2f_lw_axi_master_bready; // hps_0:h2f_lw_BREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_bready
wire hps_0_h2f_lw_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rlast -> hps_0:h2f_lw_RLAST
wire hps_0_h2f_lw_axi_master_wlast; // hps_0:h2f_lw_WLAST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wlast
wire [1:0] hps_0_h2f_lw_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rresp -> hps_0:h2f_lw_RRESP
wire [11:0] hps_0_h2f_lw_axi_master_awid; // hps_0:h2f_lw_AWID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awid
wire [11:0] hps_0_h2f_lw_axi_master_bid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bid -> hps_0:h2f_lw_BID
wire hps_0_h2f_lw_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bvalid -> hps_0:h2f_lw_BVALID
wire [2:0] hps_0_h2f_lw_axi_master_awsize; // hps_0:h2f_lw_AWSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awsize
wire hps_0_h2f_lw_axi_master_awvalid; // hps_0:h2f_lw_AWVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awvalid
wire hps_0_h2f_lw_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rvalid -> hps_0:h2f_lw_RVALID
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [63:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [12:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [7:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [63:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [31:0] mm_interconnect_0_sysid_qsys_control_slave_readdata; // sysid_qsys:readdata -> mm_interconnect_0:sysid_qsys_control_slave_readdata
wire [0:0] mm_interconnect_0_sysid_qsys_control_slave_address; // mm_interconnect_0:sysid_qsys_control_slave_address -> sysid_qsys:address
wire [31:0] mm_interconnect_0_custom_leds_0_s0_readdata; // custom_leds_0:avs_s0_readdata -> mm_interconnect_0:custom_leds_0_s0_readdata
wire [0:0] mm_interconnect_0_custom_leds_0_s0_address; // mm_interconnect_0:custom_leds_0_s0_address -> custom_leds_0:avs_s0_address
wire mm_interconnect_0_custom_leds_0_s0_read; // mm_interconnect_0:custom_leds_0_s0_read -> custom_leds_0:avs_s0_read
wire mm_interconnect_0_custom_leds_0_s0_write; // mm_interconnect_0:custom_leds_0_s0_write -> custom_leds_0:avs_s0_write
wire [31:0] mm_interconnect_0_custom_leds_0_s0_writedata; // mm_interconnect_0:custom_leds_0_s0_writedata -> custom_leds_0:avs_s0_writedata
wire mm_interconnect_0_dipsw_pio_s1_chipselect; // mm_interconnect_0:dipsw_pio_s1_chipselect -> dipsw_pio:chipselect
wire [31:0] mm_interconnect_0_dipsw_pio_s1_readdata; // dipsw_pio:readdata -> mm_interconnect_0:dipsw_pio_s1_readdata
wire [1:0] mm_interconnect_0_dipsw_pio_s1_address; // mm_interconnect_0:dipsw_pio_s1_address -> dipsw_pio:address
wire mm_interconnect_0_dipsw_pio_s1_write; // mm_interconnect_0:dipsw_pio_s1_write -> dipsw_pio:write_n
wire [31:0] mm_interconnect_0_dipsw_pio_s1_writedata; // mm_interconnect_0:dipsw_pio_s1_writedata -> dipsw_pio:writedata
wire mm_interconnect_0_button_pio_s1_chipselect; // mm_interconnect_0:button_pio_s1_chipselect -> button_pio:chipselect
wire [31:0] mm_interconnect_0_button_pio_s1_readdata; // button_pio:readdata -> mm_interconnect_0:button_pio_s1_readdata
wire [1:0] mm_interconnect_0_button_pio_s1_address; // mm_interconnect_0:button_pio_s1_address -> button_pio:address
wire mm_interconnect_0_button_pio_s1_write; // mm_interconnect_0:button_pio_s1_write -> button_pio:write_n
wire [31:0] mm_interconnect_0_button_pio_s1_writedata; // mm_interconnect_0:button_pio_s1_writedata -> button_pio:writedata
wire [31:0] hps_only_master_master_readdata; // mm_interconnect_1:hps_only_master_master_readdata -> hps_only_master:master_readdata
wire hps_only_master_master_waitrequest; // mm_interconnect_1:hps_only_master_master_waitrequest -> hps_only_master:master_waitrequest
wire [31:0] hps_only_master_master_address; // hps_only_master:master_address -> mm_interconnect_1:hps_only_master_master_address
wire hps_only_master_master_read; // hps_only_master:master_read -> mm_interconnect_1:hps_only_master_master_read
wire [3:0] hps_only_master_master_byteenable; // hps_only_master:master_byteenable -> mm_interconnect_1:hps_only_master_master_byteenable
wire hps_only_master_master_readdatavalid; // mm_interconnect_1:hps_only_master_master_readdatavalid -> hps_only_master:master_readdatavalid
wire hps_only_master_master_write; // hps_only_master:master_write -> mm_interconnect_1:hps_only_master_master_write
wire [31:0] hps_only_master_master_writedata; // hps_only_master:master_writedata -> mm_interconnect_1:hps_only_master_master_writedata
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_awburst; // mm_interconnect_1:hps_0_f2h_axi_slave_awburst -> hps_0:f2h_AWBURST
wire [4:0] mm_interconnect_1_hps_0_f2h_axi_slave_awuser; // mm_interconnect_1:hps_0_f2h_axi_slave_awuser -> hps_0:f2h_AWUSER
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_arlen; // mm_interconnect_1:hps_0_f2h_axi_slave_arlen -> hps_0:f2h_ARLEN
wire [15:0] mm_interconnect_1_hps_0_f2h_axi_slave_wstrb; // mm_interconnect_1:hps_0_f2h_axi_slave_wstrb -> hps_0:f2h_WSTRB
wire mm_interconnect_1_hps_0_f2h_axi_slave_wready; // hps_0:f2h_WREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_wready
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_rid; // hps_0:f2h_RID -> mm_interconnect_1:hps_0_f2h_axi_slave_rid
wire mm_interconnect_1_hps_0_f2h_axi_slave_rready; // mm_interconnect_1:hps_0_f2h_axi_slave_rready -> hps_0:f2h_RREADY
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_awlen; // mm_interconnect_1:hps_0_f2h_axi_slave_awlen -> hps_0:f2h_AWLEN
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_wid; // mm_interconnect_1:hps_0_f2h_axi_slave_wid -> hps_0:f2h_WID
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_arcache; // mm_interconnect_1:hps_0_f2h_axi_slave_arcache -> hps_0:f2h_ARCACHE
wire mm_interconnect_1_hps_0_f2h_axi_slave_wvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_wvalid -> hps_0:f2h_WVALID
wire [31:0] mm_interconnect_1_hps_0_f2h_axi_slave_araddr; // mm_interconnect_1:hps_0_f2h_axi_slave_araddr -> hps_0:f2h_ARADDR
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_arprot; // mm_interconnect_1:hps_0_f2h_axi_slave_arprot -> hps_0:f2h_ARPROT
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_awprot; // mm_interconnect_1:hps_0_f2h_axi_slave_awprot -> hps_0:f2h_AWPROT
wire [127:0] mm_interconnect_1_hps_0_f2h_axi_slave_wdata; // mm_interconnect_1:hps_0_f2h_axi_slave_wdata -> hps_0:f2h_WDATA
wire mm_interconnect_1_hps_0_f2h_axi_slave_arvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_arvalid -> hps_0:f2h_ARVALID
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_awcache; // mm_interconnect_1:hps_0_f2h_axi_slave_awcache -> hps_0:f2h_AWCACHE
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_arid; // mm_interconnect_1:hps_0_f2h_axi_slave_arid -> hps_0:f2h_ARID
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_arlock; // mm_interconnect_1:hps_0_f2h_axi_slave_arlock -> hps_0:f2h_ARLOCK
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_awlock; // mm_interconnect_1:hps_0_f2h_axi_slave_awlock -> hps_0:f2h_AWLOCK
wire [31:0] mm_interconnect_1_hps_0_f2h_axi_slave_awaddr; // mm_interconnect_1:hps_0_f2h_axi_slave_awaddr -> hps_0:f2h_AWADDR
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_bresp; // hps_0:f2h_BRESP -> mm_interconnect_1:hps_0_f2h_axi_slave_bresp
wire mm_interconnect_1_hps_0_f2h_axi_slave_arready; // hps_0:f2h_ARREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_arready
wire [127:0] mm_interconnect_1_hps_0_f2h_axi_slave_rdata; // hps_0:f2h_RDATA -> mm_interconnect_1:hps_0_f2h_axi_slave_rdata
wire mm_interconnect_1_hps_0_f2h_axi_slave_awready; // hps_0:f2h_AWREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_awready
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_arburst; // mm_interconnect_1:hps_0_f2h_axi_slave_arburst -> hps_0:f2h_ARBURST
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_arsize; // mm_interconnect_1:hps_0_f2h_axi_slave_arsize -> hps_0:f2h_ARSIZE
wire mm_interconnect_1_hps_0_f2h_axi_slave_bready; // mm_interconnect_1:hps_0_f2h_axi_slave_bready -> hps_0:f2h_BREADY
wire mm_interconnect_1_hps_0_f2h_axi_slave_rlast; // hps_0:f2h_RLAST -> mm_interconnect_1:hps_0_f2h_axi_slave_rlast
wire mm_interconnect_1_hps_0_f2h_axi_slave_wlast; // mm_interconnect_1:hps_0_f2h_axi_slave_wlast -> hps_0:f2h_WLAST
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_rresp; // hps_0:f2h_RRESP -> mm_interconnect_1:hps_0_f2h_axi_slave_rresp
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_awid; // mm_interconnect_1:hps_0_f2h_axi_slave_awid -> hps_0:f2h_AWID
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_bid; // hps_0:f2h_BID -> mm_interconnect_1:hps_0_f2h_axi_slave_bid
wire mm_interconnect_1_hps_0_f2h_axi_slave_bvalid; // hps_0:f2h_BVALID -> mm_interconnect_1:hps_0_f2h_axi_slave_bvalid
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_awsize; // mm_interconnect_1:hps_0_f2h_axi_slave_awsize -> hps_0:f2h_AWSIZE
wire mm_interconnect_1_hps_0_f2h_axi_slave_awvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_awvalid -> hps_0:f2h_AWVALID
wire [4:0] mm_interconnect_1_hps_0_f2h_axi_slave_aruser; // mm_interconnect_1:hps_0_f2h_axi_slave_aruser -> hps_0:f2h_ARUSER
wire mm_interconnect_1_hps_0_f2h_axi_slave_rvalid; // hps_0:f2h_RVALID -> mm_interconnect_1:hps_0_f2h_axi_slave_rvalid
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [button_pio:reset_n, custom_leds_0:reset, dipsw_pio:reset_n, jtag_uart:rst_n, mm_interconnect_0:fpga_only_master_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_0:onchip_memory2_0_reset1_reset_bridge_in_reset_reset, mm_interconnect_1:hps_only_master_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:hps_only_master_master_translator_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_translator:in_reset, sysid_qsys:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [mm_interconnect_0:hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset]
soc_system_button_pio button_pio (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_button_pio_s1_address), // s1.address
.write_n (~mm_interconnect_0_button_pio_s1_write), // .write_n
.writedata (mm_interconnect_0_button_pio_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_button_pio_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_button_pio_s1_readdata), // .readdata
.in_port (button_pio_external_connection_export) // external_connection.export
);
custom_leds custom_leds_0 (
.clk (clk_clk), // clock.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.avs_s0_address (mm_interconnect_0_custom_leds_0_s0_address), // s0.address
.avs_s0_read (mm_interconnect_0_custom_leds_0_s0_read), // .read
.avs_s0_write (mm_interconnect_0_custom_leds_0_s0_write), // .write
.avs_s0_readdata (mm_interconnect_0_custom_leds_0_s0_readdata), // .readdata
.avs_s0_writedata (mm_interconnect_0_custom_leds_0_s0_writedata), // .writedata
.leds (custom_leds_0_leds_leds) // leds.leds
);
soc_system_dipsw_pio dipsw_pio (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_dipsw_pio_s1_address), // s1.address
.write_n (~mm_interconnect_0_dipsw_pio_s1_write), // .write_n
.writedata (mm_interconnect_0_dipsw_pio_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_dipsw_pio_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_dipsw_pio_s1_readdata), // .readdata
.in_port (dipsw_pio_external_connection_export) // external_connection.export
);
soc_system_fpga_only_master #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) fpga_only_master (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (fpga_only_master_master_address), // master.address
.master_readdata (fpga_only_master_master_readdata), // .readdata
.master_read (fpga_only_master_master_read), // .read
.master_write (fpga_only_master_master_write), // .write
.master_writedata (fpga_only_master_master_writedata), // .writedata
.master_waitrequest (fpga_only_master_master_waitrequest), // .waitrequest
.master_readdatavalid (fpga_only_master_master_readdatavalid), // .readdatavalid
.master_byteenable (fpga_only_master_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
soc_system_hps_0 #(
.F2S_Width (3),
.S2F_Width (2)
) hps_0 (
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_0_hps_io_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_0_hps_io_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_0_hps_io_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_0_hps_io_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_0_hps_io_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_0_hps_io_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_0_hps_io_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_0_hps_io_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_0_hps_io_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_0_hps_io_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_0_hps_io_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_0_hps_io_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_0_hps_io_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_0_hps_io_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_0_hps_io_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_0_hps_io_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_0_hps_io_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_0_hps_io_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_0_hps_io_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_0_hps_io_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_0_hps_io_hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_0_hps_io_hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_0_hps_io_hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_0_hps_io_hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_0_hps_io_hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_0_hps_io_hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_0_hps_io_hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_0_hps_io_hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_0_hps_io_hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_0_hps_io_hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_0_hps_io_hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_0_hps_io_hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_0_hps_io_hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_0_hps_io_hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_0_hps_io_hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_0_hps_io_hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_0_hps_io_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_0_hps_io_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_0_hps_io_hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_0_hps_io_hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_0_hps_io_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_0_hps_io_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.h2f_rst_n (hps_0_h2f_reset_reset_n), // h2f_reset.reset_n
.h2f_axi_clk (clk_clk), // h2f_axi_clock.clk
.h2f_AWID (hps_0_h2f_axi_master_awid), // h2f_axi_master.awid
.h2f_AWADDR (hps_0_h2f_axi_master_awaddr), // .awaddr
.h2f_AWLEN (hps_0_h2f_axi_master_awlen), // .awlen
.h2f_AWSIZE (hps_0_h2f_axi_master_awsize), // .awsize
.h2f_AWBURST (hps_0_h2f_axi_master_awburst), // .awburst
.h2f_AWLOCK (hps_0_h2f_axi_master_awlock), // .awlock
.h2f_AWCACHE (hps_0_h2f_axi_master_awcache), // .awcache
.h2f_AWPROT (hps_0_h2f_axi_master_awprot), // .awprot
.h2f_AWVALID (hps_0_h2f_axi_master_awvalid), // .awvalid
.h2f_AWREADY (hps_0_h2f_axi_master_awready), // .awready
.h2f_WID (hps_0_h2f_axi_master_wid), // .wid
.h2f_WDATA (hps_0_h2f_axi_master_wdata), // .wdata
.h2f_WSTRB (hps_0_h2f_axi_master_wstrb), // .wstrb
.h2f_WLAST (hps_0_h2f_axi_master_wlast), // .wlast
.h2f_WVALID (hps_0_h2f_axi_master_wvalid), // .wvalid
.h2f_WREADY (hps_0_h2f_axi_master_wready), // .wready
.h2f_BID (hps_0_h2f_axi_master_bid), // .bid
.h2f_BRESP (hps_0_h2f_axi_master_bresp), // .bresp
.h2f_BVALID (hps_0_h2f_axi_master_bvalid), // .bvalid
.h2f_BREADY (hps_0_h2f_axi_master_bready), // .bready
.h2f_ARID (hps_0_h2f_axi_master_arid), // .arid
.h2f_ARADDR (hps_0_h2f_axi_master_araddr), // .araddr
.h2f_ARLEN (hps_0_h2f_axi_master_arlen), // .arlen
.h2f_ARSIZE (hps_0_h2f_axi_master_arsize), // .arsize
.h2f_ARBURST (hps_0_h2f_axi_master_arburst), // .arburst
.h2f_ARLOCK (hps_0_h2f_axi_master_arlock), // .arlock
.h2f_ARCACHE (hps_0_h2f_axi_master_arcache), // .arcache
.h2f_ARPROT (hps_0_h2f_axi_master_arprot), // .arprot
.h2f_ARVALID (hps_0_h2f_axi_master_arvalid), // .arvalid
.h2f_ARREADY (hps_0_h2f_axi_master_arready), // .arready
.h2f_RID (hps_0_h2f_axi_master_rid), // .rid
.h2f_RDATA (hps_0_h2f_axi_master_rdata), // .rdata
.h2f_RRESP (hps_0_h2f_axi_master_rresp), // .rresp
.h2f_RLAST (hps_0_h2f_axi_master_rlast), // .rlast
.h2f_RVALID (hps_0_h2f_axi_master_rvalid), // .rvalid
.h2f_RREADY (hps_0_h2f_axi_master_rready), // .rready
.f2h_axi_clk (clk_clk), // f2h_axi_clock.clk
.f2h_AWID (mm_interconnect_1_hps_0_f2h_axi_slave_awid), // f2h_axi_slave.awid
.f2h_AWADDR (mm_interconnect_1_hps_0_f2h_axi_slave_awaddr), // .awaddr
.f2h_AWLEN (mm_interconnect_1_hps_0_f2h_axi_slave_awlen), // .awlen
.f2h_AWSIZE (mm_interconnect_1_hps_0_f2h_axi_slave_awsize), // .awsize
.f2h_AWBURST (mm_interconnect_1_hps_0_f2h_axi_slave_awburst), // .awburst
.f2h_AWLOCK (mm_interconnect_1_hps_0_f2h_axi_slave_awlock), // .awlock
.f2h_AWCACHE (mm_interconnect_1_hps_0_f2h_axi_slave_awcache), // .awcache
.f2h_AWPROT (mm_interconnect_1_hps_0_f2h_axi_slave_awprot), // .awprot
.f2h_AWVALID (mm_interconnect_1_hps_0_f2h_axi_slave_awvalid), // .awvalid
.f2h_AWREADY (mm_interconnect_1_hps_0_f2h_axi_slave_awready), // .awready
.f2h_AWUSER (mm_interconnect_1_hps_0_f2h_axi_slave_awuser), // .awuser
.f2h_WID (mm_interconnect_1_hps_0_f2h_axi_slave_wid), // .wid
.f2h_WDATA (mm_interconnect_1_hps_0_f2h_axi_slave_wdata), // .wdata
.f2h_WSTRB (mm_interconnect_1_hps_0_f2h_axi_slave_wstrb), // .wstrb
.f2h_WLAST (mm_interconnect_1_hps_0_f2h_axi_slave_wlast), // .wlast
.f2h_WVALID (mm_interconnect_1_hps_0_f2h_axi_slave_wvalid), // .wvalid
.f2h_WREADY (mm_interconnect_1_hps_0_f2h_axi_slave_wready), // .wready
.f2h_BID (mm_interconnect_1_hps_0_f2h_axi_slave_bid), // .bid
.f2h_BRESP (mm_interconnect_1_hps_0_f2h_axi_slave_bresp), // .bresp
.f2h_BVALID (mm_interconnect_1_hps_0_f2h_axi_slave_bvalid), // .bvalid
.f2h_BREADY (mm_interconnect_1_hps_0_f2h_axi_slave_bready), // .bready
.f2h_ARID (mm_interconnect_1_hps_0_f2h_axi_slave_arid), // .arid
.f2h_ARADDR (mm_interconnect_1_hps_0_f2h_axi_slave_araddr), // .araddr
.f2h_ARLEN (mm_interconnect_1_hps_0_f2h_axi_slave_arlen), // .arlen
.f2h_ARSIZE (mm_interconnect_1_hps_0_f2h_axi_slave_arsize), // .arsize
.f2h_ARBURST (mm_interconnect_1_hps_0_f2h_axi_slave_arburst), // .arburst
.f2h_ARLOCK (mm_interconnect_1_hps_0_f2h_axi_slave_arlock), // .arlock
.f2h_ARCACHE (mm_interconnect_1_hps_0_f2h_axi_slave_arcache), // .arcache
.f2h_ARPROT (mm_interconnect_1_hps_0_f2h_axi_slave_arprot), // .arprot
.f2h_ARVALID (mm_interconnect_1_hps_0_f2h_axi_slave_arvalid), // .arvalid
.f2h_ARREADY (mm_interconnect_1_hps_0_f2h_axi_slave_arready), // .arready
.f2h_ARUSER (mm_interconnect_1_hps_0_f2h_axi_slave_aruser), // .aruser
.f2h_RID (mm_interconnect_1_hps_0_f2h_axi_slave_rid), // .rid
.f2h_RDATA (mm_interconnect_1_hps_0_f2h_axi_slave_rdata), // .rdata
.f2h_RRESP (mm_interconnect_1_hps_0_f2h_axi_slave_rresp), // .rresp
.f2h_RLAST (mm_interconnect_1_hps_0_f2h_axi_slave_rlast), // .rlast
.f2h_RVALID (mm_interconnect_1_hps_0_f2h_axi_slave_rvalid), // .rvalid
.f2h_RREADY (mm_interconnect_1_hps_0_f2h_axi_slave_rready), // .rready
.h2f_lw_axi_clk (clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (hps_0_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (hps_0_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (hps_0_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (hps_0_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (hps_0_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (hps_0_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (hps_0_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (hps_0_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (hps_0_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (hps_0_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (hps_0_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (hps_0_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (hps_0_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (hps_0_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (hps_0_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (hps_0_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (hps_0_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (hps_0_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (hps_0_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (hps_0_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (hps_0_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (hps_0_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (hps_0_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (hps_0_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (hps_0_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (hps_0_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (hps_0_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (hps_0_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (hps_0_h2f_lw_axi_master_rready) // .rready
);
soc_system_fpga_only_master #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) hps_only_master (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (hps_only_master_master_address), // master.address
.master_readdata (hps_only_master_master_readdata), // .readdata
.master_read (hps_only_master_master_read), // .read
.master_write (hps_only_master_master_write), // .write
.master_writedata (hps_only_master_master_writedata), // .writedata
.master_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.master_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.master_byteenable (hps_only_master_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
soc_system_jtag_uart jtag_uart (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq () // irq.irq
);
soc_system_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
soc_system_sysid_qsys sysid_qsys (
.clock (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata), // control_slave.readdata
.address (mm_interconnect_0_sysid_qsys_control_slave_address) // .address
);
soc_system_mm_interconnect_0 mm_interconnect_0 (
.hps_0_h2f_axi_master_awid (hps_0_h2f_axi_master_awid), // hps_0_h2f_axi_master.awid
.hps_0_h2f_axi_master_awaddr (hps_0_h2f_axi_master_awaddr), // .awaddr
.hps_0_h2f_axi_master_awlen (hps_0_h2f_axi_master_awlen), // .awlen
.hps_0_h2f_axi_master_awsize (hps_0_h2f_axi_master_awsize), // .awsize
.hps_0_h2f_axi_master_awburst (hps_0_h2f_axi_master_awburst), // .awburst
.hps_0_h2f_axi_master_awlock (hps_0_h2f_axi_master_awlock), // .awlock
.hps_0_h2f_axi_master_awcache (hps_0_h2f_axi_master_awcache), // .awcache
.hps_0_h2f_axi_master_awprot (hps_0_h2f_axi_master_awprot), // .awprot
.hps_0_h2f_axi_master_awvalid (hps_0_h2f_axi_master_awvalid), // .awvalid
.hps_0_h2f_axi_master_awready (hps_0_h2f_axi_master_awready), // .awready
.hps_0_h2f_axi_master_wid (hps_0_h2f_axi_master_wid), // .wid
.hps_0_h2f_axi_master_wdata (hps_0_h2f_axi_master_wdata), // .wdata
.hps_0_h2f_axi_master_wstrb (hps_0_h2f_axi_master_wstrb), // .wstrb
.hps_0_h2f_axi_master_wlast (hps_0_h2f_axi_master_wlast), // .wlast
.hps_0_h2f_axi_master_wvalid (hps_0_h2f_axi_master_wvalid), // .wvalid
.hps_0_h2f_axi_master_wready (hps_0_h2f_axi_master_wready), // .wready
.hps_0_h2f_axi_master_bid (hps_0_h2f_axi_master_bid), // .bid
.hps_0_h2f_axi_master_bresp (hps_0_h2f_axi_master_bresp), // .bresp
.hps_0_h2f_axi_master_bvalid (hps_0_h2f_axi_master_bvalid), // .bvalid
.hps_0_h2f_axi_master_bready (hps_0_h2f_axi_master_bready), // .bready
.hps_0_h2f_axi_master_arid (hps_0_h2f_axi_master_arid), // .arid
.hps_0_h2f_axi_master_araddr (hps_0_h2f_axi_master_araddr), // .araddr
.hps_0_h2f_axi_master_arlen (hps_0_h2f_axi_master_arlen), // .arlen
.hps_0_h2f_axi_master_arsize (hps_0_h2f_axi_master_arsize), // .arsize
.hps_0_h2f_axi_master_arburst (hps_0_h2f_axi_master_arburst), // .arburst
.hps_0_h2f_axi_master_arlock (hps_0_h2f_axi_master_arlock), // .arlock
.hps_0_h2f_axi_master_arcache (hps_0_h2f_axi_master_arcache), // .arcache
.hps_0_h2f_axi_master_arprot (hps_0_h2f_axi_master_arprot), // .arprot
.hps_0_h2f_axi_master_arvalid (hps_0_h2f_axi_master_arvalid), // .arvalid
.hps_0_h2f_axi_master_arready (hps_0_h2f_axi_master_arready), // .arready
.hps_0_h2f_axi_master_rid (hps_0_h2f_axi_master_rid), // .rid
.hps_0_h2f_axi_master_rdata (hps_0_h2f_axi_master_rdata), // .rdata
.hps_0_h2f_axi_master_rresp (hps_0_h2f_axi_master_rresp), // .rresp
.hps_0_h2f_axi_master_rlast (hps_0_h2f_axi_master_rlast), // .rlast
.hps_0_h2f_axi_master_rvalid (hps_0_h2f_axi_master_rvalid), // .rvalid
.hps_0_h2f_axi_master_rready (hps_0_h2f_axi_master_rready), // .rready
.hps_0_h2f_lw_axi_master_awid (hps_0_h2f_lw_axi_master_awid), // hps_0_h2f_lw_axi_master.awid
.hps_0_h2f_lw_axi_master_awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.hps_0_h2f_lw_axi_master_awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.hps_0_h2f_lw_axi_master_awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.hps_0_h2f_lw_axi_master_awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.hps_0_h2f_lw_axi_master_awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.hps_0_h2f_lw_axi_master_awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.hps_0_h2f_lw_axi_master_awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.hps_0_h2f_lw_axi_master_awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.hps_0_h2f_lw_axi_master_awready (hps_0_h2f_lw_axi_master_awready), // .awready
.hps_0_h2f_lw_axi_master_wid (hps_0_h2f_lw_axi_master_wid), // .wid
.hps_0_h2f_lw_axi_master_wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.hps_0_h2f_lw_axi_master_wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.hps_0_h2f_lw_axi_master_wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.hps_0_h2f_lw_axi_master_wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.hps_0_h2f_lw_axi_master_wready (hps_0_h2f_lw_axi_master_wready), // .wready
.hps_0_h2f_lw_axi_master_bid (hps_0_h2f_lw_axi_master_bid), // .bid
.hps_0_h2f_lw_axi_master_bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.hps_0_h2f_lw_axi_master_bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.hps_0_h2f_lw_axi_master_bready (hps_0_h2f_lw_axi_master_bready), // .bready
.hps_0_h2f_lw_axi_master_arid (hps_0_h2f_lw_axi_master_arid), // .arid
.hps_0_h2f_lw_axi_master_araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.hps_0_h2f_lw_axi_master_arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.hps_0_h2f_lw_axi_master_arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.hps_0_h2f_lw_axi_master_arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.hps_0_h2f_lw_axi_master_arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.hps_0_h2f_lw_axi_master_arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.hps_0_h2f_lw_axi_master_arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.hps_0_h2f_lw_axi_master_arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.hps_0_h2f_lw_axi_master_arready (hps_0_h2f_lw_axi_master_arready), // .arready
.hps_0_h2f_lw_axi_master_rid (hps_0_h2f_lw_axi_master_rid), // .rid
.hps_0_h2f_lw_axi_master_rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.hps_0_h2f_lw_axi_master_rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.hps_0_h2f_lw_axi_master_rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.hps_0_h2f_lw_axi_master_rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.hps_0_h2f_lw_axi_master_rready (hps_0_h2f_lw_axi_master_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.fpga_only_master_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // fpga_only_master_clk_reset_reset_bridge_in_reset.reset
.hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.onchip_memory2_0_reset1_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // onchip_memory2_0_reset1_reset_bridge_in_reset.reset
.fpga_only_master_master_address (fpga_only_master_master_address), // fpga_only_master_master.address
.fpga_only_master_master_waitrequest (fpga_only_master_master_waitrequest), // .waitrequest
.fpga_only_master_master_byteenable (fpga_only_master_master_byteenable), // .byteenable
.fpga_only_master_master_read (fpga_only_master_master_read), // .read
.fpga_only_master_master_readdata (fpga_only_master_master_readdata), // .readdata
.fpga_only_master_master_readdatavalid (fpga_only_master_master_readdatavalid), // .readdatavalid
.fpga_only_master_master_write (fpga_only_master_master_write), // .write
.fpga_only_master_master_writedata (fpga_only_master_master_writedata), // .writedata
.button_pio_s1_address (mm_interconnect_0_button_pio_s1_address), // button_pio_s1.address
.button_pio_s1_write (mm_interconnect_0_button_pio_s1_write), // .write
.button_pio_s1_readdata (mm_interconnect_0_button_pio_s1_readdata), // .readdata
.button_pio_s1_writedata (mm_interconnect_0_button_pio_s1_writedata), // .writedata
.button_pio_s1_chipselect (mm_interconnect_0_button_pio_s1_chipselect), // .chipselect
.custom_leds_0_s0_address (mm_interconnect_0_custom_leds_0_s0_address), // custom_leds_0_s0.address
.custom_leds_0_s0_write (mm_interconnect_0_custom_leds_0_s0_write), // .write
.custom_leds_0_s0_read (mm_interconnect_0_custom_leds_0_s0_read), // .read
.custom_leds_0_s0_readdata (mm_interconnect_0_custom_leds_0_s0_readdata), // .readdata
.custom_leds_0_s0_writedata (mm_interconnect_0_custom_leds_0_s0_writedata), // .writedata
.dipsw_pio_s1_address (mm_interconnect_0_dipsw_pio_s1_address), // dipsw_pio_s1.address
.dipsw_pio_s1_write (mm_interconnect_0_dipsw_pio_s1_write), // .write
.dipsw_pio_s1_readdata (mm_interconnect_0_dipsw_pio_s1_readdata), // .readdata
.dipsw_pio_s1_writedata (mm_interconnect_0_dipsw_pio_s1_writedata), // .writedata
.dipsw_pio_s1_chipselect (mm_interconnect_0_dipsw_pio_s1_chipselect), // .chipselect
.jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
.jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write
.jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read
.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.sysid_qsys_control_slave_address (mm_interconnect_0_sysid_qsys_control_slave_address), // sysid_qsys_control_slave.address
.sysid_qsys_control_slave_readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata) // .readdata
);
soc_system_mm_interconnect_1 mm_interconnect_1 (
.hps_0_f2h_axi_slave_awid (mm_interconnect_1_hps_0_f2h_axi_slave_awid), // hps_0_f2h_axi_slave.awid
.hps_0_f2h_axi_slave_awaddr (mm_interconnect_1_hps_0_f2h_axi_slave_awaddr), // .awaddr
.hps_0_f2h_axi_slave_awlen (mm_interconnect_1_hps_0_f2h_axi_slave_awlen), // .awlen
.hps_0_f2h_axi_slave_awsize (mm_interconnect_1_hps_0_f2h_axi_slave_awsize), // .awsize
.hps_0_f2h_axi_slave_awburst (mm_interconnect_1_hps_0_f2h_axi_slave_awburst), // .awburst
.hps_0_f2h_axi_slave_awlock (mm_interconnect_1_hps_0_f2h_axi_slave_awlock), // .awlock
.hps_0_f2h_axi_slave_awcache (mm_interconnect_1_hps_0_f2h_axi_slave_awcache), // .awcache
.hps_0_f2h_axi_slave_awprot (mm_interconnect_1_hps_0_f2h_axi_slave_awprot), // .awprot
.hps_0_f2h_axi_slave_awuser (mm_interconnect_1_hps_0_f2h_axi_slave_awuser), // .awuser
.hps_0_f2h_axi_slave_awvalid (mm_interconnect_1_hps_0_f2h_axi_slave_awvalid), // .awvalid
.hps_0_f2h_axi_slave_awready (mm_interconnect_1_hps_0_f2h_axi_slave_awready), // .awready
.hps_0_f2h_axi_slave_wid (mm_interconnect_1_hps_0_f2h_axi_slave_wid), // .wid
.hps_0_f2h_axi_slave_wdata (mm_interconnect_1_hps_0_f2h_axi_slave_wdata), // .wdata
.hps_0_f2h_axi_slave_wstrb (mm_interconnect_1_hps_0_f2h_axi_slave_wstrb), // .wstrb
.hps_0_f2h_axi_slave_wlast (mm_interconnect_1_hps_0_f2h_axi_slave_wlast), // .wlast
.hps_0_f2h_axi_slave_wvalid (mm_interconnect_1_hps_0_f2h_axi_slave_wvalid), // .wvalid
.hps_0_f2h_axi_slave_wready (mm_interconnect_1_hps_0_f2h_axi_slave_wready), // .wready
.hps_0_f2h_axi_slave_bid (mm_interconnect_1_hps_0_f2h_axi_slave_bid), // .bid
.hps_0_f2h_axi_slave_bresp (mm_interconnect_1_hps_0_f2h_axi_slave_bresp), // .bresp
.hps_0_f2h_axi_slave_bvalid (mm_interconnect_1_hps_0_f2h_axi_slave_bvalid), // .bvalid
.hps_0_f2h_axi_slave_bready (mm_interconnect_1_hps_0_f2h_axi_slave_bready), // .bready
.hps_0_f2h_axi_slave_arid (mm_interconnect_1_hps_0_f2h_axi_slave_arid), // .arid
.hps_0_f2h_axi_slave_araddr (mm_interconnect_1_hps_0_f2h_axi_slave_araddr), // .araddr
.hps_0_f2h_axi_slave_arlen (mm_interconnect_1_hps_0_f2h_axi_slave_arlen), // .arlen
.hps_0_f2h_axi_slave_arsize (mm_interconnect_1_hps_0_f2h_axi_slave_arsize), // .arsize
.hps_0_f2h_axi_slave_arburst (mm_interconnect_1_hps_0_f2h_axi_slave_arburst), // .arburst
.hps_0_f2h_axi_slave_arlock (mm_interconnect_1_hps_0_f2h_axi_slave_arlock), // .arlock
.hps_0_f2h_axi_slave_arcache (mm_interconnect_1_hps_0_f2h_axi_slave_arcache), // .arcache
.hps_0_f2h_axi_slave_arprot (mm_interconnect_1_hps_0_f2h_axi_slave_arprot), // .arprot
.hps_0_f2h_axi_slave_aruser (mm_interconnect_1_hps_0_f2h_axi_slave_aruser), // .aruser
.hps_0_f2h_axi_slave_arvalid (mm_interconnect_1_hps_0_f2h_axi_slave_arvalid), // .arvalid
.hps_0_f2h_axi_slave_arready (mm_interconnect_1_hps_0_f2h_axi_slave_arready), // .arready
.hps_0_f2h_axi_slave_rid (mm_interconnect_1_hps_0_f2h_axi_slave_rid), // .rid
.hps_0_f2h_axi_slave_rdata (mm_interconnect_1_hps_0_f2h_axi_slave_rdata), // .rdata
.hps_0_f2h_axi_slave_rresp (mm_interconnect_1_hps_0_f2h_axi_slave_rresp), // .rresp
.hps_0_f2h_axi_slave_rlast (mm_interconnect_1_hps_0_f2h_axi_slave_rlast), // .rlast
.hps_0_f2h_axi_slave_rvalid (mm_interconnect_1_hps_0_f2h_axi_slave_rvalid), // .rvalid
.hps_0_f2h_axi_slave_rready (mm_interconnect_1_hps_0_f2h_axi_slave_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
.hps_only_master_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // hps_only_master_clk_reset_reset_bridge_in_reset.reset
.hps_only_master_master_translator_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // hps_only_master_master_translator_reset_reset_bridge_in_reset.reset
.hps_only_master_master_address (hps_only_master_master_address), // hps_only_master_master.address
.hps_only_master_master_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.hps_only_master_master_byteenable (hps_only_master_master_byteenable), // .byteenable
.hps_only_master_master_read (hps_only_master_master_read), // .read
.hps_only_master_master_readdata (hps_only_master_master_readdata), // .readdata
.hps_only_master_master_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.hps_only_master_master_write (hps_only_master_master_write), // .write
.hps_only_master_master_writedata (hps_only_master_master_writedata) // .writedata
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~hps_0_h2f_reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.13 2010/02/10 00:41:46 yanx Exp $
`timescale 1 ps / 1 ps
module glbl ();
//parameter ROC_WIDTH = 100000;
parameter ROC_WIDTH = 1000;
parameter TOC_WIDTH = 0;
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_XRES4V2_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_XRES4V2_PP_SYMBOL_V
/**
* top_xres4v2: XRES (Input buffer with Glitch filter).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_xres4v2 (
//# {{data|Data Signals}}
input FILT_IN_H ,
input INP_SEL_H ,
inout PAD ,
inout PAD_A_ESD_H ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
input DISABLE_PULLUP_H,
input ENABLE_H ,
input ENABLE_VDDIO ,
input EN_VDDIO_SIG_H ,
output XRES_H_N ,
//# {{power|Power}}
inout PULLUP_H ,
input VSWITCH ,
input VCCD ,
input VCCHIB ,
input VDDA ,
input VDDIO ,
input VDDIO_Q ,
output TIE_HI_ESD ,
inout TIE_WEAK_HI_H ,
input VSSA ,
input VSSD ,
input VSSIO ,
input VSSIO_Q ,
output TIE_LO_ESD
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_XRES4V2_PP_SYMBOL_V
|
// finalproject_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2015.04.23.00:32:40
`timescale 1 ps / 1 ps
module finalproject_mm_interconnect_1 (
input wire clocks_c1_clk, // clocks_c1.clk
input wire clock_crossing_io_m0_reset_reset_bridge_in_reset_reset, // clock_crossing_io_m0_reset_reset_bridge_in_reset.reset
input wire [21:0] clock_crossing_io_m0_address, // clock_crossing_io_m0.address
output wire clock_crossing_io_m0_waitrequest, // .waitrequest
input wire [0:0] clock_crossing_io_m0_burstcount, // .burstcount
input wire [3:0] clock_crossing_io_m0_byteenable, // .byteenable
input wire clock_crossing_io_m0_read, // .read
output wire [31:0] clock_crossing_io_m0_readdata, // .readdata
output wire clock_crossing_io_m0_readdatavalid, // .readdatavalid
input wire clock_crossing_io_m0_write, // .write
input wire [31:0] clock_crossing_io_m0_writedata, // .writedata
input wire clock_crossing_io_m0_debugaccess, // .debugaccess
output wire [1:0] CY7C67200_IF_0_hpi_address, // CY7C67200_IF_0_hpi.address
output wire CY7C67200_IF_0_hpi_write, // .write
output wire CY7C67200_IF_0_hpi_read, // .read
input wire [31:0] CY7C67200_IF_0_hpi_readdata, // .readdata
output wire [31:0] CY7C67200_IF_0_hpi_writedata, // .writedata
output wire CY7C67200_IF_0_hpi_chipselect // .chipselect
);
wire clock_crossing_io_m0_translator_avalon_universal_master_0_waitrequest; // CY7C67200_IF_0_hpi_translator:uav_waitrequest -> clock_crossing_io_m0_translator:uav_waitrequest
wire [31:0] clock_crossing_io_m0_translator_avalon_universal_master_0_readdata; // CY7C67200_IF_0_hpi_translator:uav_readdata -> clock_crossing_io_m0_translator:uav_readdata
wire clock_crossing_io_m0_translator_avalon_universal_master_0_debugaccess; // clock_crossing_io_m0_translator:uav_debugaccess -> CY7C67200_IF_0_hpi_translator:uav_debugaccess
wire [21:0] clock_crossing_io_m0_translator_avalon_universal_master_0_address; // clock_crossing_io_m0_translator:uav_address -> CY7C67200_IF_0_hpi_translator:uav_address
wire clock_crossing_io_m0_translator_avalon_universal_master_0_read; // clock_crossing_io_m0_translator:uav_read -> CY7C67200_IF_0_hpi_translator:uav_read
wire [3:0] clock_crossing_io_m0_translator_avalon_universal_master_0_byteenable; // clock_crossing_io_m0_translator:uav_byteenable -> CY7C67200_IF_0_hpi_translator:uav_byteenable
wire clock_crossing_io_m0_translator_avalon_universal_master_0_readdatavalid; // CY7C67200_IF_0_hpi_translator:uav_readdatavalid -> clock_crossing_io_m0_translator:uav_readdatavalid
wire clock_crossing_io_m0_translator_avalon_universal_master_0_lock; // clock_crossing_io_m0_translator:uav_lock -> CY7C67200_IF_0_hpi_translator:uav_lock
wire clock_crossing_io_m0_translator_avalon_universal_master_0_write; // clock_crossing_io_m0_translator:uav_write -> CY7C67200_IF_0_hpi_translator:uav_write
wire [31:0] clock_crossing_io_m0_translator_avalon_universal_master_0_writedata; // clock_crossing_io_m0_translator:uav_writedata -> CY7C67200_IF_0_hpi_translator:uav_writedata
wire [2:0] clock_crossing_io_m0_translator_avalon_universal_master_0_burstcount; // clock_crossing_io_m0_translator:uav_burstcount -> CY7C67200_IF_0_hpi_translator:uav_burstcount
altera_merlin_master_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (22),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) clock_crossing_io_m0_translator (
.clk (clocks_c1_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_crossing_io_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (clock_crossing_io_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (clock_crossing_io_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (clock_crossing_io_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (clock_crossing_io_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_crossing_io_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_crossing_io_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (clock_crossing_io_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (clock_crossing_io_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (clock_crossing_io_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (clock_crossing_io_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (clock_crossing_io_m0_address), // avalon_anti_master_0.address
.av_waitrequest (clock_crossing_io_m0_waitrequest), // .waitrequest
.av_burstcount (clock_crossing_io_m0_burstcount), // .burstcount
.av_byteenable (clock_crossing_io_m0_byteenable), // .byteenable
.av_read (clock_crossing_io_m0_read), // .read
.av_readdata (clock_crossing_io_m0_readdata), // .readdata
.av_readdatavalid (clock_crossing_io_m0_readdatavalid), // .readdatavalid
.av_write (clock_crossing_io_m0_write), // .write
.av_writedata (clock_crossing_io_m0_writedata), // .writedata
.av_debugaccess (clock_crossing_io_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (22),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (2),
.AV_WRITE_WAIT_CYCLES (2),
.AV_SETUP_WAIT_CYCLES (2),
.AV_DATA_HOLD_CYCLES (2)
) cy7c67200_if_0_hpi_translator (
.clk (clocks_c1_clk), // clk.clk
.reset (clock_crossing_io_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_crossing_io_m0_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (clock_crossing_io_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (clock_crossing_io_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (clock_crossing_io_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (clock_crossing_io_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_crossing_io_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_crossing_io_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (clock_crossing_io_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (clock_crossing_io_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (clock_crossing_io_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (clock_crossing_io_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (CY7C67200_IF_0_hpi_address), // avalon_anti_slave_0.address
.av_write (CY7C67200_IF_0_hpi_write), // .write
.av_read (CY7C67200_IF_0_hpi_read), // .read
.av_readdata (CY7C67200_IF_0_hpi_readdata), // .readdata
.av_writedata (CY7C67200_IF_0_hpi_writedata), // .writedata
.av_chipselect (CY7C67200_IF_0_hpi_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_axi_trn_bridge.v
// Version : 1.8
//
// Description : AXI - TRN Bridge for Root Port Model.
// Root Port Usrapp's require TRN interface.
//-----------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_axi_trn_bridge # (
parameter C_DATA_WIDTH = 64,
parameter RBAR_WIDTH = 7,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1
)
(
// Common
input user_clk,
input user_reset,
input user_lnk_up,
// AXI TX
//-----------
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
output s_axis_tx_tvalid, // TX data is valid
input s_axis_tx_tready, // TX ready for data
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
output s_axis_tx_tlast, // TX data is last
output [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
input m_axis_rx_tvalid, // RX data is valid
output m_axis_rx_tready, // RX ready for data
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
input m_axis_rx_tlast, // RX data is last
input [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Usrapp I/O //
//---------------------------------------------//
// TRN TX
//-----------
input [C_DATA_WIDTH-1:0] trn_td, // TX data from usrapp
input trn_tsof, // TX start of packet
input trn_teof, // TX end of packet
input trn_tsrc_rdy, // TX source ready
output trn_tdst_rdy, // TX destination ready
input trn_tsrc_dsc, // TX source discontinue
input [REM_WIDTH-1:0] trn_trem, // TX remainder
input trn_terrfwd, // TX error forward
input trn_tstr, // TX streaming enable
input trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
output [C_DATA_WIDTH-1:0] trn_rd, // RX data to usrapp
output trn_rsof, // RX start of packet
output trn_reof, // RX end of packet
output trn_rsrc_rdy, // RX source ready
input trn_rdst_rdy, // RX destination ready
output reg trn_rsrc_dsc, // RX source discontinue
output [REM_WIDTH-1:0] trn_rrem, // RX remainder
output wire trn_rerrfwd, // RX error forward
output [RBAR_WIDTH-1:0] trn_rbar_hit // RX BAR hit
);
//DWORD Reordering between AXI and TRN interface//
generate begin:gen_axis_txdata
if (C_DATA_WIDTH == 64)
begin
assign s_axis_tx_tdata = {trn_td[31:0],trn_td[63:32]};
end
else if (C_DATA_WIDTH == 128)
begin
assign s_axis_tx_tdata = {trn_td[31:0],trn_td[63:32],trn_td[95:64],trn_td[127:96]};
end
end
endgenerate
//Coversion from trn_rem to s_axis_tkeep[7:0]//
generate begin: gen_axis_tx_tkeep
if (C_DATA_WIDTH == 64)
begin
assign s_axis_tx_tkeep = (trn_teof && ~trn_trem) ? 8'h0F : 8'hFF;
// always @*
// begin
// if (trn_teof && ~trn_trem) begin
// s_axis_tx_tkeep <= 8'h0F;
// end else begin
// s_axis_tx_tkeep <= 8'hFF;
// end
// end
end
else if (C_DATA_WIDTH == 128)
begin
assign s_axis_tx_tkeep = (trn_teof) ? ((trn_trem == 2'b11) ? 16'hFFFF :
((trn_trem == 2'b10) ? 16'h0FFF :
((trn_trem == 2'b01) ? 16'h00FF : 16'h000F ))) :
16'hFFFF;
// always @*
// begin
// if (trn_teof)
// begin
// case (trn_trem)
// 2'b11: begin s_axis_tx_tkeep <= 16'hFFFF; end
// 2'b10: begin s_axis_tx_tkeep <= 16'h0FFF; end
// 2'b01: begin s_axis_tx_tkeep <= 16'h00FF; end
// 2'b00: begin s_axis_tx_tkeep <= 16'h000F; end
// endcase
// end
// else
// begin
// s_axis_tx_tkeep <= 16'hFFFF;
// end
// end
end
end
endgenerate
//Connection of s_axis_tx_tuser with trn_tsrc_dsc,trn_tstr,trn_terr_fwd and trn_terr_fwd
assign s_axis_tx_tuser [3] = trn_tsrc_dsc;
assign s_axis_tx_tuser [2] = trn_tstr;
assign s_axis_tx_tuser [1] = trn_terrfwd;
assign s_axis_tx_tuser [0] = trn_tecrc_gen;
//Constraint trn_tsrc_rdy. If constrained, testbench keep trn_tsrc_rdy constantly asserted. This makes axi bridge to generate trn_tsof immeditely after trn_teof of previous packet.//
reg trn_tsrc_rdy_derived = 1'b0;
always @*
begin
if(trn_tsof && trn_tsrc_rdy && trn_tdst_rdy && !trn_teof)
begin
trn_tsrc_rdy_derived <= 1'b1;
end
else if(trn_tsrc_rdy_derived && trn_teof && trn_tsrc_rdy && trn_tdst_rdy)
begin
trn_tsrc_rdy_derived <= 1'b0;
end
end
assign s_axis_tx_tvalid = trn_tsrc_rdy_derived || trn_tsof || trn_teof;
assign trn_tdst_rdy = s_axis_tx_tready;
assign s_axis_tx_tlast = trn_teof;
assign m_axis_rx_tready = trn_rdst_rdy;
generate begin:gen_trn_rd
if (C_DATA_WIDTH == 64) begin
assign trn_rd = {m_axis_rx_tdata[31:0],m_axis_rx_tdata[63:32]};
end else if (C_DATA_WIDTH == 128) begin
assign trn_rd = {m_axis_rx_tdata[31:0],m_axis_rx_tdata [63:32],m_axis_rx_tdata [95:64],m_axis_rx_tdata [127:96]};
end
end
endgenerate
//Regenerate trn_rsof
//Used clock. Latency may have been added
reg in_packet_reg;
generate begin:gen_trn_rsof
if (C_DATA_WIDTH == 64)
begin
always @(posedge user_clk)
begin
if (user_reset)
in_packet_reg <= 1'b0;
else if (m_axis_rx_tvalid && m_axis_rx_tready)
in_packet_reg <= ~m_axis_rx_tlast;
end
assign trn_rsof = m_axis_rx_tvalid & ~in_packet_reg;
end
else if (C_DATA_WIDTH == 128)
begin
assign trn_rsof = m_axis_rx_tuser [14];
end
end
endgenerate
generate begin: gen_trn_reof
if (C_DATA_WIDTH == 64)
begin
assign trn_reof = m_axis_rx_tlast;
end
else if (C_DATA_WIDTH == 128)
begin
assign trn_reof = m_axis_rx_tuser[21]; //is_eof[4];
end
end
endgenerate
assign trn_rsrc_rdy = m_axis_rx_tvalid;
//Regenerate trn_rsrc_dsc
//Used clock. Latency may have been added
always @(posedge user_clk)
begin
if (user_reset)
trn_rsrc_dsc <= 1'b1;
else
trn_rsrc_dsc <= ~user_lnk_up;
end
wire [4:0] is_sof;
wire [4:0] is_eof;
assign is_sof = m_axis_rx_tuser[14:10];
assign is_eof = m_axis_rx_tuser[21:17];
generate begin:gen_trn_rrem
if (C_DATA_WIDTH == 64)
begin
assign trn_rrem = m_axis_rx_tlast ? (m_axis_rx_tkeep == 8'hFF) ? 1'b1 : 1'b0: 1'b1;
end
else if (C_DATA_WIDTH == 128)
begin
assign trn_rrem[0] = is_eof[2];
assign trn_rrem[1] = (is_eof[4] || is_sof[4] ) ? ( (is_sof[4] && is_eof[4] && is_eof[3]) || (!is_sof[4] && is_eof[4] && is_eof[3]) || (is_sof[4] && !is_eof[4] && !is_sof[3]) ) : 1'b1;
end
end
endgenerate
assign trn_rerrfwd = m_axis_rx_tuser[1];
assign trn_rbar_hit = m_axis_rx_tuser[8:2];
endmodule
|
// Certain arithmetic operations between a signal of width n and a constant can be directly mapped
// to a single k-LUT (where n <= k). This is preferable to normal alumacc techmapping process
// because for many targets, arithmetic techmapping creates hard logic (such as carry cells) which often
// cannot be optimized further.
//
// TODO: Currently, only comparisons with 1-bit output are mapped. Potentially, all arithmetic cells
// with n <= k inputs should be techmapped in this way, because this shortens the critical path
// from n to 1 by avoiding carry chains.
(* techmap_celltype = "$lt $le $gt $ge" *)
module _90_lut_cmp_ (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
parameter _TECHMAP_CONSTMSK_A_ = 0;
parameter _TECHMAP_CONSTVAL_A_ = 0;
parameter _TECHMAP_CONSTMSK_B_ = 0;
parameter _TECHMAP_CONSTVAL_B_ = 0;
function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut;
input integer width;
input integer operation;
input integer swap;
input integer sign;
input integer operand;
integer n, i_var, i_cst, lhs, rhs, o_bit;
begin
gen_lut = width'b0;
for (n = 0; n < (1 << width); n++) begin
if (sign)
i_var = n[width-1:0];
else
i_var = n;
i_cst = operand;
if (swap) begin
lhs = i_cst;
rhs = i_var;
end else begin
lhs = i_var;
rhs = i_cst;
end
if (operation == 0)
o_bit = (lhs < rhs);
if (operation == 1)
o_bit = (lhs <= rhs);
if (operation == 2)
o_bit = (lhs > rhs);
if (operation == 3)
o_bit = (lhs >= rhs);
gen_lut = gen_lut | (o_bit << n);
end
end
endfunction
generate
if (_TECHMAP_CELLTYPE_ == "$lt")
localparam operation = 0;
if (_TECHMAP_CELLTYPE_ == "$le")
localparam operation = 1;
if (_TECHMAP_CELLTYPE_ == "$gt")
localparam operation = 2;
if (_TECHMAP_CELLTYPE_ == "$ge")
localparam operation = 3;
if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)
wire _TECHMAP_FAIL_ = 1;
else if (&_TECHMAP_CONSTMSK_B_)
\$lut #(
.WIDTH(A_WIDTH),
.LUT({ gen_lut(A_WIDTH, operation, 0, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_B_) })
) _TECHMAP_REPLACE_ (
.A(A),
.Y(Y)
);
else if (&_TECHMAP_CONSTMSK_A_)
\$lut #(
.WIDTH(B_WIDTH),
.LUT({ gen_lut(B_WIDTH, operation, 1, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_A_) })
) _TECHMAP_REPLACE_ (
.A(B),
.Y(Y)
);
else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
|
//wishbone_interconnect.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Log:
5/18/2013: Implemented new naming Scheme
*/
module wishbone_mem_interconnect (
//Control Signals
input clk,
input rst,
//Master Signals
input i_m_we,
input i_m_stb,
input i_m_cyc,
input [3:0] i_m_sel,
input [31:0] i_m_adr,
input [31:0] i_m_dat,
output reg [31:0] o_m_dat,
output reg o_m_ack,
output reg o_m_int,
//Slave 0
output o_s0_we,
output o_s0_cyc,
output o_s0_stb,
output [3:0] o_s0_sel,
input i_s0_ack,
output [31:0] o_s0_dat,
input [31:0] i_s0_dat,
output [31:0] o_s0_adr,
input i_s0_int
);
parameter MEM_SEL_0 = 0;
parameter MEM_OFFSET_0 = 32'h00000000;
parameter MEM_SIZE_0 = 32'h800000;
reg [31:0] mem_select;
always @(rst or i_m_adr or mem_select) begin
if (rst) begin
//nothing selected
mem_select <= 32'hFFFFFFFF;
end
else begin
if ((i_m_adr >= MEM_OFFSET_0) && (i_m_adr < (MEM_OFFSET_0 + MEM_SIZE_0))) begin
mem_select <= MEM_SEL_0;
end
else begin
mem_select <= 32'hFFFFFFFF;
end
end
end
//data in from slave
always @ (mem_select or i_s0_dat) begin
case (mem_select)
MEM_SEL_0: begin
o_m_dat <= i_s0_dat;
end
default: begin
o_m_dat <= 32'h0000;
end
endcase
end
//ack in from mem slave
always @ (mem_select or i_s0_ack) begin
case (mem_select)
MEM_SEL_0: begin
o_m_ack <= i_s0_ack;
end
default: begin
o_m_ack <= 1'h0;
end
endcase
end
//int in from slave
always @ (mem_select or i_s0_int) begin
case (mem_select)
MEM_SEL_0: begin
o_m_int <= i_s0_int;
end
default: begin
o_m_int <= 1'h0;
end
endcase
end
assign o_s0_we = (mem_select == MEM_SEL_0) ? i_m_we: 1'b0;
assign o_s0_stb = (mem_select == MEM_SEL_0) ? i_m_stb: 1'b0;
assign o_s0_sel = (mem_select == MEM_SEL_0) ? i_m_sel: 4'b0;
assign o_s0_cyc = (mem_select == MEM_SEL_0) ? i_m_cyc: 1'b0;
assign o_s0_adr = (mem_select == MEM_SEL_0) ? i_m_adr: 32'h0;
assign o_s0_dat = (mem_select == MEM_SEL_0) ? i_m_dat: 32'h0;
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: adc_data_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1.dp1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module adc_data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "12"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "12"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//-----------------------------------------------------------------
// System Generator version 2015.2 Verilog source file.
//
// Copyright(C) 2013 by Xilinx, Inc. All rights reserved. This
// text/file contains proprietary, confidential information of Xilinx,
// Inc., is distributed under license from Xilinx, Inc., and may be used,
// copied and/or disclosed only pursuant to the terms of a valid license
// agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
// this text/file solely for design, simulation, implementation and
// creation of design files limited to Xilinx devices or technologies.
// Use with non-Xilinx devices or technologies is expressly prohibited
// and immediately terminates your license unless covered by a separate
// agreement.
//
// Xilinx is providing this design, code, or information "as is" solely
// for use in developing programs and solutions for Xilinx devices. By
// providing this design, code, or information as one possible
// implementation of this feature, application or standard, Xilinx is
// making no representation that this implementation is free from any
// claims of infringement. You are responsible for obtaining any rights
// you may require for your implementation. Xilinx expressly disclaims
// any warranty whatsoever with respect to the adequacy of the
// implementation, including but not limited to warranties of
// merchantability or fitness for a particular purpose.
//
// Xilinx products are not intended for use in life support appliances,
// devices, or systems. Use in such applications is expressly prohibited.
//
// Any modifications that are made to the source code are done at the user's
// sole risk and will be unsupported.
//
// This copyright and support notice must be retained as part of this
// text at all times. (c) Copyright 1995-2013 Xilinx, Inc. All rights
// reserved.
//-----------------------------------------------------------------
`include "conv_pkg.v"
`timescale 1 ns / 10 ps
module sysgen_constant_828adcadae (
output [(8 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 8'b00000001;
endmodule
`timescale 1 ns / 10 ps
module sysgen_inverter_dea83a2b38 (
input [(1 - 1):0] ip,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire ip_1_26;
reg op_mem_22_20[0:(1 - 1)];
initial
begin
op_mem_22_20[0] = 1'b0;
end
wire op_mem_22_20_front_din;
wire op_mem_22_20_back;
wire op_mem_22_20_push_front_pop_back_en;
localparam [(1 - 1):0] const_value = 1'b1;
wire internal_ip_12_1_bitnot;
assign ip_1_26 = ip;
assign op_mem_22_20_back = op_mem_22_20[0];
always @(posedge clk)
begin:proc_op_mem_22_20
integer i;
if (((ce == 1'b1) && (op_mem_22_20_push_front_pop_back_en == 1'b1)))
begin
op_mem_22_20[0] <= op_mem_22_20_front_din;
end
end
assign internal_ip_12_1_bitnot = ~ip_1_26;
assign op_mem_22_20_push_front_pop_back_en = 1'b0;
assign op = internal_ip_12_1_bitnot;
endmodule
`timescale 1 ns / 10 ps
module sysgen_logical_8b7810a2aa (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
output [(1 - 1):0] y,
input clk,
input ce,
input clr);
wire d0_1_24;
wire d1_1_27;
wire fully_2_1_bit;
assign d0_1_24 = d0;
assign d1_1_27 = d1;
assign fully_2_1_bit = d0_1_24 | d1_1_27;
assign y = fully_2_1_bit;
endmodule
`timescale 1 ns / 10 ps
module sysgen_logical_f9d74a72d1 (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
output [(1 - 1):0] y,
input clk,
input ce,
input clr);
wire d0_1_24;
wire d1_1_27;
wire fully_2_1_bit;
assign d0_1_24 = d0;
assign d1_1_27 = d1;
assign fully_2_1_bit = d0_1_24 & d1_1_27;
assign y = fully_2_1_bit;
endmodule
`timescale 1 ns / 10 ps
module sysgen_reinterpret_ad93f43143 (
input [(16 - 1):0] input_port,
output [(16 - 1):0] output_port,
input clk,
input ce,
input clr);
wire [(16 - 1):0] input_port_1_40;
wire signed [(16 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40;
assign output_port = output_port_5_5_force;
endmodule
`timescale 1 ns / 10 ps
module channelizer_xlslice (x, y);
//Parameter Definitions
parameter new_msb= 9;
parameter new_lsb= 1;
parameter x_width= 16;
parameter y_width= 8;
//Port Declartions
input [x_width-1:0] x;
output [y_width-1:0] y;
assign y = x[new_msb:new_lsb];
endmodule
`timescale 1 ns / 10 ps
module sysgen_constant_fa8d4b3e6d (
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 1'b1;
endmodule
`timescale 1 ns / 10 ps
module sysgen_concat_c4ee67c59a (
input [(16 - 1):0] in0,
input [(16 - 1):0] in1,
output [(32 - 1):0] y,
input clk,
input ce,
input clr);
wire [(16 - 1):0] in0_1_23;
wire [(16 - 1):0] in1_1_27;
wire [(32 - 1):0] y_2_1_concat;
assign in0_1_23 = in0;
assign in1_1_27 = in1;
assign y_2_1_concat = {in0_1_23, in1_1_27};
assign y = y_2_1_concat;
endmodule
`timescale 1 ns / 10 ps
module channelizer_xlconvert (din, clk, ce, clr, en, dout);
//Parameter Definitions
parameter din_width= 16;
parameter din_bin_pt= 4;
parameter din_arith= `xlUnsigned;
parameter dout_width= 8;
parameter dout_bin_pt= 2;
parameter dout_arith= `xlUnsigned;
parameter en_width = 1;
parameter en_bin_pt = 0;
parameter en_arith = `xlUnsigned;
parameter bool_conversion = 0;
parameter latency = 0;
parameter quantization= `xlTruncate;
parameter overflow= `xlWrap;
//Port Declartions
input [din_width-1:0] din;
input clk, ce, clr;
input [en_width-1:0] en;
output [dout_width-1:0] dout;
//Wire Declartions
wire [dout_width-1:0] result;
wire internal_ce;
assign internal_ce = ce & en[0];
generate
if (bool_conversion == 1)
begin:bool_converion_generate
assign result = din;
end
else
begin:std_conversion
convert_type #(din_width,
din_bin_pt,
din_arith,
dout_width,
dout_bin_pt,
dout_arith,
quantization,
overflow)
conv_udp (.inp(din), .res(result));
end
endgenerate
generate
if (latency > 0)
begin:latency_test
synth_reg # (dout_width, latency)
reg1 (
.i(result),
.ce(internal_ce),
.clr(clr),
.clk(clk),
.o(dout));
end
else
begin:latency0
assign dout = result;
end
endgenerate
endmodule
`timescale 1 ns / 10 ps
module sysgen_reinterpret_af1a0b71e1 (
input [(16 - 1):0] input_port,
output [(16 - 1):0] output_port,
input clk,
input ce,
input clr);
wire signed [(16 - 1):0] input_port_1_40;
wire [(16 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40;
assign output_port = output_port_5_5_force;
endmodule
`timescale 1 ns / 10 ps
module sysgen_constant_ff57ff80b6 (
output [(32 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 32'b00000000000000000000000000000000;
endmodule
`timescale 1 ns / 10 ps
module sysgen_constant_9b3be16c34 (
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 1'b0;
endmodule
`timescale 1 ns / 10 ps
module sysgen_delay_2640a39ee9 (
input [(1 - 1):0] d,
input [(1 - 1):0] en,
input [(1 - 1):0] rst,
output [(1 - 1):0] q,
input clk,
input ce,
input clr);
wire d_1_22;
wire en_1_25;
wire rst_1_29;
wire op_mem_0_8_24_next;
reg op_mem_0_8_24 = 1'b0;
wire op_mem_0_8_24_rst;
wire op_mem_0_8_24_en;
wire op_mem_1_8_24_next;
reg op_mem_1_8_24 = 1'b0;
wire op_mem_1_8_24_rst;
wire op_mem_1_8_24_en;
wire op_mem_2_8_24_next;
reg op_mem_2_8_24 = 1'b0;
wire op_mem_2_8_24_rst;
wire op_mem_2_8_24_en;
wire op_mem_3_8_24_next;
reg op_mem_3_8_24 = 1'b0;
wire op_mem_3_8_24_rst;
wire op_mem_3_8_24_en;
wire op_mem_4_8_24_next;
reg op_mem_4_8_24 = 1'b0;
wire op_mem_4_8_24_rst;
wire op_mem_4_8_24_en;
wire op_mem_5_8_24_next;
reg op_mem_5_8_24 = 1'b0;
wire op_mem_5_8_24_rst;
wire op_mem_5_8_24_en;
wire op_mem_6_8_24_next;
reg op_mem_6_8_24 = 1'b0;
wire op_mem_6_8_24_rst;
wire op_mem_6_8_24_en;
wire op_mem_7_8_24_next;
reg op_mem_7_8_24 = 1'b0;
wire op_mem_7_8_24_rst;
wire op_mem_7_8_24_en;
wire op_mem_8_8_24_next;
reg op_mem_8_8_24 = 1'b0;
wire op_mem_8_8_24_rst;
wire op_mem_8_8_24_en;
wire op_mem_9_8_24_next;
reg op_mem_9_8_24 = 1'b0;
wire op_mem_9_8_24_rst;
wire op_mem_9_8_24_en;
wire op_mem_10_8_24_next;
reg op_mem_10_8_24 = 1'b0;
wire op_mem_10_8_24_rst;
wire op_mem_10_8_24_en;
wire op_mem_11_8_24_next;
reg op_mem_11_8_24 = 1'b0;
wire op_mem_11_8_24_rst;
wire op_mem_11_8_24_en;
wire op_mem_12_8_24_next;
reg op_mem_12_8_24 = 1'b0;
wire op_mem_12_8_24_rst;
wire op_mem_12_8_24_en;
wire op_mem_13_8_24_next;
reg op_mem_13_8_24 = 1'b0;
wire op_mem_13_8_24_rst;
wire op_mem_13_8_24_en;
wire op_mem_14_8_24_next;
reg op_mem_14_8_24 = 1'b0;
wire op_mem_14_8_24_rst;
wire op_mem_14_8_24_en;
wire op_mem_15_8_24_next;
reg op_mem_15_8_24 = 1'b0;
wire op_mem_15_8_24_rst;
wire op_mem_15_8_24_en;
wire op_mem_16_8_24_next;
reg op_mem_16_8_24 = 1'b0;
wire op_mem_16_8_24_rst;
wire op_mem_16_8_24_en;
localparam [(5 - 1):0] const_value = 5'b10001;
reg op_mem_0_join_10_5;
reg op_mem_0_join_10_5_en;
reg op_mem_0_join_10_5_rst;
reg op_mem_2_join_10_5;
reg op_mem_2_join_10_5_en;
reg op_mem_2_join_10_5_rst;
reg op_mem_5_join_10_5;
reg op_mem_5_join_10_5_en;
reg op_mem_5_join_10_5_rst;
reg op_mem_13_join_10_5;
reg op_mem_13_join_10_5_en;
reg op_mem_13_join_10_5_rst;
reg op_mem_4_join_10_5;
reg op_mem_4_join_10_5_en;
reg op_mem_4_join_10_5_rst;
reg op_mem_7_join_10_5;
reg op_mem_7_join_10_5_en;
reg op_mem_7_join_10_5_rst;
reg op_mem_15_join_10_5;
reg op_mem_15_join_10_5_en;
reg op_mem_15_join_10_5_rst;
reg op_mem_6_join_10_5;
reg op_mem_6_join_10_5_en;
reg op_mem_6_join_10_5_rst;
reg op_mem_12_join_10_5;
reg op_mem_12_join_10_5_en;
reg op_mem_12_join_10_5_rst;
reg op_mem_3_join_10_5;
reg op_mem_3_join_10_5_en;
reg op_mem_3_join_10_5_rst;
reg op_mem_16_join_10_5;
reg op_mem_16_join_10_5_en;
reg op_mem_16_join_10_5_rst;
reg op_mem_10_join_10_5;
reg op_mem_10_join_10_5_en;
reg op_mem_10_join_10_5_rst;
reg op_mem_1_join_10_5;
reg op_mem_1_join_10_5_en;
reg op_mem_1_join_10_5_rst;
reg op_mem_8_join_10_5;
reg op_mem_8_join_10_5_en;
reg op_mem_8_join_10_5_rst;
reg op_mem_14_join_10_5;
reg op_mem_14_join_10_5_en;
reg op_mem_14_join_10_5_rst;
reg op_mem_9_join_10_5;
reg op_mem_9_join_10_5_en;
reg op_mem_9_join_10_5_rst;
reg op_mem_11_join_10_5;
reg op_mem_11_join_10_5_en;
reg op_mem_11_join_10_5_rst;
assign d_1_22 = d;
assign en_1_25 = en;
assign rst_1_29 = rst;
always @(posedge clk)
begin:proc_op_mem_0_8_24
if (((ce == 1'b1) && (op_mem_0_8_24_rst == 1'b1)))
begin
op_mem_0_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_0_8_24_en == 1'b1)))
begin
op_mem_0_8_24 <= op_mem_0_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_1_8_24
if (((ce == 1'b1) && (op_mem_1_8_24_rst == 1'b1)))
begin
op_mem_1_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_1_8_24_en == 1'b1)))
begin
op_mem_1_8_24 <= op_mem_1_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_2_8_24
if (((ce == 1'b1) && (op_mem_2_8_24_rst == 1'b1)))
begin
op_mem_2_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_2_8_24_en == 1'b1)))
begin
op_mem_2_8_24 <= op_mem_2_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_3_8_24
if (((ce == 1'b1) && (op_mem_3_8_24_rst == 1'b1)))
begin
op_mem_3_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_3_8_24_en == 1'b1)))
begin
op_mem_3_8_24 <= op_mem_3_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_4_8_24
if (((ce == 1'b1) && (op_mem_4_8_24_rst == 1'b1)))
begin
op_mem_4_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_4_8_24_en == 1'b1)))
begin
op_mem_4_8_24 <= op_mem_4_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_5_8_24
if (((ce == 1'b1) && (op_mem_5_8_24_rst == 1'b1)))
begin
op_mem_5_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_5_8_24_en == 1'b1)))
begin
op_mem_5_8_24 <= op_mem_5_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_6_8_24
if (((ce == 1'b1) && (op_mem_6_8_24_rst == 1'b1)))
begin
op_mem_6_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_6_8_24_en == 1'b1)))
begin
op_mem_6_8_24 <= op_mem_6_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_7_8_24
if (((ce == 1'b1) && (op_mem_7_8_24_rst == 1'b1)))
begin
op_mem_7_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_7_8_24_en == 1'b1)))
begin
op_mem_7_8_24 <= op_mem_7_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_8_8_24
if (((ce == 1'b1) && (op_mem_8_8_24_rst == 1'b1)))
begin
op_mem_8_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_8_8_24_en == 1'b1)))
begin
op_mem_8_8_24 <= op_mem_8_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_9_8_24
if (((ce == 1'b1) && (op_mem_9_8_24_rst == 1'b1)))
begin
op_mem_9_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_9_8_24_en == 1'b1)))
begin
op_mem_9_8_24 <= op_mem_9_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_10_8_24
if (((ce == 1'b1) && (op_mem_10_8_24_rst == 1'b1)))
begin
op_mem_10_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_10_8_24_en == 1'b1)))
begin
op_mem_10_8_24 <= op_mem_10_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_11_8_24
if (((ce == 1'b1) && (op_mem_11_8_24_rst == 1'b1)))
begin
op_mem_11_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_11_8_24_en == 1'b1)))
begin
op_mem_11_8_24 <= op_mem_11_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_12_8_24
if (((ce == 1'b1) && (op_mem_12_8_24_rst == 1'b1)))
begin
op_mem_12_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_12_8_24_en == 1'b1)))
begin
op_mem_12_8_24 <= op_mem_12_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_13_8_24
if (((ce == 1'b1) && (op_mem_13_8_24_rst == 1'b1)))
begin
op_mem_13_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_13_8_24_en == 1'b1)))
begin
op_mem_13_8_24 <= op_mem_13_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_14_8_24
if (((ce == 1'b1) && (op_mem_14_8_24_rst == 1'b1)))
begin
op_mem_14_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_14_8_24_en == 1'b1)))
begin
op_mem_14_8_24 <= op_mem_14_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_15_8_24
if (((ce == 1'b1) && (op_mem_15_8_24_rst == 1'b1)))
begin
op_mem_15_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_15_8_24_en == 1'b1)))
begin
op_mem_15_8_24 <= op_mem_15_8_24_next;
end
end
always @(posedge clk)
begin:proc_op_mem_16_8_24
if (((ce == 1'b1) && (op_mem_16_8_24_rst == 1'b1)))
begin
op_mem_16_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_16_8_24_en == 1'b1)))
begin
op_mem_16_8_24 <= op_mem_16_8_24_next;
end
end
always @(d_1_22 or en_1_25 or op_mem_0_8_24 or op_mem_10_8_24 or op_mem_11_8_24 or op_mem_12_8_24 or op_mem_13_8_24 or op_mem_14_8_24 or op_mem_15_8_24 or op_mem_1_8_24 or op_mem_2_8_24 or op_mem_3_8_24 or op_mem_4_8_24 or op_mem_5_8_24 or op_mem_6_8_24 or op_mem_7_8_24 or op_mem_8_8_24 or op_mem_9_8_24 or rst_1_29)
begin:proc_if_10_5
if (rst_1_29)
begin
op_mem_0_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_0_join_10_5_rst = 1'b0;
end
else
begin
op_mem_0_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_0_join_10_5_en = 1'b1;
end
else
begin
op_mem_0_join_10_5_en = 1'b0;
end
op_mem_0_join_10_5 = d_1_22;
if (rst_1_29)
begin
op_mem_2_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_2_join_10_5_rst = 1'b0;
end
else
begin
op_mem_2_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_2_join_10_5_en = 1'b1;
end
else
begin
op_mem_2_join_10_5_en = 1'b0;
end
op_mem_2_join_10_5 = op_mem_1_8_24;
if (rst_1_29)
begin
op_mem_5_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_5_join_10_5_rst = 1'b0;
end
else
begin
op_mem_5_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_5_join_10_5_en = 1'b1;
end
else
begin
op_mem_5_join_10_5_en = 1'b0;
end
op_mem_5_join_10_5 = op_mem_4_8_24;
if (rst_1_29)
begin
op_mem_13_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_13_join_10_5_rst = 1'b0;
end
else
begin
op_mem_13_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_13_join_10_5_en = 1'b1;
end
else
begin
op_mem_13_join_10_5_en = 1'b0;
end
op_mem_13_join_10_5 = op_mem_12_8_24;
if (rst_1_29)
begin
op_mem_4_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_4_join_10_5_rst = 1'b0;
end
else
begin
op_mem_4_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_4_join_10_5_en = 1'b1;
end
else
begin
op_mem_4_join_10_5_en = 1'b0;
end
op_mem_4_join_10_5 = op_mem_3_8_24;
if (rst_1_29)
begin
op_mem_7_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_7_join_10_5_rst = 1'b0;
end
else
begin
op_mem_7_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_7_join_10_5_en = 1'b1;
end
else
begin
op_mem_7_join_10_5_en = 1'b0;
end
op_mem_7_join_10_5 = op_mem_6_8_24;
if (rst_1_29)
begin
op_mem_15_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_15_join_10_5_rst = 1'b0;
end
else
begin
op_mem_15_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_15_join_10_5_en = 1'b1;
end
else
begin
op_mem_15_join_10_5_en = 1'b0;
end
op_mem_15_join_10_5 = op_mem_14_8_24;
if (rst_1_29)
begin
op_mem_6_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_6_join_10_5_rst = 1'b0;
end
else
begin
op_mem_6_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_6_join_10_5_en = 1'b1;
end
else
begin
op_mem_6_join_10_5_en = 1'b0;
end
op_mem_6_join_10_5 = op_mem_5_8_24;
if (rst_1_29)
begin
op_mem_12_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_12_join_10_5_rst = 1'b0;
end
else
begin
op_mem_12_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_12_join_10_5_en = 1'b1;
end
else
begin
op_mem_12_join_10_5_en = 1'b0;
end
op_mem_12_join_10_5 = op_mem_11_8_24;
if (rst_1_29)
begin
op_mem_3_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_3_join_10_5_rst = 1'b0;
end
else
begin
op_mem_3_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_3_join_10_5_en = 1'b1;
end
else
begin
op_mem_3_join_10_5_en = 1'b0;
end
op_mem_3_join_10_5 = op_mem_2_8_24;
if (rst_1_29)
begin
op_mem_16_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_16_join_10_5_rst = 1'b0;
end
else
begin
op_mem_16_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_16_join_10_5_en = 1'b1;
end
else
begin
op_mem_16_join_10_5_en = 1'b0;
end
op_mem_16_join_10_5 = op_mem_15_8_24;
if (rst_1_29)
begin
op_mem_10_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_10_join_10_5_rst = 1'b0;
end
else
begin
op_mem_10_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_10_join_10_5_en = 1'b1;
end
else
begin
op_mem_10_join_10_5_en = 1'b0;
end
op_mem_10_join_10_5 = op_mem_9_8_24;
if (rst_1_29)
begin
op_mem_1_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_1_join_10_5_rst = 1'b0;
end
else
begin
op_mem_1_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_1_join_10_5_en = 1'b1;
end
else
begin
op_mem_1_join_10_5_en = 1'b0;
end
op_mem_1_join_10_5 = op_mem_0_8_24;
if (rst_1_29)
begin
op_mem_8_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_8_join_10_5_rst = 1'b0;
end
else
begin
op_mem_8_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_8_join_10_5_en = 1'b1;
end
else
begin
op_mem_8_join_10_5_en = 1'b0;
end
op_mem_8_join_10_5 = op_mem_7_8_24;
if (rst_1_29)
begin
op_mem_14_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_14_join_10_5_rst = 1'b0;
end
else
begin
op_mem_14_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_14_join_10_5_en = 1'b1;
end
else
begin
op_mem_14_join_10_5_en = 1'b0;
end
op_mem_14_join_10_5 = op_mem_13_8_24;
if (rst_1_29)
begin
op_mem_9_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_9_join_10_5_rst = 1'b0;
end
else
begin
op_mem_9_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_9_join_10_5_en = 1'b1;
end
else
begin
op_mem_9_join_10_5_en = 1'b0;
end
op_mem_9_join_10_5 = op_mem_8_8_24;
if (rst_1_29)
begin
op_mem_11_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_11_join_10_5_rst = 1'b0;
end
else
begin
op_mem_11_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_11_join_10_5_en = 1'b1;
end
else
begin
op_mem_11_join_10_5_en = 1'b0;
end
op_mem_11_join_10_5 = op_mem_10_8_24;
end
assign op_mem_0_8_24_next = d_1_22;
assign op_mem_0_8_24_rst = op_mem_0_join_10_5_rst;
assign op_mem_0_8_24_en = op_mem_0_join_10_5_en;
assign op_mem_1_8_24_next = op_mem_0_8_24;
assign op_mem_1_8_24_rst = op_mem_1_join_10_5_rst;
assign op_mem_1_8_24_en = op_mem_1_join_10_5_en;
assign op_mem_2_8_24_next = op_mem_1_8_24;
assign op_mem_2_8_24_rst = op_mem_2_join_10_5_rst;
assign op_mem_2_8_24_en = op_mem_2_join_10_5_en;
assign op_mem_3_8_24_next = op_mem_2_8_24;
assign op_mem_3_8_24_rst = op_mem_3_join_10_5_rst;
assign op_mem_3_8_24_en = op_mem_3_join_10_5_en;
assign op_mem_4_8_24_next = op_mem_3_8_24;
assign op_mem_4_8_24_rst = op_mem_4_join_10_5_rst;
assign op_mem_4_8_24_en = op_mem_4_join_10_5_en;
assign op_mem_5_8_24_next = op_mem_4_8_24;
assign op_mem_5_8_24_rst = op_mem_5_join_10_5_rst;
assign op_mem_5_8_24_en = op_mem_5_join_10_5_en;
assign op_mem_6_8_24_next = op_mem_5_8_24;
assign op_mem_6_8_24_rst = op_mem_6_join_10_5_rst;
assign op_mem_6_8_24_en = op_mem_6_join_10_5_en;
assign op_mem_7_8_24_next = op_mem_6_8_24;
assign op_mem_7_8_24_rst = op_mem_7_join_10_5_rst;
assign op_mem_7_8_24_en = op_mem_7_join_10_5_en;
assign op_mem_8_8_24_next = op_mem_7_8_24;
assign op_mem_8_8_24_rst = op_mem_8_join_10_5_rst;
assign op_mem_8_8_24_en = op_mem_8_join_10_5_en;
assign op_mem_9_8_24_next = op_mem_8_8_24;
assign op_mem_9_8_24_rst = op_mem_9_join_10_5_rst;
assign op_mem_9_8_24_en = op_mem_9_join_10_5_en;
assign op_mem_10_8_24_next = op_mem_9_8_24;
assign op_mem_10_8_24_rst = op_mem_10_join_10_5_rst;
assign op_mem_10_8_24_en = op_mem_10_join_10_5_en;
assign op_mem_11_8_24_next = op_mem_10_8_24;
assign op_mem_11_8_24_rst = op_mem_11_join_10_5_rst;
assign op_mem_11_8_24_en = op_mem_11_join_10_5_en;
assign op_mem_12_8_24_next = op_mem_11_8_24;
assign op_mem_12_8_24_rst = op_mem_12_join_10_5_rst;
assign op_mem_12_8_24_en = op_mem_12_join_10_5_en;
assign op_mem_13_8_24_next = op_mem_12_8_24;
assign op_mem_13_8_24_rst = op_mem_13_join_10_5_rst;
assign op_mem_13_8_24_en = op_mem_13_join_10_5_en;
assign op_mem_14_8_24_next = op_mem_13_8_24;
assign op_mem_14_8_24_rst = op_mem_14_join_10_5_rst;
assign op_mem_14_8_24_en = op_mem_14_join_10_5_en;
assign op_mem_15_8_24_next = op_mem_14_8_24;
assign op_mem_15_8_24_rst = op_mem_15_join_10_5_rst;
assign op_mem_15_8_24_en = op_mem_15_join_10_5_en;
assign op_mem_16_8_24_next = op_mem_15_8_24;
assign op_mem_16_8_24_rst = op_mem_16_join_10_5_rst;
assign op_mem_16_8_24_en = op_mem_16_join_10_5_en;
assign q = op_mem_16_8_24;
endmodule
`timescale 1 ns / 10 ps
module sysgen_delay_52cccd8896 (
input [(1 - 1):0] d,
input [(1 - 1):0] en,
input [(1 - 1):0] rst,
output [(1 - 1):0] q,
input clk,
input ce,
input clr);
wire d_1_22;
wire en_1_25;
wire rst_1_29;
wire op_mem_0_8_24_next;
reg op_mem_0_8_24 = 1'b0;
wire op_mem_0_8_24_rst;
wire op_mem_0_8_24_en;
localparam [(1 - 1):0] const_value = 1'b1;
reg op_mem_0_join_10_5;
reg op_mem_0_join_10_5_en;
reg op_mem_0_join_10_5_rst;
assign d_1_22 = d;
assign en_1_25 = en;
assign rst_1_29 = rst;
always @(posedge clk)
begin:proc_op_mem_0_8_24
if (((ce == 1'b1) && (op_mem_0_8_24_rst == 1'b1)))
begin
op_mem_0_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_0_8_24_en == 1'b1)))
begin
op_mem_0_8_24 <= op_mem_0_8_24_next;
end
end
always @(d_1_22 or en_1_25 or rst_1_29)
begin:proc_if_10_5
if (rst_1_29)
begin
op_mem_0_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_0_join_10_5_rst = 1'b0;
end
else
begin
op_mem_0_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_0_join_10_5_en = 1'b1;
end
else
begin
op_mem_0_join_10_5_en = 1'b0;
end
op_mem_0_join_10_5 = d_1_22;
end
assign op_mem_0_8_24_next = d_1_22;
assign op_mem_0_8_24_rst = op_mem_0_join_10_5_rst;
assign op_mem_0_8_24_en = op_mem_0_join_10_5_en;
assign q = op_mem_0_8_24;
endmodule
`timescale 1 ns / 10 ps
module sysgen_reinterpret_4bd3487388 (
input [(34 - 1):0] input_port,
output [(34 - 1):0] output_port,
input clk,
input ce,
input clr);
wire signed [(34 - 1):0] input_port_1_40;
wire [(34 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40;
assign output_port = output_port_5_5_force;
endmodule
`timescale 1 ns / 10 ps
module sysgen_constant_1aff05159a (
output [(4 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 4'b1111;
endmodule
`timescale 1 ns / 10 ps
module sysgen_relational_f303c211e7 (
input [(4 - 1):0] a,
input [(4 - 1):0] b,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire [(4 - 1):0] a_1_31;
wire [(4 - 1):0] b_1_34;
localparam [(1 - 1):0] const_value = 1'b1;
wire result_12_3_rel;
assign a_1_31 = a;
assign b_1_34 = b;
assign result_12_3_rel = a_1_31 == b_1_34;
assign op = result_12_3_rel;
endmodule
`timescale 1 ns / 10 ps
module sysgen_relational_fc1426e2d9 (
input [(8 - 1):0] a,
input [(8 - 1):0] b,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire [(8 - 1):0] a_1_31;
wire [(8 - 1):0] b_1_34;
localparam [(1 - 1):0] const_value = 1'b1;
wire result_12_3_rel;
assign a_1_31 = a;
assign b_1_34 = b;
assign result_12_3_rel = a_1_31 == b_1_34;
assign op = result_12_3_rel;
endmodule
`timescale 1 ns / 10 ps
module sysgen_relational_9133ff9c4b (
input [(2 - 1):0] a,
input [(2 - 1):0] b,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire [(2 - 1):0] a_1_31;
wire [(2 - 1):0] b_1_34;
localparam [(1 - 1):0] const_value = 1'b1;
wire result_12_3_rel;
assign a_1_31 = a;
assign b_1_34 = b;
assign result_12_3_rel = a_1_31 == b_1_34;
assign op = result_12_3_rel;
endmodule
`timescale 1 ns / 10 ps
module sysgen_constant_07b701207a (
output [(8 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 8'b11001000;
endmodule
`timescale 1 ns / 10 ps
module sysgen_constant_118900d9b9 (
output [(2 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 2'b11;
endmodule
//-----------------------------------------------------------------
// System Generator version 13.2 VERILOG source file.
//
// Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
// text/file contains proprietary, confidential information of Xilinx,
// Inc., is distributed under license from Xilinx, Inc., and may be used,
// copied and/or disclosed only pursuant to the terms of a valid license
// agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
// this text/file solely for design, simulation, implementation and
// creation of design files limited to Xilinx devices or technologies.
// Use with non-Xilinx devices or technologies is expressly prohibited
// and immediately terminates your license unless covered by a separate
// agreement.
//
// Xilinx is providing this design, code, or information "as is" solely
// for use in developing programs and solutions for Xilinx devices. By
// providing this design, code, or information as one possible
// implementation of this feature, application or standard, Xilinx is
// making no representation that this implementation is free from any
// claims of infringement. You are responsible for obtaining any rights
// you may require for your implementation. Xilinx expressly disclaims
// any warranty whatsoever with respect to the adequacy of the
// implementation, including but not limited to warranties of
// merchantability or fitness for a particular purpose.
//
// Xilinx products are not intended for use in life support appliances,
// devices, or systems. Use in such applications is expressly prohibited.
//
// Any modifications that are made to the source code are done at the user's
// sole risk and will be unsupported.
//
// This copyright and support notice must be retained as part of this
// text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
// reserved.
//-----------------------------------------------------------------
module channelizer_xlaxififogen(
s_aclk,
ce,
aresetn,
axis_underflow,
axis_overflow,
axis_data_count,
axis_prog_full_thresh,
axis_prog_empty_thresh,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
s_axis_tvalid,
s_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
m_axis_tvalid,
m_axis_tready
);
parameter core_name0 = "";
parameter has_aresetn = -1;
parameter tdata_width = -1;
parameter tdest_width = -1;
parameter tstrb_width = -1;
parameter tkeep_width = -1;
parameter tid_width = -1;
parameter tuser_width = -1;
parameter depth_bits = -1;
input ce;
input s_aclk;
input aresetn;
output axis_underflow;
output axis_overflow;
output [depth_bits-1:0] axis_data_count;
input [depth_bits-2:0] axis_prog_full_thresh;
input [depth_bits-2:0] axis_prog_empty_thresh;
input [tdata_width-1:0] s_axis_tdata;
input [tstrb_width-1:0] s_axis_tstrb;
input [tkeep_width-1:0] s_axis_tkeep;
input s_axis_tlast;
input [tid_width-1:0] s_axis_tid;
input [tdest_width-1:0] s_axis_tdest;
input [tuser_width-1:0] s_axis_tuser;
input s_axis_tvalid;
output s_axis_tready;
output [tdata_width-1:0] m_axis_tdata;
output [tstrb_width-1:0] m_axis_tstrb;
output [tkeep_width-1:0] m_axis_tkeep;
output m_axis_tlast;
output [tid_width-1:0] m_axis_tid;
output [tdest_width-1:0] m_axis_tdest;
output [tuser_width-1:0] m_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
wire srst;
reg reset_gen1 = 1'b0;
reg reset_gen_d1 = 1'b0;
reg reset_gen_d2 = 1'b0;
always @(posedge s_aclk)
begin
reset_gen1 <= 1'b1;
reset_gen_d1 <= reset_gen1;
reset_gen_d2 <= reset_gen_d1;
end
generate
if(has_aresetn == 0)
begin:if_block
assign srst = reset_gen_d2;
end
else
begin:else_block
assign srst = ~((~aresetn) & ce);
end
endgenerate
generate
if (core_name0 == "channelizer_fifo_generator_v12_0_0")
begin:comp0
channelizer_fifo_generator_v12_0_0 core_instance0 (
.s_aclk(s_aclk),
.s_aresetn(srst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid (s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid (m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready)
);
end
endgenerate
endmodule
module channelizer_xlcounter_free (ce, clr, clk, op, up, load, din, en, rst);
parameter core_name0= "";
parameter op_width= 5;
parameter op_arith= `xlSigned;
input ce, clr, clk;
input up, load;
input [op_width-1:0] din;
input en, rst;
output [op_width-1:0] op;
parameter [(8*op_width)-1:0] oneStr = { op_width{"1"}};
wire core_sinit;
wire core_ce;
wire [op_width-1:0] op_net;
assign core_ce = ce & en;
assign core_sinit = (clr | rst) & ce;
assign op = op_net;
generate
if (core_name0 == "channelizer_c_counter_binary_v12_0_0")
begin:comp0
channelizer_c_counter_binary_v12_0_0 core_instance0 (
.CLK(clk),
.CE(core_ce),
.SINIT(core_sinit),
.Q(op_net)
);
end
if (core_name0 == "channelizer_c_counter_binary_v12_0_1")
begin:comp1
channelizer_c_counter_binary_v12_0_1 core_instance1 (
.CLK(clk),
.CE(core_ce),
.SINIT(core_sinit),
.Q(op_net)
);
end
if (core_name0 == "channelizer_c_counter_binary_v12_0_2")
begin:comp2
channelizer_c_counter_binary_v12_0_2 core_instance2 (
.CLK(clk),
.CE(core_ce),
.SINIT(core_sinit),
.Q(op_net)
);
end
if (core_name0 == "channelizer_c_counter_binary_v12_0_3")
begin:comp3
channelizer_c_counter_binary_v12_0_3 core_instance3 (
.CLK(clk),
.CE(core_ce),
.SINIT(core_sinit),
.Q(op_net)
);
end
endgenerate
endmodule
module channelizer_xldpram (dina, addra, wea, a_ce, a_clk, rsta, ena, douta, dinb, addrb, web, b_ce, b_clk, rstb, enb, doutb);
parameter core_name0= "";
parameter c_width_a= 13;
parameter c_address_width_a= 4;
parameter c_width_b= 13;
parameter c_address_width_b= 4;
parameter latency= 1;
input [c_width_a-1:0] dina;
input [c_address_width_a-1:0] addra;
input wea, a_ce, a_clk, rsta, ena;
input [c_width_b-1:0] dinb;
input [c_address_width_b-1:0] addrb;
input web, b_ce, b_clk, rstb, enb;
output [c_width_a-1:0] douta;
output [c_width_b-1:0] doutb;
wire [c_address_width_a-1:0] core_addra;
wire [c_address_width_b-1:0] core_addrb;
wire [c_width_a-1:0] core_dina,core_douta,dly_douta;
wire [c_width_b-1:0] core_dinb,core_doutb,dly_doutb;
wire core_wea,core_web;
wire core_a_ce,core_b_ce;
wire sinita,sinitb;
assign core_addra = addra;
assign core_dina = dina;
assign douta = dly_douta;
assign core_wea = wea;
assign core_a_ce = a_ce & ena;
assign sinita = rsta & a_ce;
assign core_addrb = addrb;
assign core_dinb = dinb;
assign doutb = dly_doutb;
assign core_web = web;
assign core_b_ce = b_ce & enb;
assign sinitb = rstb & b_ce;
generate
if (core_name0 == "channelizer_blk_mem_gen_v8_2_0")
begin:comp0
channelizer_blk_mem_gen_v8_2_0 core_instance0 (
.addra(core_addra),
.clka(a_clk),
.addrb(core_addrb),
.clkb(b_clk),
.dina(core_dina),
.wea(core_wea),
.dinb(core_dinb),
.web(core_web),
.ena(core_a_ce),
.enb(core_b_ce),
.rsta(sinita),
.rstb(sinitb),
.douta(core_douta),
.doutb(core_doutb)
);
end
if (latency > 2)
begin:latency_test_instA
synth_reg # (c_width_a, latency-2)
regA(
.i(core_douta),
.ce(core_a_ce),
.clr(1'b0),
.clk(a_clk),
.o(dly_douta));
end
if (latency > 2)
begin:latency_test_instB
synth_reg # (c_width_b, latency-2)
regB(
.i(core_doutb),
.ce(core_b_ce),
.clr(1'b0),
.clk(b_clk),
.o(dly_doutb));
end
if (latency <= 2)
begin:latency1
assign dly_douta = core_douta;
assign dly_doutb = core_doutb;
end
endgenerate
endmodule
`timescale 1 ns / 10 ps
module xlfast_fourier_transform_c87919ddd6bfbf81b10158bf539068dc (ce,clk,event_data_in_channel_halt,event_data_out_channel_halt,event_frame_started,event_status_channel_halt,event_tlast_missing,event_tlast_unexpected,m_axis_data_tdata_xn_im_0,m_axis_data_tdata_xn_re_0,m_axis_data_tlast,m_axis_data_tready,m_axis_data_tvalid,rst,s_axis_config_tdata_fwd_inv,s_axis_config_tready,s_axis_config_tvalid,s_axis_data_tdata_xn_im_0,s_axis_data_tdata_xn_re_0,s_axis_data_tlast,s_axis_data_tready,s_axis_data_tvalid);
input ce;
input clk;
output event_data_in_channel_halt;
output event_data_out_channel_halt;
output event_frame_started;
output event_status_channel_halt;
output event_tlast_missing;
output event_tlast_unexpected;
output[20:0] m_axis_data_tdata_xn_im_0;
output[20:0] m_axis_data_tdata_xn_re_0;
output m_axis_data_tlast;
input m_axis_data_tready;
output m_axis_data_tvalid;
input rst;
input[0:0] s_axis_config_tdata_fwd_inv;
output s_axis_config_tready;
input s_axis_config_tvalid;
input[15:0] s_axis_data_tdata_xn_im_0;
input[15:0] s_axis_data_tdata_xn_re_0;
input s_axis_data_tlast;
output s_axis_data_tready;
input s_axis_data_tvalid;
wire aresetn_net;
wire[47:0] m_axis_data_tdata_net;
wire[7:0] s_axis_config_tdata_net;
wire[31:0] s_axis_data_tdata_net;
assign aresetn_net = rst | (~ ce);
assign m_axis_data_tdata_xn_im_0 = m_axis_data_tdata_net[44 : 24];
assign m_axis_data_tdata_xn_re_0 = m_axis_data_tdata_net[20 : 0];
assign s_axis_config_tdata_net[7 : 1] = 7'b0;
assign s_axis_config_tdata_net[0 : 0] = s_axis_config_tdata_fwd_inv;
assign s_axis_data_tdata_net[31 : 16] = s_axis_data_tdata_xn_im_0;
assign s_axis_data_tdata_net[15 : 0] = s_axis_data_tdata_xn_re_0;
channelizer_xfft_v9_0_0 channelizer_xfft_v9_0_0_instance(
.aclk(clk),
.aclken(ce),
.aresetn(aresetn_net),
.event_data_in_channel_halt(event_data_in_channel_halt),
.event_data_out_channel_halt(event_data_out_channel_halt),
.event_frame_started(event_frame_started),
.event_status_channel_halt(event_status_channel_halt),
.event_tlast_missing(event_tlast_missing),
.event_tlast_unexpected(event_tlast_unexpected),
.m_axis_data_tdata(m_axis_data_tdata_net),
.m_axis_data_tlast(m_axis_data_tlast),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tvalid(m_axis_data_tvalid),
.s_axis_config_tdata(s_axis_config_tdata_net),
.s_axis_config_tready(s_axis_config_tready),
.s_axis_config_tvalid(s_axis_config_tvalid),
.s_axis_data_tdata(s_axis_data_tdata_net),
.s_axis_data_tlast(s_axis_data_tlast),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tvalid(s_axis_data_tvalid)
);
endmodule
`timescale 1 ns / 10 ps
module xlfir_compiler_19490f93cbd7e22fee0db5c2ec90c7a6 (ce,clk,event_s_config_tlast_missing,event_s_config_tlast_unexpected,event_s_data_tlast_missing,event_s_data_tlast_unexpected,m_axis_data_tdata_path0,m_axis_data_tdata_path1,m_axis_data_tlast,m_axis_data_tready,m_axis_data_tvalid,rst,s_axis_config_tdata_fsel,s_axis_config_tlast,s_axis_config_tready,s_axis_config_tvalid,s_axis_data_tdata_path0,s_axis_data_tdata_path1,s_axis_data_tlast,s_axis_data_tready,s_axis_data_tvalid,src_ce,src_clk);
input ce;
input clk;
output event_s_config_tlast_missing;
output event_s_config_tlast_unexpected;
output event_s_data_tlast_missing;
output event_s_data_tlast_unexpected;
output[33:0] m_axis_data_tdata_path0;
output[33:0] m_axis_data_tdata_path1;
output m_axis_data_tlast;
input m_axis_data_tready;
output m_axis_data_tvalid;
input rst;
input[3:0] s_axis_config_tdata_fsel;
input s_axis_config_tlast;
output s_axis_config_tready;
input s_axis_config_tvalid;
input[17:0] s_axis_data_tdata_path0;
input[17:0] s_axis_data_tdata_path1;
input s_axis_data_tlast;
output s_axis_data_tready;
input s_axis_data_tvalid;
input src_ce;
input src_clk;
wire aresetn_net;
wire[79:0] m_axis_data_tdata_net;
wire[7:0] s_axis_config_tdata_net;
wire[47:0] s_axis_data_tdata_net;
assign aresetn_net = rst | (~ ce);
assign m_axis_data_tdata_path1 = m_axis_data_tdata_net[73 : 40];
assign m_axis_data_tdata_path0 = m_axis_data_tdata_net[33 : 0];
assign s_axis_config_tdata_net[7 : 4] = 4'b0;
assign s_axis_config_tdata_net[3 : 0] = s_axis_config_tdata_fsel;
assign s_axis_data_tdata_net[47 : 42] = 6'b0;
assign s_axis_data_tdata_net[41 : 24] = s_axis_data_tdata_path1;
assign s_axis_data_tdata_net[23 : 18] = 6'b0;
assign s_axis_data_tdata_net[17 : 0] = s_axis_data_tdata_path0;
channelizer_fir_compiler_v7_2_0 channelizer_fir_compiler_v7_2_0_instance(
.aclk(clk),
.aclken(ce),
.aresetn(aresetn_net),
.event_s_config_tlast_missing(event_s_config_tlast_missing),
.event_s_config_tlast_unexpected(event_s_config_tlast_unexpected),
.event_s_data_tlast_missing(event_s_data_tlast_missing),
.event_s_data_tlast_unexpected(event_s_data_tlast_unexpected),
.m_axis_data_tdata(m_axis_data_tdata_net),
.m_axis_data_tlast(m_axis_data_tlast),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tvalid(m_axis_data_tvalid),
.s_axis_config_tdata(s_axis_config_tdata_net),
.s_axis_config_tlast(s_axis_config_tlast),
.s_axis_config_tready(s_axis_config_tready),
.s_axis_config_tvalid(s_axis_config_tvalid),
.s_axis_data_tdata(s_axis_data_tdata_net),
.s_axis_data_tlast(s_axis_data_tlast),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tvalid(s_axis_data_tvalid)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S18KAPWR_TB_V
`define SKY130_FD_SC_LP__DLYBUF4S18KAPWR_TB_V
/**
* dlybuf4s18kapwr: Delay Buffer 4-stage 0.18um length inner stage
* gates on keep-alive power rail.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlybuf4s18kapwr.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg KAPWR;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
KAPWR = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 KAPWR = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 KAPWR = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 KAPWR = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 KAPWR = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 KAPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__dlybuf4s18kapwr dut (.A(A), .VPWR(VPWR), .VGND(VGND), .KAPWR(KAPWR), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S18KAPWR_TB_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_comm_vpi.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ([email protected]) ////
//// Gyorgy Jeney ([email protected]) ////
//// Nathan Yawn ([email protected]) ////
//// Raul Fajardo ([email protected]) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2008 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_comm_vpi.v,v $
// Revision 1.2.1 2009/09/08 14:57 rfajardo
// Changed clock and reset outputs to inputs for minsoc
//
// $Log: dbg_comm_vpi.v,v $
// Revision 1.2 2009/05/17 20:55:57 Nathan
// Changed email address to opencores.org
//
// Revision 1.1 2008/07/26 17:33:20 Nathan
// Added debug comm module for use with VPI / network communication.
//
// Revision 1.1 2002/03/28 19:59:54 lampret
// Added bench directory
//
// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
// First import.
//
// Revision 1.3 2001/09/24 14:06:13 mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.2 2001/09/20 10:10:30 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
//
//
//
//
`include "timescale.v"
`define JP_PORT "4567"
`define TIMEOUT_COUNT 6'd20 // 1/2 of a TCK clock will be this many SYS_CLK ticks. Must be less than 6 bits.
module dbg_comm_vpi (
SYS_CLK,
P_TMS,
P_TCK,
P_TRST,
P_TDI,
P_TDO
);
//parameter Tp = 20;
input SYS_CLK;
output P_TMS;
output P_TCK;
output P_TRST;
output P_TDI;
input P_TDO;
reg [4:0] memory; // [0:0];
wire P_TCK;
wire P_TRST;
wire P_TDI;
wire P_TMS;
wire P_TDO;
reg [3:0] in_word_r;
reg [5:0] clk_count;
// Handle commands from the upper level
initial
begin
in_word_r = 5'b0;
memory = 5'b0;
$jp_init(`JP_PORT);
#5500; // Wait until reset is complete
while(1)
begin
#1;
$jp_in(memory); // This will not change memory[][] if no command has been sent from jp
if(memory[4]) // was memory[0][4]
begin
in_word_r = memory[3:0];
memory = memory & 4'b1111;
clk_count = 6'b000000; // Reset the timeout clock in case jp wants to wait for a timeout / half TCK period
end
end
end
// Send the output bit to the upper layer
always @ (P_TDO)
begin
$jp_out(P_TDO);
end
assign P_TCK = in_word_r[0];
assign P_TRST = in_word_r[1];
assign P_TDI = in_word_r[2];
assign P_TMS = in_word_r[3];
// Send timeouts / wait periods to the upper layer
always @ (posedge SYS_CLK)
begin
if(clk_count < `TIMEOUT_COUNT) clk_count[5:0] = clk_count[5:0] + 1;
else if(clk_count == `TIMEOUT_COUNT) begin
$jp_wait_time();
clk_count[5:0] = clk_count[5:0] + 1;
end
// else it's already timed out, don't do anything
end
endmodule
|
// limbus_tristate_conduit_pin_sharer_0.v
// This file was auto-generated from altera_tristate_conduit_pin_sharer_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module limbus_tristate_conduit_pin_sharer_0 (
input wire clk_clk, // clk.clk
input wire reset_reset, // reset.reset
output wire request, // tcm.request
input wire grant, // .grant
output wire [18:0] sram_tcm_address_out, // .sram_tcm_address_out_out
output wire [1:0] sram_tcm_byteenable_n_out, // .sram_tcm_byteenable_n_out_out
output wire [0:0] sram_tcm_outputenable_n_out, // .sram_tcm_outputenable_n_out_out
output wire [0:0] sram_tcm_write_n_out, // .sram_tcm_write_n_out_out
output wire [15:0] sram_tcm_data_out, // .sram_tcm_data_out_out
input wire [15:0] sram_tcm_data_in, // .sram_tcm_data_out_in
output wire sram_tcm_data_outen, // .sram_tcm_data_out_outen
output wire [0:0] sram_tcm_chipselect_n_out, // .sram_tcm_chipselect_n_out_out
input wire tcs0_request, // tcs0.request
output wire tcs0_grant, // .grant
input wire [18:0] tcs0_address_out, // .address_out
input wire [1:0] tcs0_byteenable_n_out, // .byteenable_n_out
input wire [0:0] tcs0_outputenable_n_out, // .outputenable_n_out
input wire [0:0] tcs0_write_n_out, // .write_n_out
input wire [15:0] tcs0_data_out, // .data_out
output wire [15:0] tcs0_data_in, // .data_in
input wire tcs0_data_outen, // .data_outen
input wire [0:0] tcs0_chipselect_n_out // .chipselect_n_out
);
wire [0:0] arbiter_grant_data; // arbiter:next_grant -> pin_sharer:next_grant
wire arbiter_grant_ready; // pin_sharer:ack -> arbiter:ack
wire pin_sharer_tcs0_arb_valid; // pin_sharer:arb_sram_tcm -> arbiter:sink0_valid
limbus_tristate_conduit_pin_sharer_0_pin_sharer pin_sharer (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // reset.reset
.request (request), // tcm.request
.grant (grant), // .grant
.sram_tcm_address_out (sram_tcm_address_out), // .sram_tcm_address_out_out
.sram_tcm_byteenable_n_out (sram_tcm_byteenable_n_out), // .sram_tcm_byteenable_n_out_out
.sram_tcm_outputenable_n_out (sram_tcm_outputenable_n_out), // .sram_tcm_outputenable_n_out_out
.sram_tcm_write_n_out (sram_tcm_write_n_out), // .sram_tcm_write_n_out_out
.sram_tcm_data_out (sram_tcm_data_out), // .sram_tcm_data_out_out
.sram_tcm_data_in (sram_tcm_data_in), // .sram_tcm_data_out_in
.sram_tcm_data_outen (sram_tcm_data_outen), // .sram_tcm_data_out_outen
.sram_tcm_chipselect_n_out (sram_tcm_chipselect_n_out), // .sram_tcm_chipselect_n_out_out
.tcs0_request (tcs0_request), // tcs0.request
.tcs0_grant (tcs0_grant), // .grant
.tcs0_tcm_address_out (tcs0_address_out), // .address_out
.tcs0_tcm_byteenable_n_out (tcs0_byteenable_n_out), // .byteenable_n_out
.tcs0_tcm_outputenable_n_out (tcs0_outputenable_n_out), // .outputenable_n_out
.tcs0_tcm_write_n_out (tcs0_write_n_out), // .write_n_out
.tcs0_tcm_data_out (tcs0_data_out), // .data_out
.tcs0_tcm_data_in (tcs0_data_in), // .data_in
.tcs0_tcm_data_outen (tcs0_data_outen), // .data_outen
.tcs0_tcm_chipselect_n_out (tcs0_chipselect_n_out), // .chipselect_n_out
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.arb_sram_tcm (pin_sharer_tcs0_arb_valid) // tcs0_arb.valid
);
limbus_tristate_conduit_pin_sharer_0_arbiter arbiter (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // clk_reset.reset
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.sink0_valid (pin_sharer_tcs0_arb_valid) // sink0.valid
);
endmodule
|
/*
for a elctric speed control, we will be generationg
1 - 1.5MS plus width: rolling speed from -max to 0, 0.1ms as 1 step
1.5 - 2MS plus width: rolling speed from 0 to +max
the pwm period is 18--22ms here we defined it as 20MS, 50 HZ
*/
module quadpwm(rst_n, freq_clk, enable, mode, led);
input rst_n;
input freq_clk;
input enable;
input mode;
output pwm0;
output pwm1;
output pwm2;
output pwm3;
reg pwm0_reg;
reg pwm1_reg;
reg pwm2_reg;
reg pwm3_reg;
reg[31:0] engine_reg;
//debug led
reg led;
// generate 2500 Hz from 50 MHz
reg [31:0] count_reg;
reg pwm_clk;
always @(posedge freq_clk or negedge rst_n) begin
if (!rst_n) begin
count_reg <= 0;
pwm_clk <= 0;
end
else if (enable)
begin
if (count_reg < 999999) begin
count_reg <= count_reg + 1;
end else begin
count_reg <= 0;
pwm_clk <= ~pwm_clk;
end
end
end
reg[31:0] pwm_load_register;
/*process the pwm0 signal period*/
always @ (posedge pwm_clk or negedge rst_n)
begin
if (!rst_n)
begin
pwm_load_register <= 1'b0;
end
else if (out_div)
begin
case (pha_reg)
1'd1:
begin
pha_reg <= 1'd0;
end
1'd0:
begin
pha_reg <= 1'd1;
end
endcase
end
end
assign pwm0 = pwm0_reg;
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07:56:48 06/02/2013
// Design Name:
// Module Name: rom
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rom ( input [7:0] addr,output reg [15:0] dout );
always @ (addr)
case (addr)
8'b0000_0000: dout = 16'b0111_0000_0001_0111; ///addi r1,r0,#7;
8'b0000_0001: dout = 16'b1000_0001_0010_0010; //Subi r2,r1,#2
8'b0000_0010: dout = 16'b1010_0000_0010_0000; //store [r0],r2
8'b0000_0011: dout = 16'b1001_0000_0011_0000; //load r3 [r0]
8'b0000_0100: dout = 16'b0001_0001_0010_0100; //add r4,r1,r2
8'b0000_0101: dout = 16'b0010_0100_0010_0101; //Sub r5,r4,r2
8'b0000_0110: dout = 16'b1100_0000_0101_0001; //stori [1],$r5;
8'b0000_0111: dout = 16'b1011_0000_0110_0001; //loadi r6,[1];
8'b0000_1000: dout = 16'b0101_0100_0111_0011; //SHL r7, r4,#3
8'b0000_1001: dout = 16'b0110_0100_1000_0010; //SHR r8,r4,#2
8'b0000_1010: dout = 16'b0011_0100_0001_1001; //AND R9, R4, R1;
8'b0000_1011: dout = 16'b0100_0100_0010_1010; //OR R10, R4, R2;
8'b0000_1100: dout = 16'b1101_0110_0101_0111; //Bre Jump R10, R4, R2;
8'b0000_1101: dout = 16'b0000_0000_0000_0000; //Halt
default: dout = 16'h0000;
endcase
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// usbHostSlaveAvalonWrap.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module wrapper. Enable connection to Altera Avalon bus
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module usbHostSlaveAvalonWrap(
clk,
reset,
address,
writedata,
readdata,
write,
read,
waitrequest,
chipselect,
irq,
usbClk,
USBWireVPI,
USBWireVMI,
USBWireDataInTick,
USBWireVPO,
USBWireVMO,
USBWireDataOutTick,
USBWireOutEn_n,
USBFullSpeed
);
input clk;
input reset;
input [7:0] address;
input [7:0] writedata;
output [7:0] readdata;
input write;
input read;
output waitrequest;
input chipselect;
output irq;
input usbClk;
input USBWireVPI /* synthesis useioff=1 */;
input USBWireVMI /* synthesis useioff=1 */;
output USBWireVPO /* synthesis useioff=1 */;
output USBWireVMO /* synthesis useioff=1 */;
output USBWireDataOutTick /* synthesis useioff=1 */;
output USBWireDataInTick /* synthesis useioff=1 */;
output USBWireOutEn_n /* synthesis useioff=1 */;
output USBFullSpeed /* synthesis useioff=1 */;
wire clk;
wire reset;
wire [7:0] address;
wire [7:0] writedata;
wire [7:0] readdata;
wire write;
wire read;
wire waitrequest;
wire chipselect;
wire irq;
wire usbClk;
wire USBWireVPI;
wire USBWireVMI;
wire USBWireVPO;
wire USBWireVMO;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBWireOutEn_n;
wire USBFullSpeed;
//internal wiring
wire strobe_i;
wire ack_o;
wire hostSOFSentIntOut;
wire hostConnEventIntOut;
wire hostResumeIntOut;
wire hostTransDoneIntOut;
wire slaveSOFRxedIntOut;
wire slaveResetEventIntOut;
wire slaveResumeIntOut;
wire slaveTransDoneIntOut;
wire slaveNAKSentIntOut;
wire USBWireCtrlOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
assign irq = hostSOFSentIntOut | hostConnEventIntOut |
hostResumeIntOut | hostTransDoneIntOut |
slaveSOFRxedIntOut | slaveResetEventIntOut |
slaveResumeIntOut | slaveTransDoneIntOut |
slaveNAKSentIntOut;
assign strobe_i = chipselect & ( read | write);
assign waitrequest = ~ack_o;
assign USBWireOutEn_n = ~USBWireCtrlOut;
assign USBWireDataIn = {USBWireVPI, USBWireVMI};
assign {USBWireVPO, USBWireVMO} = USBWireDataOut;
//Parameters declaration:
defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
parameter HOST_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
parameter HOST_FIFO_ADDR_WIDTH = 6;
defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
parameter EP0_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
parameter EP0_FIFO_ADDR_WIDTH = 6;
defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
parameter EP1_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
parameter EP1_FIFO_ADDR_WIDTH = 6;
defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
parameter EP2_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
parameter EP2_FIFO_ADDR_WIDTH = 6;
defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
parameter EP3_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
parameter EP3_FIFO_ADDR_WIDTH = 6;
usbHostSlave usbHostSlaveInst (
.clk_i(clk),
.rst_i(reset),
.address_i(address),
.data_i(writedata),
.data_o(readdata),
.we_i(write),
.strobe_i(strobe_i),
.ack_o(ack_o),
.usbClk(usbClk),
.hostSOFSentIntOut(hostSOFSentIntOut),
.hostConnEventIntOut(hostConnEventIntOut),
.hostResumeIntOut(hostResumeIntOut),
.hostTransDoneIntOut(hostTransDoneIntOut),
.slaveSOFRxedIntOut(slaveSOFRxedIntOut),
.slaveResetEventIntOut(slaveResetEventIntOut),
.slaveResumeIntOut(slaveResumeIntOut),
.slaveTransDoneIntOut(slaveTransDoneIntOut),
.slaveNAKSentIntOut(slaveNAKSentIntOut),
.USBWireDataIn(USBWireDataIn),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOut(USBWireDataOut),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.USBFullSpeed(USBFullSpeed));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NAND4_PP_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4_PP_SYMBOL_V
|
//-----------------------------------------------------------------------------
// File : test_setup.v
// Creation date : 28.11.2017
// Creation time : 16:51:22
// Description : Test arrangement for verifying the wishbone example design.
// Created by : TermosPullo
// Tool : Kactus2 3.4.1176 32-bit
// Plugin : Verilog generator 2.1
// This file was generated based on IP-XACT component tut.fi:other.subsystem.test:wb_example.setup:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/other.subsystem.test/wb_example.setup/1.0/wb_example.setup.1.0.xml
//-----------------------------------------------------------------------------
module test_setup();
// clock_generator_0_wb_system_to_wb_example_0_wb_system wires:
wire clock_generator_0_wb_system_to_wb_example_0_wb_systemclk;
wire clock_generator_0_wb_system_to_wb_example_0_wb_systemrst;
// Ad-hoc wires:
wire wb_example_0_start_to_wb_example_bench_0_start;
wire wb_example_0_done_to_wb_example_bench_0_done;
wire wb_example_bench_0_clk_i_to_clock_generator_0_clk_o;
wire wb_example_bench_0_rst_i_to_clock_generator_0_rst_o;
// clock_generator_0 port wires:
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
// wb_example.bench_0 port wires:
wire wb_example_bench_0_clk_i;
wire wb_example_bench_0_done;
wire wb_example_bench_0_rst_i;
wire wb_example_bench_0_start;
// wb_example_0 port wires:
wire wb_example_0_clk_i;
wire wb_example_0_done;
wire wb_example_0_rst_i;
wire wb_example_0_start;
// clock_generator_0 assignments:
assign clock_generator_0_wb_system_to_wb_example_0_wb_systemclk = clock_generator_0_clk_o;
assign wb_example_bench_0_clk_i_to_clock_generator_0_clk_o = clock_generator_0_clk_o;
assign clock_generator_0_wb_system_to_wb_example_0_wb_systemrst = clock_generator_0_rst_o;
assign wb_example_bench_0_rst_i_to_clock_generator_0_rst_o = clock_generator_0_rst_o;
// wb_example.bench_0 assignments:
assign wb_example_bench_0_clk_i = wb_example_bench_0_clk_i_to_clock_generator_0_clk_o;
assign wb_example_bench_0_done = wb_example_0_done_to_wb_example_bench_0_done;
assign wb_example_bench_0_rst_i = wb_example_bench_0_rst_i_to_clock_generator_0_rst_o;
assign wb_example_0_start_to_wb_example_bench_0_start = wb_example_bench_0_start;
// wb_example_0 assignments:
assign wb_example_0_clk_i = clock_generator_0_wb_system_to_wb_example_0_wb_systemclk;
assign wb_example_0_done_to_wb_example_bench_0_done = wb_example_0_done;
assign wb_example_0_rst_i = clock_generator_0_wb_system_to_wb_example_0_wb_systemrst;
assign wb_example_0_start = wb_example_0_start_to_wb_example_bench_0_start;
// IP-XACT VLNV: tut.fi:other.test:clock_generator:1.1
clock_generator clock_generator_0(
// Interface: wb_system
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
// IP-XACT VLNV: tut.fi:other.subsystem.test:wb_example.bench:1.0
TestInitializer #(
.WAIT_TIME (1200))
wb_example_bench_0(
// These ports are not in any interface
.clk_i (wb_example_bench_0_clk_i),
.done (wb_example_bench_0_done),
.rst_i (wb_example_bench_0_rst_i),
.start (wb_example_bench_0_start));
// IP-XACT VLNV: tut.fi:other.subsystem:wb_example:1.0
wb_example_0 wb_example_0(
// Interface: wb_system
.clk_i (wb_example_0_clk_i),
.rst_i (wb_example_0_rst_i),
// These ports are not in any interface
.start (wb_example_0_start),
.done (wb_example_0_done));
endmodule
|
// system_acl_iface_acl_kernel_interface_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.05.05.08:40:40
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface_mm_interconnect_1 (
input wire clk_reset_clk_clk, // clk_reset_clk.clk
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cntrl_reset_reset_bridge_in_reset_reset, // kernel_cntrl_reset_reset_bridge_in_reset.reset
input wire sw_reset_clk_reset_reset_bridge_in_reset_reset, // sw_reset_clk_reset_reset_bridge_in_reset.reset
input wire [13:0] kernel_cntrl_m0_address, // kernel_cntrl_m0.address
output wire kernel_cntrl_m0_waitrequest, // .waitrequest
input wire [0:0] kernel_cntrl_m0_burstcount, // .burstcount
input wire [3:0] kernel_cntrl_m0_byteenable, // .byteenable
input wire kernel_cntrl_m0_read, // .read
output wire [31:0] kernel_cntrl_m0_readdata, // .readdata
output wire kernel_cntrl_m0_readdatavalid, // .readdatavalid
input wire kernel_cntrl_m0_write, // .write
input wire [31:0] kernel_cntrl_m0_writedata, // .writedata
input wire kernel_cntrl_m0_debugaccess, // .debugaccess
output wire address_span_extender_0_cntl_write, // address_span_extender_0_cntl.write
output wire address_span_extender_0_cntl_read, // .read
input wire [63:0] address_span_extender_0_cntl_readdata, // .readdata
output wire [63:0] address_span_extender_0_cntl_writedata, // .writedata
output wire [7:0] address_span_extender_0_cntl_byteenable, // .byteenable
output wire [9:0] address_span_extender_0_windowed_slave_address, // address_span_extender_0_windowed_slave.address
output wire address_span_extender_0_windowed_slave_write, // .write
output wire address_span_extender_0_windowed_slave_read, // .read
input wire [31:0] address_span_extender_0_windowed_slave_readdata, // .readdata
output wire [31:0] address_span_extender_0_windowed_slave_writedata, // .writedata
output wire [0:0] address_span_extender_0_windowed_slave_burstcount, // .burstcount
output wire [3:0] address_span_extender_0_windowed_slave_byteenable, // .byteenable
input wire address_span_extender_0_windowed_slave_readdatavalid, // .readdatavalid
input wire address_span_extender_0_windowed_slave_waitrequest, // .waitrequest
output wire irq_ena_0_s_write, // irq_ena_0_s.write
output wire irq_ena_0_s_read, // .read
input wire [31:0] irq_ena_0_s_readdata, // .readdata
output wire [31:0] irq_ena_0_s_writedata, // .writedata
output wire [3:0] irq_ena_0_s_byteenable, // .byteenable
input wire irq_ena_0_s_waitrequest, // .waitrequest
output wire mem_org_mode_s_write, // mem_org_mode_s.write
output wire mem_org_mode_s_read, // .read
input wire [31:0] mem_org_mode_s_readdata, // .readdata
output wire [31:0] mem_org_mode_s_writedata, // .writedata
input wire mem_org_mode_s_waitrequest, // .waitrequest
output wire sw_reset_s_write, // sw_reset_s.write
output wire sw_reset_s_read, // .read
input wire [63:0] sw_reset_s_readdata, // .readdata
output wire [63:0] sw_reset_s_writedata, // .writedata
output wire [7:0] sw_reset_s_byteenable, // .byteenable
input wire sw_reset_s_waitrequest, // .waitrequest
output wire [8:0] sys_description_rom_s1_address, // sys_description_rom_s1.address
output wire sys_description_rom_s1_write, // .write
input wire [63:0] sys_description_rom_s1_readdata, // .readdata
output wire [63:0] sys_description_rom_s1_writedata, // .writedata
output wire [7:0] sys_description_rom_s1_byteenable, // .byteenable
output wire sys_description_rom_s1_chipselect, // .chipselect
output wire sys_description_rom_s1_clken, // .clken
output wire sys_description_rom_s1_debugaccess, // .debugaccess
output wire version_id_0_s_read, // version_id_0_s.read
input wire [31:0] version_id_0_s_readdata // .readdata
);
wire kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest; // kernel_cntrl_m0_agent:av_waitrequest -> kernel_cntrl_m0_translator:uav_waitrequest
wire [2:0] kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount; // kernel_cntrl_m0_translator:uav_burstcount -> kernel_cntrl_m0_agent:av_burstcount
wire [31:0] kernel_cntrl_m0_translator_avalon_universal_master_0_writedata; // kernel_cntrl_m0_translator:uav_writedata -> kernel_cntrl_m0_agent:av_writedata
wire [13:0] kernel_cntrl_m0_translator_avalon_universal_master_0_address; // kernel_cntrl_m0_translator:uav_address -> kernel_cntrl_m0_agent:av_address
wire kernel_cntrl_m0_translator_avalon_universal_master_0_lock; // kernel_cntrl_m0_translator:uav_lock -> kernel_cntrl_m0_agent:av_lock
wire kernel_cntrl_m0_translator_avalon_universal_master_0_write; // kernel_cntrl_m0_translator:uav_write -> kernel_cntrl_m0_agent:av_write
wire kernel_cntrl_m0_translator_avalon_universal_master_0_read; // kernel_cntrl_m0_translator:uav_read -> kernel_cntrl_m0_agent:av_read
wire [31:0] kernel_cntrl_m0_translator_avalon_universal_master_0_readdata; // kernel_cntrl_m0_agent:av_readdata -> kernel_cntrl_m0_translator:uav_readdata
wire kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess; // kernel_cntrl_m0_translator:uav_debugaccess -> kernel_cntrl_m0_agent:av_debugaccess
wire [3:0] kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable; // kernel_cntrl_m0_translator:uav_byteenable -> kernel_cntrl_m0_agent:av_byteenable
wire kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid; // kernel_cntrl_m0_agent:av_readdatavalid -> kernel_cntrl_m0_translator:uav_readdatavalid
wire address_span_extender_0_windowed_slave_agent_m0_waitrequest; // address_span_extender_0_windowed_slave_translator:uav_waitrequest -> address_span_extender_0_windowed_slave_agent:m0_waitrequest
wire [2:0] address_span_extender_0_windowed_slave_agent_m0_burstcount; // address_span_extender_0_windowed_slave_agent:m0_burstcount -> address_span_extender_0_windowed_slave_translator:uav_burstcount
wire [31:0] address_span_extender_0_windowed_slave_agent_m0_writedata; // address_span_extender_0_windowed_slave_agent:m0_writedata -> address_span_extender_0_windowed_slave_translator:uav_writedata
wire [13:0] address_span_extender_0_windowed_slave_agent_m0_address; // address_span_extender_0_windowed_slave_agent:m0_address -> address_span_extender_0_windowed_slave_translator:uav_address
wire address_span_extender_0_windowed_slave_agent_m0_write; // address_span_extender_0_windowed_slave_agent:m0_write -> address_span_extender_0_windowed_slave_translator:uav_write
wire address_span_extender_0_windowed_slave_agent_m0_lock; // address_span_extender_0_windowed_slave_agent:m0_lock -> address_span_extender_0_windowed_slave_translator:uav_lock
wire address_span_extender_0_windowed_slave_agent_m0_read; // address_span_extender_0_windowed_slave_agent:m0_read -> address_span_extender_0_windowed_slave_translator:uav_read
wire [31:0] address_span_extender_0_windowed_slave_agent_m0_readdata; // address_span_extender_0_windowed_slave_translator:uav_readdata -> address_span_extender_0_windowed_slave_agent:m0_readdata
wire address_span_extender_0_windowed_slave_agent_m0_readdatavalid; // address_span_extender_0_windowed_slave_translator:uav_readdatavalid -> address_span_extender_0_windowed_slave_agent:m0_readdatavalid
wire address_span_extender_0_windowed_slave_agent_m0_debugaccess; // address_span_extender_0_windowed_slave_agent:m0_debugaccess -> address_span_extender_0_windowed_slave_translator:uav_debugaccess
wire [3:0] address_span_extender_0_windowed_slave_agent_m0_byteenable; // address_span_extender_0_windowed_slave_agent:m0_byteenable -> address_span_extender_0_windowed_slave_translator:uav_byteenable
wire address_span_extender_0_windowed_slave_agent_rf_source_endofpacket; // address_span_extender_0_windowed_slave_agent:rf_source_endofpacket -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_endofpacket
wire address_span_extender_0_windowed_slave_agent_rf_source_valid; // address_span_extender_0_windowed_slave_agent:rf_source_valid -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_valid
wire address_span_extender_0_windowed_slave_agent_rf_source_startofpacket; // address_span_extender_0_windowed_slave_agent:rf_source_startofpacket -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_startofpacket
wire [89:0] address_span_extender_0_windowed_slave_agent_rf_source_data; // address_span_extender_0_windowed_slave_agent:rf_source_data -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_data
wire address_span_extender_0_windowed_slave_agent_rf_source_ready; // address_span_extender_0_windowed_slave_agent_rsp_fifo:in_ready -> address_span_extender_0_windowed_slave_agent:rf_source_ready
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_endofpacket -> address_span_extender_0_windowed_slave_agent:rf_sink_endofpacket
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_valid -> address_span_extender_0_windowed_slave_agent:rf_sink_valid
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_startofpacket -> address_span_extender_0_windowed_slave_agent:rf_sink_startofpacket
wire [89:0] address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_data -> address_span_extender_0_windowed_slave_agent:rf_sink_data
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready; // address_span_extender_0_windowed_slave_agent:rf_sink_ready -> address_span_extender_0_windowed_slave_agent_rsp_fifo:out_ready
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid; // address_span_extender_0_windowed_slave_agent:rdata_fifo_src_valid -> address_span_extender_0_windowed_slave_agent_rdata_fifo:in_valid
wire [33:0] address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data; // address_span_extender_0_windowed_slave_agent:rdata_fifo_src_data -> address_span_extender_0_windowed_slave_agent_rdata_fifo:in_data
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready; // address_span_extender_0_windowed_slave_agent_rdata_fifo:in_ready -> address_span_extender_0_windowed_slave_agent:rdata_fifo_src_ready
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid; // address_span_extender_0_windowed_slave_agent_rdata_fifo:out_valid -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_valid
wire [33:0] address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data; // address_span_extender_0_windowed_slave_agent_rdata_fifo:out_data -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_data
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready; // address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_ready -> address_span_extender_0_windowed_slave_agent_rdata_fifo:out_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> address_span_extender_0_windowed_slave_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> address_span_extender_0_windowed_slave_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> address_span_extender_0_windowed_slave_agent:cp_startofpacket
wire [88:0] cmd_mux_src_data; // cmd_mux:src_data -> address_span_extender_0_windowed_slave_agent:cp_data
wire [6:0] cmd_mux_src_channel; // cmd_mux:src_channel -> address_span_extender_0_windowed_slave_agent:cp_channel
wire cmd_mux_src_ready; // address_span_extender_0_windowed_slave_agent:cp_ready -> cmd_mux:src_ready
wire address_span_extender_0_cntl_agent_m0_waitrequest; // address_span_extender_0_cntl_translator:uav_waitrequest -> address_span_extender_0_cntl_agent:m0_waitrequest
wire [3:0] address_span_extender_0_cntl_agent_m0_burstcount; // address_span_extender_0_cntl_agent:m0_burstcount -> address_span_extender_0_cntl_translator:uav_burstcount
wire [63:0] address_span_extender_0_cntl_agent_m0_writedata; // address_span_extender_0_cntl_agent:m0_writedata -> address_span_extender_0_cntl_translator:uav_writedata
wire [13:0] address_span_extender_0_cntl_agent_m0_address; // address_span_extender_0_cntl_agent:m0_address -> address_span_extender_0_cntl_translator:uav_address
wire address_span_extender_0_cntl_agent_m0_write; // address_span_extender_0_cntl_agent:m0_write -> address_span_extender_0_cntl_translator:uav_write
wire address_span_extender_0_cntl_agent_m0_lock; // address_span_extender_0_cntl_agent:m0_lock -> address_span_extender_0_cntl_translator:uav_lock
wire address_span_extender_0_cntl_agent_m0_read; // address_span_extender_0_cntl_agent:m0_read -> address_span_extender_0_cntl_translator:uav_read
wire [63:0] address_span_extender_0_cntl_agent_m0_readdata; // address_span_extender_0_cntl_translator:uav_readdata -> address_span_extender_0_cntl_agent:m0_readdata
wire address_span_extender_0_cntl_agent_m0_readdatavalid; // address_span_extender_0_cntl_translator:uav_readdatavalid -> address_span_extender_0_cntl_agent:m0_readdatavalid
wire address_span_extender_0_cntl_agent_m0_debugaccess; // address_span_extender_0_cntl_agent:m0_debugaccess -> address_span_extender_0_cntl_translator:uav_debugaccess
wire [7:0] address_span_extender_0_cntl_agent_m0_byteenable; // address_span_extender_0_cntl_agent:m0_byteenable -> address_span_extender_0_cntl_translator:uav_byteenable
wire address_span_extender_0_cntl_agent_rf_source_endofpacket; // address_span_extender_0_cntl_agent:rf_source_endofpacket -> address_span_extender_0_cntl_agent_rsp_fifo:in_endofpacket
wire address_span_extender_0_cntl_agent_rf_source_valid; // address_span_extender_0_cntl_agent:rf_source_valid -> address_span_extender_0_cntl_agent_rsp_fifo:in_valid
wire address_span_extender_0_cntl_agent_rf_source_startofpacket; // address_span_extender_0_cntl_agent:rf_source_startofpacket -> address_span_extender_0_cntl_agent_rsp_fifo:in_startofpacket
wire [125:0] address_span_extender_0_cntl_agent_rf_source_data; // address_span_extender_0_cntl_agent:rf_source_data -> address_span_extender_0_cntl_agent_rsp_fifo:in_data
wire address_span_extender_0_cntl_agent_rf_source_ready; // address_span_extender_0_cntl_agent_rsp_fifo:in_ready -> address_span_extender_0_cntl_agent:rf_source_ready
wire address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket; // address_span_extender_0_cntl_agent_rsp_fifo:out_endofpacket -> address_span_extender_0_cntl_agent:rf_sink_endofpacket
wire address_span_extender_0_cntl_agent_rsp_fifo_out_valid; // address_span_extender_0_cntl_agent_rsp_fifo:out_valid -> address_span_extender_0_cntl_agent:rf_sink_valid
wire address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket; // address_span_extender_0_cntl_agent_rsp_fifo:out_startofpacket -> address_span_extender_0_cntl_agent:rf_sink_startofpacket
wire [125:0] address_span_extender_0_cntl_agent_rsp_fifo_out_data; // address_span_extender_0_cntl_agent_rsp_fifo:out_data -> address_span_extender_0_cntl_agent:rf_sink_data
wire address_span_extender_0_cntl_agent_rsp_fifo_out_ready; // address_span_extender_0_cntl_agent:rf_sink_ready -> address_span_extender_0_cntl_agent_rsp_fifo:out_ready
wire address_span_extender_0_cntl_agent_rdata_fifo_src_valid; // address_span_extender_0_cntl_agent:rdata_fifo_src_valid -> address_span_extender_0_cntl_agent_rdata_fifo:in_valid
wire [65:0] address_span_extender_0_cntl_agent_rdata_fifo_src_data; // address_span_extender_0_cntl_agent:rdata_fifo_src_data -> address_span_extender_0_cntl_agent_rdata_fifo:in_data
wire address_span_extender_0_cntl_agent_rdata_fifo_src_ready; // address_span_extender_0_cntl_agent_rdata_fifo:in_ready -> address_span_extender_0_cntl_agent:rdata_fifo_src_ready
wire address_span_extender_0_cntl_agent_rdata_fifo_out_valid; // address_span_extender_0_cntl_agent_rdata_fifo:out_valid -> address_span_extender_0_cntl_agent:rdata_fifo_sink_valid
wire [65:0] address_span_extender_0_cntl_agent_rdata_fifo_out_data; // address_span_extender_0_cntl_agent_rdata_fifo:out_data -> address_span_extender_0_cntl_agent:rdata_fifo_sink_data
wire address_span_extender_0_cntl_agent_rdata_fifo_out_ready; // address_span_extender_0_cntl_agent:rdata_fifo_sink_ready -> address_span_extender_0_cntl_agent_rdata_fifo:out_ready
wire sys_description_rom_s1_agent_m0_waitrequest; // sys_description_rom_s1_translator:uav_waitrequest -> sys_description_rom_s1_agent:m0_waitrequest
wire [3:0] sys_description_rom_s1_agent_m0_burstcount; // sys_description_rom_s1_agent:m0_burstcount -> sys_description_rom_s1_translator:uav_burstcount
wire [63:0] sys_description_rom_s1_agent_m0_writedata; // sys_description_rom_s1_agent:m0_writedata -> sys_description_rom_s1_translator:uav_writedata
wire [13:0] sys_description_rom_s1_agent_m0_address; // sys_description_rom_s1_agent:m0_address -> sys_description_rom_s1_translator:uav_address
wire sys_description_rom_s1_agent_m0_write; // sys_description_rom_s1_agent:m0_write -> sys_description_rom_s1_translator:uav_write
wire sys_description_rom_s1_agent_m0_lock; // sys_description_rom_s1_agent:m0_lock -> sys_description_rom_s1_translator:uav_lock
wire sys_description_rom_s1_agent_m0_read; // sys_description_rom_s1_agent:m0_read -> sys_description_rom_s1_translator:uav_read
wire [63:0] sys_description_rom_s1_agent_m0_readdata; // sys_description_rom_s1_translator:uav_readdata -> sys_description_rom_s1_agent:m0_readdata
wire sys_description_rom_s1_agent_m0_readdatavalid; // sys_description_rom_s1_translator:uav_readdatavalid -> sys_description_rom_s1_agent:m0_readdatavalid
wire sys_description_rom_s1_agent_m0_debugaccess; // sys_description_rom_s1_agent:m0_debugaccess -> sys_description_rom_s1_translator:uav_debugaccess
wire [7:0] sys_description_rom_s1_agent_m0_byteenable; // sys_description_rom_s1_agent:m0_byteenable -> sys_description_rom_s1_translator:uav_byteenable
wire sys_description_rom_s1_agent_rf_source_endofpacket; // sys_description_rom_s1_agent:rf_source_endofpacket -> sys_description_rom_s1_agent_rsp_fifo:in_endofpacket
wire sys_description_rom_s1_agent_rf_source_valid; // sys_description_rom_s1_agent:rf_source_valid -> sys_description_rom_s1_agent_rsp_fifo:in_valid
wire sys_description_rom_s1_agent_rf_source_startofpacket; // sys_description_rom_s1_agent:rf_source_startofpacket -> sys_description_rom_s1_agent_rsp_fifo:in_startofpacket
wire [125:0] sys_description_rom_s1_agent_rf_source_data; // sys_description_rom_s1_agent:rf_source_data -> sys_description_rom_s1_agent_rsp_fifo:in_data
wire sys_description_rom_s1_agent_rf_source_ready; // sys_description_rom_s1_agent_rsp_fifo:in_ready -> sys_description_rom_s1_agent:rf_source_ready
wire sys_description_rom_s1_agent_rsp_fifo_out_endofpacket; // sys_description_rom_s1_agent_rsp_fifo:out_endofpacket -> sys_description_rom_s1_agent:rf_sink_endofpacket
wire sys_description_rom_s1_agent_rsp_fifo_out_valid; // sys_description_rom_s1_agent_rsp_fifo:out_valid -> sys_description_rom_s1_agent:rf_sink_valid
wire sys_description_rom_s1_agent_rsp_fifo_out_startofpacket; // sys_description_rom_s1_agent_rsp_fifo:out_startofpacket -> sys_description_rom_s1_agent:rf_sink_startofpacket
wire [125:0] sys_description_rom_s1_agent_rsp_fifo_out_data; // sys_description_rom_s1_agent_rsp_fifo:out_data -> sys_description_rom_s1_agent:rf_sink_data
wire sys_description_rom_s1_agent_rsp_fifo_out_ready; // sys_description_rom_s1_agent:rf_sink_ready -> sys_description_rom_s1_agent_rsp_fifo:out_ready
wire sys_description_rom_s1_agent_rdata_fifo_src_valid; // sys_description_rom_s1_agent:rdata_fifo_src_valid -> sys_description_rom_s1_agent:rdata_fifo_sink_valid
wire [65:0] sys_description_rom_s1_agent_rdata_fifo_src_data; // sys_description_rom_s1_agent:rdata_fifo_src_data -> sys_description_rom_s1_agent:rdata_fifo_sink_data
wire sys_description_rom_s1_agent_rdata_fifo_src_ready; // sys_description_rom_s1_agent:rdata_fifo_sink_ready -> sys_description_rom_s1_agent:rdata_fifo_src_ready
wire sw_reset_s_agent_m0_waitrequest; // sw_reset_s_translator:uav_waitrequest -> sw_reset_s_agent:m0_waitrequest
wire [3:0] sw_reset_s_agent_m0_burstcount; // sw_reset_s_agent:m0_burstcount -> sw_reset_s_translator:uav_burstcount
wire [63:0] sw_reset_s_agent_m0_writedata; // sw_reset_s_agent:m0_writedata -> sw_reset_s_translator:uav_writedata
wire [13:0] sw_reset_s_agent_m0_address; // sw_reset_s_agent:m0_address -> sw_reset_s_translator:uav_address
wire sw_reset_s_agent_m0_write; // sw_reset_s_agent:m0_write -> sw_reset_s_translator:uav_write
wire sw_reset_s_agent_m0_lock; // sw_reset_s_agent:m0_lock -> sw_reset_s_translator:uav_lock
wire sw_reset_s_agent_m0_read; // sw_reset_s_agent:m0_read -> sw_reset_s_translator:uav_read
wire [63:0] sw_reset_s_agent_m0_readdata; // sw_reset_s_translator:uav_readdata -> sw_reset_s_agent:m0_readdata
wire sw_reset_s_agent_m0_readdatavalid; // sw_reset_s_translator:uav_readdatavalid -> sw_reset_s_agent:m0_readdatavalid
wire sw_reset_s_agent_m0_debugaccess; // sw_reset_s_agent:m0_debugaccess -> sw_reset_s_translator:uav_debugaccess
wire [7:0] sw_reset_s_agent_m0_byteenable; // sw_reset_s_agent:m0_byteenable -> sw_reset_s_translator:uav_byteenable
wire sw_reset_s_agent_rf_source_endofpacket; // sw_reset_s_agent:rf_source_endofpacket -> sw_reset_s_agent_rsp_fifo:in_endofpacket
wire sw_reset_s_agent_rf_source_valid; // sw_reset_s_agent:rf_source_valid -> sw_reset_s_agent_rsp_fifo:in_valid
wire sw_reset_s_agent_rf_source_startofpacket; // sw_reset_s_agent:rf_source_startofpacket -> sw_reset_s_agent_rsp_fifo:in_startofpacket
wire [125:0] sw_reset_s_agent_rf_source_data; // sw_reset_s_agent:rf_source_data -> sw_reset_s_agent_rsp_fifo:in_data
wire sw_reset_s_agent_rf_source_ready; // sw_reset_s_agent_rsp_fifo:in_ready -> sw_reset_s_agent:rf_source_ready
wire sw_reset_s_agent_rsp_fifo_out_endofpacket; // sw_reset_s_agent_rsp_fifo:out_endofpacket -> sw_reset_s_agent:rf_sink_endofpacket
wire sw_reset_s_agent_rsp_fifo_out_valid; // sw_reset_s_agent_rsp_fifo:out_valid -> sw_reset_s_agent:rf_sink_valid
wire sw_reset_s_agent_rsp_fifo_out_startofpacket; // sw_reset_s_agent_rsp_fifo:out_startofpacket -> sw_reset_s_agent:rf_sink_startofpacket
wire [125:0] sw_reset_s_agent_rsp_fifo_out_data; // sw_reset_s_agent_rsp_fifo:out_data -> sw_reset_s_agent:rf_sink_data
wire sw_reset_s_agent_rsp_fifo_out_ready; // sw_reset_s_agent:rf_sink_ready -> sw_reset_s_agent_rsp_fifo:out_ready
wire sw_reset_s_agent_rdata_fifo_src_valid; // sw_reset_s_agent:rdata_fifo_src_valid -> sw_reset_s_agent:rdata_fifo_sink_valid
wire [65:0] sw_reset_s_agent_rdata_fifo_src_data; // sw_reset_s_agent:rdata_fifo_src_data -> sw_reset_s_agent:rdata_fifo_sink_data
wire sw_reset_s_agent_rdata_fifo_src_ready; // sw_reset_s_agent:rdata_fifo_sink_ready -> sw_reset_s_agent:rdata_fifo_src_ready
wire mem_org_mode_s_agent_m0_waitrequest; // mem_org_mode_s_translator:uav_waitrequest -> mem_org_mode_s_agent:m0_waitrequest
wire [2:0] mem_org_mode_s_agent_m0_burstcount; // mem_org_mode_s_agent:m0_burstcount -> mem_org_mode_s_translator:uav_burstcount
wire [31:0] mem_org_mode_s_agent_m0_writedata; // mem_org_mode_s_agent:m0_writedata -> mem_org_mode_s_translator:uav_writedata
wire [13:0] mem_org_mode_s_agent_m0_address; // mem_org_mode_s_agent:m0_address -> mem_org_mode_s_translator:uav_address
wire mem_org_mode_s_agent_m0_write; // mem_org_mode_s_agent:m0_write -> mem_org_mode_s_translator:uav_write
wire mem_org_mode_s_agent_m0_lock; // mem_org_mode_s_agent:m0_lock -> mem_org_mode_s_translator:uav_lock
wire mem_org_mode_s_agent_m0_read; // mem_org_mode_s_agent:m0_read -> mem_org_mode_s_translator:uav_read
wire [31:0] mem_org_mode_s_agent_m0_readdata; // mem_org_mode_s_translator:uav_readdata -> mem_org_mode_s_agent:m0_readdata
wire mem_org_mode_s_agent_m0_readdatavalid; // mem_org_mode_s_translator:uav_readdatavalid -> mem_org_mode_s_agent:m0_readdatavalid
wire mem_org_mode_s_agent_m0_debugaccess; // mem_org_mode_s_agent:m0_debugaccess -> mem_org_mode_s_translator:uav_debugaccess
wire [3:0] mem_org_mode_s_agent_m0_byteenable; // mem_org_mode_s_agent:m0_byteenable -> mem_org_mode_s_translator:uav_byteenable
wire mem_org_mode_s_agent_rf_source_endofpacket; // mem_org_mode_s_agent:rf_source_endofpacket -> mem_org_mode_s_agent_rsp_fifo:in_endofpacket
wire mem_org_mode_s_agent_rf_source_valid; // mem_org_mode_s_agent:rf_source_valid -> mem_org_mode_s_agent_rsp_fifo:in_valid
wire mem_org_mode_s_agent_rf_source_startofpacket; // mem_org_mode_s_agent:rf_source_startofpacket -> mem_org_mode_s_agent_rsp_fifo:in_startofpacket
wire [89:0] mem_org_mode_s_agent_rf_source_data; // mem_org_mode_s_agent:rf_source_data -> mem_org_mode_s_agent_rsp_fifo:in_data
wire mem_org_mode_s_agent_rf_source_ready; // mem_org_mode_s_agent_rsp_fifo:in_ready -> mem_org_mode_s_agent:rf_source_ready
wire mem_org_mode_s_agent_rsp_fifo_out_endofpacket; // mem_org_mode_s_agent_rsp_fifo:out_endofpacket -> mem_org_mode_s_agent:rf_sink_endofpacket
wire mem_org_mode_s_agent_rsp_fifo_out_valid; // mem_org_mode_s_agent_rsp_fifo:out_valid -> mem_org_mode_s_agent:rf_sink_valid
wire mem_org_mode_s_agent_rsp_fifo_out_startofpacket; // mem_org_mode_s_agent_rsp_fifo:out_startofpacket -> mem_org_mode_s_agent:rf_sink_startofpacket
wire [89:0] mem_org_mode_s_agent_rsp_fifo_out_data; // mem_org_mode_s_agent_rsp_fifo:out_data -> mem_org_mode_s_agent:rf_sink_data
wire mem_org_mode_s_agent_rsp_fifo_out_ready; // mem_org_mode_s_agent:rf_sink_ready -> mem_org_mode_s_agent_rsp_fifo:out_ready
wire mem_org_mode_s_agent_rdata_fifo_src_valid; // mem_org_mode_s_agent:rdata_fifo_src_valid -> mem_org_mode_s_agent:rdata_fifo_sink_valid
wire [33:0] mem_org_mode_s_agent_rdata_fifo_src_data; // mem_org_mode_s_agent:rdata_fifo_src_data -> mem_org_mode_s_agent:rdata_fifo_sink_data
wire mem_org_mode_s_agent_rdata_fifo_src_ready; // mem_org_mode_s_agent:rdata_fifo_sink_ready -> mem_org_mode_s_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> mem_org_mode_s_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> mem_org_mode_s_agent:cp_valid
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> mem_org_mode_s_agent:cp_startofpacket
wire [88:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> mem_org_mode_s_agent:cp_data
wire [6:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> mem_org_mode_s_agent:cp_channel
wire cmd_mux_004_src_ready; // mem_org_mode_s_agent:cp_ready -> cmd_mux_004:src_ready
wire version_id_0_s_agent_m0_waitrequest; // version_id_0_s_translator:uav_waitrequest -> version_id_0_s_agent:m0_waitrequest
wire [2:0] version_id_0_s_agent_m0_burstcount; // version_id_0_s_agent:m0_burstcount -> version_id_0_s_translator:uav_burstcount
wire [31:0] version_id_0_s_agent_m0_writedata; // version_id_0_s_agent:m0_writedata -> version_id_0_s_translator:uav_writedata
wire [13:0] version_id_0_s_agent_m0_address; // version_id_0_s_agent:m0_address -> version_id_0_s_translator:uav_address
wire version_id_0_s_agent_m0_write; // version_id_0_s_agent:m0_write -> version_id_0_s_translator:uav_write
wire version_id_0_s_agent_m0_lock; // version_id_0_s_agent:m0_lock -> version_id_0_s_translator:uav_lock
wire version_id_0_s_agent_m0_read; // version_id_0_s_agent:m0_read -> version_id_0_s_translator:uav_read
wire [31:0] version_id_0_s_agent_m0_readdata; // version_id_0_s_translator:uav_readdata -> version_id_0_s_agent:m0_readdata
wire version_id_0_s_agent_m0_readdatavalid; // version_id_0_s_translator:uav_readdatavalid -> version_id_0_s_agent:m0_readdatavalid
wire version_id_0_s_agent_m0_debugaccess; // version_id_0_s_agent:m0_debugaccess -> version_id_0_s_translator:uav_debugaccess
wire [3:0] version_id_0_s_agent_m0_byteenable; // version_id_0_s_agent:m0_byteenable -> version_id_0_s_translator:uav_byteenable
wire version_id_0_s_agent_rf_source_endofpacket; // version_id_0_s_agent:rf_source_endofpacket -> version_id_0_s_agent_rsp_fifo:in_endofpacket
wire version_id_0_s_agent_rf_source_valid; // version_id_0_s_agent:rf_source_valid -> version_id_0_s_agent_rsp_fifo:in_valid
wire version_id_0_s_agent_rf_source_startofpacket; // version_id_0_s_agent:rf_source_startofpacket -> version_id_0_s_agent_rsp_fifo:in_startofpacket
wire [89:0] version_id_0_s_agent_rf_source_data; // version_id_0_s_agent:rf_source_data -> version_id_0_s_agent_rsp_fifo:in_data
wire version_id_0_s_agent_rf_source_ready; // version_id_0_s_agent_rsp_fifo:in_ready -> version_id_0_s_agent:rf_source_ready
wire version_id_0_s_agent_rsp_fifo_out_endofpacket; // version_id_0_s_agent_rsp_fifo:out_endofpacket -> version_id_0_s_agent:rf_sink_endofpacket
wire version_id_0_s_agent_rsp_fifo_out_valid; // version_id_0_s_agent_rsp_fifo:out_valid -> version_id_0_s_agent:rf_sink_valid
wire version_id_0_s_agent_rsp_fifo_out_startofpacket; // version_id_0_s_agent_rsp_fifo:out_startofpacket -> version_id_0_s_agent:rf_sink_startofpacket
wire [89:0] version_id_0_s_agent_rsp_fifo_out_data; // version_id_0_s_agent_rsp_fifo:out_data -> version_id_0_s_agent:rf_sink_data
wire version_id_0_s_agent_rsp_fifo_out_ready; // version_id_0_s_agent:rf_sink_ready -> version_id_0_s_agent_rsp_fifo:out_ready
wire version_id_0_s_agent_rdata_fifo_src_valid; // version_id_0_s_agent:rdata_fifo_src_valid -> version_id_0_s_agent:rdata_fifo_sink_valid
wire [33:0] version_id_0_s_agent_rdata_fifo_src_data; // version_id_0_s_agent:rdata_fifo_src_data -> version_id_0_s_agent:rdata_fifo_sink_data
wire version_id_0_s_agent_rdata_fifo_src_ready; // version_id_0_s_agent:rdata_fifo_sink_ready -> version_id_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> version_id_0_s_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> version_id_0_s_agent:cp_valid
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> version_id_0_s_agent:cp_startofpacket
wire [88:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> version_id_0_s_agent:cp_data
wire [6:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> version_id_0_s_agent:cp_channel
wire cmd_mux_005_src_ready; // version_id_0_s_agent:cp_ready -> cmd_mux_005:src_ready
wire irq_ena_0_s_agent_m0_waitrequest; // irq_ena_0_s_translator:uav_waitrequest -> irq_ena_0_s_agent:m0_waitrequest
wire [2:0] irq_ena_0_s_agent_m0_burstcount; // irq_ena_0_s_agent:m0_burstcount -> irq_ena_0_s_translator:uav_burstcount
wire [31:0] irq_ena_0_s_agent_m0_writedata; // irq_ena_0_s_agent:m0_writedata -> irq_ena_0_s_translator:uav_writedata
wire [13:0] irq_ena_0_s_agent_m0_address; // irq_ena_0_s_agent:m0_address -> irq_ena_0_s_translator:uav_address
wire irq_ena_0_s_agent_m0_write; // irq_ena_0_s_agent:m0_write -> irq_ena_0_s_translator:uav_write
wire irq_ena_0_s_agent_m0_lock; // irq_ena_0_s_agent:m0_lock -> irq_ena_0_s_translator:uav_lock
wire irq_ena_0_s_agent_m0_read; // irq_ena_0_s_agent:m0_read -> irq_ena_0_s_translator:uav_read
wire [31:0] irq_ena_0_s_agent_m0_readdata; // irq_ena_0_s_translator:uav_readdata -> irq_ena_0_s_agent:m0_readdata
wire irq_ena_0_s_agent_m0_readdatavalid; // irq_ena_0_s_translator:uav_readdatavalid -> irq_ena_0_s_agent:m0_readdatavalid
wire irq_ena_0_s_agent_m0_debugaccess; // irq_ena_0_s_agent:m0_debugaccess -> irq_ena_0_s_translator:uav_debugaccess
wire [3:0] irq_ena_0_s_agent_m0_byteenable; // irq_ena_0_s_agent:m0_byteenable -> irq_ena_0_s_translator:uav_byteenable
wire irq_ena_0_s_agent_rf_source_endofpacket; // irq_ena_0_s_agent:rf_source_endofpacket -> irq_ena_0_s_agent_rsp_fifo:in_endofpacket
wire irq_ena_0_s_agent_rf_source_valid; // irq_ena_0_s_agent:rf_source_valid -> irq_ena_0_s_agent_rsp_fifo:in_valid
wire irq_ena_0_s_agent_rf_source_startofpacket; // irq_ena_0_s_agent:rf_source_startofpacket -> irq_ena_0_s_agent_rsp_fifo:in_startofpacket
wire [89:0] irq_ena_0_s_agent_rf_source_data; // irq_ena_0_s_agent:rf_source_data -> irq_ena_0_s_agent_rsp_fifo:in_data
wire irq_ena_0_s_agent_rf_source_ready; // irq_ena_0_s_agent_rsp_fifo:in_ready -> irq_ena_0_s_agent:rf_source_ready
wire irq_ena_0_s_agent_rsp_fifo_out_endofpacket; // irq_ena_0_s_agent_rsp_fifo:out_endofpacket -> irq_ena_0_s_agent:rf_sink_endofpacket
wire irq_ena_0_s_agent_rsp_fifo_out_valid; // irq_ena_0_s_agent_rsp_fifo:out_valid -> irq_ena_0_s_agent:rf_sink_valid
wire irq_ena_0_s_agent_rsp_fifo_out_startofpacket; // irq_ena_0_s_agent_rsp_fifo:out_startofpacket -> irq_ena_0_s_agent:rf_sink_startofpacket
wire [89:0] irq_ena_0_s_agent_rsp_fifo_out_data; // irq_ena_0_s_agent_rsp_fifo:out_data -> irq_ena_0_s_agent:rf_sink_data
wire irq_ena_0_s_agent_rsp_fifo_out_ready; // irq_ena_0_s_agent:rf_sink_ready -> irq_ena_0_s_agent_rsp_fifo:out_ready
wire irq_ena_0_s_agent_rdata_fifo_src_valid; // irq_ena_0_s_agent:rdata_fifo_src_valid -> irq_ena_0_s_agent:rdata_fifo_sink_valid
wire [33:0] irq_ena_0_s_agent_rdata_fifo_src_data; // irq_ena_0_s_agent:rdata_fifo_src_data -> irq_ena_0_s_agent:rdata_fifo_sink_data
wire irq_ena_0_s_agent_rdata_fifo_src_ready; // irq_ena_0_s_agent:rdata_fifo_sink_ready -> irq_ena_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> irq_ena_0_s_agent:cp_endofpacket
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> irq_ena_0_s_agent:cp_valid
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> irq_ena_0_s_agent:cp_startofpacket
wire [88:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> irq_ena_0_s_agent:cp_data
wire [6:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> irq_ena_0_s_agent:cp_channel
wire cmd_mux_006_src_ready; // irq_ena_0_s_agent:cp_ready -> cmd_mux_006:src_ready
wire kernel_cntrl_m0_agent_cp_endofpacket; // kernel_cntrl_m0_agent:cp_endofpacket -> router:sink_endofpacket
wire kernel_cntrl_m0_agent_cp_valid; // kernel_cntrl_m0_agent:cp_valid -> router:sink_valid
wire kernel_cntrl_m0_agent_cp_startofpacket; // kernel_cntrl_m0_agent:cp_startofpacket -> router:sink_startofpacket
wire [88:0] kernel_cntrl_m0_agent_cp_data; // kernel_cntrl_m0_agent:cp_data -> router:sink_data
wire kernel_cntrl_m0_agent_cp_ready; // router:sink_ready -> kernel_cntrl_m0_agent:cp_ready
wire address_span_extender_0_windowed_slave_agent_rp_endofpacket; // address_span_extender_0_windowed_slave_agent:rp_endofpacket -> router_001:sink_endofpacket
wire address_span_extender_0_windowed_slave_agent_rp_valid; // address_span_extender_0_windowed_slave_agent:rp_valid -> router_001:sink_valid
wire address_span_extender_0_windowed_slave_agent_rp_startofpacket; // address_span_extender_0_windowed_slave_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [88:0] address_span_extender_0_windowed_slave_agent_rp_data; // address_span_extender_0_windowed_slave_agent:rp_data -> router_001:sink_data
wire address_span_extender_0_windowed_slave_agent_rp_ready; // router_001:sink_ready -> address_span_extender_0_windowed_slave_agent:rp_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire [88:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire [6:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire address_span_extender_0_cntl_agent_rp_endofpacket; // address_span_extender_0_cntl_agent:rp_endofpacket -> router_002:sink_endofpacket
wire address_span_extender_0_cntl_agent_rp_valid; // address_span_extender_0_cntl_agent:rp_valid -> router_002:sink_valid
wire address_span_extender_0_cntl_agent_rp_startofpacket; // address_span_extender_0_cntl_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [124:0] address_span_extender_0_cntl_agent_rp_data; // address_span_extender_0_cntl_agent:rp_data -> router_002:sink_data
wire address_span_extender_0_cntl_agent_rp_ready; // router_002:sink_ready -> address_span_extender_0_cntl_agent:rp_ready
wire sys_description_rom_s1_agent_rp_endofpacket; // sys_description_rom_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
wire sys_description_rom_s1_agent_rp_valid; // sys_description_rom_s1_agent:rp_valid -> router_003:sink_valid
wire sys_description_rom_s1_agent_rp_startofpacket; // sys_description_rom_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [124:0] sys_description_rom_s1_agent_rp_data; // sys_description_rom_s1_agent:rp_data -> router_003:sink_data
wire sys_description_rom_s1_agent_rp_ready; // router_003:sink_ready -> sys_description_rom_s1_agent:rp_ready
wire sw_reset_s_agent_rp_endofpacket; // sw_reset_s_agent:rp_endofpacket -> router_004:sink_endofpacket
wire sw_reset_s_agent_rp_valid; // sw_reset_s_agent:rp_valid -> router_004:sink_valid
wire sw_reset_s_agent_rp_startofpacket; // sw_reset_s_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [124:0] sw_reset_s_agent_rp_data; // sw_reset_s_agent:rp_data -> router_004:sink_data
wire sw_reset_s_agent_rp_ready; // router_004:sink_ready -> sw_reset_s_agent:rp_ready
wire mem_org_mode_s_agent_rp_endofpacket; // mem_org_mode_s_agent:rp_endofpacket -> router_005:sink_endofpacket
wire mem_org_mode_s_agent_rp_valid; // mem_org_mode_s_agent:rp_valid -> router_005:sink_valid
wire mem_org_mode_s_agent_rp_startofpacket; // mem_org_mode_s_agent:rp_startofpacket -> router_005:sink_startofpacket
wire [88:0] mem_org_mode_s_agent_rp_data; // mem_org_mode_s_agent:rp_data -> router_005:sink_data
wire mem_org_mode_s_agent_rp_ready; // router_005:sink_ready -> mem_org_mode_s_agent:rp_ready
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_004:sink_valid
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire [88:0] router_005_src_data; // router_005:src_data -> rsp_demux_004:sink_data
wire [6:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_004:sink_channel
wire router_005_src_ready; // rsp_demux_004:sink_ready -> router_005:src_ready
wire version_id_0_s_agent_rp_endofpacket; // version_id_0_s_agent:rp_endofpacket -> router_006:sink_endofpacket
wire version_id_0_s_agent_rp_valid; // version_id_0_s_agent:rp_valid -> router_006:sink_valid
wire version_id_0_s_agent_rp_startofpacket; // version_id_0_s_agent:rp_startofpacket -> router_006:sink_startofpacket
wire [88:0] version_id_0_s_agent_rp_data; // version_id_0_s_agent:rp_data -> router_006:sink_data
wire version_id_0_s_agent_rp_ready; // router_006:sink_ready -> version_id_0_s_agent:rp_ready
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_005:sink_valid
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire [88:0] router_006_src_data; // router_006:src_data -> rsp_demux_005:sink_data
wire [6:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_005:sink_channel
wire router_006_src_ready; // rsp_demux_005:sink_ready -> router_006:src_ready
wire irq_ena_0_s_agent_rp_endofpacket; // irq_ena_0_s_agent:rp_endofpacket -> router_007:sink_endofpacket
wire irq_ena_0_s_agent_rp_valid; // irq_ena_0_s_agent:rp_valid -> router_007:sink_valid
wire irq_ena_0_s_agent_rp_startofpacket; // irq_ena_0_s_agent:rp_startofpacket -> router_007:sink_startofpacket
wire [88:0] irq_ena_0_s_agent_rp_data; // irq_ena_0_s_agent:rp_data -> router_007:sink_data
wire irq_ena_0_s_agent_rp_ready; // router_007:sink_ready -> irq_ena_0_s_agent:rp_ready
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_006:sink_valid
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire [88:0] router_007_src_data; // router_007:src_data -> rsp_demux_006:sink_data
wire [6:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_006:sink_channel
wire router_007_src_ready; // rsp_demux_006:sink_ready -> router_007:src_ready
wire router_src_endofpacket; // router:src_endofpacket -> kernel_cntrl_m0_limiter:cmd_sink_endofpacket
wire router_src_valid; // router:src_valid -> kernel_cntrl_m0_limiter:cmd_sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> kernel_cntrl_m0_limiter:cmd_sink_startofpacket
wire [88:0] router_src_data; // router:src_data -> kernel_cntrl_m0_limiter:cmd_sink_data
wire [6:0] router_src_channel; // router:src_channel -> kernel_cntrl_m0_limiter:cmd_sink_channel
wire router_src_ready; // kernel_cntrl_m0_limiter:cmd_sink_ready -> router:src_ready
wire kernel_cntrl_m0_limiter_cmd_src_endofpacket; // kernel_cntrl_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire kernel_cntrl_m0_limiter_cmd_src_startofpacket; // kernel_cntrl_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire [88:0] kernel_cntrl_m0_limiter_cmd_src_data; // kernel_cntrl_m0_limiter:cmd_src_data -> cmd_demux:sink_data
wire [6:0] kernel_cntrl_m0_limiter_cmd_src_channel; // kernel_cntrl_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire kernel_cntrl_m0_limiter_cmd_src_ready; // cmd_demux:sink_ready -> kernel_cntrl_m0_limiter:cmd_src_ready
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> kernel_cntrl_m0_limiter:rsp_sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> kernel_cntrl_m0_limiter:rsp_sink_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> kernel_cntrl_m0_limiter:rsp_sink_startofpacket
wire [88:0] rsp_mux_src_data; // rsp_mux:src_data -> kernel_cntrl_m0_limiter:rsp_sink_data
wire [6:0] rsp_mux_src_channel; // rsp_mux:src_channel -> kernel_cntrl_m0_limiter:rsp_sink_channel
wire rsp_mux_src_ready; // kernel_cntrl_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire kernel_cntrl_m0_limiter_rsp_src_endofpacket; // kernel_cntrl_m0_limiter:rsp_src_endofpacket -> kernel_cntrl_m0_agent:rp_endofpacket
wire kernel_cntrl_m0_limiter_rsp_src_valid; // kernel_cntrl_m0_limiter:rsp_src_valid -> kernel_cntrl_m0_agent:rp_valid
wire kernel_cntrl_m0_limiter_rsp_src_startofpacket; // kernel_cntrl_m0_limiter:rsp_src_startofpacket -> kernel_cntrl_m0_agent:rp_startofpacket
wire [88:0] kernel_cntrl_m0_limiter_rsp_src_data; // kernel_cntrl_m0_limiter:rsp_src_data -> kernel_cntrl_m0_agent:rp_data
wire [6:0] kernel_cntrl_m0_limiter_rsp_src_channel; // kernel_cntrl_m0_limiter:rsp_src_channel -> kernel_cntrl_m0_agent:rp_channel
wire kernel_cntrl_m0_limiter_rsp_src_ready; // kernel_cntrl_m0_agent:rp_ready -> kernel_cntrl_m0_limiter:rsp_src_ready
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [88:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire [6:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire [88:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire [6:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire [88:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire [6:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire [88:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire [6:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire [88:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
wire [6:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire [88:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire [6:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire [88:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire [6:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire [88:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire [6:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire [88:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire [6:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
wire [88:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
wire [6:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> address_span_extender_0_cntl_cmd_width_adapter:in_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> address_span_extender_0_cntl_cmd_width_adapter:in_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> address_span_extender_0_cntl_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> address_span_extender_0_cntl_cmd_width_adapter:in_data
wire [6:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> address_span_extender_0_cntl_cmd_width_adapter:in_channel
wire cmd_mux_001_src_ready; // address_span_extender_0_cntl_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
wire address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket; // address_span_extender_0_cntl_cmd_width_adapter:out_endofpacket -> address_span_extender_0_cntl_agent:cp_endofpacket
wire address_span_extender_0_cntl_cmd_width_adapter_src_valid; // address_span_extender_0_cntl_cmd_width_adapter:out_valid -> address_span_extender_0_cntl_agent:cp_valid
wire address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket; // address_span_extender_0_cntl_cmd_width_adapter:out_startofpacket -> address_span_extender_0_cntl_agent:cp_startofpacket
wire [124:0] address_span_extender_0_cntl_cmd_width_adapter_src_data; // address_span_extender_0_cntl_cmd_width_adapter:out_data -> address_span_extender_0_cntl_agent:cp_data
wire address_span_extender_0_cntl_cmd_width_adapter_src_ready; // address_span_extender_0_cntl_agent:cp_ready -> address_span_extender_0_cntl_cmd_width_adapter:out_ready
wire [6:0] address_span_extender_0_cntl_cmd_width_adapter_src_channel; // address_span_extender_0_cntl_cmd_width_adapter:out_channel -> address_span_extender_0_cntl_agent:cp_channel
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> sys_description_rom_s1_cmd_width_adapter:in_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> sys_description_rom_s1_cmd_width_adapter:in_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> sys_description_rom_s1_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> sys_description_rom_s1_cmd_width_adapter:in_data
wire [6:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> sys_description_rom_s1_cmd_width_adapter:in_channel
wire cmd_mux_002_src_ready; // sys_description_rom_s1_cmd_width_adapter:in_ready -> cmd_mux_002:src_ready
wire sys_description_rom_s1_cmd_width_adapter_src_endofpacket; // sys_description_rom_s1_cmd_width_adapter:out_endofpacket -> sys_description_rom_s1_agent:cp_endofpacket
wire sys_description_rom_s1_cmd_width_adapter_src_valid; // sys_description_rom_s1_cmd_width_adapter:out_valid -> sys_description_rom_s1_agent:cp_valid
wire sys_description_rom_s1_cmd_width_adapter_src_startofpacket; // sys_description_rom_s1_cmd_width_adapter:out_startofpacket -> sys_description_rom_s1_agent:cp_startofpacket
wire [124:0] sys_description_rom_s1_cmd_width_adapter_src_data; // sys_description_rom_s1_cmd_width_adapter:out_data -> sys_description_rom_s1_agent:cp_data
wire sys_description_rom_s1_cmd_width_adapter_src_ready; // sys_description_rom_s1_agent:cp_ready -> sys_description_rom_s1_cmd_width_adapter:out_ready
wire [6:0] sys_description_rom_s1_cmd_width_adapter_src_channel; // sys_description_rom_s1_cmd_width_adapter:out_channel -> sys_description_rom_s1_agent:cp_channel
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sw_reset_s_cmd_width_adapter:in_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sw_reset_s_cmd_width_adapter:in_valid
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sw_reset_s_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sw_reset_s_cmd_width_adapter:in_data
wire [6:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sw_reset_s_cmd_width_adapter:in_channel
wire cmd_mux_003_src_ready; // sw_reset_s_cmd_width_adapter:in_ready -> cmd_mux_003:src_ready
wire sw_reset_s_cmd_width_adapter_src_endofpacket; // sw_reset_s_cmd_width_adapter:out_endofpacket -> sw_reset_s_agent:cp_endofpacket
wire sw_reset_s_cmd_width_adapter_src_valid; // sw_reset_s_cmd_width_adapter:out_valid -> sw_reset_s_agent:cp_valid
wire sw_reset_s_cmd_width_adapter_src_startofpacket; // sw_reset_s_cmd_width_adapter:out_startofpacket -> sw_reset_s_agent:cp_startofpacket
wire [124:0] sw_reset_s_cmd_width_adapter_src_data; // sw_reset_s_cmd_width_adapter:out_data -> sw_reset_s_agent:cp_data
wire sw_reset_s_cmd_width_adapter_src_ready; // sw_reset_s_agent:cp_ready -> sw_reset_s_cmd_width_adapter:out_ready
wire [6:0] sw_reset_s_cmd_width_adapter_src_channel; // sw_reset_s_cmd_width_adapter:out_channel -> sw_reset_s_agent:cp_channel
wire router_002_src_endofpacket; // router_002:src_endofpacket -> address_span_extender_0_cntl_rsp_width_adapter:in_endofpacket
wire router_002_src_valid; // router_002:src_valid -> address_span_extender_0_cntl_rsp_width_adapter:in_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> address_span_extender_0_cntl_rsp_width_adapter:in_startofpacket
wire [124:0] router_002_src_data; // router_002:src_data -> address_span_extender_0_cntl_rsp_width_adapter:in_data
wire [6:0] router_002_src_channel; // router_002:src_channel -> address_span_extender_0_cntl_rsp_width_adapter:in_channel
wire router_002_src_ready; // address_span_extender_0_cntl_rsp_width_adapter:in_ready -> router_002:src_ready
wire address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket; // address_span_extender_0_cntl_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
wire address_span_extender_0_cntl_rsp_width_adapter_src_valid; // address_span_extender_0_cntl_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
wire address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket; // address_span_extender_0_cntl_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
wire [88:0] address_span_extender_0_cntl_rsp_width_adapter_src_data; // address_span_extender_0_cntl_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
wire address_span_extender_0_cntl_rsp_width_adapter_src_ready; // rsp_demux_001:sink_ready -> address_span_extender_0_cntl_rsp_width_adapter:out_ready
wire [6:0] address_span_extender_0_cntl_rsp_width_adapter_src_channel; // address_span_extender_0_cntl_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
wire router_003_src_endofpacket; // router_003:src_endofpacket -> sys_description_rom_s1_rsp_width_adapter:in_endofpacket
wire router_003_src_valid; // router_003:src_valid -> sys_description_rom_s1_rsp_width_adapter:in_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> sys_description_rom_s1_rsp_width_adapter:in_startofpacket
wire [124:0] router_003_src_data; // router_003:src_data -> sys_description_rom_s1_rsp_width_adapter:in_data
wire [6:0] router_003_src_channel; // router_003:src_channel -> sys_description_rom_s1_rsp_width_adapter:in_channel
wire router_003_src_ready; // sys_description_rom_s1_rsp_width_adapter:in_ready -> router_003:src_ready
wire sys_description_rom_s1_rsp_width_adapter_src_endofpacket; // sys_description_rom_s1_rsp_width_adapter:out_endofpacket -> rsp_demux_002:sink_endofpacket
wire sys_description_rom_s1_rsp_width_adapter_src_valid; // sys_description_rom_s1_rsp_width_adapter:out_valid -> rsp_demux_002:sink_valid
wire sys_description_rom_s1_rsp_width_adapter_src_startofpacket; // sys_description_rom_s1_rsp_width_adapter:out_startofpacket -> rsp_demux_002:sink_startofpacket
wire [88:0] sys_description_rom_s1_rsp_width_adapter_src_data; // sys_description_rom_s1_rsp_width_adapter:out_data -> rsp_demux_002:sink_data
wire sys_description_rom_s1_rsp_width_adapter_src_ready; // rsp_demux_002:sink_ready -> sys_description_rom_s1_rsp_width_adapter:out_ready
wire [6:0] sys_description_rom_s1_rsp_width_adapter_src_channel; // sys_description_rom_s1_rsp_width_adapter:out_channel -> rsp_demux_002:sink_channel
wire router_004_src_endofpacket; // router_004:src_endofpacket -> sw_reset_s_rsp_width_adapter:in_endofpacket
wire router_004_src_valid; // router_004:src_valid -> sw_reset_s_rsp_width_adapter:in_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> sw_reset_s_rsp_width_adapter:in_startofpacket
wire [124:0] router_004_src_data; // router_004:src_data -> sw_reset_s_rsp_width_adapter:in_data
wire [6:0] router_004_src_channel; // router_004:src_channel -> sw_reset_s_rsp_width_adapter:in_channel
wire router_004_src_ready; // sw_reset_s_rsp_width_adapter:in_ready -> router_004:src_ready
wire sw_reset_s_rsp_width_adapter_src_endofpacket; // sw_reset_s_rsp_width_adapter:out_endofpacket -> rsp_demux_003:sink_endofpacket
wire sw_reset_s_rsp_width_adapter_src_valid; // sw_reset_s_rsp_width_adapter:out_valid -> rsp_demux_003:sink_valid
wire sw_reset_s_rsp_width_adapter_src_startofpacket; // sw_reset_s_rsp_width_adapter:out_startofpacket -> rsp_demux_003:sink_startofpacket
wire [88:0] sw_reset_s_rsp_width_adapter_src_data; // sw_reset_s_rsp_width_adapter:out_data -> rsp_demux_003:sink_data
wire sw_reset_s_rsp_width_adapter_src_ready; // rsp_demux_003:sink_ready -> sw_reset_s_rsp_width_adapter:out_ready
wire [6:0] sw_reset_s_rsp_width_adapter_src_channel; // sw_reset_s_rsp_width_adapter:out_channel -> rsp_demux_003:sink_channel
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> crosser:in_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
wire [88:0] cmd_demux_src0_data; // cmd_demux:src0_data -> crosser:in_data
wire [6:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> crosser:in_channel
wire cmd_demux_src0_ready; // crosser:in_ready -> cmd_demux:src0_ready
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux:sink0_valid
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
wire [88:0] crosser_out_data; // crosser:out_data -> cmd_mux:sink0_data
wire [6:0] crosser_out_channel; // crosser:out_channel -> cmd_mux:sink0_channel
wire crosser_out_ready; // cmd_mux:sink0_ready -> crosser:out_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> crosser_001:in_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> crosser_001:in_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> crosser_001:in_startofpacket
wire [88:0] cmd_demux_src1_data; // cmd_demux:src1_data -> crosser_001:in_data
wire [6:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> crosser_001:in_channel
wire cmd_demux_src1_ready; // crosser_001:in_ready -> cmd_demux:src1_ready
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_001:sink0_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_001:sink0_valid
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [88:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_001:sink0_data
wire [6:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_001:sink0_channel
wire crosser_001_out_ready; // cmd_mux_001:sink0_ready -> crosser_001:out_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> crosser_002:in_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> crosser_002:in_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> crosser_002:in_startofpacket
wire [88:0] rsp_demux_src0_data; // rsp_demux:src0_data -> crosser_002:in_data
wire [6:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> crosser_002:in_channel
wire rsp_demux_src0_ready; // crosser_002:in_ready -> rsp_demux:src0_ready
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> rsp_mux:sink0_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> rsp_mux:sink0_valid
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> rsp_mux:sink0_startofpacket
wire [88:0] crosser_002_out_data; // crosser_002:out_data -> rsp_mux:sink0_data
wire [6:0] crosser_002_out_channel; // crosser_002:out_channel -> rsp_mux:sink0_channel
wire crosser_002_out_ready; // rsp_mux:sink0_ready -> crosser_002:out_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> crosser_003:in_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> crosser_003:in_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> crosser_003:in_startofpacket
wire [88:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> crosser_003:in_data
wire [6:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> crosser_003:in_channel
wire rsp_demux_001_src0_ready; // crosser_003:in_ready -> rsp_demux_001:src0_ready
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_mux:sink1_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_mux:sink1_valid
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_mux:sink1_startofpacket
wire [88:0] crosser_003_out_data; // crosser_003:out_data -> rsp_mux:sink1_data
wire [6:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_mux:sink1_channel
wire crosser_003_out_ready; // rsp_mux:sink1_ready -> crosser_003:out_ready
wire [6:0] kernel_cntrl_m0_limiter_cmd_valid_data; // kernel_cntrl_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) kernel_cntrl_m0_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cntrl_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (kernel_cntrl_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (kernel_cntrl_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (kernel_cntrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (kernel_cntrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (kernel_cntrl_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (kernel_cntrl_m0_address), // avalon_anti_master_0.address
.av_waitrequest (kernel_cntrl_m0_waitrequest), // .waitrequest
.av_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.av_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.av_read (kernel_cntrl_m0_read), // .read
.av_readdata (kernel_cntrl_m0_readdata), // .readdata
.av_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.av_write (kernel_cntrl_m0_write), // .write
.av_writedata (kernel_cntrl_m0_writedata), // .writedata
.av_debugaccess (kernel_cntrl_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (10),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_0_windowed_slave_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_windowed_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (address_span_extender_0_windowed_slave_agent_m0_burstcount), // .burstcount
.uav_read (address_span_extender_0_windowed_slave_agent_m0_read), // .read
.uav_write (address_span_extender_0_windowed_slave_agent_m0_write), // .write
.uav_waitrequest (address_span_extender_0_windowed_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_windowed_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_windowed_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_windowed_slave_agent_m0_readdata), // .readdata
.uav_writedata (address_span_extender_0_windowed_slave_agent_m0_writedata), // .writedata
.uav_lock (address_span_extender_0_windowed_slave_agent_m0_lock), // .lock
.uav_debugaccess (address_span_extender_0_windowed_slave_agent_m0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_windowed_slave_address), // avalon_anti_slave_0.address
.av_write (address_span_extender_0_windowed_slave_write), // .write
.av_read (address_span_extender_0_windowed_slave_read), // .read
.av_readdata (address_span_extender_0_windowed_slave_readdata), // .readdata
.av_writedata (address_span_extender_0_windowed_slave_writedata), // .writedata
.av_burstcount (address_span_extender_0_windowed_slave_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_windowed_slave_byteenable), // .byteenable
.av_readdatavalid (address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.av_waitrequest (address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_0_cntl_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_cntl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (address_span_extender_0_cntl_agent_m0_burstcount), // .burstcount
.uav_read (address_span_extender_0_cntl_agent_m0_read), // .read
.uav_write (address_span_extender_0_cntl_agent_m0_write), // .write
.uav_waitrequest (address_span_extender_0_cntl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_cntl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_cntl_agent_m0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_cntl_agent_m0_readdata), // .readdata
.uav_writedata (address_span_extender_0_cntl_agent_m0_writedata), // .writedata
.uav_lock (address_span_extender_0_cntl_agent_m0_lock), // .lock
.uav_debugaccess (address_span_extender_0_cntl_agent_m0_debugaccess), // .debugaccess
.av_write (address_span_extender_0_cntl_write), // avalon_anti_slave_0.write
.av_read (address_span_extender_0_cntl_read), // .read
.av_readdata (address_span_extender_0_cntl_readdata), // .readdata
.av_writedata (address_span_extender_0_cntl_writedata), // .writedata
.av_byteenable (address_span_extender_0_cntl_byteenable), // .byteenable
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (2),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sys_description_rom_s1_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sys_description_rom_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sys_description_rom_s1_agent_m0_burstcount), // .burstcount
.uav_read (sys_description_rom_s1_agent_m0_read), // .read
.uav_write (sys_description_rom_s1_agent_m0_write), // .write
.uav_waitrequest (sys_description_rom_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sys_description_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sys_description_rom_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sys_description_rom_s1_agent_m0_readdata), // .readdata
.uav_writedata (sys_description_rom_s1_agent_m0_writedata), // .writedata
.uav_lock (sys_description_rom_s1_agent_m0_lock), // .lock
.uav_debugaccess (sys_description_rom_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sys_description_rom_s1_address), // avalon_anti_slave_0.address
.av_write (sys_description_rom_s1_write), // .write
.av_readdata (sys_description_rom_s1_readdata), // .readdata
.av_writedata (sys_description_rom_s1_writedata), // .writedata
.av_byteenable (sys_description_rom_s1_byteenable), // .byteenable
.av_chipselect (sys_description_rom_s1_chipselect), // .chipselect
.av_clken (sys_description_rom_s1_clken), // .clken
.av_debugaccess (sys_description_rom_s1_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sw_reset_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sw_reset_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sw_reset_s_agent_m0_burstcount), // .burstcount
.uav_read (sw_reset_s_agent_m0_read), // .read
.uav_write (sw_reset_s_agent_m0_write), // .write
.uav_waitrequest (sw_reset_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sw_reset_s_agent_m0_byteenable), // .byteenable
.uav_readdata (sw_reset_s_agent_m0_readdata), // .readdata
.uav_writedata (sw_reset_s_agent_m0_writedata), // .writedata
.uav_lock (sw_reset_s_agent_m0_lock), // .lock
.uav_debugaccess (sw_reset_s_agent_m0_debugaccess), // .debugaccess
.av_write (sw_reset_s_write), // avalon_anti_slave_0.write
.av_read (sw_reset_s_read), // .read
.av_readdata (sw_reset_s_readdata), // .readdata
.av_writedata (sw_reset_s_writedata), // .writedata
.av_byteenable (sw_reset_s_byteenable), // .byteenable
.av_waitrequest (sw_reset_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) mem_org_mode_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (mem_org_mode_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (mem_org_mode_s_agent_m0_burstcount), // .burstcount
.uav_read (mem_org_mode_s_agent_m0_read), // .read
.uav_write (mem_org_mode_s_agent_m0_write), // .write
.uav_waitrequest (mem_org_mode_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (mem_org_mode_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (mem_org_mode_s_agent_m0_byteenable), // .byteenable
.uav_readdata (mem_org_mode_s_agent_m0_readdata), // .readdata
.uav_writedata (mem_org_mode_s_agent_m0_writedata), // .writedata
.uav_lock (mem_org_mode_s_agent_m0_lock), // .lock
.uav_debugaccess (mem_org_mode_s_agent_m0_debugaccess), // .debugaccess
.av_write (mem_org_mode_s_write), // avalon_anti_slave_0.write
.av_read (mem_org_mode_s_read), // .read
.av_readdata (mem_org_mode_s_readdata), // .readdata
.av_writedata (mem_org_mode_s_writedata), // .writedata
.av_waitrequest (mem_org_mode_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) version_id_0_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (version_id_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.uav_read (version_id_0_s_agent_m0_read), // .read
.uav_write (version_id_0_s_agent_m0_write), // .write
.uav_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.uav_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.uav_lock (version_id_0_s_agent_m0_lock), // .lock
.uav_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.av_read (version_id_0_s_read), // avalon_anti_slave_0.read
.av_readdata (version_id_0_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) irq_ena_0_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (irq_ena_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (irq_ena_0_s_agent_m0_burstcount), // .burstcount
.uav_read (irq_ena_0_s_agent_m0_read), // .read
.uav_write (irq_ena_0_s_agent_m0_write), // .write
.uav_waitrequest (irq_ena_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (irq_ena_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (irq_ena_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (irq_ena_0_s_agent_m0_readdata), // .readdata
.uav_writedata (irq_ena_0_s_agent_m0_writedata), // .writedata
.uav_lock (irq_ena_0_s_agent_m0_lock), // .lock
.uav_debugaccess (irq_ena_0_s_agent_m0_debugaccess), // .debugaccess
.av_write (irq_ena_0_s_write), // avalon_anti_slave_0.write
.av_read (irq_ena_0_s_read), // .read
.av_readdata (irq_ena_0_s_readdata), // .readdata
.av_writedata (irq_ena_0_s_writedata), // .writedata
.av_byteenable (irq_ena_0_s_byteenable), // .byteenable
.av_waitrequest (irq_ena_0_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_BEGIN_BURST (68),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_BURST_TYPE_H (65),
.PKT_BURST_TYPE_L (64),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_TRANS_EXCLUSIVE (55),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_THREAD_ID_H (76),
.PKT_THREAD_ID_L (76),
.PKT_CACHE_H (83),
.PKT_CACHE_L (80),
.PKT_DATA_SIDEBAND_H (67),
.PKT_DATA_SIDEBAND_L (67),
.PKT_QOS_H (69),
.PKT_QOS_L (69),
.PKT_ADDR_SIDEBAND_H (66),
.PKT_ADDR_SIDEBAND_L (66),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_DATA_W (89),
.ST_CHANNEL_W (7),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) kernel_cntrl_m0_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (kernel_cntrl_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (kernel_cntrl_m0_translator_avalon_universal_master_0_write), // .write
.av_read (kernel_cntrl_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (kernel_cntrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (kernel_cntrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (kernel_cntrl_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (kernel_cntrl_m0_agent_cp_valid), // cp.valid
.cp_data (kernel_cntrl_m0_agent_cp_data), // .data
.cp_startofpacket (kernel_cntrl_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cntrl_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (kernel_cntrl_m0_agent_cp_ready), // .ready
.rp_valid (kernel_cntrl_m0_limiter_rsp_src_valid), // rp.valid
.rp_data (kernel_cntrl_m0_limiter_rsp_src_data), // .data
.rp_channel (kernel_cntrl_m0_limiter_rsp_src_channel), // .channel
.rp_startofpacket (kernel_cntrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (kernel_cntrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (kernel_cntrl_m0_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_windowed_slave_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (address_span_extender_0_windowed_slave_agent_m0_address), // m0.address
.m0_burstcount (address_span_extender_0_windowed_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (address_span_extender_0_windowed_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (address_span_extender_0_windowed_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (address_span_extender_0_windowed_slave_agent_m0_lock), // .lock
.m0_readdata (address_span_extender_0_windowed_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (address_span_extender_0_windowed_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (address_span_extender_0_windowed_slave_agent_m0_read), // .read
.m0_waitrequest (address_span_extender_0_windowed_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (address_span_extender_0_windowed_slave_agent_m0_writedata), // .writedata
.m0_write (address_span_extender_0_windowed_slave_agent_m0_write), // .write
.rp_endofpacket (address_span_extender_0_windowed_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (address_span_extender_0_windowed_slave_agent_rp_ready), // .ready
.rp_valid (address_span_extender_0_windowed_slave_agent_rp_valid), // .valid
.rp_data (address_span_extender_0_windowed_slave_agent_rp_data), // .data
.rp_startofpacket (address_span_extender_0_windowed_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (address_span_extender_0_windowed_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (address_span_extender_0_windowed_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (address_span_extender_0_windowed_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (address_span_extender_0_windowed_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (address_span_extender_0_windowed_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_windowed_slave_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_windowed_slave_agent_rf_source_data), // in.data
.in_valid (address_span_extender_0_windowed_slave_agent_rf_source_valid), // .valid
.in_ready (address_span_extender_0_windowed_slave_agent_rf_source_ready), // .ready
.in_startofpacket (address_span_extender_0_windowed_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (address_span_extender_0_windowed_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_windowed_slave_agent_rdata_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_cntl_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (address_span_extender_0_cntl_agent_m0_address), // m0.address
.m0_burstcount (address_span_extender_0_cntl_agent_m0_burstcount), // .burstcount
.m0_byteenable (address_span_extender_0_cntl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (address_span_extender_0_cntl_agent_m0_debugaccess), // .debugaccess
.m0_lock (address_span_extender_0_cntl_agent_m0_lock), // .lock
.m0_readdata (address_span_extender_0_cntl_agent_m0_readdata), // .readdata
.m0_readdatavalid (address_span_extender_0_cntl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (address_span_extender_0_cntl_agent_m0_read), // .read
.m0_waitrequest (address_span_extender_0_cntl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (address_span_extender_0_cntl_agent_m0_writedata), // .writedata
.m0_write (address_span_extender_0_cntl_agent_m0_write), // .write
.rp_endofpacket (address_span_extender_0_cntl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (address_span_extender_0_cntl_agent_rp_ready), // .ready
.rp_valid (address_span_extender_0_cntl_agent_rp_valid), // .valid
.rp_data (address_span_extender_0_cntl_agent_rp_data), // .data
.rp_startofpacket (address_span_extender_0_cntl_agent_rp_startofpacket), // .startofpacket
.cp_ready (address_span_extender_0_cntl_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (address_span_extender_0_cntl_cmd_width_adapter_src_valid), // .valid
.cp_data (address_span_extender_0_cntl_cmd_width_adapter_src_data), // .data
.cp_startofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (address_span_extender_0_cntl_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (address_span_extender_0_cntl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (address_span_extender_0_cntl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (address_span_extender_0_cntl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (address_span_extender_0_cntl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (address_span_extender_0_cntl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (address_span_extender_0_cntl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (address_span_extender_0_cntl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (address_span_extender_0_cntl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (address_span_extender_0_cntl_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (address_span_extender_0_cntl_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (address_span_extender_0_cntl_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (address_span_extender_0_cntl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (address_span_extender_0_cntl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (address_span_extender_0_cntl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_cntl_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_cntl_agent_rf_source_data), // in.data
.in_valid (address_span_extender_0_cntl_agent_rf_source_valid), // .valid
.in_ready (address_span_extender_0_cntl_agent_rf_source_ready), // .ready
.in_startofpacket (address_span_extender_0_cntl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (address_span_extender_0_cntl_agent_rf_source_endofpacket), // .endofpacket
.out_data (address_span_extender_0_cntl_agent_rsp_fifo_out_data), // out.data
.out_valid (address_span_extender_0_cntl_agent_rsp_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_cntl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (66),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_cntl_agent_rdata_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_cntl_agent_rdata_fifo_src_data), // in.data
.in_valid (address_span_extender_0_cntl_agent_rdata_fifo_src_valid), // .valid
.in_ready (address_span_extender_0_cntl_agent_rdata_fifo_src_ready), // .ready
.out_data (address_span_extender_0_cntl_agent_rdata_fifo_out_data), // out.data
.out_valid (address_span_extender_0_cntl_agent_rdata_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_cntl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sys_description_rom_s1_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sys_description_rom_s1_agent_m0_address), // m0.address
.m0_burstcount (sys_description_rom_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sys_description_rom_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sys_description_rom_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sys_description_rom_s1_agent_m0_lock), // .lock
.m0_readdata (sys_description_rom_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sys_description_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sys_description_rom_s1_agent_m0_read), // .read
.m0_waitrequest (sys_description_rom_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sys_description_rom_s1_agent_m0_writedata), // .writedata
.m0_write (sys_description_rom_s1_agent_m0_write), // .write
.rp_endofpacket (sys_description_rom_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sys_description_rom_s1_agent_rp_ready), // .ready
.rp_valid (sys_description_rom_s1_agent_rp_valid), // .valid
.rp_data (sys_description_rom_s1_agent_rp_data), // .data
.rp_startofpacket (sys_description_rom_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sys_description_rom_s1_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (sys_description_rom_s1_cmd_width_adapter_src_valid), // .valid
.cp_data (sys_description_rom_s1_cmd_width_adapter_src_data), // .data
.cp_startofpacket (sys_description_rom_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (sys_description_rom_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (sys_description_rom_s1_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (sys_description_rom_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sys_description_rom_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sys_description_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sys_description_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sys_description_rom_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sys_description_rom_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sys_description_rom_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sys_description_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sys_description_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sys_description_rom_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sys_description_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sys_description_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sys_description_rom_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sys_description_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sys_description_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sys_description_rom_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (3),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sys_description_rom_s1_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sys_description_rom_s1_agent_rf_source_data), // in.data
.in_valid (sys_description_rom_s1_agent_rf_source_valid), // .valid
.in_ready (sys_description_rom_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sys_description_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sys_description_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sys_description_rom_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sys_description_rom_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sys_description_rom_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sys_description_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sys_description_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sw_reset_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sw_reset_s_agent_m0_address), // m0.address
.m0_burstcount (sw_reset_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (sw_reset_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sw_reset_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (sw_reset_s_agent_m0_lock), // .lock
.m0_readdata (sw_reset_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sw_reset_s_agent_m0_read), // .read
.m0_waitrequest (sw_reset_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sw_reset_s_agent_m0_writedata), // .writedata
.m0_write (sw_reset_s_agent_m0_write), // .write
.rp_endofpacket (sw_reset_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sw_reset_s_agent_rp_ready), // .ready
.rp_valid (sw_reset_s_agent_rp_valid), // .valid
.rp_data (sw_reset_s_agent_rp_data), // .data
.rp_startofpacket (sw_reset_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (sw_reset_s_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (sw_reset_s_cmd_width_adapter_src_valid), // .valid
.cp_data (sw_reset_s_cmd_width_adapter_src_data), // .data
.cp_startofpacket (sw_reset_s_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (sw_reset_s_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (sw_reset_s_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (sw_reset_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sw_reset_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sw_reset_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sw_reset_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sw_reset_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sw_reset_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sw_reset_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sw_reset_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sw_reset_s_agent_rf_source_data), // in.data
.in_valid (sw_reset_s_agent_rf_source_valid), // .valid
.in_ready (sw_reset_s_agent_rf_source_ready), // .ready
.in_startofpacket (sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (sw_reset_s_agent_rsp_fifo_out_data), // out.data
.out_valid (sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (sw_reset_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) mem_org_mode_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (mem_org_mode_s_agent_m0_address), // m0.address
.m0_burstcount (mem_org_mode_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (mem_org_mode_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (mem_org_mode_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (mem_org_mode_s_agent_m0_lock), // .lock
.m0_readdata (mem_org_mode_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (mem_org_mode_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (mem_org_mode_s_agent_m0_read), // .read
.m0_waitrequest (mem_org_mode_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (mem_org_mode_s_agent_m0_writedata), // .writedata
.m0_write (mem_org_mode_s_agent_m0_write), // .write
.rp_endofpacket (mem_org_mode_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (mem_org_mode_s_agent_rp_ready), // .ready
.rp_valid (mem_org_mode_s_agent_rp_valid), // .valid
.rp_data (mem_org_mode_s_agent_rp_data), // .data
.rp_startofpacket (mem_org_mode_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (mem_org_mode_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (mem_org_mode_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (mem_org_mode_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (mem_org_mode_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (mem_org_mode_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (mem_org_mode_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (mem_org_mode_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (mem_org_mode_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (mem_org_mode_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (mem_org_mode_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (mem_org_mode_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (mem_org_mode_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (mem_org_mode_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (mem_org_mode_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (mem_org_mode_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (mem_org_mode_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) mem_org_mode_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (mem_org_mode_s_agent_rf_source_data), // in.data
.in_valid (mem_org_mode_s_agent_rf_source_valid), // .valid
.in_ready (mem_org_mode_s_agent_rf_source_ready), // .ready
.in_startofpacket (mem_org_mode_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (mem_org_mode_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (mem_org_mode_s_agent_rsp_fifo_out_data), // out.data
.out_valid (mem_org_mode_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (mem_org_mode_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (mem_org_mode_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (mem_org_mode_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) version_id_0_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (version_id_0_s_agent_m0_address), // m0.address
.m0_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (version_id_0_s_agent_m0_lock), // .lock
.m0_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (version_id_0_s_agent_m0_read), // .read
.m0_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.m0_write (version_id_0_s_agent_m0_write), // .write
.rp_endofpacket (version_id_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (version_id_0_s_agent_rp_ready), // .ready
.rp_valid (version_id_0_s_agent_rp_valid), // .valid
.rp_data (version_id_0_s_agent_rp_data), // .data
.rp_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (version_id_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (version_id_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (version_id_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (version_id_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (version_id_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_0_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_0_s_agent_rf_source_data), // in.data
.in_valid (version_id_0_s_agent_rf_source_valid), // .valid
.in_ready (version_id_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (version_id_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (version_id_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) irq_ena_0_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (irq_ena_0_s_agent_m0_address), // m0.address
.m0_burstcount (irq_ena_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (irq_ena_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (irq_ena_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (irq_ena_0_s_agent_m0_lock), // .lock
.m0_readdata (irq_ena_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (irq_ena_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (irq_ena_0_s_agent_m0_read), // .read
.m0_waitrequest (irq_ena_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (irq_ena_0_s_agent_m0_writedata), // .writedata
.m0_write (irq_ena_0_s_agent_m0_write), // .write
.rp_endofpacket (irq_ena_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (irq_ena_0_s_agent_rp_ready), // .ready
.rp_valid (irq_ena_0_s_agent_rp_valid), // .valid
.rp_data (irq_ena_0_s_agent_rp_data), // .data
.rp_startofpacket (irq_ena_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (irq_ena_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (irq_ena_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (irq_ena_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (irq_ena_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (irq_ena_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (irq_ena_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (irq_ena_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (irq_ena_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (irq_ena_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (irq_ena_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (irq_ena_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (irq_ena_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (irq_ena_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (irq_ena_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (irq_ena_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (irq_ena_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) irq_ena_0_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (irq_ena_0_s_agent_rf_source_data), // in.data
.in_valid (irq_ena_0_s_agent_rf_source_valid), // .valid
.in_ready (irq_ena_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (irq_ena_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (irq_ena_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (irq_ena_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (irq_ena_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (irq_ena_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (irq_ena_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (irq_ena_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router router (
.sink_ready (kernel_cntrl_m0_agent_cp_ready), // sink.ready
.sink_valid (kernel_cntrl_m0_agent_cp_valid), // .valid
.sink_data (kernel_cntrl_m0_agent_cp_data), // .data
.sink_startofpacket (kernel_cntrl_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cntrl_m0_agent_cp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001 router_001 (
.sink_ready (address_span_extender_0_windowed_slave_agent_rp_ready), // sink.ready
.sink_valid (address_span_extender_0_windowed_slave_agent_rp_valid), // .valid
.sink_data (address_span_extender_0_windowed_slave_agent_rp_data), // .data
.sink_startofpacket (address_span_extender_0_windowed_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_windowed_slave_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_002 router_002 (
.sink_ready (address_span_extender_0_cntl_agent_rp_ready), // sink.ready
.sink_valid (address_span_extender_0_cntl_agent_rp_valid), // .valid
.sink_data (address_span_extender_0_cntl_agent_rp_data), // .data
.sink_startofpacket (address_span_extender_0_cntl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_cntl_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_003 router_003 (
.sink_ready (sys_description_rom_s1_agent_rp_ready), // sink.ready
.sink_valid (sys_description_rom_s1_agent_rp_valid), // .valid
.sink_data (sys_description_rom_s1_agent_rp_data), // .data
.sink_startofpacket (sys_description_rom_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sys_description_rom_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_003 router_004 (
.sink_ready (sw_reset_s_agent_rp_ready), // sink.ready
.sink_valid (sw_reset_s_agent_rp_valid), // .valid
.sink_data (sw_reset_s_agent_rp_data), // .data
.sink_startofpacket (sw_reset_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sw_reset_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_005 (
.sink_ready (mem_org_mode_s_agent_rp_ready), // sink.ready
.sink_valid (mem_org_mode_s_agent_rp_valid), // .valid
.sink_data (mem_org_mode_s_agent_rp_data), // .data
.sink_startofpacket (mem_org_mode_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (mem_org_mode_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_006 (
.sink_ready (version_id_0_s_agent_rp_ready), // sink.ready
.sink_valid (version_id_0_s_agent_rp_valid), // .valid
.sink_data (version_id_0_s_agent_rp_data), // .data
.sink_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (version_id_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_007 (
.sink_ready (irq_ena_0_s_agent_rp_ready), // sink.ready
.sink_valid (irq_ena_0_s_agent_rp_valid), // .valid
.sink_data (irq_ena_0_s_agent_rp_data), // .data
.sink_startofpacket (irq_ena_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (irq_ena_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.MAX_OUTSTANDING_RESPONSES (5),
.PIPELINED (0),
.ST_DATA_W (89),
.ST_CHANNEL_W (7),
.VALID_WIDTH (7),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) kernel_cntrl_m0_limiter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (kernel_cntrl_m0_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (kernel_cntrl_m0_limiter_cmd_src_data), // .data
.cmd_src_channel (kernel_cntrl_m0_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (kernel_cntrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (kernel_cntrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (kernel_cntrl_m0_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (kernel_cntrl_m0_limiter_rsp_src_valid), // .valid
.rsp_src_data (kernel_cntrl_m0_limiter_rsp_src_data), // .data
.rsp_src_channel (kernel_cntrl_m0_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (kernel_cntrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (kernel_cntrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (kernel_cntrl_m0_limiter_cmd_valid_data) // cmd_valid.data
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_demux cmd_demux (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cntrl_m0_limiter_cmd_src_ready), // sink.ready
.sink_channel (kernel_cntrl_m0_limiter_cmd_src_channel), // .channel
.sink_data (kernel_cntrl_m0_limiter_cmd_src_data), // .data
.sink_startofpacket (kernel_cntrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cntrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (kernel_cntrl_m0_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux_001 (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (crosser_001_out_ready), // sink0.ready
.sink0_valid (crosser_001_out_valid), // .valid
.sink0_channel (crosser_001_out_channel), // .channel
.sink0_data (crosser_001_out_data), // .data
.sink0_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_001_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_002 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_003 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_004 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_005 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_006 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_src6_valid), // .valid
.sink0_channel (cmd_demux_src6_channel), // .channel
.sink0_data (cmd_demux_src6_data), // .data
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux rsp_demux_001 (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (address_span_extender_0_cntl_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (address_span_extender_0_cntl_rsp_width_adapter_src_channel), // .channel
.sink_data (address_span_extender_0_cntl_rsp_width_adapter_src_data), // .data
.sink_startofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (address_span_extender_0_cntl_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_002 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sys_description_rom_s1_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sys_description_rom_s1_rsp_width_adapter_src_channel), // .channel
.sink_data (sys_description_rom_s1_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sys_description_rom_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sys_description_rom_s1_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sys_description_rom_s1_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_003 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sw_reset_s_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sw_reset_s_rsp_width_adapter_src_channel), // .channel
.sink_data (sw_reset_s_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sw_reset_s_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sw_reset_s_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sw_reset_s_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_004 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_005 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_006 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_mux rsp_mux (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_002_out_ready), // sink0.ready
.sink0_valid (crosser_002_out_valid), // .valid
.sink0_channel (crosser_002_out_channel), // .channel
.sink0_data (crosser_002_out_data), // .data
.sink0_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.sink1_ready (crosser_003_out_ready), // sink1.ready
.sink1_valid (crosser_003_out_valid), // .valid
.sink1_channel (crosser_003_out_channel), // .channel
.sink1_data (crosser_003_out_data), // .data
.sink1_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) address_span_extender_0_cntl_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_001_src_valid), // sink.valid
.in_channel (cmd_mux_001_src_channel), // .channel
.in_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_001_src_ready), // .ready
.in_data (cmd_mux_001_src_data), // .data
.out_endofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (address_span_extender_0_cntl_cmd_width_adapter_src_data), // .data
.out_channel (address_span_extender_0_cntl_cmd_width_adapter_src_channel), // .channel
.out_valid (address_span_extender_0_cntl_cmd_width_adapter_src_valid), // .valid
.out_ready (address_span_extender_0_cntl_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sys_description_rom_s1_cmd_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_002_src_valid), // sink.valid
.in_channel (cmd_mux_002_src_channel), // .channel
.in_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_002_src_ready), // .ready
.in_data (cmd_mux_002_src_data), // .data
.out_endofpacket (sys_description_rom_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sys_description_rom_s1_cmd_width_adapter_src_data), // .data
.out_channel (sys_description_rom_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sys_description_rom_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sys_description_rom_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sys_description_rom_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sw_reset_s_cmd_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_003_src_valid), // sink.valid
.in_channel (cmd_mux_003_src_channel), // .channel
.in_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_003_src_ready), // .ready
.in_data (cmd_mux_003_src_data), // .data
.out_endofpacket (sw_reset_s_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sw_reset_s_cmd_width_adapter_src_data), // .data
.out_channel (sw_reset_s_cmd_width_adapter_src_channel), // .channel
.out_valid (sw_reset_s_cmd_width_adapter_src_valid), // .valid
.out_ready (sw_reset_s_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sw_reset_s_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) address_span_extender_0_cntl_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_002_src_valid), // sink.valid
.in_channel (router_002_src_channel), // .channel
.in_startofpacket (router_002_src_startofpacket), // .startofpacket
.in_endofpacket (router_002_src_endofpacket), // .endofpacket
.in_ready (router_002_src_ready), // .ready
.in_data (router_002_src_data), // .data
.out_endofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (address_span_extender_0_cntl_rsp_width_adapter_src_data), // .data
.out_channel (address_span_extender_0_cntl_rsp_width_adapter_src_channel), // .channel
.out_valid (address_span_extender_0_cntl_rsp_width_adapter_src_valid), // .valid
.out_ready (address_span_extender_0_cntl_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sys_description_rom_s1_rsp_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_003_src_valid), // sink.valid
.in_channel (router_003_src_channel), // .channel
.in_startofpacket (router_003_src_startofpacket), // .startofpacket
.in_endofpacket (router_003_src_endofpacket), // .endofpacket
.in_ready (router_003_src_ready), // .ready
.in_data (router_003_src_data), // .data
.out_endofpacket (sys_description_rom_s1_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sys_description_rom_s1_rsp_width_adapter_src_data), // .data
.out_channel (sys_description_rom_s1_rsp_width_adapter_src_channel), // .channel
.out_valid (sys_description_rom_s1_rsp_width_adapter_src_valid), // .valid
.out_ready (sys_description_rom_s1_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sys_description_rom_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sw_reset_s_rsp_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_004_src_valid), // sink.valid
.in_channel (router_004_src_channel), // .channel
.in_startofpacket (router_004_src_startofpacket), // .startofpacket
.in_endofpacket (router_004_src_endofpacket), // .endofpacket
.in_ready (router_004_src_ready), // .ready
.in_data (router_004_src_data), // .data
.out_endofpacket (sw_reset_s_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sw_reset_s_rsp_width_adapter_src_data), // .data
.out_channel (sw_reset_s_rsp_width_adapter_src_channel), // .channel
.out_valid (sw_reset_s_rsp_width_adapter_src_valid), // .valid
.out_ready (sw_reset_s_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sw_reset_s_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_reset_clk_clk), // in_clk.clk
.in_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (kernel_clk_out_clk_clk), // out_clk.clk
.out_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src0_ready), // in.ready
.in_valid (cmd_demux_src0_valid), // .valid
.in_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.in_channel (cmd_demux_src0_channel), // .channel
.in_data (cmd_demux_src0_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_reset_clk_clk), // in_clk.clk
.in_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (kernel_clk_out_clk_clk), // out_clk.clk
.out_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src1_ready), // in.ready
.in_valid (cmd_demux_src1_valid), // .valid
.in_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.in_channel (cmd_demux_src1_channel), // .channel
.in_data (cmd_demux_src1_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (kernel_clk_out_clk_clk), // in_clk.clk
.in_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_reset_clk_clk), // out_clk.clk
.out_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_src0_ready), // in.ready
.in_valid (rsp_demux_src0_valid), // .valid
.in_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_src0_channel), // .channel
.in_data (rsp_demux_src0_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (kernel_clk_out_clk_clk), // in_clk.clk
.in_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_reset_clk_clk), // out_clk.clk
.out_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_001_src0_ready), // in.ready
.in_valid (rsp_demux_001_src0_valid), // .valid
.in_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_001_src0_channel), // .channel
.in_data (rsp_demux_001_src0_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O2BB2A_FUNCTIONAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: gng_top_tb
// Description: Top level testbench. Compares output and intermediate values to
// expected results stored in text files.
//////////////////////////////////////////////////////////////////////////////////
module gng_top_tb;
reg clk, rst, test_clk;
wire [15:0] data_out;
integer lzd_file, urn_file, mult_in_file, mult1_file, sum1_file, mult2_file, sum2_file, output_file, scan_line;
reg [5:0] ref_lzd;
reg [63:0] ref_urn;
reg [14:0] ref_mult_in;
reg [34:0] ref_mult1;
reg [38:0] ref_sum1;
reg [35:0] ref_mult2;
reg [40:0] ref_sum2;
reg [15:0] ref_output;
reg [15:0] test_en_reg;
reg test_fail;
initial
begin
lzd_file = $fopen("lzd_ref_results.txt","r");
urn_file = $fopen("urn_ref_results.txt","r");
mult_in_file = $fopen("mult_input_ref_results.txt","r");
mult1_file = $fopen("mult1_output_ref_results.txt","r");
sum1_file = $fopen("sum1_output_ref_results.txt","r");
mult2_file = $fopen("mult2_output_ref_results.txt","r");
sum2_file = $fopen("sum2_output_ref_results.txt","r");
output_file = $fopen("output_ref_results.txt","r");
rst = 1'b1;
clk = 1'b0;
test_clk = 1'b0;
test_en_reg = 13'd0;
test_fail = 1'b0;
#20 rst = 1'b0;
end
always
#10 clk <= ~clk;
always begin
#1 test_clk <= ~test_clk;
#9 ;
end
gng_top i_gng_top (.clk(clk), .rst(rst), .awgn_out(data_out));
always @ (posedge test_clk) begin
test_en_reg <= {test_en_reg[14:0],1'b1};
end
always @(posedge test_clk) begin
if (test_en_reg[3]) begin
// Check Tausworthe generator output
scan_line = $fscanf(urn_file, "%b\n", ref_urn);
if (!$feof(urn_file)) begin
if (ref_urn !== i_gng_top.urn_data) begin
test_fail <= 1'b1;
$warning("***Mismatch in Uniform Random Number Generator data***");
end
end
end
if (test_en_reg[5]) begin
// Test Leading Zero Detector
scan_line = $fscanf(lzd_file, "%x\n", ref_lzd);
if (!$feof(lzd_file)) begin
if (ref_lzd !== (i_gng_top.i_gng_interpolator.lz_pos + 6'd1)) begin
// Add one to account for 0 vs 1 indexing
test_fail <= 1'b1;
$warning("***Mismatch in LZD data***");
end
end
// Test Mask To Zero
scan_line = $fscanf(mult_in_file, "%x\n", ref_mult_in);
if (!$feof(mult_in_file)) begin
if (ref_mult_in !== i_gng_top.i_gng_interpolator.mult_in) begin
test_fail <= 1'b1;
$warning("***Mismatch in Mask To Zero output data***");
end
end
end
if (test_en_reg[9]) begin
// Test first multiply
scan_line = $fscanf(mult1_file, "%x\n", ref_mult1);
if (!$feof(mult1_file)) begin
if (ref_mult1 !== i_gng_top.i_gng_interpolator.i_mult_add1.prod) begin
test_fail <= 1'b1;
$warning("***Mismatch in first multiply***");
end
end
end
if (test_en_reg[10]) begin
// Test first add
scan_line = $fscanf(sum1_file, "%x\n", ref_sum1);
if (!$feof(sum1_file)) begin
if (ref_sum1 !== i_gng_top.i_gng_interpolator.i_mult_add1.result) begin
test_fail <= 1'b1;
$warning("***Mismatch in first add***");
end
end
end
if (test_en_reg[12]) begin
// Test second multiply
scan_line = $fscanf(mult2_file, "%x\n", ref_mult2);
if (!$feof(mult2_file)) begin
if (ref_mult2 !== i_gng_top.i_gng_interpolator.i_mult_add2.prod) begin
test_fail <= 1'b1;
$warning("***Mismatch in second multiply***");
end
end
end
if (test_en_reg[13]) begin
// Test second add
scan_line = $fscanf(sum2_file, "%x\n", ref_sum2);
if (!$feof(sum2_file)) begin
if (ref_sum2 !== i_gng_top.i_gng_interpolator.i_mult_add2.result) begin
test_fail <= 1'b1;
$warning("***Mismatch in second add***");
end
end
end
if (test_en_reg[14]) begin
// Test second add
scan_line = $fscanf(output_file, "%d\n", ref_output);
if (!$feof(output_file)) begin
if (ref_output !== data_out) begin
test_fail <= 1'b1;
$warning("***Mismatch in output data***");
end
end
else begin
if (test_fail) begin
$display("TEST FAILED : Errors occured during simulation - check transcript");
$finish;
end
else begin
$display("Test Passed! All test-points are bit-accurate to the reference.");
$finish;
end
end
end
end
endmodule
|
/**
\file "inverters-delay.v"
Modifying default delay value.
$Id: inverters-delay.v,v 1.2 2010/04/06 00:08:33 fang Exp $
*/
`timescale 1ns/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
wire in;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
// prsim stuff
initial
begin
// @haco@ inverters.haco-c
$prsim_default_after(25); // in prsim time units
$prsim("inverters.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("timing after");
// $prsim_cmd("watchall");
// $prsim_cmd("fanin out1");
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.out0", "in1");
$to_prsim("TOP.out1", "in2");
$to_prsim("TOP.out2", "in3");
$to_prsim("TOP.out3", "in4");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$from_prsim("out4","TOP.out");
end
initial #30 $finish;
always @(in)
begin
$display("at time %7.3f, observed in %b", $realtime,in);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2I_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__MUX2I_BEHAVIORAL_PP_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_lp__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_lp__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2I_BEHAVIORAL_PP_V |
`timescale 1ns/1ns
/*
* Trial test bench for clock switching between two asynchronous clocks, but where one clock is synchronous to a much
* higher speed clock which is used to control the digital state machine
*
* Enable the `define STOP_IN_PHI1_D to stop the clocks low for the handover, and omit it to stop in PHI2.
*
* ie for Beeb816 there's not much time to detect whether to switch to the low speed clock when running in a
* high speed mode if STOP_ON_PHI1 is selected - this is probably why we defaulted to stopping in PHI2 instead.
*
* In this version
* o hsclk = high speed clock
* o hsclk_by4 = hsclk div 4, alternative for 65816 clock
* o hsclk_by2 = hsclk div 2, expected to be the 65816 CPU clock
* o lsclk = low speed clock
*
* The state machine needs at least a 2x relationship between hsclk and the CPU clock, and assumes that
* the lsclk is much slower. Clock switching with this version is quicker than with the fully async one,
* but there is still the same limitation that when stopping in PHI1 (PHI2) the clock selection signal must only
* change in PHI1 (PHI2).
*
* Sample clock must be >= 6x faster than the async BBC clock due to the length of the retiming chain.
*
* Setting stop on PHI1 requires the state machine to wait with clock low until it sees a falling edge on the other clock
* Setting stop on PHI2 requires the state machine to wait with clock low until it sees a rising edge on the other clock
*
*
*/
//`define STOP_ON_PHI1_D 1
//`define DIVIDE_BY_4_D
`define CHANGEDGE negedge
`define LSCLK_HALF_CYCLE 250 // 2MHz mother board clock
`define HSCLK_HALF_CYCLE 30.5 // 16.384MHZ XTAL
`define HSCLK_DIV 2'b00
`define CPUCLK_DIV 2'b00
module clkctrl2_tb ;
reg reset_b_r;
reg lsclk_r;
reg hsclk_r;
reg hienable_r;
wire clkout;
wire hsclk_selected_w;
initial
begin
$dumpvars();
reset_b_r = 0;
lsclk_r = 0;
hsclk_r = 0;
hienable_r = 0;
#500 reset_b_r = 1;
#2000;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 1;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 0;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 1;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 0;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 1;
#2000 $finish();
end
always
#`LSCLK_HALF_CYCLE lsclk_r = !lsclk_r ;
always
#`HSCLK_HALF_CYCLE hsclk_r = !hsclk_r ;
`ifdef SYNC_SWITCH_D
clkctrl2 clkctrl2_u(
.hsclk_in(hsclk_r),
.lsclk_in(lsclk_r),
.rst_b(reset_b_r),
.hsclk_sel(hienable_r),
.hsclk_div_sel(`HSCLK_DIV),
.cpuclk_div_sel(`CPUCLK_DIV),
.hsclk_selected(hsclk_selected_w),
.clkout(clkout)
);
`else
clkctrl clkctrl_u(
.hsclk_in(hsclk_r),
.lsclk_in(lsclk_r),
.rst_b(reset_b_r),
.hsclk_sel(hienable_r),
.cpuclk_div_sel(`CPUCLK_DIV),
.hsclk_selected(hsclk_selected_w),
.clkout(clkout)
);
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41A_4_V
`define SKY130_FD_SC_MS__O41A_4_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o41a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o41a_4 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o41a_4 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41A_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRTN_SYMBOL_V
`define SKY130_FD_SC_HS__DFRTN_SYMBOL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRTN_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O21AI_BEHAVIORAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21AI_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221OI_2_V
`define SKY130_FD_SC_LS__A221OI_2_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a221oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a221oi_2 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221OI_2_V
|
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
/*
########################################################################
EPIPHANY CONFIGURATION REGISTER
########################################################################
-------------------------------------------------------------
ESYSRESET ***Elink reset***
[0] 0 - elink active
1 - elink in reset
-------------------------------------------------------------
ESYSCFGTX ***Elink transmitter configuration***
[0] 0 - link TX disable
1 - link TX enable
[1] 0 - normal pass through transaction mode
1 - mmu mode
[3:2] 00 - normal mode
01 - gpio mode
10 - reserved
11 - reserved
[7:4] Transmit control mode for eMesh
[9:8] 00 - No division, full speed
01 - Divide by 2
10 - Reserved
11 - Reserved
-------------------------------------------------------------
ESYSCFGRX ***Elink receiver configuration***
[0] 0 - link RX disable
1 - link RX enable
[1] 0 - normal transaction mode
1 - mmu mode
[3:2] 00 - normal mode
01 - GPIO mode (drive rd wait pins from registers)
10 - loopback mode (loops TX-->RX)
11 - reserved
[4] 0 - set monitor to count traffic
1 - set monitor to count congestion
-------------------------------------------------------------
ESYSCFGCLK ***Epiphany clock frequency setting***
[3:0] Output divider
000 - DC
0001 - CLKIN/64
0010 - CLKIN/32
0011 - CLKIN/16
0100 - CLKIN/8
0101 - CLKIN/4
0110 - CLKIN/2
0111 - CLKIN/1 (full speed)
1XXX - RESERVED
[7:4] PLL settings (TBD)
-------------------------------------------------------------
ESYSCOREID ***CORE ID***
[5:0] Column ID-->default at powerup/reset
[11:6] Row ID
-------------------------------------------------------------
ESYSVERSION ***Version number (read only)***
[7:0] Revision #, incremented in each change (match git?)
[15:8] Type (features included in FPGA load, same board)
[23:16] Board platform #
[31:24] Generation # (needed??)
-------------------------------------------------------------
ESYSDATAIN ***Data on elink input pins
[7:0] rx_data[7:0]
[8] tx_frame
[9] tx_wait_rd
[10] tx_wait_wr
-------------------------------------------------------------
ESYSDATAOUT ***Data on eLink output pins
[7:0] tx_data[7:0]
[8] tx_frame
[9] rx_wait_rd
[10] rx_wait_wr
########################################################################
*/
`define E_REG_SYSRESET 20'hf0340
`define E_REG_SYSCFGTX 20'hf0344
`define E_REG_SYSCFGRX 20'hf0348
`define E_REG_SYSCFGCLK 20'hf034c
`define E_REG_SYSCOREID 20'hf0350
`define E_REG_SYSVERSION 20'hf0354
`define E_REG_SYSDATAIN 20'hf0358
`define E_REG_SYSDATAOUT 20'hf035c
`define E_VERSION 32'h01_02_03_04
module ecfg (/*AUTOARG*/
// Outputs
mi_data_out, mi_data_sel, ecfg_sw_reset, ecfg_reset,
ecfg_tx_enable, ecfg_tx_mmu_mode, ecfg_tx_gpio_mode,
ecfg_tx_ctrl_mode, ecfg_tx_clkdiv, ecfg_rx_enable,
ecfg_rx_mmu_mode, ecfg_rx_gpio_mode, ecfg_rx_loopback_mode,
ecfg_cclk_en, ecfg_cclk_div, ecfg_cclk_pllcfg, ecfg_coreid,
ecfg_gpio_dataout,
// Inputs
param_coreid, clk, hw_reset, mi_access, mi_write, mi_addr,
mi_data_in
);
//Register file parameters
/*
#####################################################################
COMPILE TIME PARAMETERS
######################################################################
*/
parameter EMAW = 12; //mmu table address width
parameter EDW = 32; //Epiphany native data width
parameter EAW = 32; //Epiphany native address width
parameter IDW = 12; //Elink ID (row,column coordinate)
parameter RFAW = 5; //Number of registers=2^RFAW
/*****************************/
/*STATIC CONFIG SIGNALS */
/*****************************/
input [IDW-1:0] param_coreid;
/*****************************/
/*SIMPLE MEMORY INTERFACE */
/*****************************/
input clk;
input hw_reset;
input mi_access;
input mi_write;
input [19:0] mi_addr;
input [31:0] mi_data_in;
output [31:0] mi_data_out;
output mi_data_sel;
/*****************************/
/*ELINK CONTROL SIGNALS */
/*****************************/
//RESET
output ecfg_sw_reset;
output ecfg_reset;
//tx
output ecfg_tx_enable; //enable signal for TX
output ecfg_tx_mmu_mode; //enables MMU on transnmit path
output ecfg_tx_gpio_mode; //forces TX output pins to constants
output [3:0] ecfg_tx_ctrl_mode; //value for emesh ctrlmode tag
output [3:0] ecfg_tx_clkdiv; //transmit clock divider
//rx
output ecfg_rx_enable; //enable signal for rx
output ecfg_rx_mmu_mode; //enables MMU on rx path
output ecfg_rx_gpio_mode; //forces rx wait pins to constants
output ecfg_rx_loopback_mode; //loops back tx to rx receiver (after serdes)
//cclk
output ecfg_cclk_en; //cclk enable
output [3:0] ecfg_cclk_div; //cclk divider setting
output [3:0] ecfg_cclk_pllcfg; //pll configuration
//coreid
output [11:0] ecfg_coreid; //core-id of fpga elink
//gpio
output [11:0] ecfg_gpio_dataout; //data for elink outputs {rd_wait,wr_wait,frame,data[7:0}
//registers
reg [11:0] ecfg_cfgtx_reg;
reg [4:0] ecfg_cfgrx_reg;
reg [7:0] ecfg_cfgclk_reg;
reg [11:0] ecfg_coreid_reg;
wire [31:0] ecfg_version_reg;
reg ecfg_reset_reg;
reg [11:0] ecfg_gpio_datain_reg;
reg [11:0] ecfg_gpio_dataout_reg;
reg [31:0] mi_data_out;
reg mi_data_sel;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_reset_match;
wire ecfg_cfgtx_match;
wire ecfg_cfgrx_match;
wire ecfg_cfgclk_match;
wire ecfg_coreid_match;
wire ecfg_version_match;
wire ecfg_datain_match;
wire ecfg_dataout_match;
wire ecfg_match;
wire ecfg_regmux;
wire [31:0] ecfg_reg_mux;
wire ecfg_cfgtx_write;
wire ecfg_cfgrx_write;
wire ecfg_cfgclk_write;
wire ecfg_coreid_write;
wire ecfg_version_write;
wire ecfg_datain_write;
wire ecfg_dataout_write;
wire ecfg_rx_monitor_mode;
wire ecfg_reset_write;
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
//read/write decode
assign ecfg_write = mi_access & mi_write;
assign ecfg_read = mi_access & ~mi_write;
//address match signals
assign ecfg_reset_match = mi_addr[19:0]==`E_REG_SYSRESET;
assign ecfg_cfgtx_match = mi_addr[19:0]==`E_REG_SYSCFGTX;
assign ecfg_cfgrx_match = mi_addr[19:0]==`E_REG_SYSCFGRX;
assign ecfg_cfgclk_match = mi_addr[19:0]==`E_REG_SYSCFGCLK;
assign ecfg_coreid_match = mi_addr[19:0]==`E_REG_SYSCOREID;
assign ecfg_version_match = mi_addr[19:0]==`E_REG_SYSVERSION;
assign ecfg_datain_match = mi_addr[19:0]==`E_REG_SYSDATAIN;
assign ecfg_dataout_match = mi_addr[19:0]==`E_REG_SYSDATAOUT;
assign ecfg_match = ecfg_reset_match |
ecfg_cfgtx_match |
ecfg_cfgrx_match |
ecfg_cfgclk_match |
ecfg_coreid_match |
ecfg_version_match |
ecfg_datain_match |
ecfg_dataout_match;
//Write enables
assign ecfg_reset_write = ecfg_reset_match & ecfg_write;
assign ecfg_cfgtx_write = ecfg_cfgtx_match & ecfg_write;
assign ecfg_cfgrx_write = ecfg_cfgrx_match & ecfg_write;
assign ecfg_cfgclk_write = ecfg_cfgclk_match & ecfg_write;
assign ecfg_coreid_write = ecfg_coreid_match & ecfg_write;
assign ecfg_version_write = ecfg_version_match & ecfg_write;
assign ecfg_datain_write = ecfg_datain_match & ecfg_write;
assign ecfg_dataout_write = ecfg_dataout_match & ecfg_write;
//###########################
//# ESYSCFGTX
//###########################
always @ (posedge clk)
if(hw_reset)
ecfg_cfgtx_reg[11:0] <= 12'b0;
else if (ecfg_cfgtx_write)
ecfg_cfgtx_reg[11:0] <= mi_data_in[11:0];
assign ecfg_tx_enable = ecfg_cfgtx_reg[0];
assign ecfg_tx_mmu_mode = ecfg_cfgtx_reg[1];
assign ecfg_tx_gpio_mode = ecfg_cfgtx_reg[3:2]==2'b01;
assign ecfg_tx_ctrl_mode[3:0] = ecfg_cfgtx_reg[7:4];
assign ecfg_tx_clkdiv[3:0] = ecfg_cfgtx_reg[11:8];
//###########################
//# ESYSCFGRX
//###########################
always @ (posedge clk)
if(hw_reset)
ecfg_cfgrx_reg[4:0] <= 5'b0;
else if (ecfg_cfgrx_write)
ecfg_cfgrx_reg[4:0] <= mi_data_in[4:0];
assign ecfg_rx_enable = ecfg_cfgrx_reg[0];
assign ecfg_rx_mmu_mode = ecfg_cfgrx_reg[1];
assign ecfg_rx_gpio_mode = ecfg_cfgrx_reg[3:2]==2'b01;
assign ecfg_rx_loopback_mode = ecfg_cfgrx_reg[3:2]==2'b10;
assign ecfg_rx_monitor_mode = ecfg_cfgrx_reg[4];
//###########################
//# ESYSCFGCLK
//###########################
always @ (posedge clk)
if(hw_reset)
ecfg_cfgclk_reg[7:0] <= 8'b0;
else if (ecfg_cfgclk_write)
ecfg_cfgclk_reg[7:0] <= mi_data_in[7:0];
assign ecfg_cclk_en = ~(ecfg_cfgclk_reg[3:0]==4'b0000);
assign ecfg_cclk_div[3:0] = ecfg_cfgclk_reg[3:0];
assign ecfg_cclk_pllcfg[3:0] = ecfg_cfgclk_reg[7:4];
//###########################
//# ESYSCOREID
//###########################
always @ (posedge clk)
if(hw_reset)
ecfg_coreid_reg[IDW-1:0] <= param_coreid[IDW-1:0];
else if (ecfg_coreid_write)
ecfg_coreid_reg[IDW-1:0] <= mi_data_in[IDW-1:0];
assign ecfg_coreid[IDW-1:0] = ecfg_coreid_reg[IDW-1:0];
//###########################
//# ESYSVERSION
//###########################
assign ecfg_version_reg[31:0] = `E_VERSION;
//###########################
//# ESYSDATAIN
//###########################
always @ (posedge clk)
if(hw_reset)
ecfg_gpio_datain_reg[11:0] <= 12'b0;
else if (ecfg_datain_write)
ecfg_gpio_datain_reg[11:0] <= mi_data_in[11:0];
//###########################
//# ESYSDATAOUT
//###########################
always @ (posedge clk)
if(hw_reset)
ecfg_gpio_dataout_reg[11:0] <= 12'b0;
else if (ecfg_dataout_write)
ecfg_gpio_dataout_reg[11:0] <= mi_data_in[11:0];
assign ecfg_gpio_dataout[11:0] = ecfg_gpio_dataout_reg[11:0];
//###########################
//# ESYSRESET
//###########################
always @ (posedge clk)
if(hw_reset)
ecfg_reset_reg <= 1'b0;
else if (ecfg_reset_write)
ecfg_reset_reg <= mi_data_in[0];
assign ecfg_sw_reset = ecfg_reset_reg;
assign ecfg_reset = ecfg_sw_reset | hw_reset;
//###############################
//# DATA READBACK MUX
//###############################
assign ecfg_reg_mux[31:0] = ({(32){ecfg_reset_match}} & {20'b0,ecfg_cfgtx_reg[11:0]}) |
({(32){ecfg_cfgtx_match}} & {20'b0,ecfg_cfgtx_reg[11:0]}) |
({(32){ecfg_cfgrx_match}} & {27'b0,ecfg_cfgrx_reg[4:0]}) |
({(32){ecfg_cfgclk_match}} & {24'b0,ecfg_cfgclk_reg[7:0]}) |
({(32){ecfg_coreid_match}} & {20'b0,ecfg_coreid_reg[11:0]}) |
({(32){ecfg_version_match}} & ecfg_version_reg[31:0]) |
({(32){ecfg_datain_match}} & {20'b0,ecfg_gpio_datain_reg[11:0]}) |
({(32){ecfg_dataout_match}} & {20'b0,ecfg_gpio_dataout_reg[11:0]}) ;
//Pipelineing readback
always @ (posedge clk)
if(ecfg_read)
begin
mi_data_out[31:0] <= ecfg_reg_mux[31:0];
mi_data_sel <= ecfg_match;
end
endmodule // para_config
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAP_1_V
`define SKY130_FD_SC_HS__TAP_1_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog wrapper for tap with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__tap_1 (
VPWR,
VGND
);
input VPWR;
input VGND;
sky130_fd_sc_hs__tap base (
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__tap_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__tap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAP_1_V
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: David McCoy ([email protected])
* Description:
* Contains all the Platform independent PCIE Interface controllers to
* read/write data with a host computer and send/receive data from the FPGA
* The platform dependent PCIE interface is described in the module
* pcie_axi_bridge
*
* The interface that this module presents is a signle PPFIFO with signals
* to allow users to multiplex the data between a peripheral bus a memory
* bus and a DMA controller. Users should use the following signals:
*
* o_per_fifo_sel: Peripheral Bus Selected
* o_mem_fifo_sel: Memory Selected
* o_dma_fifo_sel: DMA Selected
*
* o_data_size Size of data to read/write
* o_data_address Address of the data to start reading to/from
* o_data_fifo_flg Flag indicating that the address should not be
* incremented
* o_data_read_flg Flag indicating that this is a read
* o_data_write_flg Flag indicating that this is a write
*
* i_usr_interrupt_stb User strobes this signal to send an interrupt to
* to the host
* i_usr_interrupt_value A value to send a long with the interrupt to help
* the user identify the interrupt
*
* i_data_clk A clock the ingress/egress data is referenced to
*
* Data Interface:
*
* For data interface see: http://cospandesign.github.io/fpga,fifo/2016/05/02/ppfifo.html
*
* o_ingress_fifo_rdy
* i_ingress_fifo_act
* o_ingress_fifo_size
* i_ingress_fifo_stb
* o_ingress_fifo_data
*
*
* o_egress_fifo_rdy
* i_egress_fifo_act
* o_egress_fifo_size
* i_egress_fifo_stb
* i_egress_fifo_data
*
*
* Changes:
*/
`include "project_defines.v"
//XXX: MAXIMUM PACKET SIZE CANNOT BE OVER THE 'MPS' SETTING FROM THE HOST
module artemis_pcie_controller #(
parameter SERIAL_NUMBER = 64'h000000000000C594,
parameter DATA_INGRESS_FIFO_DEPTH = 10, //4096
parameter DATA_EGRESS_FIFO_DEPTH = 6 //256
)(
input clk,
input rst,
//The Following Signals are clocked at 62.5MHz
// PCI Express Fabric Interface
input gtp_clk_p,
input gtp_clk_n,
output pci_exp_txp,
output pci_exp_txn,
input pci_exp_rxp,
input pci_exp_rxn,
input i_pcie_reset,
// Transaction (TRN) Interface
output user_lnk_up,
(* KEEP = "TRUE" *) output clk_62p5,
// Conifguration: Interrupt
output [31:0] o_bar_addr0,
output [31:0] o_bar_addr1,
output [31:0] o_bar_addr2,
output [31:0] o_bar_addr3,
output [31:0] o_bar_addr4,
output [31:0] o_bar_addr5,
// Configuration: Power Management
input cfg_turnoff_ok,
output cfg_to_turnoff,
input cfg_pm_wake,
// System Interface
output o_pcie_reset,
output received_hot_reset,
output gtp_reset_done,
output gtp_pll_lock_detect,
output pll_lock_detect,
//GTP PHY Configurations
output rx_elec_idle,
input [1:0] rx_equalizer_ctrl,
input [3:0] tx_diff_ctrl,
input [2:0] tx_pre_emphasis,
output [4:0] cfg_ltssm_state,
output [5:0] tx_buf_av,
output tx_err_drop,
//Extra Info
output [6:0] o_bar_hit,
output o_receive_axi_ready,
output [2:0] cfg_pcie_link_state,
output [7:0] cfg_bus_number,
output [4:0] cfg_device_number,
output [2:0] cfg_function_number,
output [15:0] cfg_status,
output [15:0] cfg_command,
output [15:0] cfg_dstatus,
output [15:0] cfg_dcommand,
output [15:0] cfg_lstatus,
output [15:0] cfg_lcommand,
// Configuration: Error
input cfg_err_ur,
input cfg_err_cor,
input cfg_err_ecrc,
input cfg_err_cpl_timeout,
input cfg_err_cpl_abort,
input cfg_err_posted,
input cfg_err_locked,
input [47:0] cfg_err_tlp_cpl_header,
output cfg_err_cpl_rdy,
//Debug
output [7:0] o_cfg_read_exec,
output [3:0] o_cfg_sm_state,
output [3:0] o_sm_state,
output [7:0] o_ingress_count,
output [3:0] o_ingress_state,
output [7:0] o_ingress_ri_count,
output [7:0] o_ingress_ci_count,
output [31:0] o_ingress_cmplt_count,
output [31:0] o_ingress_addr,
output dbg_reg_detected_correctable,
output dbg_reg_detected_fatal,
output dbg_reg_detected_non_fatal,
output dbg_reg_detected_unsupported,
output dbg_bad_dllp_status,
output dbg_bad_tlp_lcrc,
output dbg_bad_tlp_seq_num,
output dbg_bad_tlp_status,
output dbg_dl_protocol_status,
output dbg_fc_protocol_err_status,
output dbg_mlfrmd_length,
output dbg_mlfrmd_mps,
output dbg_mlfrmd_tcvc,
output dbg_mlfrmd_tlp_status,
output dbg_mlfrmd_unrec_type,
output dbg_poistlpstatus,
output dbg_rcvr_overflow_status,
output dbg_rply_rollover_status,
output dbg_rply_timeout_status,
output dbg_ur_no_bar_hit,
output dbg_ur_pois_cfg_wr,
output dbg_ur_status,
output dbg_ur_unsup_msg,
output [15:0] dbg_tag_ingress_fin,
output [15:0] dbg_tag_en,
output dbg_rerrfwd,
output dbg_ready_drop,
output o_dbg_reenable_stb,
output o_dbg_reenable_nzero_stb, //If the host responded a bit then this will be greater than zero
output o_sys_rst,
//User Interfaces
output o_per_fifo_sel,
output o_mem_fifo_sel,
output o_dma_fifo_sel,
input i_write_fin,
input i_read_fin,
output [31:0] o_data_size,
output [31:0] o_data_address,
output o_data_fifo_flg,
output o_data_read_flg,
output o_data_write_flg,
input i_usr_interrupt_stb,
input [31:0] i_usr_interrupt_value,
output [2:0] o_cplt_sts,
output o_unknown_tlp_stb,
output o_unexpected_end_stb,
//Ingress FIFO
input i_data_clk,
output o_ingress_fifo_rdy,
input i_ingress_fifo_act,
output [23:0] o_ingress_fifo_size,
input i_ingress_fifo_stb,
output [31:0] o_ingress_fifo_data,
output o_ingress_fifo_idle,
//Egress FIFO
output [1:0] o_egress_fifo_rdy,
input [1:0] i_egress_fifo_act,
output [23:0] o_egress_fifo_size,
input i_egress_fifo_stb,
input [31:0] i_egress_fifo_data
);
// local parameters
// registes/wires
// Control Signals
wire [1:0] c_in_wr_ready;
wire [1:0] c_in_wr_activate;
wire [23:0] c_in_wr_size;
wire c_in_wr_stb;
wire [31:0] c_in_wr_data;
wire c_out_rd_stb;
wire c_out_rd_ready;
wire c_out_rd_activate;
wire [23:0] c_out_rd_size;
wire [31:0] c_out_rd_data;
//Data
wire [1:0] d_in_wr_ready;
wire [1:0] d_in_wr_activate;
wire [23:0] d_in_wr_size;
wire d_in_wr_stb;
wire [31:0] d_in_wr_data;
wire d_out_rd_stb;
wire d_out_rd_ready;
wire d_out_rd_activate;
wire [23:0] d_out_rd_size;
wire [31:0] d_out_rd_data;
wire [31:0] m_axis_rx_tdata;
wire [3:0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire [21:0] m_axis_rx_tuser;
wire s_axis_tx_tready;
wire [31:0] s_axis_tx_tdata;
wire [3:0] s_axis_tx_tkeep;
wire [3:0] s_axis_tx_tuser;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
wire cfg_trn_pending;
wire cfg_interrupt_stb;
wire cfg_interrupt;
wire cfg_interrupt_rdy;
wire cfg_interrupt_assert;
wire [7:0] cfg_interrupt_do;
wire [7:0] cfg_interrupt_di;
wire [2:0] cfg_interrupt_mmenable;
wire cfg_interrupt_msienable;
wire [7:0] w_interrupt_msi_value;
wire w_interrupt_stb;
//XXX: Configuration Registers this should be read in by the controller
wire [31:0] w_write_a_addr;
wire [31:0] w_write_b_addr;
wire [31:0] w_read_a_addr;
wire [31:0] w_read_b_addr;
wire [31:0] w_status_addr;
wire [31:0] w_buffer_size;
wire [31:0] w_ping_value;
wire [31:0] w_dev_addr;
wire [1:0] w_update_buf;
wire w_update_buf_stb;
//XXX: Control SM Signals
wire [31:0] w_control_addr_base;
wire [31:0] w_cmd_data_count;
wire [31:0] w_cmd_data_address;
assign w_control_addr_base = o_bar_addr0;
//XXX: These signals are controlled by the buffer controller
//BUFFER Interface
wire w_buf_we;
wire [31:0] w_buf_addr;
wire [31:0] w_buf_dat;
wire s_axis_tx_discont;
wire s_axis_tx_stream;
wire s_axis_tx_err_fwd;
wire s_axis_tx_s6_not_used;
wire [31:0] cfg_do;
wire cfg_rd_wr_done;
wire [9:0] cfg_dwaddr;
wire cfg_rd_en;
wire cfg_enable;
wire tx_cfg_gnt;
wire rx_np_ok;
wire [6:0] w_bar_hit;
wire w_enable_config_read;
wire w_finished_config_read;
wire w_reg_write_stb;
//Command Strobe Signals
wire w_cmd_rst_stb;
wire w_cmd_wr_stb;
wire w_cmd_rd_stb;
wire w_cmd_ping_stb;
wire w_cmd_rd_cfg_stb;
wire w_cmd_unknown_stb;
//Command Flag Signals
wire w_cmd_flg_fifo_stb;
wire w_cmd_flg_sel_per_stb;
wire w_cmd_flg_sel_mem_stb;
wire w_cmd_flg_sel_dma_stb;
//Egress FIFO Signals
wire w_egress_enable;
wire w_egress_finished;
wire [7:0] w_egress_tlp_command;
wire [13:0] w_egress_tlp_flags;
wire [31:0] w_egress_tlp_address;
wire [15:0] w_egress_tlp_requester_id;
wire [7:0] w_egress_tag;
/****************************************************************************
* Egress FIFO Signals
****************************************************************************/
wire w_ctr_fifo_sel;
wire w_egress_fifo_rdy;
wire w_egress_fifo_act;
wire [23:0] w_egress_fifo_size;
wire [31:0] w_egress_fifo_data;
wire w_egress_fifo_stb;
wire w_e_ctr_fifo_rdy;
wire w_e_ctr_fifo_act;
wire [23:0] w_e_ctr_fifo_size;
wire [31:0] w_e_ctr_fifo_data;
wire w_e_ctr_fifo_stb;
wire w_e_per_fifo_rdy;
wire w_e_per_fifo_act;
wire [23:0] w_e_per_fifo_size;
wire [31:0] w_e_per_fifo_data;
wire w_e_per_fifo_stb;
wire w_e_mem_fifo_rdy;
wire w_e_mem_fifo_act;
wire [23:0] w_e_mem_fifo_size;
wire [31:0] w_e_mem_fifo_data;
wire w_e_mem_fifo_stb;
wire w_e_dma_fifo_rdy;
wire w_e_dma_fifo_act;
wire [23:0] w_e_dma_fifo_size;
wire [31:0] w_e_dma_fifo_data;
wire w_e_dma_fifo_stb;
wire [12:0] w_ibm_buf_offset;
wire w_bb_buf_we;
wire [10:0] w_bb_buf_addr;
wire [31:0] w_bb_buf_data;
wire [23:0] w_bb_data_count;
wire [1:0] w_i_data_fifo_rdy;
wire [1:0] w_o_data_fifo_act;
wire [23:0] w_o_data_fifo_size;
wire w_i_data_fifo_stb;
wire [31:0] w_i_data_fifo_data;
wire w_e_data_fifo_rdy;
wire w_e_data_fifo_act;
wire [23:0] w_e_data_fifo_size;
wire w_e_data_fifo_stb;
wire [31:0] w_e_data_fifo_data;
wire w_egress_inactive;
wire w_dat_fifo_sel;
wire [23:0] w_buf_max_size;
assign w_buf_max_size = 2**DATA_INGRESS_FIFO_DEPTH;
//Credit Manager
wire w_rcb_128B_sel;
wire [2:0] fc_sel;
wire [7:0] fc_nph;
wire [11:0] fc_npd;
wire [7:0] fc_ph;
wire [11:0] fc_pd;
wire [7:0] fc_cplh;
wire [11:0] fc_cpld;
wire w_pcie_ctr_fc_ready;
wire w_pcie_ctr_cmt_stb;
wire [9:0] w_pcie_ctr_dword_req_cnt;
wire w_pcie_ing_fc_rcv_stb;
wire [9:0] w_pcie_ing_fc_rcv_cnt;
//Buffer Manager
wire w_hst_buf_fin_stb;
wire [1:0] w_hst_buf_fin;
wire w_ctr_en;
wire w_ctr_mem_rd_req_stb;
wire w_ctr_dat_fin;
wire w_ctr_tag_rdy;
wire [7:0] w_ctr_tag;
wire [9:0] w_ctr_dword_size;
wire w_ctr_buf_sel;
wire w_ctr_idle;
wire [11:0] w_ctr_start_addr;
wire [7:0] w_ing_cplt_tag;
wire [6:0] w_ing_cplt_lwr_addr;
wire [1:0] w_bld_buf_en;
wire w_bld_buf_fin;
wire w_wr_fin;
wire w_rd_fin;
cross_clock_enable rd_fin_en (
.rst (o_pcie_reset ),
.in_en (i_read_fin ),
.out_clk (clk_62p5 ),
.out_en (w_rd_fin )
);
cross_clock_enable wr_fin_en (
.rst (o_pcie_reset ),
.in_en (i_write_fin ),
.out_clk (clk_62p5 ),
.out_en (w_wr_fin )
);
/****************************************************************************
* Interrupt State Machine Signals
****************************************************************************/
pcie_axi_bridge pcie_interface
//sim_pcie_axi_bridge pcie_interface
(
// PCI Express Fabric Interface
.pci_exp_txp (pci_exp_txp ),
.pci_exp_txn (pci_exp_txn ),
.pci_exp_rxp (pci_exp_rxp ),
.pci_exp_rxn (pci_exp_rxn ),
// Transaction (TRN) Interface
.user_lnk_up (user_lnk_up ),
// Tx
.s_axis_tx_tready (s_axis_tx_tready ),
.s_axis_tx_tdata (s_axis_tx_tdata ),
.s_axis_tx_tkeep (s_axis_tx_tkeep ),
.s_axis_tx_tuser (s_axis_tx_tuser ),
.s_axis_tx_tlast (s_axis_tx_tlast ),
.s_axis_tx_tvalid (s_axis_tx_tvalid ),
.tx_cfg_gnt (tx_cfg_gnt ),
// .user_enable_comm (user_enable_comm ),
// Rx
.m_axis_rx_tdata (m_axis_rx_tdata ),
.m_axis_rx_tkeep (m_axis_rx_tkeep ),
.m_axis_rx_tlast (m_axis_rx_tlast ),
.m_axis_rx_tvalid (m_axis_rx_tvalid ),
.m_axis_rx_tready (m_axis_rx_tready ),
.m_axis_rx_tuser (m_axis_rx_tuser ),
// output reg [21:0] m_axis_rx_tuser,
// input rx_np_ok,
.rx_np_ok (rx_np_ok ),
// Flow Control
.fc_sel (fc_sel ),
.fc_nph (fc_nph ),
.fc_npd (fc_npd ),
.fc_ph (fc_ph ),
.fc_pd (fc_pd ),
.fc_cplh (fc_cplh ),
.fc_cpld (fc_cpld ),
// Host Interface
.cfg_do (cfg_do ),
.cfg_rd_wr_done (cfg_rd_wr_done ),
.cfg_dwaddr (cfg_dwaddr ),
.cfg_rd_en (cfg_rd_en ),
// Configuration: Error
.cfg_err_ur (cfg_err_ur ),
.cfg_err_cor (cfg_err_cor ),
.cfg_err_ecrc (cfg_err_ecrc ),
.cfg_err_cpl_timeout (cfg_err_cpl_timeout ),
.cfg_err_cpl_abort (cfg_err_cpl_abort ),
.cfg_err_posted (cfg_err_posted ),
.cfg_err_locked (cfg_err_locked ),
.cfg_err_tlp_cpl_header (cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy (cfg_err_cpl_rdy ),
// Conifguration: Interrupt
.cfg_interrupt (cfg_interrupt ),
.cfg_interrupt_rdy (cfg_interrupt_rdy ),
.cfg_interrupt_assert (cfg_interrupt_assert ),
.cfg_interrupt_do (cfg_interrupt_do ),
.cfg_interrupt_di (cfg_interrupt_di ),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable ),
.cfg_interrupt_msienable (cfg_interrupt_msienable ),
// Configuration: Power Management
.cfg_turnoff_ok (cfg_turnoff_ok ),
.cfg_to_turnoff (cfg_to_turnoff ),
.cfg_pm_wake (cfg_pm_wake ),
//Core Controller
// Configuration: System/Status
.cfg_pcie_link_state (cfg_pcie_link_state ),
.cfg_trn_pending (cfg_trn_pending ), //XXX: Do I need to use cfg_trn_pending??
.cfg_dsn (SERIAL_NUMBER ),
.cfg_bus_number (cfg_bus_number ),
.cfg_device_number (cfg_device_number ),
.cfg_function_number (cfg_function_number ),
.cfg_status (cfg_status ),
.cfg_command (cfg_command ),
.cfg_dstatus (cfg_dstatus ),
.cfg_dcommand (cfg_dcommand ),
.cfg_lstatus (cfg_lstatus ),
.cfg_lcommand (cfg_lcommand ),
// System Interface
.sys_clk_p (gtp_clk_p ),
.sys_clk_n (gtp_clk_n ),
.sys_reset (i_pcie_reset ),
.user_clk_out (clk_62p5 ),
.user_reset_out (o_pcie_reset ),
.received_hot_reset (received_hot_reset ),
.pll_lock_detect (pll_lock_detect ),
.gtp_pll_lock_detect (gtp_pll_lock_detect ),
.gtp_reset_done (gtp_reset_done ),
.rx_elec_idle (rx_elec_idle ),
.rx_equalizer_ctrl (rx_equalizer_ctrl ),
.tx_diff_ctrl (tx_diff_ctrl ),
.tx_pre_emphasis (tx_pre_emphasis ),
.cfg_ltssm_state (cfg_ltssm_state ),
.tx_buf_av (tx_buf_av ),
.tx_err_drop (tx_err_drop ),
.o_bar_hit (w_bar_hit ),
.dbg_reg_detected_correctable (dbg_reg_detected_correctable ),
.dbg_reg_detected_fatal (dbg_reg_detected_fatal ),
.dbg_reg_detected_non_fatal (dbg_reg_detected_non_fatal ),
.dbg_reg_detected_unsupported (dbg_reg_detected_unsupported ),
.dbg_bad_dllp_status (dbg_bad_dllp_status ),
.dbg_bad_tlp_lcrc (dbg_bad_tlp_lcrc ),
.dbg_bad_tlp_seq_num (dbg_bad_tlp_seq_num ),
.dbg_bad_tlp_status (dbg_bad_tlp_status ),
.dbg_dl_protocol_status (dbg_dl_protocol_status ),
.dbg_fc_protocol_err_status (dbg_fc_protocol_err_status ),
.dbg_mlfrmd_length (dbg_mlfrmd_length ),
.dbg_mlfrmd_mps (dbg_mlfrmd_mps ),
.dbg_mlfrmd_tcvc (dbg_mlfrmd_tcvc ),
.dbg_mlfrmd_tlp_status (dbg_mlfrmd_tlp_status ),
.dbg_mlfrmd_unrec_type (dbg_mlfrmd_unrec_type ),
.dbg_poistlpstatus (dbg_poistlpstatus ),
.dbg_rcvr_overflow_status (dbg_rcvr_overflow_status ),
.dbg_rply_rollover_status (dbg_rply_rollover_status ),
.dbg_rply_timeout_status (dbg_rply_timeout_status ),
.dbg_ur_no_bar_hit (dbg_ur_no_bar_hit ),
.dbg_ur_pois_cfg_wr (dbg_ur_pois_cfg_wr ),
.dbg_ur_status (dbg_ur_status ),
.dbg_ur_unsup_msg (dbg_ur_unsup_msg )
);
/****************************************************************************
* Read the BAR Addresses from Config Space
****************************************************************************/
config_parser cfg (
.clk (clk_62p5 ),
.rst (o_pcie_reset ),
.i_en (w_enable_config_read ),
.o_finished (w_finished_config_read ),
.i_cfg_do (cfg_do ),
.i_cfg_rd_wr_done (cfg_rd_wr_done ),
.o_cfg_dwaddr (cfg_dwaddr ),
.o_cfg_rd_en (cfg_rd_en ),
.o_bar_addr0 (o_bar_addr0 ),
.o_bar_addr1 (o_bar_addr1 ),
.o_bar_addr2 (o_bar_addr2 ),
.o_bar_addr3 (o_bar_addr3 ),
.o_bar_addr4 (o_bar_addr4 ),
.o_bar_addr5 (o_bar_addr5 )
);
buffer_builder #(
.MEM_DEPTH (11 ), //8K Buffer
.DATA_WIDTH (32 )
) bb (
.mem_clk (clk_62p5 ),
.rst (o_pcie_reset ),
.i_ppfifo_wr_en (w_bld_buf_en ),
.o_ppfifo_wr_fin (w_bld_buf_fin ),
.i_bram_we (w_bb_buf_we ),
.i_bram_addr (w_bb_buf_addr ),
.i_bram_din (w_bb_buf_data ),
.ppfifo_clk (clk_62p5 ),
.i_data_count (w_bb_data_count ),
.i_write_ready (w_i_data_fifo_rdy ),
.o_write_activate (w_o_data_fifo_act ),
.i_write_size (w_o_data_fifo_size ),
.o_write_stb (w_i_data_fifo_stb ),
.o_write_data (w_i_data_fifo_data )
);
credit_manager cm (
.clk (clk_62p5 ),
.rst (o_pcie_reset ),
//Credits
.o_fc_sel (fc_sel ),
.i_rcb_sel (w_rcb_128B_sel ),
.i_fc_cplh (fc_cplh ),
.i_fc_cpld (fc_cpld ),
//PCIE Control Interface
.o_ready (w_pcie_ctr_fc_ready ),
.i_cmt_stb (w_pcie_ctr_cmt_stb ),
.i_dword_req_count (w_pcie_ctr_dword_req_cnt ),
//Completion Receive Size
.i_rcv_stb (w_pcie_ing_fc_rcv_stb ),
.i_dword_rcv_count (w_pcie_ing_fc_rcv_cnt )
);
ingress_buffer_manager buf_man (
.clk (clk_62p5 ),
.rst (o_pcie_reset ),
//Host Interface
.i_hst_buf_rdy_stb (w_update_buf_stb ),
.i_hst_buf_rdy (w_update_buf ),
.o_hst_buf_fin_stb (w_hst_buf_fin_stb ),
.o_hst_buf_fin (w_hst_buf_fin ),
//PCIE Control Interface
.i_ctr_en (w_ctr_en ),
.i_ctr_mem_rd_req_stb (w_ctr_mem_rd_req_stb ),
.i_ctr_dat_fin (w_ctr_dat_fin ),
.o_ctr_tag_rdy (w_ctr_tag_rdy ),
.o_ctr_tag (w_ctr_tag ),
.o_ctr_dword_size (w_ctr_dword_size ),
.o_ctr_start_addr (w_ctr_start_addr ),
.o_ctr_buf_sel (w_ctr_buf_sel ),
.o_ctr_idle (w_ctr_idle ),
//PCIE Ingress Interface
.i_ing_cplt_stb (w_pcie_ing_fc_rcv_stb ),
.i_ing_cplt_tag (w_ing_cplt_tag ),
.i_ing_cplt_pkt_cnt (w_pcie_ing_fc_rcv_cnt ),
.i_ing_cplt_lwr_addr (w_ing_cplt_lwr_addr ),
//Buffer Block Interface
.o_bld_mem_addr (w_ibm_buf_offset ),
.o_bld_buf_en (w_bld_buf_en ),
.i_bld_buf_fin (w_bld_buf_fin ),
.o_dbg_tag_ingress_fin (dbg_tag_ingress_fin ),
.o_dbg_tag_en (dbg_tag_en ),
.o_dbg_reenable_stb (o_dbg_reenable_stb ),
.o_dbg_reenable_nzero_stb (o_dbg_reenable_nzero_stb )
);
pcie_control controller (
.clk (clk_62p5 ),
.rst (o_pcie_reset ),
//Configuration Values
.i_pcie_bus_num (cfg_bus_number ),
.i_pcie_dev_num (cfg_device_number ),
.i_pcie_fun_num (cfg_function_number ),
//Ingress Machine Interface
.i_write_a_addr (w_write_a_addr ),
.i_write_b_addr (w_write_b_addr ),
.i_read_a_addr (w_read_a_addr ),
.i_read_b_addr (w_read_b_addr ),
.i_status_addr (w_status_addr ),
.i_buffer_size (w_buffer_size ),
.i_ping_value (w_ping_value ),
.i_dev_addr (w_dev_addr ),
.i_update_buf (w_update_buf ),
.i_update_buf_stb (w_update_buf_stb ),
.i_reg_write_stb (w_reg_write_stb ),
//.i_device_select (w_device_select ),
.i_cmd_rst_stb (w_cmd_rst_stb ),
.i_cmd_wr_stb (w_cmd_wr_stb ),
.i_cmd_rd_stb (w_cmd_rd_stb ),
.i_cmd_ping_stb (w_cmd_ping_stb ),
.i_cmd_rd_cfg_stb (w_cmd_rd_cfg_stb ),
.i_cmd_unknown (w_cmd_unknown_stb ),
.i_cmd_flg_fifo (w_cmd_flg_fifo_stb ),
.i_cmd_flg_sel_periph (w_cmd_flg_sel_per_stb ),
.i_cmd_flg_sel_memory (w_cmd_flg_sel_mem_stb ),
.i_cmd_flg_sel_dma (w_cmd_flg_sel_dma_stb ),
.i_cmd_data_count (w_cmd_data_count ),
.i_cmd_data_address (w_cmd_data_address ),
.o_ctr_sel (w_ctr_fifo_sel ),
//User Interface
.o_per_sel (o_per_fifo_sel ),
.o_mem_sel (o_mem_fifo_sel ),
.o_dma_sel (o_dma_fifo_sel ),
//.i_write_fin (i_write_fin ),
.i_write_fin (w_wr_fin ),
// .i_read_fin (i_read_fin & w_egress_inactive ),
.i_read_fin (w_rd_fin & w_egress_inactive ),
.o_data_fifo_sel (w_dat_fifo_sel ),
.i_interrupt_stb (i_usr_interrupt_stb ),
.i_interrupt_value (i_usr_interrupt_value ),
.o_data_size (o_data_size ),
.o_data_address (o_data_address ),
.o_data_fifo_flg (o_data_fifo_flg ),
.o_data_read_flg (o_data_read_flg ),
.o_data_write_flg (o_data_write_flg ),
//Peripheral/Memory/DMA Egress FIFO Interface
.i_e_fifo_rdy (w_egress_fifo_rdy ),
.i_e_fifo_size (w_egress_fifo_size ),
//Egress Controller Interface
.o_egress_enable (w_egress_enable ),
.i_egress_finished (w_egress_finished ),
.o_egress_tlp_command (w_egress_tlp_command ),
.o_egress_tlp_flags (w_egress_tlp_flags ),
.o_egress_tlp_address (w_egress_tlp_address ),
.o_egress_tlp_requester_id (w_egress_tlp_requester_id ),
.o_egress_tag (w_egress_tag ),
.o_interrupt_msi_value (w_interrupt_msi_value ),
// .o_interrupt_stb (w_interrupt_stb ),
.o_interrupt_send_en (cfg_interrupt ),
.i_interrupt_send_rdy (cfg_interrupt_rdy ),
.o_egress_fifo_rdy (w_e_ctr_fifo_rdy ),
.i_egress_fifo_act (w_e_ctr_fifo_act ),
.o_egress_fifo_size (w_e_ctr_fifo_size ),
.i_egress_fifo_stb (w_e_ctr_fifo_stb ),
.o_egress_fifo_data (w_e_ctr_fifo_data ),
//Ingress Buffer Interface
.i_ibm_buf_fin_stb (w_hst_buf_fin_stb ),
.i_ibm_buf_fin (w_hst_buf_fin ),
.o_ibm_en (w_ctr_en ),
.o_ibm_req_stb (w_ctr_mem_rd_req_stb ),
.o_ibm_dat_fin (w_ctr_dat_fin ),
.i_ibm_tag_rdy (w_ctr_tag_rdy ),
.i_ibm_tag (w_ctr_tag ),
.i_ibm_dword_cnt (w_ctr_dword_size ),
.i_ibm_start_addr (w_ctr_start_addr ),
.i_ibm_buf_sel (w_ctr_buf_sel ),
.i_ibm_idle (w_ctr_idle ),
.i_buf_max_size (w_buf_max_size ),
.o_buf_data_count (w_bb_data_count ),
//System Interface
.o_sys_rst (o_sys_rst ),
.i_fc_ready (w_pcie_ctr_fc_ready ),
.o_fc_cmt_stb (w_pcie_ctr_cmt_stb ),
.o_dword_req_cnt (w_pcie_ctr_dword_req_cnt ),
//Configuration Reader Interface
.o_cfg_read_exec (o_cfg_read_exec ),
.o_cfg_sm_state (o_cfg_sm_state ),
.o_sm_state (o_sm_state )
);
//XXX: Need to think about resets
/****************************************************************************
* Single IN/OUT FIFO Solution (This Can Change in the future):
* Instead of dedicating unique FIFOs for each bus, I can just do one
* FIFO. This will reduce the size of the core at the cost of
* a certain amount of time it will take to fill up the FIFOs
****************************************************************************/
//INGRESS FIFO
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (DATA_INGRESS_FIFO_DEPTH ) // 1024 32-bit values (4096 Bytes)
) i_data_fifo (
.reset (o_pcie_reset || rst ),
//Write Side
.write_clock (clk_62p5 ),
.write_ready (w_i_data_fifo_rdy ),
.write_activate (w_o_data_fifo_act ),
.write_fifo_size (w_o_data_fifo_size ),
.write_strobe (w_i_data_fifo_stb ),
.write_data (w_i_data_fifo_data ),
//Read Side
.read_clock (i_data_clk ),
.read_ready (o_ingress_fifo_rdy ),
.read_activate (i_ingress_fifo_act ),
.read_count (o_ingress_fifo_size ),
.read_strobe (i_ingress_fifo_stb ),
.read_data (o_ingress_fifo_data ),
.inactive (o_ingress_fifo_idle )
);
//EGRESS FIFOs
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (DATA_EGRESS_FIFO_DEPTH ) // 64 32-bit values (256 Bytes)
) e_data_fifo (
.reset (o_pcie_reset || rst ),
//Write Side
.write_clock (i_data_clk ),
.write_ready (o_egress_fifo_rdy ),
.write_activate (i_egress_fifo_act ),
.write_fifo_size (o_egress_fifo_size ),
.write_strobe (i_egress_fifo_stb ),
.write_data (i_egress_fifo_data ),
//Read Side
.read_clock (clk_62p5 ),
.read_ready (w_e_data_fifo_rdy ),
.read_activate (w_e_data_fifo_act ),
.read_count (w_e_data_fifo_size ),
.read_strobe (w_e_data_fifo_stb ),
.read_data (w_e_data_fifo_data ),
.inactive (w_egress_inactive )
);
pcie_ingress ingress (
.clk (clk_62p5 ),
.rst (o_pcie_reset ),
//AXI Stream Host 2 Device
.o_axi_ingress_ready (m_axis_rx_tready ),
.i_axi_ingress_data (m_axis_rx_tdata ),
.i_axi_ingress_keep (m_axis_rx_tkeep ),
.i_axi_ingress_last (m_axis_rx_tlast ),
.i_axi_ingress_valid (m_axis_rx_tvalid ),
//Configuration
.o_reg_write_stb (w_reg_write_stb ), //Strobes when new register data is detected
//Parsed out Register Values
.o_write_a_addr (w_write_a_addr ),
.o_write_b_addr (w_write_b_addr ),
.o_read_a_addr (w_read_a_addr ),
.o_read_b_addr (w_read_b_addr ),
.o_status_addr (w_status_addr ),
.o_buffer_size (w_buffer_size ),
.o_ping_value (w_ping_value ),
.o_dev_addr (w_dev_addr ),
.o_update_buf (w_update_buf ),
.o_update_buf_stb (w_update_buf_stb ),
//Command Interface
//.o_device_select (w_device_select ),
.o_cmd_rst_stb (w_cmd_rst_stb ), //Strobe when a reset command is detected
.o_cmd_wr_stb (w_cmd_wr_stb ), //Strobes when a write request is detected
.o_cmd_rd_stb (w_cmd_rd_stb ), //Strobes when a read request is detected
.o_cmd_ping_stb (w_cmd_ping_stb ), //Strobes when a ping request is detected
.o_cmd_rd_cfg_stb (w_cmd_rd_cfg_stb ), //Strobes when a read configuration id detected
.o_cmd_unknown_stb (w_cmd_unknown_stb ),
.o_cmd_flg_fifo_stb (w_cmd_flg_fifo_stb ), //Flag indicating that transfer shouldn't auto increment addr
.o_cmd_flg_sel_per_stb (w_cmd_flg_sel_per_stb ),
.o_cmd_flg_sel_mem_stb (w_cmd_flg_sel_mem_stb ),
.o_cmd_flg_sel_dma_stb (w_cmd_flg_sel_dma_stb ),
//Input Configuration Registers from either PCIE_A1 or controller
.i_bar_hit (o_bar_hit ),
//Local Address of where BAR0 is located (Used to do address translation)
.i_control_addr_base (w_control_addr_base ),
.o_enable_config_read (w_enable_config_read ),
.i_finished_config_read (w_finished_config_read ),
//When a command is detected the size of the transaction is reported here
.o_cmd_data_count (w_cmd_data_count ),
.o_cmd_data_address (w_cmd_data_address ),
//Flow Control
.o_cplt_pkt_stb (w_pcie_ing_fc_rcv_stb ),
.o_cplt_pkt_cnt (w_pcie_ing_fc_rcv_cnt ),
.o_cplt_sts (o_cplt_sts ),
.o_unknown_tlp_stb (o_unknown_tlp_stb ),
.o_unexpected_end_stb (o_unexpected_end_stb ),
.o_cplt_pkt_tag (w_ing_cplt_tag ),
.o_cplt_pkt_lwr_addr (w_ing_cplt_lwr_addr ),
//Buffer interface, the buffer controller will manage this
.i_buf_offset (w_ibm_buf_offset ),
.o_buf_we (w_bb_buf_we ),
.o_buf_addr (w_bb_buf_addr ),
.o_buf_data (w_bb_buf_data ),
.o_state (o_ingress_state ),
.o_ingress_count (o_ingress_count ),
.o_ingress_ri_count (o_ingress_ri_count ),
.o_ingress_ci_count (o_ingress_ci_count ),
.o_ingress_cmplt_count (o_ingress_cmplt_count ),
.o_ingress_addr (o_ingress_addr )
);
pcie_egress egress (
.clk (clk_62p5 ),
.rst (o_pcie_reset ),
.i_enable (w_egress_enable ),
.o_finished (w_egress_finished ),
.i_command (w_egress_tlp_command ),
.i_flags (w_egress_tlp_flags ),
.i_address (w_egress_tlp_address ),
.i_requester_id (w_egress_tlp_requester_id ),
.i_tag (w_egress_tag ),
.i_req_dword_cnt (w_pcie_ctr_dword_req_cnt ),
//AXI Interface
.i_axi_egress_ready (s_axis_tx_tready ),
.o_axi_egress_data (s_axis_tx_tdata ),
.o_axi_egress_keep (s_axis_tx_tkeep ),
.o_axi_egress_last (s_axis_tx_tlast ),
.o_axi_egress_valid (s_axis_tx_tvalid ),
//Data FIFO Interface
.i_fifo_rdy (w_egress_fifo_rdy ),
.o_fifo_act (w_egress_fifo_act ),
.i_fifo_size (w_egress_fifo_size ),
.i_fifo_data (w_egress_fifo_data ),
.o_fifo_stb (w_egress_fifo_stb ),
.dbg_ready_drop (dbg_ready_drop )
);
/****************************************************************************
* FIFO Multiplexer
****************************************************************************/
assign w_egress_fifo_rdy = (w_ctr_fifo_sel) ? w_e_ctr_fifo_rdy:
(w_dat_fifo_sel) ? w_e_data_fifo_rdy:
1'b0;
assign w_egress_fifo_size = (w_ctr_fifo_sel) ? w_e_ctr_fifo_size:
(w_dat_fifo_sel) ? w_e_data_fifo_size:
24'h0;
assign w_egress_fifo_data = (w_ctr_fifo_sel) ? w_e_ctr_fifo_data:
(w_dat_fifo_sel) ? w_e_data_fifo_data:
32'h00;
assign w_e_ctr_fifo_act = (w_ctr_fifo_sel) ? w_egress_fifo_act:
1'b0;
assign w_e_ctr_fifo_stb = (w_ctr_fifo_sel) ? w_egress_fifo_stb:
1'b0;
assign w_e_data_fifo_act = (w_dat_fifo_sel) ? w_egress_fifo_act:
1'b0;
assign w_e_data_fifo_stb = (w_dat_fifo_sel) ? w_egress_fifo_stb:
1'b0;
//assign w_dat_fifo_sel = (o_per_fifo_sel || o_mem_fifo_sel || o_dma_fifo_sel);
/****************************************************************************
* Temporary Debug Signals
****************************************************************************/
//This used to go to the wishbone slave device
//Need to create a flow controller
assign o_receive_axi_ready = 0;
/****************************************************************************
* AXI Signals from the user to the PCIE_A1 Core
****************************************************************************/
assign s_axis_tx_discont = 0;
assign s_axis_tx_stream = 0;
assign s_axis_tx_err_fwd = 0;
assign s_axis_tx_s6_not_used = 0;
assign s_axis_tx_tuser = {s_axis_tx_discont,
s_axis_tx_stream,
s_axis_tx_err_fwd,
s_axis_tx_s6_not_used};
//Use this BAR Hist because it is buffered with the AXI transaction
assign o_bar_hit = m_axis_rx_tuser[8:2];
assign dbg_rerrfwd = m_axis_rx_tuser[1];
/****************************************************************************
* The Following Signals Need to be integrated into the core
****************************************************************************/
//XXX: THIS SIGNAL MIGHT NEED TO BE SET HIGH WHEN AN UPSTREAM DATA REQUEST IS SENT
assign cfg_trn_pending = 1'b0;
//Allow PCIE_A1 Core to have priority over transactions
assign tx_cfg_gnt = 1'b1;
//Allow PCIE_A1 Core to send non-posted transactions to the user application (Flow Control from user app)
assign rx_np_ok = 1'b1;
/****************************************************************************
* Ingress Buffer Manager
****************************************************************************/
//XXX: THIS IS TEMPORARY BEFORE BUFFER MANAGER IS DONE
/****************************************************************************
* Add the configuration state machine controller to a command, the user
* should be able to send an initialization signal from the host, this will
* Trigger the configuration controller to read the internal address register
* of the bars... is this needed anymore? The host will only write small
* transactions to configure the state machine, there doesn't seem to be a
* reason for the configuration state machine any more
****************************************************************************/
//assign cfg_interrupt_di = i_interrupt_channel;
//assign cfg_interrupt_stb = i_interrupt_stb;
assign cfg_interrupt_di = w_interrupt_msi_value;
//assign cfg_interrupt_stb = w_interrupt_stb;
assign w_rcb_128B_sel = cfg_lcommand[3];
/****************************************************************************
* Interrupt State Machine
****************************************************************************/
//asynchronous logic
//synchronous logic
localparam IDLE = 0;
localparam SEND_INTERRUPT = 1;
reg int_state = IDLE;
/*
always @ (posedge clk_62p5) begin
if (o_pcie_reset) begin
cfg_interrupt <= 0;
int_state <= IDLE;
end
else begin
case (int_state)
IDLE: begin
cfg_interrupt <= 0;
if (cfg_interrupt_stb)
int_state <= SEND_INTERRUPT;
end
SEND_INTERRUPT: begin
cfg_interrupt <= 1;
if (cfg_interrupt_rdy) begin
int_state <= IDLE;
cfg_interrupt <= 0;
end
end
endcase
end
end
*/
endmodule
|
`timescale 1ps / 1ps
`default_nettype none
module tb (
input wire FCLK_IN,
//full speed
inout wire [7:0] BUS_DATA,
input wire [15:0] ADD,
input wire RD_B,
input wire WR_B,
//high speed
inout wire [7:0] FD,
input wire FREAD,
input wire FSTROBE,
input wire FMODE
);
//SRAM
wire [19:0] SRAM_A;
wire [15:0] SRAM_IO;
wire SRAM_BHE_B;
wire SRAM_BLE_B;
wire SRAM_CE1_B;
wire SRAM_OE_B;
wire SRAM_WE_B;
wire [4:0] LED;
wire SDA;
wire SCL;
sram_test dut(.FCLK_IN(FCLK_IN),
.BUS_DATA(BUS_DATA), .ADD(ADD), .RD_B(RD_B), .WR_B(WR_B),
.FD(FD), .FREAD(FREAD), .FSTROBE(FSTROBE), .FMODE(FMODE),
.SRAM_A(SRAM_A), .SRAM_IO(SRAM_IO), .SRAM_BHE_B(SRAM_BHE_B), .SRAM_BLE_B(SRAM_BLE_B), .SRAM_CE1_B(SRAM_CE1_B), .SRAM_OE_B(SRAM_OE_B), .SRAM_WE_B(SRAM_WE_B),
.LED(LED), .SDA(SDA), .SCL(SCL) );
defparam dut.i_out_fifo.DEPTH = 21'h100;
/// SRAM
reg [15:0] sram [1048576-1:0];
always@(negedge SRAM_WE_B)
sram[SRAM_A] <= SRAM_IO;
assign SRAM_IO = !SRAM_OE_B ? sram[SRAM_A] : 16'hzzzz;
initial begin
$dumpfile("sram_test.vcd");
$dumpvars(0);
end
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "XILINX"
)
(
/*
* Clock: 156.25MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* Ethernet: QSFP28
*/
input wire qsfp_tx_clk_1,
input wire qsfp_tx_rst_1,
output wire [63:0] qsfp_txd_1,
output wire [7:0] qsfp_txc_1,
input wire qsfp_rx_clk_1,
input wire qsfp_rx_rst_1,
input wire [63:0] qsfp_rxd_1,
input wire [7:0] qsfp_rxc_1,
input wire qsfp_tx_clk_2,
input wire qsfp_tx_rst_2,
output wire [63:0] qsfp_txd_2,
output wire [7:0] qsfp_txc_2,
input wire qsfp_rx_clk_2,
input wire qsfp_rx_rst_2,
input wire [63:0] qsfp_rxd_2,
input wire [7:0] qsfp_rxc_2,
input wire qsfp_tx_clk_3,
input wire qsfp_tx_rst_3,
output wire [63:0] qsfp_txd_3,
output wire [7:0] qsfp_txc_3,
input wire qsfp_rx_clk_3,
input wire qsfp_rx_rst_3,
input wire [63:0] qsfp_rxd_3,
input wire [7:0] qsfp_rxc_3,
input wire qsfp_tx_clk_4,
input wire qsfp_tx_rst_4,
output wire [63:0] qsfp_txd_4,
output wire [7:0] qsfp_txc_4,
input wire qsfp_rx_clk_4,
input wire qsfp_rx_rst_4,
input wire [63:0] qsfp_rxd_4,
input wire [7:0] qsfp_rxc_4,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_gmii_clk,
input wire phy_gmii_rst,
input wire phy_gmii_clk_en,
input wire [7:0] phy_gmii_rxd,
input wire phy_gmii_rx_dv,
input wire phy_gmii_rx_er,
output wire [7:0] phy_gmii_txd,
output wire phy_gmii_tx_en,
output wire phy_gmii_tx_er,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// AXI between MAC and Ethernet modules
wire [63:0] mac_rx_axis_tdata;
wire [7:0] mac_rx_axis_tkeep;
wire mac_rx_axis_tvalid;
wire mac_rx_axis_tready;
wire mac_rx_axis_tlast;
wire mac_rx_axis_tuser;
wire [63:0] mac_tx_axis_tdata;
wire [7:0] mac_tx_axis_tkeep;
wire mac_tx_axis_tvalid;
wire mac_tx_axis_tready;
wire mac_tx_axis_tlast;
wire mac_tx_axis_tuser;
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [63:0] rx_fifo_udp_payload_axis_tdata;
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [63:0] tx_fifo_udp_payload_axis_tdata;
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
valid_last <= tx_udp_payload_axis_tvalid;
if (tx_udp_payload_axis_tvalid && !valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
end
end
end
//assign led = sw;
assign led = led_reg;
assign phy_reset_n = !rst;
assign qsfp_txd_2 = 64'h0707070707070707;
assign qsfp_txc_2 = 8'hff;
assign qsfp_txd_3 = 64'h0707070707070707;
assign qsfp_txc_3 = 8'hff;
assign qsfp_txd_4 = 64'h0707070707070707;
assign qsfp_txc_4 = 8'hff;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(qsfp_rx_clk_1),
.rx_rst(qsfp_rx_rst_1),
.tx_clk(qsfp_tx_clk_1),
.tx_rst(qsfp_tx_rst_1),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(mac_tx_axis_tdata),
.tx_axis_tkeep(mac_tx_axis_tkeep),
.tx_axis_tvalid(mac_tx_axis_tvalid),
.tx_axis_tready(mac_tx_axis_tready),
.tx_axis_tlast(mac_tx_axis_tlast),
.tx_axis_tuser(mac_tx_axis_tuser),
.rx_axis_tdata(mac_rx_axis_tdata),
.rx_axis_tkeep(mac_rx_axis_tkeep),
.rx_axis_tvalid(mac_rx_axis_tvalid),
.rx_axis_tready(mac_rx_axis_tready),
.rx_axis_tlast(mac_rx_axis_tlast),
.rx_axis_tuser(mac_rx_axis_tuser),
.xgmii_rxd(qsfp_rxd_1),
.xgmii_rxc(qsfp_rxc_1),
.xgmii_txd(qsfp_txd_1),
.xgmii_txc(qsfp_txc_1),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
);
// 1G interface for debugging
wire [7:0] gig_rx_axis_tdata;
wire gig_rx_axis_tvalid;
wire gig_rx_axis_tready;
wire gig_rx_axis_tlast;
wire gig_rx_axis_tuser;
wire [7:0] gig_tx_axis_tdata;
wire gig_tx_axis_tvalid;
wire gig_tx_axis_tready;
wire gig_tx_axis_tlast;
wire gig_tx_axis_tuser;
wire [63:0] gig_rx_axis_tdata_64;
wire [7:0] gig_rx_axis_tkeep_64;
wire gig_rx_axis_tvalid_64;
wire gig_rx_axis_tready_64;
wire gig_rx_axis_tlast_64;
wire gig_rx_axis_tuser_64;
wire [63:0] gig_tx_axis_tdata_64;
wire [7:0] gig_tx_axis_tkeep_64;
wire gig_tx_axis_tvalid_64;
wire gig_tx_axis_tready_64;
wire gig_tx_axis_tlast_64;
wire gig_tx_axis_tuser_64;
eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_1g_inst (
.rx_clk(phy_gmii_clk),
.rx_rst(phy_gmii_rst),
.tx_clk(phy_gmii_clk),
.tx_rst(phy_gmii_rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(gig_tx_axis_tdata),
.tx_axis_tvalid(gig_tx_axis_tvalid),
.tx_axis_tready(gig_tx_axis_tready),
.tx_axis_tlast(gig_tx_axis_tlast),
.tx_axis_tuser(gig_tx_axis_tuser),
.rx_axis_tdata(gig_rx_axis_tdata),
.rx_axis_tvalid(gig_rx_axis_tvalid),
.rx_axis_tready(gig_rx_axis_tready),
.rx_axis_tlast(gig_rx_axis_tlast),
.rx_axis_tuser(gig_rx_axis_tuser),
.gmii_rxd(phy_gmii_rxd),
.gmii_rx_dv(phy_gmii_rx_dv),
.gmii_rx_er(phy_gmii_rx_er),
.gmii_txd(phy_gmii_txd),
.gmii_tx_en(phy_gmii_tx_en),
.gmii_tx_er(phy_gmii_tx_er),
.rx_clk_enable(phy_gmii_clk_en),
.tx_clk_enable(phy_gmii_clk_en),
.rx_mii_select(1'b0),
.tx_mii_select(1'b0),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
);
axis_adapter #(
.S_DATA_WIDTH(8),
.M_DATA_WIDTH(64),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
gig_rx_axis_adapter_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(gig_rx_axis_tdata),
.s_axis_tkeep(1'b1),
.s_axis_tvalid(gig_rx_axis_tvalid),
.s_axis_tready(gig_rx_axis_tready),
.s_axis_tlast(gig_rx_axis_tlast),
.s_axis_tuser(gig_rx_axis_tuser),
// AXI output
.m_axis_tdata(gig_rx_axis_tdata_64),
.m_axis_tkeep(gig_rx_axis_tkeep_64),
.m_axis_tvalid(gig_rx_axis_tvalid_64),
.m_axis_tready(gig_rx_axis_tready_64),
.m_axis_tlast(gig_rx_axis_tlast_64),
.m_axis_tuser(gig_rx_axis_tuser_64)
);
axis_adapter #(
.S_DATA_WIDTH(64),
.M_DATA_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
)
gig_tx_axis_adapter_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(gig_tx_axis_tdata_64),
.s_axis_tkeep(gig_tx_axis_tkeep_64),
.s_axis_tvalid(gig_tx_axis_tvalid_64),
.s_axis_tready(gig_tx_axis_tready_64),
.s_axis_tlast(gig_tx_axis_tlast_64),
.s_axis_tuser(gig_tx_axis_tuser_64),
// AXI output
.m_axis_tdata(gig_tx_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(gig_tx_axis_tvalid),
.m_axis_tready(gig_tx_axis_tready),
.m_axis_tlast(gig_tx_axis_tlast),
.m_axis_tuser(gig_tx_axis_tuser)
);
// tap port mux logic
// sw[3] enable
// sw[2] select 0 rx, 1 tx
reg [1:0] mac_rx_tdest;
reg [1:0] tx_tdest;
reg [1:0] gig_rx_tdest;
always @* begin
if (sw[3]) begin
if (sw[2]) begin
// Tap on TX path
// MAC RX out -> stack RX in
// stack TX out -> gig TX in
// gig RX out -> MAC TX in
mac_rx_tdest = 2'd1;
tx_tdest = 2'd2;
gig_rx_tdest = 2'd0;
end else begin
// Tap on RX path
// MAC RX out -> gig TX in
// stack TX out -> MAC TX in
// gig RX out -> stack RX in
mac_rx_tdest = 2'd2;
tx_tdest = 2'd0;
gig_rx_tdest = 2'd1;
end
end else begin
// Tap disabled
// MAC RX out -> stack RX in
// stack TX out -> MAC TX in
// gig RX out -> blackhole
mac_rx_tdest = 2'd1;
tx_tdest = 2'd0;
gig_rx_tdest = 2'd3;
end
end
axis_switch #(
.S_COUNT(3),
.M_COUNT(3),
.DATA_WIDTH(64),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_WIDTH(2),
.USER_ENABLE(1),
.USER_WIDTH(1),
.M_BASE({2'd2, 2'd1, 2'd0}),
.M_TOP({2'd2, 2'd1, 2'd0}),
.M_CONNECT({3{3'b111}}),
.S_REG_TYPE(0),
.M_REG_TYPE(2),
.ARB_TYPE_ROUND_ROBIN(0),
.ARB_LSB_HIGH_PRIORITY(1)
)
axis_switch_inst (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata({ gig_rx_axis_tdata_64, tx_axis_tdata, mac_rx_axis_tdata}),
.s_axis_tkeep({ gig_rx_axis_tkeep_64, tx_axis_tkeep, mac_rx_axis_tkeep}),
.s_axis_tvalid({gig_rx_axis_tvalid_64, tx_axis_tvalid, mac_rx_axis_tvalid}),
.s_axis_tready({gig_rx_axis_tready_64, tx_axis_tready, mac_rx_axis_tready}),
.s_axis_tlast({ gig_rx_axis_tlast_64, tx_axis_tlast, mac_rx_axis_tlast}),
.s_axis_tid(0),
.s_axis_tdest({ gig_rx_tdest, tx_tdest, mac_rx_tdest}),
.s_axis_tuser({ gig_rx_axis_tuser_64, tx_axis_tuser, mac_rx_axis_tuser}),
// AXI outputs
.m_axis_tdata({ gig_tx_axis_tdata_64, rx_axis_tdata, mac_tx_axis_tdata}),
.m_axis_tkeep({ gig_tx_axis_tkeep_64, rx_axis_tkeep, mac_tx_axis_tkeep}),
.m_axis_tvalid({gig_tx_axis_tvalid_64, rx_axis_tvalid, mac_tx_axis_tvalid}),
.m_axis_tready({gig_tx_axis_tready_64, rx_axis_tready, mac_tx_axis_tready}),
.m_axis_tlast({ gig_tx_axis_tlast_64, rx_axis_tlast, mac_tx_axis_tlast}),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser({ gig_tx_axis_tuser_64, rx_axis_tuser, mac_tx_axis_tuser})
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
|
(** * References: Typing Mutable References *)
Require Export Smallstep.
(** So far, we have considered a variety of _pure_ language features,
including functional abstraction, basic types such as numbers and
booleans, and structured types such as records and variants. These
features form the backbone of most programming languages -- including
purely functional languages such as Haskell, "mostly functional"
languages such as ML, imperative languages such as C, and
object-oriented languages such as Java.
Most practical programming languages also include various _impure_
features that cannot be described in the simple semantic framework
we have used so far. In particular, besides just yielding
results, evaluation of terms in these languages may assign to
mutable variables (reference cells, arrays, mutable record fields,
etc.), perform input and output to files, displays, or network
connections, make non-local transfers of control via exceptions,
jumps, or continuations, engage in inter-process synchronization
and communication, and so on. In the literature on programming
languages, such "side effects" of computation are more generally
referred to as _computational effects_.
In this chapter, we'll see how one sort of computational
effect -- mutable references -- can be added to the calculi we have
studied. The main extension will be dealing explicitly with a
_store_ (or _heap_). This extension is straightforward to define;
the most interesting part is the refinement we need to make to the
statement of the type preservation theorem. *)
(* ###################################################################### *)
(** * Definitions *)
(** Pretty much every programming language provides some form of
assignment operation that changes the contents of a previously
allocated piece of storage. (Coq's internal language is a rare
exception!)
In some languages -- notably ML and its relatives -- the
mechanisms for name-binding and those for assignment are kept
separate. We can have a variable [x] whose _value_ is the number
[5], or we can have a variable [y] whose value is a
_reference_ (or _pointer_) to a mutable cell whose current
contents is [5]. These are different things, and the difference
is visible to the programmer. We can add [x] to another number,
but not assign to it. We can use [y] directly to assign a new
value to the cell that it points to (by writing [y:=84]), but we
cannot use it directly as an argument to an operation like [+].
Instead, we must explicitly _dereference_ it, writing [!y] to
obtain its current contents.
In most other languages -- in particular, in all members of the C
family, including Java -- _every_ variable name refers to a mutable
cell, and the operation of dereferencing a variable to obtain its
current contents is implicit.
For purposes of formal study, it is useful to keep these
mechanisms separate. The development in this chapter will closely
follow ML's model. Applying the lessons learned here to C-like
languages is a straightforward matter of collapsing some
distinctions and rendering some operations such as dereferencing
implicit instead of explicit.
In this chapter, we study adding mutable references to the
simply-typed lambda calculus with natural numbers. *)
(* ###################################################################### *)
(** * Syntax *)
Module STLCRef.
(** The basic operations on references are _allocation_,
_dereferencing_, and _assignment_.
- To allocate a reference, we use the [ref] operator, providing
an initial value for the new cell. For example, [ref 5]
creates a new cell containing the value [5], and evaluates to
a reference to that cell.
- To read the current value of this cell, we use the
dereferencing operator [!]; for example, [!(ref 5)] evaluates
to [5].
- To change the value stored in a cell, we use the assignment
operator. If [r] is a reference, [r := 7] will store the
value [7] in the cell referenced by [r]. However, [r := 7]
evaluates to the trivial value [unit]; it exists only to have
the _side effect_ of modifying the contents of a cell. *)
(* ################################### *)
(** *** Types *)
(** We start with the simply typed lambda calculus over the
natural numbers. To the base natural number type and arrow types
we need to add two more types to deal with references. First, we
need the _unit type_, which we will use as the result type of an
assignment operation. We then add _reference types_. *)
(** If [T] is a type, then [Ref T] is the type of references which
point to a cell holding values of type [T].
T ::= Nat
| Unit
| T -> T
| Ref T
*)
Inductive ty : Type :=
| TNat : ty
| TUnit : ty
| TArrow : ty -> ty -> ty
| TRef : ty -> ty.
(* ################################### *)
(** *** Terms *)
(** Besides variables, abstractions, applications,
natural-number-related terms, and [unit], we need four more sorts
of terms in order to handle mutable references:
<<
t ::= ... Terms
| ref t allocation
| !t dereference
| t := t assignment
| l location
>>
*)
Inductive tm : Type :=
(* STLC with numbers: *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm
(* New terms: *)
| tunit : tm
| tref : tm -> tm
| tderef : tm -> tm
| tassign : tm -> tm -> tm
| tloc : nat -> tm.
(** Intuitively...
- [ref t] (formally, [tref t]) allocates a new reference cell
with the value [t] and evaluates to the location of the newly
allocated cell;
- [!t] (formally, [tderef t]) evaluates to the contents of the
cell referenced by [t];
- [t1 := t2] (formally, [tassign t1 t2]) assigns [t2] to the
cell referenced by [t1]; and
- [l] (formally, [tloc l]) is a reference to the cell at
location [l]. We'll discuss locations later. *)
(** In informal examples, we'll also freely use the extensions
of the STLC developed in the [MoreStlc] chapter; however, to keep
the proofs small, we won't bother formalizing them again here. It
would be easy to do so, since there are no very interesting
interactions between those features and references. *)
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "tzero"
| Case_aux c "tsucc" | Case_aux c "tpred"
| Case_aux c "tmult" | Case_aux c "tif0"
| Case_aux c "tunit" | Case_aux c "tref"
| Case_aux c "tderef" | Case_aux c "tassign"
| Case_aux c "tloc" ].
Module ExampleVariables.
Definition x := Id 0.
Definition y := Id 1.
Definition r := Id 2.
Definition s := Id 3.
End ExampleVariables.
(* ################################### *)
(** *** Typing (Preview) *)
(** Informally, the typing rules for allocation, dereferencing, and
assignment will look like this:
Gamma |- t1 : T1
------------------------ (T_Ref)
Gamma |- ref t1 : Ref T1
Gamma |- t1 : Ref T11
--------------------- (T_Deref)
Gamma |- !t1 : T11
Gamma |- t1 : Ref T11
Gamma |- t2 : T11
------------------------ (T_Assign)
Gamma |- t1 := t2 : Unit
The rule for locations will require a bit more machinery, and this
will motivate some changes to the other rules; we'll come back to
this later. *)
(* ################################### *)
(** *** Values and Substitution *)
(** Besides abstractions and numbers, we have two new types of values:
the unit value, and locations. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_nat : forall n,
value (tnat n)
| v_unit :
value tunit
| v_loc : forall l,
value (tloc l).
Hint Constructors value.
(** Extending substitution to handle the new syntax of terms is
straightforward. *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
| tabs x' T t1 =>
if eq_id_dec x x' then t else tabs x' T (subst x s t1)
| tnat n =>
t
| tsucc t1 =>
tsucc (subst x s t1)
| tpred t1 =>
tpred (subst x s t1)
| tmult t1 t2 =>
tmult (subst x s t1) (subst x s t2)
| tif0 t1 t2 t3 =>
tif0 (subst x s t1) (subst x s t2) (subst x s t3)
| tunit =>
t
| tref t1 =>
tref (subst x s t1)
| tderef t1 =>
tderef (subst x s t1)
| tassign t1 t2 =>
tassign (subst x s t1) (subst x s t2)
| tloc _ =>
t
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ###################################################################### *)
(** * Pragmatics *)
(* ################################### *)
(** ** Side Effects and Sequencing *)
(** The fact that the result of an assignment expression is the
trivial value [unit] allows us to use a nice abbreviation for
_sequencing_. For example, we can write
<<
r:=succ(!r); !r
>>
as an abbreviation for
<<
(\x:Unit. !r) (r := succ(!r)).
>>
This has the effect of evaluating two expressions in order and
returning the value of the second. Restricting the type of the first
expression to [Unit] helps the typechecker to catch some silly
errors by permitting us to throw away the first value only if it
is really guaranteed to be trivial.
Notice that, if the second expression is also an assignment, then
the type of the whole sequence will be [Unit], so we can validly
place it to the left of another [;] to build longer sequences of
assignments:
<<
r:=succ(!r); r:=succ(!r); r:=succ(!r); r:=succ(!r); !r
>>
*)
(** Formally, we introduce sequencing as a "derived form"
[tseq] that expands into an abstraction and an application. *)
Definition tseq t1 t2 :=
tapp (tabs (Id 0) TUnit t2) t1.
(* ################################### *)
(** ** References and Aliasing *)
(** It is important to bear in mind the difference between the
_reference_ that is bound to [r] and the _cell_ in the store that
is pointed to by this reference.
If we make a copy of [r], for example by binding its value to
another variable [s], what gets copied is only the _reference_,
not the contents of the cell itself.
For example, after evaluating
<<
let r = ref 5 in
let s = r in
s := 82;
(!r)+1
>>
the cell referenced by [r] will contain the value [82], while the
result of the whole expression will be [83]. The references [r]
and [s] are said to be _aliases_ for the same cell.
The possibility of aliasing can make programs with references
quite tricky to reason about. For example, the expression
<<
r := 5; r := !s
>>
assigns [5] to [r] and then immediately overwrites it with [s]'s
current value; this has exactly the same effect as the single
assignment
<<
r := !s
>>
_unless_ we happen to do it in a context where [r] and [s] are
aliases for the same cell! *)
(* ################################### *)
(** ** Shared State *)
(** Of course, aliasing is also a large part of what makes references
useful. In particular, it allows us to set up "implicit
communication channels" -- shared state -- between different parts
of a program. For example, suppose we define a reference cell and
two functions that manipulate its contents:
<<
let c = ref 0 in
let incc = \_:Unit. (c := succ (!c); !c) in
let decc = \_:Unit. (c := pred (!c); !c) in
...
>>
*)
(** Note that, since their argument types are [Unit], the
abstractions in the definitions of [incc] and [decc] are not
providing any useful information to the bodies of the
functions (using the wildcard [_] as the name of the bound
variable is a reminder of this). Instead, their purpose is to
"slow down" the execution of the function bodies: since function
abstractions are values, the two [let]s are executed simply by
binding these functions to the names [incc] and [decc], rather
than by actually incrementing or decrementing [c]. Later, each
call to one of these functions results in its body being executed
once and performing the appropriate mutation on [c]. Such
functions are often called _thunks_.
In the context of these declarations, calling [incc] results in
changes to [c] that can be observed by calling [decc]. For
example, if we replace the [...] with [(incc unit; incc unit; decc
unit)], the result of the whole program will be [1]. *)
(** ** Objects *)
(** We can go a step further and write a _function_ that creates [c],
[incc], and [decc], packages [incc] and [decc] together into a
record, and returns this record:
<<
newcounter =
\_:Unit.
let c = ref 0 in
let incc = \_:Unit. (c := succ (!c); !c) in
let decc = \_:Unit. (c := pred (!c); !c) in
{i=incc, d=decc}
>>
*)
(** Now, each time we call [newcounter], we get a new record of
functions that share access to the same storage cell [c]. The
caller of [newcounter] can't get at this storage cell directly,
but can affect it indirectly by calling the two functions. In
other words, we've created a simple form of _object_.
<<
let c1 = newcounter unit in
let c2 = newcounter unit in
// Note that we've allocated two separate storage cells now!
let r1 = c1.i unit in
let r2 = c2.i unit in
r2 // yields 1, not 2!
>>
*)
(** **** Exercise: 1 star (store_draw) *)
(** Draw (on paper) the contents of the store at the point in
execution where the first two [let]s have finished and the third
one is about to begin. *)
(* 0 0 *)
(** [] *)
(* ################################### *)
(** ** References to Compound Types *)
(** A reference cell need not contain just a number: the primitives
we've defined above allow us to create references to values of any
type, including functions. For example, we can use references to
functions to give a (not very efficient) implementation of arrays
of numbers, as follows. Write [NatArray] for the type
[Ref (Nat->Nat)].
Recall the [equal] function from the [MoreStlc] chapter:
<<
equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if m=0 then iszero n
else if n=0 then false
else eq (pred m) (pred n))
>>
Now, to build a new array, we allocate a reference cell and fill
it with a function that, when given an index, always returns [0].
<<
newarray = \_:Unit. ref (\n:Nat.0)
>>
To look up an element of an array, we simply apply
the function to the desired index.
<<
lookup = \a:NatArray. \n:Nat. (!a) n
>>
The interesting part of the encoding is the [update] function. It
takes an array, an index, and a new value to be stored at that index, and
does its job by creating (and storing in the reference) a new function
that, when it is asked for the value at this very index, returns the new
value that was given to [update], and on all other indices passes the
lookup to the function that was previously stored in the reference.
<<
update = \a:NatArray. \m:Nat. \v:Nat.
let oldf = !a in
a := (\n:Nat. if equal m n then v else oldf n);
>>
References to values containing other references can also be very
useful, allowing us to define data structures such as mutable
lists and trees. *)
(** **** Exercise: 2 stars (compact_update) *)
(** If we defined [update] more compactly like this
<<
update = \a:NatArray. \m:Nat. \v:Nat.
a := (\n:Nat. if equal m n then v else (!a) n)
>>
would it behave the same? *)
(* No, evaluation will be delayed causing an infinite loop due to functions are values. *)
(** [] *)
(* ################################### *)
(** ** Null References *)
(** There is one more difference between our references and C-style
mutable variables: in C-like languages, variables holding pointers
into the heap may sometimes have the value [NULL]. Dereferencing
such a "null pointer" is an error, and results in an
exception (Java) or in termination of the program (C).
Null pointers cause significant trouble in C-like languages: the
fact that any pointer might be null means that any dereference
operation in the program can potentially fail. However, even in
ML-like languages, there are occasionally situations where we may
or may not have a valid pointer in our hands. Fortunately, there
is no need to extend the basic mechanisms of references to achieve
this: the sum types introduced in the [MoreStlc] chapter already
give us what we need.
First, we can use sums to build an analog of the [option] types
introduced in the [Lists] chapter. Define [Option T] to be an
abbreviation for [Unit + T].
Then a "nullable reference to a [T]" is simply an element of the
type [Option (Ref T)]. *)
(* ################################### *)
(** ** Garbage Collection *)
(** A last issue that we should mention before we move on with
formalizing references is storage _de_-allocation. We have not
provided any primitives for freeing reference cells when they are
no longer needed. Instead, like many modern languages (including
ML and Java) we rely on the run-time system to perform _garbage
collection_, collecting and reusing cells that can no longer be
reached by the program.
This is _not_ just a question of taste in language design: it is
extremely difficult to achieve type safety in the presence of an
explicit deallocation operation. The reason for this is the
familiar _dangling reference_ problem: we allocate a cell holding
a number, save a reference to it in some data structure, use it
for a while, then deallocate it and allocate a new cell holding a
boolean, possibly reusing the same storage. Now we can have two
names for the same storage cell -- one with type [Ref Nat] and the
other with type [Ref Bool]. *)
(** **** Exercise: 1 star (type_safety_violation) *)
(** Show how this can lead to a violation of type safety. *)
(* Deallocate some place and allocate it with another type. *)
(** [] *)
(* ###################################################################### *)
(** * Operational Semantics *)
(* ################################### *)
(** ** Locations *)
(** The most subtle aspect of the treatment of references
appears when we consider how to formalize their operational
behavior. One way to see why is to ask, "What should be the
_values_ of type [Ref T]?" The crucial observation that we need
to take into account is that evaluating a [ref] operator should
_do_ something -- namely, allocate some storage -- and the result
of the operation should be a reference to this storage.
What, then, is a reference?
The run-time store in most programming language implementations is
essentially just a big array of bytes. The run-time system keeps track
of which parts of this array are currently in use; when we need to
allocate a new reference cell, we allocate a large enough segment from
the free region of the store (4 bytes for integer cells, 8 bytes for
cells storing [Float]s, etc.), mark it as being used, and return the
index (typically, a 32- or 64-bit integer) of the start of the newly
allocated region. These indices are references.
For present purposes, there is no need to be quite so concrete.
We can think of the store as an array of _values_, rather than an
array of bytes, abstracting away from the different sizes of the
run-time representations of different values. A reference, then,
is simply an index into the store. (If we like, we can even
abstract away from the fact that these indices are numbers, but
for purposes of formalization in Coq it is a bit more convenient
to use numbers.) We'll use the word _location_ instead of
_reference_ or _pointer_ from now on to emphasize this abstract
quality.
Treating locations abstractly in this way will prevent us from
modeling the _pointer arithmetic_ found in low-level languages
such as C. This limitation is intentional. While pointer
arithmetic is occasionally very useful, especially for
implementing low-level services such as garbage collectors, it
cannot be tracked by most type systems: knowing that location [n]
in the store contains a [float] doesn't tell us anything useful
about the type of location [n+4]. In C, pointer arithmetic is a
notorious source of type safety violations. *)
(* ################################### *)
(** ** Stores *)
(** Recall that, in the small-step operational semantics for
IMP, the step relation needed to carry along an auxiliary state in
addition to the program being executed. In the same way, once we
have added reference cells to the STLC, our step relation must
carry along a store to keep track of the contents of reference
cells.
We could re-use the same functional representation we used for
states in IMP, but for carrying out the proofs in this chapter it
is actually more convenient to represent a store simply as a
_list_ of values. (The reason we couldn't use this representation
before is that, in IMP, a program could modify any location at any
time, so states had to be ready to map _any_ variable to a value.
However, in the STLC with references, the only way to create a
reference cell is with [tref t1], which puts the value of [t1]
in a new reference cell and evaluates to the location of the newly
created reference cell. When evaluating such an expression, we can
just add a new reference cell to the end of the list representing
the store.) *)
Definition store := list tm.
(** We use [store_lookup n st] to retrieve the value of the reference
cell at location [n] in the store [st]. Note that we must give a
default value to [nth] in case we try looking up an index which is
too large. (In fact, we will never actually do this, but proving
it will of course require some work!) *)
Definition store_lookup (n:nat) (st:store) :=
nth n st tunit.
(** To add a new reference cell to the store, we use [snoc]. *)
Fixpoint snoc {A:Type} (l:list A) (x:A) : list A :=
match l with
| nil => x :: nil
| h :: t => h :: snoc t x
end.
(** We will need some boring lemmas about [snoc]. The proofs are
routine inductions. *)
Lemma length_snoc : forall A (l:list A) x,
length (snoc l x) = S (length l).
Proof.
induction l; intros; [ auto | simpl; rewrite IHl; auto ]. Qed.
(* The "solve by inversion" tactic is explained in Stlc.v. *)
Lemma nth_lt_snoc : forall A (l:list A) x d n,
n < length l ->
nth n l d = nth n (snoc l x) d.
Proof.
induction l as [|a l']; intros; try solve by inversion.
Case "l = a :: l'".
destruct n; auto.
simpl. apply IHl'.
simpl in H. apply lt_S_n in H. assumption.
Qed.
Lemma nth_eq_snoc : forall A (l:list A) x d,
nth (length l) (snoc l x) d = x.
Proof.
induction l; intros; [ auto | simpl; rewrite IHl; auto ].
Qed.
(** To update the store, we use the [replace] function, which replaces
the contents of a cell at a particular index. *)
Fixpoint replace {A:Type} (n:nat) (x:A) (l:list A) : list A :=
match l with
| nil => nil
| h :: t =>
match n with
| O => x :: t
| S n' => h :: replace n' x t
end
end.
(** Of course, we also need some boring lemmas about [replace], which
are also fairly straightforward to prove. *)
Lemma replace_nil : forall A n (x:A),
replace n x nil = nil.
Proof.
destruct n; auto.
Qed.
Lemma length_replace : forall A n x (l:list A),
length (replace n x l) = length l.
Proof with auto.
intros A n x l. generalize dependent n.
induction l; intros n.
destruct n...
destruct n...
simpl. rewrite IHl...
Qed.
Lemma lookup_replace_eq : forall l t st,
l < length st ->
store_lookup l (replace l t st) = t.
Proof with auto.
intros l t st.
unfold store_lookup.
generalize dependent l.
induction st as [|t' st']; intros l Hlen.
Case "st = []".
inversion Hlen.
Case "st = t' :: st'".
destruct l; simpl...
apply IHst'. simpl in Hlen. omega.
Qed.
Lemma lookup_replace_neq : forall l1 l2 t st,
l1 <> l2 ->
store_lookup l1 (replace l2 t st) = store_lookup l1 st.
Proof with auto.
unfold store_lookup.
induction l1 as [|l1']; intros l2 t st Hneq.
Case "l1 = 0".
destruct st.
SCase "st = []". rewrite replace_nil...
SCase "st = _ :: _". destruct l2... contradict Hneq...
Case "l1 = S l1'".
destruct st as [|t2 st2].
SCase "st = []". destruct l2...
SCase "st = t2 :: st2".
destruct l2...
simpl; apply IHl1'...
Qed.
(* ################################### *)
(** ** Reduction *)
(** Next, we need to extend our operational semantics to take stores
into account. Since the result of evaluating an expression will
in general depend on the contents of the store in which it is
evaluated, the evaluation rules should take not just a term but
also a store as argument. Furthermore, since the evaluation of a
term may cause side effects on the store that may affect the
evaluation of other terms in the future, the evaluation rules need
to return a new store. Thus, the shape of the single-step
evaluation relation changes from [t ==> t'] to [t / st ==> t' /
st'], where [st] and [st'] are the starting and ending states of
the store.
To carry through this change, we first need to augment all of our
existing evaluation rules with stores:
value v2
-------------------------------------- (ST_AppAbs)
(\x:T.t12) v2 / st ==> [x:=v2]t12 / st
t1 / st ==> t1' / st'
--------------------------- (ST_App1)
t1 t2 / st ==> t1' t2 / st'
value v1 t2 / st ==> t2' / st'
---------------------------------- (ST_App2)
v1 t2 / st ==> v1 t2' / st'
Note that the first rule here returns the store unchanged:
function application, in itself, has no side effects. The other two
rules simply propagate side effects from premise to conclusion.
Now, the result of evaluating a [ref] expression will be a fresh
location; this is why we included locations in the syntax of terms
and in the set of values.
It is crucial to note that making this extension to the syntax of
terms does not mean that we intend _programmers_ to write terms
involving explicit, concrete locations: such terms will arise only
as intermediate results of evaluation. This may initially seem
odd, but really it follows naturally from our design decision to
represent the result of every evaluation step by a modified
term. If we had chosen a more "machine-like" model for evaluation,
e.g. with an explicit stack to contain values of bound
identifiers, then the idea of adding locations to the set of
allowed values would probably seem more obvious.
In terms of this expanded syntax, we can state evaluation rules for
the new constructs that manipulate locations and the store. First, to
evaluate a dereferencing expression [!t1], we must first reduce [t1]
until it becomes a value:
t1 / st ==> t1' / st'
----------------------- (ST_Deref)
!t1 / st ==> !t1' / st'
Once [t1] has finished reducing, we should have an expression of
the form [!l], where [l] is some location. (A term that attempts
to dereference any other sort of value, such as a function or
[unit], is erroneous, as is a term that tries to derefence a
location that is larger than the size [|st|] of the currently
allocated store; the evaluation rules simply get stuck in this
case. The type safety properties that we'll establish below
assure us that well-typed terms will never misbehave in this way.)
l < |st|
---------------------------------- (ST_DerefLoc)
!(loc l) / st ==> lookup l st / st
Next, to evaluate an assignment expression [t1:=t2], we must first
evaluate [t1] until it becomes a value (a location), and then
evaluate [t2] until it becomes a value (of any sort):
t1 / st ==> t1' / st'
----------------------------------- (ST_Assign1)
t1 := t2 / st ==> t1' := t2 / st'
t2 / st ==> t2' / st'
--------------------------------- (ST_Assign2)
v1 := t2 / st ==> v1 := t2' / st'
Once we have finished with [t1] and [t2], we have an expression of
the form [l:=v2], which we execute by updating the store to make
location [l] contain [v2]:
l < |st|
------------------------------------- (ST_Assign)
loc l := v2 / st ==> unit / [l:=v2]st
The notation [[l:=v2]st] means "the store that maps [l] to [v2]
and maps all other locations to the same thing as [st.]" Note
that the term resulting from this evaluation step is just [unit];
the interesting result is the updated store.)
Finally, to evaluate an expression of the form [ref t1], we first
evaluate [t1] until it becomes a value:
t1 / st ==> t1' / st'
----------------------------- (ST_Ref)
ref t1 / st ==> ref t1' / st'
Then, to evaluate the [ref] itself, we choose a fresh location at
the end of the current store -- i.e., location [|st|] -- and yield
a new store that extends [st] with the new value [v1].
-------------------------------- (ST_RefValue)
ref v1 / st ==> loc |st| / st,v1
The value resulting from this step is the newly allocated location
itself. (Formally, [st,v1] means [snoc st v1].)
Note that these evaluation rules do not perform any kind of
garbage collection: we simply allow the store to keep growing
without bound as evaluation proceeds. This does not affect the
correctness of the results of evaluation (after all, the
definition of "garbage" is precisely parts of the store that are
no longer reachable and so cannot play any further role in
evaluation), but it means that a naive implementation of our
evaluator might sometimes run out of memory where a more
sophisticated evaluator would be able to continue by reusing
locations whose contents have become garbage.
Formally... *)
Reserved Notation "t1 '/' st1 '==>' t2 '/' st2"
(at level 40, st1 at level 39, t2 at level 39).
Inductive step : tm * store -> tm * store -> Prop :=
| ST_AppAbs : forall x T t12 v2 st,
value v2 ->
tapp (tabs x T t12) v2 / st ==> [x:=v2]t12 / st
| ST_App1 : forall t1 t1' t2 st st',
t1 / st ==> t1' / st' ->
tapp t1 t2 / st ==> tapp t1' t2 / st'
| ST_App2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tapp v1 t2 / st ==> tapp v1 t2'/ st'
| ST_SuccNat : forall n st,
tsucc (tnat n) / st ==> tnat (S n) / st
| ST_Succ : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tsucc t1 / st ==> tsucc t1' / st'
| ST_PredNat : forall n st,
tpred (tnat n) / st ==> tnat (pred n) / st
| ST_Pred : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tpred t1 / st ==> tpred t1' / st'
| ST_MultNats : forall n1 n2 st,
tmult (tnat n1) (tnat n2) / st ==> tnat (mult n1 n2) / st
| ST_Mult1 : forall t1 t2 t1' st st',
t1 / st ==> t1' / st' ->
tmult t1 t2 / st ==> tmult t1' t2 / st'
| ST_Mult2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tmult v1 t2 / st ==> tmult v1 t2' / st'
| ST_If0 : forall t1 t1' t2 t3 st st',
t1 / st ==> t1' / st' ->
tif0 t1 t2 t3 / st ==> tif0 t1' t2 t3 / st'
| ST_If0_Zero : forall t2 t3 st,
tif0 (tnat 0) t2 t3 / st ==> t2 / st
| ST_If0_Nonzero : forall n t2 t3 st,
tif0 (tnat (S n)) t2 t3 / st ==> t3 / st
| ST_RefValue : forall v1 st,
value v1 ->
tref v1 / st ==> tloc (length st) / snoc st v1
| ST_Ref : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tref t1 / st ==> tref t1' / st'
| ST_DerefLoc : forall st l,
l < length st ->
tderef (tloc l) / st ==> store_lookup l st / st
| ST_Deref : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tderef t1 / st ==> tderef t1' / st'
| ST_Assign : forall v2 l st,
value v2 ->
l < length st ->
tassign (tloc l) v2 / st ==> tunit / replace l v2 st
| ST_Assign1 : forall t1 t1' t2 st st',
t1 / st ==> t1' / st' ->
tassign t1 t2 / st ==> tassign t1' t2 / st'
| ST_Assign2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tassign v1 t2 / st ==> tassign v1 t2' / st'
where "t1 '/' st1 '==>' t2 '/' st2" := (step (t1,st1) (t2,st2)).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_SuccNat"
| Case_aux c "ST_Succ" | Case_aux c "ST_PredNat"
| Case_aux c "ST_Pred" | Case_aux c "ST_MultNats"
| Case_aux c "ST_Mult1" | Case_aux c "ST_Mult2"
| Case_aux c "ST_If0" | Case_aux c "ST_If0_Zero"
| Case_aux c "ST_If0_Nonzero" | Case_aux c "ST_RefValue"
| Case_aux c "ST_Ref" | Case_aux c "ST_DerefLoc"
| Case_aux c "ST_Deref" | Case_aux c "ST_Assign"
| Case_aux c "ST_Assign1" | Case_aux c "ST_Assign2" ].
Hint Constructors step.
Definition multistep := (multi step).
Notation "t1 '/' st '==>*' t2 '/' st'" := (multistep (t1,st) (t2,st'))
(at level 40, st at level 39, t2 at level 39).
(* ################################### *)
(** * Typing *)
(** Our contexts for free variables will be exactly the same as for
the STLC, partial maps from identifiers to types. *)
Definition context := partial_map ty.
(* ################################### *)
(** ** Store typings *)
(** Having extended our syntax and evaluation rules to accommodate
references, our last job is to write down typing rules for the new
constructs -- and, of course, to check that they are sound.
Naturally, the key question is, "What is the type of a location?"
First of all, notice that we do _not_ need to answer this question
for purposes of typechecking the terms that programmers actually
write. Concrete location constants arise only in terms that are
the intermediate results of evaluation; they are not in the
language that programmers write. So we only need to determine the
type of a location when we're in the middle of an evaluation
sequence, e.g. trying to apply the progress or preservation
lemmas. Thus, even though we normally think of typing as a
_static_ program property, it makes sense for the typing of
locations to depend on the _dynamic_ progress of the program too.
As a first try, note that when we evaluate a term containing
concrete locations, the type of the result depends on the contents
of the store that we start with. For example, if we evaluate the
term [!(loc 1)] in the store [[unit, unit]], the result is [unit];
if we evaluate the same term in the store [[unit, \x:Unit.x]], the
result is [\x:Unit.x]. With respect to the former store, the
location [1] has type [Unit], and with respect to the latter it
has type [Unit->Unit]. This observation leads us immediately to a
first attempt at a typing rule for locations:
Gamma |- lookup l st : T1
----------------------------
Gamma |- loc l : Ref T1
That is, to find the type of a location [l], we look up the
current contents of [l] in the store and calculate the type [T1]
of the contents. The type of the location is then [Ref T1].
Having begun in this way, we need to go a little further to reach a
consistent state. In effect, by making the type of a term depend on
the store, we have changed the typing relation from a three-place
relation (between contexts, terms, and types) to a four-place relation
(between contexts, _stores_, terms, and types). Since the store is,
intuitively, part of the context in which we calculate the type of a
term, let's write this four-place relation with the store to the left
of the turnstile: [Gamma; st |- t : T]. Our rule for typing
references now has the form
Gamma; st |- lookup l st : T1
--------------------------------
Gamma; st |- loc l : Ref T1
and all the rest of the typing rules in the system are extended
similarly with stores. The other rules do not need to do anything
interesting with their stores -- just pass them from premise to
conclusion.
However, there are two problems with this rule. First, typechecking
is rather inefficient, since calculating the type of a location [l]
involves calculating the type of the current contents [v] of [l]. If
[l] appears many times in a term [t], we will re-calculate the type of
[v] many times in the course of constructing a typing derivation for
[t]. Worse, if [v] itself contains locations, then we will have to
recalculate _their_ types each time they appear.
Second, the proposed typing rule for locations may not allow us to
derive anything at all, if the store contains a _cycle_. For example,
there is no finite typing derivation for the location [0] with respect
to this store:
<<
[\x:Nat. (!(loc 1)) x, \x:Nat. (!(loc 0)) x]
>>
*)
(** **** Exercise: 2 stars (cyclic_store) *)
(** Can you find a term whose evaluation will create this particular
cyclic store? *)
(*
let a = ref 0 in
let b = ref (\x:Nat (!a) x ) in
a := ref (\x:Nat (!b) x)
*)
(** [] *)
(** Both of these problems arise from the fact that our proposed
typing rule for locations requires us to recalculate the type of a
location every time we mention it in a term. But this,
intuitively, should not be necessary. After all, when a location
is first created, we know the type of the initial value that we
are storing into it. Suppose we are willing to enforce the
invariant that the type of the value contained in a given location
_never changes_; that is, although we may later store other values
into this location, those other values will always have the same
type as the initial one. In other words, we always have in mind a
single, definite type for every location in the store, which is
fixed when the location is allocated. Then these intended types
can be collected together as a _store typing_ ---a finite function
mapping locations to types.
As usual, this _conservative_ typing restriction on allowed
updates means that we will rule out as ill-typed some programs
that could evaluate perfectly well without getting stuck.
*)
(** Just like we did for stores, we will represent a store type simply
as a list of types: the type at index [i] records the type of the
value stored in cell [i]. *)
Definition store_ty := list ty.
(** The [store_Tlookup] function retrieves the type at a particular
index. *)
Definition store_Tlookup (n:nat) (ST:store_ty) :=
nth n ST TUnit.
(** Suppose we are _given_ a store typing [ST] describing the store
[st] in which some term [t] will be evaluated. Then we can use
[ST] to calculate the type of the result of [t] without ever
looking directly at [st]. For example, if [ST] is [[Unit,
Unit->Unit]], then we may immediately infer that [!(loc 1)] has
type [Unit->Unit]. More generally, the typing rule for locations
can be reformulated in terms of store typings like this:
l < |ST|
-------------------------------------
Gamma; ST |- loc l : Ref (lookup l ST)
That is, as long as [l] is a valid location (it is less than the
length of [ST]), we can compute the type of [l] just by looking it
up in [ST]. Typing is again a four-place relation, but it is
parameterized on a store _typing_ rather than a concrete store.
The rest of the typing rules are analogously augmented with store
typings. *)
(* ################################### *)
(** ** The Typing Relation *)
(** We can now give the typing relation for the STLC with
references. Here, again, are the rules we're adding to the base
STLC (with numbers and [Unit]): *)
(**
l < |ST|
-------------------------------------- (T_Loc)
Gamma; ST |- loc l : Ref (lookup l ST)
Gamma; ST |- t1 : T1
---------------------------- (T_Ref)
Gamma; ST |- ref t1 : Ref T1
Gamma; ST |- t1 : Ref T11
------------------------- (T_Deref)
Gamma; ST |- !t1 : T11
Gamma; ST |- t1 : Ref T11
Gamma; ST |- t2 : T11
----------------------------- (T_Assign)
Gamma; ST |- t1 := t2 : Unit
*)
Reserved Notation "Gamma ';' ST '|-' t '\in' T" (at level 40).
Inductive has_type : context -> store_ty -> tm -> ty -> Prop :=
| T_Var : forall Gamma ST x T,
Gamma x = Some T ->
Gamma; ST |- (tvar x) \in T
| T_Abs : forall Gamma ST x T11 T12 t12,
(extend Gamma x T11); ST |- t12 \in T12 ->
Gamma; ST |- (tabs x T11 t12) \in (TArrow T11 T12)
| T_App : forall T1 T2 Gamma ST t1 t2,
Gamma; ST |- t1 \in (TArrow T1 T2) ->
Gamma; ST |- t2 \in T1 ->
Gamma; ST |- (tapp t1 t2) \in T2
| T_Nat : forall Gamma ST n,
Gamma; ST |- (tnat n) \in TNat
| T_Succ : forall Gamma ST t1,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- (tsucc t1) \in TNat
| T_Pred : forall Gamma ST t1,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- (tpred t1) \in TNat
| T_Mult : forall Gamma ST t1 t2,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- t2 \in TNat ->
Gamma; ST |- (tmult t1 t2) \in TNat
| T_If0 : forall Gamma ST t1 t2 t3 T,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- t2 \in T ->
Gamma; ST |- t3 \in T ->
Gamma; ST |- (tif0 t1 t2 t3) \in T
| T_Unit : forall Gamma ST,
Gamma; ST |- tunit \in TUnit
| T_Loc : forall Gamma ST l,
l < length ST ->
Gamma; ST |- (tloc l) \in (TRef (store_Tlookup l ST))
| T_Ref : forall Gamma ST t1 T1,
Gamma; ST |- t1 \in T1 ->
Gamma; ST |- (tref t1) \in (TRef T1)
| T_Deref : forall Gamma ST t1 T11,
Gamma; ST |- t1 \in (TRef T11) ->
Gamma; ST |- (tderef t1) \in T11
| T_Assign : forall Gamma ST t1 t2 T11,
Gamma; ST |- t1 \in (TRef T11) ->
Gamma; ST |- t2 \in T11 ->
Gamma; ST |- (tassign t1 t2) \in TUnit
where "Gamma ';' ST '|-' t '\in' T" := (has_type Gamma ST t T).
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs" | Case_aux c "T_App"
| Case_aux c "T_Nat" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Mult" | Case_aux c "T_If0"
| Case_aux c "T_Unit" | Case_aux c "T_Loc"
| Case_aux c "T_Ref" | Case_aux c "T_Deref"
| Case_aux c "T_Assign" ].
(** Of course, these typing rules will accurately predict the results
of evaluation only if the concrete store used during evaluation
actually conforms to the store typing that we assume for purposes
of typechecking. This proviso exactly parallels the situation
with free variables in the STLC: the substitution lemma promises
us that, if [Gamma |- t : T], then we can replace the free
variables in [t] with values of the types listed in [Gamma] to
obtain a closed term of type [T], which, by the type preservation
theorem will evaluate to a final result of type [T] if it yields
any result at all. (We will see later how to formalize an
analogous intuition for stores and store typings.)
However, for purposes of typechecking the terms that programmers
actually write, we do not need to do anything tricky to guess what
store typing we should use. Recall that concrete location
constants arise only in terms that are the intermediate results of
evaluation; they are not in the language that programmers write.
Thus, we can simply typecheck the programmer's terms with respect
to the _empty_ store typing. As evaluation proceeds and new
locations are created, we will always be able to see how to extend
the store typing by looking at the type of the initial values
being placed in newly allocated cells; this intuition is
formalized in the statement of the type preservation theorem
below. *)
(* ################################### *)
(** * Properties *)
(** Our final task is to check that standard type safety properties
continue to hold for the STLC with references. The progress
theorem ("well-typed terms are not stuck") can be stated and
proved almost as for the STLC; we just need to add a few
straightforward cases to the proof, dealing with the new
constructs. The preservation theorem is a bit more interesting,
so let's look at it first. *)
(* ################################### *)
(** ** Well-Typed Stores *)
(** Since we have extended both the evaluation relation (with initial
and final stores) and the typing relation (with a store typing),
we need to change the statement of preservation to include these
parameters. Clearly, though, we cannot just add stores and store
typings without saying anything about how they are related: *)
Theorem preservation_wrong1 : forall ST T t st t' st',
empty; ST |- t \in T ->
t / st ==> t' / st' ->
empty; ST |- t' \in T.
Abort.
(** If we typecheck with respect to some set of assumptions about the
types of the values in the store and then evaluate with respect to
a store that violates these assumptions, the result will be
disaster. We say that a store [st] is _well typed_ with respect a
store typing [ST] if the term at each location [l] in [st] has the
type at location [l] in [ST]. Since only closed terms ever get
stored in locations (why?), it suffices to type them in the empty
context. The following definition of [store_well_typed] formalizes
this. *)
Definition store_well_typed (ST:store_ty) (st:store) :=
length ST = length st /\
(forall l, l < length st ->
empty; ST |- (store_lookup l st) \in (store_Tlookup l ST)).
(** Informally, we will write [ST |- st] for [store_well_typed ST st]. *)
(** Intuitively, a store [st] is consistent with a store typing
[ST] if every value in the store has the type predicted by the
store typing. (The only subtle point is the fact that, when
typing the values in the store, we supply the very same store
typing to the typing relation! This allows us to type circular
stores.) *)
(** **** Exercise: 2 stars (store_not_unique) *)
(** Can you find a store [st], and two
different store typings [ST1] and [ST2] such that both
[ST1 |- st] and [ST2 |- st]? *)
(*
st = [\x:Nat. !(loc 1) x , \x:Nat. !(loc 0) x]
ST1 = [Nat -> X , Nat -> X]
ST2 = [Nat -> Y , Nat -> Y]
*)
(** [] *)
(** We can now state something closer to the desired preservation
property: *)
Theorem preservation_wrong2 : forall ST T t st t' st',
empty; ST |- t \in T ->
t / st ==> t' / st' ->
store_well_typed ST st ->
empty; ST |- t' \in T.
Abort.
(** This statement is fine for all of the evaluation rules except the
allocation rule [ST_RefValue]. The problem is that this rule
yields a store with a larger domain than the initial store, which
falsifies the conclusion of the above statement: if [st']
includes a binding for a fresh location [l], then [l] cannot be in
the domain of [ST], and it will not be the case that [t']
(which definitely mentions [l]) is typable under [ST]. *)
(* ############################################ *)
(** ** Extending Store Typings *)
(** Evidently, since the store can increase in size during evaluation,
we need to allow the store typing to grow as well. This motivates
the following definition. We say that the store type [ST']
_extends_ [ST] if [ST'] is just [ST] with some new types added to
the end. *)
Inductive extends : store_ty -> store_ty -> Prop :=
| extends_nil : forall ST',
extends ST' nil
| extends_cons : forall x ST' ST,
extends ST' ST ->
extends (x::ST') (x::ST).
Hint Constructors extends.
(** We'll need a few technical lemmas about extended contexts.
First, looking up a type in an extended store typing yields the
same result as in the original: *)
Lemma extends_lookup : forall l ST ST',
l < length ST ->
extends ST' ST ->
store_Tlookup l ST' = store_Tlookup l ST.
Proof with auto.
intros l ST ST' Hlen H.
generalize dependent ST'. generalize dependent l.
induction ST as [|a ST2]; intros l Hlen ST' HST'.
Case "nil". inversion Hlen.
Case "cons". unfold store_Tlookup in *.
destruct ST'.
SCase "ST' = nil". inversion HST'.
SCase "ST' = a' :: ST'2".
inversion HST'; subst.
destruct l as [|l'].
SSCase "l = 0"...
SSCase "l = S l'". simpl. apply IHST2...
simpl in Hlen; omega.
Qed.
(** Next, if [ST'] extends [ST], the length of [ST'] is at least that
of [ST]. *)
Lemma length_extends : forall l ST ST',
l < length ST ->
extends ST' ST ->
l < length ST'.
Proof with eauto.
intros. generalize dependent l. induction H0; intros l Hlen.
inversion Hlen.
simpl in *.
destruct l; try omega.
apply lt_n_S. apply IHextends. omega.
Qed.
(** Finally, [snoc ST T] extends [ST], and [extends] is reflexive. *)
Lemma extends_snoc : forall ST T,
extends (snoc ST T) ST.
Proof with auto.
induction ST; intros T...
simpl...
Qed.
Lemma extends_refl : forall ST,
extends ST ST.
Proof.
induction ST; auto.
Qed.
(* ################################### *)
(** ** Preservation, Finally *)
(** We can now give the final, correct statement of the type
preservation property: *)
Definition preservation_theorem := forall ST t t' T st st',
empty; ST |- t \in T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
empty; ST' |- t' \in T /\
store_well_typed ST' st').
(** Note that the preservation theorem merely asserts that there is
_some_ store typing [ST'] extending [ST] (i.e., agreeing with [ST]
on the values of all the old locations) such that the new term
[t'] is well typed with respect to [ST']; it does not tell us
exactly what [ST'] is. It is intuitively clear, of course, that
[ST'] is either [ST] or else it is exactly [snoc ST T1], where
[T1] is the type of the value [v1] in the extended store [snoc st
v1], but stating this explicitly would complicate the statement of
the theorem without actually making it any more useful: the weaker
version above is already in the right form (because its conclusion
implies its hypothesis) to "turn the crank" repeatedly and
conclude that every _sequence_ of evaluation steps preserves
well-typedness. Combining this with the progress property, we
obtain the usual guarantee that "well-typed programs never go
wrong."
In order to prove this, we'll need a few lemmas, as usual. *)
(* ################################### *)
(** ** Substitution lemma *)
(** First, we need an easy extension of the standard substitution
lemma, along with the same machinery about context invariance that
we used in the proof of the substitution lemma for the STLC. *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_succ : forall x t1,
appears_free_in x t1 ->
appears_free_in x (tsucc t1)
| afi_pred : forall x t1,
appears_free_in x t1 ->
appears_free_in x (tpred t1)
| afi_mult1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tmult t1 t2)
| afi_mult2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tmult t1 t2)
| afi_if0_1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if0_2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if0_3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_ref : forall x t1,
appears_free_in x t1 -> appears_free_in x (tref t1)
| afi_deref : forall x t1,
appears_free_in x t1 -> appears_free_in x (tderef t1)
| afi_assign1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tassign t1 t2)
| afi_assign2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tassign t1 t2).
Tactic Notation "afi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "afi_var"
| Case_aux c "afi_app1" | Case_aux c "afi_app2" | Case_aux c "afi_abs"
| Case_aux c "afi_succ" | Case_aux c "afi_pred"
| Case_aux c "afi_mult1" | Case_aux c "afi_mult2"
| Case_aux c "afi_if0_1" | Case_aux c "afi_if0_2" | Case_aux c "afi_if0_3"
| Case_aux c "afi_ref" | Case_aux c "afi_deref"
| Case_aux c "afi_assign1" | Case_aux c "afi_assign2" ].
Hint Constructors appears_free_in.
Lemma free_in_context : forall x t T Gamma ST,
appears_free_in x t ->
Gamma; ST |- t \in T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros. generalize dependent Gamma. generalize dependent T.
afi_cases (induction H) Case;
intros; (try solve [ inversion H0; subst; eauto ]).
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H8.
rewrite extend_neq in H8; assumption.
Qed.
Lemma context_invariance : forall Gamma Gamma' ST t T,
Gamma; ST |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma'; ST |- t \in T.
Proof with eauto.
intros.
generalize dependent Gamma'.
has_type_cases (induction H) Case; intros...
Case "T_Var".
apply T_Var. symmetry. rewrite <- H...
Case "T_Abs".
apply T_Abs. apply IHhas_type; intros.
unfold extend.
destruct (eq_id_dec x x0)...
Case "T_App".
eapply T_App.
apply IHhas_type1...
apply IHhas_type2...
Case "T_Mult".
eapply T_Mult.
apply IHhas_type1...
apply IHhas_type2...
Case "T_If0".
eapply T_If0.
apply IHhas_type1...
apply IHhas_type2...
apply IHhas_type3...
Case "T_Assign".
eapply T_Assign.
apply IHhas_type1...
apply IHhas_type2...
Qed.
Lemma substitution_preserves_typing : forall Gamma ST x s S t T,
empty; ST |- s \in S ->
(extend Gamma x S); ST |- t \in T ->
Gamma; ST |- ([x:=s]t) \in T.
Proof with eauto.
intros Gamma ST x s S t T Hs Ht.
generalize dependent Gamma. generalize dependent T.
t_cases (induction t) Case; intros T Gamma H;
inversion H; subst; simpl...
Case "tvar".
rename i into y.
destruct (eq_id_dec x y).
SCase "x = y".
subst.
rewrite extend_eq in H3.
inversion H3; subst.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ _ _ _ Hcontra Hs) as [T' HT'].
inversion HT'.
SCase "x <> y".
apply T_Var.
rewrite extend_neq in H3...
Case "tabs". subst.
rename i into y.
destruct (eq_id_dec x y).
SCase "x = y".
subst.
apply T_Abs. eapply context_invariance...
intros. apply extend_shadow.
SCase "x <> x0".
apply T_Abs. apply IHt.
eapply context_invariance...
intros. unfold extend.
destruct (eq_id_dec y x0)...
subst.
rewrite neq_id...
Qed.
(* ################################### *)
(** ** Assignment Preserves Store Typing *)
(** Next, we must show that replacing the contents of a cell in the
store with a new value of appropriate type does not change the
overall type of the store. (This is needed for the [ST_Assign]
rule.) *)
Lemma assign_pres_store_typing : forall ST st l t,
l < length st ->
store_well_typed ST st ->
empty; ST |- t \in (store_Tlookup l ST) ->
store_well_typed ST (replace l t st).
Proof with auto.
intros ST st l t Hlen HST Ht.
inversion HST; subst.
split. rewrite length_replace...
intros l' Hl'.
destruct (beq_nat l' l) eqn: Heqll'.
Case "l' = l".
apply beq_nat_true in Heqll'; subst.
rewrite lookup_replace_eq...
Case "l' <> l".
apply beq_nat_false in Heqll'.
rewrite lookup_replace_neq...
rewrite length_replace in Hl'.
apply H0...
Qed.
(* ######################################## *)
(** ** Weakening for Stores *)
(** Finally, we need a lemma on store typings, stating that, if a
store typing is extended with a new location, the extended one
still allows us to assign the same types to the same terms as the
original.
(The lemma is called [store_weakening] because it resembles the
"weakening" lemmas found in proof theory, which show that adding a
new assumption to some logical theory does not decrease the set of
provable theorems.) *)
Lemma store_weakening : forall Gamma ST ST' t T,
extends ST' ST ->
Gamma; ST |- t \in T ->
Gamma; ST' |- t \in T.
Proof with eauto.
intros. has_type_cases (induction H0) Case; eauto.
Case "T_Loc".
erewrite <- extends_lookup...
apply T_Loc.
eapply length_extends...
Qed.
(** We can use the [store_weakening] lemma to prove that if a store is
well typed with respect to a store typing, then the store extended
with a new term [t] will still be well typed with respect to the
store typing extended with [t]'s type. *)
Lemma store_well_typed_snoc : forall ST st t1 T1,
store_well_typed ST st ->
empty; ST |- t1 \in T1 ->
store_well_typed (snoc ST T1) (snoc st t1).
Proof with auto.
intros.
unfold store_well_typed in *.
inversion H as [Hlen Hmatch]; clear H.
rewrite !length_snoc.
split...
Case "types match.".
intros l Hl.
unfold store_lookup, store_Tlookup.
apply le_lt_eq_dec in Hl; inversion Hl as [Hlt | Heq].
SCase "l < length st".
apply lt_S_n in Hlt.
rewrite <- !nth_lt_snoc...
apply store_weakening with ST. apply extends_snoc.
apply Hmatch...
rewrite Hlen...
SCase "l = length st".
inversion Heq.
rewrite nth_eq_snoc.
rewrite <- Hlen. rewrite nth_eq_snoc...
apply store_weakening with ST... apply extends_snoc.
Qed.
(* ################################### *)
(** ** Preservation! *)
(** Now that we've got everything set up right, the proof of
preservation is actually quite straightforward. *)
Theorem preservation : forall ST t t' T st st',
empty; ST |- t \in T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
empty; ST' |- t' \in T /\
store_well_typed ST' st').
Proof with eauto using store_weakening, extends_refl.
remember (@empty ty) as Gamma.
intros ST t t' T st st' Ht.
generalize dependent t'.
has_type_cases (induction Ht) Case; intros t' HST Hstep;
subst; try (solve by inversion); inversion Hstep; subst;
try (eauto using store_weakening, extends_refl).
Case "T_App".
SCase "ST_AppAbs". exists ST.
inversion Ht1; subst.
split; try split... eapply substitution_preserves_typing...
SCase "ST_App1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
SCase "ST_App2".
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Succ".
SCase "ST_Succ".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Pred".
SCase "ST_Pred".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Mult".
SCase "ST_Mult1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
SCase "ST_Mult2".
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_If0".
SCase "ST_If0_1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'... split...
Case "T_Ref".
SCase "ST_RefValue".
exists (snoc ST T1).
inversion HST; subst.
split.
apply extends_snoc.
split.
replace (TRef T1)
with (TRef (store_Tlookup (length st) (snoc ST T1))).
apply T_Loc.
rewrite <- H. rewrite length_snoc. omega.
unfold store_Tlookup. rewrite <- H. rewrite nth_eq_snoc...
apply store_well_typed_snoc; assumption.
SCase "ST_Ref".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Deref".
SCase "ST_DerefLoc".
exists ST. split; try split...
inversion HST as [_ Hsty].
replace T11 with (store_Tlookup l ST).
apply Hsty...
inversion Ht; subst...
SCase "ST_Deref".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Assign".
SCase "ST_Assign".
exists ST. split; try split...
eapply assign_pres_store_typing...
inversion Ht1; subst...
SCase "ST_Assign1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
SCase "ST_Assign2".
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Qed.
(** **** Exercise: 3 stars (preservation_informal) *)
(** Write a careful informal proof of the preservation theorem,
concentrating on the [T_App], [T_Deref], [T_Assign], and [T_Ref]
cases.
By induction on the derivation of the type of t.
Just apply the constructor and induction hypothesis.
[] *)
(* ################################### *)
(** ** Progress *)
(** Fortunately, progress for this system is pretty easy to prove; the
proof is very similar to the proof of progress for the STLC, with
a few new cases for the new syntactic constructs. *)
Theorem progress : forall ST t T st,
empty; ST |- t \in T ->
store_well_typed ST st ->
(value t \/ exists t', exists st', t / st ==> t' / st').
Proof with eauto.
intros ST t T st Ht HST. remember (@empty ty) as Gamma.
has_type_cases (induction Ht) Case; subst; try solve by inversion...
Case "T_App".
right. destruct IHHt1 as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve by inversion.
destruct IHHt2 as [Ht2p | Ht2p]...
SSCase "t2 steps".
inversion Ht2p as [t2' [st' Hstep]].
exists (tapp (tabs x T t) t2'). exists st'...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tapp t1' t2). exists st'...
Case "T_Succ".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [ inversion Ht ].
SSCase "t1 is a tnat".
exists (tnat (S n)). exists st...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tsucc t1'). exists st'...
Case "T_Pred".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [inversion Ht ].
SSCase "t1 is a tnat".
exists (tnat (pred n)). exists st...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tpred t1'). exists st'...
Case "T_Mult".
right. destruct IHHt1 as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [inversion Ht1].
destruct IHHt2 as [Ht2p | Ht2p]...
SSCase "t2 is a value".
inversion Ht2p; subst; try solve [inversion Ht2].
exists (tnat (mult n n0)). exists st...
SSCase "t2 steps".
inversion Ht2p as [t2' [st' Hstep]].
exists (tmult (tnat n) t2'). exists st'...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tmult t1' t2). exists st'...
Case "T_If0".
right. destruct IHHt1 as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [inversion Ht1].
destruct n.
SSCase "n = 0". exists t2. exists st...
SSCase "n = S n'". exists t3. exists st...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tif0 t1' t2 t3). exists st'...
Case "T_Ref".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tref t1'). exists st'...
Case "T_Deref".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve by inversion.
eexists. eexists. apply ST_DerefLoc...
inversion Ht; subst. inversion HST; subst.
rewrite <- H...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tderef t1'). exists st'...
Case "T_Assign".
right. destruct IHHt1 as [Ht1p|Ht1p]...
SCase "t1 is a value".
destruct IHHt2 as [Ht2p|Ht2p]...
SSCase "t2 is a value".
inversion Ht1p; subst; try solve by inversion.
eexists. eexists. apply ST_Assign...
inversion HST; subst. inversion Ht1; subst.
rewrite H in H5...
SSCase "t2 steps".
inversion Ht2p as [t2' [st' Hstep]].
exists (tassign t1 t2'). exists st'...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tassign t1' t2). exists st'...
Qed.
(* ################################### *)
(** * References and Nontermination *)
Section RefsAndNontermination.
Import ExampleVariables.
(** We know that the simply typed lambda calculus is _normalizing_,
that is, every well-typed term can be reduced to a value in a
finite number of steps. What about STLC + references?
Surprisingly, adding references causes us to lose the
normalization property: there exist well-typed terms in the STLC +
references which can continue to reduce forever, without ever
reaching a normal form!
How can we construct such a term? The main idea is to make a
function which calls itself. We first make a function which calls
another function stored in a reference cell; the trick is that we
then smuggle in a reference to itself!
<<
(\r:Ref (Unit -> Unit).
r := (\x:Unit.(!r) unit); (!r) unit)
(ref (\x:Unit.unit))
>>
First, [ref (\x:Unit.unit)] creates a reference to a cell of type
[Unit -> Unit]. We then pass this reference as the argument to a
function which binds it to the name [r], and assigns to it the
function (\x:Unit.(!r) unit) -- that is, the function which
ignores its argument and calls the function stored in [r] on the
argument [unit]; but of course, that function is itself! To get
the ball rolling we finally execute this function with [(!r)
unit].
*)
Definition loop_fun :=
tabs x TUnit (tapp (tderef (tvar r)) tunit).
Definition loop :=
tapp
(tabs r (TRef (TArrow TUnit TUnit))
(tseq (tassign (tvar r) loop_fun)
(tapp (tderef (tvar r)) tunit)))
(tref (tabs x TUnit tunit)).
(** This term is well typed: *)
Lemma loop_typeable : exists T, empty; nil |- loop \in T.
Proof with eauto.
eexists. unfold loop. unfold loop_fun.
eapply T_App...
eapply T_Abs...
eapply T_App...
eapply T_Abs. eapply T_App. eapply T_Deref. eapply T_Var.
unfold extend. simpl. reflexivity. auto.
eapply T_Assign.
eapply T_Var. unfold extend. simpl. reflexivity.
eapply T_Abs.
eapply T_App...
eapply T_Deref. eapply T_Var. reflexivity.
Qed.
(** To show formally that the term diverges, we first define the
[step_closure] of the single-step reduction relation, written
[==>+]. This is just like the reflexive step closure of
single-step reduction (which we're been writing [==>*]), except
that it is not reflexive: [t ==>+ t'] means that [t] can reach
[t'] by _one or more_ steps of reduction. *)
Inductive step_closure {X:Type} (R: relation X) : X -> X -> Prop :=
| sc_one : forall (x y : X),
R x y -> step_closure R x y
| sc_step : forall (x y z : X),
R x y ->
step_closure R y z ->
step_closure R x z.
Definition multistep1 := (step_closure step).
Notation "t1 '/' st '==>+' t2 '/' st'" := (multistep1 (t1,st) (t2,st'))
(at level 40, st at level 39, t2 at level 39).
(** Now, we can show that the expression [loop] reduces to the
expression [!(loc 0) unit] and the size-one store [ [r:=(loc 0)]
loop_fun]. *)
(** As a convenience, we introduce a slight variant of the [normalize]
tactic, called [reduce], which tries solving the goal with
[multi_refl] at each step, instead of waiting until the goal can't
be reduced any more. Of course, the whole point is that [loop]
doesn't normalize, so the old [normalize] tactic would just go
into an infinite loop reducing it forever! *)
Ltac print_goal := match goal with |- ?x => idtac x end.
Ltac reduce :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; compute)];
try solve [apply multi_refl]).
Lemma loop_steps_to_loop_fun :
loop / nil ==>*
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil.
Proof with eauto.
unfold loop.
reduce.
Qed.
(** Finally, the latter expression reduces in two steps to itself! *)
Lemma loop_fun_step_self :
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil ==>+
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil.
Proof with eauto.
unfold loop_fun; simpl.
eapply sc_step. apply ST_App1...
eapply sc_one. compute. apply ST_AppAbs...
Qed.
(** **** Exercise: 4 stars (factorial_ref) *)
(** Use the above ideas to implement a factorial function in STLC with
references. (There is no need to prove formally that it really
behaves like the factorial. Just use the example below to make
sure it gives the correct result when applied to the argument
[4].) *)
Definition factorial : tm :=
tabs y TNat (tapp (tabs r (TRef (TArrow TNat TNat))
(tseq (tassign (tvar r) (tabs x TNat (tif0 (tvar x) (tnat 1) (tmult (tvar x)
(tapp (tderef (tvar r)) (tpred (tvar x))))))) (tapp (tderef (tvar r)) (tvar y))))
(tref (tabs x TNat (tnat 1)))).
Lemma factorial_type : empty; nil |- factorial \in (TArrow TNat TNat).
Proof with eauto.
unfold factorial.
repeat econstructor.
Qed.
(** If your definition is correct, you should be able to just
uncomment the example below; the proof should be fully
automatic using the [reduce] tactic. *)
Lemma factorial_4 : exists st,
tapp factorial (tnat 4) / nil ==>* tnat 24 / st.
Proof.
eexists. unfold factorial. reduce.
Qed.
(** [] *)
(* ################################### *)
(** * Additional Exercises *)
(** **** Exercise: 5 stars, optional (garabage_collector) *)
(** Challenge problem: modify our formalization to include an account
of garbage collection, and prove that it satisfies whatever nice
properties you can think to prove about it. *)
(* Use a number to count how many time a space is allocated.
Free the space when the number decreased to zero. *)
(** [] *)
End RefsAndNontermination.
End STLCRef.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=25 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=sclk" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="OFF" width_clock=5 areset clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:14:18:59:15:SJ cbx_altiobuf_bidir 2015:10:14:18:59:15:SJ cbx_altiobuf_in 2015:10:14:18:59:15:SJ cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_altpll 2015:10:14:18:59:15:SJ cbx_cycloneii 2015:10:14:18:59:15:SJ cbx_lpm_add_sub 2015:10:14:18:59:15:SJ cbx_lpm_compare 2015:10:14:18:59:15:SJ cbx_lpm_counter 2015:10:14:18:59:15:SJ cbx_lpm_decode 2015:10:14:18:59:15:SJ cbx_lpm_mux 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_nadder 2015:10:14:18:59:15:SJ cbx_stratix 2015:10:14:18:59:15:SJ cbx_stratixii 2015:10:14:18:59:15:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ cbx_util_mgl 2015:10:14:18:59:15:SJ VERSION_END
//CBXI_INSTANCE_NAME="ROM_sclk_sclk_0_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module sclk_altpll
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
wire wire_pll1_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll1_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll1
(
.activeclock(),
.areset(areset),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(wire_pll1_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 25,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.self_reset_on_loss_lock = "off",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]},
locked = (wire_pll1_locked & pll_lock_sync);
endmodule //sclk_altpll
//VALID FILE
|
// 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9
// 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0
//----------------------------------------------------------------------------------------
//
// The MIT License (MIT)
// Copyright (c) 2016 Enrique Sedano ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify,
// merge, publish, distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be included in all copies
// or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
// PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
// CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
// OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
//----------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------
//
// This module is a member of
// ____ __
// _ __/ __ \__ ______/ /_ __
// | | / / /_/ / / / / __ / / / /
// | |/ / _, _/ /_/ / /_/ / /_/ /
// |___/_/ |_|\__,_/\__,_/\__, /
// /____/ v 0.0 - Development
//
// Module: dpth_alu_top.v
// Version: 0.0
// Description:
// ALU top. Contains the ALU itself and the registers and muxes it requires.
//----------------------------------------------------------------------------------------
`include "defines.vh"
module dpth_alu_top (
//------------------------------
// Top level control signals
//------------------------------
input wire clk,
input wire rst_n,
//------------------------------
// Inputs
//------------------------------
input wire [15:0] rx,
input wire [15:0] m_data,
input wire ld_ir,
input wire ld_ra,
input wire ld_rz,
input wire ld_rn,
//------------------------------
// Outputs
//------------------------------
output reg [15:0] ir,
output wire [15:0] alu_out,
output reg rz,
output reg rn
);
//------------------------------
// Local registers
//------------------------------
reg [15:0] ra;
//------------------------------
// Local wires
//------------------------------
wire [15:0] ir_ext;
wire [15:0] alu_in_a;
reg [15:0] alu_in_b;
wire alu_z;
wire alu_n;
//------------------------------
// Local registers assignments
//------------------------------
always @(negedge rst_n, posedge clk)
begin: p_alu_ir_update
if (rst_n == 1'b0)
ir <= {16{1'b0}};
else if (ld_ir == 1'b1)
ir <= m_data;
end
always @(negedge rst_n, posedge clk)
begin: p_alu_ra_update
if (rst_n == 1'b0)
ra <= {16{1'b0}};
else if (ld_ra == 1'b1)
ra <= rx;
end
always @(negedge rst_n, posedge clk)
begin: p_alu_rz_update
if (rst_n == 1'b0)
rz <= 1'b0;
else if (ld_ir == 1'b1)
rz <= alu_z;
end
always @(negedge rst_n, posedge clk)
begin: p_alu_rn_update
if (rst_n == 1'b0)
rn <= 1'b0;
else if (ld_ir == 1'b1)
rn <= alu_n;
end
//------------------------------
// SELDAT mux
//------------------------------
always @(*)
begin : p_seldat_mux
if (ir[14] == 1'b0)
alu_in_b = m_data;
else if (ir[2] == 1'b0)
alu_in_b = ir_ext;
else
alu_in_b = rx;
end
//------------------------------
// Local wires
//------------------------------
assign ir_ext = {{12{ir[7]}}, ir[6:3]};
//------------------------------
// ALU
//------------------------------
dpth_alu alu (
// Input operands
.in_a ( alu_in_a ),
.in_b ( alu_in_b ),
// Output result
.out ( alu_out ),
// Input control
.op ( ir[1:0] ),
.enable( operate ),
// Output parameters
.z ( alu_z ),
.n ( alu_n )
);
endmodule
//----------------------------------------------------------------------------------------
// Trivia:
//----------------------------------------------------------------------------------------
// 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9
// 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* GMII PHY interface
*/
module gmii_phy_if #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2"
)
(
input wire clk,
input wire rst,
/*
* GMII interface to MAC
*/
output wire mac_gmii_rx_clk,
output wire mac_gmii_rx_rst,
output wire [7:0] mac_gmii_rxd,
output wire mac_gmii_rx_dv,
output wire mac_gmii_rx_er,
output wire mac_gmii_tx_clk,
output wire mac_gmii_tx_rst,
input wire [7:0] mac_gmii_txd,
input wire mac_gmii_tx_en,
input wire mac_gmii_tx_er,
/*
* GMII interface to PHY
*/
input wire phy_gmii_rx_clk,
input wire [7:0] phy_gmii_rxd,
input wire phy_gmii_rx_dv,
input wire phy_gmii_rx_er,
input wire phy_mii_tx_clk,
output wire phy_gmii_tx_clk,
output wire [7:0] phy_gmii_txd,
output wire phy_gmii_tx_en,
output wire phy_gmii_tx_er,
/*
* Control
*/
input wire mii_select
);
ssio_sdr_in #
(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.WIDTH(10)
)
rx_ssio_sdr_inst (
.input_clk(phy_gmii_rx_clk),
.input_d({phy_gmii_rxd, phy_gmii_rx_dv, phy_gmii_rx_er}),
.output_clk(mac_gmii_rx_clk),
.output_q({mac_gmii_rxd, mac_gmii_rx_dv, mac_gmii_rx_er})
);
ssio_sdr_out #
(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(10)
)
tx_ssio_sdr_inst (
.clk(mac_gmii_tx_clk),
.input_d({mac_gmii_txd, mac_gmii_tx_en, mac_gmii_tx_er}),
.output_clk(phy_gmii_tx_clk),
.output_q({phy_gmii_txd, phy_gmii_tx_en, phy_gmii_tx_er})
);
generate
if (TARGET == "XILINX") begin
BUFGMUX
gmii_bufgmux_inst (
.I0(clk),
.I1(phy_mii_tx_clk),
.S(mii_select),
.O(mac_gmii_tx_clk)
);
end else begin
assign mac_gmii_tx_clk = mii_select ? phy_mii_tx_clk : clk;
end
endgenerate
// reset sync
reg [3:0] tx_rst_reg = 4'hf;
assign mac_gmii_tx_rst = tx_rst_reg[0];
always @(posedge mac_gmii_tx_clk or posedge rst) begin
if (rst) begin
tx_rst_reg <= 4'hf;
end else begin
tx_rst_reg <= {1'b0, tx_rst_reg[3:1]};
end
end
reg [3:0] rx_rst_reg = 4'hf;
assign mac_gmii_rx_rst = rx_rst_reg[0];
always @(posedge mac_gmii_rx_clk or posedge rst) begin
if (rst) begin
rx_rst_reg <= 4'hf;
end else begin
rx_rst_reg <= {1'b0, rx_rst_reg[3:1]};
end
end
endmodule
|
// Fetch-Issue Pipeline Register
module iss_pipe_reg
(
input wire clk,
input wire reset,
input wire clr,
input wire enable,
// PC related inputs from fetch stage
input wire[31:0] next_pc_iss_pipe_reg_i,
input wire[31:0] instr_iss_pipe_reg_i,
input wire brn_pred_iss_pipe_reg_i,
input wire[31:0] curr_pc_iss_pipe_reg_i,
input wire[31:0] next_pred_pc_iss_pipe_reg_i,
// Register outputs
output wire[31:0] next_pc_iss_pipe_reg_o,
output wire[31:0] instr_iss_pipe_reg_o,
output wire brn_pred_iss_pipe_reg_o,
output wire[31:0] curr_pc_iss_pipe_reg_o,
output wire[31:0] next_pred_pc_iss_pipe_reg_o
);
reg [31:0] next_pc_iss_pipe_reg;
reg [31:0] instr_iss_pipe_reg;
reg brn_pred_iss_pipe_reg;
reg [31:0] curr_pc_iss_pipe_reg;
reg [31:0] next_pred_pc_iss_pipe_reg;
assign next_pc_iss_pipe_reg_o = next_pc_iss_pipe_reg;
assign instr_iss_pipe_reg_o = instr_iss_pipe_reg;
assign brn_pred_iss_pipe_reg_o = brn_pred_iss_pipe_reg;
assign curr_pc_iss_pipe_reg_o = curr_pc_iss_pipe_reg;
assign next_pred_pc_iss_pipe_reg_o = next_pred_pc_iss_pipe_reg;
always @(posedge clk or posedge reset)
if (reset | clr)
begin
next_pc_iss_pipe_reg <= 31'b0;
instr_iss_pipe_reg <= 31'b0;
brn_pred_iss_pipe_reg <= 31'b0;
curr_pc_iss_pipe_reg <= 31'b0;
next_pred_pc_iss_pipe_reg <= 31'b0;
end
else if (~enable)
begin
next_pc_iss_pipe_reg <= next_pc_iss_pipe_reg_i;
instr_iss_pipe_reg <= instr_iss_pipe_reg_i;
brn_pred_iss_pipe_reg <= brn_pred_iss_pipe_reg_i;
curr_pc_iss_pipe_reg <= curr_pc_iss_pipe_reg_i;
next_pred_pc_iss_pipe_reg <= next_pred_pc_iss_pipe_reg_i;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE SD Card Controller IP Core ////
//// ////
//// sd_data_master.v ////
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// State machine resposible for controlling data transfers ////
//// on 4-bit sd card data interface ////
//// ////
//// Author(s): ////
//// - Marek Czerski, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson ([email protected]) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sd_data_master (
input sd_clk,
input rst,
input start_tx_i,
input start_rx_i,
//Output to SD-Host Reg
output reg d_write_o,
output reg d_read_o,
//To fifo filler
output reg start_tx_fifo_o,
output reg start_rx_fifo_o,
input tx_fifo_empty_i,
input tx_fifo_full_i,
input rx_fifo_full_i,
//SD-DATA_Host
input xfr_complete_i,
input crc_ok_i,
//status output
output reg [`INT_DATA_SIZE-1:0] int_status_o,
input int_status_rst_i
);
reg tx_cycle;
parameter SIZE = 3;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
parameter IDLE = 3'b000;
parameter START_TX_FIFO = 3'b001;
parameter START_RX_FIFO = 3'b010;
parameter DATA_TRANSFER = 3'b100;
reg trans_done;
always @(state or start_tx_i or start_rx_i or tx_fifo_full_i or xfr_complete_i or trans_done)
begin: FSM_COMBO
case(state)
IDLE: begin
if (start_tx_i == 1) begin
next_state <= START_TX_FIFO;
end
else if (start_rx_i == 1) begin
next_state <= START_RX_FIFO;
end
else begin
next_state <= IDLE;
end
end
START_TX_FIFO: begin
if (tx_fifo_full_i == 1 && xfr_complete_i == 0)
next_state <= DATA_TRANSFER;
else
next_state <= START_TX_FIFO;
end
START_RX_FIFO: begin
if (xfr_complete_i == 0)
next_state <= DATA_TRANSFER;
else
next_state <= START_RX_FIFO;
end
DATA_TRANSFER: begin
if (trans_done)
next_state <= IDLE;
else
next_state <= DATA_TRANSFER;
end
default: next_state <= IDLE;
endcase
end
//----------------Seq logic------------
always @(posedge sd_clk or posedge rst)
begin: FSM_SEQ
if (rst) begin
state <= IDLE;
end
else begin
state <= next_state;
end
end
//Output logic-----------------
always @(posedge sd_clk or posedge rst)
begin
if (rst) begin
start_tx_fifo_o <= 0;
start_rx_fifo_o <= 0;
d_write_o <= 0;
d_read_o <= 0;
trans_done <= 0;
tx_cycle <= 0;
int_status_o <= 0;
end
else begin
case(state)
IDLE: begin
start_tx_fifo_o <= 0;
start_rx_fifo_o <= 0;
d_write_o <= 0;
d_read_o <= 0;
trans_done <= 0;
tx_cycle <= 0;
end
START_RX_FIFO: begin
start_rx_fifo_o <= 1;
start_tx_fifo_o <= 0;
tx_cycle <= 0;
d_read_o <= 1;
end
START_TX_FIFO: begin
start_rx_fifo_o <= 0;
start_tx_fifo_o <= 1;
tx_cycle <= 1;
if (tx_fifo_full_i == 1)
d_write_o <= 1;
end
DATA_TRANSFER: begin
d_read_o <= 0;
d_write_o <= 0;
if (tx_cycle) begin
if (tx_fifo_empty_i) begin
if (!trans_done)
int_status_o[`INT_DATA_CFE] <= 1;
trans_done <= 1;
//stop sd_data_serial_host
d_write_o <= 1;
d_read_o <= 1;
end
end
else begin
if (rx_fifo_full_i) begin
if (!trans_done)
int_status_o[`INT_DATA_CFE] <= 1;
trans_done <= 1;
//stop sd_data_serial_host
d_write_o <= 1;
d_read_o <= 1;
end
end
if (xfr_complete_i) begin //Transfer complete
d_write_o <= 0;
d_read_o <= 0;
trans_done <= 1;
if (!crc_ok_i) begin //Wrong CRC and Data line free.
if (!trans_done)
int_status_o[`INT_DATA_CCRCE] <= 1;
end
else if (crc_ok_i) begin //Data Line free
if (!trans_done)
int_status_o[`INT_DATA_CC] <= 1;
end
end
end
endcase
if (int_status_rst_i)
int_status_o<=0;
end
end
endmodule
|
//
// Copyright (c) 2015 Jan Adelsbach <[email protected]>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module pdp1_iot(i_clk, i_rst,
pd_inst, pd_wait, pd_in, pd_out,
bs_stb, bs_adr, bs_pout, bs_pin, bs_dout, bs_din);
input i_clk;
input i_rst;
input [0:17] pd_inst;
output pd_wait;
input [0:17] pd_in;
output [0:17] pd_out;
output reg bs_stb;
output [0:10] bs_adr;
output bs_pout;
input bs_pin;
output [0:17] bs_dout;
input [0:17] bs_din;
wire [0:4] w_inst_op;
wire w_inst_w;
wire w_inst_p;
wire [0:4] w_inst_sop;
wire [0:5] w_inst_dev;
assign w_inst_op = pd_inst[0:4];
assign w_inst_w = pd_inst[5];
assign w_inst_p = pd_inst[6];
assign w_inst_sop = pd_inst[7:11];
assign w_inst_dev = pd_inst[12:17];
reg r_IOH;
reg r_IOP;
assign bs_adr = {w_inst_dev|w_inst_sop};
assign bs_pout = w_inst_p|w_inst_w;
assign pd_wait = r_IOH | ~r_IOP;
always @(posedge i_clk) begin
if(i_rst) begin
r_IOH <= 0;
r_IOP <= 0;
end
else begin
if(bs_pin)
r_IOP <= 1'b1;
if(w_inst_op == `PDP1_OP_IOT) begin
if(~(|{w_inst_dev, w_inst_sop})) begin // IOT 0000
if(r_IOP)
r_IOP <= 1'b0;
end
if(~r_IOH) begin
bs_stb <= 1'b1;
if(w_inst_w|w_inst_p)
r_IOP <= 1'b0;
if(w_inst_w)
r_IOH <= 1'b1;
end
else begin
if(bs_pin)
r_IOH <= 1'b0;
end
end // if (w_inst_op == `PDP1_OP_IOT)
end // else: !if(i_rst)
end // always @ (posedge i_clk)
endmodule // pdp1_iot
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__dlygate4sd2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V |
/**
* $Id: red_pitaya_top.v 1271 2014-02-25 12:32:34Z matej.oblak $
*
* @brief Red Pitaya TOP module. It connects external pins and PS part with
* other application modules.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
/**
* GENERAL DESCRIPTION:
*
* Top module connects PS part with rest of Red Pitaya applications.
*
*
* /-------\
* PS DDR <------> | PS | AXI <-> custom bus
* PS MIO <------> | / | <------------+
* PS CLK -------> | ARM | |
* \-------/ |
* |
* /-------\ |
* -> | SCOPE | <---+
* | \-------/ |
* | |
* /--------\ | /-----\ |
* ADC ---> | | --+-> | | |
* | ANALOG | | DSP | <----+
* DAC <--- | | <---- | | |
* \--------/ ^ \-----/ |
* | |
* | /-------\ |
* -- | ASG | <---+
* \-------/ |
* |
* /--------\ |
* RX ----> | | |
* SATA | DAISY | <-----------------+
* TX <---- | |
* \--------/
* | |
* | |
* (FREE)
*
*
* Inside analog module, ADC data is translated from unsigned neg-slope into
* two's complement. Similar is done on DAC data.
*
* Scope module stores data from ADC into RAM, arbitrary signal generator (ASG)
* sends data from RAM to DAC. MIMO PID uses ADC ADC as input and DAC as its output.
*
* Daisy chain connects with other boards with fast serial link. Data which is
* send and received is at the moment undefined. This is left for the user.
*
*/
module red_pitaya_top (
// PS connections
inout [54-1: 0] FIXED_IO_mio ,
inout FIXED_IO_ps_clk ,
inout FIXED_IO_ps_porb ,
inout FIXED_IO_ps_srstb ,
inout FIXED_IO_ddr_vrn ,
inout FIXED_IO_ddr_vrp ,
// DDR
inout [15-1: 0] DDR_addr ,
inout [ 3-1: 0] DDR_ba ,
inout DDR_cas_n ,
inout DDR_ck_n ,
inout DDR_ck_p ,
inout DDR_cke ,
inout DDR_cs_n ,
inout [ 4-1: 0] DDR_dm ,
inout [32-1: 0] DDR_dq ,
inout [ 4-1: 0] DDR_dqs_n ,
inout [ 4-1: 0] DDR_dqs_p ,
inout DDR_odt ,
inout DDR_ras_n ,
inout DDR_reset_n ,
inout DDR_we_n ,
// Red Pitaya periphery
// ADC
input [16-1: 2] adc_dat_a_i , // ADC CH1
input [16-1: 2] adc_dat_b_i , // ADC CH2
input adc_clk_p_i , // ADC data clock
input adc_clk_n_i , // ADC data clock
output [ 2-1: 0] adc_clk_o , // optional ADC clock source
output adc_cdcs_o , // ADC clock duty cycle stabilizer
// DAC
output [14-1: 0] dac_dat_o , // DAC combined data
output dac_wrt_o , // DAC write
output dac_sel_o , // DAC channel select
output dac_clk_o , // DAC clock
output dac_rst_o , // DAC reset
// PWM DAC
output [ 4-1: 0] dac_pwm_o , // serial PWM DAC
// XADC
input [ 5-1: 0] vinp_i , // voltages p
input [ 5-1: 0] vinn_i , // voltages n
// Expansion connector
inout [ 8-1: 0] exp_p_io ,
inout [ 8-1: 0] exp_n_io ,
// SATA connector
output [ 2-1: 0] daisy_p_o , // line 1 is clock capable
output [ 2-1: 0] daisy_n_o ,
input [ 2-1: 0] daisy_p_i , // line 1 is clock capable
input [ 2-1: 0] daisy_n_i ,
// LED
output [ 8-1: 0] led_o
);
//---------------------------------------------------------------------------------
//
// Connections to PS
wire [ 4-1: 0] fclk ; //[0]-125MHz, [1]-250MHz, [2]-50MHz, [3]-200MHz
wire [ 4-1: 0] frstn ;
wire ps_sys_clk ;
wire ps_sys_rstn ;
wire [ 32-1: 0] ps_sys_addr ;
wire [ 32-1: 0] ps_sys_wdata ;
wire [ 4-1: 0] ps_sys_sel ;
wire ps_sys_wen ;
wire ps_sys_ren ;
wire [ 32-1: 0] ps_sys_rdata ;
wire ps_sys_err ;
wire ps_sys_ack ;
// AXI masters
wire axi1_clk , axi0_clk ;
wire axi1_rstn , axi0_rstn ;
wire [ 32-1: 0] axi1_waddr , axi0_waddr ;
wire [ 64-1: 0] axi1_wdata , axi0_wdata ;
wire [ 8-1: 0] axi1_wsel , axi0_wsel ;
wire axi1_wvalid , axi0_wvalid ;
wire [ 4-1: 0] axi1_wlen , axi0_wlen ;
wire axi1_wfixed , axi0_wfixed ;
wire axi1_werr , axi0_werr ;
wire axi1_wrdy , axi0_wrdy ;
red_pitaya_ps i_ps (
.FIXED_IO_mio ( FIXED_IO_mio ),
.FIXED_IO_ps_clk ( FIXED_IO_ps_clk ),
.FIXED_IO_ps_porb ( FIXED_IO_ps_porb ),
.FIXED_IO_ps_srstb ( FIXED_IO_ps_srstb ),
.FIXED_IO_ddr_vrn ( FIXED_IO_ddr_vrn ),
.FIXED_IO_ddr_vrp ( FIXED_IO_ddr_vrp ),
// DDR
.DDR_addr (DDR_addr ),
.DDR_ba (DDR_ba ),
.DDR_cas_n (DDR_cas_n ),
.DDR_ck_n (DDR_ck_n ),
.DDR_ck_p (DDR_ck_p ),
.DDR_cke (DDR_cke ),
.DDR_cs_n (DDR_cs_n ),
.DDR_dm (DDR_dm ),
.DDR_dq (DDR_dq ),
.DDR_dqs_n (DDR_dqs_n ),
.DDR_dqs_p (DDR_dqs_p ),
.DDR_odt (DDR_odt ),
.DDR_ras_n (DDR_ras_n ),
.DDR_reset_n (DDR_reset_n ),
.DDR_we_n (DDR_we_n ),
.fclk_clk_o (fclk ),
.fclk_rstn_o (frstn ),
// ADC analog inputs
.vinp_i (vinp_i ), // voltages p
.vinn_i (vinn_i ), // voltages n
// system read/write channel
.sys_clk_o (ps_sys_clk ), // system clock
.sys_rstn_o (ps_sys_rstn ), // system reset - active low
.sys_addr_o (ps_sys_addr ), // system read/write address
.sys_wdata_o (ps_sys_wdata), // system write data
.sys_sel_o (ps_sys_sel ), // system write byte select
.sys_wen_o (ps_sys_wen ), // system write enable
.sys_ren_o (ps_sys_ren ), // system read enable
.sys_rdata_i (ps_sys_rdata), // system read data
.sys_err_i (ps_sys_err ), // system error indicator
.sys_ack_i (ps_sys_ack ), // system acknowledge signal
// AXI masters
.axi1_clk_i (axi1_clk ), .axi0_clk_i (axi0_clk ), // global clock
.axi1_rstn_i (axi1_rstn ), .axi0_rstn_i (axi0_rstn ), // global reset
.axi1_waddr_i (axi1_waddr ), .axi0_waddr_i (axi0_waddr ), // system write address
.axi1_wdata_i (axi1_wdata ), .axi0_wdata_i (axi0_wdata ), // system write data
.axi1_wsel_i (axi1_wsel ), .axi0_wsel_i (axi0_wsel ), // system write byte select
.axi1_wvalid_i (axi1_wvalid ), .axi0_wvalid_i (axi0_wvalid ), // system write data valid
.axi1_wlen_i (axi1_wlen ), .axi0_wlen_i (axi0_wlen ), // system write burst length
.axi1_wfixed_i (axi1_wfixed ), .axi0_wfixed_i (axi0_wfixed ), // system write burst type (fixed / incremental)
.axi1_werr_o (axi1_werr ), .axi0_werr_o (axi0_werr ), // system write error
.axi1_wrdy_o (axi1_wrdy ), .axi0_wrdy_o (axi0_wrdy ) // system write ready
);
////////////////////////////////////////////////////////////////////////////////
// system bus decoder & multiplexer (it breaks memory addresses into 8 regions)
////////////////////////////////////////////////////////////////////////////////
wire sys_clk = ps_sys_clk ;
wire sys_rstn = ps_sys_rstn ;
wire [ 32-1: 0] sys_addr = ps_sys_addr ;
wire [ 32-1: 0] sys_wdata = ps_sys_wdata;
wire [ 4-1: 0] sys_sel = ps_sys_sel ;
wire [8 -1: 0] sys_wen ;
wire [8 -1: 0] sys_ren ;
wire [8*32-1: 0] sys_rdata ;
wire [8* 1-1: 0] sys_err ;
wire [8* 1-1: 0] sys_ack ;
wire [8 -1: 0] sys_cs ;
assign sys_cs = 8'h01 << sys_addr[22:20];
assign sys_wen = sys_cs & {8{ps_sys_wen}};
assign sys_ren = sys_cs & {8{ps_sys_ren}};
assign ps_sys_rdata = sys_rdata[sys_addr[22:20]*32+:32];
assign ps_sys_err = |(sys_cs & sys_err);
assign ps_sys_ack = |(sys_cs & sys_ack);
// unused system bus slave ports
assign sys_rdata[5*32+:32] = 32'h0;
assign sys_err [5 ] = 1'b0;
assign sys_ack [5 ] = 1'b1;
assign sys_rdata[6*32+:32] = 32'h0;
assign sys_err [6 ] = 1'b0;
assign sys_ack [6 ] = 1'b1;
assign sys_rdata[7*32+:32] = 32'h0;
assign sys_err [7 ] = 1'b0;
assign sys_ack [7 ] = 1'b1;
////////////////////////////////////////////////////////////////////////////////
// local signals
////////////////////////////////////////////////////////////////////////////////
// PLL signals
wire adc_clk_in;
wire pll_adc_clk;
wire pll_dac_clk_1x;
wire pll_dac_clk_2x;
wire pll_dac_clk_2p;
wire pll_ser_clk;
wire pll_pwm_clk;
wire pll_locked;
// fast serial signals
wire ser_clk ;
// PWM clock and reset
wire pwm_clk ;
reg pwm_rstn;
// ADC signals
wire adc_clk;
reg adc_rstn;
reg [14-1:0] adc_dat_a, adc_dat_b;
wire signed [14-1:0] adc_a , adc_b ;
// DAC signals
wire dac_clk_1x;
wire dac_clk_2x;
wire dac_clk_2p;
reg dac_rst;
reg [14-1:0] dac_dat_a, dac_dat_b;
wire [14-1:0] dac_a , dac_b ;
// ASG
wire signed [14-1:0] asg_a , asg_b ;
// configuration
wire digital_loop;
////////////////////////////////////////////////////////////////////////////////
// PLL (clock and reaset)
////////////////////////////////////////////////////////////////////////////////
// diferential clock input
IBUFDS i_clk (.I (adc_clk_p_i), .IB (adc_clk_n_i), .O (adc_clk_in)); // differential clock input
red_pitaya_pll pll (
// inputs
.clk (adc_clk_in), // clock
.rstn (frstn[0] ), // reset - active low
// output clocks
.clk_adc (pll_adc_clk ), // ADC clock
.clk_dac_1x (pll_dac_clk_1x), // DAC clock 125MHz
.clk_dac_2x (pll_dac_clk_2x), // DAC clock 250MHz
.clk_dac_2p (pll_dac_clk_2p), // DAC clock 250MHz -45DGR
.clk_ser (pll_ser_clk ), // fast serial clock
.clk_pwm (pll_pwm_clk ), // PWM clock
// status outputs
.pll_locked (pll_locked)
);
BUFG bufg_adc_clk (.O (adc_clk ), .I (pll_adc_clk ));
BUFG bufg_dac_clk_1x (.O (dac_clk_1x), .I (pll_dac_clk_1x));
BUFG bufg_dac_clk_2x (.O (dac_clk_2x), .I (pll_dac_clk_2x));
BUFG bufg_dac_clk_2p (.O (dac_clk_2p), .I (pll_dac_clk_2p));
BUFG bufg_ser_clk (.O (ser_clk ), .I (pll_ser_clk ));
BUFG bufg_pwm_clk (.O (pwm_clk ), .I (pll_pwm_clk ));
// ADC reset (active low)
always @(posedge adc_clk)
adc_rstn <= frstn[0] & pll_locked;
// DAC reset (active high)
always @(posedge dac_clk_1x)
dac_rst <= ~frstn[0] | ~pll_locked;
// PWM reset (active low)
always @(posedge pwm_clk)
pwm_rstn <= frstn[0] & pll_locked;
////////////////////////////////////////////////////////////////////////////////
// ADC IO
////////////////////////////////////////////////////////////////////////////////
// generating ADC clock is disabled
assign adc_clk_o = 2'b10;
//ODDR i_adc_clk_p ( .Q(adc_clk_o[0]), .D1(1'b1), .D2(1'b0), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));
//ODDR i_adc_clk_n ( .Q(adc_clk_o[1]), .D1(1'b0), .D2(1'b1), .C(fclk[0]), .CE(1'b1), .R(1'b0), .S(1'b0));
// ADC clock duty cycle stabilizer is enabled
assign adc_cdcs_o = 1'b1 ;
// IO block registers should be used here
// lowest 2 bits reserved for 16bit ADC
always @(posedge adc_clk)
begin
adc_dat_a <= adc_dat_a_i[16-1:2];
adc_dat_b <= adc_dat_b_i[16-1:2];
end
// transform into 2's complement (negative slope)
assign adc_a = digital_loop ? dac_a : {adc_dat_a[14-1], ~adc_dat_a[14-2:0]};
assign adc_b = digital_loop ? dac_b : {adc_dat_b[14-1], ~adc_dat_b[14-2:0]};
////////////////////////////////////////////////////////////////////////////////
// DAC IO
////////////////////////////////////////////////////////////////////////////////
// output registers + signed to unsigned (also to negative slope)
always @(posedge dac_clk_1x)
begin
dac_dat_a <= {dac_a[14-1], ~dac_a[14-2:0]};
dac_dat_b <= {dac_b[14-1], ~dac_b[14-2:0]};
end
// DDR outputs
ODDR oddr_dac_clk (.Q(dac_clk_o), .D1(1'b0 ), .D2(1'b1 ), .C(dac_clk_2p), .CE(1'b1), .R(1'b0 ), .S(1'b0));
ODDR oddr_dac_wrt (.Q(dac_wrt_o), .D1(1'b0 ), .D2(1'b1 ), .C(dac_clk_2x), .CE(1'b1), .R(1'b0 ), .S(1'b0));
ODDR oddr_dac_sel (.Q(dac_sel_o), .D1(1'b1 ), .D2(1'b0 ), .C(dac_clk_1x), .CE(1'b1), .R(dac_rst), .S(1'b0));
ODDR oddr_dac_rst (.Q(dac_rst_o), .D1(dac_rst ), .D2(dac_rst ), .C(dac_clk_1x), .CE(1'b1), .R(1'b0 ), .S(1'b0));
ODDR oddr_dac_dat [14-1:0] (.Q(dac_dat_o), .D1(dac_dat_b), .D2(dac_dat_a), .C(dac_clk_1x), .CE(1'b1), .R(dac_rst), .S(1'b0));
//---------------------------------------------------------------------------------
// House Keeping
wire [ 8-1: 0] exp_p_in , exp_n_in ;
wire [ 8-1: 0] exp_p_out, exp_n_out;
wire [ 8-1: 0] exp_p_dir, exp_n_dir;
red_pitaya_hk i_hk (
// system signals
.clk_i ( adc_clk ), // clock
.rstn_i ( adc_rstn ), // reset - active low
// LED
.led_o ( led_o ), // LED output
// global configuration
.digital_loop ( digital_loop ),
// Expansion connector
.exp_p_dat_i ( exp_p_in ), // input data
.exp_p_dat_o ( exp_p_out ), // output data
.exp_p_dir_o ( exp_p_dir ), // 1-output enable
.exp_n_dat_i ( exp_n_in ),
.exp_n_dat_o ( exp_n_out ),
.exp_n_dir_o ( exp_n_dir ),
// System bus
.sys_addr ( sys_addr ), // address
.sys_wdata ( sys_wdata ), // write data
.sys_sel ( sys_sel ), // write byte select
.sys_wen ( sys_wen[0] ), // write enable
.sys_ren ( sys_ren[0] ), // read enable
.sys_rdata ( sys_rdata[ 0*32+31: 0*32] ), // read data
.sys_err ( sys_err[0] ), // error indicator
.sys_ack ( sys_ack[0] ) // acknowledge signal
);
IOBUF i_iobufp [8-1:0] (.O(exp_p_in), .IO(exp_p_io), .I(exp_p_out), .T(~exp_p_dir) );
IOBUF i_iobufn [8-1:0] (.O(exp_n_in), .IO(exp_n_io), .I(exp_n_out), .T(~exp_n_dir) );
//---------------------------------------------------------------------------------
// Oscilloscope application
wire [ 2-1:0] trig_asg_out;
wire trig_scope_out;
wire [14-1: 0] to_scope_a;
wire [14-1: 0] to_scope_b;
wire dsp_trigger;
red_pitaya_scope i_scope (
// ADC
.adc_a_i ( to_scope_a /*adc_a*/ ), // CH 1
.adc_b_i ( to_scope_b /*adc_a*/ ), // CH 2
.adc_clk_i ( adc_clk ), // clock
.adc_rstn_i ( adc_rstn ), // reset - active low
.trig_ext_i ( exp_p_in[0] ), // external trigger
.trig_asg_i ( trig_asg_out ), // ASG trigger
.trig_dsp_i ( dsp_trigger ),
.trig_scope_o ( trig_scope_out ), // scope trigger to feed other instruments
// AXI0 master // AXI1 master
.axi0_clk_o (axi0_clk ), .axi1_clk_o (axi1_clk ),
.axi0_rstn_o (axi0_rstn ), .axi1_rstn_o (axi1_rstn ),
.axi0_waddr_o (axi0_waddr ), .axi1_waddr_o (axi1_waddr ),
.axi0_wdata_o (axi0_wdata ), .axi1_wdata_o (axi1_wdata ),
.axi0_wsel_o (axi0_wsel ), .axi1_wsel_o (axi1_wsel ),
.axi0_wvalid_o (axi0_wvalid), .axi1_wvalid_o (axi1_wvalid),
.axi0_wlen_o (axi0_wlen ), .axi1_wlen_o (axi1_wlen ),
.axi0_wfixed_o (axi0_wfixed), .axi1_wfixed_o (axi1_wfixed),
.axi0_werr_i (axi0_werr ), .axi1_werr_i (axi1_werr ),
.axi0_wrdy_i (axi0_wrdy ), .axi1_wrdy_i (axi1_wrdy ),
// System bus
.sys_addr ( sys_addr ), // address
.sys_wdata ( sys_wdata ), // write data
.sys_sel ( sys_sel ), // write byte select
.sys_wen ( sys_wen[1] ), // write enable
.sys_ren ( sys_ren[1] ), // read enable
.sys_rdata ( sys_rdata[ 1*32+31: 1*32] ), // read data
.sys_err ( sys_err[1] ), // error indicator
.sys_ack ( sys_ack[1] ) // acknowledge signal
);
//---------------------------------------------------------------------------------
// DAC arbitrary signal generator
wire [14-1: 0] asg1phase_o;
red_pitaya_asg i_asg (
// DAC
.dac_a_o ( asg_a ), // CH 1
.dac_b_o ( asg_b ), // CH 2
.dac_clk_i ( adc_clk ), // clock
.dac_rstn_i ( adc_rstn ), // reset - active low
.trig_a_i ( exp_p_in[0] ),
.trig_b_i ( exp_p_in[0] ),
.trig_out_o ( trig_asg_out ),
.trig_scope_i ( trig_scope_out ),
.asg1phase_o ( asg1phase_o ),
// System bus
.sys_addr ( sys_addr ), // address
.sys_wdata ( sys_wdata ), // write data
.sys_sel ( sys_sel ), // write byte select
.sys_wen ( sys_wen[2] ), // write enable
.sys_ren ( sys_ren[2] ), // read enable
.sys_rdata ( sys_rdata[ 2*32+31: 2*32] ), // read data
.sys_err ( sys_err[2] ), // error indicator
.sys_ack ( sys_ack[2] ) // acknowledge signal
);
//---------------------------------------------------------------------------------
// DSP module
red_pitaya_dsp i_dsp (
// signals
.clk_i ( adc_clk ), // clock
.rstn_i ( adc_rstn ), // reset - active low
.dat_a_i ( adc_a ), // in 1
.dat_b_i ( adc_b ), // in 2
.dat_a_o ( dac_a ), // out 1
.dat_b_o ( dac_b ), // out 2
.asg1_i ( asg_a ),
.asg2_i ( asg_b ),
.scope1_o ( to_scope_a ),
.scope2_o ( to_scope_b ),
.asg1phase_i ( asg1phase_o ),
.pwm0 ( pwm_signals[0] ),
.pwm1 ( pwm_signals[1] ),
.pwm2 ( pwm_signals[2] ),
.pwm3 ( pwm_signals[3] ),
.trig_o ( dsp_trigger ),
// System bus
.sys_addr ( sys_addr ), // address
.sys_wdata ( sys_wdata ), // write data
.sys_sel ( sys_sel ), // write byte select
.sys_wen ( sys_wen[3] ), // write enable
.sys_ren ( sys_ren[3] ), // read enable
.sys_rdata ( sys_rdata[ 3*32+31: 3*32] ), // read data
.sys_err ( sys_err[3] ), // error indicator
.sys_ack ( sys_ack[3] ) // acknowledge signal
);
// the ams module has been obsoleted by PWM control via DSP module (outputs)
// and by the fact that RedPitaya has migrated aux. inputs to be PS controlled
// we keep the module to go back to FPGA controlled aux. inputs if needed
//---------------------------------------------------------------------------------
// Analog mixed signals
// XADC and slow PWM DAC control
wire [ 24-1: 0] pwm_cfg_a;
wire [ 24-1: 0] pwm_cfg_b;
wire [ 24-1: 0] pwm_cfg_c;
wire [ 24-1: 0] pwm_cfg_d;
red_pitaya_ams i_ams (
// power test
.clk_i ( adc_clk ), // clock
.rstn_i ( adc_rstn ), // reset - active low
// PWM configuration
.dac_a_o ( pwm_cfg_a ),
.dac_b_o ( pwm_cfg_b ),
.dac_c_o ( pwm_cfg_c ),
.dac_d_o ( pwm_cfg_d ),
.pwm0_i ( pwm_signals[0] ),
.pwm1_i ( pwm_signals[1] ),
// System bus
.sys_addr ( sys_addr ), // address
.sys_wdata ( sys_wdata ), // write data
.sys_sel ( sys_sel ), // write byte select
.sys_wen ( sys_wen[4] ), // write enable
.sys_ren ( sys_ren[4] ), // read enable
.sys_rdata ( sys_rdata[ 4*32+31: 4*32] ), // read data
.sys_err ( sys_err[4] ), // error indicator
.sys_ack ( sys_ack[4] ) // acknowledge signal
);
wire [ 14-1: 0] pwm_signals[4-1:0];
red_pitaya_pwm pwm [4-1:0] (
// system signals
.clk (pwm_clk ),
.rstn (pwm_rstn),
// configuration
.cfg ({pwm_cfg_d, pwm_cfg_c, pwm_cfg_b, pwm_cfg_a}),
//.signal_i ({pwm_signals[3],pwm_signals[2],pwm_signals[1],pwm_signals[0]}),
// PWM outputs
.pwm_o (dac_pwm_o),
.pwm_s ()
);
//---------------------------------------------------------------------------------
// Daisy chain
// simple communication module
assign daisy_p_o = 1'bz;
assign daisy_n_o = 1'bz;
endmodule
|
`timescale 1 ns / 1 ps
module sensor_interface_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 5
)
(
// Users to add ports here
// Register file signals
input wire clk,
input wire mm_en,
input wire mm_wr,
output reg [C_S_AXI_ADDR_WIDTH-1:0] mm_addr,
output reg [C_S_AXI_DATA_WIDTH-1:0] mm_wdata,
input wire [C_S_AXI_DATA_WIDTH-1:0] mm_rdata,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam OPT_MEM_ADDR_BITS = 1;
// Register file signals
reg [C_S_AXI_ADDR_WIDTH-1:0] reg_file [C_S_AXI_DATA_WIDTH-1:0];
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (S_AXI_BREADY && axi_bvalid)
begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK or negedge S_AXI_ARESETN )
begin
if (S_AXI_ARESETN == 1'b1) begin
if (slv_reg_wren)
begin
/*
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
reg_file[axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]][(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
*/
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
mm_addr <= axi_araddr;
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= {mm_rdata[7:0], mm_rdata[15:8], mm_rdata[23:16], mm_rdata[31:24]}; // register read data
end
end
end
// Add user logic here
// User logic ends
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MAJ3_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__MAJ3_PP_BLACKBOX_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MAJ3_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD3_FUNCTIONAL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD3_FUNCTIONAL_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd3 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD3_FUNCTIONAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 11:21:36 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_util_ds_buf_0_0 -prefix
// system_util_ds_buf_0_0_ system_util_ds_buf_0_0_sim_netlist.v
// Design : system_util_ds_buf_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_util_ds_buf_0_0,util_ds_buf,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "util_ds_buf,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_util_ds_buf_0_0
(BUFG_I,
BUFG_O);
(* x_interface_info = "xilinx.com:signal:clock:1.0 BUFG_I CLK" *) input [0:0]BUFG_I;
(* x_interface_info = "xilinx.com:signal:clock:1.0 BUFG_O CLK" *) output [0:0]BUFG_O;
wire [0:0]BUFG_I;
wire [0:0]BUFG_O;
wire [0:0]NLW_U0_BUFGCE_O_UNCONNECTED;
wire [0:0]NLW_U0_BUFG_GT_O_UNCONNECTED;
wire [0:0]NLW_U0_BUFHCE_O_UNCONNECTED;
wire [0:0]NLW_U0_BUFH_O_UNCONNECTED;
wire [0:0]NLW_U0_IBUF_DS_ODIV2_UNCONNECTED;
wire [0:0]NLW_U0_IBUF_OUT_UNCONNECTED;
wire [0:0]NLW_U0_IOBUF_DS_N_UNCONNECTED;
wire [0:0]NLW_U0_IOBUF_DS_P_UNCONNECTED;
wire [0:0]NLW_U0_IOBUF_IO_O_UNCONNECTED;
wire [0:0]NLW_U0_OBUF_DS_N_UNCONNECTED;
wire [0:0]NLW_U0_OBUF_DS_P_UNCONNECTED;
(* C_BUF_TYPE = "BUFG" *)
(* C_SIZE = "1" *)
system_util_ds_buf_0_0_util_ds_buf U0
(.BUFGCE_CE(1'b0),
.BUFGCE_I(1'b0),
.BUFGCE_O(NLW_U0_BUFGCE_O_UNCONNECTED[0]),
.BUFG_GT_CE(1'b0),
.BUFG_GT_CEMASK(1'b0),
.BUFG_GT_CLR(1'b0),
.BUFG_GT_CLRMASK(1'b0),
.BUFG_GT_DIV({1'b0,1'b0,1'b0}),
.BUFG_GT_I(1'b0),
.BUFG_GT_O(NLW_U0_BUFG_GT_O_UNCONNECTED[0]),
.BUFG_I(BUFG_I),
.BUFG_O(BUFG_O),
.BUFHCE_CE(1'b0),
.BUFHCE_I(1'b0),
.BUFHCE_O(NLW_U0_BUFHCE_O_UNCONNECTED[0]),
.BUFH_I(1'b0),
.BUFH_O(NLW_U0_BUFH_O_UNCONNECTED[0]),
.IBUF_DS_N(1'b0),
.IBUF_DS_ODIV2(NLW_U0_IBUF_DS_ODIV2_UNCONNECTED[0]),
.IBUF_DS_P(1'b0),
.IBUF_OUT(NLW_U0_IBUF_OUT_UNCONNECTED[0]),
.IOBUF_DS_N(NLW_U0_IOBUF_DS_N_UNCONNECTED[0]),
.IOBUF_DS_P(NLW_U0_IOBUF_DS_P_UNCONNECTED[0]),
.IOBUF_IO_I(1'b0),
.IOBUF_IO_O(NLW_U0_IOBUF_IO_O_UNCONNECTED[0]),
.IOBUF_IO_T(1'b0),
.OBUF_DS_N(NLW_U0_OBUF_DS_N_UNCONNECTED[0]),
.OBUF_DS_P(NLW_U0_OBUF_DS_P_UNCONNECTED[0]),
.OBUF_IN(1'b0));
endmodule
(* C_BUF_TYPE = "BUFG" *) (* C_SIZE = "1" *)
module system_util_ds_buf_0_0_util_ds_buf
(IBUF_DS_P,
IBUF_DS_N,
IBUF_OUT,
IBUF_DS_ODIV2,
OBUF_IN,
OBUF_DS_P,
OBUF_DS_N,
IOBUF_DS_P,
IOBUF_DS_N,
IOBUF_IO_T,
IOBUF_IO_I,
IOBUF_IO_O,
BUFG_I,
BUFG_O,
BUFGCE_I,
BUFGCE_CE,
BUFGCE_O,
BUFH_I,
BUFH_O,
BUFHCE_I,
BUFHCE_CE,
BUFHCE_O,
BUFG_GT_I,
BUFG_GT_CE,
BUFG_GT_CEMASK,
BUFG_GT_CLR,
BUFG_GT_CLRMASK,
BUFG_GT_DIV,
BUFG_GT_O);
input [0:0]IBUF_DS_P;
input [0:0]IBUF_DS_N;
output [0:0]IBUF_OUT;
output [0:0]IBUF_DS_ODIV2;
input [0:0]OBUF_IN;
output [0:0]OBUF_DS_P;
output [0:0]OBUF_DS_N;
inout [0:0]IOBUF_DS_P;
inout [0:0]IOBUF_DS_N;
input [0:0]IOBUF_IO_T;
input [0:0]IOBUF_IO_I;
output [0:0]IOBUF_IO_O;
input [0:0]BUFG_I;
output [0:0]BUFG_O;
input [0:0]BUFGCE_I;
input [0:0]BUFGCE_CE;
output [0:0]BUFGCE_O;
input [0:0]BUFH_I;
output [0:0]BUFH_O;
input [0:0]BUFHCE_I;
input [0:0]BUFHCE_CE;
output [0:0]BUFHCE_O;
input [0:0]BUFG_GT_I;
input [0:0]BUFG_GT_CE;
input [0:0]BUFG_GT_CEMASK;
input [0:0]BUFG_GT_CLR;
input [0:0]BUFG_GT_CLRMASK;
input [2:0]BUFG_GT_DIV;
output [0:0]BUFG_GT_O;
wire \<const0> ;
wire [0:0]BUFG_I;
wire [0:0]BUFG_O;
assign BUFGCE_O[0] = \<const0> ;
assign BUFG_GT_O[0] = \<const0> ;
assign BUFHCE_O[0] = \<const0> ;
assign BUFH_O[0] = \<const0> ;
assign IBUF_DS_ODIV2[0] = \<const0> ;
assign IBUF_OUT[0] = \<const0> ;
assign IOBUF_IO_O[0] = \<const0> ;
assign OBUF_DS_N[0] = \<const0> ;
assign OBUF_DS_P[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* box_type = "PRIMITIVE" *)
BUFG \USE_BUFG.GEN_BUFG[0].BUFG_U
(.I(BUFG_I),
.O(BUFG_O));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__EINVP_PP_BLACKBOX_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_PP_BLACKBOX_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// General Round Robin Arbiter ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// skar.Wei ////
//// ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// Copyright (C) 2015 skar.Wei<[email protected]> ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//
// copy from wb_conmax
//
//
//
//
//
`include "wb_conbus_defines.v"
module wb_conbus_arb(
clk,
rst,
req,
gnt
);
input clk;
input rst;
input [ 1: 0] req; // Req input
output gnt; // Grant output
//input next; // Next Target
///////////////////////////////////////////////////////////////////////
//
// Parameters
//
parameter grant0 = 1'h0,
grant1 = 1'h1;
///////////////////////////////////////////////////////////////////////
//
// Local Registers and Wires
//
reg state = 0, next_state = 0;
///////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign gnt = state;
always@(posedge clk or posedge rst)
if(rst) state <= #1 grant0;
else state <= #1 next_state;
///////////////////////////////////////////////////////////////////////
//
// Next State Logic
// - implements round robin arbitration algorithm
// - switches grant if current req is dropped or next is asserted
// - parks at last grant
//
always@(state or req ) begin
next_state = state; // Default Keep State
case(state) // synopsys parallel_case full_case
grant0:
// if this req is dropped or next is asserted, check for other req's
if(!req[0] )
begin
if(req[1]) next_state = grant1;
/*
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
*/
end
grant1:
// if this req is dropped or next is asserted, check for other req's
if(!req[1] ) begin
/*
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
*/
if(req[0]) next_state = grant0;
end
/*
grant2:
// if this req is dropped or next is asserted, check for other req's
if(!req[2] ) begin
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
end
grant3:
// if this req is dropped or next is asserted, check for other req's
if(!req[3] ) begin
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
end
grant4:
// if this req is dropped or next is asserted, check for other req's
if(!req[4] ) begin
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
end
grant5:
// if this req is dropped or next is asserted, check for other req's
if(!req[5] ) begin
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
end
grant6:
// if this req is dropped or next is asserted, check for other req's
if(!req[6] ) begin
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
end
grant7:
// if this req is dropped or next is asserted, check for other req's
if(!req[7] ) begin
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
end*/
endcase
end
endmodule
|
(** * Logic: Logic in Coq *)
Require Export Tactics.
(** In previous chapters, we have seen many examples of factual
claims (_propositions_) and ways of presenting evidence of their
truth (_proofs_). In particular, we have worked extensively with
_equality propositions_ of the form [e1 = e2], with
implications ([P -> Q]), and with quantified propositions ([forall
x, P]). In this chapter, we will see how Coq can be used to carry
out other familiar forms of logical reasoning.
Before diving into details, let's talk a bit about the status of
mathematical statements in Coq. Recall that Coq is a _typed_
language, which means that every sensible expression in its world
has an associated type. Logical claims are no exception: any
statement we might try to prove in Coq has a type, namely [Prop],
the type of _propositions_. We can see this with the [Check]
command: *)
Check 3 = 3.
(* ===> Prop *)
Check forall n m : nat, n + m = m + n.
(* ===> Prop *)
(** Note that all well-formed propositions have type [Prop] in Coq,
regardless of whether they are true or not. Simply _being_ a
proposition is one thing; being _provable_ is something else! *)
Check forall n : nat, n = 2.
(* ===> Prop *)
Check 3 = 4.
(* ===> Prop *)
(** Indeed, propositions don't just have types: they are _first-class
objects_ that can be manipulated in the same ways as the other
entities in Coq's world. So far, we've seen one primary place
that propositions can appear: in [Theorem] (and [Lemma] and
[Example]) declarations. *)
Theorem plus_2_2_is_4 :
2 + 2 = 4.
Proof. reflexivity. Qed.
(** But propositions can be used in many other ways. For example, we
can give a name to a proposition using a [Definition], just as we
have given names to expressions of other sorts. *)
Definition plus_fact : Prop := 2 + 2 = 4.
Check plus_fact.
(* ===> plus_fact : Prop *)
(** We can later use this name in any situation where a proposition is
expected -- for example, as the claim in a [Theorem] declaration. *)
Theorem plus_fact_is_true :
plus_fact.
Proof. reflexivity. Qed.
(** We can also write _parameterized_ propositions -- that is,
functions that take arguments of some type and return a
proposition. For instance, the following function takes a number
and returns a proposition asserting that this number is equal to
three: *)
Definition is_three (n : nat) : Prop :=
n = 3.
Check is_three.
(* ===> nat -> Prop *)
(** In Coq, functions that return propositions are said to define
_properties_ of their arguments. For instance, here's a
polymorphic property defining the familiar notion of an _injective
function_. *)
Definition injective {A B} (f : A -> B) :=
forall x y : A, f x = f y -> x = y.
Lemma succ_inj : injective S.
Proof.
intros n m H. inversion H. reflexivity.
Qed.
(** The equality operator [=] that we have been using so far is also
just a function that returns a [Prop]. The expression [n = m] is
just syntactic sugar for [eq n m], defined using Coq's [Notation]
mechanism. Because [=] can be used with elements of any type, it
is also polymorphic: *)
Check @eq.
(* ===> forall A : Type, A -> A -> Prop *)
(** (Notice that we wrote [@eq] instead of [eq]: The type argument [A]
to [eq] is declared as implicit, so we need to turn off implicit
arguments to see the full type of [eq].) *)
(* ################################################################# *)
(** * Logical Connectives *)
(* ================================================================= *)
(** ** Conjunction *)
(** The _conjunction_ or _logical and_ of propositions [A] and [B] is
written [A /\ B], denoting the claim that both [A] and [B] are
true. *)
Example and_example : 3 + 4 = 7 /\ 2 * 2 = 4.
(** To prove a conjunction, use the [split] tactic. Its effect is to
generate two subgoals, one for each part of the statement: *)
Proof.
split.
- (* 3 + 4 = 7 *) reflexivity.
- (* 2 + 2 = 4 *) reflexivity.
Qed.
(** More generally, the following principle works for any two
propositions [A] and [B]: *)
Lemma and_intro : forall A B : Prop, A -> B -> A /\ B.
Proof.
intros A B HA HB. split.
- apply HA.
- apply HB.
Qed.
(** A logical statement with multiple arrows is just a theorem that
has several hypotheses. Here, [and_intro] says that, for any
propositions [A] and [B], if we assume that [A] is true and we
assume that [B] is true, then [A /\ B] is also true.
Since applying a theorem with hypotheses to some goal has the
effect of generating as many subgoals as there are hypotheses for
that theorem, we can, apply [and_intro] to achieve the same effect
as [split]. *)
Example and_example' : 3 + 4 = 7 /\ 2 * 2 = 4.
Proof.
apply and_intro.
- (* 3 + 4 = 7 *) reflexivity.
- (* 2 + 2 = 4 *) reflexivity.
Qed.
(** **** Exercise: 2 stars (and_exercise) *)
Example and_exercise :
forall n m : nat, n + m = 0 -> n = 0 /\ m = 0.
Proof.
intros. split.
-destruct n.
+ reflexivity.
+ simpl in H. inversion H.
-destruct m.
+ reflexivity.
+ rewrite <- plus_n_Sm in H. inversion H.
Qed.
(** [] *)
(** So much for proving conjunctive statements. To go in the other
direction -- i.e., to _use_ a conjunctive hypothesis to prove
something else -- we employ the [destruct] tactic.
If the proof context contains a hypothesis [H] of the form [A /\
B], writing [destruct H as [HA HB]] will remove [H] from the
context and add two new hypotheses: [HA], stating that [A] is
true, and [HB], stating that [B] is true. For instance: *)
Lemma and_example2 :
forall n m : nat, n = 0 /\ m = 0 -> n + m = 0.
Proof.
intros n m H.
destruct H as [Hn Hm].
rewrite Hn. rewrite Hm.
reflexivity.
Qed.
(** As usual, we can also destruct [H] when we introduce it instead of
introducing and then destructing it: *)
Lemma and_example2' :
forall n m : nat, n = 0 /\ m = 0 -> n + m = 0.
Proof.
intros n m [Hn Hm].
rewrite Hn. rewrite Hm.
reflexivity.
Qed.
(** You may wonder why we bothered packing the two hypotheses [n = 0]
and [m = 0] into a single conjunction, since we could have also
stated the theorem with two separate premises: *)
Lemma and_example2'' :
forall n m : nat, n = 0 -> m = 0 -> n + m = 0.
Proof.
intros n m Hn Hm.
rewrite Hn. rewrite Hm.
reflexivity.
Qed.
(** In this case, there is not much difference between the two
theorems. But it is often necessary to explicitly decompose
conjunctions that arise from intermediate steps in proofs,
especially in bigger developments. Here's a simplified
example: *)
Lemma and_example3 :
forall n m : nat, n + m = 0 -> n * m = 0.
Proof.
intros n m H.
assert (H' : n = 0 /\ m = 0).
{ apply and_exercise. apply H. }
destruct H' as [Hn Hm].
rewrite Hn. reflexivity.
Qed.
(** Another common situation with conjunctions is that we know [A /\
B] but in some context we need just [A] (or just [B]). The
following lemmas are useful in such cases: *)
Lemma proj1 : forall P Q : Prop,
P /\ Q -> P.
Proof.
intros P Q [HP HQ].
apply HP. Qed.
(** **** Exercise: 1 star, optional (proj2) *)
Lemma proj2 : forall P Q : Prop,
P /\ Q -> Q.
Proof.
intros p q [HP HQ]. apply HQ.
Qed.
(** [] *)
(** Finally, we sometimes need to rearrange the order of conjunctions
and/or the grouping of conjuncts in multi-way conjunctions. The
following commutativity and associativity theorems come in handy
in such cases. *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
(* WORKED IN CLASS *)
intros P Q [HP HQ].
split.
- (* left *) apply HQ.
- (* right *) apply HP. Qed.
(** **** Exercise: 2 stars (and_assoc) *)
(** (In the following proof of associativity, notice how the _nested_
intro pattern breaks the hypothesis [H : P /\ (Q /\ R)] down into
[HP : P], [HQ : Q], and [HR : R]. Finish the proof from
there.) *)
Theorem and_assoc : forall P Q R : Prop,
P /\ (Q /\ R) -> (P /\ Q) /\ R.
Proof.
intros P Q R [HP [HQ HR]].
split.
- split.
+ apply HP.
+ apply HQ.
- apply HR.
Qed.
(** [] *)
(** By the way, the infix notation [/\] is actually just syntactic
sugar for [and A B]. That is, [and] is a Coq operator that takes
two propositions as arguments and yields a proposition. *)
Check and.
(* ===> and : Prop -> Prop -> Prop *)
(* ================================================================= *)
(** ** Disjunction *)
(** Another important connective is the _disjunction_, or _logical or_
of two propositions: [A \/ B] is true when either [A] or [B]
is. (Alternatively, we can write [or A B], where [or : Prop ->
Prop -> Prop].)
To use a disjunctive hypothesis in a proof, we proceed by case
analysis, which, as for [nat] or other data types, can be done
with [destruct] or [intros]. Here is an example: *)
Lemma or_example :
forall n m : nat, n = 0 \/ m = 0 -> n * m = 0.
Proof.
(* This pattern implicitly does case analysis on
[n = 0 \/ m = 0] *)
intros n m [Hn | Hm].
- (* Here, [n = 0] *)
rewrite Hn. reflexivity.
- (* Here, [m = 0] *)
rewrite Hm. rewrite <- mult_n_O.
reflexivity.
Qed.
(** We can see in this example that, when we perform case analysis on
a disjunction [A \/ B], we must satisfy two proof obligations,
each showing that the conclusion holds under a different
assumption -- [A] in the first subgoal and [B] in the second.
Note that the case analysis pattern ([Hn | Hm]) allows us to name
the hypothesis that is generated in each subgoal.
Conversely, to show that a disjunction holds, we need to show that
one of its sides does. This is done via two tactics, [left] and
[right]. As their names imply, the first one requires proving the
left side of the disjunction, while the second requires proving
its right side. Here is a trivial use... *)
Lemma or_intro : forall A B : Prop, A -> A \/ B.
Proof.
intros A B HA.
left.
apply HA.
Qed.
(** ... and a slightly more interesting example requiring the use of
both [left] and [right]: *)
Lemma zero_or_succ :
forall n : nat, n = 0 \/ n = S (pred n).
Proof.
intros [|n].
- left. reflexivity.
- right. reflexivity.
Qed.
(** **** Exercise: 1 star (mult_eq_0) *)
Lemma mult_eq_0 :
forall n m, n * m = 0 -> n = 0 \/ m = 0.
Proof.
intros. destruct n.
- left. reflexivity.
- right. destruct m.
+ reflexivity.
+ inversion H.
Qed.
(** [] *)
(** **** Exercise: 1 star (or_commut) *)
Theorem or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros. destruct H.
- right. apply H.
- left. apply H.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Falsehood and Negation *)
(** So far, we have mostly been concerned with proving that certain
things are _true_ -- addition is commutative, appending lists is
associative, etc. Of course, we may also be interested in
_negative_ results, showing that certain propositions are _not_
true. In Coq, such negative statements are expressed with the
negation operator [~].
To see how negation works, recall the discussion of the _principle
of explosion_ from the [Tactics] chapter; it asserts that, if we
assume a contradiction, then any other proposition can be derived.
Following this intuition, we could define [~ P] ("not [P]") as
[forall Q, P -> Q]. Coq actually makes a slightly different
choice, defining [~ P] as [P -> False], where [False] is a
_particular_ contradictory proposition defined in the standard
library. *)
Module MyNot.
Definition not (P:Prop) := P -> False.
Notation "~ x" := (not x) : type_scope.
Check not.
(* ===> Prop -> Prop *)
End MyNot.
(** Since [False] is a contradictory proposition, the principle of
explosion also applies to it. If we get [False] into the proof
context, we can [destruct] it to complete any goal: *)
Theorem ex_falso_quodlibet : forall (P:Prop),
False -> P.
Proof.
(* WORKED IN CLASS *)
intros P contra.
destruct contra. Qed.
(** The Latin _ex falso quodlibet_ means, literally, "from falsehood
follows whatever you like"; this is another common name for the
principle of explosion. *)
(** **** Exercise: 2 stars, optional (not_implies_our_not) *)
(** Show that Coq's definition of negation implies the intuitive one
mentioned above: *)
Fact not_implies_our_not : forall (P:Prop),
~ P -> (forall (Q:Prop), P -> Q).
Proof.
intros. destruct H. apply H0.
Qed.
(** [] *)
(** This is how we use [not] to state that [0] and [1] are different
elements of [nat]: *)
Theorem zero_not_one : ~(0 = 1).
Proof.
intros contra. inversion contra.
Qed.
(** Such inequality statements are frequent enough to warrant a
special notation, [x <> y]: *)
Check (0 <> 1).
(* ===> Prop *)
Theorem zero_not_one' : 0 <> 1.
Proof.
intros H. inversion H.
Qed.
(** It takes a little practice to get used to working with negation in
Coq. Even though you can see perfectly well why a statement
involving negation is true, it can be a little tricky at first to
get things into the right configuration so that Coq can understand
it! Here are proofs of a few familiar facts to get you warmed
up. *)
Theorem not_False :
~ False.
Proof.
unfold not. intros H. destruct H. Qed.
Theorem contradiction_implies_anything : forall P Q : Prop,
(P /\ ~P) -> Q.
Proof.
(* WORKED IN CLASS *)
intros P Q [HP HNA]. unfold not in HNA.
apply HNA in HP. destruct HP. Qed.
Theorem double_neg : forall P : Prop,
P -> ~~P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not. intros G. apply G. apply H. Qed.
(** **** Exercise: 2 stars, advanced, recommended (double_neg_inf) *)
(** Write an informal proof of [double_neg]:
_Theorem_: [P] implies [~~P], for any proposition [P].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars, recommended (contrapositive) *)
Theorem contrapositive : forall P Q : Prop,
(P -> Q) -> (~Q -> ~P).
Proof.
intros. intros H1. destruct H0. apply H. apply H1.
Qed.
(** [] *)
(** **** Exercise: 1 star (not_both_true_and_false) *)
Theorem not_both_true_and_false : forall P : Prop,
~ (P /\ ~P).
Proof.
unfold not. intros. apply H. destruct H. apply H.
Qed.
(** [] *)
(** **** Exercise: 1 star, advanced (informal_not_PNP) *)
(** Write an informal proof (in English) of the proposition [forall P
: Prop, ~(P /\ ~P)]. *)
(* FILL IN HERE *)
(** [] *)
(** Similarly, since inequality involves a negation, it requires a
little practice to be able to work with it fluently. Here is one
useful trick. If you are trying to prove a goal that is
nonsensical (e.g., the goal state is [false = true]), apply
[ex_falso_quodlibet] to change the goal to [False]. This makes it
easier to use assumptions of the form [~P] that may be available
in the context -- in particular, assumptions of the form
[x<>y]. *)
Theorem not_true_is_false : forall b : bool,
b <> true -> b = false.
Proof.
intros [] H.
- (* b = true *)
unfold not in H.
apply ex_falso_quodlibet.
apply H. reflexivity.
- (* b = false *)
reflexivity.
Qed.
(** Since reasoning with [ex_falso_quodlibet] is quite common, Coq
provides a built-in tactic, [exfalso], for applying it. *)
Theorem not_true_is_false' : forall b : bool,
b <> true -> b = false.
Proof.
intros [] H.
- (* b = false *)
unfold not in H.
exfalso. (* <=== *)
apply H. reflexivity.
- (* b = true *) reflexivity.
Qed.
(* ================================================================= *)
(** ** Truth *)
(** Besides [False], Coq's standard library also defines [True], a
proposition that is trivially true. To prove it, we use the
predefined constant [I : True]: *)
Lemma True_is_true : True.
Proof. apply I. Qed.
(** Unlike [False], which is used extensively, [True] is used quite
rarely, since it is trivial (and therefore uninteresting) to prove
as a goal, and it carries no useful information as a hypothesis.
But it can be quite useful when defining complex [Prop]s using
conditionals or as a parameter to higher-order [Prop]s. We will
see some examples such uses of [True] later on. *)
(* ================================================================= *)
(** ** Logical Equivalence *)
(** The handy "if and only if" connective, which asserts that two
propositions have the same truth value, is just the conjunction of
two implications. *)
Module MyIff.
Definition iff (P Q : Prop) := (P -> Q) /\ (Q -> P).
Notation "P <-> Q" := (iff P Q)
(at level 95, no associativity)
: type_scope.
End MyIff.
Theorem iff_sym : forall P Q : Prop,
(P <-> Q) -> (Q <-> P).
Proof.
(* WORKED IN CLASS *)
intros P Q [HAB HBA].
split.
- (* -> *) apply HBA.
- (* <- *) apply HAB. Qed.
Lemma not_true_iff_false : forall b,
b <> true <-> b = false.
Proof.
(* WORKED IN CLASS *)
intros b. split.
- (* -> *) apply not_true_is_false.
- (* <- *)
intros H. rewrite H. intros H'. inversion H'.
Qed.
(** **** Exercise: 1 star, optional (iff_properties) *)
(** Using the above proof that [<->] is symmetric ([iff_sym]) as
a guide, prove that it is also reflexive and transitive. *)
Theorem iff_refl : forall P : Prop,
P <-> P.
Proof.
(* FILL IN HERE *) Admitted.
Theorem iff_trans : forall P Q R : Prop,
(P <-> Q) -> (Q <-> R) -> (P <-> R).
Proof.
intros. unfold iff. split.
- unfold iff in H. unfold iff in H0. destruct H.
destruct H0. intros. apply H0. apply H. apply H3.
- unfold iff in H. unfold iff in H0. destruct H. destruct H0.
intros. apply H1. apply H2. apply H3.
Qed.
(** [] *)
(** **** Exercise: 3 stars (or_distributes_over_and) *)
Theorem or_distributes_over_and : forall P Q R : Prop,
P \/ (Q /\ R) <-> (P \/ Q) /\ (P \/ R).
Proof.
intros. split.
- intros. split.
+ destruct H.
*left. apply H.
*right. destruct H. apply H.
+ destruct H.
* left. apply H.
* destruct H. right. apply H0.
-intros [[H1P | H1Q] [H2P | H2R]].
+ left. apply H1P.
+ left. apply H1P.
+ left. apply H2P.
+ right. split.
* apply H1Q.
* apply H2R.
Qed.
(** [] *)
(** Some of Coq's tactics treat [iff] statements specially, avoiding
the need for some low-level proof-state manipulation. In
particular, [rewrite] and [reflexivity] can be used with [iff]
statements, not just equalities. To enable this behavior, we need
to import a special Coq library that allows rewriting with other
formulas besides equality: *)
Require Import Coq.Setoids.Setoid.
(** Here is a simple example demonstrating how these tactics work with
[iff]. First, let's prove a couple of basic iff equivalences: *)
Lemma mult_0 : forall n m, n * m = 0 <-> n = 0 \/ m = 0.
Proof.
split.
- apply mult_eq_0.
- apply or_example.
Qed.
Lemma or_assoc :
forall P Q R : Prop, P \/ (Q \/ R) <-> (P \/ Q) \/ R.
Proof.
intros P Q R. split.
- intros [H | [H | H]].
+ left. left. apply H.
+ left. right. apply H.
+ right. apply H.
- intros [[H | H] | H].
+ left. apply H.
+ right. left. apply H.
+ right. right. apply H.
Qed.
(** We can now use these facts with [rewrite] and [reflexivity] to
give smooth proofs of statements involving equivalences. Here is
a ternary version of the previous [mult_0] result: *)
Lemma mult_0_3 :
forall n m p, n * m * p = 0 <-> n = 0 \/ m = 0 \/ p = 0.
Proof.
intros n m p.
rewrite mult_0. rewrite mult_0. rewrite or_assoc.
reflexivity.
Qed.
(** The [apply] tactic can also be used with [<->]. When given an
equivalence as its argument, [apply] tries to guess which side of
the equivalence to use. *)
Lemma apply_iff_example :
forall n m : nat, n * m = 0 -> n = 0 \/ m = 0.
Proof.
intros n m H. apply mult_0. apply H.
Qed.
(* ================================================================= *)
(** ** Existential Quantification *)
(** Another important logical connective is _existential
quantification_. To say that there is some [x] of type [T] such
that some property [P] holds of [x], we write [exists x : T,
P]. As with [forall], the type annotation [: T] can be omitted if
Coq is able to infer from the context what the type of [x] should
be.
To prove a statement of the form [exists x, P], we must show that
[P] holds for some specific choice of value for [x], known as the
_witness_ of the existential. This is done in two steps: First,
we explicitly tell Coq which witness [t] we have in mind by
invoking the tactic [exists t]; then we prove that [P] holds after
all occurrences of [x] are replaced by [t]. Here is an example: *)
Lemma four_is_even : exists n : nat, 4 = n + n.
Proof.
exists 2. reflexivity.
Qed.
(** Conversely, if we have an existential hypothesis [exists x, P] in
the context, we can destruct it to obtain a witness [x] and a
hypothesis stating that [P] holds of [x]. *)
Theorem exists_example_2 : forall n,
(exists m, n = 4 + m) ->
(exists o, n = 2 + o).
Proof.
intros n [m Hm].
exists (2 + m).
apply Hm. Qed.
(** **** Exercise: 1 star (dist_not_exists) *)
(** Prove that "[P] holds for all [x]" implies "there is no [x] for
which [P] does not hold." *)
Theorem dist_not_exists : forall (X:Type) (P : X -> Prop),
(forall x, P x) -> ~ (exists x, ~ P x).
Proof.
unfold not. intros. destruct H0. apply H0 in H. apply H.
Qed.
(** [] *)
(** **** Exercise: 2 stars (dist_exists_or) *)
(** Prove that existential quantification distributes over
disjunction. *)
Theorem dist_exists_or : forall (X:Type) (P Q : X -> Prop),
(exists x, P x \/ Q x) <-> (exists x, P x) \/ (exists x, Q x).
Proof.
intros. split.
- intros H. destruct H. destruct H.
+ left. exists x. apply H.
+ right. exists x. apply H.
- intros H. destruct H.
+ destruct H. exists x. left. apply H.
+ destruct H. exists x. right. apply H.
Qed.
(** [] *)
(* ################################################################# *)
(** * Programming with Propositions *)
(** The logical connectives that we have seen provide a rich
vocabulary for defining complex propositions from simpler ones.
To illustrate, let's look at how to express the claim that an
element [x] occurs in a list [l]. Notice that this property has a
simple recursive structure:
- If [l] is the empty list, then [x] cannot occur on it, so the
property "[x] appears in [l]" is simply false.
- Otherwise, [l] has the form [x' :: l']. In this case, [x]
occurs in [l] if either it is equal to [x'] or it occurs in
[l']. *)
(** We can translate this directly into a straightforward Coq
function, [In]. (It can also be found in the Coq standard
library.) *)
Fixpoint In {A : Type} (x : A) (l : list A) : Prop :=
match l with
| [] => False
| x' :: l' => x' = x \/ In x l'
end.
(** When [In] is applied to a concrete list, it expands into a
concrete sequence of nested conjunctions. *)
Example In_example_1 : In 4 [3; 4; 5].
Proof.
simpl. right. left. reflexivity.
Qed.
Example In_example_2 :
forall n, In n [2; 4] ->
exists n', n = 2 * n'.
Proof.
simpl.
intros n [H | [H | []]].
- exists 1. rewrite <- H. reflexivity.
- exists 2. rewrite <- H. reflexivity.
Qed.
(** (Notice the use of the empty pattern to discharge the last case
_en passant_.) *)
(** We can also prove more generic, higher-level lemmas about [In].
Note, in the next, how [In] starts out applied to a variable and
only gets expanded when we do case analysis on this variable: *)
Lemma In_map :
forall (A B : Type) (f : A -> B) (l : list A) (x : A),
In x l ->
In (f x) (map f l).
Proof.
intros A B f l x.
induction l as [|x' l' IHl'].
- (* l = nil, contradiction *)
simpl. intros [].
- (* l = x' :: l' *)
simpl. intros [H | H].
+ rewrite H. left. reflexivity.
+ right. apply IHl'. apply H.
Qed.
(** This way of defining propositions, though convenient in some
cases, also has some drawbacks. In particular, it is subject to
Coq's usual restrictions regarding the definition of recursive
functions, e.g., the requirement that they be "obviously
terminating." In the next chapter, we will see how to define
propositions _inductively_, a different technique with its own set
of strengths and limitations. *)
(** **** Exercise: 2 stars (In_map_iff) *)
Lemma In_map_iff :
forall (A B : Type) (f : A -> B) (l : list A) (y : B),
In y (map f l) <->
exists x, f x = y /\ In x l.
Proof.
split.
-induction l as [| h t IHl].
+ intros. inversion H.
+ intros. simpl. simpl in H. admit.
- admit.
Qed.
(** [] *)
(** **** Exercise: 2 stars (in_app_iff) *)
Lemma in_app_iff : forall A l l' (a:A),
In a (l++l') <-> In a l \/ In a l'.
Proof.
split.
- intros. induction l as [|h t IHl].
+ simpl in H. right. apply H.
+ simpl in H. simpl. destruct H.
* left. left. apply H.
* apply or_assoc. right. apply IHl. apply H.
- intros. induction l as [|h t IHl].
+ simpl. simpl in H. destruct H.
* inversion H.
* apply H.
+ simpl in H. simpl. apply or_assoc in H. destruct H.
* left. apply H.
* right. apply IHl in H. apply H.
Qed.
(** [] *)
(** **** Exercise: 3 stars (All) *)
(** Recall that functions returning propositions can be seen as
_properties_ of their arguments. For instance, if [P] has type
[nat -> Prop], then [P n] states that property [P] holds of [n].
Drawing inspiration from [In], write a recursive function [All]
stating that some property [P] holds of all elements of a list
[l]. To make sure your definition is correct, prove the [All_In]
lemma below. (Of course, your definition should _not_ just
restate the left-hand side of [All_In].) *)
Fixpoint All {T} (P : T -> Prop) (l : list T) : Prop :=
match l with
| [] => True
| h :: t => (P h) /\ (All P t)
end.
Lemma All_In :
forall T (P : T -> Prop) (l : list T),
(forall x, In x l -> P x) <->
All P l.
Proof.
intros. split.
- intros. induction l as [|x l' IHl].
+ simpl. apply I.
+ simpl. split.
* apply H. simpl. left. reflexivity.
* apply IHl. simpl in H. intros. apply H. right. apply H0.
- induction l as [|h l' IHl].
+ intros. simpl in H0. inversion H0.
+ intros. simpl in H,H0. destruct H0.
* destruct H. rewrite H0 in H. apply H.
* destruct H. apply IHl in H0.
{ apply H0. }
{ apply H1. }
Qed. (** [] *)
(** **** Exercise: 3 stars (combine_odd_even) *)
(** Complete the definition of the [combine_odd_even] function below.
It takes as arguments two properties of numbers, [Podd] and
[Peven], and it should return a property [P] such that [P n] is
equivalent to [Podd n] when [n] is odd and equivalent to [Peven n]
otherwise. *)
Definition combine_odd_even (Podd Peven : nat -> Prop) : nat -> Prop
(* REPLACE THIS LINE WITH := _your_definition_ . *) . Admitted.
(** To test your definition, prove the following facts: *)
Theorem combine_odd_even_intro :
forall (Podd Peven : nat -> Prop) (n : nat),
(oddb n = true -> Podd n) ->
(oddb n = false -> Peven n) ->
combine_odd_even Podd Peven n.
Proof.
(* FILL IN HERE *) Admitted.
Theorem combine_odd_even_elim_odd :
forall (Podd Peven : nat -> Prop) (n : nat),
combine_odd_even Podd Peven n ->
oddb n = true ->
Podd n.
Proof.
(* FILL IN HERE *) Admitted.
Theorem combine_odd_even_elim_even :
forall (Podd Peven : nat -> Prop) (n : nat),
combine_odd_even Podd Peven n ->
oddb n = false ->
Peven n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Applying Theorems to Arguments *)
(** One feature of Coq that distinguishes it from many other proof
assistants is that it treats _proofs_ as first-class objects.
There is a great deal to be said about this, but it is not
necessary to understand it in detail in order to use Coq. This
section gives just a taste, while a deeper exploration can be
found in the optional chapters [ProofObjects] and
[IndPrinciples]. *)
(** We have seen that we can use the [Check] command to ask Coq to
print the type of an expression. We can also use [Check] to ask
what theorem a particular identifier refers to. *)
Check plus_comm.
(* ===> forall n m : nat, n + m = m + n *)
(** Coq prints the _statement_ of the [plus_comm] theorem in the same
way that it prints the _type_ of any term that we ask it to
[Check]. Why?
The reason is that the identifier [plus_comm] actually refers to a
_proof object_ -- a data structure that represents a logical
derivation establishing of the truth of the statement [forall n m
: nat, n + m = m + n]. The type of this object _is_ the statement
of the theorem that it is a proof of.
Intuitively, this makes sense because the statement of a theorem
tells us what we can use that theorem for, just as the type of a
computational object tells us what we can do with that object --
e.g., if we have a term of type [nat -> nat -> nat], we can give
it two [nat]s as arguments and get a [nat] back. Similarly, if we
have an object of type [n = m -> n + n = m + m] and we provide it
an "argument" of type [n = m], we can derive [n + n = m + m].
Operationally, this analogy goes even further: by applying a
theorem, as if it were a function, to hypotheses with matching
types, we can specialize its result without having to resort to
intermediate assertions. For example, suppose we wanted to prove
the following result: *)
Lemma plus_comm3 :
forall n m p, n + (m + p) = (p + m) + n.
(** It appears at first sight that we ought to be able to prove this
by rewriting with [plus_comm] twice to make the two sides match.
The problem, however, is that the second [rewrite] will undo the
effect of the first. *)
Proof.
intros n m p.
rewrite plus_comm.
rewrite plus_comm.
(* We are back where we started... *)
(** One simple way of fixing this problem, using only tools that we
already know, is to use [assert] to derive a specialized version
of [plus_comm] that can be used to rewrite exactly where we
want. *)
rewrite plus_comm.
assert (H : m + p = p + m).
{ rewrite plus_comm. reflexivity. }
rewrite H.
reflexivity.
Qed.
(** A more elegant alternative is to apply [plus_comm] directly to the
arguments we want to instantiate it with, in much the same way as
we apply a polymorphic function to a type argument. *)
Lemma plus_comm3_take2 :
forall n m p, n + (m + p) = (p + m) + n.
Proof.
intros n m p.
rewrite plus_comm.
rewrite (plus_comm m).
reflexivity.
Qed.
(** You can "use theorems as functions" in this way with almost all
tactics that take a theorem name as an argument. Note also that
theorem application uses the same inference mechanisms as function
application; thus, it is possible, for example, to supply
wildcards as arguments to be inferred, or to declare some
hypotheses to a theorem as implicit by default. These features
are illustrated in the proof below. *)
Example lemma_application_ex :
forall {n : nat} {ns : list nat},
In n (map (fun m => m * 0) ns) ->
n = 0.
Proof.
intros n ns H.
destruct (proj1 _ _ (In_map_iff _ _ _ _ _) H)
as [m [Hm _]].
rewrite mult_0_r in Hm. rewrite <- Hm. reflexivity.
Qed.
(** We will see many more examples of the idioms from this section in
later chapters. *)
(* ################################################################# *)
(** * Coq vs. Set Theory *)
(** Coq's logical core, the _Calculus of Inductive Constructions_,
differs in some important ways from other formal systems that are
used by mathematicians for writing down precise and rigorous
proofs. For example, in the most popular foundation for
mainstream paper-and-pencil mathematics, Zermelo-Fraenkel Set
Theory (ZFC), a mathematical object can potentially be a member of
many different sets; a term in Coq's logic, on the other hand, is
a member of at most one type. This difference often leads to
slightly different ways of capturing informal mathematical
concepts, though these are by and large quite natural and easy to
work with. For example, instead of saying that a natural number
[n] belongs to the set of even numbers, we would say in Coq that
[ev n] holds, where [ev : nat -> Prop] is a property describing
even numbers.
However, there are some cases where translating standard
mathematical reasoning into Coq can be either cumbersome or
sometimes even impossible, unless we enrich the core logic with
additional axioms. We conclude this chapter with a brief
discussion of some of the most significant differences between the
two worlds. *)
(** ** Functional Extensionality
The equality assertions that we have seen so far mostly have
concerned elements of inductive types ([nat], [bool], etc.). But
since Coq's equality operator is polymorphic, these are not the
only possibilities -- in particular, we can write propositions
claiming that two _functions_ are equal to each other: *)
Example function_equality_ex : plus 3 = plus (pred 4).
Proof. reflexivity. Qed.
(** In common mathematical practice, two functions [f] and [g] are
considered equal if they produce the same outputs:
(forall x, f x = g x) -> f = g
This is known as the principle of _functional extensionality_.
Informally speaking, an "extensional property" is one that
pertains to an object's observable behavior. Thus, functional
extensionality simply means that a function's identity is
completely determined by what we can observe from it -- i.e., in
Coq terms, the results we obtain after applying it.
Functional extensionality is not part of Coq's basic axioms: the
only way to show that two functions are equal is by
simplification (as we did in the proof of [function_equality_ex]).
But we can add it to Coq's core logic using the [Axiom]
command. *)
Axiom functional_extensionality : forall {X Y: Type}
{f g : X -> Y},
(forall (x:X), f x = g x) -> f = g.
(** Using [Axiom] has the same effect as stating a theorem and
skipping its proof using [Admitted], but it alerts the reader that
this isn't just something we're going to come back and fill in
later!
We can now invoke functional extensionality in proofs: *)
Lemma plus_comm_ext : plus = fun n m => m + n.
Proof.
apply functional_extensionality. intros n.
apply functional_extensionality. intros m.
apply plus_comm.
Qed.
(** Naturally, we must be careful when adding new axioms into Coq's
logic, as they may render it inconsistent -- that is, it may
become possible to prove every proposition, including [False]!
Unfortunately, there is no simple way of telling whether an axiom
is safe: hard work is generally required to establish the
consistency of any particular combination of axioms. Fortunately,
it is known that adding functional extensionality, in particular,
_is_ consistent.
Note that it is possible to check whether a particular proof
relies on any additional axioms, using the [Print Assumptions]
command. For instance, if we run it on [plus_comm_ext], we see
that it uses [functional_extensionality]: *)
Print Assumptions plus_comm_ext.
(* ===>
Axioms:
functional_extensionality :
forall (X Y : Type) (f g : X -> Y),
(forall x : X, f x = g x) -> f = g *)
(** **** Exercise: 5 stars (tr_rev) *)
(** One problem with the definition of the list-reversing function
[rev] that we have is that it performs a call to [app] on each
step; running [app] takes time asymptotically linear in the size
of the list, which means that [rev] has quadratic running time.
We can improve this with the following definition: *)
Fixpoint rev_append {X} (l1 l2 : list X) : list X :=
match l1 with
| [] => l2
| x :: l1' => rev_append l1' (x :: l2)
end.
Definition tr_rev {X} (l : list X) : list X :=
rev_append l [].
(** This version is said to be _tail-recursive_, because the recursive
call to the function is the last operation that needs to be
performed (i.e., we don't have to execute [++] after the recursive
call); a decent compiler will generate very efficient code in this
case. Prove that both definitions are indeed equivalent. *)
Lemma tr_rev_correct : forall X, @tr_rev X = @rev X.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Propositions and Booleans *)
(** We've seen that Coq has two different ways of encoding logical
facts: with _booleans_ (of type [bool]), and with
_propositions_ (of type [Prop]). For instance, to claim that a
number [n] is even, we can say either (1) that [evenb n] returns
[true] or (2) that there exists some [k] such that [n = double k].
Indeed, these two notions of evenness are equivalent, as can
easily be shown with a couple of auxiliary lemmas (one of which is
left as an exercise).
We often say that the boolean [evenb n] _reflects_ the proposition
[exists k, n = double k]. *)
Theorem evenb_double : forall k, evenb (double k) = true.
Proof.
intros k. induction k as [|k' IHk'].
- reflexivity.
- simpl. apply IHk'.
Qed.
(** **** Exercise: 3 stars (evenb_double_conv) *)
Theorem evenb_double_conv : forall n,
exists k, n = if evenb n then double k
else S (double k).
Proof.
(* Hint: Use the [evenb_S] lemma from [Induction.v]. *)
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem even_bool_prop : forall n,
evenb n = true <-> exists k, n = double k.
Proof.
intros n. split.
- intros H. destruct (evenb_double_conv n) as [k Hk].
rewrite Hk. rewrite H. exists k. reflexivity.
- intros [k Hk]. rewrite Hk. apply evenb_double.
Qed.
(** Similarly, to state that two numbers [n] and [m] are equal, we can
say either (1) that [beq_nat n m] returns [true] or (2) that [n =
m]. These two notions are equivalent. *)
Theorem beq_nat_true_iff : forall n1 n2 : nat,
beq_nat n1 n2 = true <-> n1 = n2.
Proof.
intros n1 n2. split.
- apply beq_nat_true.
- intros H. rewrite H. rewrite <- beq_nat_refl. reflexivity.
Qed.
(** However, while the boolean and propositional formulations of a
claim are equivalent from a purely logical perspective, we have
also seen that they need not be equivalent _operationally_.
Equality provides an extreme example: knowing that [beq_nat n m =
true] is generally of little help in the middle of a proof
involving [n] and [m]; however, if we convert the statement to the
equivalent form [n = m], we can rewrite with it.
The case of even numbers is also interesting. Recall that, when
proving the backwards direction of
[even_bool_prop] ([evenb_double], going from the propositional to
the boolean claim), we used a simple induction on [k]). On the
other hand, the converse (the [evenb_double_conv] exercise)
required a clever generalization, since we can't directly prove
[(exists k, n = double k) -> evenb n = true].
For these examples, the propositional claims were more useful than
their boolean counterparts, but this is not always the case. For
instance, we cannot test whether a general proposition is true or
not in a function definition; as a consequence, the following code
fragment is rejected: *)
Fail Definition is_even_prime n :=
if n = 2 then true
else false.
(** Coq complains that [n = 2] has type [Prop], while it expects an
elements of [bool] (or some other inductive type with two
elements). The reason for this error message has to do with the
_computational_ nature of Coq's core language, which is designed
so that every function that it can express is computable and
total. One reason for this is to allow the extraction of
executable programs from Coq developments. As a consequence,
[Prop] in Coq does _not_ have a universal case analysis operation
telling whether any given proposition is true or false, since such
an operation would allow us to write non-computable functions.
Although general non-computable properties cannot be phrased as
boolean computations, it is worth noting that even many
_computable_ properties are easier to express using [Prop] than
[bool], since recursive function definitions are subject to
significant restrictions in Coq. For instance, the next chapter
shows how to define the property that a regular expression matches
a given string using [Prop]. Doing the same with [bool] would
amount to writing a regular expression matcher, which would be
more complicated, harder to understand, and harder to reason
about.
Conversely, an important side benefit of stating facts using
booleans is enabling some proof automation through computation
with Coq terms, a technique known as _proof by
reflection_. Consider the following statement: *)
Example even_1000 : exists k, 1000 = double k.
(** The most direct proof of this fact is to give the value of [k]
explicitly. *)
Proof. exists 500. reflexivity. Qed.
(** On the other hand, the proof of the corresponding boolean
statement is even simpler: *)
Example even_1000' : evenb 1000 = true.
Proof. reflexivity. Qed.
(** What is interesting is that, since the two notions are equivalent,
we can use the boolean formulation to prove the other one without
mentioning 500 explicitly: *)
Example even_1000'' : exists k, 1000 = double k.
Proof. apply even_bool_prop. reflexivity. Qed.
(** Although we haven't gained much in terms of proof size in this
case, larger proofs can often be made considerably simpler by the
use of reflection. As an extreme example, the Coq proof of the
famous _4-color theorem_ uses reflection to reduce the analysis of
hundreds of different cases to a boolean computation. We won't
cover reflection in great detail, but it serves as a good example
showing the complementary strengths of booleans and general
propositions. *)
(** **** Exercise: 2 stars (logical_connectives) *)
(** The following lemmas relate the propositional connectives studied
in this chapter to the corresponding boolean operations. *)
Lemma andb_true_iff : forall b1 b2:bool,
b1 && b2 = true <-> b1 = true /\ b2 = true.
Proof.
(* FILL IN HERE *) Admitted.
Lemma orb_true_iff : forall b1 b2,
b1 || b2 = true <-> b1 = true \/ b2 = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (beq_nat_false_iff) *)
(** The following theorem is an alternate "negative" formulation of
[beq_nat_true_iff] that is more convenient in certain
situations (we'll see examples in later chapters). *)
Theorem beq_nat_false_iff : forall x y : nat,
beq_nat x y = false <-> x <> y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (beq_list) *)
(** Given a boolean operator [beq] for testing equality of elements of
some type [A], we can define a function [beq_list beq] for testing
equality of lists with elements in [A]. Complete the definition
of the [beq_list] function below. To make sure that your
definition is correct, prove the lemma [beq_list_true_iff]. *)
Fixpoint beq_list {A} (beq : A -> A -> bool)
(l1 l2 : list A) : bool
(* REPLACE THIS LINE WITH := _your_definition_ . *) . Admitted.
Lemma beq_list_true_iff :
forall A (beq : A -> A -> bool),
(forall a1 a2, beq a1 a2 = true <-> a1 = a2) ->
forall l1 l2, beq_list beq l1 l2 = true <-> l1 = l2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, recommended (All_forallb) *)
(** Recall the function [forallb], from the exercise
[forall_exists_challenge] in chapter [Tactics]: *)
Fixpoint forallb {X : Type} (test : X -> bool) (l : list X) : bool :=
match l with
| [] => true
| x :: l' => andb (test x) (forallb test l')
end.
(** Prove the theorem below, which relates [forallb] to the [All]
property of the above exercise. *)
Theorem forallb_true_iff : forall X test (l : list X),
forallb test l = true <-> All (fun x => test x = true) l.
Proof.
(* FILL IN HERE *) Admitted.
(** Are there any important properties of the function [forallb] which
are not captured by your specification? *)
(* FILL IN HERE *)
(** [] *)
(* ================================================================= *)
(** ** Classical vs. Constructive Logic *)
(** We have seen that it is not possible to test whether or not a
proposition [P] holds while defining a Coq function. You may be
surprised to learn that a similar restriction applies to _proofs_!
In other words, the following intuitive reasoning principle is not
derivable in Coq: *)
Definition excluded_middle := forall P : Prop,
P \/ ~ P.
(** To understand operationally why this is the case, recall that, to
prove a statement of the form [P \/ Q], we use the [left] and
[right] tactics, which effectively require knowing which side of
the disjunction holds. However, the universally quantified [P] in
[excluded_middle] is an _arbitrary_ proposition, which we know
nothing about. We don't have enough information to choose which
of [left] or [right] to apply, just as Coq doesn't have enough
information to mechanically decide whether [P] holds or not inside
a function. On the other hand, if we happen to know that [P] is
reflected in some boolean term [b], then knowing whether it holds
or not is trivial: we just have to check the value of [b]. This
leads to the following theorem: *)
Theorem restricted_excluded_middle : forall P b,
(P <-> b = true) -> P \/ ~ P.
Proof.
intros P [] H.
- left. rewrite H. reflexivity.
- right. rewrite H. intros contra. inversion contra.
Qed.
(** In particular, the excluded middle is valid for equations [n = m],
between natural numbers [n] and [m].
You may find it strange that the general excluded middle is not
available by default in Coq; after all, any given claim must be
either true or false. Nonetheless, there is an advantage in not
assuming the excluded middle: statements in Coq can make stronger
claims than the analogous statements in standard mathematics.
Notably, if there is a Coq proof of [exists x, P x], it is
possible to explicitly exhibit a value of [x] for which we can
prove [P x] -- in other words, every proof of existence is
necessarily _constructive_. Because of this, logics like Coq's,
which do not assume the excluded middle, are referred to as
_constructive logics_. More conventional logical systems such as
ZFC, in which the excluded middle does hold for arbitrary
propositions, are referred to as _classical_.
The following example illustrates why assuming the excluded middle
may lead to non-constructive proofs: *)
(** _Claim_: There exist irrational numbers [a] and [b] such that [a ^
b] is rational.
_Proof_: It is not difficult to show that [sqrt 2] is irrational.
If [sqrt 2 ^ sqrt 2] is rational, it suffices to take [a = b =
sqrt 2] and we are done. Otherwise, [sqrt 2 ^ sqrt 2] is
irrational. In this case, we can take [a = sqrt 2 ^ sqrt 2] and
[b = sqrt 2], since [a ^ b = sqrt 2 ^ (sqrt 2 * sqrt 2) = sqrt 2 ^
2 = 2]. []
Do you see what happened here? We used the excluded middle to
consider separately the cases where [sqrt 2 ^ sqrt 2] is rational
and where it is not, without knowing which one actually holds!
Because of that, we wind up knowing that such [a] and [b] exist
but we cannot determine what their actual values are (at least,
using this line of argument).
As useful as constructive logic is, it does have its limitations:
There are many statements that can easily be proven in classical
logic but that have much more complicated constructive proofs, and
there are some that are known to have no constructive proof at
all! Fortunately, like functional extensionality, the excluded
middle is known to be compatible with Coq's logic, allowing us to
add it safely as an axiom. However, we will not need to do so in
this book: the results that we cover can be developed entirely
within constructive logic at negligible extra cost.
It takes some practice to understand which proof techniques must
be avoided in constructive reasoning, but arguments by
contradiction, in particular, are infamous for leading to
non-constructive proofs. Here's a typical example: suppose that
we want to show that there exists [x] with some property [P],
i.e., such that [P x]. We start by assuming that our conclusion
is false; that is, [~ exists x, P x]. From this premise, it is not
hard to derive [forall x, ~ P x]. If we manage to show that this
intermediate fact results in a contradiction, we arrive at an
existence proof without ever exhibiting a value of [x] for which
[P x] holds!
The technical flaw here, from a constructive standpoint, is that
we claimed to prove [exists x, P x] using a proof of [~ ~ exists
x, P x]. However, allowing ourselves to remove double negations
from arbitrary statements is equivalent to assuming the excluded
middle, as shown in one of the exercises below. Thus, this line
of reasoning cannot be encoded in Coq without assuming additional
axioms. *)
(** **** Exercise: 3 stars (excluded_middle_irrefutable) *)
(** The consistency of Coq with the general excluded middle axiom
requires complicated reasoning that cannot be carried out within
Coq itself. However, the following theorem implies that it is
always safe to assume a decidability axiom (i.e., an instance of
excluded middle) for any _particular_ Prop [P]. Why? Because we
cannot prove the negation of such an axiom; if we could, we would
have both [~ (P \/ ~P)] and [~ ~ (P \/ ~P)], a contradiction. *)
Theorem excluded_middle_irrefutable: forall (P:Prop),
~ ~ (P \/ ~ P).
Proof.
unfold not. intros P H. apply H. admit.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (not_exists_dist) *)
(** It is a theorem of classical logic that the following two
assertions are equivalent:
~ (exists x, ~ P x)
forall x, P x
The [dist_not_exists] theorem above proves one side of this
equivalence. Interestingly, the other direction cannot be proved
in constructive logic. Your job is to show that it is implied by
the excluded middle. *)
Theorem not_exists_dist :
excluded_middle ->
forall (X:Type) (P : X -> Prop),
~ (exists x, ~ P x) -> (forall x, P x).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (classical_axioms) *)
(** For those who like a challenge, here is an exercise taken from the
Coq'Art book by Bertot and Casteran (p. 123). Each of the
following four statements, together with [excluded_middle], can be
considered as characterizing classical logic. We can't prove any
of them in Coq, but we can consistently add any one of them as an
axiom if we wish to work in classical logic.
Prove that all five propositions (these four plus
[excluded_middle]) are equivalent. *)
Definition peirce := forall P Q: Prop,
((P->Q)->P)->P.
Definition double_negation_elimination := forall P:Prop,
~~P -> P.
Definition de_morgan_not_and_not := forall P Q:Prop,
~(~P /\ ~Q) -> P\/Q.
Definition implies_to_or := forall P Q:Prop,
(P->Q) -> (~P\/Q).
(* FILL IN HERE *)
(** [] *)
(** $Date: 2015-08-11 12:03:04 -0400 (Tue, 11 Aug 2015) $ *)
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*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBEC_P_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__PROBEC_P_PP_SYMBOL_V
/**
* probec_p: Virtual current probe point.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__probec_p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBEC_P_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4B_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__AND4B_PP_BLACKBOX_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4B_PP_BLACKBOX_V
|
//sata_command_layer.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sata_defines.v"
`define RESET_TIMEOUT 32'h00000002
module sata_command_layer (
input rst, //reset
input clk,
input data_in_clk,
input data_out_clk,
//User Interface
output sata_init,
output command_layer_ready,
output reg busy,
input send_sync_escape,
input [15:0] user_features,
//XXX: New Stb
input write_data_en,
input single_rdwr,
input read_data_en,
output dev_error,
input send_user_command_stb,
input soft_reset_en,
output reg pio_data_ready,
input [7:0] command,
input [15:0] sector_count,
input [47:0] sector_address,
input fifo_reset,
input [31:0] user_din,
input user_din_stb,
output [1:0] user_din_ready,
input [1:0] user_din_activate,
output [23:0] user_din_size,
output [31:0] user_dout,
output user_dout_ready,
input user_dout_activate,
input user_dout_stb,
output [23:0] user_dout_size,
//Transfer Layer Interface
input transport_layer_ready,
output reg sync_escape,
output t_send_command_stb,
output reg t_send_control_stb,
output t_send_data_stb,
input t_dma_activate_stb,
input t_d2h_reg_stb,
input t_pio_setup_stb,
input t_d2h_data_stb,
input t_dma_setup_stb,
input t_set_device_bits_stb,
input t_remote_abort,
input t_xmit_error,
input t_read_crc_error,
//PIO
input t_pio_response,
input t_pio_direction,
input [15:0] t_pio_transfer_count,
input [7:0] t_pio_e_status,
//Host to Device Register Values
output [7:0] h2d_command,
output reg [15:0] h2d_features,
output [7:0] h2d_control,
output [3:0] h2d_port_mult,
output [7:0] h2d_device,
output [47:0] h2d_lba,
output [15:0] h2d_sector_count,
//Device to Host Register Values
input d2h_interrupt,
input d2h_notification,
input [3:0] d2h_port_mult,
input [7:0] d2h_device,
input [47:0] d2h_lba,
input [15:0] d2h_sector_count,
input [7:0] d2h_status,
input [7:0] d2h_error,
//command layer data interface
input t_if_strobe,
output [31:0] t_if_data,
output t_if_ready,
input t_if_activate,
output [23:0] t_if_size,
input t_of_strobe,
input [31:0] t_of_data,
output [1:0] t_of_ready,
input [1:0] t_of_activate,
output [23:0] t_of_size,
//Debug
output [3:0] cl_c_state,
output [3:0] cl_w_state,
output [3:0] cl_r_state
);
//Parameters
parameter IDLE = 4'h0;
parameter PIO_WAIT_FOR_DATA = 4'h1;
parameter PIO_WRITE_DATA = 4'h2;
parameter WAIT_FOR_DATA = 4'h1;
parameter WAIT_FOR_DMA_ACT = 4'h1;
parameter WAIT_FOR_WRITE_DATA = 4'h2;
parameter SEND_DATA = 4'h3;
parameter WAIT_FOR_STATUS = 4'h4;
//Registers/Wires
reg [3:0] cntrl_state;
reg srst;
reg [7:0] status;
wire idle;
reg cntrl_send_data_stb;
reg send_command_stb;
reg prev_send_command;
wire dev_busy;
wire dev_data_req;
reg [31:0] reset_count;
wire reset_timeout;
//Read State Machine
reg [3:0] read_state;
reg read_data_stb;
reg single_read_prev;
//Write State Machine
reg [3:0] write_state;
reg write_data_stb;
reg single_write_prev;
reg dma_send_data_stb;
reg dma_act_detected;
wire write_data_available;
reg first_write;
reg first_read;
reg enable_tl_data_ready;
//Ping Pong FIFOs
wire [1:0] if_write_ready;
wire [1:0] if_write_activate;
wire [23:0] if_write_size;
wire if_write_strobe;
wire if_starved;
wire [31:0] if_write_data;
wire if_read_strobe;
wire if_read_ready;
wire if_read_activate;
wire [23:0] if_read_size;
wire [31:0] if_read_data;
wire [31:0] of_write_data;
wire [1:0] of_write_ready;
wire [1:0] of_write_activate;
wire [23:0] of_read_size;
wire of_write_strobe;
wire out_fifo_starved;
wire of_read_ready;
wire [31:0] of_read_data;
wire of_read_activate;
wire [23:0] of_write_size;
wire of_read_strobe;
//XXX: There is a bug in the PPFIFO in that the FPGA code the FIFO cannot be filled up
//Submodules
//ping pong FIFO
//Input FIFO
ppfifo # (
.DATA_WIDTH (`DATA_SIZE ),
.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH + 1)
) fifo_in (
.reset (rst || fifo_reset ),
//write side
//XXX: This can be different clocks
.write_clock (data_in_clk ),
.write_data (if_write_data ),
.write_ready (if_write_ready ),
.write_activate (if_write_activate ),
.write_fifo_size (if_write_size ),
.write_strobe (if_write_strobe ),
.starved (if_starved ),
//read side
//XXX: This can be different clocks
.read_clock (clk ),
.read_strobe (if_read_strobe ),
.read_ready (if_read_ready ),
.read_activate (if_read_activate ),
.read_count (if_read_size ),
.read_data (if_read_data )
);
//Output FIFO
ppfifo # (
.DATA_WIDTH (`DATA_SIZE ),
.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH + 1)
) fifo_out (
.reset (rst ),
//write side
//XXX: This can be different clocks
.write_clock (clk ),
.write_data (of_write_data ),
.write_ready (of_write_ready ),
.write_activate (of_write_activate ),
.write_fifo_size (of_write_size ),
.write_strobe (of_write_strobe ),
.starved (out_fifo_starved ),
//read side
//XXX: This can be different clocks
.read_clock (data_out_clk ),
.read_strobe (of_read_strobe ),
.read_ready (of_read_ready ),
.read_activate (of_read_activate ),
.read_count (of_read_size ),
.read_data (of_read_data )
);
//Asynchronous Logic
//Attach output of Input FIFO to TL
assign t_if_ready = if_read_ready && enable_tl_data_ready;
assign t_if_size = if_read_size;
assign t_if_data = if_read_data;
assign if_read_activate = t_if_activate;
assign if_read_strobe = t_if_strobe;
//Attach input of output FIFO to TL
assign t_of_ready = of_write_ready;
//assign t_of_size = of_write_size;
assign t_of_size = 24'h00800;
assign of_write_data = t_of_data;
assign of_write_activate = t_of_activate;
assign of_write_strobe = t_of_strobe;
assign if_write_data = user_din;
assign if_write_strobe = user_din_stb;
assign user_din_ready = if_write_ready;
assign if_write_activate = user_din_activate;
//assign user_din_size = if_write_size;
assign user_din_size = 24'h00800;
//assign user_din_size = 24'h00400;
//assign user_din_size = 24'h00200;
assign user_dout = of_read_data;
assign user_dout_ready = of_read_ready;
assign of_read_activate = user_dout_activate;
assign user_dout_size = of_read_size;
assign of_read_strobe = user_dout_stb;
assign write_data_available = (if_read_ready || if_read_activate) || (if_write_ready != 2'b11);
//Strobes
assign t_send_command_stb = read_data_stb || write_data_stb || send_command_stb;
assign t_send_data_stb = dma_send_data_stb ||cntrl_send_data_stb;
//IDLE
assign idle = (cntrl_state == IDLE) &&
(read_state == IDLE) &&
(write_state == IDLE) &&
transport_layer_ready;
assign command_layer_ready = idle;
assign sata_init = reset_timeout;
assign h2d_command = (write_data_en) ? `COMMAND_DMA_WRITE_EX :
(read_data_en) ? `COMMAND_DMA_READ_EX :
(send_user_command_stb) ? command :
h2d_command;
assign h2d_sector_count = sector_count;
assign h2d_lba = (write_data_en) ? (!single_rdwr && !first_write) ? d2h_lba + 1 : sector_address :
(read_data_en) ? (!single_rdwr && !first_read) ? d2h_lba + 1 : sector_address :
sector_address;
//XXX: The individual bits should be controlled directly
assign h2d_control = {5'h00, srst, 2'b00};
//XXX: This should be controlled from a higher level
assign h2d_port_mult = 4'h0;
//XXX: This should be controlled from a higher level
assign h2d_device = `D2H_REG_DEVICE;
assign dev_busy = status[`STATUS_BUSY_BIT];
assign dev_data_req = status[`STATUS_DRQ_BIT];
assign dev_error = status[`STATUS_ERR_BIT];
assign cl_c_state = cntrl_state;
assign cl_r_state = read_state;
assign cl_w_state = write_state;
assign reset_timeout = (reset_count >= `RESET_TIMEOUT);
//Synchronous Logic
//Control State Machine
always @ (posedge clk) begin
if (rst) begin
cntrl_state <= IDLE;
h2d_features <= `D2H_REG_FEATURES;
srst <= 0;
//Strobes
t_send_control_stb <= 0;
cntrl_send_data_stb <= 0;
pio_data_ready <= 0;
status <= 0;
prev_send_command <= 0;
send_command_stb <= 0;
reset_count <= 0;
busy <= 1;
end
else begin
t_send_control_stb <= 0;
cntrl_send_data_stb <= 0;
pio_data_ready <= 0;
send_command_stb <= 0;
//Reset Count
if (reset_count < `RESET_TIMEOUT) begin
reset_count <= reset_count + 1;
end
if (fifo_reset) begin
reset_count <= 0;
end
if (!reset_timeout) begin
cntrl_state <= IDLE;
end
//detected the first a user attempting to send a command
if (send_user_command_stb && !prev_send_command) begin
prev_send_command <= 1;
send_command_stb <= 1;
end
if (!send_user_command_stb) begin
prev_send_command <= 0;
end
if (t_d2h_reg_stb) begin
busy <= 0;
h2d_features <= `D2H_REG_FEATURES;
end
if (t_send_command_stb || t_send_control_stb || send_user_command_stb) begin
busy <= 1;
if (send_user_command_stb) begin
h2d_features <= user_features;
end
end
case (cntrl_state)
IDLE: begin
//Soft Reset will break out of any flow
if ((soft_reset_en) && !srst) begin
srst <= 1;
t_send_control_stb <= 1;
reset_count <= 0;
end
if (idle) begin
//The only way to transition to another state is if CL is IDLE
//User Initiated commands
if (!soft_reset_en && srst && reset_timeout) begin
srst <= 0;
t_send_control_stb <= 1;
end
end
//Device Initiated Transfers
if(t_pio_setup_stb) begin
if (t_pio_direction) begin
//Read from device
cntrl_state <= PIO_WAIT_FOR_DATA;
end
else begin
//Write to device
cntrl_state <= PIO_WRITE_DATA;
end
end
if (t_set_device_bits_stb) begin
status <= d2h_status;
//status register was updated
end
if (t_d2h_reg_stb) begin
status <= d2h_status;
end
end
PIO_WAIT_FOR_DATA: begin
if (t_d2h_data_stb) begin
//the next peice of data is related to the PIO
pio_data_ready <= 1;
cntrl_state <= IDLE;
status <= t_pio_e_status;
end
end
PIO_WRITE_DATA: begin
if (if_read_activate) begin
cntrl_send_data_stb <= 0;
cntrl_state <= IDLE;
status <= t_pio_e_status;
end
end
default: begin
cntrl_state <= IDLE;
end
endcase
if (send_sync_escape) begin
cntrl_state <= IDLE;
busy <= 0;
end
end
end
//Read State Machine
always @ (posedge clk) begin
if (rst) begin
read_state <= IDLE;
sync_escape <= 0;
read_data_stb <= 0;
single_read_prev <= 0;
first_read <= 1;
end
else begin
read_data_stb <= 0;
sync_escape <= 0;
if (!read_data_en) begin
single_read_prev <= 0;
end
case (read_state)
IDLE: begin
if (idle) begin
sync_escape <= 0;
//The only way to transition to another state is if CL is IDLE
if (read_data_en) begin
if (single_rdwr) begin
if (!single_read_prev) begin
single_read_prev <= 1;
read_data_stb <= 1;
read_state <= WAIT_FOR_DATA;
end
end
else begin
//send a request to read data
read_data_stb <= 1;
read_state <= WAIT_FOR_DATA;
end
end
else begin
first_read <= 1;
end
end
end
WAIT_FOR_DATA: begin
//This state seems useless because it only sets a value but the state is used to indicate the system is idle or not
if (t_d2h_data_stb) begin
first_read <= 0;
end
/*
if (soft_reset_en) begin
//XXX: Issue a SYNC ESCAPE to cancel a large read request otherwise let it play out
//sync_escape <= 1;
end
*/
end
default: begin
read_state <= IDLE;
end
endcase
if (soft_reset_en || !reset_timeout || send_sync_escape) begin
if (read_state != IDLE) begin
sync_escape <= 1;
end
if (send_sync_escape) begin
sync_escape <= 1;
end
read_state <= IDLE;
end
//If this is received go back to IDLE
if (t_d2h_reg_stb) begin
read_state <= IDLE;
end
end
end
//Write State Machine
always @ (posedge clk) begin
if (rst) begin
write_state <= IDLE;
dma_send_data_stb <= 0;
write_data_stb <= 0;
single_write_prev <= 0;
first_write <= 1;
enable_tl_data_ready <= 0;
dma_act_detected <= 0;
end
else begin
dma_send_data_stb <= 0;
write_data_stb <= 0;
if (enable_tl_data_ready && if_read_activate) begin
//Closes the loop on the data write feedback
enable_tl_data_ready <= 0;
end
if (!write_data_en) begin
single_write_prev <= 0;
end
if (t_dma_activate_stb) begin
//Set an enable signal instead of a strobe so that there is no chance of missing this signal
dma_act_detected <= 1;
end
case (write_state)
IDLE: begin
if (idle) begin
//The only way to transition to another state is if CL is IDLE
if (write_data_en) begin
if (single_rdwr) begin
if (!single_write_prev) begin
single_write_prev <= 1;
write_state <= WAIT_FOR_DMA_ACT;
write_data_stb <= 1;
end
end
else begin
//send a request to write data
write_state <= WAIT_FOR_DMA_ACT;
write_data_stb <= 1;
end
end
else begin
//reset the the first write when the user deassertes the write_data_en
first_write <= 1;
end
end
end
WAIT_FOR_DMA_ACT: begin
if (dma_act_detected) begin
dma_act_detected <= 0;
first_write <= 0;
enable_tl_data_ready <= 1;
write_state <= WAIT_FOR_WRITE_DATA;
end
end
WAIT_FOR_WRITE_DATA: begin
if (if_read_activate) begin
write_state <= SEND_DATA;
end
end
SEND_DATA: begin
if (transport_layer_ready) begin
//Send the Data FIS
dma_send_data_stb <= 1;
write_state <= WAIT_FOR_DMA_ACT;
end
end
WAIT_FOR_STATUS: begin
if (t_d2h_reg_stb) begin
write_state <= IDLE;
end
end
default: begin
write_state <= IDLE;
end
endcase
if (soft_reset_en || !reset_timeout) begin
//Break out of the normal flow and return to IDLE
write_state <= IDLE;
end
if (t_d2h_reg_stb) begin
//Whenever I read a register transfer from the device I need to go back to IDLE
write_state <= IDLE;
end
if (send_sync_escape) begin
write_state <= IDLE;
end
end
end
endmodule
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <[email protected]>
*
* Nobody can figure out what this file is for... hehe
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module hw_dbg (
input clk,
input rst_lck,
output reg rst,
input butc_,
input bute_,
input butw_,
input butn_,
input buts_,
// Wishbone master interface for the VDU
output reg [15:0] vdu_dat_o,
output reg [11:1] vdu_adr_o,
output vdu_we_o,
output vdu_stb_o,
output [ 1:0] vdu_sel_o,
output reg vdu_tga_o,
input vdu_ack_i,
// Wishbone master interface for the ZBT SRAM
input [15:0] zbt_dat_i,
output [19:1] zbt_adr_o,
output zbt_we_o,
output [ 1:0] zbt_sel_o,
output reg zbt_stb_o,
input zbt_ack_i
);
// Registers and nets
reg [ 5:0] st;
reg op;
reg [ 6:0] cur;
reg mr, ml, md, mu, dm;
reg br, bl, bd, bu, bc;
reg [15:0] cnt;
reg [ 4:0] i;
reg [19:0] adr;
reg [ 2:0] sp;
reg [15:0] col;
reg [ 3:0] nibb;
reg [ 7:0] low_adr;
wire [7:0] o;
wire cur_dump;
wire action;
wire [2:0] off;
wire [3:0] nib, inc_nib, dec_nib;
wire up_down;
wire left_right;
wire spg;
// Module instantiations
init_msg msg0 (
.i (i),
.o (o)
);
inc i0 (
.i (nib),
.o (inc_nib)
);
dec d0 (
.i (nib),
.o (dec_nib)
);
// Continuous assignments
assign vdu_we_o = op;
assign vdu_stb_o = op;
assign vdu_sel_o = 2'b11;
assign zbt_we_o = 1'b0;
assign zbt_sel_o = 2'b11;
assign cur_dump = (cur < 7'd25 && cur > 7'd19);
assign off = cur - 7'd20;
assign nib = off==3'd0 ? adr[19:16]
: (off==3'd1 ? adr[15:12]
: (off==3'd2 ? adr[11:8]
: (off==3'd3 ? adr[7:4] : adr[3:0])));
assign left_right = mr | ml;
assign up_down = mu | md;
assign action = left_right | up_down | dm;
assign spg = sp>3'b0;
assign zbt_adr_o = { adr[19:5] + low_adr[7:4], low_adr[3:0] };
// Behaviour
always @(posedge clk)
if (rst_lck)
begin
vdu_dat_o <= 16'd12;
vdu_adr_o <= 11'h4;
vdu_tga_o <= 1'b1;
st <= 6'd0;
op <= 1'b1;
i <= 4'h0;
zbt_stb_o <= 1'b0;
end
else
case (st)
6'd0: if (vdu_ack_i) begin
vdu_dat_o <= { 8'h06, o };
vdu_adr_o <= i + 5'h4;
vdu_tga_o <= 1'b0;
st <= (i==5'd21) ? 6'h2 : 6'h1;
op <= 1'b0;
i <= i + 5'h1;
end
6'd1: if (!vdu_ack_i) begin
st <= 6'h0;
op <= 1'b1;
i <= i;
end
6'd2: // main wait state
if (!vdu_ack_i && action) begin
vdu_dat_o <= mr ? (cur==7'd15 ? 7'd20 : cur + 7'b1)
: ((ml && cur==7'd20) ? 7'd15 : cur - 7'b1);
vdu_adr_o <= 11'h0;
vdu_tga_o <= 1'b1;
st <= left_right ? 6'h3 : (dm ? 6'h5 : 6'h4);
op <= left_right;
col <= 16'd80;
sp <= 2'h3;
nibb <= 4'h0;
end
6'd3: if (vdu_ack_i) begin
vdu_dat_o <= 16'h0;
vdu_adr_o <= 11'h0;
vdu_tga_o <= 1'b1;
st <= 6'h2;
op <= 1'b0;
end
6'd4: // redraw the mem_dump counter
if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h03, itoa(nib) };
vdu_adr_o <= cur;
vdu_tga_o <= 1'b0;
st <= 6'h3;
op <= 1'b1;
end
6'd5: // memory dump
if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h05, spg ? 8'h20 : itoa(nibb) };
vdu_adr_o <= col;
vdu_tga_o <= 1'b0;
st <= 6'h6;
op <= 1'b1;
sp <= spg ? (sp - 3'b1) : 3'd4;
col <= col + 16'd1;
nibb <= spg ? nibb : (nibb + 4'h2);
end
6'd6: if (vdu_ack_i) begin
st <= (col==16'd160) ? 6'h7 : 6'h5;
op <= 1'b0;
end
6'd7: begin
low_adr <= 8'h0;
st <= 6'h8;
end
6'd8: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h5, itoa(zbt_adr_o[7:4]) };
vdu_adr_o <= col;
st <= 6'd9;
op <= 1'b1;
end
6'd9: if (vdu_ack_i) begin
st <= 6'd10;
op <= 1'b0;
col <= col + 16'd1;
end
6'd10: if (!zbt_ack_i) begin
st <= 6'd11;
zbt_stb_o <= 1'b1;
end
6'd11: if (zbt_ack_i) begin
st <= 6'd12;
zbt_stb_o <= 1'b0;
end
6'd12: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[15:12]) };
vdu_adr_o <= col;
st <= 6'd13;
op <= 1'b1;
end
6'd13: if (vdu_ack_i) begin
st <= 6'd14;
op <= 1'b0;
col <= col + 16'd1;
end
6'd14: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[11:8]) };
vdu_adr_o <= col;
st <= 6'd15;
op <= 1'b1;
end
6'd15: if (vdu_ack_i) begin
st <= 6'd16;
op <= 1'b0;
col <= col + 16'd1;
end
6'd16: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[7:4]) };
vdu_adr_o <= col;
st <= 6'd17;
op <= 1'b1;
end
6'd17: if (vdu_ack_i) begin
st <= 6'd18;
op <= 1'b0;
col <= col + 16'd1;
end
6'd18: if (!vdu_ack_i) begin
vdu_dat_o <= { 8'h7, itoa(zbt_dat_i[3:0]) };
vdu_adr_o <= col;
st <= 6'd19;
op <= 1'b1;
end
6'd19: if (vdu_ack_i) begin
st <= (zbt_adr_o[4:1]==4'hf) ? 6'd22 : 6'd20;
op <= 1'b0;
col <= col + 16'd1;
low_adr <= low_adr + 8'h1;
end
6'd20: if (!vdu_ack_i) begin
vdu_dat_o <= 16'h0720;
vdu_adr_o <= col;
st <= 6'd21;
op <= 1'b1;
end
6'd21: if (vdu_ack_i) begin
st <= 6'd10;
op <= 1'b0;
col <= col + 16'd1;
end
6'd22: st <= (low_adr==8'h0) ? 6'd2 : 6'd8;
endcase
// rst
always @(posedge clk)
rst <= rst_lck ? 1'b1 : ((butc_ && cur==7'd12) ? 1'b0 : rst);
// cur
always @(posedge clk)
cur <= rst_lck ? 7'd12 : (mr ? (cur==7'd15 ? 7'd20 : cur + 7'b1)
: (ml ? (cur==7'd20 ? 7'd15 : cur - 7'b1) : cur));
// adr
always @(posedge clk)
adr <= rst_lck ? 16'h0
: (mu ? (off==3'd0 ? { inc_nib, adr[15:0] }
: (off==3'd1 ? { adr[19:16], inc_nib, adr[11:0] }
: (off==3'd2 ? { adr[19:12], inc_nib, adr[7:0] }
: (off==3'd3 ? { adr[19:8], inc_nib, adr[3:0] }
: { adr[19:4], inc_nib }))))
: (md ? (off==3'd0 ? { dec_nib, adr[15:0] }
: (off==3'd1 ? { adr[19:16], dec_nib, adr[11:0] }
: (off==3'd2 ? { adr[19:12], dec_nib, adr[7:0] }
: (off==3'd3 ? { adr[19:8], dec_nib, adr[3:0] }
: { adr[19:4], dec_nib })))) : adr));
// mr - move right
always @(posedge clk)
mr <= rst_lck ? 1'b0 : (bute_ && !br
&& cnt==16'h0 && cur != 7'd24);
// br - button right
always @(posedge clk) br <= (cnt==16'h0 ? bute_ : br);
// ml - move right
always @(posedge clk)
ml <= rst_lck ? 1'b0 : (butw_ && !bl
&& cnt==16'h0 && cur != 7'd12);
// bl - button right
always @(posedge clk) bl <= (cnt==16'h0 ? butw_ : bl);
// md - move down
always @(posedge clk)
md <= rst_lck ? 1'b0 : (buts_ && !bd && cnt==16'h0 && cur_dump);
// bd - button down
always @(posedge clk) bd <= (cnt==16'h0 ? buts_ : bd);
// mu - move up
always @(posedge clk)
mu <= rst_lck ? 1'b0 : (butn_ && !bu && cnt==16'h0 && cur_dump);
// bu - button up
always @(posedge clk) bu <= (cnt==16'h0 ? butn_ : bu);
// dm - dump
always @(posedge clk)
dm <= rst_lck ? 1'b0 : (butc_ && !bc && cur==7'd13);
// bc - center button
always @(posedge clk) bc <= (cnt==16'h0 ? butc_ : bc);
// cnt - button counter
always @(posedge clk) cnt <= cnt + 1'b1;
function [7:0] itoa;
input [3:0] i;
begin
if (i < 8'd10) itoa = i + 8'h30;
else itoa = i + 8'h57;
end
endfunction
endmodule
module init_msg (
input [4:0] i,
output reg [7:0] o
);
// Behaviour
always @(i)
case (i)
5'h00: o <= 8'h68; // h
5'h01: o <= 8'h77; // w
5'h02: o <= 8'h5f; // _
5'h03: o <= 8'h64; // d
5'h04: o <= 8'h62; // b
5'h05: o <= 8'h67; // g
5'h06: o <= 8'h20; //
5'h07: o <= 8'h5b; // [
5'h08: o <= 8'h43; // C
5'h09: o <= 8'h44; // D
5'h0a: o <= 8'h57; // W
5'h0b: o <= 8'h42; // B
5'h0c: o <= 8'h5d; // ]
5'h0d: o <= 8'h20; //
5'h0f: o <= 8'h78; // x
default: o <= 8'h30; // 0
endcase
endmodule
module inc (
input [3:0] i,
output reg [3:0] o
);
// Behaviour
always @(i)
case (i)
4'h0: o <= 4'h1;
4'h1: o <= 4'h2;
4'h2: o <= 4'h3;
4'h3: o <= 4'h4;
4'h4: o <= 4'h5;
4'h5: o <= 4'h6;
4'h6: o <= 4'h7;
4'h7: o <= 4'h8;
4'h8: o <= 4'h9;
4'h9: o <= 4'ha;
4'ha: o <= 4'hb;
4'hb: o <= 4'hc;
4'hc: o <= 4'hd;
4'hd: o <= 4'he;
4'he: o <= 4'hf;
default: o <= 4'h0;
endcase
endmodule
module dec (
input [3:0] i,
output reg [3:0] o
);
// Behaviour
always @(i)
case (i)
4'h0: o <= 4'hf;
4'h1: o <= 4'h0;
4'h2: o <= 4'h1;
4'h3: o <= 4'h2;
4'h4: o <= 4'h3;
4'h5: o <= 4'h4;
4'h6: o <= 4'h5;
4'h7: o <= 4'h6;
4'h8: o <= 4'h7;
4'h9: o <= 4'h8;
4'ha: o <= 4'h9;
4'hb: o <= 4'ha;
4'hc: o <= 4'hb;
4'hd: o <= 4'hc;
4'he: o <= 4'hd;
default: o <= 4'he;
endcase
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_frame_join_4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_0_axis_tdata = 8'd0;
reg input_0_axis_tvalid = 1'b0;
reg input_0_axis_tlast = 1'b0;
reg input_0_axis_tuser = 1'b0;
reg [7:0] input_1_axis_tdata = 8'd0;
reg input_1_axis_tvalid = 1'b0;
reg input_1_axis_tlast = 1'b0;
reg input_1_axis_tuser = 1'b0;
reg [7:0] input_2_axis_tdata = 8'd0;
reg input_2_axis_tvalid = 1'b0;
reg input_2_axis_tlast = 1'b0;
reg input_2_axis_tuser = 1'b0;
reg [7:0] input_3_axis_tdata = 8'd0;
reg input_3_axis_tvalid = 1'b0;
reg input_3_axis_tlast = 1'b0;
reg input_3_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [15:0] tag = 0;
// Outputs
wire input_0_axis_tready;
wire input_1_axis_tready;
wire input_2_axis_tready;
wire input_3_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready,
tag);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
busy);
// dump file
$dumpfile("test_axis_frame_join_4.lxt");
$dumpvars(0, test_axis_frame_join_4);
end
axis_frame_join_4 #(
.TAG_ENABLE(1)
)
UUT (
.clk(clk),
.rst(rst),
// axi input
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tuser(input_3_axis_tuser),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// config
.tag(tag),
// status
.busy(busy)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_cmos_edgelogic.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// CMOS edge logic
*/
////////////////////////////////////////////////////////////////////////
`include "sys.h"
module bw_io_cmos_edgelogic(
// Outputs
to_core, por, pad_up, bsr_up, pad_dn_l, bsr_dn_l,
// Inputs
data, oe, bsr_mode, por_l,
bsr_data_to_core, se, rcvr_data
);
//////////////////////////////////////////////////////////////////////////
// INPUTS
//////////////////////////////////////////////////////////////////////////
input data;
input oe;
input bsr_mode;
input por_l;
input se;
input bsr_data_to_core;
input rcvr_data;
supply0 vss;
//////////////////////////////////////////////////////////////////////////
// OUTPUTS
//////////////////////////////////////////////////////////////////////////
output pad_up;
output pad_dn_l;
output bsr_up;
output bsr_dn_l;
output por;
output to_core;
// WIRES
wire pad_up;
wire pad_dn_l;
wire bsr_up;
wire bsr_dn_l;
wire por;
wire to_core;
//always
//begin
// bsr_up = pad_up;
// bsr_dn_l = pad_dn_l;
// por = ~por_l;
// pad_up = data && oe;
// pad_dn_l = ~(~data && oe);
// to_core = (bsr_mode && !se) ? bsr_data_to_core : rcvr_data;
//end
assign bsr_up = pad_up;
assign bsr_dn_l = pad_dn_l;
assign por = ~por_l;
assign pad_up = data && oe;
assign pad_dn_l = ~(~data && oe);
assign to_core = (bsr_mode && !se) ? bsr_data_to_core : rcvr_data;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFSTP_PP_SYMBOL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_PP_SYMBOL_V
|
module top(
input i_ce,
input i_clk,
input i_d1,
input i_d2,
input i_rst,
output [23:0] io
);
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S1;
wire [0:0] LIOB33_X0Y21_IOB_X0Y22_O;
wire [0:0] LIOB33_X0Y23_IOB_X0Y23_O;
wire [0:0] LIOB33_X0Y23_IOB_X0Y24_O;
wire [0:0] LIOB33_X0Y25_IOB_X0Y25_O;
wire [0:0] LIOB33_X0Y25_IOB_X0Y26_O;
wire [0:0] LIOB33_X0Y27_IOB_X0Y27_O;
wire [0:0] LIOB33_X0Y27_IOB_X0Y28_O;
wire [0:0] LIOB33_X0Y29_IOB_X0Y29_O;
wire [0:0] LIOB33_X0Y29_IOB_X0Y30_O;
wire [0:0] LIOB33_X0Y31_IOB_X0Y31_O;
wire [0:0] LIOB33_X0Y31_IOB_X0Y32_O;
wire [0:0] LIOB33_X0Y33_IOB_X0Y33_O;
wire [0:0] LIOB33_X0Y33_IOB_X0Y34_O;
wire [0:0] LIOB33_X0Y35_IOB_X0Y35_O;
wire [0:0] LIOB33_X0Y35_IOB_X0Y36_O;
wire [0:0] LIOB33_X0Y37_IOB_X0Y37_O;
wire [0:0] LIOB33_X0Y37_IOB_X0Y38_O;
wire [0:0] LIOB33_X0Y39_IOB_X0Y39_O;
wire [0:0] LIOB33_X0Y39_IOB_X0Y40_O;
wire [0:0] LIOB33_X0Y41_IOB_X0Y41_O;
wire [0:0] LIOB33_X0Y41_IOB_X0Y42_O;
wire [0:0] LIOB33_X0Y43_IOB_X0Y43_O;
wire [0:0] LIOB33_X0Y45_IOB_X0Y45_O;
wire [0:0] LIOB33_X0Y45_IOB_X0Y46_O;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_CLK;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_D1;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_D2;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_OCE;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_OQ;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_SR;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_T1;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_TQ;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_CLK;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_D1;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_D2;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_OCE;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_OQ;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_SR;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_T1;
wire [0:0] LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_TQ;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_CLK;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_D1;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_D2;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OCE;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OQ;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_SR;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_T1;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_TQ;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_CLK;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_D1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_D2;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_OCE;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_OQ;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_SR;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_T1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_TQ;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_CLK;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_D1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_D2;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_OCE;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_OQ;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_SR;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_T1;
wire [0:0] LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_TQ;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_CLK;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_D1;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_D2;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_OCE;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_OQ;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_SR;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_T1;
wire [0:0] LIOI3_X0Y21_OLOGIC_X0Y22_TQ;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_CLK;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_D1;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_D2;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_OCE;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_OQ;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_SR;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_T1;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y23_TQ;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_CLK;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_D1;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_D2;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_OCE;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_OQ;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_SR;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_T1;
wire [0:0] LIOI3_X0Y23_OLOGIC_X0Y24_TQ;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_CLK;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_D1;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_D2;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_OCE;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_OQ;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_SR;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_T1;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y25_TQ;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_CLK;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_D1;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_D2;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_OCE;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_OQ;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_SR;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_T1;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_TQ;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_CLK;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_D1;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_D2;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_OCE;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_OQ;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_SR;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_T1;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y27_TQ;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_CLK;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_D1;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_D2;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_OCE;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_OQ;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_SR;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_T1;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_TQ;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_CLK;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_D1;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_D2;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_OCE;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_OQ;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_SR;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_T1;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y29_TQ;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_CLK;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_D1;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_D2;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_OCE;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_OQ;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_SR;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_T1;
wire [0:0] LIOI3_X0Y29_OLOGIC_X0Y30_TQ;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_CLK;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_D1;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_D2;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_OCE;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_OQ;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_SR;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_T1;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y33_TQ;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_CLK;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_D1;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_D2;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_OCE;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_OQ;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_SR;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_T1;
wire [0:0] LIOI3_X0Y33_OLOGIC_X0Y34_TQ;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_CLK;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_D1;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_D2;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_OCE;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_OQ;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_SR;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_T1;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y35_TQ;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_CLK;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_D1;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_D2;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_OCE;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_OQ;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_SR;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_T1;
wire [0:0] LIOI3_X0Y35_OLOGIC_X0Y36_TQ;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_CLK;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_D1;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_D2;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_OCE;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_OQ;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_SR;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_T1;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y39_TQ;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_CLK;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_D1;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_D2;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_OCE;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_OQ;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_SR;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_T1;
wire [0:0] LIOI3_X0Y39_OLOGIC_X0Y40_TQ;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_CLK;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_D1;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_D2;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_OCE;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_OQ;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_SR;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_T1;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y41_TQ;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_CLK;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_D1;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_D2;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_OCE;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_OQ;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_SR;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_T1;
wire [0:0] LIOI3_X0Y41_OLOGIC_X0Y42_TQ;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_CLK;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_D1;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_D2;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_OCE;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_OQ;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_SR;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_T1;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y45_TQ;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_CLK;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_D1;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_D2;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_OCE;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_OQ;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_SR;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_T1;
wire [0:0] LIOI3_X0Y45_OLOGIC_X0Y46_TQ;
wire [0:0] RIOB33_X43Y25_IOB_X1Y26_I;
wire [0:0] RIOB33_X43Y43_IOB_X1Y43_I;
wire [0:0] RIOB33_X43Y43_IOB_X1Y44_I;
wire [0:0] RIOB33_X43Y45_IOB_X1Y45_I;
wire [0:0] RIOB33_X43Y45_IOB_X1Y46_I;
wire [0:0] RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y43_D;
wire [0:0] RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y43_O;
wire [0:0] RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y44_D;
wire [0:0] RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y44_O;
wire [0:0] RIOI3_X43Y25_ILOGIC_X1Y26_D;
wire [0:0] RIOI3_X43Y25_ILOGIC_X1Y26_O;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y45_D;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y45_O;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y46_D;
wire [0:0] RIOI3_X43Y45_ILOGIC_X1Y46_O;
(* KEEP, DONT_TOUCH, BEL = "BUFGCTRL" *)
BUFGCTRL #(
.INIT_OUT(0),
.IS_CE0_INVERTED(0),
.IS_CE1_INVERTED(1),
.IS_IGNORE0_INVERTED(1),
.IS_IGNORE1_INVERTED(0),
.IS_S0_INVERTED(0),
.IS_S1_INVERTED(1),
.PRESELECT_I0("TRUE"),
.PRESELECT_I1("FALSE")
) CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_BUFGCTRL (
.CE0(1'b1),
.CE1(1'b1),
.I0(RIOB33_X43Y25_IOB_X1Y26_I),
.I1(1'b1),
.IGNORE0(1'b1),
.IGNORE1(1'b1),
.O(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.S0(1'b1),
.S1(1'b1)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y21_IOB_X0Y22_OBUF (
.I(LIOI3_X0Y21_OLOGIC_X0Y22_OQ),
.O(io[23])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y23_IOB_X0Y23_OBUF (
.I(LIOI3_X0Y23_OLOGIC_X0Y23_OQ),
.O(io[22])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y23_IOB_X0Y24_OBUF (
.I(LIOI3_X0Y23_OLOGIC_X0Y24_OQ),
.O(io[21])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y25_IOB_X0Y25_OBUF (
.I(LIOI3_X0Y25_OLOGIC_X0Y25_OQ),
.O(io[20])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y25_IOB_X0Y26_OBUF (
.I(LIOI3_X0Y25_OLOGIC_X0Y26_OQ),
.O(io[19])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y27_IOB_X0Y27_OBUF (
.I(LIOI3_X0Y27_OLOGIC_X0Y27_OQ),
.O(io[18])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y27_IOB_X0Y28_OBUF (
.I(LIOI3_X0Y27_OLOGIC_X0Y28_OQ),
.O(io[17])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y29_IOB_X0Y29_OBUF (
.I(LIOI3_X0Y29_OLOGIC_X0Y29_OQ),
.O(io[16])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y29_IOB_X0Y30_OBUF (
.I(LIOI3_X0Y29_OLOGIC_X0Y30_OQ),
.O(io[15])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y31_IOB_X0Y31_OBUF (
.I(LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_OQ),
.O(io[14])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y31_IOB_X0Y32_OBUF (
.I(LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_OQ),
.O(io[13])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y33_IOB_X0Y33_OBUF (
.I(LIOI3_X0Y33_OLOGIC_X0Y33_OQ),
.O(io[12])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y33_IOB_X0Y34_OBUF (
.I(LIOI3_X0Y33_OLOGIC_X0Y34_OQ),
.O(io[11])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y35_IOB_X0Y35_OBUF (
.I(LIOI3_X0Y35_OLOGIC_X0Y35_OQ),
.O(io[10])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y35_IOB_X0Y36_OBUF (
.I(LIOI3_X0Y35_OLOGIC_X0Y36_OQ),
.O(io[9])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y37_IOB_X0Y37_OBUF (
.I(LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_OQ),
.O(io[8])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y37_IOB_X0Y38_OBUF (
.I(LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_OQ),
.O(io[7])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y39_IOB_X0Y39_OBUF (
.I(LIOI3_X0Y39_OLOGIC_X0Y39_OQ),
.O(io[6])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y39_IOB_X0Y40_OBUF (
.I(LIOI3_X0Y39_OLOGIC_X0Y40_OQ),
.O(io[5])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y41_IOB_X0Y41_OBUF (
.I(LIOI3_X0Y41_OLOGIC_X0Y41_OQ),
.O(io[4])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y41_IOB_X0Y42_OBUF (
.I(LIOI3_X0Y41_OLOGIC_X0Y42_OQ),
.O(io[3])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y43_IOB_X0Y43_OBUF (
.I(LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OQ),
.O(io[2])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y45_IOB_X0Y45_OBUF (
.I(LIOI3_X0Y45_OLOGIC_X0Y45_OQ),
.O(io[1])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y45_IOB_X0Y46_OBUF (
.I(LIOI3_X0Y45_OLOGIC_X0Y46_OQ),
.O(io[0])
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y21_OLOGIC_X0Y22_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y21_OLOGIC_X0Y22_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y23_OLOGIC_X0Y24_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y23_OLOGIC_X0Y24_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y23_OLOGIC_X0Y23_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y23_OLOGIC_X0Y23_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y25_OLOGIC_X0Y26_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y25_OLOGIC_X0Y26_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y25_OLOGIC_X0Y25_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y25_OLOGIC_X0Y25_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y27_OLOGIC_X0Y28_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y27_OLOGIC_X0Y28_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y27_OLOGIC_X0Y27_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y27_OLOGIC_X0Y27_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y29_OLOGIC_X0Y30_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y29_OLOGIC_X0Y30_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y29_OLOGIC_X0Y29_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y29_OLOGIC_X0Y29_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y33_OLOGIC_X0Y34_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y33_OLOGIC_X0Y34_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_X0Y33_OLOGIC_X0Y33_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y33_OLOGIC_X0Y33_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y35_OLOGIC_X0Y36_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y35_OLOGIC_X0Y36_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y35_OLOGIC_X0Y35_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y35_OLOGIC_X0Y35_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y39_OLOGIC_X0Y40_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y39_OLOGIC_X0Y40_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y39_OLOGIC_X0Y39_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y39_OLOGIC_X0Y39_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y41_OLOGIC_X0Y42_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y41_OLOGIC_X0Y42_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y41_OLOGIC_X0Y41_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y41_OLOGIC_X0Y41_OQ),
.S(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y45_OLOGIC_X0Y46_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y45_OLOGIC_X0Y46_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_X0Y45_OLOGIC_X0Y45_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_X0Y45_OLOGIC_X0Y45_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("SYNC")
) LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_OQ),
.S(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "OUTFF" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D1_INVERTED(1'b0),
.IS_D2_INVERTED(1'b0),
.SRTYPE("ASYNC")
) LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_ODDR_OQ (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(RIOB33_X43Y45_IOB_X1Y45_I),
.D1(RIOB33_X43Y43_IOB_X1Y44_I),
.D2(RIOB33_X43Y43_IOB_X1Y43_I),
.Q(LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_OQ),
.R(RIOB33_X43Y45_IOB_X1Y46_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y25_IOB_X1Y26_IBUF (
.I(i_clk),
.O(RIOB33_X43Y25_IOB_X1Y26_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y43_IOB_X1Y43_IBUF (
.I(i_d2),
.O(RIOB33_X43Y43_IOB_X1Y43_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y43_IOB_X1Y44_IBUF (
.I(i_d1),
.O(RIOB33_X43Y43_IOB_X1Y44_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y45_IOB_X1Y45_IBUF (
.I(i_ce),
.O(RIOB33_X43Y45_IOB_X1Y45_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y45_IOB_X1Y46_IBUF (
.I(i_rst),
.O(RIOB33_X43Y45_IOB_X1Y46_I)
);
assign LIOI3_X0Y21_OLOGIC_X0Y22_TQ = 1'b1;
assign LIOI3_X0Y23_OLOGIC_X0Y24_TQ = 1'b1;
assign LIOI3_X0Y23_OLOGIC_X0Y23_TQ = 1'b1;
assign LIOI3_X0Y25_OLOGIC_X0Y26_TQ = 1'b1;
assign LIOI3_X0Y25_OLOGIC_X0Y25_TQ = 1'b1;
assign LIOI3_X0Y27_OLOGIC_X0Y28_TQ = 1'b1;
assign LIOI3_X0Y27_OLOGIC_X0Y27_TQ = 1'b1;
assign LIOI3_X0Y29_OLOGIC_X0Y30_TQ = 1'b1;
assign LIOI3_X0Y29_OLOGIC_X0Y29_TQ = 1'b1;
assign LIOI3_X0Y33_OLOGIC_X0Y34_TQ = 1'b1;
assign LIOI3_X0Y33_OLOGIC_X0Y33_TQ = 1'b1;
assign LIOI3_X0Y35_OLOGIC_X0Y36_TQ = 1'b1;
assign LIOI3_X0Y35_OLOGIC_X0Y35_TQ = 1'b1;
assign LIOI3_X0Y39_OLOGIC_X0Y40_TQ = 1'b1;
assign LIOI3_X0Y39_OLOGIC_X0Y39_TQ = 1'b1;
assign LIOI3_X0Y41_OLOGIC_X0Y42_TQ = 1'b1;
assign LIOI3_X0Y41_OLOGIC_X0Y41_TQ = 1'b1;
assign LIOI3_X0Y45_OLOGIC_X0Y46_TQ = 1'b1;
assign LIOI3_X0Y45_OLOGIC_X0Y45_TQ = 1'b1;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_TQ = 1'b1;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_TQ = 1'b1;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_TQ = 1'b1;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_TQ = 1'b1;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_TQ = 1'b1;
assign RIOI3_X43Y25_ILOGIC_X1Y26_O = RIOB33_X43Y25_IOB_X1Y26_I;
assign RIOI3_X43Y45_ILOGIC_X1Y46_O = RIOB33_X43Y45_IOB_X1Y46_I;
assign RIOI3_X43Y45_ILOGIC_X1Y45_O = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y44_O = RIOB33_X43Y43_IOB_X1Y44_I;
assign RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y43_O = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOB33_X0Y37_IOB_X0Y38_O = LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_OQ;
assign LIOB33_X0Y37_IOB_X0Y37_O = LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_OQ;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_SR = 1'b0;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_T1 = 1'b1;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_SR = 1'b0;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_T1 = 1'b1;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y41_OLOGIC_X0Y42_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y41_OLOGIC_X0Y42_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_T1 = 1'b1;
assign LIOI3_X0Y41_OLOGIC_X0Y42_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y41_OLOGIC_X0Y42_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y41_OLOGIC_X0Y42_T1 = 1'b1;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_T1 = 1'b1;
assign LIOB33_X0Y41_IOB_X0Y42_O = LIOI3_X0Y41_OLOGIC_X0Y42_OQ;
assign LIOB33_X0Y41_IOB_X0Y41_O = LIOI3_X0Y41_OLOGIC_X0Y41_OQ;
assign LIOI3_X0Y41_OLOGIC_X0Y41_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y41_OLOGIC_X0Y41_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOB33_X0Y23_IOB_X0Y24_O = LIOI3_X0Y23_OLOGIC_X0Y24_OQ;
assign LIOB33_X0Y23_IOB_X0Y23_O = LIOI3_X0Y23_OLOGIC_X0Y23_OQ;
assign LIOI3_X0Y41_OLOGIC_X0Y41_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y41_OLOGIC_X0Y41_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y41_OLOGIC_X0Y41_T1 = 1'b1;
assign LIOI3_X0Y35_OLOGIC_X0Y36_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y35_OLOGIC_X0Y36_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y35_OLOGIC_X0Y36_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y35_OLOGIC_X0Y36_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y35_OLOGIC_X0Y36_T1 = 1'b1;
assign LIOI3_X0Y35_OLOGIC_X0Y35_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y35_OLOGIC_X0Y35_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOB33_X0Y45_IOB_X0Y46_O = LIOI3_X0Y45_OLOGIC_X0Y46_OQ;
assign LIOB33_X0Y45_IOB_X0Y45_O = LIOI3_X0Y45_OLOGIC_X0Y45_OQ;
assign LIOI3_X0Y35_OLOGIC_X0Y35_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOB33_X0Y27_IOB_X0Y28_O = LIOI3_X0Y27_OLOGIC_X0Y28_OQ;
assign LIOB33_X0Y27_IOB_X0Y27_O = LIOI3_X0Y27_OLOGIC_X0Y27_OQ;
assign LIOI3_X0Y35_OLOGIC_X0Y35_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y35_OLOGIC_X0Y35_T1 = 1'b1;
assign LIOI3_X0Y29_OLOGIC_X0Y30_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y29_OLOGIC_X0Y30_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y29_OLOGIC_X0Y30_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y29_OLOGIC_X0Y30_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y29_OLOGIC_X0Y30_T1 = 1'b1;
assign LIOI3_X0Y29_OLOGIC_X0Y29_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y29_OLOGIC_X0Y29_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y29_OLOGIC_X0Y29_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y29_OLOGIC_X0Y29_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y29_OLOGIC_X0Y29_T1 = 1'b1;
assign LIOB33_X0Y31_IOB_X0Y32_O = LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_OQ;
assign LIOB33_X0Y31_IOB_X0Y31_O = LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_OQ;
assign LIOI3_X0Y25_OLOGIC_X0Y26_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y25_OLOGIC_X0Y26_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y25_OLOGIC_X0Y26_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y25_OLOGIC_X0Y26_SR = 1'b0;
assign LIOI3_X0Y25_OLOGIC_X0Y26_T1 = 1'b1;
assign LIOI3_X0Y25_OLOGIC_X0Y25_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y25_OLOGIC_X0Y25_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y44_D = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y25_OLOGIC_X0Y25_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign RIOI3_TBYTESRC_X43Y43_ILOGIC_X1Y43_D = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y25_OLOGIC_X0Y25_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y25_OLOGIC_X0Y25_T1 = 1'b1;
assign LIOI3_X0Y21_OLOGIC_X0Y22_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y21_OLOGIC_X0Y22_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOB33_X0Y35_IOB_X0Y36_O = LIOI3_X0Y35_OLOGIC_X0Y36_OQ;
assign LIOB33_X0Y35_IOB_X0Y35_O = LIOI3_X0Y35_OLOGIC_X0Y35_OQ;
assign LIOI3_X0Y21_OLOGIC_X0Y22_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y21_OLOGIC_X0Y22_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y21_OLOGIC_X0Y22_T1 = 1'b1;
assign LIOI3_X0Y45_OLOGIC_X0Y46_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y45_OLOGIC_X0Y46_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y45_OLOGIC_X0Y46_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y45_OLOGIC_X0Y46_SR = 1'b0;
assign LIOI3_X0Y45_OLOGIC_X0Y46_T1 = 1'b1;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_T1 = 1'b1;
assign LIOB33_X0Y39_IOB_X0Y40_O = LIOI3_X0Y39_OLOGIC_X0Y40_OQ;
assign LIOB33_X0Y39_IOB_X0Y39_O = LIOI3_X0Y39_OLOGIC_X0Y39_OQ;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S1 = 1'b1;
assign LIOB33_X0Y21_IOB_X0Y22_O = LIOI3_X0Y21_OLOGIC_X0Y22_OQ;
assign LIOI3_X0Y45_OLOGIC_X0Y45_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y45_OLOGIC_X0Y45_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y45_OLOGIC_X0Y45_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y45_OLOGIC_X0Y45_SR = 1'b0;
assign LIOI3_X0Y45_OLOGIC_X0Y45_T1 = 1'b1;
assign LIOI3_X0Y39_OLOGIC_X0Y40_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y39_OLOGIC_X0Y40_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y39_OLOGIC_X0Y40_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y39_OLOGIC_X0Y40_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y39_OLOGIC_X0Y40_T1 = 1'b1;
assign LIOI3_X0Y39_OLOGIC_X0Y39_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y39_OLOGIC_X0Y39_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOB33_X0Y43_IOB_X0Y43_O = LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OQ;
assign LIOB33_X0Y25_IOB_X0Y26_O = LIOI3_X0Y25_OLOGIC_X0Y26_OQ;
assign LIOB33_X0Y25_IOB_X0Y25_O = LIOI3_X0Y25_OLOGIC_X0Y25_OQ;
assign LIOI3_X0Y39_OLOGIC_X0Y39_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y39_OLOGIC_X0Y39_SR = 1'b0;
assign LIOI3_X0Y39_OLOGIC_X0Y39_T1 = 1'b1;
assign LIOI3_X0Y33_OLOGIC_X0Y34_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y33_OLOGIC_X0Y34_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y33_OLOGIC_X0Y34_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y33_OLOGIC_X0Y34_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y33_OLOGIC_X0Y34_T1 = 1'b1;
assign RIOI3_X43Y45_ILOGIC_X1Y46_D = RIOB33_X43Y45_IOB_X1Y46_I;
assign RIOI3_X43Y45_ILOGIC_X1Y45_D = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y33_OLOGIC_X0Y33_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y33_OLOGIC_X0Y33_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y33_OLOGIC_X0Y33_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y33_OLOGIC_X0Y33_SR = 1'b0;
assign LIOI3_X0Y33_OLOGIC_X0Y33_T1 = 1'b1;
assign LIOB33_X0Y29_IOB_X0Y30_O = LIOI3_X0Y29_OLOGIC_X0Y30_OQ;
assign LIOB33_X0Y29_IOB_X0Y29_O = LIOI3_X0Y29_OLOGIC_X0Y29_OQ;
assign LIOI3_X0Y27_OLOGIC_X0Y28_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y27_OLOGIC_X0Y28_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y27_OLOGIC_X0Y28_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y27_OLOGIC_X0Y28_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y27_OLOGIC_X0Y28_T1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I0 = RIOB33_X43Y25_IOB_X1Y26_I;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I1 = 1'b1;
assign LIOI3_X0Y27_OLOGIC_X0Y27_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y27_OLOGIC_X0Y27_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign RIOI3_X43Y25_ILOGIC_X1Y26_D = RIOB33_X43Y25_IOB_X1Y26_I;
assign LIOI3_X0Y27_OLOGIC_X0Y27_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y27_OLOGIC_X0Y27_SR = 1'b0;
assign LIOI3_X0Y27_OLOGIC_X0Y27_T1 = 1'b1;
assign LIOB33_X0Y33_IOB_X0Y34_O = LIOI3_X0Y33_OLOGIC_X0Y34_OQ;
assign LIOB33_X0Y33_IOB_X0Y33_O = LIOI3_X0Y33_OLOGIC_X0Y33_OQ;
assign LIOI3_X0Y23_OLOGIC_X0Y24_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y23_OLOGIC_X0Y24_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y23_OLOGIC_X0Y24_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y23_OLOGIC_X0Y24_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y23_OLOGIC_X0Y24_T1 = 1'b1;
assign LIOI3_X0Y23_OLOGIC_X0Y23_D1 = RIOB33_X43Y43_IOB_X1Y44_I;
assign LIOI3_X0Y23_OLOGIC_X0Y23_D2 = RIOB33_X43Y43_IOB_X1Y43_I;
assign LIOI3_X0Y23_OLOGIC_X0Y23_OCE = RIOB33_X43Y45_IOB_X1Y45_I;
assign LIOI3_X0Y23_OLOGIC_X0Y23_SR = RIOB33_X43Y45_IOB_X1Y46_I;
assign LIOI3_X0Y23_OLOGIC_X0Y23_T1 = 1'b1;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y38_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y32_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_TBYTETERM_X0Y37_OLOGIC_X0Y37_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y41_OLOGIC_X0Y42_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_TBYTESRC_X0Y31_OLOGIC_X0Y31_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y41_OLOGIC_X0Y41_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y35_OLOGIC_X0Y36_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y35_OLOGIC_X0Y35_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y29_OLOGIC_X0Y30_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y29_OLOGIC_X0Y29_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y25_OLOGIC_X0Y26_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y25_OLOGIC_X0Y25_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y21_OLOGIC_X0Y22_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y45_OLOGIC_X0Y46_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y45_OLOGIC_X0Y45_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y39_OLOGIC_X0Y40_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y39_OLOGIC_X0Y39_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y33_OLOGIC_X0Y34_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y33_OLOGIC_X0Y33_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y27_OLOGIC_X0Y28_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y27_OLOGIC_X0Y27_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y23_OLOGIC_X0Y24_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
assign LIOI3_X0Y23_OLOGIC_X0Y23_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
endmodule
|
(** * MoreCoq: More About Coq's Tactics *)
Require Export Poly.
(** This chapter introduces several more proof strategies and
tactics that, together, allow us to prove theorems about the
functional programs we have been writing. In particular, we'll
reason about functions that work with natural numbers and lists.
In particular, we will see:
- how to use auxiliary lemmas, in both forwards and backwards reasoning;
- how to reason about data constructors, which are injective and disjoint;
- how to create a strong induction hypotheses (and when
strengthening is required); and
- how to reason by case analysis.
*)
(* ###################################################### *)
(** * The [apply] Tactic *)
(** We often encounter situations where the goal to be proved is
exactly the same as some hypothesis in the context or some
previously proved lemma. *)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n;o] = [n;p] ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
rewrite <- eq1.
(* At this point, we could finish with
"[rewrite -> eq2. reflexivity.]" as we have
done several times above. But we can achieve the
same effect in a single step by using the
[apply] tactic instead: *)
apply eq2. Qed.
(** The [apply] tactic also works with _conditional_ hypotheses
and lemmas: if the statement being applied is an implication, then
the premises of this implication will be added to the list of
subgoals needing to be proved. *)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q;o] = [r;p]) ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
apply eq2. apply eq1. Qed.
(** You may find it instructive to experiment with this proof
and see if there is a way to complete it using just [rewrite]
instead of [apply]. *)
(** Typically, when we use [apply H], the statement [H] will
begin with a [forall] binding some _universal variables_. When
Coq matches the current goal against the conclusion of [H], it
will try to find appropriate values for these variables. For
example, when we do [apply eq2] in the following proof, the
universal variable [q] in [eq2] gets instantiated with [n] and [r]
gets instantiated with [m]. *)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros n m eq1 eq2.
apply eq2. apply eq1. Qed.
(** **** Exercise: 2 stars, optional (silly_ex) *)
(** Complete the following proof without using [simpl]. *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof. intros. apply H. apply H0.
Qed.
(** [] *)
(** To use the [apply] tactic, the (conclusion of the) fact
being applied must match the goal _exactly_ -- for example, [apply]
will not work if the left and right sides of the equality are
swapped. *)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
simpl.
(* Here we cannot use [apply] directly *)
Abort.
(** In this case we can use the [symmetry] tactic, which switches the
left and right sides of an equality in the goal. *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
symmetry.
simpl. (* Actually, this [simpl] is unnecessary, since
[apply] will perform simplification first. *)
apply H. Qed.
(** **** Exercise: 3 stars (apply_exercise1) *)
(** Hint: you can use [apply] with previously defined lemmas, not
just hypotheses in the context. Remember that [SearchAbout] is
your friend. *)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' ->
l' = rev l.
Proof. intros. SearchAbout rev. rewrite H. SearchAbout rev. rewrite rev_involutive.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (apply_rewrite) *)
(** Briefly explain the difference between the tactics [apply] and
[rewrite]. Are there situations where both can usefully be
applied?
apply does all. rewrite baby step.
(* FILL IN HERE *)
*)
(** [] *)
(* ###################################################### *)
(** * The [apply ... with ...] Tactic *)
(** The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
Example trans_eq_example : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
Theorem trans_eq : forall (X:Type) (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(** Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
apply trans_eq with (m:=[c;d]). apply eq1. apply eq2. Qed.
(** Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: [apply trans_eq with [c,d]]. *)
(** **** Exercise: 3 stars, optional (apply_with_exercise) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof. intros. apply trans_eq with m. apply H0. apply H.
Qed.
(** [] *)
(* ###################################################### *)
(** * The [inversion] tactic *)
(** Recall the definition of natural numbers:
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
It is clear from this definition that every number has one of two
forms: either it is the constructor [O] or it is built by applying
the constructor [S] to another number. But there is more here than
meets the eye: implicit in the definition (and in our informal
understanding of how datatype declarations work in other
programming languages) are two other facts:
- The constructor [S] is _injective_. That is, the only way we can
have [S n = S m] is if [n = m].
- The constructors [O] and [S] are _disjoint_. That is, [O] is not
equal to [S n] for any [n]. *)
(** Similar principles apply to all inductively defined types: all
constructors are injective, and the values built from distinct
constructors are never equal. For lists, the [cons] constructor is
injective and [nil] is different from every non-empty list. For
booleans, [true] and [false] are unequal. (Since neither [true]
nor [false] take any arguments, their injectivity is not an issue.) *)
(** Coq provides a tactic called [inversion] that allows us to exploit
these principles in proofs.
The [inversion] tactic is used like this. Suppose [H] is a
hypothesis in the context (or a previously proven lemma) of the
form
c a1 a2 ... an = d b1 b2 ... bm
for some constructors [c] and [d] and arguments [a1 ... an] and
[b1 ... bm]. Then [inversion H] instructs Coq to "invert" this
equality to extract the information it contains about these terms:
- If [c] and [d] are the same constructor, then we know, by the
injectivity of this constructor, that [a1 = b1], [a2 = b2],
etc.; [inversion H] adds these facts to the context, and tries
to use them to rewrite the goal.
- If [c] and [d] are different constructors, then the hypothesis
[H] is contradictory. That is, a false assumption has crept
into the context, and this means that any goal whatsoever is
provable! In this case, [inversion H] marks the current goal as
completed and pops it off the goal stack. *)
(** The [inversion] tactic is probably easier to understand by
seeing it in action than from general descriptions like the above.
Below you will find example theorems that demonstrate the use of
[inversion] and exercises to test your understanding. *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros n m eq. inversion eq. reflexivity. Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. inversion eq. reflexivity. Qed.
(** As a convenience, the [inversion] tactic can also
destruct equalities between complex values, binding
multiple variables as it goes. *)
Theorem silly5 : forall (n m o : nat),
[n;m] = [o;o] ->
[n] = [m].
Proof.
intros n m o eq. inversion eq. reflexivity. Qed.
(** **** Exercise: 1 star (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof. intros. inversion H. inversion H0. symmetry. apply H2.
Qed.
(** [] *)
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
(** **** Exercise: 1 star (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof. intros. inversion H.
Qed.
(** [] *)
(** While the injectivity of constructors allows us to reason
[forall (n m : nat), S n = S m -> n = m], the reverse direction of
the implication is an instance of a more general fact about
constructors and functions, which we will often find useful: *)
Theorem f_equal : forall (A B : Type) (f: A -> B) (x y: A),
x = y -> f x = f y.
Proof. intros A B f x y eq. rewrite eq. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (practice) *)
(** A couple more nontrivial but not-too-complicated proofs to work
together in class, or for you to work as exercises. *)
Theorem beq_nat_0_l : forall n,
beq_nat 0 n = true -> n = 0.
Proof. intros. SearchAbout beq_nat. induction n. reflexivity. simpl. simpl in H. inversion H.
Qed.
Theorem beq_nat_0_r : forall n,
beq_nat n 0 = true -> n = 0.
Proof. intros. induction n. reflexivity. simpl in H. inversion H.
Qed.
(** [] *)
(* ###################################################### *)
(** * Using Tactics on Hypotheses *)
(** By default, most tactics work on the goal formula and leave
the context unchanged. However, most tactics also have a variant
that performs a similar operation on a statement in the context.
For example, the tactic [simpl in H] performs simplification in
the hypothesis named [H] in the context. *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros n m b H. simpl in H. apply H. Qed.
(** Similarly, the tactic [apply L in H] matches some
conditional statement [L] (of the form [L1 -> L2], say) against a
hypothesis [H] in the context. However, unlike ordinary
[apply] (which rewrites a goal matching [L2] into a subgoal [L1]),
[apply L in H] matches [H] against [L1] and, if successful,
replaces it with [L2].
In other words, [apply L in H] gives us a form of "forward
reasoning" -- from [L1 -> L2] and a hypothesis matching [L1], it
gives us a hypothesis matching [L2]. By contrast, [apply L] is
"backward reasoning" -- it says that if we know [L1->L2] and we
are trying to prove [L2], it suffices to prove [L1].
Here is a variant of a proof from above, using forward reasoning
throughout instead of backward reasoning. *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros n eq H.
symmetry in H. apply eq in H. symmetry in H.
apply H. Qed.
(** Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached. Backward reasoning starts from
the _goal_, and iteratively reasons about what would imply the
goal, until premises or previously proven theorems are reached.
If you've seen informal proofs before (for example, in a math or
computer science class), they probably used forward reasoning. In
general, Coq tends to favor backward reasoning, but in some
situations the forward style can be easier to use or to think
about. *)
(** **** Exercise: 3 stars (plus_n_n_injective) *)
(** Practice using "in" variants in this exercise. *)
Theorem mustbezero : forall n : nat, n + n = n -> n = 0.
intros. induction n as [| n']. reflexivity. simpl in H . rewrite plus_n_Sm in H.
inversion H.
rewrite <- plus_n_Sm in H1.
inversion H1. rewrite <- plus_n_Sm in H2. inversion H2. apply plus_id_example in H2.
rewrite <- H2 in IHn'. remember (S (n' + n') + S (n' + n')) as p. rewrite <- H0 in IHn'.
Abort. (*
rewrit
inversion H2. remember n' as p.
inversion H. > rewrite succ1 in H. inversion H. rewrite <- plus_n_Sm in H1.
rewrite <- plus_n_Sm in H. rewrite <- H1 in IHn'.
simpl in IHn'. rewrite succ1 in IHn'. rewrite succ1 in IHn'. rewrite succ1 in H1. rewrite H1 in IHn'. rewrite <- H1 in H.
inversion H. n' into p. in IHn'. rewrite <- succ1 in H1. rewrite H1 in H2.
rewrite succ1 in H2. rewrite <- H2 in IHn'.
assert (n' + n' +n' = (n' + n' ) + n'). reflexivity.
rewrite plus_comm in IHn'. rewrite succ1 in IHn'. rewrite H in IHn'.
rewrite succ1 in IHn'.
rewrite <- H in IHn'. inversion H1. inversion H.
simpl in H. inversion H. rewrite <- H in H1. rewrite <- plus_n_Sm in H1.
SearchAbout beq_nat. inversion H. rewrite <- plus_n_Sm in H2.
inversion H. SearchAbout "+". apply plus_id_example in H2.
rewrite <- plus_n_Sm in H3.
rewrite plus_n_Sm in H1.
rewrite succ1 in H1. symmetry in H1.
rewrite succ1 in H3. symmetry in H3.
assert (n' + n' = n'). rewrite <- H2.
rewrite succ1. rewrite <- H3.
inversion H2.
inversion H3.
rewrite H3. simpl.
inversion H.
SearchAbout "+". rewrite succ1 in H2. inversion H2.
rewrite <- H in H1.
inversion H1.
rewrite <- plus_n_Sm in H1. inversion H2.
*)
Theorem m2 : forall n : nat, n + n = 2 * n.
Proof. intros. simpl. rewrite plus_0_r. reflexivity.
Qed.
Theorem t : forall n :nat, n + n = 0 -> n = 0.
Proof. intros. induction n. reflexivity. rewrite <- succ1 in H. inversion H.
Qed.
Theorem test : forall m : nat, 1 + 1 = m + m -> 1 = m.
Proof. intros. simpl. simpl in H. induction m. simpl in H. inversion H. rewrite <- succ1 in H.
rewrite <- plus_n_Sm in H. inversion H. simpl in H1. symmetry in H1. apply t in H1. rewrite H1. reflexivity.
Theorem plus_n_n_injective : forall n m, n + n = m + m -> n = m.
intros n. induction n as [| n']. intros. simpl in H. symmetry in H. apply t in H. rewrite H. reflexivity.
intros.
induction m. simpl in H. inversion H. rewrite <- succ1 in H. rewrite <- succ1 in H. rewrite <- plus_n_Sm in H. rewrite <- plus_n_Sm in H.
inversion H. apply IHn' in H1. rewrite H1. reflexivity.
Qed.
(** [] *)
(* ###################################################### *)
(** * Varying the Induction Hypothesis *)
(** Sometimes it is important to control the exact form of the
induction hypothesis when carrying out inductive proofs in Coq.
In particular, we need to be careful about which of the
assumptions we move (using [intros]) from the goal to the context
before invoking the [induction] tactic. For example, suppose
we want to show that the [double] function is injective -- i.e.,
that it always maps different arguments to different results:
Theorem double_injective: forall n m, double n = double m -> n = m.
The way we _start_ this proof is a little bit delicate: if we
begin it with
intros n. induction n.
]]
all is well. But if we begin it with
intros n m. induction n.
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'". apply f_equal.
(* Here we are stuck. The induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the goal is not provable. *)
Abort.
(** What went wrong? *)
(** The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context --
intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we know
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.) *)
(** To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for _every_ [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
SCase "m = O".
(* The 0 case is trivial *)
inversion eq.
SCase "m = S m'".
apply f_equal.
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
apply IHn'. inversion eq. reflexivity. Qed.
(** What this teaches us is that we need to be careful about using
induction to try to prove something too specific: If we're proving
a property of [n] and [m] by induction on [n], we may need to
leave [m] generic. *)
(** The proof of this theorem (left as an exercise) has to be treated similarly: *)
(** **** Exercise: 2 stars (beq_nat_true) *)
Theorem beq_nat_true : forall n m,
beq_nat n m = true -> n = m.
Proof. intros n. induction n. intros. destruct m. reflexivity. simpl in H. inversion H.
induction m. intros. inversion H. intros. simpl in H. apply IHn in H. rewrite H. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (beq_nat_true_informal) *)
(** Give a careful informal proof of [beq_nat_true], being as explicit
as possible about quantifiers. *)
(* FILL IN HERE *)
(** [] *)
(** The strategy of doing fewer [intros] before an [induction] doesn't
always work directly; sometimes a little _rearrangement_ of
quantified variables is needed. Suppose, for example, that we
wanted to prove [double_injective] by induction on [m] instead of
[n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
(* Stuck again here, just like before. *)
Abort.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) *)
(** What can we do about this? One possibility is to rewrite the
statement of the lemma so that [m] is quantified before [n]. This
will work, but it's not nice: We don't want to have to mangle the
statements of lemmas to fit the needs of a particular strategy for
proving them -- we want to state them in the most clear and
natural way. *)
(** What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". SearchAbout "f_equal". apply f_equal.
apply IHm'. inversion eq. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that
the proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [double n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** Here's another illustration of [inversion] and using an
appropriately general induction hypothesis. This is a slightly
roundabout way of stating a fact that we have already proved
above. The extra equalities force us to do a little more
equational reasoning and exercise some of the tactics we've seen
recently. *)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l'].
Case "l = []".
intros n eq. rewrite <- eq. reflexivity.
Case "l = v' :: l'".
intros n eq. simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. apply IHl'. inversion eq. reflexivity. Qed.
(** It might be tempting to start proving the above theorem
by introducing [n] and [eq] at the outset. However, this leads
to an induction hypothesis that is not strong enough. Compare
the above to the following (aborted) attempt: *)
Theorem length_snoc_bad : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l n eq. induction l as [| v' l'].
Case "l = []".
rewrite <- eq. reflexivity.
Case "l = v' :: l'".
simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. Abort. (* apply IHl'. *) (* The IH doesn't apply! *)
(** As in the double examples, the problem is that by
introducing [n] before doing induction on [l], the induction
hypothesis is specialized to one particular natural number, namely
[n]. In the induction case, however, we need to be able to use
the induction hypothesis on some other natural number [n'].
Retaining the more general form of the induction hypothesis thus
gives us more flexibility.
In general, a good rule of thumb is to make the induction hypothesis
as general as possible. *)
(** **** Exercise: 3 stars (gen_dep_practice) *)
(** Prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index n l = None.
Proof. intros n X l. generalize dependent n . induction l as [| v' l']. simpl. reflexivity.
induction n. simpl. intros. inversion H.
simpl. intros. apply IHl'. inversion H. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index n l = None].
_Proof_:
I'm too lazy.
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (gen_dep_practice_more) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof. intros. generalize dependent n. induction l as [|v' l']. simpl. intros. rewrite H. reflexivity.
simpl. induction n as [|n']. simpl. intros. inversion H. intros. inversion H. apply IHl' in H1. rewrite H.
rewrite H1. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]
from [Lists]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof. intros. generalize dependent n. generalize dependent l2. induction l1 as [|l1'].
simpl. induction l2 as [|l2']. simpl. intros. exact H.
simpl. intros. exact H. simpl. intros. simpl in H. induction n. simpl. inversion H. inversion H. apply IHl1 in H1.
rewrite H. rewrite H1. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
Theorem nil_app_r : forall (X : Type) (l : list X), l = l ++ [].
Proof. intros. induction l . reflexivity. simpl. rewrite <- IHl. reflexivity.
Qed.
SearchAbout "app_length".
Theorem app_length_helper : forall (X : Type) (l1 l2 : list X),
length (l1 ++ l2) = length (l2 ++ l1).
Proof. intros X l1. simpl. induction l1. simpl. intros. apply f_equal. SearchAbout app. simpl. apply nil_app_r.
simpl. induction l2. simpl. rewrite <- nil_app_r. reflexivity. simpl. apply f_equal.
rewrite IHl1. simpl. rewrite <- IHl2. apply f_equal. rewrite IHl1. reflexivity.
Qed.
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof. intros. generalize dependent n. induction l . simpl. intros. rewrite <- H. reflexivity.
simpl. intros. destruct n. simpl. inversion H. simpl. rewrite app_length_helper. simpl.
rewrite <- plus_n_Sm. apply f_equal. apply f_equal. inversion H. apply IHl in H1. rewrite H1. inversion H. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (double_induction) *)
(** Prove the following principle of induction over two naturals. *)
Theorem double_induction: forall (P : nat -> nat -> Prop),
P 0 0 ->
(forall m, P m 0 -> P (S m) 0) ->
(forall n, P 0 n -> P 0 (S n)) ->
(forall m n, P m n -> P (S m) (S n)) ->
forall m n, P m n.
Proof. simpl. intros. generalize dependent n. induction m. simpl. induction n. exact H.
apply H1. exact IHn. destruct n . apply H0. apply IHm. apply H2. apply IHm.
Qed.
(** [] *)
(* ###################################################### *)
(** * Using [destruct] on Compound Expressions *)
(** We have seen many examples where the [destruct] tactic is
used to perform case analysis of the value of some variable. But
sometimes we need to reason by cases on the result of some
_expression_. We can also do this with [destruct].
Here are some examples: *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
Case "beq_nat n 3 = true". reflexivity.
Case "beq_nat n 3 = false". destruct (beq_nat n 5).
SCase "beq_nat n 5 = true". reflexivity.
SCase "beq_nat n 5 = false". reflexivity. Qed.
(** After unfolding [sillyfun] in the above proof, we find that
we are stuck on [if (beq_nat n 3) then ... else ...]. Well,
either [n] is equal to [3] or it isn't, so we use [destruct
(beq_nat n 3)] to let us reason about the two cases.
In general, the [destruct] tactic can be used to perform case
analysis of the results of arbitrary computations. If [e] is an
expression whose type is some inductively defined type [T], then,
for each constructor [c] of [T], [destruct e] generates a subgoal
in which all occurrences of [e] (in the goal and in the context)
are replaced by [c].
*)
(** **** Exercise: 1 star (override_shadow) *)
Theorem override_shadow : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof. intros. simpl. unfold override. destruct (beq_nat k1 k2). reflexivity.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (combine_split) *)
(** Complete the proof below *)
(*PAUL KLINE*)
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) ->
combine l1 l2 = l.
Proof. intros. generalize dependent l1. generalize dependent l2. simpl. induction l. simpl.
intros. inversion H. reflexivity.
intro l2. induction l2. intros. simpl in H. destruct x. inversion H.
simpl. destruct x. simpl. intros. inversion H.
induction l1. simpl. apply f_equal. simpl. apply IHl. inversion H1.
simpl. apply f_equal. apply IHl.
destruct (split l). simpl. reflexivity.
Qed.
(** [] *)
(** Sometimes, doing a [destruct] on a compound expression (a
non-variable) will erase information we need to complete a proof. *)
(** For example, suppose
we define a function [sillyfun1] like this: *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(** And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* stuck... *)
Abort.
(** We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep some
memory of this expression and how it was destructed, because we
need to be able to reason that since, in this branch of the case
analysis, [beq_nat n 3 = true], it must be that [n = 3], from
which it follows that [n] is odd.
What we would really like is to substitute away all existing
occurences of [beq_nat n 3], but at the same time add an equation
to the context that records which case we are in. The [eqn:]
qualifier allows us to introduce such an equation (with whatever
name we choose). *)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3) eqn:Heqe3.
(* Now we have the same state as at the point where we got stuck
above, except that the context contains an extra equality
assumption, which is exactly what we need to make progress. *)
Case "e3 = true". apply beq_nat_true in Heqe3.
rewrite -> Heqe3. reflexivity.
Case "e3 = false".
(* When we come to the second equality test in the body of the
function we are reasoning about, we can use [eqn:] again in the
same way, allow us to finish the proof. *)
destruct (beq_nat n 5) eqn:Heqe5.
SCase "e5 = true".
apply beq_nat_true in Heqe5.
rewrite -> Heqe5. reflexivity.
SCase "e5 = false". inversion eq. Qed.
(** **** Exercise: 2 stars (destruct_eqn_practice) *)
Theorem bool_fn_applied_thrice :
forall (f : bool -> bool) (b : bool),
f (f (f b)) = f b.
Proof. intros. destruct b eqn:hb. destruct (f true) eqn :fb. rewrite fb. rewrite fb. reflexivity.
destruct (f false) eqn : hfalse. rewrite fb. reflexivity. rewrite hfalse. reflexivity.
destruct (f false) eqn : a. destruct (f true) eqn : htrue. exact htrue. exact a. rewrite a. rewrite a.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (override_same) *)
Theorem override_same : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override f k1 x1) k2 = f k2.
Proof. intros. simpl. unfold override. destruct (beq_nat k1 k2) eqn: b1. rewrite <- H.
SearchAbout beq_nat. apply beq_nat_true in b1. rewrite b1. reflexivity.
reflexivity.
Qed.
(** [] *)
(* ################################################################## *)
(** * Review *)
(** We've now seen a bunch of Coq's fundamental tactics. We'll
introduce a few more as we go along through the coming lectures,
and later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [symmetry]:
changes a goal of the form [t=u] into [u=t]
- [symmetry in H]:
changes a hypothesis of the form [t=u] into [u=t]
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [destruct... eqn:...]:
specify the name of an equation to be added to the context,
recording the result of the case analysis
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
- [generalize dependent x]:
move the variable [x] (and anything else that depends on it)
from the context back to an explicit hypothesis in the goal
formula
*)
(* ###################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (beq_nat_sym) *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof. intro n. induction n . intro m. induction m . reflexivity.
simpl. reflexivity.
intros. symmetry. destruct m eqn : hm. simpl. reflexivity. simpl. symmetry. apply IHn.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (beq_nat_sym_informal) *)
(** Give an informal proof of this lemma that corresponds to your
formal proof above:
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (beq_nat_trans) *)
Theorem beq_nat_trans : forall n m p,
beq_nat n m = true ->
beq_nat m p = true ->
beq_nat n p = true.
Proof. intros. apply beq_nat_true in H. rewrite <- H in H0. exact H0.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (split_combine) *)
(** We have just proven that for all lists of pairs, [combine] is the
inverse of [split]. How would you formalize the statement that
[split] is the inverse of [combine]? When is this property true?
Complete the definition of [split_combine_statement] below with a
property that states that [split] is the inverse of
[combine]. Then, prove that the property holds. (Be sure to leave
your induction hypothesis general by not doing [intros] on more
things than necessary. Hint: what property do you need of [l1]
and [l2] for [split] [combine l1 l2 = (l1,l2)] to be true?) *)
Definition split_combine_statement : Prop :=
forall (X : Type) (l1 l2 : list X ),length l1 = length l2 -> split (combine l1 l2) = (l1,l2).
Theorem length_0 : forall (X : Type) (l : list X), length l = 0 -> l = [].
Proof. intros. induction l. reflexivity. simpl in H. inversion H.
Qed.
Theorem split_combine : split_combine_statement.
Proof. intro X. intros. generalize dependent l2. induction l1. simpl. intros. symmetry in H. apply length_0 in H. rewrite H. reflexivity. destruct l2.
simpl. intros. inversion H. intros. inversion H. simpl. apply IHl1 in H1. rewrite H1. simpl. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (override_permute) *)
Theorem override_permute : forall (X:Type) x1 x2 k1 k2 k3 (f : nat->X),
beq_nat k2 k1 = false ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof. simpl. intro. intro. intro. intro. intros. generalize dependent k1. generalize dependent k2. simpl. induction k1. intros. unfold override.
intros. induction k3. simpl. rewrite H. reflexivity. simpl. reflexivity. intros. unfold override. destruct (beq_nat (S k1) k3) eqn : a.
destruct k3. apply beq_nat_true in a. rewrite a in H. rewrite H. reflexivity. apply beq_nat_true in a . inversion a. rewrite H1 in H. rewrite H. reflexivity.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (filter_exercise) *)
(** This one is a bit challenging. Pay attention to the form of your IH. *)
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced (forall_exists_challenge) *)
(** Define two recursive [Fixpoints], [forallb] and [existsb]. The
first checks whether every element in a list satisfies a given
predicate:
forallb oddb [1;3;5;7;9] = true
forallb negb [false;false] = true
forallb evenb [0;2;4;5] = false
forallb (beq_nat 5) [] = true
The second checks whether there exists an element in the list that
satisfies a given predicate:
existsb (beq_nat 5) [0;2;3;6] = false
existsb (andb true) [true;true;false] = true
existsb oddb [1;0;0;0;0;3] = true
existsb evenb [] = false
Next, define a _nonrecursive_ version of [existsb] -- call it
[existsb'] -- using [forallb] and [negb].
Prove theorem [existsb_existsb'] that [existsb'] and [existsb] have
the same behavior.
*)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 16:01:37 -0500 (Wed, 31 Dec 2014) $ *)
|
//----------------------------------------------------------------------
// Title : Demo Testbench
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : demo_tb.v
// Version : 1.3
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------
// Description: This testbench will exercise the PHY ports of the EMAC
// to demonstrate the functionality.
//----------------------------------------------------------------------
`timescale 1ps / 1ps
module testbench;
//--------------------------------------------------------------------
// Testbench signals
//--------------------------------------------------------------------
wire reset;
wire tx_client_clk;
wire [7:0] tx_ifg_delay;
wire rx_client_clk;
wire [15:0] pause_val;
wire pause_req;
// GMII wires
wire gmii_tx_clk;
wire gmii_tx_en;
wire gmii_tx_er;
wire [7:0] gmii_txd;
wire gmii_rx_clk;
wire gmii_rx_dv;
wire gmii_rx_er;
wire [7:0] gmii_rxd;
// Not asserted: full duplex only testbench
wire mii_tx_clk;
wire gmii_crs;
wire gmii_col;
// MDIO wires
wire mdc;
wire mdc_in;
wire mdio_in;
wire mdio_out;
wire mdio_tri;
// Host wires
wire [1:0] host_opcode;
wire [9:0] host_addr;
wire [31:0] host_wr_data;
wire [31:0] host_rd_data;
wire host_miim_sel;
wire host_req;
wire host_miim_rdy;
// Clock wires
wire host_clk;
reg gtx_clk;
reg refclk;
//----------------------------------------------------------------
// Testbench Semaphores
//----------------------------------------------------------------
wire configuration_busy;
wire monitor_finished_1g;
wire monitor_finished_100m;
wire monitor_finished_10m;
//----------------------------------------------------------------
// Wire up device under test
//----------------------------------------------------------------
v6_emac_v1_3_example_design dut
(
// Client receiver interface
.EMACCLIENTRXDVLD (),
.EMACCLIENTRXFRAMEDROP (),
.EMACCLIENTRXSTATS (),
.EMACCLIENTRXSTATSVLD (),
.EMACCLIENTRXSTATSBYTEVLD (),
// Client transmitter interface
.CLIENTEMACTXIFGDELAY (tx_ifg_delay),
.EMACCLIENTTXSTATS (),
.EMACCLIENTTXSTATSVLD (),
.EMACCLIENTTXSTATSBYTEVLD (),
// MAC Control interface
.CLIENTEMACPAUSEREQ (pause_req),
.CLIENTEMACPAUSEVAL (pause_val),
// Clock signal
.GTX_CLK (gtx_clk),
// GMII interface
.GMII_TXD (gmii_txd),
.GMII_TX_EN (gmii_tx_en),
.GMII_TX_ER (gmii_tx_er),
.GMII_TX_CLK (gmii_tx_clk),
.GMII_RXD (gmii_rxd),
.GMII_RX_DV (gmii_rx_dv),
.GMII_RX_ER (gmii_rx_er),
.GMII_RX_CLK (gmii_rx_clk),
// MDIO interface
.MDC (mdc),
.MDIO_I (mdio_in),
.MDIO_O (mdio_out),
.MDIO_T (mdio_tri),
// Host interface
.HOSTCLK (host_clk),
.HOSTOPCODE (host_opcode),
.HOSTREQ (host_req),
.HOSTMIIMSEL (host_miim_sel),
.HOSTADDR (host_addr),
.HOSTWRDATA (host_wr_data),
.HOSTMIIMRDY (host_miim_rdy),
.HOSTRDDATA (host_rd_data),
.REFCLK (refclk),
// Asynchronous reset
.RESET (reset)
);
//--------------------------------------------------------------------------
// Flow control is unused in this demonstration
//--------------------------------------------------------------------------
assign pause_req = 1'b0;
assign pause_val = 16'b0;
// IFG stretching not used in demo.
assign tx_ifg_delay = 8'b0;
//--------------------------------------------------------------------------
// Simulate the MDIO_IN port floating high
//--------------------------------------------------------------------------
assign (strong0, weak1) mdio_in = 1'b1;
//--------------------------------------------------------------------------
// Clock drivers
//--------------------------------------------------------------------------
// Drive GTX_CLK at 125 MHz
initial
begin
gtx_clk <= 1'b0;
#10000;
forever
begin
gtx_clk <= 1'b0;
#4000;
gtx_clk <= 1'b1;
#4000;
end
end
// Drive refclk at 200MHz
initial
begin
refclk <= 1'b0;
#10000;
forever
begin
refclk <= 1'b1;
#2500;
refclk <= 1'b0;
#2500;
end
end
//--------------------------------------------------------------------
// Instantiate the PHY stimulus and monitor
//--------------------------------------------------------------------
phy_tb phy_test
(
//----------------------------------------------------------------
// GMII interface
//----------------------------------------------------------------
.gmii_txd (gmii_txd),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_er (gmii_tx_er),
.gmii_tx_clk (gmii_tx_clk),
.gmii_rxd (gmii_rxd),
.gmii_rx_dv (gmii_rx_dv),
.gmii_rx_er (gmii_rx_er),
.gmii_rx_clk (gmii_rx_clk),
.gmii_col (gmii_col),
.gmii_crs (gmii_crs),
.mii_tx_clk (mii_tx_clk),
//----------------------------------------------------------------
// Testbench semaphores
//----------------------------------------------------------------
.configuration_busy (configuration_busy),
.monitor_finished_1g (monitor_finished_1g),
.monitor_finished_100m (monitor_finished_100m),
.monitor_finished_10m (monitor_finished_10m),
.monitor_error (monitor_error)
);
//--------------------------------------------------------------------
// Instantiate the host configuration stimulus
//--------------------------------------------------------------------
configuration_tb config_test
(
.reset (reset),
//----------------------------------------------------------------
// Host interface
//----------------------------------------------------------------
.host_clk (host_clk),
.host_opcode (host_opcode),
.host_req (host_req),
.host_miim_sel (host_miim_sel),
.host_addr (host_addr),
.host_wr_data (host_wr_data),
.host_miim_rdy (host_miim_rdy),
.host_rd_data (host_rd_data),
//----------------------------------------------------------------
// Testbench semaphores
//----------------------------------------------------------------
.configuration_busy (configuration_busy),
.monitor_finished_1g (monitor_finished_1g),
.monitor_finished_100m (monitor_finished_100m),
.monitor_finished_10m (monitor_finished_10m),
.monitor_error (monitor_error)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4BB_2_V
`define SKY130_FD_SC_HDLL__AND4BB_2_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4bb_2 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4bb_2 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4BB_2_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / DSP_MULTIPLIER
// /___/ /\ Filename : DSP_MULTIPLIER.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// 10/22/14 - 808642 - Added #1 to $finish
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP_MULTIPLIER #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter AMULTSEL = "A",
parameter BMULTSEL = "B",
parameter USE_MULT = "MULTIPLY"
)(
output AMULT26,
output BMULT17,
output [44:0] U,
output [44:0] V,
input [26:0] A2A1,
input [26:0] AD_DATA,
input [17:0] B2B1
);
// define constants
localparam MODULE_NAME = "DSP_MULTIPLIER";
// Parameter encodings and registers
localparam AMULTSEL_A = 0;
localparam AMULTSEL_AD = 1;
localparam BMULTSEL_AD = 1;
localparam BMULTSEL_B = 0;
localparam USE_MULT_DYNAMIC = 1;
localparam USE_MULT_MULTIPLY = 0;
localparam USE_MULT_NONE = 2;
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DSP_MULTIPLIER_dr.v"
`else
reg [16:1] AMULTSEL_REG = AMULTSEL;
reg [16:1] BMULTSEL_REG = BMULTSEL;
reg [64:1] USE_MULT_REG = USE_MULT;
`endif
`ifdef XIL_XECLIB
wire AMULTSEL_BIN;
wire BMULTSEL_BIN;
wire [1:0] USE_MULT_BIN;
`else
reg AMULTSEL_BIN;
reg BMULTSEL_BIN;
reg [1:0] USE_MULT_BIN;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign AMULTSEL_BIN =
(AMULTSEL_REG == "A") ? AMULTSEL_A :
(AMULTSEL_REG == "AD") ? AMULTSEL_AD :
AMULTSEL_A;
assign BMULTSEL_BIN =
(BMULTSEL_REG == "B") ? BMULTSEL_B :
(BMULTSEL_REG == "AD") ? BMULTSEL_AD :
BMULTSEL_B;
assign USE_MULT_BIN =
(USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY :
(USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC :
(USE_MULT_REG == "NONE") ? USE_MULT_NONE :
USE_MULT_MULTIPLY;
`else
always @(trig_attr) begin
#1;
AMULTSEL_BIN =
(AMULTSEL_REG == "A") ? AMULTSEL_A :
(AMULTSEL_REG == "AD") ? AMULTSEL_AD :
AMULTSEL_A;
BMULTSEL_BIN =
(BMULTSEL_REG == "B") ? BMULTSEL_B :
(BMULTSEL_REG == "AD") ? BMULTSEL_AD :
BMULTSEL_B;
USE_MULT_BIN =
(USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY :
(USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC :
(USE_MULT_REG == "NONE") ? USE_MULT_NONE :
USE_MULT_MULTIPLY;
end
`endif
`ifndef XIL_TIMING
initial begin
$display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME);
#1 $finish;
end
`endif
`ifndef XIL_XECLIB
always @(trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((AMULTSEL_REG != "A") &&
(AMULTSEL_REG != "AD"))) begin
$display("Error: [Unisim %s-101] AMULTSEL attribute is set to %s. Legal values for this attribute are A or AD. Instance: %m", MODULE_NAME, AMULTSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((BMULTSEL_REG != "B") &&
(BMULTSEL_REG != "AD"))) begin
$display("Error: [Unisim %s-102] BMULTSEL attribute is set to %s. Legal values for this attribute are B or AD. Instance: %m", MODULE_NAME, BMULTSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_MULT_REG != "MULTIPLY") &&
(USE_MULT_REG != "DYNAMIC") &&
(USE_MULT_REG != "NONE"))) begin
$display("Error: [Unisim %s-103] USE_MULT attribute is set to %s. Legal values for this attribute are MULTIPLY, DYNAMIC or NONE. Instance: %m", MODULE_NAME, USE_MULT_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
// begin behavioral model
localparam M_WIDTH = 45;
reg [17:0] b_mult_mux;
reg [26:0] a_mult_mux;
reg [M_WIDTH-1:0] mult;
reg [M_WIDTH-2:0] ps_u_mask;
reg [M_WIDTH-2:0] ps_v_mask;
// initialize regs
`ifndef XIL_XECLIB
initial begin
ps_u_mask = 44'h55555555555;
ps_v_mask = 44'haaaaaaaaaaa;
end
`endif
always @(*) begin
if (AMULTSEL_BIN == AMULTSEL_A) a_mult_mux = A2A1;
else a_mult_mux = AD_DATA;
end
always @(*) begin
if (BMULTSEL_BIN == BMULTSEL_B) b_mult_mux = B2B1;
else b_mult_mux = AD_DATA;
end
assign AMULT26 = a_mult_mux[26];
assign BMULT17 = b_mult_mux[17];
// U[44],V[44] 11 when mult[44]=0, 10 when mult[44]=1
assign U = {1'b1, mult[43:0] & ps_u_mask};
assign V = {~mult[44], mult[43:0] & ps_v_mask};
always @(*) begin
if (USE_MULT_BIN == USE_MULT_NONE) mult = 45'b0;
else mult = ({{18{a_mult_mux[26]}},a_mult_mux} * {{27{b_mult_mux[17]}},b_mult_mux});
end
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(A2A1[0] => U[10]) = (0:0:0, 0:0:0);
(A2A1[0] => U[11]) = (0:0:0, 0:0:0);
(A2A1[0] => U[12]) = (0:0:0, 0:0:0);
(A2A1[0] => U[13]) = (0:0:0, 0:0:0);
(A2A1[0] => U[14]) = (0:0:0, 0:0:0);
(A2A1[0] => U[15]) = (0:0:0, 0:0:0);
(A2A1[0] => U[16]) = (0:0:0, 0:0:0);
(A2A1[0] => U[17]) = (0:0:0, 0:0:0);
(A2A1[0] => U[18]) = (0:0:0, 0:0:0);
(A2A1[0] => U[19]) = (0:0:0, 0:0:0);
(A2A1[0] => U[1]) = (0:0:0, 0:0:0);
(A2A1[0] => U[20]) = (0:0:0, 0:0:0);
(A2A1[0] => U[21]) = (0:0:0, 0:0:0);
(A2A1[0] => U[2]) = (0:0:0, 0:0:0);
(A2A1[0] => U[3]) = (0:0:0, 0:0:0);
(A2A1[0] => U[4]) = (0:0:0, 0:0:0);
(A2A1[0] => U[5]) = (0:0:0, 0:0:0);
(A2A1[0] => U[6]) = (0:0:0, 0:0:0);
(A2A1[0] => U[7]) = (0:0:0, 0:0:0);
(A2A1[0] => U[8]) = (0:0:0, 0:0:0);
(A2A1[0] => U[9]) = (0:0:0, 0:0:0);
(A2A1[0] => V[0]) = (0:0:0, 0:0:0);
(A2A1[0] => V[10]) = (0:0:0, 0:0:0);
(A2A1[0] => V[11]) = (0:0:0, 0:0:0);
(A2A1[0] => V[12]) = (0:0:0, 0:0:0);
(A2A1[0] => V[13]) = (0:0:0, 0:0:0);
(A2A1[0] => V[14]) = (0:0:0, 0:0:0);
(A2A1[0] => V[15]) = (0:0:0, 0:0:0);
(A2A1[0] => V[16]) = (0:0:0, 0:0:0);
(A2A1[0] => V[17]) = (0:0:0, 0:0:0);
(A2A1[0] => V[18]) = (0:0:0, 0:0:0);
(A2A1[0] => V[19]) = (0:0:0, 0:0:0);
(A2A1[0] => V[20]) = (0:0:0, 0:0:0);
(A2A1[0] => V[4]) = (0:0:0, 0:0:0);
(A2A1[0] => V[5]) = (0:0:0, 0:0:0);
(A2A1[0] => V[6]) = (0:0:0, 0:0:0);
(A2A1[0] => V[7]) = (0:0:0, 0:0:0);
(A2A1[0] => V[8]) = (0:0:0, 0:0:0);
(A2A1[0] => V[9]) = (0:0:0, 0:0:0);
(A2A1[10] => U[11]) = (0:0:0, 0:0:0);
(A2A1[10] => U[12]) = (0:0:0, 0:0:0);
(A2A1[10] => U[13]) = (0:0:0, 0:0:0);
(A2A1[10] => U[14]) = (0:0:0, 0:0:0);
(A2A1[10] => U[15]) = (0:0:0, 0:0:0);
(A2A1[10] => U[16]) = (0:0:0, 0:0:0);
(A2A1[10] => U[17]) = (0:0:0, 0:0:0);
(A2A1[10] => U[18]) = (0:0:0, 0:0:0);
(A2A1[10] => U[19]) = (0:0:0, 0:0:0);
(A2A1[10] => U[20]) = (0:0:0, 0:0:0);
(A2A1[10] => U[21]) = (0:0:0, 0:0:0);
(A2A1[10] => U[22]) = (0:0:0, 0:0:0);
(A2A1[10] => U[23]) = (0:0:0, 0:0:0);
(A2A1[10] => U[24]) = (0:0:0, 0:0:0);
(A2A1[10] => U[25]) = (0:0:0, 0:0:0);
(A2A1[10] => U[26]) = (0:0:0, 0:0:0);
(A2A1[10] => U[27]) = (0:0:0, 0:0:0);
(A2A1[10] => U[28]) = (0:0:0, 0:0:0);
(A2A1[10] => U[29]) = (0:0:0, 0:0:0);
(A2A1[10] => U[30]) = (0:0:0, 0:0:0);
(A2A1[10] => U[31]) = (0:0:0, 0:0:0);
(A2A1[10] => V[10]) = (0:0:0, 0:0:0);
(A2A1[10] => V[11]) = (0:0:0, 0:0:0);
(A2A1[10] => V[12]) = (0:0:0, 0:0:0);
(A2A1[10] => V[13]) = (0:0:0, 0:0:0);
(A2A1[10] => V[14]) = (0:0:0, 0:0:0);
(A2A1[10] => V[15]) = (0:0:0, 0:0:0);
(A2A1[10] => V[16]) = (0:0:0, 0:0:0);
(A2A1[10] => V[17]) = (0:0:0, 0:0:0);
(A2A1[10] => V[18]) = (0:0:0, 0:0:0);
(A2A1[10] => V[19]) = (0:0:0, 0:0:0);
(A2A1[10] => V[20]) = (0:0:0, 0:0:0);
(A2A1[10] => V[21]) = (0:0:0, 0:0:0);
(A2A1[10] => V[22]) = (0:0:0, 0:0:0);
(A2A1[10] => V[23]) = (0:0:0, 0:0:0);
(A2A1[10] => V[24]) = (0:0:0, 0:0:0);
(A2A1[10] => V[25]) = (0:0:0, 0:0:0);
(A2A1[10] => V[26]) = (0:0:0, 0:0:0);
(A2A1[10] => V[27]) = (0:0:0, 0:0:0);
(A2A1[10] => V[28]) = (0:0:0, 0:0:0);
(A2A1[10] => V[29]) = (0:0:0, 0:0:0);
(A2A1[10] => V[30]) = (0:0:0, 0:0:0);
(A2A1[11] => U[12]) = (0:0:0, 0:0:0);
(A2A1[11] => U[13]) = (0:0:0, 0:0:0);
(A2A1[11] => U[14]) = (0:0:0, 0:0:0);
(A2A1[11] => U[15]) = (0:0:0, 0:0:0);
(A2A1[11] => U[16]) = (0:0:0, 0:0:0);
(A2A1[11] => U[17]) = (0:0:0, 0:0:0);
(A2A1[11] => U[18]) = (0:0:0, 0:0:0);
(A2A1[11] => U[19]) = (0:0:0, 0:0:0);
(A2A1[11] => U[20]) = (0:0:0, 0:0:0);
(A2A1[11] => U[21]) = (0:0:0, 0:0:0);
(A2A1[11] => U[22]) = (0:0:0, 0:0:0);
(A2A1[11] => U[23]) = (0:0:0, 0:0:0);
(A2A1[11] => U[24]) = (0:0:0, 0:0:0);
(A2A1[11] => U[25]) = (0:0:0, 0:0:0);
(A2A1[11] => U[26]) = (0:0:0, 0:0:0);
(A2A1[11] => U[27]) = (0:0:0, 0:0:0);
(A2A1[11] => U[28]) = (0:0:0, 0:0:0);
(A2A1[11] => U[29]) = (0:0:0, 0:0:0);
(A2A1[11] => U[30]) = (0:0:0, 0:0:0);
(A2A1[11] => U[31]) = (0:0:0, 0:0:0);
(A2A1[11] => U[32]) = (0:0:0, 0:0:0);
(A2A1[11] => V[11]) = (0:0:0, 0:0:0);
(A2A1[11] => V[12]) = (0:0:0, 0:0:0);
(A2A1[11] => V[13]) = (0:0:0, 0:0:0);
(A2A1[11] => V[14]) = (0:0:0, 0:0:0);
(A2A1[11] => V[15]) = (0:0:0, 0:0:0);
(A2A1[11] => V[16]) = (0:0:0, 0:0:0);
(A2A1[11] => V[17]) = (0:0:0, 0:0:0);
(A2A1[11] => V[18]) = (0:0:0, 0:0:0);
(A2A1[11] => V[19]) = (0:0:0, 0:0:0);
(A2A1[11] => V[20]) = (0:0:0, 0:0:0);
(A2A1[11] => V[21]) = (0:0:0, 0:0:0);
(A2A1[11] => V[22]) = (0:0:0, 0:0:0);
(A2A1[11] => V[23]) = (0:0:0, 0:0:0);
(A2A1[11] => V[24]) = (0:0:0, 0:0:0);
(A2A1[11] => V[25]) = (0:0:0, 0:0:0);
(A2A1[11] => V[26]) = (0:0:0, 0:0:0);
(A2A1[11] => V[27]) = (0:0:0, 0:0:0);
(A2A1[11] => V[28]) = (0:0:0, 0:0:0);
(A2A1[11] => V[29]) = (0:0:0, 0:0:0);
(A2A1[11] => V[30]) = (0:0:0, 0:0:0);
(A2A1[11] => V[31]) = (0:0:0, 0:0:0);
(A2A1[12] => U[13]) = (0:0:0, 0:0:0);
(A2A1[12] => U[14]) = (0:0:0, 0:0:0);
(A2A1[12] => U[15]) = (0:0:0, 0:0:0);
(A2A1[12] => U[16]) = (0:0:0, 0:0:0);
(A2A1[12] => U[17]) = (0:0:0, 0:0:0);
(A2A1[12] => U[18]) = (0:0:0, 0:0:0);
(A2A1[12] => U[19]) = (0:0:0, 0:0:0);
(A2A1[12] => U[20]) = (0:0:0, 0:0:0);
(A2A1[12] => U[21]) = (0:0:0, 0:0:0);
(A2A1[12] => U[22]) = (0:0:0, 0:0:0);
(A2A1[12] => U[23]) = (0:0:0, 0:0:0);
(A2A1[12] => U[24]) = (0:0:0, 0:0:0);
(A2A1[12] => U[25]) = (0:0:0, 0:0:0);
(A2A1[12] => U[26]) = (0:0:0, 0:0:0);
(A2A1[12] => U[27]) = (0:0:0, 0:0:0);
(A2A1[12] => U[28]) = (0:0:0, 0:0:0);
(A2A1[12] => U[29]) = (0:0:0, 0:0:0);
(A2A1[12] => U[30]) = (0:0:0, 0:0:0);
(A2A1[12] => U[31]) = (0:0:0, 0:0:0);
(A2A1[12] => U[32]) = (0:0:0, 0:0:0);
(A2A1[12] => U[33]) = (0:0:0, 0:0:0);
(A2A1[12] => V[12]) = (0:0:0, 0:0:0);
(A2A1[12] => V[13]) = (0:0:0, 0:0:0);
(A2A1[12] => V[14]) = (0:0:0, 0:0:0);
(A2A1[12] => V[15]) = (0:0:0, 0:0:0);
(A2A1[12] => V[16]) = (0:0:0, 0:0:0);
(A2A1[12] => V[17]) = (0:0:0, 0:0:0);
(A2A1[12] => V[18]) = (0:0:0, 0:0:0);
(A2A1[12] => V[19]) = (0:0:0, 0:0:0);
(A2A1[12] => V[20]) = (0:0:0, 0:0:0);
(A2A1[12] => V[21]) = (0:0:0, 0:0:0);
(A2A1[12] => V[22]) = (0:0:0, 0:0:0);
(A2A1[12] => V[23]) = (0:0:0, 0:0:0);
(A2A1[12] => V[24]) = (0:0:0, 0:0:0);
(A2A1[12] => V[25]) = (0:0:0, 0:0:0);
(A2A1[12] => V[26]) = (0:0:0, 0:0:0);
(A2A1[12] => V[27]) = (0:0:0, 0:0:0);
(A2A1[12] => V[28]) = (0:0:0, 0:0:0);
(A2A1[12] => V[29]) = (0:0:0, 0:0:0);
(A2A1[12] => V[30]) = (0:0:0, 0:0:0);
(A2A1[12] => V[31]) = (0:0:0, 0:0:0);
(A2A1[12] => V[32]) = (0:0:0, 0:0:0);
(A2A1[13] => U[14]) = (0:0:0, 0:0:0);
(A2A1[13] => U[15]) = (0:0:0, 0:0:0);
(A2A1[13] => U[16]) = (0:0:0, 0:0:0);
(A2A1[13] => U[17]) = (0:0:0, 0:0:0);
(A2A1[13] => U[18]) = (0:0:0, 0:0:0);
(A2A1[13] => U[19]) = (0:0:0, 0:0:0);
(A2A1[13] => U[20]) = (0:0:0, 0:0:0);
(A2A1[13] => U[21]) = (0:0:0, 0:0:0);
(A2A1[13] => U[22]) = (0:0:0, 0:0:0);
(A2A1[13] => U[23]) = (0:0:0, 0:0:0);
(A2A1[13] => U[24]) = (0:0:0, 0:0:0);
(A2A1[13] => U[25]) = (0:0:0, 0:0:0);
(A2A1[13] => U[26]) = (0:0:0, 0:0:0);
(A2A1[13] => U[27]) = (0:0:0, 0:0:0);
(A2A1[13] => U[28]) = (0:0:0, 0:0:0);
(A2A1[13] => U[29]) = (0:0:0, 0:0:0);
(A2A1[13] => U[30]) = (0:0:0, 0:0:0);
(A2A1[13] => U[31]) = (0:0:0, 0:0:0);
(A2A1[13] => U[32]) = (0:0:0, 0:0:0);
(A2A1[13] => U[33]) = (0:0:0, 0:0:0);
(A2A1[13] => U[34]) = (0:0:0, 0:0:0);
(A2A1[13] => V[13]) = (0:0:0, 0:0:0);
(A2A1[13] => V[14]) = (0:0:0, 0:0:0);
(A2A1[13] => V[15]) = (0:0:0, 0:0:0);
(A2A1[13] => V[16]) = (0:0:0, 0:0:0);
(A2A1[13] => V[17]) = (0:0:0, 0:0:0);
(A2A1[13] => V[18]) = (0:0:0, 0:0:0);
(A2A1[13] => V[19]) = (0:0:0, 0:0:0);
(A2A1[13] => V[20]) = (0:0:0, 0:0:0);
(A2A1[13] => V[21]) = (0:0:0, 0:0:0);
(A2A1[13] => V[22]) = (0:0:0, 0:0:0);
(A2A1[13] => V[23]) = (0:0:0, 0:0:0);
(A2A1[13] => V[24]) = (0:0:0, 0:0:0);
(A2A1[13] => V[25]) = (0:0:0, 0:0:0);
(A2A1[13] => V[26]) = (0:0:0, 0:0:0);
(A2A1[13] => V[27]) = (0:0:0, 0:0:0);
(A2A1[13] => V[28]) = (0:0:0, 0:0:0);
(A2A1[13] => V[29]) = (0:0:0, 0:0:0);
(A2A1[13] => V[30]) = (0:0:0, 0:0:0);
(A2A1[13] => V[31]) = (0:0:0, 0:0:0);
(A2A1[13] => V[32]) = (0:0:0, 0:0:0);
(A2A1[13] => V[33]) = (0:0:0, 0:0:0);
(A2A1[14] => U[15]) = (0:0:0, 0:0:0);
(A2A1[14] => U[16]) = (0:0:0, 0:0:0);
(A2A1[14] => U[17]) = (0:0:0, 0:0:0);
(A2A1[14] => U[18]) = (0:0:0, 0:0:0);
(A2A1[14] => U[19]) = (0:0:0, 0:0:0);
(A2A1[14] => U[20]) = (0:0:0, 0:0:0);
(A2A1[14] => U[21]) = (0:0:0, 0:0:0);
(A2A1[14] => U[22]) = (0:0:0, 0:0:0);
(A2A1[14] => U[23]) = (0:0:0, 0:0:0);
(A2A1[14] => U[24]) = (0:0:0, 0:0:0);
(A2A1[14] => U[25]) = (0:0:0, 0:0:0);
(A2A1[14] => U[26]) = (0:0:0, 0:0:0);
(A2A1[14] => U[27]) = (0:0:0, 0:0:0);
(A2A1[14] => U[28]) = (0:0:0, 0:0:0);
(A2A1[14] => U[29]) = (0:0:0, 0:0:0);
(A2A1[14] => U[30]) = (0:0:0, 0:0:0);
(A2A1[14] => U[31]) = (0:0:0, 0:0:0);
(A2A1[14] => U[32]) = (0:0:0, 0:0:0);
(A2A1[14] => U[33]) = (0:0:0, 0:0:0);
(A2A1[14] => U[34]) = (0:0:0, 0:0:0);
(A2A1[14] => V[14]) = (0:0:0, 0:0:0);
(A2A1[14] => V[15]) = (0:0:0, 0:0:0);
(A2A1[14] => V[16]) = (0:0:0, 0:0:0);
(A2A1[14] => V[17]) = (0:0:0, 0:0:0);
(A2A1[14] => V[18]) = (0:0:0, 0:0:0);
(A2A1[14] => V[19]) = (0:0:0, 0:0:0);
(A2A1[14] => V[20]) = (0:0:0, 0:0:0);
(A2A1[14] => V[21]) = (0:0:0, 0:0:0);
(A2A1[14] => V[22]) = (0:0:0, 0:0:0);
(A2A1[14] => V[23]) = (0:0:0, 0:0:0);
(A2A1[14] => V[24]) = (0:0:0, 0:0:0);
(A2A1[14] => V[25]) = (0:0:0, 0:0:0);
(A2A1[14] => V[26]) = (0:0:0, 0:0:0);
(A2A1[14] => V[27]) = (0:0:0, 0:0:0);
(A2A1[14] => V[28]) = (0:0:0, 0:0:0);
(A2A1[14] => V[29]) = (0:0:0, 0:0:0);
(A2A1[14] => V[30]) = (0:0:0, 0:0:0);
(A2A1[14] => V[31]) = (0:0:0, 0:0:0);
(A2A1[14] => V[32]) = (0:0:0, 0:0:0);
(A2A1[14] => V[33]) = (0:0:0, 0:0:0);
(A2A1[15] => U[16]) = (0:0:0, 0:0:0);
(A2A1[15] => U[17]) = (0:0:0, 0:0:0);
(A2A1[15] => U[18]) = (0:0:0, 0:0:0);
(A2A1[15] => U[19]) = (0:0:0, 0:0:0);
(A2A1[15] => U[20]) = (0:0:0, 0:0:0);
(A2A1[15] => U[21]) = (0:0:0, 0:0:0);
(A2A1[15] => U[22]) = (0:0:0, 0:0:0);
(A2A1[15] => U[23]) = (0:0:0, 0:0:0);
(A2A1[15] => U[24]) = (0:0:0, 0:0:0);
(A2A1[15] => U[25]) = (0:0:0, 0:0:0);
(A2A1[15] => U[26]) = (0:0:0, 0:0:0);
(A2A1[15] => U[27]) = (0:0:0, 0:0:0);
(A2A1[15] => U[28]) = (0:0:0, 0:0:0);
(A2A1[15] => U[29]) = (0:0:0, 0:0:0);
(A2A1[15] => U[30]) = (0:0:0, 0:0:0);
(A2A1[15] => U[31]) = (0:0:0, 0:0:0);
(A2A1[15] => U[32]) = (0:0:0, 0:0:0);
(A2A1[15] => U[33]) = (0:0:0, 0:0:0);
(A2A1[15] => U[34]) = (0:0:0, 0:0:0);
(A2A1[15] => U[35]) = (0:0:0, 0:0:0);
(A2A1[15] => U[36]) = (0:0:0, 0:0:0);
(A2A1[15] => V[15]) = (0:0:0, 0:0:0);
(A2A1[15] => V[16]) = (0:0:0, 0:0:0);
(A2A1[15] => V[17]) = (0:0:0, 0:0:0);
(A2A1[15] => V[18]) = (0:0:0, 0:0:0);
(A2A1[15] => V[19]) = (0:0:0, 0:0:0);
(A2A1[15] => V[20]) = (0:0:0, 0:0:0);
(A2A1[15] => V[21]) = (0:0:0, 0:0:0);
(A2A1[15] => V[22]) = (0:0:0, 0:0:0);
(A2A1[15] => V[23]) = (0:0:0, 0:0:0);
(A2A1[15] => V[24]) = (0:0:0, 0:0:0);
(A2A1[15] => V[25]) = (0:0:0, 0:0:0);
(A2A1[15] => V[26]) = (0:0:0, 0:0:0);
(A2A1[15] => V[27]) = (0:0:0, 0:0:0);
(A2A1[15] => V[28]) = (0:0:0, 0:0:0);
(A2A1[15] => V[29]) = (0:0:0, 0:0:0);
(A2A1[15] => V[30]) = (0:0:0, 0:0:0);
(A2A1[15] => V[31]) = (0:0:0, 0:0:0);
(A2A1[15] => V[32]) = (0:0:0, 0:0:0);
(A2A1[15] => V[33]) = (0:0:0, 0:0:0);
(A2A1[15] => V[34]) = (0:0:0, 0:0:0);
(A2A1[15] => V[35]) = (0:0:0, 0:0:0);
(A2A1[16] => U[17]) = (0:0:0, 0:0:0);
(A2A1[16] => U[18]) = (0:0:0, 0:0:0);
(A2A1[16] => U[19]) = (0:0:0, 0:0:0);
(A2A1[16] => U[20]) = (0:0:0, 0:0:0);
(A2A1[16] => U[21]) = (0:0:0, 0:0:0);
(A2A1[16] => U[22]) = (0:0:0, 0:0:0);
(A2A1[16] => U[23]) = (0:0:0, 0:0:0);
(A2A1[16] => U[24]) = (0:0:0, 0:0:0);
(A2A1[16] => U[25]) = (0:0:0, 0:0:0);
(A2A1[16] => U[26]) = (0:0:0, 0:0:0);
(A2A1[16] => U[27]) = (0:0:0, 0:0:0);
(A2A1[16] => U[28]) = (0:0:0, 0:0:0);
(A2A1[16] => U[29]) = (0:0:0, 0:0:0);
(A2A1[16] => U[30]) = (0:0:0, 0:0:0);
(A2A1[16] => U[31]) = (0:0:0, 0:0:0);
(A2A1[16] => U[32]) = (0:0:0, 0:0:0);
(A2A1[16] => U[33]) = (0:0:0, 0:0:0);
(A2A1[16] => U[34]) = (0:0:0, 0:0:0);
(A2A1[16] => U[35]) = (0:0:0, 0:0:0);
(A2A1[16] => U[36]) = (0:0:0, 0:0:0);
(A2A1[16] => V[16]) = (0:0:0, 0:0:0);
(A2A1[16] => V[17]) = (0:0:0, 0:0:0);
(A2A1[16] => V[18]) = (0:0:0, 0:0:0);
(A2A1[16] => V[19]) = (0:0:0, 0:0:0);
(A2A1[16] => V[20]) = (0:0:0, 0:0:0);
(A2A1[16] => V[21]) = (0:0:0, 0:0:0);
(A2A1[16] => V[22]) = (0:0:0, 0:0:0);
(A2A1[16] => V[23]) = (0:0:0, 0:0:0);
(A2A1[16] => V[24]) = (0:0:0, 0:0:0);
(A2A1[16] => V[25]) = (0:0:0, 0:0:0);
(A2A1[16] => V[26]) = (0:0:0, 0:0:0);
(A2A1[16] => V[27]) = (0:0:0, 0:0:0);
(A2A1[16] => V[28]) = (0:0:0, 0:0:0);
(A2A1[16] => V[29]) = (0:0:0, 0:0:0);
(A2A1[16] => V[30]) = (0:0:0, 0:0:0);
(A2A1[16] => V[31]) = (0:0:0, 0:0:0);
(A2A1[16] => V[32]) = (0:0:0, 0:0:0);
(A2A1[16] => V[33]) = (0:0:0, 0:0:0);
(A2A1[16] => V[34]) = (0:0:0, 0:0:0);
(A2A1[16] => V[35]) = (0:0:0, 0:0:0);
(A2A1[17] => U[18]) = (0:0:0, 0:0:0);
(A2A1[17] => U[19]) = (0:0:0, 0:0:0);
(A2A1[17] => U[20]) = (0:0:0, 0:0:0);
(A2A1[17] => U[21]) = (0:0:0, 0:0:0);
(A2A1[17] => U[22]) = (0:0:0, 0:0:0);
(A2A1[17] => U[23]) = (0:0:0, 0:0:0);
(A2A1[17] => U[24]) = (0:0:0, 0:0:0);
(A2A1[17] => U[25]) = (0:0:0, 0:0:0);
(A2A1[17] => U[26]) = (0:0:0, 0:0:0);
(A2A1[17] => U[27]) = (0:0:0, 0:0:0);
(A2A1[17] => U[28]) = (0:0:0, 0:0:0);
(A2A1[17] => U[29]) = (0:0:0, 0:0:0);
(A2A1[17] => U[30]) = (0:0:0, 0:0:0);
(A2A1[17] => U[31]) = (0:0:0, 0:0:0);
(A2A1[17] => U[32]) = (0:0:0, 0:0:0);
(A2A1[17] => U[33]) = (0:0:0, 0:0:0);
(A2A1[17] => U[34]) = (0:0:0, 0:0:0);
(A2A1[17] => U[35]) = (0:0:0, 0:0:0);
(A2A1[17] => U[36]) = (0:0:0, 0:0:0);
(A2A1[17] => U[37]) = (0:0:0, 0:0:0);
(A2A1[17] => V[17]) = (0:0:0, 0:0:0);
(A2A1[17] => V[18]) = (0:0:0, 0:0:0);
(A2A1[17] => V[19]) = (0:0:0, 0:0:0);
(A2A1[17] => V[20]) = (0:0:0, 0:0:0);
(A2A1[17] => V[21]) = (0:0:0, 0:0:0);
(A2A1[17] => V[22]) = (0:0:0, 0:0:0);
(A2A1[17] => V[23]) = (0:0:0, 0:0:0);
(A2A1[17] => V[24]) = (0:0:0, 0:0:0);
(A2A1[17] => V[25]) = (0:0:0, 0:0:0);
(A2A1[17] => V[26]) = (0:0:0, 0:0:0);
(A2A1[17] => V[27]) = (0:0:0, 0:0:0);
(A2A1[17] => V[28]) = (0:0:0, 0:0:0);
(A2A1[17] => V[29]) = (0:0:0, 0:0:0);
(A2A1[17] => V[30]) = (0:0:0, 0:0:0);
(A2A1[17] => V[31]) = (0:0:0, 0:0:0);
(A2A1[17] => V[32]) = (0:0:0, 0:0:0);
(A2A1[17] => V[33]) = (0:0:0, 0:0:0);
(A2A1[17] => V[34]) = (0:0:0, 0:0:0);
(A2A1[17] => V[35]) = (0:0:0, 0:0:0);
(A2A1[17] => V[36]) = (0:0:0, 0:0:0);
(A2A1[18] => U[19]) = (0:0:0, 0:0:0);
(A2A1[18] => U[20]) = (0:0:0, 0:0:0);
(A2A1[18] => U[21]) = (0:0:0, 0:0:0);
(A2A1[18] => U[22]) = (0:0:0, 0:0:0);
(A2A1[18] => U[23]) = (0:0:0, 0:0:0);
(A2A1[18] => U[24]) = (0:0:0, 0:0:0);
(A2A1[18] => U[25]) = (0:0:0, 0:0:0);
(A2A1[18] => U[26]) = (0:0:0, 0:0:0);
(A2A1[18] => U[27]) = (0:0:0, 0:0:0);
(A2A1[18] => U[28]) = (0:0:0, 0:0:0);
(A2A1[18] => U[29]) = (0:0:0, 0:0:0);
(A2A1[18] => U[30]) = (0:0:0, 0:0:0);
(A2A1[18] => U[31]) = (0:0:0, 0:0:0);
(A2A1[18] => U[32]) = (0:0:0, 0:0:0);
(A2A1[18] => U[33]) = (0:0:0, 0:0:0);
(A2A1[18] => U[34]) = (0:0:0, 0:0:0);
(A2A1[18] => U[35]) = (0:0:0, 0:0:0);
(A2A1[18] => U[36]) = (0:0:0, 0:0:0);
(A2A1[18] => U[37]) = (0:0:0, 0:0:0);
(A2A1[18] => U[38]) = (0:0:0, 0:0:0);
(A2A1[18] => V[18]) = (0:0:0, 0:0:0);
(A2A1[18] => V[19]) = (0:0:0, 0:0:0);
(A2A1[18] => V[20]) = (0:0:0, 0:0:0);
(A2A1[18] => V[21]) = (0:0:0, 0:0:0);
(A2A1[18] => V[22]) = (0:0:0, 0:0:0);
(A2A1[18] => V[23]) = (0:0:0, 0:0:0);
(A2A1[18] => V[24]) = (0:0:0, 0:0:0);
(A2A1[18] => V[25]) = (0:0:0, 0:0:0);
(A2A1[18] => V[26]) = (0:0:0, 0:0:0);
(A2A1[18] => V[27]) = (0:0:0, 0:0:0);
(A2A1[18] => V[28]) = (0:0:0, 0:0:0);
(A2A1[18] => V[29]) = (0:0:0, 0:0:0);
(A2A1[18] => V[30]) = (0:0:0, 0:0:0);
(A2A1[18] => V[31]) = (0:0:0, 0:0:0);
(A2A1[18] => V[32]) = (0:0:0, 0:0:0);
(A2A1[18] => V[33]) = (0:0:0, 0:0:0);
(A2A1[18] => V[34]) = (0:0:0, 0:0:0);
(A2A1[18] => V[35]) = (0:0:0, 0:0:0);
(A2A1[18] => V[36]) = (0:0:0, 0:0:0);
(A2A1[18] => V[37]) = (0:0:0, 0:0:0);
(A2A1[19] => U[20]) = (0:0:0, 0:0:0);
(A2A1[19] => U[21]) = (0:0:0, 0:0:0);
(A2A1[19] => U[22]) = (0:0:0, 0:0:0);
(A2A1[19] => U[23]) = (0:0:0, 0:0:0);
(A2A1[19] => U[24]) = (0:0:0, 0:0:0);
(A2A1[19] => U[25]) = (0:0:0, 0:0:0);
(A2A1[19] => U[26]) = (0:0:0, 0:0:0);
(A2A1[19] => U[27]) = (0:0:0, 0:0:0);
(A2A1[19] => U[28]) = (0:0:0, 0:0:0);
(A2A1[19] => U[29]) = (0:0:0, 0:0:0);
(A2A1[19] => U[30]) = (0:0:0, 0:0:0);
(A2A1[19] => U[31]) = (0:0:0, 0:0:0);
(A2A1[19] => U[32]) = (0:0:0, 0:0:0);
(A2A1[19] => U[33]) = (0:0:0, 0:0:0);
(A2A1[19] => U[34]) = (0:0:0, 0:0:0);
(A2A1[19] => U[35]) = (0:0:0, 0:0:0);
(A2A1[19] => U[36]) = (0:0:0, 0:0:0);
(A2A1[19] => U[37]) = (0:0:0, 0:0:0);
(A2A1[19] => U[38]) = (0:0:0, 0:0:0);
(A2A1[19] => U[39]) = (0:0:0, 0:0:0);
(A2A1[19] => V[19]) = (0:0:0, 0:0:0);
(A2A1[19] => V[20]) = (0:0:0, 0:0:0);
(A2A1[19] => V[21]) = (0:0:0, 0:0:0);
(A2A1[19] => V[22]) = (0:0:0, 0:0:0);
(A2A1[19] => V[23]) = (0:0:0, 0:0:0);
(A2A1[19] => V[24]) = (0:0:0, 0:0:0);
(A2A1[19] => V[25]) = (0:0:0, 0:0:0);
(A2A1[19] => V[26]) = (0:0:0, 0:0:0);
(A2A1[19] => V[27]) = (0:0:0, 0:0:0);
(A2A1[19] => V[28]) = (0:0:0, 0:0:0);
(A2A1[19] => V[29]) = (0:0:0, 0:0:0);
(A2A1[19] => V[30]) = (0:0:0, 0:0:0);
(A2A1[19] => V[31]) = (0:0:0, 0:0:0);
(A2A1[19] => V[32]) = (0:0:0, 0:0:0);
(A2A1[19] => V[33]) = (0:0:0, 0:0:0);
(A2A1[19] => V[34]) = (0:0:0, 0:0:0);
(A2A1[19] => V[35]) = (0:0:0, 0:0:0);
(A2A1[19] => V[36]) = (0:0:0, 0:0:0);
(A2A1[19] => V[37]) = (0:0:0, 0:0:0);
(A2A1[19] => V[38]) = (0:0:0, 0:0:0);
(A2A1[1] => U[10]) = (0:0:0, 0:0:0);
(A2A1[1] => U[11]) = (0:0:0, 0:0:0);
(A2A1[1] => U[12]) = (0:0:0, 0:0:0);
(A2A1[1] => U[13]) = (0:0:0, 0:0:0);
(A2A1[1] => U[14]) = (0:0:0, 0:0:0);
(A2A1[1] => U[15]) = (0:0:0, 0:0:0);
(A2A1[1] => U[16]) = (0:0:0, 0:0:0);
(A2A1[1] => U[17]) = (0:0:0, 0:0:0);
(A2A1[1] => U[18]) = (0:0:0, 0:0:0);
(A2A1[1] => U[19]) = (0:0:0, 0:0:0);
(A2A1[1] => U[1]) = (0:0:0, 0:0:0);
(A2A1[1] => U[20]) = (0:0:0, 0:0:0);
(A2A1[1] => U[21]) = (0:0:0, 0:0:0);
(A2A1[1] => U[22]) = (0:0:0, 0:0:0);
(A2A1[1] => U[2]) = (0:0:0, 0:0:0);
(A2A1[1] => U[3]) = (0:0:0, 0:0:0);
(A2A1[1] => U[4]) = (0:0:0, 0:0:0);
(A2A1[1] => U[5]) = (0:0:0, 0:0:0);
(A2A1[1] => U[6]) = (0:0:0, 0:0:0);
(A2A1[1] => U[7]) = (0:0:0, 0:0:0);
(A2A1[1] => U[8]) = (0:0:0, 0:0:0);
(A2A1[1] => U[9]) = (0:0:0, 0:0:0);
(A2A1[1] => V[10]) = (0:0:0, 0:0:0);
(A2A1[1] => V[11]) = (0:0:0, 0:0:0);
(A2A1[1] => V[12]) = (0:0:0, 0:0:0);
(A2A1[1] => V[13]) = (0:0:0, 0:0:0);
(A2A1[1] => V[14]) = (0:0:0, 0:0:0);
(A2A1[1] => V[15]) = (0:0:0, 0:0:0);
(A2A1[1] => V[16]) = (0:0:0, 0:0:0);
(A2A1[1] => V[17]) = (0:0:0, 0:0:0);
(A2A1[1] => V[18]) = (0:0:0, 0:0:0);
(A2A1[1] => V[19]) = (0:0:0, 0:0:0);
(A2A1[1] => V[20]) = (0:0:0, 0:0:0);
(A2A1[1] => V[21]) = (0:0:0, 0:0:0);
(A2A1[1] => V[4]) = (0:0:0, 0:0:0);
(A2A1[1] => V[5]) = (0:0:0, 0:0:0);
(A2A1[1] => V[6]) = (0:0:0, 0:0:0);
(A2A1[1] => V[7]) = (0:0:0, 0:0:0);
(A2A1[1] => V[8]) = (0:0:0, 0:0:0);
(A2A1[1] => V[9]) = (0:0:0, 0:0:0);
(A2A1[20] => U[21]) = (0:0:0, 0:0:0);
(A2A1[20] => U[22]) = (0:0:0, 0:0:0);
(A2A1[20] => U[23]) = (0:0:0, 0:0:0);
(A2A1[20] => U[24]) = (0:0:0, 0:0:0);
(A2A1[20] => U[25]) = (0:0:0, 0:0:0);
(A2A1[20] => U[26]) = (0:0:0, 0:0:0);
(A2A1[20] => U[27]) = (0:0:0, 0:0:0);
(A2A1[20] => U[28]) = (0:0:0, 0:0:0);
(A2A1[20] => U[29]) = (0:0:0, 0:0:0);
(A2A1[20] => U[30]) = (0:0:0, 0:0:0);
(A2A1[20] => U[31]) = (0:0:0, 0:0:0);
(A2A1[20] => U[32]) = (0:0:0, 0:0:0);
(A2A1[20] => U[33]) = (0:0:0, 0:0:0);
(A2A1[20] => U[34]) = (0:0:0, 0:0:0);
(A2A1[20] => U[35]) = (0:0:0, 0:0:0);
(A2A1[20] => U[36]) = (0:0:0, 0:0:0);
(A2A1[20] => U[37]) = (0:0:0, 0:0:0);
(A2A1[20] => U[38]) = (0:0:0, 0:0:0);
(A2A1[20] => U[39]) = (0:0:0, 0:0:0);
(A2A1[20] => V[20]) = (0:0:0, 0:0:0);
(A2A1[20] => V[21]) = (0:0:0, 0:0:0);
(A2A1[20] => V[22]) = (0:0:0, 0:0:0);
(A2A1[20] => V[23]) = (0:0:0, 0:0:0);
(A2A1[20] => V[24]) = (0:0:0, 0:0:0);
(A2A1[20] => V[25]) = (0:0:0, 0:0:0);
(A2A1[20] => V[26]) = (0:0:0, 0:0:0);
(A2A1[20] => V[27]) = (0:0:0, 0:0:0);
(A2A1[20] => V[28]) = (0:0:0, 0:0:0);
(A2A1[20] => V[29]) = (0:0:0, 0:0:0);
(A2A1[20] => V[30]) = (0:0:0, 0:0:0);
(A2A1[20] => V[31]) = (0:0:0, 0:0:0);
(A2A1[20] => V[32]) = (0:0:0, 0:0:0);
(A2A1[20] => V[33]) = (0:0:0, 0:0:0);
(A2A1[20] => V[34]) = (0:0:0, 0:0:0);
(A2A1[20] => V[35]) = (0:0:0, 0:0:0);
(A2A1[20] => V[36]) = (0:0:0, 0:0:0);
(A2A1[20] => V[37]) = (0:0:0, 0:0:0);
(A2A1[20] => V[38]) = (0:0:0, 0:0:0);
(A2A1[21] => U[22]) = (0:0:0, 0:0:0);
(A2A1[21] => U[23]) = (0:0:0, 0:0:0);
(A2A1[21] => U[24]) = (0:0:0, 0:0:0);
(A2A1[21] => U[25]) = (0:0:0, 0:0:0);
(A2A1[21] => U[26]) = (0:0:0, 0:0:0);
(A2A1[21] => U[27]) = (0:0:0, 0:0:0);
(A2A1[21] => U[28]) = (0:0:0, 0:0:0);
(A2A1[21] => U[29]) = (0:0:0, 0:0:0);
(A2A1[21] => U[30]) = (0:0:0, 0:0:0);
(A2A1[21] => U[31]) = (0:0:0, 0:0:0);
(A2A1[21] => U[32]) = (0:0:0, 0:0:0);
(A2A1[21] => U[33]) = (0:0:0, 0:0:0);
(A2A1[21] => U[34]) = (0:0:0, 0:0:0);
(A2A1[21] => U[35]) = (0:0:0, 0:0:0);
(A2A1[21] => U[36]) = (0:0:0, 0:0:0);
(A2A1[21] => U[37]) = (0:0:0, 0:0:0);
(A2A1[21] => U[38]) = (0:0:0, 0:0:0);
(A2A1[21] => U[39]) = (0:0:0, 0:0:0);
(A2A1[21] => U[40]) = (0:0:0, 0:0:0);
(A2A1[21] => V[21]) = (0:0:0, 0:0:0);
(A2A1[21] => V[22]) = (0:0:0, 0:0:0);
(A2A1[21] => V[23]) = (0:0:0, 0:0:0);
(A2A1[21] => V[24]) = (0:0:0, 0:0:0);
(A2A1[21] => V[25]) = (0:0:0, 0:0:0);
(A2A1[21] => V[26]) = (0:0:0, 0:0:0);
(A2A1[21] => V[27]) = (0:0:0, 0:0:0);
(A2A1[21] => V[28]) = (0:0:0, 0:0:0);
(A2A1[21] => V[29]) = (0:0:0, 0:0:0);
(A2A1[21] => V[30]) = (0:0:0, 0:0:0);
(A2A1[21] => V[31]) = (0:0:0, 0:0:0);
(A2A1[21] => V[32]) = (0:0:0, 0:0:0);
(A2A1[21] => V[33]) = (0:0:0, 0:0:0);
(A2A1[21] => V[34]) = (0:0:0, 0:0:0);
(A2A1[21] => V[35]) = (0:0:0, 0:0:0);
(A2A1[21] => V[36]) = (0:0:0, 0:0:0);
(A2A1[21] => V[37]) = (0:0:0, 0:0:0);
(A2A1[21] => V[38]) = (0:0:0, 0:0:0);
(A2A1[21] => V[39]) = (0:0:0, 0:0:0);
(A2A1[22] => U[23]) = (0:0:0, 0:0:0);
(A2A1[22] => U[24]) = (0:0:0, 0:0:0);
(A2A1[22] => U[25]) = (0:0:0, 0:0:0);
(A2A1[22] => U[26]) = (0:0:0, 0:0:0);
(A2A1[22] => U[27]) = (0:0:0, 0:0:0);
(A2A1[22] => U[28]) = (0:0:0, 0:0:0);
(A2A1[22] => U[29]) = (0:0:0, 0:0:0);
(A2A1[22] => U[30]) = (0:0:0, 0:0:0);
(A2A1[22] => U[31]) = (0:0:0, 0:0:0);
(A2A1[22] => U[32]) = (0:0:0, 0:0:0);
(A2A1[22] => U[33]) = (0:0:0, 0:0:0);
(A2A1[22] => U[34]) = (0:0:0, 0:0:0);
(A2A1[22] => U[35]) = (0:0:0, 0:0:0);
(A2A1[22] => U[36]) = (0:0:0, 0:0:0);
(A2A1[22] => U[37]) = (0:0:0, 0:0:0);
(A2A1[22] => U[38]) = (0:0:0, 0:0:0);
(A2A1[22] => U[39]) = (0:0:0, 0:0:0);
(A2A1[22] => U[40]) = (0:0:0, 0:0:0);
(A2A1[22] => U[41]) = (0:0:0, 0:0:0);
(A2A1[22] => V[22]) = (0:0:0, 0:0:0);
(A2A1[22] => V[23]) = (0:0:0, 0:0:0);
(A2A1[22] => V[24]) = (0:0:0, 0:0:0);
(A2A1[22] => V[25]) = (0:0:0, 0:0:0);
(A2A1[22] => V[26]) = (0:0:0, 0:0:0);
(A2A1[22] => V[27]) = (0:0:0, 0:0:0);
(A2A1[22] => V[28]) = (0:0:0, 0:0:0);
(A2A1[22] => V[29]) = (0:0:0, 0:0:0);
(A2A1[22] => V[30]) = (0:0:0, 0:0:0);
(A2A1[22] => V[31]) = (0:0:0, 0:0:0);
(A2A1[22] => V[32]) = (0:0:0, 0:0:0);
(A2A1[22] => V[33]) = (0:0:0, 0:0:0);
(A2A1[22] => V[34]) = (0:0:0, 0:0:0);
(A2A1[22] => V[35]) = (0:0:0, 0:0:0);
(A2A1[22] => V[36]) = (0:0:0, 0:0:0);
(A2A1[22] => V[37]) = (0:0:0, 0:0:0);
(A2A1[22] => V[38]) = (0:0:0, 0:0:0);
(A2A1[22] => V[39]) = (0:0:0, 0:0:0);
(A2A1[22] => V[40]) = (0:0:0, 0:0:0);
(A2A1[23] => U[24]) = (0:0:0, 0:0:0);
(A2A1[23] => U[25]) = (0:0:0, 0:0:0);
(A2A1[23] => U[26]) = (0:0:0, 0:0:0);
(A2A1[23] => U[27]) = (0:0:0, 0:0:0);
(A2A1[23] => U[28]) = (0:0:0, 0:0:0);
(A2A1[23] => U[29]) = (0:0:0, 0:0:0);
(A2A1[23] => U[30]) = (0:0:0, 0:0:0);
(A2A1[23] => U[31]) = (0:0:0, 0:0:0);
(A2A1[23] => U[32]) = (0:0:0, 0:0:0);
(A2A1[23] => U[33]) = (0:0:0, 0:0:0);
(A2A1[23] => U[34]) = (0:0:0, 0:0:0);
(A2A1[23] => U[35]) = (0:0:0, 0:0:0);
(A2A1[23] => U[36]) = (0:0:0, 0:0:0);
(A2A1[23] => U[37]) = (0:0:0, 0:0:0);
(A2A1[23] => U[38]) = (0:0:0, 0:0:0);
(A2A1[23] => U[39]) = (0:0:0, 0:0:0);
(A2A1[23] => U[40]) = (0:0:0, 0:0:0);
(A2A1[23] => U[41]) = (0:0:0, 0:0:0);
(A2A1[23] => U[42]) = (0:0:0, 0:0:0);
(A2A1[23] => V[23]) = (0:0:0, 0:0:0);
(A2A1[23] => V[24]) = (0:0:0, 0:0:0);
(A2A1[23] => V[25]) = (0:0:0, 0:0:0);
(A2A1[23] => V[26]) = (0:0:0, 0:0:0);
(A2A1[23] => V[27]) = (0:0:0, 0:0:0);
(A2A1[23] => V[28]) = (0:0:0, 0:0:0);
(A2A1[23] => V[29]) = (0:0:0, 0:0:0);
(A2A1[23] => V[30]) = (0:0:0, 0:0:0);
(A2A1[23] => V[31]) = (0:0:0, 0:0:0);
(A2A1[23] => V[32]) = (0:0:0, 0:0:0);
(A2A1[23] => V[33]) = (0:0:0, 0:0:0);
(A2A1[23] => V[34]) = (0:0:0, 0:0:0);
(A2A1[23] => V[35]) = (0:0:0, 0:0:0);
(A2A1[23] => V[36]) = (0:0:0, 0:0:0);
(A2A1[23] => V[37]) = (0:0:0, 0:0:0);
(A2A1[23] => V[38]) = (0:0:0, 0:0:0);
(A2A1[23] => V[39]) = (0:0:0, 0:0:0);
(A2A1[23] => V[40]) = (0:0:0, 0:0:0);
(A2A1[23] => V[41]) = (0:0:0, 0:0:0);
(A2A1[24] => U[25]) = (0:0:0, 0:0:0);
(A2A1[24] => U[26]) = (0:0:0, 0:0:0);
(A2A1[24] => U[27]) = (0:0:0, 0:0:0);
(A2A1[24] => U[28]) = (0:0:0, 0:0:0);
(A2A1[24] => U[29]) = (0:0:0, 0:0:0);
(A2A1[24] => U[30]) = (0:0:0, 0:0:0);
(A2A1[24] => U[31]) = (0:0:0, 0:0:0);
(A2A1[24] => U[32]) = (0:0:0, 0:0:0);
(A2A1[24] => U[33]) = (0:0:0, 0:0:0);
(A2A1[24] => U[34]) = (0:0:0, 0:0:0);
(A2A1[24] => U[35]) = (0:0:0, 0:0:0);
(A2A1[24] => U[36]) = (0:0:0, 0:0:0);
(A2A1[24] => U[37]) = (0:0:0, 0:0:0);
(A2A1[24] => U[38]) = (0:0:0, 0:0:0);
(A2A1[24] => U[39]) = (0:0:0, 0:0:0);
(A2A1[24] => U[40]) = (0:0:0, 0:0:0);
(A2A1[24] => U[41]) = (0:0:0, 0:0:0);
(A2A1[24] => U[42]) = (0:0:0, 0:0:0);
(A2A1[24] => V[24]) = (0:0:0, 0:0:0);
(A2A1[24] => V[25]) = (0:0:0, 0:0:0);
(A2A1[24] => V[26]) = (0:0:0, 0:0:0);
(A2A1[24] => V[27]) = (0:0:0, 0:0:0);
(A2A1[24] => V[28]) = (0:0:0, 0:0:0);
(A2A1[24] => V[29]) = (0:0:0, 0:0:0);
(A2A1[24] => V[30]) = (0:0:0, 0:0:0);
(A2A1[24] => V[31]) = (0:0:0, 0:0:0);
(A2A1[24] => V[32]) = (0:0:0, 0:0:0);
(A2A1[24] => V[33]) = (0:0:0, 0:0:0);
(A2A1[24] => V[34]) = (0:0:0, 0:0:0);
(A2A1[24] => V[35]) = (0:0:0, 0:0:0);
(A2A1[24] => V[36]) = (0:0:0, 0:0:0);
(A2A1[24] => V[37]) = (0:0:0, 0:0:0);
(A2A1[24] => V[38]) = (0:0:0, 0:0:0);
(A2A1[24] => V[39]) = (0:0:0, 0:0:0);
(A2A1[24] => V[40]) = (0:0:0, 0:0:0);
(A2A1[24] => V[41]) = (0:0:0, 0:0:0);
(A2A1[25] => U[26]) = (0:0:0, 0:0:0);
(A2A1[25] => U[27]) = (0:0:0, 0:0:0);
(A2A1[25] => U[28]) = (0:0:0, 0:0:0);
(A2A1[25] => U[29]) = (0:0:0, 0:0:0);
(A2A1[25] => U[30]) = (0:0:0, 0:0:0);
(A2A1[25] => U[31]) = (0:0:0, 0:0:0);
(A2A1[25] => U[32]) = (0:0:0, 0:0:0);
(A2A1[25] => U[33]) = (0:0:0, 0:0:0);
(A2A1[25] => U[34]) = (0:0:0, 0:0:0);
(A2A1[25] => U[35]) = (0:0:0, 0:0:0);
(A2A1[25] => U[36]) = (0:0:0, 0:0:0);
(A2A1[25] => U[37]) = (0:0:0, 0:0:0);
(A2A1[25] => U[38]) = (0:0:0, 0:0:0);
(A2A1[25] => U[39]) = (0:0:0, 0:0:0);
(A2A1[25] => U[40]) = (0:0:0, 0:0:0);
(A2A1[25] => U[41]) = (0:0:0, 0:0:0);
(A2A1[25] => U[42]) = (0:0:0, 0:0:0);
(A2A1[25] => U[43]) = (0:0:0, 0:0:0);
(A2A1[25] => V[25]) = (0:0:0, 0:0:0);
(A2A1[25] => V[26]) = (0:0:0, 0:0:0);
(A2A1[25] => V[27]) = (0:0:0, 0:0:0);
(A2A1[25] => V[28]) = (0:0:0, 0:0:0);
(A2A1[25] => V[29]) = (0:0:0, 0:0:0);
(A2A1[25] => V[30]) = (0:0:0, 0:0:0);
(A2A1[25] => V[31]) = (0:0:0, 0:0:0);
(A2A1[25] => V[32]) = (0:0:0, 0:0:0);
(A2A1[25] => V[33]) = (0:0:0, 0:0:0);
(A2A1[25] => V[34]) = (0:0:0, 0:0:0);
(A2A1[25] => V[35]) = (0:0:0, 0:0:0);
(A2A1[25] => V[36]) = (0:0:0, 0:0:0);
(A2A1[25] => V[37]) = (0:0:0, 0:0:0);
(A2A1[25] => V[38]) = (0:0:0, 0:0:0);
(A2A1[25] => V[39]) = (0:0:0, 0:0:0);
(A2A1[25] => V[40]) = (0:0:0, 0:0:0);
(A2A1[25] => V[41]) = (0:0:0, 0:0:0);
(A2A1[25] => V[42]) = (0:0:0, 0:0:0);
(A2A1[26] => AMULT26) = (0:0:0, 0:0:0);
(A2A1[26] => U[27]) = (0:0:0, 0:0:0);
(A2A1[26] => U[28]) = (0:0:0, 0:0:0);
(A2A1[26] => U[29]) = (0:0:0, 0:0:0);
(A2A1[26] => U[30]) = (0:0:0, 0:0:0);
(A2A1[26] => U[31]) = (0:0:0, 0:0:0);
(A2A1[26] => U[32]) = (0:0:0, 0:0:0);
(A2A1[26] => U[33]) = (0:0:0, 0:0:0);
(A2A1[26] => U[34]) = (0:0:0, 0:0:0);
(A2A1[26] => U[35]) = (0:0:0, 0:0:0);
(A2A1[26] => U[36]) = (0:0:0, 0:0:0);
(A2A1[26] => U[37]) = (0:0:0, 0:0:0);
(A2A1[26] => U[38]) = (0:0:0, 0:0:0);
(A2A1[26] => U[39]) = (0:0:0, 0:0:0);
(A2A1[26] => U[40]) = (0:0:0, 0:0:0);
(A2A1[26] => U[41]) = (0:0:0, 0:0:0);
(A2A1[26] => U[42]) = (0:0:0, 0:0:0);
(A2A1[26] => U[43]) = (0:0:0, 0:0:0);
(A2A1[26] => V[26]) = (0:0:0, 0:0:0);
(A2A1[26] => V[27]) = (0:0:0, 0:0:0);
(A2A1[26] => V[28]) = (0:0:0, 0:0:0);
(A2A1[26] => V[29]) = (0:0:0, 0:0:0);
(A2A1[26] => V[30]) = (0:0:0, 0:0:0);
(A2A1[26] => V[31]) = (0:0:0, 0:0:0);
(A2A1[26] => V[32]) = (0:0:0, 0:0:0);
(A2A1[26] => V[33]) = (0:0:0, 0:0:0);
(A2A1[26] => V[34]) = (0:0:0, 0:0:0);
(A2A1[26] => V[35]) = (0:0:0, 0:0:0);
(A2A1[26] => V[36]) = (0:0:0, 0:0:0);
(A2A1[26] => V[37]) = (0:0:0, 0:0:0);
(A2A1[26] => V[38]) = (0:0:0, 0:0:0);
(A2A1[26] => V[39]) = (0:0:0, 0:0:0);
(A2A1[26] => V[40]) = (0:0:0, 0:0:0);
(A2A1[26] => V[41]) = (0:0:0, 0:0:0);
(A2A1[26] => V[42]) = (0:0:0, 0:0:0);
(A2A1[26] => V[43]) = (0:0:0, 0:0:0);
(A2A1[2] => U[10]) = (0:0:0, 0:0:0);
(A2A1[2] => U[11]) = (0:0:0, 0:0:0);
(A2A1[2] => U[12]) = (0:0:0, 0:0:0);
(A2A1[2] => U[13]) = (0:0:0, 0:0:0);
(A2A1[2] => U[14]) = (0:0:0, 0:0:0);
(A2A1[2] => U[15]) = (0:0:0, 0:0:0);
(A2A1[2] => U[16]) = (0:0:0, 0:0:0);
(A2A1[2] => U[17]) = (0:0:0, 0:0:0);
(A2A1[2] => U[18]) = (0:0:0, 0:0:0);
(A2A1[2] => U[19]) = (0:0:0, 0:0:0);
(A2A1[2] => U[20]) = (0:0:0, 0:0:0);
(A2A1[2] => U[21]) = (0:0:0, 0:0:0);
(A2A1[2] => U[22]) = (0:0:0, 0:0:0);
(A2A1[2] => U[23]) = (0:0:0, 0:0:0);
(A2A1[2] => U[2]) = (0:0:0, 0:0:0);
(A2A1[2] => U[3]) = (0:0:0, 0:0:0);
(A2A1[2] => U[4]) = (0:0:0, 0:0:0);
(A2A1[2] => U[5]) = (0:0:0, 0:0:0);
(A2A1[2] => U[6]) = (0:0:0, 0:0:0);
(A2A1[2] => U[7]) = (0:0:0, 0:0:0);
(A2A1[2] => U[8]) = (0:0:0, 0:0:0);
(A2A1[2] => U[9]) = (0:0:0, 0:0:0);
(A2A1[2] => V[10]) = (0:0:0, 0:0:0);
(A2A1[2] => V[11]) = (0:0:0, 0:0:0);
(A2A1[2] => V[12]) = (0:0:0, 0:0:0);
(A2A1[2] => V[13]) = (0:0:0, 0:0:0);
(A2A1[2] => V[14]) = (0:0:0, 0:0:0);
(A2A1[2] => V[15]) = (0:0:0, 0:0:0);
(A2A1[2] => V[16]) = (0:0:0, 0:0:0);
(A2A1[2] => V[17]) = (0:0:0, 0:0:0);
(A2A1[2] => V[18]) = (0:0:0, 0:0:0);
(A2A1[2] => V[19]) = (0:0:0, 0:0:0);
(A2A1[2] => V[20]) = (0:0:0, 0:0:0);
(A2A1[2] => V[21]) = (0:0:0, 0:0:0);
(A2A1[2] => V[22]) = (0:0:0, 0:0:0);
(A2A1[2] => V[4]) = (0:0:0, 0:0:0);
(A2A1[2] => V[5]) = (0:0:0, 0:0:0);
(A2A1[2] => V[6]) = (0:0:0, 0:0:0);
(A2A1[2] => V[7]) = (0:0:0, 0:0:0);
(A2A1[2] => V[8]) = (0:0:0, 0:0:0);
(A2A1[2] => V[9]) = (0:0:0, 0:0:0);
(A2A1[3] => U[10]) = (0:0:0, 0:0:0);
(A2A1[3] => U[11]) = (0:0:0, 0:0:0);
(A2A1[3] => U[12]) = (0:0:0, 0:0:0);
(A2A1[3] => U[13]) = (0:0:0, 0:0:0);
(A2A1[3] => U[14]) = (0:0:0, 0:0:0);
(A2A1[3] => U[15]) = (0:0:0, 0:0:0);
(A2A1[3] => U[16]) = (0:0:0, 0:0:0);
(A2A1[3] => U[17]) = (0:0:0, 0:0:0);
(A2A1[3] => U[18]) = (0:0:0, 0:0:0);
(A2A1[3] => U[19]) = (0:0:0, 0:0:0);
(A2A1[3] => U[20]) = (0:0:0, 0:0:0);
(A2A1[3] => U[21]) = (0:0:0, 0:0:0);
(A2A1[3] => U[22]) = (0:0:0, 0:0:0);
(A2A1[3] => U[23]) = (0:0:0, 0:0:0);
(A2A1[3] => U[24]) = (0:0:0, 0:0:0);
(A2A1[3] => U[3]) = (0:0:0, 0:0:0);
(A2A1[3] => U[4]) = (0:0:0, 0:0:0);
(A2A1[3] => U[5]) = (0:0:0, 0:0:0);
(A2A1[3] => U[6]) = (0:0:0, 0:0:0);
(A2A1[3] => U[7]) = (0:0:0, 0:0:0);
(A2A1[3] => U[8]) = (0:0:0, 0:0:0);
(A2A1[3] => U[9]) = (0:0:0, 0:0:0);
(A2A1[3] => V[10]) = (0:0:0, 0:0:0);
(A2A1[3] => V[11]) = (0:0:0, 0:0:0);
(A2A1[3] => V[12]) = (0:0:0, 0:0:0);
(A2A1[3] => V[13]) = (0:0:0, 0:0:0);
(A2A1[3] => V[14]) = (0:0:0, 0:0:0);
(A2A1[3] => V[15]) = (0:0:0, 0:0:0);
(A2A1[3] => V[16]) = (0:0:0, 0:0:0);
(A2A1[3] => V[17]) = (0:0:0, 0:0:0);
(A2A1[3] => V[18]) = (0:0:0, 0:0:0);
(A2A1[3] => V[19]) = (0:0:0, 0:0:0);
(A2A1[3] => V[20]) = (0:0:0, 0:0:0);
(A2A1[3] => V[21]) = (0:0:0, 0:0:0);
(A2A1[3] => V[22]) = (0:0:0, 0:0:0);
(A2A1[3] => V[23]) = (0:0:0, 0:0:0);
(A2A1[3] => V[4]) = (0:0:0, 0:0:0);
(A2A1[3] => V[5]) = (0:0:0, 0:0:0);
(A2A1[3] => V[6]) = (0:0:0, 0:0:0);
(A2A1[3] => V[7]) = (0:0:0, 0:0:0);
(A2A1[3] => V[8]) = (0:0:0, 0:0:0);
(A2A1[3] => V[9]) = (0:0:0, 0:0:0);
(A2A1[4] => U[10]) = (0:0:0, 0:0:0);
(A2A1[4] => U[11]) = (0:0:0, 0:0:0);
(A2A1[4] => U[12]) = (0:0:0, 0:0:0);
(A2A1[4] => U[13]) = (0:0:0, 0:0:0);
(A2A1[4] => U[14]) = (0:0:0, 0:0:0);
(A2A1[4] => U[15]) = (0:0:0, 0:0:0);
(A2A1[4] => U[16]) = (0:0:0, 0:0:0);
(A2A1[4] => U[17]) = (0:0:0, 0:0:0);
(A2A1[4] => U[18]) = (0:0:0, 0:0:0);
(A2A1[4] => U[19]) = (0:0:0, 0:0:0);
(A2A1[4] => U[20]) = (0:0:0, 0:0:0);
(A2A1[4] => U[21]) = (0:0:0, 0:0:0);
(A2A1[4] => U[22]) = (0:0:0, 0:0:0);
(A2A1[4] => U[23]) = (0:0:0, 0:0:0);
(A2A1[4] => U[24]) = (0:0:0, 0:0:0);
(A2A1[4] => U[25]) = (0:0:0, 0:0:0);
(A2A1[4] => U[5]) = (0:0:0, 0:0:0);
(A2A1[4] => U[6]) = (0:0:0, 0:0:0);
(A2A1[4] => U[7]) = (0:0:0, 0:0:0);
(A2A1[4] => U[8]) = (0:0:0, 0:0:0);
(A2A1[4] => U[9]) = (0:0:0, 0:0:0);
(A2A1[4] => V[10]) = (0:0:0, 0:0:0);
(A2A1[4] => V[11]) = (0:0:0, 0:0:0);
(A2A1[4] => V[12]) = (0:0:0, 0:0:0);
(A2A1[4] => V[13]) = (0:0:0, 0:0:0);
(A2A1[4] => V[14]) = (0:0:0, 0:0:0);
(A2A1[4] => V[15]) = (0:0:0, 0:0:0);
(A2A1[4] => V[16]) = (0:0:0, 0:0:0);
(A2A1[4] => V[17]) = (0:0:0, 0:0:0);
(A2A1[4] => V[18]) = (0:0:0, 0:0:0);
(A2A1[4] => V[19]) = (0:0:0, 0:0:0);
(A2A1[4] => V[20]) = (0:0:0, 0:0:0);
(A2A1[4] => V[21]) = (0:0:0, 0:0:0);
(A2A1[4] => V[22]) = (0:0:0, 0:0:0);
(A2A1[4] => V[23]) = (0:0:0, 0:0:0);
(A2A1[4] => V[24]) = (0:0:0, 0:0:0);
(A2A1[4] => V[4]) = (0:0:0, 0:0:0);
(A2A1[4] => V[5]) = (0:0:0, 0:0:0);
(A2A1[4] => V[6]) = (0:0:0, 0:0:0);
(A2A1[4] => V[7]) = (0:0:0, 0:0:0);
(A2A1[4] => V[8]) = (0:0:0, 0:0:0);
(A2A1[4] => V[9]) = (0:0:0, 0:0:0);
(A2A1[5] => U[10]) = (0:0:0, 0:0:0);
(A2A1[5] => U[11]) = (0:0:0, 0:0:0);
(A2A1[5] => U[12]) = (0:0:0, 0:0:0);
(A2A1[5] => U[13]) = (0:0:0, 0:0:0);
(A2A1[5] => U[14]) = (0:0:0, 0:0:0);
(A2A1[5] => U[15]) = (0:0:0, 0:0:0);
(A2A1[5] => U[16]) = (0:0:0, 0:0:0);
(A2A1[5] => U[17]) = (0:0:0, 0:0:0);
(A2A1[5] => U[18]) = (0:0:0, 0:0:0);
(A2A1[5] => U[19]) = (0:0:0, 0:0:0);
(A2A1[5] => U[20]) = (0:0:0, 0:0:0);
(A2A1[5] => U[21]) = (0:0:0, 0:0:0);
(A2A1[5] => U[22]) = (0:0:0, 0:0:0);
(A2A1[5] => U[23]) = (0:0:0, 0:0:0);
(A2A1[5] => U[24]) = (0:0:0, 0:0:0);
(A2A1[5] => U[25]) = (0:0:0, 0:0:0);
(A2A1[5] => U[26]) = (0:0:0, 0:0:0);
(A2A1[5] => U[6]) = (0:0:0, 0:0:0);
(A2A1[5] => U[7]) = (0:0:0, 0:0:0);
(A2A1[5] => U[8]) = (0:0:0, 0:0:0);
(A2A1[5] => U[9]) = (0:0:0, 0:0:0);
(A2A1[5] => V[10]) = (0:0:0, 0:0:0);
(A2A1[5] => V[11]) = (0:0:0, 0:0:0);
(A2A1[5] => V[12]) = (0:0:0, 0:0:0);
(A2A1[5] => V[13]) = (0:0:0, 0:0:0);
(A2A1[5] => V[14]) = (0:0:0, 0:0:0);
(A2A1[5] => V[15]) = (0:0:0, 0:0:0);
(A2A1[5] => V[16]) = (0:0:0, 0:0:0);
(A2A1[5] => V[17]) = (0:0:0, 0:0:0);
(A2A1[5] => V[18]) = (0:0:0, 0:0:0);
(A2A1[5] => V[19]) = (0:0:0, 0:0:0);
(A2A1[5] => V[20]) = (0:0:0, 0:0:0);
(A2A1[5] => V[21]) = (0:0:0, 0:0:0);
(A2A1[5] => V[22]) = (0:0:0, 0:0:0);
(A2A1[5] => V[23]) = (0:0:0, 0:0:0);
(A2A1[5] => V[24]) = (0:0:0, 0:0:0);
(A2A1[5] => V[25]) = (0:0:0, 0:0:0);
(A2A1[5] => V[5]) = (0:0:0, 0:0:0);
(A2A1[5] => V[6]) = (0:0:0, 0:0:0);
(A2A1[5] => V[7]) = (0:0:0, 0:0:0);
(A2A1[5] => V[8]) = (0:0:0, 0:0:0);
(A2A1[5] => V[9]) = (0:0:0, 0:0:0);
(A2A1[6] => U[10]) = (0:0:0, 0:0:0);
(A2A1[6] => U[11]) = (0:0:0, 0:0:0);
(A2A1[6] => U[12]) = (0:0:0, 0:0:0);
(A2A1[6] => U[13]) = (0:0:0, 0:0:0);
(A2A1[6] => U[14]) = (0:0:0, 0:0:0);
(A2A1[6] => U[15]) = (0:0:0, 0:0:0);
(A2A1[6] => U[16]) = (0:0:0, 0:0:0);
(A2A1[6] => U[17]) = (0:0:0, 0:0:0);
(A2A1[6] => U[18]) = (0:0:0, 0:0:0);
(A2A1[6] => U[19]) = (0:0:0, 0:0:0);
(A2A1[6] => U[20]) = (0:0:0, 0:0:0);
(A2A1[6] => U[21]) = (0:0:0, 0:0:0);
(A2A1[6] => U[22]) = (0:0:0, 0:0:0);
(A2A1[6] => U[23]) = (0:0:0, 0:0:0);
(A2A1[6] => U[24]) = (0:0:0, 0:0:0);
(A2A1[6] => U[25]) = (0:0:0, 0:0:0);
(A2A1[6] => U[26]) = (0:0:0, 0:0:0);
(A2A1[6] => U[27]) = (0:0:0, 0:0:0);
(A2A1[6] => U[7]) = (0:0:0, 0:0:0);
(A2A1[6] => U[8]) = (0:0:0, 0:0:0);
(A2A1[6] => U[9]) = (0:0:0, 0:0:0);
(A2A1[6] => V[10]) = (0:0:0, 0:0:0);
(A2A1[6] => V[11]) = (0:0:0, 0:0:0);
(A2A1[6] => V[12]) = (0:0:0, 0:0:0);
(A2A1[6] => V[13]) = (0:0:0, 0:0:0);
(A2A1[6] => V[14]) = (0:0:0, 0:0:0);
(A2A1[6] => V[15]) = (0:0:0, 0:0:0);
(A2A1[6] => V[16]) = (0:0:0, 0:0:0);
(A2A1[6] => V[17]) = (0:0:0, 0:0:0);
(A2A1[6] => V[18]) = (0:0:0, 0:0:0);
(A2A1[6] => V[19]) = (0:0:0, 0:0:0);
(A2A1[6] => V[20]) = (0:0:0, 0:0:0);
(A2A1[6] => V[21]) = (0:0:0, 0:0:0);
(A2A1[6] => V[22]) = (0:0:0, 0:0:0);
(A2A1[6] => V[23]) = (0:0:0, 0:0:0);
(A2A1[6] => V[24]) = (0:0:0, 0:0:0);
(A2A1[6] => V[25]) = (0:0:0, 0:0:0);
(A2A1[6] => V[26]) = (0:0:0, 0:0:0);
(A2A1[6] => V[6]) = (0:0:0, 0:0:0);
(A2A1[6] => V[7]) = (0:0:0, 0:0:0);
(A2A1[6] => V[8]) = (0:0:0, 0:0:0);
(A2A1[6] => V[9]) = (0:0:0, 0:0:0);
(A2A1[7] => U[10]) = (0:0:0, 0:0:0);
(A2A1[7] => U[11]) = (0:0:0, 0:0:0);
(A2A1[7] => U[12]) = (0:0:0, 0:0:0);
(A2A1[7] => U[13]) = (0:0:0, 0:0:0);
(A2A1[7] => U[14]) = (0:0:0, 0:0:0);
(A2A1[7] => U[15]) = (0:0:0, 0:0:0);
(A2A1[7] => U[16]) = (0:0:0, 0:0:0);
(A2A1[7] => U[17]) = (0:0:0, 0:0:0);
(A2A1[7] => U[18]) = (0:0:0, 0:0:0);
(A2A1[7] => U[19]) = (0:0:0, 0:0:0);
(A2A1[7] => U[20]) = (0:0:0, 0:0:0);
(A2A1[7] => U[21]) = (0:0:0, 0:0:0);
(A2A1[7] => U[22]) = (0:0:0, 0:0:0);
(A2A1[7] => U[23]) = (0:0:0, 0:0:0);
(A2A1[7] => U[24]) = (0:0:0, 0:0:0);
(A2A1[7] => U[25]) = (0:0:0, 0:0:0);
(A2A1[7] => U[26]) = (0:0:0, 0:0:0);
(A2A1[7] => U[27]) = (0:0:0, 0:0:0);
(A2A1[7] => U[28]) = (0:0:0, 0:0:0);
(A2A1[7] => U[8]) = (0:0:0, 0:0:0);
(A2A1[7] => U[9]) = (0:0:0, 0:0:0);
(A2A1[7] => V[10]) = (0:0:0, 0:0:0);
(A2A1[7] => V[11]) = (0:0:0, 0:0:0);
(A2A1[7] => V[12]) = (0:0:0, 0:0:0);
(A2A1[7] => V[13]) = (0:0:0, 0:0:0);
(A2A1[7] => V[14]) = (0:0:0, 0:0:0);
(A2A1[7] => V[15]) = (0:0:0, 0:0:0);
(A2A1[7] => V[16]) = (0:0:0, 0:0:0);
(A2A1[7] => V[17]) = (0:0:0, 0:0:0);
(A2A1[7] => V[18]) = (0:0:0, 0:0:0);
(A2A1[7] => V[19]) = (0:0:0, 0:0:0);
(A2A1[7] => V[20]) = (0:0:0, 0:0:0);
(A2A1[7] => V[21]) = (0:0:0, 0:0:0);
(A2A1[7] => V[22]) = (0:0:0, 0:0:0);
(A2A1[7] => V[23]) = (0:0:0, 0:0:0);
(A2A1[7] => V[24]) = (0:0:0, 0:0:0);
(A2A1[7] => V[25]) = (0:0:0, 0:0:0);
(A2A1[7] => V[26]) = (0:0:0, 0:0:0);
(A2A1[7] => V[27]) = (0:0:0, 0:0:0);
(A2A1[7] => V[7]) = (0:0:0, 0:0:0);
(A2A1[7] => V[8]) = (0:0:0, 0:0:0);
(A2A1[7] => V[9]) = (0:0:0, 0:0:0);
(A2A1[8] => U[10]) = (0:0:0, 0:0:0);
(A2A1[8] => U[11]) = (0:0:0, 0:0:0);
(A2A1[8] => U[12]) = (0:0:0, 0:0:0);
(A2A1[8] => U[13]) = (0:0:0, 0:0:0);
(A2A1[8] => U[14]) = (0:0:0, 0:0:0);
(A2A1[8] => U[15]) = (0:0:0, 0:0:0);
(A2A1[8] => U[16]) = (0:0:0, 0:0:0);
(A2A1[8] => U[17]) = (0:0:0, 0:0:0);
(A2A1[8] => U[18]) = (0:0:0, 0:0:0);
(A2A1[8] => U[19]) = (0:0:0, 0:0:0);
(A2A1[8] => U[20]) = (0:0:0, 0:0:0);
(A2A1[8] => U[21]) = (0:0:0, 0:0:0);
(A2A1[8] => U[22]) = (0:0:0, 0:0:0);
(A2A1[8] => U[23]) = (0:0:0, 0:0:0);
(A2A1[8] => U[24]) = (0:0:0, 0:0:0);
(A2A1[8] => U[25]) = (0:0:0, 0:0:0);
(A2A1[8] => U[26]) = (0:0:0, 0:0:0);
(A2A1[8] => U[27]) = (0:0:0, 0:0:0);
(A2A1[8] => U[28]) = (0:0:0, 0:0:0);
(A2A1[8] => U[29]) = (0:0:0, 0:0:0);
(A2A1[8] => U[9]) = (0:0:0, 0:0:0);
(A2A1[8] => V[10]) = (0:0:0, 0:0:0);
(A2A1[8] => V[11]) = (0:0:0, 0:0:0);
(A2A1[8] => V[12]) = (0:0:0, 0:0:0);
(A2A1[8] => V[13]) = (0:0:0, 0:0:0);
(A2A1[8] => V[14]) = (0:0:0, 0:0:0);
(A2A1[8] => V[15]) = (0:0:0, 0:0:0);
(A2A1[8] => V[16]) = (0:0:0, 0:0:0);
(A2A1[8] => V[17]) = (0:0:0, 0:0:0);
(A2A1[8] => V[18]) = (0:0:0, 0:0:0);
(A2A1[8] => V[19]) = (0:0:0, 0:0:0);
(A2A1[8] => V[20]) = (0:0:0, 0:0:0);
(A2A1[8] => V[21]) = (0:0:0, 0:0:0);
(A2A1[8] => V[22]) = (0:0:0, 0:0:0);
(A2A1[8] => V[23]) = (0:0:0, 0:0:0);
(A2A1[8] => V[24]) = (0:0:0, 0:0:0);
(A2A1[8] => V[25]) = (0:0:0, 0:0:0);
(A2A1[8] => V[26]) = (0:0:0, 0:0:0);
(A2A1[8] => V[27]) = (0:0:0, 0:0:0);
(A2A1[8] => V[28]) = (0:0:0, 0:0:0);
(A2A1[8] => V[8]) = (0:0:0, 0:0:0);
(A2A1[8] => V[9]) = (0:0:0, 0:0:0);
(A2A1[9] => U[10]) = (0:0:0, 0:0:0);
(A2A1[9] => U[11]) = (0:0:0, 0:0:0);
(A2A1[9] => U[12]) = (0:0:0, 0:0:0);
(A2A1[9] => U[13]) = (0:0:0, 0:0:0);
(A2A1[9] => U[14]) = (0:0:0, 0:0:0);
(A2A1[9] => U[15]) = (0:0:0, 0:0:0);
(A2A1[9] => U[16]) = (0:0:0, 0:0:0);
(A2A1[9] => U[17]) = (0:0:0, 0:0:0);
(A2A1[9] => U[18]) = (0:0:0, 0:0:0);
(A2A1[9] => U[19]) = (0:0:0, 0:0:0);
(A2A1[9] => U[20]) = (0:0:0, 0:0:0);
(A2A1[9] => U[21]) = (0:0:0, 0:0:0);
(A2A1[9] => U[22]) = (0:0:0, 0:0:0);
(A2A1[9] => U[23]) = (0:0:0, 0:0:0);
(A2A1[9] => U[24]) = (0:0:0, 0:0:0);
(A2A1[9] => U[25]) = (0:0:0, 0:0:0);
(A2A1[9] => U[26]) = (0:0:0, 0:0:0);
(A2A1[9] => U[27]) = (0:0:0, 0:0:0);
(A2A1[9] => U[28]) = (0:0:0, 0:0:0);
(A2A1[9] => U[29]) = (0:0:0, 0:0:0);
(A2A1[9] => U[30]) = (0:0:0, 0:0:0);
(A2A1[9] => V[10]) = (0:0:0, 0:0:0);
(A2A1[9] => V[11]) = (0:0:0, 0:0:0);
(A2A1[9] => V[12]) = (0:0:0, 0:0:0);
(A2A1[9] => V[13]) = (0:0:0, 0:0:0);
(A2A1[9] => V[14]) = (0:0:0, 0:0:0);
(A2A1[9] => V[15]) = (0:0:0, 0:0:0);
(A2A1[9] => V[16]) = (0:0:0, 0:0:0);
(A2A1[9] => V[17]) = (0:0:0, 0:0:0);
(A2A1[9] => V[18]) = (0:0:0, 0:0:0);
(A2A1[9] => V[19]) = (0:0:0, 0:0:0);
(A2A1[9] => V[20]) = (0:0:0, 0:0:0);
(A2A1[9] => V[21]) = (0:0:0, 0:0:0);
(A2A1[9] => V[22]) = (0:0:0, 0:0:0);
(A2A1[9] => V[23]) = (0:0:0, 0:0:0);
(A2A1[9] => V[24]) = (0:0:0, 0:0:0);
(A2A1[9] => V[25]) = (0:0:0, 0:0:0);
(A2A1[9] => V[26]) = (0:0:0, 0:0:0);
(A2A1[9] => V[27]) = (0:0:0, 0:0:0);
(A2A1[9] => V[28]) = (0:0:0, 0:0:0);
(A2A1[9] => V[29]) = (0:0:0, 0:0:0);
(A2A1[9] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[1]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[2]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[3]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[4]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[0]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[43]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[43]) = (0:0:0, 0:0:0);
(AD_DATA[17] => BMULT17) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[43]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[0]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[1]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[2]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[3]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[4]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[0]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[26] => AMULT26) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[43]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[2]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[3]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[4]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[2]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[3]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[4]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[9]) = (0:0:0, 0:0:0);
(B2B1[0] => U[10]) = (0:0:0, 0:0:0);
(B2B1[0] => U[11]) = (0:0:0, 0:0:0);
(B2B1[0] => U[12]) = (0:0:0, 0:0:0);
(B2B1[0] => U[13]) = (0:0:0, 0:0:0);
(B2B1[0] => U[14]) = (0:0:0, 0:0:0);
(B2B1[0] => U[15]) = (0:0:0, 0:0:0);
(B2B1[0] => U[16]) = (0:0:0, 0:0:0);
(B2B1[0] => U[17]) = (0:0:0, 0:0:0);
(B2B1[0] => U[18]) = (0:0:0, 0:0:0);
(B2B1[0] => U[19]) = (0:0:0, 0:0:0);
(B2B1[0] => U[1]) = (0:0:0, 0:0:0);
(B2B1[0] => U[20]) = (0:0:0, 0:0:0);
(B2B1[0] => U[21]) = (0:0:0, 0:0:0);
(B2B1[0] => U[22]) = (0:0:0, 0:0:0);
(B2B1[0] => U[23]) = (0:0:0, 0:0:0);
(B2B1[0] => U[24]) = (0:0:0, 0:0:0);
(B2B1[0] => U[25]) = (0:0:0, 0:0:0);
(B2B1[0] => U[26]) = (0:0:0, 0:0:0);
(B2B1[0] => U[27]) = (0:0:0, 0:0:0);
(B2B1[0] => U[28]) = (0:0:0, 0:0:0);
(B2B1[0] => U[29]) = (0:0:0, 0:0:0);
(B2B1[0] => U[2]) = (0:0:0, 0:0:0);
(B2B1[0] => U[30]) = (0:0:0, 0:0:0);
(B2B1[0] => U[31]) = (0:0:0, 0:0:0);
(B2B1[0] => U[3]) = (0:0:0, 0:0:0);
(B2B1[0] => U[4]) = (0:0:0, 0:0:0);
(B2B1[0] => U[5]) = (0:0:0, 0:0:0);
(B2B1[0] => U[6]) = (0:0:0, 0:0:0);
(B2B1[0] => U[7]) = (0:0:0, 0:0:0);
(B2B1[0] => U[8]) = (0:0:0, 0:0:0);
(B2B1[0] => U[9]) = (0:0:0, 0:0:0);
(B2B1[0] => V[0]) = (0:0:0, 0:0:0);
(B2B1[0] => V[10]) = (0:0:0, 0:0:0);
(B2B1[0] => V[11]) = (0:0:0, 0:0:0);
(B2B1[0] => V[12]) = (0:0:0, 0:0:0);
(B2B1[0] => V[13]) = (0:0:0, 0:0:0);
(B2B1[0] => V[14]) = (0:0:0, 0:0:0);
(B2B1[0] => V[15]) = (0:0:0, 0:0:0);
(B2B1[0] => V[16]) = (0:0:0, 0:0:0);
(B2B1[0] => V[17]) = (0:0:0, 0:0:0);
(B2B1[0] => V[18]) = (0:0:0, 0:0:0);
(B2B1[0] => V[19]) = (0:0:0, 0:0:0);
(B2B1[0] => V[20]) = (0:0:0, 0:0:0);
(B2B1[0] => V[21]) = (0:0:0, 0:0:0);
(B2B1[0] => V[22]) = (0:0:0, 0:0:0);
(B2B1[0] => V[23]) = (0:0:0, 0:0:0);
(B2B1[0] => V[24]) = (0:0:0, 0:0:0);
(B2B1[0] => V[25]) = (0:0:0, 0:0:0);
(B2B1[0] => V[26]) = (0:0:0, 0:0:0);
(B2B1[0] => V[27]) = (0:0:0, 0:0:0);
(B2B1[0] => V[28]) = (0:0:0, 0:0:0);
(B2B1[0] => V[29]) = (0:0:0, 0:0:0);
(B2B1[0] => V[30]) = (0:0:0, 0:0:0);
(B2B1[0] => V[4]) = (0:0:0, 0:0:0);
(B2B1[0] => V[5]) = (0:0:0, 0:0:0);
(B2B1[0] => V[6]) = (0:0:0, 0:0:0);
(B2B1[0] => V[7]) = (0:0:0, 0:0:0);
(B2B1[0] => V[8]) = (0:0:0, 0:0:0);
(B2B1[0] => V[9]) = (0:0:0, 0:0:0);
(B2B1[10] => U[11]) = (0:0:0, 0:0:0);
(B2B1[10] => U[12]) = (0:0:0, 0:0:0);
(B2B1[10] => U[13]) = (0:0:0, 0:0:0);
(B2B1[10] => U[14]) = (0:0:0, 0:0:0);
(B2B1[10] => U[15]) = (0:0:0, 0:0:0);
(B2B1[10] => U[16]) = (0:0:0, 0:0:0);
(B2B1[10] => U[17]) = (0:0:0, 0:0:0);
(B2B1[10] => U[18]) = (0:0:0, 0:0:0);
(B2B1[10] => U[19]) = (0:0:0, 0:0:0);
(B2B1[10] => U[20]) = (0:0:0, 0:0:0);
(B2B1[10] => U[21]) = (0:0:0, 0:0:0);
(B2B1[10] => U[22]) = (0:0:0, 0:0:0);
(B2B1[10] => U[23]) = (0:0:0, 0:0:0);
(B2B1[10] => U[24]) = (0:0:0, 0:0:0);
(B2B1[10] => U[25]) = (0:0:0, 0:0:0);
(B2B1[10] => U[26]) = (0:0:0, 0:0:0);
(B2B1[10] => U[27]) = (0:0:0, 0:0:0);
(B2B1[10] => U[28]) = (0:0:0, 0:0:0);
(B2B1[10] => U[29]) = (0:0:0, 0:0:0);
(B2B1[10] => U[30]) = (0:0:0, 0:0:0);
(B2B1[10] => U[31]) = (0:0:0, 0:0:0);
(B2B1[10] => U[32]) = (0:0:0, 0:0:0);
(B2B1[10] => U[33]) = (0:0:0, 0:0:0);
(B2B1[10] => U[34]) = (0:0:0, 0:0:0);
(B2B1[10] => U[35]) = (0:0:0, 0:0:0);
(B2B1[10] => U[36]) = (0:0:0, 0:0:0);
(B2B1[10] => U[37]) = (0:0:0, 0:0:0);
(B2B1[10] => U[38]) = (0:0:0, 0:0:0);
(B2B1[10] => U[39]) = (0:0:0, 0:0:0);
(B2B1[10] => U[40]) = (0:0:0, 0:0:0);
(B2B1[10] => V[10]) = (0:0:0, 0:0:0);
(B2B1[10] => V[11]) = (0:0:0, 0:0:0);
(B2B1[10] => V[12]) = (0:0:0, 0:0:0);
(B2B1[10] => V[13]) = (0:0:0, 0:0:0);
(B2B1[10] => V[14]) = (0:0:0, 0:0:0);
(B2B1[10] => V[15]) = (0:0:0, 0:0:0);
(B2B1[10] => V[16]) = (0:0:0, 0:0:0);
(B2B1[10] => V[17]) = (0:0:0, 0:0:0);
(B2B1[10] => V[18]) = (0:0:0, 0:0:0);
(B2B1[10] => V[19]) = (0:0:0, 0:0:0);
(B2B1[10] => V[20]) = (0:0:0, 0:0:0);
(B2B1[10] => V[21]) = (0:0:0, 0:0:0);
(B2B1[10] => V[22]) = (0:0:0, 0:0:0);
(B2B1[10] => V[23]) = (0:0:0, 0:0:0);
(B2B1[10] => V[24]) = (0:0:0, 0:0:0);
(B2B1[10] => V[25]) = (0:0:0, 0:0:0);
(B2B1[10] => V[26]) = (0:0:0, 0:0:0);
(B2B1[10] => V[27]) = (0:0:0, 0:0:0);
(B2B1[10] => V[28]) = (0:0:0, 0:0:0);
(B2B1[10] => V[29]) = (0:0:0, 0:0:0);
(B2B1[10] => V[30]) = (0:0:0, 0:0:0);
(B2B1[10] => V[31]) = (0:0:0, 0:0:0);
(B2B1[10] => V[32]) = (0:0:0, 0:0:0);
(B2B1[10] => V[33]) = (0:0:0, 0:0:0);
(B2B1[10] => V[34]) = (0:0:0, 0:0:0);
(B2B1[10] => V[35]) = (0:0:0, 0:0:0);
(B2B1[10] => V[36]) = (0:0:0, 0:0:0);
(B2B1[10] => V[37]) = (0:0:0, 0:0:0);
(B2B1[10] => V[38]) = (0:0:0, 0:0:0);
(B2B1[10] => V[39]) = (0:0:0, 0:0:0);
(B2B1[11] => U[11]) = (0:0:0, 0:0:0);
(B2B1[11] => U[12]) = (0:0:0, 0:0:0);
(B2B1[11] => U[13]) = (0:0:0, 0:0:0);
(B2B1[11] => U[14]) = (0:0:0, 0:0:0);
(B2B1[11] => U[15]) = (0:0:0, 0:0:0);
(B2B1[11] => U[16]) = (0:0:0, 0:0:0);
(B2B1[11] => U[17]) = (0:0:0, 0:0:0);
(B2B1[11] => U[18]) = (0:0:0, 0:0:0);
(B2B1[11] => U[19]) = (0:0:0, 0:0:0);
(B2B1[11] => U[20]) = (0:0:0, 0:0:0);
(B2B1[11] => U[21]) = (0:0:0, 0:0:0);
(B2B1[11] => U[22]) = (0:0:0, 0:0:0);
(B2B1[11] => U[23]) = (0:0:0, 0:0:0);
(B2B1[11] => U[24]) = (0:0:0, 0:0:0);
(B2B1[11] => U[25]) = (0:0:0, 0:0:0);
(B2B1[11] => U[26]) = (0:0:0, 0:0:0);
(B2B1[11] => U[27]) = (0:0:0, 0:0:0);
(B2B1[11] => U[28]) = (0:0:0, 0:0:0);
(B2B1[11] => U[29]) = (0:0:0, 0:0:0);
(B2B1[11] => U[30]) = (0:0:0, 0:0:0);
(B2B1[11] => U[31]) = (0:0:0, 0:0:0);
(B2B1[11] => U[32]) = (0:0:0, 0:0:0);
(B2B1[11] => U[33]) = (0:0:0, 0:0:0);
(B2B1[11] => U[34]) = (0:0:0, 0:0:0);
(B2B1[11] => U[35]) = (0:0:0, 0:0:0);
(B2B1[11] => U[36]) = (0:0:0, 0:0:0);
(B2B1[11] => U[37]) = (0:0:0, 0:0:0);
(B2B1[11] => U[38]) = (0:0:0, 0:0:0);
(B2B1[11] => U[39]) = (0:0:0, 0:0:0);
(B2B1[11] => U[40]) = (0:0:0, 0:0:0);
(B2B1[11] => U[41]) = (0:0:0, 0:0:0);
(B2B1[11] => V[10]) = (0:0:0, 0:0:0);
(B2B1[11] => V[11]) = (0:0:0, 0:0:0);
(B2B1[11] => V[12]) = (0:0:0, 0:0:0);
(B2B1[11] => V[13]) = (0:0:0, 0:0:0);
(B2B1[11] => V[14]) = (0:0:0, 0:0:0);
(B2B1[11] => V[15]) = (0:0:0, 0:0:0);
(B2B1[11] => V[16]) = (0:0:0, 0:0:0);
(B2B1[11] => V[17]) = (0:0:0, 0:0:0);
(B2B1[11] => V[18]) = (0:0:0, 0:0:0);
(B2B1[11] => V[19]) = (0:0:0, 0:0:0);
(B2B1[11] => V[20]) = (0:0:0, 0:0:0);
(B2B1[11] => V[21]) = (0:0:0, 0:0:0);
(B2B1[11] => V[22]) = (0:0:0, 0:0:0);
(B2B1[11] => V[23]) = (0:0:0, 0:0:0);
(B2B1[11] => V[24]) = (0:0:0, 0:0:0);
(B2B1[11] => V[25]) = (0:0:0, 0:0:0);
(B2B1[11] => V[26]) = (0:0:0, 0:0:0);
(B2B1[11] => V[27]) = (0:0:0, 0:0:0);
(B2B1[11] => V[28]) = (0:0:0, 0:0:0);
(B2B1[11] => V[29]) = (0:0:0, 0:0:0);
(B2B1[11] => V[30]) = (0:0:0, 0:0:0);
(B2B1[11] => V[31]) = (0:0:0, 0:0:0);
(B2B1[11] => V[32]) = (0:0:0, 0:0:0);
(B2B1[11] => V[33]) = (0:0:0, 0:0:0);
(B2B1[11] => V[34]) = (0:0:0, 0:0:0);
(B2B1[11] => V[35]) = (0:0:0, 0:0:0);
(B2B1[11] => V[36]) = (0:0:0, 0:0:0);
(B2B1[11] => V[37]) = (0:0:0, 0:0:0);
(B2B1[11] => V[38]) = (0:0:0, 0:0:0);
(B2B1[11] => V[39]) = (0:0:0, 0:0:0);
(B2B1[11] => V[40]) = (0:0:0, 0:0:0);
(B2B1[12] => U[13]) = (0:0:0, 0:0:0);
(B2B1[12] => U[14]) = (0:0:0, 0:0:0);
(B2B1[12] => U[15]) = (0:0:0, 0:0:0);
(B2B1[12] => U[16]) = (0:0:0, 0:0:0);
(B2B1[12] => U[17]) = (0:0:0, 0:0:0);
(B2B1[12] => U[18]) = (0:0:0, 0:0:0);
(B2B1[12] => U[19]) = (0:0:0, 0:0:0);
(B2B1[12] => U[20]) = (0:0:0, 0:0:0);
(B2B1[12] => U[21]) = (0:0:0, 0:0:0);
(B2B1[12] => U[22]) = (0:0:0, 0:0:0);
(B2B1[12] => U[23]) = (0:0:0, 0:0:0);
(B2B1[12] => U[24]) = (0:0:0, 0:0:0);
(B2B1[12] => U[25]) = (0:0:0, 0:0:0);
(B2B1[12] => U[26]) = (0:0:0, 0:0:0);
(B2B1[12] => U[27]) = (0:0:0, 0:0:0);
(B2B1[12] => U[28]) = (0:0:0, 0:0:0);
(B2B1[12] => U[29]) = (0:0:0, 0:0:0);
(B2B1[12] => U[30]) = (0:0:0, 0:0:0);
(B2B1[12] => U[31]) = (0:0:0, 0:0:0);
(B2B1[12] => U[32]) = (0:0:0, 0:0:0);
(B2B1[12] => U[33]) = (0:0:0, 0:0:0);
(B2B1[12] => U[34]) = (0:0:0, 0:0:0);
(B2B1[12] => U[35]) = (0:0:0, 0:0:0);
(B2B1[12] => U[36]) = (0:0:0, 0:0:0);
(B2B1[12] => U[37]) = (0:0:0, 0:0:0);
(B2B1[12] => U[38]) = (0:0:0, 0:0:0);
(B2B1[12] => U[39]) = (0:0:0, 0:0:0);
(B2B1[12] => U[40]) = (0:0:0, 0:0:0);
(B2B1[12] => U[41]) = (0:0:0, 0:0:0);
(B2B1[12] => V[12]) = (0:0:0, 0:0:0);
(B2B1[12] => V[13]) = (0:0:0, 0:0:0);
(B2B1[12] => V[14]) = (0:0:0, 0:0:0);
(B2B1[12] => V[15]) = (0:0:0, 0:0:0);
(B2B1[12] => V[16]) = (0:0:0, 0:0:0);
(B2B1[12] => V[17]) = (0:0:0, 0:0:0);
(B2B1[12] => V[18]) = (0:0:0, 0:0:0);
(B2B1[12] => V[19]) = (0:0:0, 0:0:0);
(B2B1[12] => V[20]) = (0:0:0, 0:0:0);
(B2B1[12] => V[21]) = (0:0:0, 0:0:0);
(B2B1[12] => V[22]) = (0:0:0, 0:0:0);
(B2B1[12] => V[23]) = (0:0:0, 0:0:0);
(B2B1[12] => V[24]) = (0:0:0, 0:0:0);
(B2B1[12] => V[25]) = (0:0:0, 0:0:0);
(B2B1[12] => V[26]) = (0:0:0, 0:0:0);
(B2B1[12] => V[27]) = (0:0:0, 0:0:0);
(B2B1[12] => V[28]) = (0:0:0, 0:0:0);
(B2B1[12] => V[29]) = (0:0:0, 0:0:0);
(B2B1[12] => V[30]) = (0:0:0, 0:0:0);
(B2B1[12] => V[31]) = (0:0:0, 0:0:0);
(B2B1[12] => V[32]) = (0:0:0, 0:0:0);
(B2B1[12] => V[33]) = (0:0:0, 0:0:0);
(B2B1[12] => V[34]) = (0:0:0, 0:0:0);
(B2B1[12] => V[35]) = (0:0:0, 0:0:0);
(B2B1[12] => V[36]) = (0:0:0, 0:0:0);
(B2B1[12] => V[37]) = (0:0:0, 0:0:0);
(B2B1[12] => V[38]) = (0:0:0, 0:0:0);
(B2B1[12] => V[39]) = (0:0:0, 0:0:0);
(B2B1[12] => V[40]) = (0:0:0, 0:0:0);
(B2B1[13] => U[13]) = (0:0:0, 0:0:0);
(B2B1[13] => U[14]) = (0:0:0, 0:0:0);
(B2B1[13] => U[15]) = (0:0:0, 0:0:0);
(B2B1[13] => U[16]) = (0:0:0, 0:0:0);
(B2B1[13] => U[17]) = (0:0:0, 0:0:0);
(B2B1[13] => U[18]) = (0:0:0, 0:0:0);
(B2B1[13] => U[19]) = (0:0:0, 0:0:0);
(B2B1[13] => U[20]) = (0:0:0, 0:0:0);
(B2B1[13] => U[21]) = (0:0:0, 0:0:0);
(B2B1[13] => U[22]) = (0:0:0, 0:0:0);
(B2B1[13] => U[23]) = (0:0:0, 0:0:0);
(B2B1[13] => U[24]) = (0:0:0, 0:0:0);
(B2B1[13] => U[25]) = (0:0:0, 0:0:0);
(B2B1[13] => U[26]) = (0:0:0, 0:0:0);
(B2B1[13] => U[27]) = (0:0:0, 0:0:0);
(B2B1[13] => U[28]) = (0:0:0, 0:0:0);
(B2B1[13] => U[29]) = (0:0:0, 0:0:0);
(B2B1[13] => U[30]) = (0:0:0, 0:0:0);
(B2B1[13] => U[31]) = (0:0:0, 0:0:0);
(B2B1[13] => U[32]) = (0:0:0, 0:0:0);
(B2B1[13] => U[33]) = (0:0:0, 0:0:0);
(B2B1[13] => U[34]) = (0:0:0, 0:0:0);
(B2B1[13] => U[35]) = (0:0:0, 0:0:0);
(B2B1[13] => U[36]) = (0:0:0, 0:0:0);
(B2B1[13] => U[37]) = (0:0:0, 0:0:0);
(B2B1[13] => U[38]) = (0:0:0, 0:0:0);
(B2B1[13] => U[39]) = (0:0:0, 0:0:0);
(B2B1[13] => U[40]) = (0:0:0, 0:0:0);
(B2B1[13] => U[41]) = (0:0:0, 0:0:0);
(B2B1[13] => U[42]) = (0:0:0, 0:0:0);
(B2B1[13] => V[12]) = (0:0:0, 0:0:0);
(B2B1[13] => V[13]) = (0:0:0, 0:0:0);
(B2B1[13] => V[14]) = (0:0:0, 0:0:0);
(B2B1[13] => V[15]) = (0:0:0, 0:0:0);
(B2B1[13] => V[16]) = (0:0:0, 0:0:0);
(B2B1[13] => V[17]) = (0:0:0, 0:0:0);
(B2B1[13] => V[18]) = (0:0:0, 0:0:0);
(B2B1[13] => V[19]) = (0:0:0, 0:0:0);
(B2B1[13] => V[20]) = (0:0:0, 0:0:0);
(B2B1[13] => V[21]) = (0:0:0, 0:0:0);
(B2B1[13] => V[22]) = (0:0:0, 0:0:0);
(B2B1[13] => V[23]) = (0:0:0, 0:0:0);
(B2B1[13] => V[24]) = (0:0:0, 0:0:0);
(B2B1[13] => V[25]) = (0:0:0, 0:0:0);
(B2B1[13] => V[26]) = (0:0:0, 0:0:0);
(B2B1[13] => V[27]) = (0:0:0, 0:0:0);
(B2B1[13] => V[28]) = (0:0:0, 0:0:0);
(B2B1[13] => V[29]) = (0:0:0, 0:0:0);
(B2B1[13] => V[30]) = (0:0:0, 0:0:0);
(B2B1[13] => V[31]) = (0:0:0, 0:0:0);
(B2B1[13] => V[32]) = (0:0:0, 0:0:0);
(B2B1[13] => V[33]) = (0:0:0, 0:0:0);
(B2B1[13] => V[34]) = (0:0:0, 0:0:0);
(B2B1[13] => V[35]) = (0:0:0, 0:0:0);
(B2B1[13] => V[36]) = (0:0:0, 0:0:0);
(B2B1[13] => V[37]) = (0:0:0, 0:0:0);
(B2B1[13] => V[38]) = (0:0:0, 0:0:0);
(B2B1[13] => V[39]) = (0:0:0, 0:0:0);
(B2B1[13] => V[40]) = (0:0:0, 0:0:0);
(B2B1[13] => V[41]) = (0:0:0, 0:0:0);
(B2B1[14] => U[15]) = (0:0:0, 0:0:0);
(B2B1[14] => U[16]) = (0:0:0, 0:0:0);
(B2B1[14] => U[17]) = (0:0:0, 0:0:0);
(B2B1[14] => U[18]) = (0:0:0, 0:0:0);
(B2B1[14] => U[19]) = (0:0:0, 0:0:0);
(B2B1[14] => U[20]) = (0:0:0, 0:0:0);
(B2B1[14] => U[21]) = (0:0:0, 0:0:0);
(B2B1[14] => U[22]) = (0:0:0, 0:0:0);
(B2B1[14] => U[23]) = (0:0:0, 0:0:0);
(B2B1[14] => U[24]) = (0:0:0, 0:0:0);
(B2B1[14] => U[25]) = (0:0:0, 0:0:0);
(B2B1[14] => U[26]) = (0:0:0, 0:0:0);
(B2B1[14] => U[27]) = (0:0:0, 0:0:0);
(B2B1[14] => U[28]) = (0:0:0, 0:0:0);
(B2B1[14] => U[29]) = (0:0:0, 0:0:0);
(B2B1[14] => U[30]) = (0:0:0, 0:0:0);
(B2B1[14] => U[31]) = (0:0:0, 0:0:0);
(B2B1[14] => U[32]) = (0:0:0, 0:0:0);
(B2B1[14] => U[33]) = (0:0:0, 0:0:0);
(B2B1[14] => U[34]) = (0:0:0, 0:0:0);
(B2B1[14] => U[35]) = (0:0:0, 0:0:0);
(B2B1[14] => U[36]) = (0:0:0, 0:0:0);
(B2B1[14] => U[37]) = (0:0:0, 0:0:0);
(B2B1[14] => U[38]) = (0:0:0, 0:0:0);
(B2B1[14] => U[39]) = (0:0:0, 0:0:0);
(B2B1[14] => U[40]) = (0:0:0, 0:0:0);
(B2B1[14] => U[41]) = (0:0:0, 0:0:0);
(B2B1[14] => U[42]) = (0:0:0, 0:0:0);
(B2B1[14] => V[14]) = (0:0:0, 0:0:0);
(B2B1[14] => V[15]) = (0:0:0, 0:0:0);
(B2B1[14] => V[16]) = (0:0:0, 0:0:0);
(B2B1[14] => V[17]) = (0:0:0, 0:0:0);
(B2B1[14] => V[18]) = (0:0:0, 0:0:0);
(B2B1[14] => V[19]) = (0:0:0, 0:0:0);
(B2B1[14] => V[20]) = (0:0:0, 0:0:0);
(B2B1[14] => V[21]) = (0:0:0, 0:0:0);
(B2B1[14] => V[22]) = (0:0:0, 0:0:0);
(B2B1[14] => V[23]) = (0:0:0, 0:0:0);
(B2B1[14] => V[24]) = (0:0:0, 0:0:0);
(B2B1[14] => V[25]) = (0:0:0, 0:0:0);
(B2B1[14] => V[26]) = (0:0:0, 0:0:0);
(B2B1[14] => V[27]) = (0:0:0, 0:0:0);
(B2B1[14] => V[28]) = (0:0:0, 0:0:0);
(B2B1[14] => V[29]) = (0:0:0, 0:0:0);
(B2B1[14] => V[30]) = (0:0:0, 0:0:0);
(B2B1[14] => V[31]) = (0:0:0, 0:0:0);
(B2B1[14] => V[32]) = (0:0:0, 0:0:0);
(B2B1[14] => V[33]) = (0:0:0, 0:0:0);
(B2B1[14] => V[34]) = (0:0:0, 0:0:0);
(B2B1[14] => V[35]) = (0:0:0, 0:0:0);
(B2B1[14] => V[36]) = (0:0:0, 0:0:0);
(B2B1[14] => V[37]) = (0:0:0, 0:0:0);
(B2B1[14] => V[38]) = (0:0:0, 0:0:0);
(B2B1[14] => V[39]) = (0:0:0, 0:0:0);
(B2B1[14] => V[40]) = (0:0:0, 0:0:0);
(B2B1[14] => V[41]) = (0:0:0, 0:0:0);
(B2B1[15] => U[15]) = (0:0:0, 0:0:0);
(B2B1[15] => U[16]) = (0:0:0, 0:0:0);
(B2B1[15] => U[17]) = (0:0:0, 0:0:0);
(B2B1[15] => U[18]) = (0:0:0, 0:0:0);
(B2B1[15] => U[19]) = (0:0:0, 0:0:0);
(B2B1[15] => U[20]) = (0:0:0, 0:0:0);
(B2B1[15] => U[21]) = (0:0:0, 0:0:0);
(B2B1[15] => U[22]) = (0:0:0, 0:0:0);
(B2B1[15] => U[23]) = (0:0:0, 0:0:0);
(B2B1[15] => U[24]) = (0:0:0, 0:0:0);
(B2B1[15] => U[25]) = (0:0:0, 0:0:0);
(B2B1[15] => U[26]) = (0:0:0, 0:0:0);
(B2B1[15] => U[27]) = (0:0:0, 0:0:0);
(B2B1[15] => U[28]) = (0:0:0, 0:0:0);
(B2B1[15] => U[29]) = (0:0:0, 0:0:0);
(B2B1[15] => U[30]) = (0:0:0, 0:0:0);
(B2B1[15] => U[31]) = (0:0:0, 0:0:0);
(B2B1[15] => U[32]) = (0:0:0, 0:0:0);
(B2B1[15] => U[33]) = (0:0:0, 0:0:0);
(B2B1[15] => U[34]) = (0:0:0, 0:0:0);
(B2B1[15] => U[35]) = (0:0:0, 0:0:0);
(B2B1[15] => U[36]) = (0:0:0, 0:0:0);
(B2B1[15] => U[37]) = (0:0:0, 0:0:0);
(B2B1[15] => U[38]) = (0:0:0, 0:0:0);
(B2B1[15] => U[39]) = (0:0:0, 0:0:0);
(B2B1[15] => U[40]) = (0:0:0, 0:0:0);
(B2B1[15] => U[41]) = (0:0:0, 0:0:0);
(B2B1[15] => U[42]) = (0:0:0, 0:0:0);
(B2B1[15] => U[43]) = (0:0:0, 0:0:0);
(B2B1[15] => V[14]) = (0:0:0, 0:0:0);
(B2B1[15] => V[15]) = (0:0:0, 0:0:0);
(B2B1[15] => V[16]) = (0:0:0, 0:0:0);
(B2B1[15] => V[17]) = (0:0:0, 0:0:0);
(B2B1[15] => V[18]) = (0:0:0, 0:0:0);
(B2B1[15] => V[19]) = (0:0:0, 0:0:0);
(B2B1[15] => V[20]) = (0:0:0, 0:0:0);
(B2B1[15] => V[21]) = (0:0:0, 0:0:0);
(B2B1[15] => V[22]) = (0:0:0, 0:0:0);
(B2B1[15] => V[23]) = (0:0:0, 0:0:0);
(B2B1[15] => V[24]) = (0:0:0, 0:0:0);
(B2B1[15] => V[25]) = (0:0:0, 0:0:0);
(B2B1[15] => V[26]) = (0:0:0, 0:0:0);
(B2B1[15] => V[27]) = (0:0:0, 0:0:0);
(B2B1[15] => V[28]) = (0:0:0, 0:0:0);
(B2B1[15] => V[29]) = (0:0:0, 0:0:0);
(B2B1[15] => V[30]) = (0:0:0, 0:0:0);
(B2B1[15] => V[31]) = (0:0:0, 0:0:0);
(B2B1[15] => V[32]) = (0:0:0, 0:0:0);
(B2B1[15] => V[33]) = (0:0:0, 0:0:0);
(B2B1[15] => V[34]) = (0:0:0, 0:0:0);
(B2B1[15] => V[35]) = (0:0:0, 0:0:0);
(B2B1[15] => V[36]) = (0:0:0, 0:0:0);
(B2B1[15] => V[37]) = (0:0:0, 0:0:0);
(B2B1[15] => V[38]) = (0:0:0, 0:0:0);
(B2B1[15] => V[39]) = (0:0:0, 0:0:0);
(B2B1[15] => V[40]) = (0:0:0, 0:0:0);
(B2B1[15] => V[41]) = (0:0:0, 0:0:0);
(B2B1[15] => V[42]) = (0:0:0, 0:0:0);
(B2B1[15] => V[43]) = (0:0:0, 0:0:0);
(B2B1[16] => U[17]) = (0:0:0, 0:0:0);
(B2B1[16] => U[18]) = (0:0:0, 0:0:0);
(B2B1[16] => U[19]) = (0:0:0, 0:0:0);
(B2B1[16] => U[20]) = (0:0:0, 0:0:0);
(B2B1[16] => U[21]) = (0:0:0, 0:0:0);
(B2B1[16] => U[22]) = (0:0:0, 0:0:0);
(B2B1[16] => U[23]) = (0:0:0, 0:0:0);
(B2B1[16] => U[24]) = (0:0:0, 0:0:0);
(B2B1[16] => U[25]) = (0:0:0, 0:0:0);
(B2B1[16] => U[26]) = (0:0:0, 0:0:0);
(B2B1[16] => U[27]) = (0:0:0, 0:0:0);
(B2B1[16] => U[28]) = (0:0:0, 0:0:0);
(B2B1[16] => U[29]) = (0:0:0, 0:0:0);
(B2B1[16] => U[30]) = (0:0:0, 0:0:0);
(B2B1[16] => U[31]) = (0:0:0, 0:0:0);
(B2B1[16] => U[32]) = (0:0:0, 0:0:0);
(B2B1[16] => U[33]) = (0:0:0, 0:0:0);
(B2B1[16] => U[34]) = (0:0:0, 0:0:0);
(B2B1[16] => U[35]) = (0:0:0, 0:0:0);
(B2B1[16] => U[36]) = (0:0:0, 0:0:0);
(B2B1[16] => U[37]) = (0:0:0, 0:0:0);
(B2B1[16] => U[38]) = (0:0:0, 0:0:0);
(B2B1[16] => U[39]) = (0:0:0, 0:0:0);
(B2B1[16] => U[40]) = (0:0:0, 0:0:0);
(B2B1[16] => U[41]) = (0:0:0, 0:0:0);
(B2B1[16] => U[42]) = (0:0:0, 0:0:0);
(B2B1[16] => U[43]) = (0:0:0, 0:0:0);
(B2B1[16] => V[16]) = (0:0:0, 0:0:0);
(B2B1[16] => V[17]) = (0:0:0, 0:0:0);
(B2B1[16] => V[18]) = (0:0:0, 0:0:0);
(B2B1[16] => V[19]) = (0:0:0, 0:0:0);
(B2B1[16] => V[20]) = (0:0:0, 0:0:0);
(B2B1[16] => V[21]) = (0:0:0, 0:0:0);
(B2B1[16] => V[22]) = (0:0:0, 0:0:0);
(B2B1[16] => V[23]) = (0:0:0, 0:0:0);
(B2B1[16] => V[24]) = (0:0:0, 0:0:0);
(B2B1[16] => V[25]) = (0:0:0, 0:0:0);
(B2B1[16] => V[26]) = (0:0:0, 0:0:0);
(B2B1[16] => V[27]) = (0:0:0, 0:0:0);
(B2B1[16] => V[28]) = (0:0:0, 0:0:0);
(B2B1[16] => V[29]) = (0:0:0, 0:0:0);
(B2B1[16] => V[30]) = (0:0:0, 0:0:0);
(B2B1[16] => V[31]) = (0:0:0, 0:0:0);
(B2B1[16] => V[32]) = (0:0:0, 0:0:0);
(B2B1[16] => V[33]) = (0:0:0, 0:0:0);
(B2B1[16] => V[34]) = (0:0:0, 0:0:0);
(B2B1[16] => V[35]) = (0:0:0, 0:0:0);
(B2B1[16] => V[36]) = (0:0:0, 0:0:0);
(B2B1[16] => V[37]) = (0:0:0, 0:0:0);
(B2B1[16] => V[38]) = (0:0:0, 0:0:0);
(B2B1[16] => V[39]) = (0:0:0, 0:0:0);
(B2B1[16] => V[40]) = (0:0:0, 0:0:0);
(B2B1[16] => V[41]) = (0:0:0, 0:0:0);
(B2B1[16] => V[42]) = (0:0:0, 0:0:0);
(B2B1[16] => V[43]) = (0:0:0, 0:0:0);
(B2B1[17] => BMULT17) = (0:0:0, 0:0:0);
(B2B1[17] => U[17]) = (0:0:0, 0:0:0);
(B2B1[17] => U[18]) = (0:0:0, 0:0:0);
(B2B1[17] => U[19]) = (0:0:0, 0:0:0);
(B2B1[17] => U[20]) = (0:0:0, 0:0:0);
(B2B1[17] => U[21]) = (0:0:0, 0:0:0);
(B2B1[17] => U[22]) = (0:0:0, 0:0:0);
(B2B1[17] => U[23]) = (0:0:0, 0:0:0);
(B2B1[17] => U[24]) = (0:0:0, 0:0:0);
(B2B1[17] => U[25]) = (0:0:0, 0:0:0);
(B2B1[17] => U[26]) = (0:0:0, 0:0:0);
(B2B1[17] => U[27]) = (0:0:0, 0:0:0);
(B2B1[17] => U[28]) = (0:0:0, 0:0:0);
(B2B1[17] => U[29]) = (0:0:0, 0:0:0);
(B2B1[17] => U[30]) = (0:0:0, 0:0:0);
(B2B1[17] => U[31]) = (0:0:0, 0:0:0);
(B2B1[17] => U[32]) = (0:0:0, 0:0:0);
(B2B1[17] => U[33]) = (0:0:0, 0:0:0);
(B2B1[17] => U[34]) = (0:0:0, 0:0:0);
(B2B1[17] => U[35]) = (0:0:0, 0:0:0);
(B2B1[17] => U[36]) = (0:0:0, 0:0:0);
(B2B1[17] => U[37]) = (0:0:0, 0:0:0);
(B2B1[17] => U[38]) = (0:0:0, 0:0:0);
(B2B1[17] => U[39]) = (0:0:0, 0:0:0);
(B2B1[17] => U[40]) = (0:0:0, 0:0:0);
(B2B1[17] => U[41]) = (0:0:0, 0:0:0);
(B2B1[17] => U[42]) = (0:0:0, 0:0:0);
(B2B1[17] => U[43]) = (0:0:0, 0:0:0);
(B2B1[17] => V[16]) = (0:0:0, 0:0:0);
(B2B1[17] => V[17]) = (0:0:0, 0:0:0);
(B2B1[17] => V[18]) = (0:0:0, 0:0:0);
(B2B1[17] => V[19]) = (0:0:0, 0:0:0);
(B2B1[17] => V[20]) = (0:0:0, 0:0:0);
(B2B1[17] => V[21]) = (0:0:0, 0:0:0);
(B2B1[17] => V[22]) = (0:0:0, 0:0:0);
(B2B1[17] => V[23]) = (0:0:0, 0:0:0);
(B2B1[17] => V[24]) = (0:0:0, 0:0:0);
(B2B1[17] => V[25]) = (0:0:0, 0:0:0);
(B2B1[17] => V[26]) = (0:0:0, 0:0:0);
(B2B1[17] => V[27]) = (0:0:0, 0:0:0);
(B2B1[17] => V[28]) = (0:0:0, 0:0:0);
(B2B1[17] => V[29]) = (0:0:0, 0:0:0);
(B2B1[17] => V[30]) = (0:0:0, 0:0:0);
(B2B1[17] => V[31]) = (0:0:0, 0:0:0);
(B2B1[17] => V[32]) = (0:0:0, 0:0:0);
(B2B1[17] => V[33]) = (0:0:0, 0:0:0);
(B2B1[17] => V[34]) = (0:0:0, 0:0:0);
(B2B1[17] => V[35]) = (0:0:0, 0:0:0);
(B2B1[17] => V[36]) = (0:0:0, 0:0:0);
(B2B1[17] => V[37]) = (0:0:0, 0:0:0);
(B2B1[17] => V[38]) = (0:0:0, 0:0:0);
(B2B1[17] => V[39]) = (0:0:0, 0:0:0);
(B2B1[17] => V[40]) = (0:0:0, 0:0:0);
(B2B1[17] => V[41]) = (0:0:0, 0:0:0);
(B2B1[17] => V[42]) = (0:0:0, 0:0:0);
(B2B1[17] => V[43]) = (0:0:0, 0:0:0);
(B2B1[1] => U[0]) = (0:0:0, 0:0:0);
(B2B1[1] => U[10]) = (0:0:0, 0:0:0);
(B2B1[1] => U[11]) = (0:0:0, 0:0:0);
(B2B1[1] => U[12]) = (0:0:0, 0:0:0);
(B2B1[1] => U[13]) = (0:0:0, 0:0:0);
(B2B1[1] => U[14]) = (0:0:0, 0:0:0);
(B2B1[1] => U[15]) = (0:0:0, 0:0:0);
(B2B1[1] => U[16]) = (0:0:0, 0:0:0);
(B2B1[1] => U[17]) = (0:0:0, 0:0:0);
(B2B1[1] => U[18]) = (0:0:0, 0:0:0);
(B2B1[1] => U[19]) = (0:0:0, 0:0:0);
(B2B1[1] => U[1]) = (0:0:0, 0:0:0);
(B2B1[1] => U[20]) = (0:0:0, 0:0:0);
(B2B1[1] => U[21]) = (0:0:0, 0:0:0);
(B2B1[1] => U[22]) = (0:0:0, 0:0:0);
(B2B1[1] => U[23]) = (0:0:0, 0:0:0);
(B2B1[1] => U[24]) = (0:0:0, 0:0:0);
(B2B1[1] => U[25]) = (0:0:0, 0:0:0);
(B2B1[1] => U[26]) = (0:0:0, 0:0:0);
(B2B1[1] => U[27]) = (0:0:0, 0:0:0);
(B2B1[1] => U[28]) = (0:0:0, 0:0:0);
(B2B1[1] => U[29]) = (0:0:0, 0:0:0);
(B2B1[1] => U[2]) = (0:0:0, 0:0:0);
(B2B1[1] => U[30]) = (0:0:0, 0:0:0);
(B2B1[1] => U[31]) = (0:0:0, 0:0:0);
(B2B1[1] => U[32]) = (0:0:0, 0:0:0);
(B2B1[1] => U[33]) = (0:0:0, 0:0:0);
(B2B1[1] => U[3]) = (0:0:0, 0:0:0);
(B2B1[1] => U[4]) = (0:0:0, 0:0:0);
(B2B1[1] => U[5]) = (0:0:0, 0:0:0);
(B2B1[1] => U[6]) = (0:0:0, 0:0:0);
(B2B1[1] => U[7]) = (0:0:0, 0:0:0);
(B2B1[1] => U[8]) = (0:0:0, 0:0:0);
(B2B1[1] => U[9]) = (0:0:0, 0:0:0);
(B2B1[1] => V[0]) = (0:0:0, 0:0:0);
(B2B1[1] => V[10]) = (0:0:0, 0:0:0);
(B2B1[1] => V[11]) = (0:0:0, 0:0:0);
(B2B1[1] => V[12]) = (0:0:0, 0:0:0);
(B2B1[1] => V[13]) = (0:0:0, 0:0:0);
(B2B1[1] => V[14]) = (0:0:0, 0:0:0);
(B2B1[1] => V[15]) = (0:0:0, 0:0:0);
(B2B1[1] => V[16]) = (0:0:0, 0:0:0);
(B2B1[1] => V[17]) = (0:0:0, 0:0:0);
(B2B1[1] => V[18]) = (0:0:0, 0:0:0);
(B2B1[1] => V[19]) = (0:0:0, 0:0:0);
(B2B1[1] => V[20]) = (0:0:0, 0:0:0);
(B2B1[1] => V[21]) = (0:0:0, 0:0:0);
(B2B1[1] => V[22]) = (0:0:0, 0:0:0);
(B2B1[1] => V[23]) = (0:0:0, 0:0:0);
(B2B1[1] => V[24]) = (0:0:0, 0:0:0);
(B2B1[1] => V[25]) = (0:0:0, 0:0:0);
(B2B1[1] => V[26]) = (0:0:0, 0:0:0);
(B2B1[1] => V[27]) = (0:0:0, 0:0:0);
(B2B1[1] => V[28]) = (0:0:0, 0:0:0);
(B2B1[1] => V[29]) = (0:0:0, 0:0:0);
(B2B1[1] => V[30]) = (0:0:0, 0:0:0);
(B2B1[1] => V[31]) = (0:0:0, 0:0:0);
(B2B1[1] => V[32]) = (0:0:0, 0:0:0);
(B2B1[1] => V[4]) = (0:0:0, 0:0:0);
(B2B1[1] => V[5]) = (0:0:0, 0:0:0);
(B2B1[1] => V[6]) = (0:0:0, 0:0:0);
(B2B1[1] => V[7]) = (0:0:0, 0:0:0);
(B2B1[1] => V[8]) = (0:0:0, 0:0:0);
(B2B1[1] => V[9]) = (0:0:0, 0:0:0);
(B2B1[2] => U[10]) = (0:0:0, 0:0:0);
(B2B1[2] => U[11]) = (0:0:0, 0:0:0);
(B2B1[2] => U[12]) = (0:0:0, 0:0:0);
(B2B1[2] => U[13]) = (0:0:0, 0:0:0);
(B2B1[2] => U[14]) = (0:0:0, 0:0:0);
(B2B1[2] => U[15]) = (0:0:0, 0:0:0);
(B2B1[2] => U[16]) = (0:0:0, 0:0:0);
(B2B1[2] => U[17]) = (0:0:0, 0:0:0);
(B2B1[2] => U[18]) = (0:0:0, 0:0:0);
(B2B1[2] => U[19]) = (0:0:0, 0:0:0);
(B2B1[2] => U[20]) = (0:0:0, 0:0:0);
(B2B1[2] => U[21]) = (0:0:0, 0:0:0);
(B2B1[2] => U[22]) = (0:0:0, 0:0:0);
(B2B1[2] => U[23]) = (0:0:0, 0:0:0);
(B2B1[2] => U[24]) = (0:0:0, 0:0:0);
(B2B1[2] => U[25]) = (0:0:0, 0:0:0);
(B2B1[2] => U[26]) = (0:0:0, 0:0:0);
(B2B1[2] => U[27]) = (0:0:0, 0:0:0);
(B2B1[2] => U[28]) = (0:0:0, 0:0:0);
(B2B1[2] => U[29]) = (0:0:0, 0:0:0);
(B2B1[2] => U[2]) = (0:0:0, 0:0:0);
(B2B1[2] => U[30]) = (0:0:0, 0:0:0);
(B2B1[2] => U[31]) = (0:0:0, 0:0:0);
(B2B1[2] => U[32]) = (0:0:0, 0:0:0);
(B2B1[2] => U[33]) = (0:0:0, 0:0:0);
(B2B1[2] => U[3]) = (0:0:0, 0:0:0);
(B2B1[2] => U[4]) = (0:0:0, 0:0:0);
(B2B1[2] => U[5]) = (0:0:0, 0:0:0);
(B2B1[2] => U[6]) = (0:0:0, 0:0:0);
(B2B1[2] => U[7]) = (0:0:0, 0:0:0);
(B2B1[2] => U[8]) = (0:0:0, 0:0:0);
(B2B1[2] => U[9]) = (0:0:0, 0:0:0);
(B2B1[2] => V[10]) = (0:0:0, 0:0:0);
(B2B1[2] => V[11]) = (0:0:0, 0:0:0);
(B2B1[2] => V[12]) = (0:0:0, 0:0:0);
(B2B1[2] => V[13]) = (0:0:0, 0:0:0);
(B2B1[2] => V[14]) = (0:0:0, 0:0:0);
(B2B1[2] => V[15]) = (0:0:0, 0:0:0);
(B2B1[2] => V[16]) = (0:0:0, 0:0:0);
(B2B1[2] => V[17]) = (0:0:0, 0:0:0);
(B2B1[2] => V[18]) = (0:0:0, 0:0:0);
(B2B1[2] => V[19]) = (0:0:0, 0:0:0);
(B2B1[2] => V[20]) = (0:0:0, 0:0:0);
(B2B1[2] => V[21]) = (0:0:0, 0:0:0);
(B2B1[2] => V[22]) = (0:0:0, 0:0:0);
(B2B1[2] => V[23]) = (0:0:0, 0:0:0);
(B2B1[2] => V[24]) = (0:0:0, 0:0:0);
(B2B1[2] => V[25]) = (0:0:0, 0:0:0);
(B2B1[2] => V[26]) = (0:0:0, 0:0:0);
(B2B1[2] => V[27]) = (0:0:0, 0:0:0);
(B2B1[2] => V[28]) = (0:0:0, 0:0:0);
(B2B1[2] => V[29]) = (0:0:0, 0:0:0);
(B2B1[2] => V[30]) = (0:0:0, 0:0:0);
(B2B1[2] => V[31]) = (0:0:0, 0:0:0);
(B2B1[2] => V[32]) = (0:0:0, 0:0:0);
(B2B1[2] => V[4]) = (0:0:0, 0:0:0);
(B2B1[2] => V[5]) = (0:0:0, 0:0:0);
(B2B1[2] => V[6]) = (0:0:0, 0:0:0);
(B2B1[2] => V[7]) = (0:0:0, 0:0:0);
(B2B1[2] => V[8]) = (0:0:0, 0:0:0);
(B2B1[2] => V[9]) = (0:0:0, 0:0:0);
(B2B1[3] => U[10]) = (0:0:0, 0:0:0);
(B2B1[3] => U[11]) = (0:0:0, 0:0:0);
(B2B1[3] => U[12]) = (0:0:0, 0:0:0);
(B2B1[3] => U[13]) = (0:0:0, 0:0:0);
(B2B1[3] => U[14]) = (0:0:0, 0:0:0);
(B2B1[3] => U[15]) = (0:0:0, 0:0:0);
(B2B1[3] => U[16]) = (0:0:0, 0:0:0);
(B2B1[3] => U[17]) = (0:0:0, 0:0:0);
(B2B1[3] => U[18]) = (0:0:0, 0:0:0);
(B2B1[3] => U[19]) = (0:0:0, 0:0:0);
(B2B1[3] => U[20]) = (0:0:0, 0:0:0);
(B2B1[3] => U[21]) = (0:0:0, 0:0:0);
(B2B1[3] => U[22]) = (0:0:0, 0:0:0);
(B2B1[3] => U[23]) = (0:0:0, 0:0:0);
(B2B1[3] => U[24]) = (0:0:0, 0:0:0);
(B2B1[3] => U[25]) = (0:0:0, 0:0:0);
(B2B1[3] => U[26]) = (0:0:0, 0:0:0);
(B2B1[3] => U[27]) = (0:0:0, 0:0:0);
(B2B1[3] => U[28]) = (0:0:0, 0:0:0);
(B2B1[3] => U[29]) = (0:0:0, 0:0:0);
(B2B1[3] => U[2]) = (0:0:0, 0:0:0);
(B2B1[3] => U[30]) = (0:0:0, 0:0:0);
(B2B1[3] => U[31]) = (0:0:0, 0:0:0);
(B2B1[3] => U[32]) = (0:0:0, 0:0:0);
(B2B1[3] => U[33]) = (0:0:0, 0:0:0);
(B2B1[3] => U[34]) = (0:0:0, 0:0:0);
(B2B1[3] => U[35]) = (0:0:0, 0:0:0);
(B2B1[3] => U[3]) = (0:0:0, 0:0:0);
(B2B1[3] => U[4]) = (0:0:0, 0:0:0);
(B2B1[3] => U[5]) = (0:0:0, 0:0:0);
(B2B1[3] => U[6]) = (0:0:0, 0:0:0);
(B2B1[3] => U[7]) = (0:0:0, 0:0:0);
(B2B1[3] => U[8]) = (0:0:0, 0:0:0);
(B2B1[3] => U[9]) = (0:0:0, 0:0:0);
(B2B1[3] => V[10]) = (0:0:0, 0:0:0);
(B2B1[3] => V[11]) = (0:0:0, 0:0:0);
(B2B1[3] => V[12]) = (0:0:0, 0:0:0);
(B2B1[3] => V[13]) = (0:0:0, 0:0:0);
(B2B1[3] => V[14]) = (0:0:0, 0:0:0);
(B2B1[3] => V[15]) = (0:0:0, 0:0:0);
(B2B1[3] => V[16]) = (0:0:0, 0:0:0);
(B2B1[3] => V[17]) = (0:0:0, 0:0:0);
(B2B1[3] => V[18]) = (0:0:0, 0:0:0);
(B2B1[3] => V[19]) = (0:0:0, 0:0:0);
(B2B1[3] => V[20]) = (0:0:0, 0:0:0);
(B2B1[3] => V[21]) = (0:0:0, 0:0:0);
(B2B1[3] => V[22]) = (0:0:0, 0:0:0);
(B2B1[3] => V[23]) = (0:0:0, 0:0:0);
(B2B1[3] => V[24]) = (0:0:0, 0:0:0);
(B2B1[3] => V[25]) = (0:0:0, 0:0:0);
(B2B1[3] => V[26]) = (0:0:0, 0:0:0);
(B2B1[3] => V[27]) = (0:0:0, 0:0:0);
(B2B1[3] => V[28]) = (0:0:0, 0:0:0);
(B2B1[3] => V[29]) = (0:0:0, 0:0:0);
(B2B1[3] => V[30]) = (0:0:0, 0:0:0);
(B2B1[3] => V[31]) = (0:0:0, 0:0:0);
(B2B1[3] => V[32]) = (0:0:0, 0:0:0);
(B2B1[3] => V[33]) = (0:0:0, 0:0:0);
(B2B1[3] => V[34]) = (0:0:0, 0:0:0);
(B2B1[3] => V[4]) = (0:0:0, 0:0:0);
(B2B1[3] => V[5]) = (0:0:0, 0:0:0);
(B2B1[3] => V[6]) = (0:0:0, 0:0:0);
(B2B1[3] => V[7]) = (0:0:0, 0:0:0);
(B2B1[3] => V[8]) = (0:0:0, 0:0:0);
(B2B1[3] => V[9]) = (0:0:0, 0:0:0);
(B2B1[4] => U[10]) = (0:0:0, 0:0:0);
(B2B1[4] => U[11]) = (0:0:0, 0:0:0);
(B2B1[4] => U[12]) = (0:0:0, 0:0:0);
(B2B1[4] => U[13]) = (0:0:0, 0:0:0);
(B2B1[4] => U[14]) = (0:0:0, 0:0:0);
(B2B1[4] => U[15]) = (0:0:0, 0:0:0);
(B2B1[4] => U[16]) = (0:0:0, 0:0:0);
(B2B1[4] => U[17]) = (0:0:0, 0:0:0);
(B2B1[4] => U[18]) = (0:0:0, 0:0:0);
(B2B1[4] => U[19]) = (0:0:0, 0:0:0);
(B2B1[4] => U[20]) = (0:0:0, 0:0:0);
(B2B1[4] => U[21]) = (0:0:0, 0:0:0);
(B2B1[4] => U[22]) = (0:0:0, 0:0:0);
(B2B1[4] => U[23]) = (0:0:0, 0:0:0);
(B2B1[4] => U[24]) = (0:0:0, 0:0:0);
(B2B1[4] => U[25]) = (0:0:0, 0:0:0);
(B2B1[4] => U[26]) = (0:0:0, 0:0:0);
(B2B1[4] => U[27]) = (0:0:0, 0:0:0);
(B2B1[4] => U[28]) = (0:0:0, 0:0:0);
(B2B1[4] => U[29]) = (0:0:0, 0:0:0);
(B2B1[4] => U[30]) = (0:0:0, 0:0:0);
(B2B1[4] => U[31]) = (0:0:0, 0:0:0);
(B2B1[4] => U[32]) = (0:0:0, 0:0:0);
(B2B1[4] => U[33]) = (0:0:0, 0:0:0);
(B2B1[4] => U[34]) = (0:0:0, 0:0:0);
(B2B1[4] => U[35]) = (0:0:0, 0:0:0);
(B2B1[4] => U[5]) = (0:0:0, 0:0:0);
(B2B1[4] => U[6]) = (0:0:0, 0:0:0);
(B2B1[4] => U[7]) = (0:0:0, 0:0:0);
(B2B1[4] => U[8]) = (0:0:0, 0:0:0);
(B2B1[4] => U[9]) = (0:0:0, 0:0:0);
(B2B1[4] => V[10]) = (0:0:0, 0:0:0);
(B2B1[4] => V[11]) = (0:0:0, 0:0:0);
(B2B1[4] => V[12]) = (0:0:0, 0:0:0);
(B2B1[4] => V[13]) = (0:0:0, 0:0:0);
(B2B1[4] => V[14]) = (0:0:0, 0:0:0);
(B2B1[4] => V[15]) = (0:0:0, 0:0:0);
(B2B1[4] => V[16]) = (0:0:0, 0:0:0);
(B2B1[4] => V[17]) = (0:0:0, 0:0:0);
(B2B1[4] => V[18]) = (0:0:0, 0:0:0);
(B2B1[4] => V[19]) = (0:0:0, 0:0:0);
(B2B1[4] => V[20]) = (0:0:0, 0:0:0);
(B2B1[4] => V[21]) = (0:0:0, 0:0:0);
(B2B1[4] => V[22]) = (0:0:0, 0:0:0);
(B2B1[4] => V[23]) = (0:0:0, 0:0:0);
(B2B1[4] => V[24]) = (0:0:0, 0:0:0);
(B2B1[4] => V[25]) = (0:0:0, 0:0:0);
(B2B1[4] => V[26]) = (0:0:0, 0:0:0);
(B2B1[4] => V[27]) = (0:0:0, 0:0:0);
(B2B1[4] => V[28]) = (0:0:0, 0:0:0);
(B2B1[4] => V[29]) = (0:0:0, 0:0:0);
(B2B1[4] => V[30]) = (0:0:0, 0:0:0);
(B2B1[4] => V[31]) = (0:0:0, 0:0:0);
(B2B1[4] => V[32]) = (0:0:0, 0:0:0);
(B2B1[4] => V[33]) = (0:0:0, 0:0:0);
(B2B1[4] => V[34]) = (0:0:0, 0:0:0);
(B2B1[4] => V[4]) = (0:0:0, 0:0:0);
(B2B1[4] => V[5]) = (0:0:0, 0:0:0);
(B2B1[4] => V[6]) = (0:0:0, 0:0:0);
(B2B1[4] => V[7]) = (0:0:0, 0:0:0);
(B2B1[4] => V[8]) = (0:0:0, 0:0:0);
(B2B1[4] => V[9]) = (0:0:0, 0:0:0);
(B2B1[5] => U[10]) = (0:0:0, 0:0:0);
(B2B1[5] => U[11]) = (0:0:0, 0:0:0);
(B2B1[5] => U[12]) = (0:0:0, 0:0:0);
(B2B1[5] => U[13]) = (0:0:0, 0:0:0);
(B2B1[5] => U[14]) = (0:0:0, 0:0:0);
(B2B1[5] => U[15]) = (0:0:0, 0:0:0);
(B2B1[5] => U[16]) = (0:0:0, 0:0:0);
(B2B1[5] => U[17]) = (0:0:0, 0:0:0);
(B2B1[5] => U[18]) = (0:0:0, 0:0:0);
(B2B1[5] => U[19]) = (0:0:0, 0:0:0);
(B2B1[5] => U[20]) = (0:0:0, 0:0:0);
(B2B1[5] => U[21]) = (0:0:0, 0:0:0);
(B2B1[5] => U[22]) = (0:0:0, 0:0:0);
(B2B1[5] => U[23]) = (0:0:0, 0:0:0);
(B2B1[5] => U[24]) = (0:0:0, 0:0:0);
(B2B1[5] => U[25]) = (0:0:0, 0:0:0);
(B2B1[5] => U[26]) = (0:0:0, 0:0:0);
(B2B1[5] => U[27]) = (0:0:0, 0:0:0);
(B2B1[5] => U[28]) = (0:0:0, 0:0:0);
(B2B1[5] => U[29]) = (0:0:0, 0:0:0);
(B2B1[5] => U[30]) = (0:0:0, 0:0:0);
(B2B1[5] => U[31]) = (0:0:0, 0:0:0);
(B2B1[5] => U[32]) = (0:0:0, 0:0:0);
(B2B1[5] => U[33]) = (0:0:0, 0:0:0);
(B2B1[5] => U[34]) = (0:0:0, 0:0:0);
(B2B1[5] => U[35]) = (0:0:0, 0:0:0);
(B2B1[5] => U[36]) = (0:0:0, 0:0:0);
(B2B1[5] => U[5]) = (0:0:0, 0:0:0);
(B2B1[5] => U[6]) = (0:0:0, 0:0:0);
(B2B1[5] => U[7]) = (0:0:0, 0:0:0);
(B2B1[5] => U[8]) = (0:0:0, 0:0:0);
(B2B1[5] => U[9]) = (0:0:0, 0:0:0);
(B2B1[5] => V[10]) = (0:0:0, 0:0:0);
(B2B1[5] => V[11]) = (0:0:0, 0:0:0);
(B2B1[5] => V[12]) = (0:0:0, 0:0:0);
(B2B1[5] => V[13]) = (0:0:0, 0:0:0);
(B2B1[5] => V[14]) = (0:0:0, 0:0:0);
(B2B1[5] => V[15]) = (0:0:0, 0:0:0);
(B2B1[5] => V[16]) = (0:0:0, 0:0:0);
(B2B1[5] => V[17]) = (0:0:0, 0:0:0);
(B2B1[5] => V[18]) = (0:0:0, 0:0:0);
(B2B1[5] => V[19]) = (0:0:0, 0:0:0);
(B2B1[5] => V[20]) = (0:0:0, 0:0:0);
(B2B1[5] => V[21]) = (0:0:0, 0:0:0);
(B2B1[5] => V[22]) = (0:0:0, 0:0:0);
(B2B1[5] => V[23]) = (0:0:0, 0:0:0);
(B2B1[5] => V[24]) = (0:0:0, 0:0:0);
(B2B1[5] => V[25]) = (0:0:0, 0:0:0);
(B2B1[5] => V[26]) = (0:0:0, 0:0:0);
(B2B1[5] => V[27]) = (0:0:0, 0:0:0);
(B2B1[5] => V[28]) = (0:0:0, 0:0:0);
(B2B1[5] => V[29]) = (0:0:0, 0:0:0);
(B2B1[5] => V[30]) = (0:0:0, 0:0:0);
(B2B1[5] => V[31]) = (0:0:0, 0:0:0);
(B2B1[5] => V[32]) = (0:0:0, 0:0:0);
(B2B1[5] => V[33]) = (0:0:0, 0:0:0);
(B2B1[5] => V[34]) = (0:0:0, 0:0:0);
(B2B1[5] => V[35]) = (0:0:0, 0:0:0);
(B2B1[5] => V[4]) = (0:0:0, 0:0:0);
(B2B1[5] => V[5]) = (0:0:0, 0:0:0);
(B2B1[5] => V[6]) = (0:0:0, 0:0:0);
(B2B1[5] => V[7]) = (0:0:0, 0:0:0);
(B2B1[5] => V[8]) = (0:0:0, 0:0:0);
(B2B1[5] => V[9]) = (0:0:0, 0:0:0);
(B2B1[6] => U[10]) = (0:0:0, 0:0:0);
(B2B1[6] => U[11]) = (0:0:0, 0:0:0);
(B2B1[6] => U[12]) = (0:0:0, 0:0:0);
(B2B1[6] => U[13]) = (0:0:0, 0:0:0);
(B2B1[6] => U[14]) = (0:0:0, 0:0:0);
(B2B1[6] => U[15]) = (0:0:0, 0:0:0);
(B2B1[6] => U[16]) = (0:0:0, 0:0:0);
(B2B1[6] => U[17]) = (0:0:0, 0:0:0);
(B2B1[6] => U[18]) = (0:0:0, 0:0:0);
(B2B1[6] => U[19]) = (0:0:0, 0:0:0);
(B2B1[6] => U[20]) = (0:0:0, 0:0:0);
(B2B1[6] => U[21]) = (0:0:0, 0:0:0);
(B2B1[6] => U[22]) = (0:0:0, 0:0:0);
(B2B1[6] => U[23]) = (0:0:0, 0:0:0);
(B2B1[6] => U[24]) = (0:0:0, 0:0:0);
(B2B1[6] => U[25]) = (0:0:0, 0:0:0);
(B2B1[6] => U[26]) = (0:0:0, 0:0:0);
(B2B1[6] => U[27]) = (0:0:0, 0:0:0);
(B2B1[6] => U[28]) = (0:0:0, 0:0:0);
(B2B1[6] => U[29]) = (0:0:0, 0:0:0);
(B2B1[6] => U[30]) = (0:0:0, 0:0:0);
(B2B1[6] => U[31]) = (0:0:0, 0:0:0);
(B2B1[6] => U[32]) = (0:0:0, 0:0:0);
(B2B1[6] => U[33]) = (0:0:0, 0:0:0);
(B2B1[6] => U[34]) = (0:0:0, 0:0:0);
(B2B1[6] => U[35]) = (0:0:0, 0:0:0);
(B2B1[6] => U[36]) = (0:0:0, 0:0:0);
(B2B1[6] => U[7]) = (0:0:0, 0:0:0);
(B2B1[6] => U[8]) = (0:0:0, 0:0:0);
(B2B1[6] => U[9]) = (0:0:0, 0:0:0);
(B2B1[6] => V[10]) = (0:0:0, 0:0:0);
(B2B1[6] => V[11]) = (0:0:0, 0:0:0);
(B2B1[6] => V[12]) = (0:0:0, 0:0:0);
(B2B1[6] => V[13]) = (0:0:0, 0:0:0);
(B2B1[6] => V[14]) = (0:0:0, 0:0:0);
(B2B1[6] => V[15]) = (0:0:0, 0:0:0);
(B2B1[6] => V[16]) = (0:0:0, 0:0:0);
(B2B1[6] => V[17]) = (0:0:0, 0:0:0);
(B2B1[6] => V[18]) = (0:0:0, 0:0:0);
(B2B1[6] => V[19]) = (0:0:0, 0:0:0);
(B2B1[6] => V[20]) = (0:0:0, 0:0:0);
(B2B1[6] => V[21]) = (0:0:0, 0:0:0);
(B2B1[6] => V[22]) = (0:0:0, 0:0:0);
(B2B1[6] => V[23]) = (0:0:0, 0:0:0);
(B2B1[6] => V[24]) = (0:0:0, 0:0:0);
(B2B1[6] => V[25]) = (0:0:0, 0:0:0);
(B2B1[6] => V[26]) = (0:0:0, 0:0:0);
(B2B1[6] => V[27]) = (0:0:0, 0:0:0);
(B2B1[6] => V[28]) = (0:0:0, 0:0:0);
(B2B1[6] => V[29]) = (0:0:0, 0:0:0);
(B2B1[6] => V[30]) = (0:0:0, 0:0:0);
(B2B1[6] => V[31]) = (0:0:0, 0:0:0);
(B2B1[6] => V[32]) = (0:0:0, 0:0:0);
(B2B1[6] => V[33]) = (0:0:0, 0:0:0);
(B2B1[6] => V[34]) = (0:0:0, 0:0:0);
(B2B1[6] => V[35]) = (0:0:0, 0:0:0);
(B2B1[6] => V[6]) = (0:0:0, 0:0:0);
(B2B1[6] => V[7]) = (0:0:0, 0:0:0);
(B2B1[6] => V[8]) = (0:0:0, 0:0:0);
(B2B1[6] => V[9]) = (0:0:0, 0:0:0);
(B2B1[7] => U[10]) = (0:0:0, 0:0:0);
(B2B1[7] => U[11]) = (0:0:0, 0:0:0);
(B2B1[7] => U[12]) = (0:0:0, 0:0:0);
(B2B1[7] => U[13]) = (0:0:0, 0:0:0);
(B2B1[7] => U[14]) = (0:0:0, 0:0:0);
(B2B1[7] => U[15]) = (0:0:0, 0:0:0);
(B2B1[7] => U[16]) = (0:0:0, 0:0:0);
(B2B1[7] => U[17]) = (0:0:0, 0:0:0);
(B2B1[7] => U[18]) = (0:0:0, 0:0:0);
(B2B1[7] => U[19]) = (0:0:0, 0:0:0);
(B2B1[7] => U[20]) = (0:0:0, 0:0:0);
(B2B1[7] => U[21]) = (0:0:0, 0:0:0);
(B2B1[7] => U[22]) = (0:0:0, 0:0:0);
(B2B1[7] => U[23]) = (0:0:0, 0:0:0);
(B2B1[7] => U[24]) = (0:0:0, 0:0:0);
(B2B1[7] => U[25]) = (0:0:0, 0:0:0);
(B2B1[7] => U[26]) = (0:0:0, 0:0:0);
(B2B1[7] => U[27]) = (0:0:0, 0:0:0);
(B2B1[7] => U[28]) = (0:0:0, 0:0:0);
(B2B1[7] => U[29]) = (0:0:0, 0:0:0);
(B2B1[7] => U[30]) = (0:0:0, 0:0:0);
(B2B1[7] => U[31]) = (0:0:0, 0:0:0);
(B2B1[7] => U[32]) = (0:0:0, 0:0:0);
(B2B1[7] => U[33]) = (0:0:0, 0:0:0);
(B2B1[7] => U[34]) = (0:0:0, 0:0:0);
(B2B1[7] => U[35]) = (0:0:0, 0:0:0);
(B2B1[7] => U[36]) = (0:0:0, 0:0:0);
(B2B1[7] => U[37]) = (0:0:0, 0:0:0);
(B2B1[7] => U[38]) = (0:0:0, 0:0:0);
(B2B1[7] => U[7]) = (0:0:0, 0:0:0);
(B2B1[7] => U[8]) = (0:0:0, 0:0:0);
(B2B1[7] => U[9]) = (0:0:0, 0:0:0);
(B2B1[7] => V[10]) = (0:0:0, 0:0:0);
(B2B1[7] => V[11]) = (0:0:0, 0:0:0);
(B2B1[7] => V[12]) = (0:0:0, 0:0:0);
(B2B1[7] => V[13]) = (0:0:0, 0:0:0);
(B2B1[7] => V[14]) = (0:0:0, 0:0:0);
(B2B1[7] => V[15]) = (0:0:0, 0:0:0);
(B2B1[7] => V[16]) = (0:0:0, 0:0:0);
(B2B1[7] => V[17]) = (0:0:0, 0:0:0);
(B2B1[7] => V[18]) = (0:0:0, 0:0:0);
(B2B1[7] => V[19]) = (0:0:0, 0:0:0);
(B2B1[7] => V[20]) = (0:0:0, 0:0:0);
(B2B1[7] => V[21]) = (0:0:0, 0:0:0);
(B2B1[7] => V[22]) = (0:0:0, 0:0:0);
(B2B1[7] => V[23]) = (0:0:0, 0:0:0);
(B2B1[7] => V[24]) = (0:0:0, 0:0:0);
(B2B1[7] => V[25]) = (0:0:0, 0:0:0);
(B2B1[7] => V[26]) = (0:0:0, 0:0:0);
(B2B1[7] => V[27]) = (0:0:0, 0:0:0);
(B2B1[7] => V[28]) = (0:0:0, 0:0:0);
(B2B1[7] => V[29]) = (0:0:0, 0:0:0);
(B2B1[7] => V[30]) = (0:0:0, 0:0:0);
(B2B1[7] => V[31]) = (0:0:0, 0:0:0);
(B2B1[7] => V[32]) = (0:0:0, 0:0:0);
(B2B1[7] => V[33]) = (0:0:0, 0:0:0);
(B2B1[7] => V[34]) = (0:0:0, 0:0:0);
(B2B1[7] => V[35]) = (0:0:0, 0:0:0);
(B2B1[7] => V[36]) = (0:0:0, 0:0:0);
(B2B1[7] => V[37]) = (0:0:0, 0:0:0);
(B2B1[7] => V[6]) = (0:0:0, 0:0:0);
(B2B1[7] => V[7]) = (0:0:0, 0:0:0);
(B2B1[7] => V[8]) = (0:0:0, 0:0:0);
(B2B1[7] => V[9]) = (0:0:0, 0:0:0);
(B2B1[8] => U[10]) = (0:0:0, 0:0:0);
(B2B1[8] => U[11]) = (0:0:0, 0:0:0);
(B2B1[8] => U[12]) = (0:0:0, 0:0:0);
(B2B1[8] => U[13]) = (0:0:0, 0:0:0);
(B2B1[8] => U[14]) = (0:0:0, 0:0:0);
(B2B1[8] => U[15]) = (0:0:0, 0:0:0);
(B2B1[8] => U[16]) = (0:0:0, 0:0:0);
(B2B1[8] => U[17]) = (0:0:0, 0:0:0);
(B2B1[8] => U[18]) = (0:0:0, 0:0:0);
(B2B1[8] => U[19]) = (0:0:0, 0:0:0);
(B2B1[8] => U[20]) = (0:0:0, 0:0:0);
(B2B1[8] => U[21]) = (0:0:0, 0:0:0);
(B2B1[8] => U[22]) = (0:0:0, 0:0:0);
(B2B1[8] => U[23]) = (0:0:0, 0:0:0);
(B2B1[8] => U[24]) = (0:0:0, 0:0:0);
(B2B1[8] => U[25]) = (0:0:0, 0:0:0);
(B2B1[8] => U[26]) = (0:0:0, 0:0:0);
(B2B1[8] => U[27]) = (0:0:0, 0:0:0);
(B2B1[8] => U[28]) = (0:0:0, 0:0:0);
(B2B1[8] => U[29]) = (0:0:0, 0:0:0);
(B2B1[8] => U[30]) = (0:0:0, 0:0:0);
(B2B1[8] => U[31]) = (0:0:0, 0:0:0);
(B2B1[8] => U[32]) = (0:0:0, 0:0:0);
(B2B1[8] => U[33]) = (0:0:0, 0:0:0);
(B2B1[8] => U[34]) = (0:0:0, 0:0:0);
(B2B1[8] => U[35]) = (0:0:0, 0:0:0);
(B2B1[8] => U[36]) = (0:0:0, 0:0:0);
(B2B1[8] => U[37]) = (0:0:0, 0:0:0);
(B2B1[8] => U[38]) = (0:0:0, 0:0:0);
(B2B1[8] => U[9]) = (0:0:0, 0:0:0);
(B2B1[8] => V[10]) = (0:0:0, 0:0:0);
(B2B1[8] => V[11]) = (0:0:0, 0:0:0);
(B2B1[8] => V[12]) = (0:0:0, 0:0:0);
(B2B1[8] => V[13]) = (0:0:0, 0:0:0);
(B2B1[8] => V[14]) = (0:0:0, 0:0:0);
(B2B1[8] => V[15]) = (0:0:0, 0:0:0);
(B2B1[8] => V[16]) = (0:0:0, 0:0:0);
(B2B1[8] => V[17]) = (0:0:0, 0:0:0);
(B2B1[8] => V[18]) = (0:0:0, 0:0:0);
(B2B1[8] => V[19]) = (0:0:0, 0:0:0);
(B2B1[8] => V[20]) = (0:0:0, 0:0:0);
(B2B1[8] => V[21]) = (0:0:0, 0:0:0);
(B2B1[8] => V[22]) = (0:0:0, 0:0:0);
(B2B1[8] => V[23]) = (0:0:0, 0:0:0);
(B2B1[8] => V[24]) = (0:0:0, 0:0:0);
(B2B1[8] => V[25]) = (0:0:0, 0:0:0);
(B2B1[8] => V[26]) = (0:0:0, 0:0:0);
(B2B1[8] => V[27]) = (0:0:0, 0:0:0);
(B2B1[8] => V[28]) = (0:0:0, 0:0:0);
(B2B1[8] => V[29]) = (0:0:0, 0:0:0);
(B2B1[8] => V[30]) = (0:0:0, 0:0:0);
(B2B1[8] => V[31]) = (0:0:0, 0:0:0);
(B2B1[8] => V[32]) = (0:0:0, 0:0:0);
(B2B1[8] => V[33]) = (0:0:0, 0:0:0);
(B2B1[8] => V[34]) = (0:0:0, 0:0:0);
(B2B1[8] => V[35]) = (0:0:0, 0:0:0);
(B2B1[8] => V[36]) = (0:0:0, 0:0:0);
(B2B1[8] => V[37]) = (0:0:0, 0:0:0);
(B2B1[8] => V[8]) = (0:0:0, 0:0:0);
(B2B1[8] => V[9]) = (0:0:0, 0:0:0);
(B2B1[9] => U[10]) = (0:0:0, 0:0:0);
(B2B1[9] => U[11]) = (0:0:0, 0:0:0);
(B2B1[9] => U[12]) = (0:0:0, 0:0:0);
(B2B1[9] => U[13]) = (0:0:0, 0:0:0);
(B2B1[9] => U[14]) = (0:0:0, 0:0:0);
(B2B1[9] => U[15]) = (0:0:0, 0:0:0);
(B2B1[9] => U[16]) = (0:0:0, 0:0:0);
(B2B1[9] => U[17]) = (0:0:0, 0:0:0);
(B2B1[9] => U[18]) = (0:0:0, 0:0:0);
(B2B1[9] => U[19]) = (0:0:0, 0:0:0);
(B2B1[9] => U[20]) = (0:0:0, 0:0:0);
(B2B1[9] => U[21]) = (0:0:0, 0:0:0);
(B2B1[9] => U[22]) = (0:0:0, 0:0:0);
(B2B1[9] => U[23]) = (0:0:0, 0:0:0);
(B2B1[9] => U[24]) = (0:0:0, 0:0:0);
(B2B1[9] => U[25]) = (0:0:0, 0:0:0);
(B2B1[9] => U[26]) = (0:0:0, 0:0:0);
(B2B1[9] => U[27]) = (0:0:0, 0:0:0);
(B2B1[9] => U[28]) = (0:0:0, 0:0:0);
(B2B1[9] => U[29]) = (0:0:0, 0:0:0);
(B2B1[9] => U[30]) = (0:0:0, 0:0:0);
(B2B1[9] => U[31]) = (0:0:0, 0:0:0);
(B2B1[9] => U[32]) = (0:0:0, 0:0:0);
(B2B1[9] => U[33]) = (0:0:0, 0:0:0);
(B2B1[9] => U[34]) = (0:0:0, 0:0:0);
(B2B1[9] => U[35]) = (0:0:0, 0:0:0);
(B2B1[9] => U[36]) = (0:0:0, 0:0:0);
(B2B1[9] => U[37]) = (0:0:0, 0:0:0);
(B2B1[9] => U[38]) = (0:0:0, 0:0:0);
(B2B1[9] => U[39]) = (0:0:0, 0:0:0);
(B2B1[9] => U[40]) = (0:0:0, 0:0:0);
(B2B1[9] => U[9]) = (0:0:0, 0:0:0);
(B2B1[9] => V[10]) = (0:0:0, 0:0:0);
(B2B1[9] => V[11]) = (0:0:0, 0:0:0);
(B2B1[9] => V[12]) = (0:0:0, 0:0:0);
(B2B1[9] => V[13]) = (0:0:0, 0:0:0);
(B2B1[9] => V[14]) = (0:0:0, 0:0:0);
(B2B1[9] => V[15]) = (0:0:0, 0:0:0);
(B2B1[9] => V[16]) = (0:0:0, 0:0:0);
(B2B1[9] => V[17]) = (0:0:0, 0:0:0);
(B2B1[9] => V[18]) = (0:0:0, 0:0:0);
(B2B1[9] => V[19]) = (0:0:0, 0:0:0);
(B2B1[9] => V[20]) = (0:0:0, 0:0:0);
(B2B1[9] => V[21]) = (0:0:0, 0:0:0);
(B2B1[9] => V[22]) = (0:0:0, 0:0:0);
(B2B1[9] => V[23]) = (0:0:0, 0:0:0);
(B2B1[9] => V[24]) = (0:0:0, 0:0:0);
(B2B1[9] => V[25]) = (0:0:0, 0:0:0);
(B2B1[9] => V[26]) = (0:0:0, 0:0:0);
(B2B1[9] => V[27]) = (0:0:0, 0:0:0);
(B2B1[9] => V[28]) = (0:0:0, 0:0:0);
(B2B1[9] => V[29]) = (0:0:0, 0:0:0);
(B2B1[9] => V[30]) = (0:0:0, 0:0:0);
(B2B1[9] => V[31]) = (0:0:0, 0:0:0);
(B2B1[9] => V[32]) = (0:0:0, 0:0:0);
(B2B1[9] => V[33]) = (0:0:0, 0:0:0);
(B2B1[9] => V[34]) = (0:0:0, 0:0:0);
(B2B1[9] => V[35]) = (0:0:0, 0:0:0);
(B2B1[9] => V[36]) = (0:0:0, 0:0:0);
(B2B1[9] => V[37]) = (0:0:0, 0:0:0);
(B2B1[9] => V[38]) = (0:0:0, 0:0:0);
(B2B1[9] => V[39]) = (0:0:0, 0:0:0);
(B2B1[9] => V[8]) = (0:0:0, 0:0:0);
(B2B1[9] => V[9]) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311OI_2_V
`define SKY130_FD_SC_LS__A311OI_2_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a311oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a311oi_2 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311OI_2_V
|
module fsa_stream_v2 #(
parameter integer C_OUT_DW = 24, /// C_CHANNEL_WIDTH * 3
parameter integer C_OUT_DV = 1,
parameter integer C_IMG_HW = 12,
parameter integer C_IMG_WW = 12,
parameter integer BR_AW = 12, /// same as C_IMG_WW
parameter integer C_CHANNEL_WIDTH = 8,
parameter integer C_S_CHANNEL = 1
)(
input clk,
input resetn,
input wire [C_IMG_HW-1:0] height ,
input wire [C_IMG_WW-1:0] width ,
input wire fsync ,
input wire en_overlay,
output wire rd_sof ,
output wire rd_en ,
output wire [BR_AW-1:0] rd_addr ,
input wire rd_black,
input wire rd_val_outer,
input wire [C_IMG_HW-1:0] rd_top_outer,
input wire [C_IMG_HW-1:0] rd_bot_outer,
input wire rd_val_inner,
input wire [C_IMG_HW-1:0] rd_top_inner,
input wire [C_IMG_HW-1:0] rd_bot_inner,
input wire lft_valid ,
input wire [C_IMG_WW-1:0] lft_edge ,
input wire rt_valid ,
input wire [C_IMG_WW-1:0] rt_edge ,
input wire lft_header_outer_valid,
input wire [C_IMG_WW-1:0] lft_header_outer_x ,
input wire lft_corner_valid,
input wire [C_IMG_WW-1:0] lft_corner_top_x,
input wire [C_IMG_HW-1:0] lft_corner_top_y,
input wire [C_IMG_WW-1:0] lft_corner_bot_x,
input wire [C_IMG_HW-1:0] lft_corner_bot_y,
input wire rt_header_outer_valid,
input wire [C_IMG_WW-1:0] rt_header_outer_x ,
input wire rt_corner_valid,
input wire [C_IMG_WW-1:0] rt_corner_top_x,
input wire [C_IMG_HW-1:0] rt_corner_top_y,
input wire [C_IMG_WW-1:0] rt_corner_bot_x,
input wire [C_IMG_HW-1:0] rt_corner_bot_y,
input wire s_axis_tvalid,
input wire [C_CHANNEL_WIDTH*C_S_CHANNEL-1:0] s_axis_tdata,
input wire s_axis_tuser,
input wire s_axis_tlast,
output wire s_axis_tready,
input wire [C_IMG_WW-1:0] s_axis_source_x,
input wire [C_IMG_HW-1:0] s_axis_source_y,
output wire m_axis_tvalid,
output wire [C_CHANNEL_WIDTH*3-1:0] m_axis_tdata,
output wire m_axis_tuser,
output wire m_axis_tlast,
input wire m_axis_tready
);
localparam integer C_STAGE_WIDTH = 2 + C_CHANNEL_WIDTH*C_S_CHANNEL;
localparam integer FIFO_DW = 2 + C_OUT_DW;
localparam integer FD_SOF = 0;
localparam integer FD_LAST = 1;
localparam integer FD_DATA = 2;
assign rd_sof = fsync;
assign rd_en = s_axis_tvalid && s_axis_tready;
assign rd_addr = s_axis_source_x;
reg rd_en_d1;
reg [C_IMG_HW-1:0] py_d1;
reg [C_IMG_WW-1:0] px_d1;
reg [C_STAGE_WIDTH-1:0] data_d1;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
rd_en_d1 <= 0;
py_d1 <= 0;
px_d1 <= 0;
data_d1 <= 0;
end
else begin
rd_en_d1 <= rd_en;
px_d1 <= s_axis_source_x;
py_d1 <= s_axis_source_y;
data_d1 <= {s_axis_tdata, s_axis_tlast, s_axis_tuser};
end
end
reg rd_en_d2;
reg [C_IMG_HW-1:0] py_d2;
reg [C_IMG_WW-1:0] px_d2;
reg [C_STAGE_WIDTH-1:0] data_d2;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
rd_en_d2 <= 0;
py_d2 <= 0;
px_d2 <= 0;
data_d2 <= 0;
end
else begin
rd_en_d2 <= rd_en_d1;
px_d2 <= px_d1;
py_d2 <= py_d1;
data_d2 <= data_d1;
end
end
reg rd_en_d3;
reg [C_IMG_HW-1:0] py_d3;
reg [C_IMG_WW-1:0] px_d3;
reg [C_STAGE_WIDTH-1:0] data_d3;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
rd_en_d3 <= 0;
py_d3 <= 0;
px_d3 <= 0;
data_d3 <= 0;
end
else begin
rd_en_d3 <= rd_en_d2;
py_d3 <= py_d2;
px_d3 <= px_d2;
data_d3 <= data_d2;
end
end
/// rd_data is valid
reg rd_en_d4;
reg [C_IMG_HW-1:0] py_d4;
reg [C_STAGE_WIDTH-1:0] data_d4;
/// corner
reg lc_t;
reg lc_b;
reg rc_t;
reg rc_b;
/// body
reg lb;
reg lb_t;
reg lb_b;
reg rb;
reg rb_t;
reg rb_b;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
rd_en_d4 <= 0;
py_d4 <= 0;
data_d4 <= 0;
lc_t <= 0;
lc_b <= 0;
rc_t <= 0;
rc_b <= 0;
lb <= 0;
lb_t <= 0;
lb_b <= 0;
rb <= 0;
rb_t <= 0;
rb_b <= 0;
end
else begin
rd_en_d4 <= rd_en_d3;
py_d4 <= py_d3;
data_d4 <= data_d3;
// @note if we use single result for multiple blockram, the image noise will result in vibrate
// header, then the defect will extent to image top at header column.
// if we blockram and result is one2one, then we can drop 'rd_val_outer', the lef_edge/rt_edge
// will work as expected.
lc_t <= (lft_corner_valid && rd_val_outer) && ((lft_corner_top_y <= py_d3 && py_d3 < rd_top_outer)
&& (lft_corner_top_x < px_d3 && px_d3 <= lft_edge));
lc_b <= (lft_corner_valid && rd_val_outer) && ((lft_corner_bot_y >= py_d3 && py_d3 > rd_bot_outer)
&& (lft_corner_bot_x < px_d3 && px_d3 <= lft_edge));
rc_t <= (rt_corner_valid && rd_val_outer) && ((rt_corner_top_y <= py_d3 && py_d3 < rd_top_outer)
&& (rt_edge <= px_d3 && px_d3 < rt_corner_top_x));
rc_b <= (rt_corner_valid && rd_val_outer) && ((rt_corner_bot_y >= py_d3 && py_d3 > rd_bot_outer)
&& (rt_edge <= px_d3 && px_d3 < rt_corner_bot_x));
lb <= lft_header_outer_valid && (px_d3 <= lft_header_outer_x);
rb <= rt_header_outer_valid && (px_d3 >= rt_header_outer_x);
lb_t <= lft_corner_valid && ((px_d3 <= lft_corner_top_x) && (py_d3 < rd_top_outer));
lb_b <= lft_corner_valid && ((px_d3 <= lft_corner_bot_x) && (py_d3 > rd_bot_outer));
rb_t <= rt_corner_valid && ((px_d3 >= rt_corner_top_x) && (py_d3 < rd_top_outer));
rb_b <= rt_corner_valid && ((px_d3 >= rt_corner_bot_x) && (py_d3 > rd_bot_outer));
end
end
/// @NOTE: delay 5, the almost_full for blockram must be 6
/// if you add delay, don't forget to change blockram config.
reg rd_en_d5;
reg [FIFO_DW-1 : 0] out_data_d5;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
rd_en_d5 <= 0;
out_data_d5 <= 0;
end
else begin
rd_en_d5 <= rd_en_d4;
out_data_d5[FD_SOF] <= data_d4[FD_SOF];
out_data_d5[FD_LAST] <= data_d4[FD_LAST];
if (en_overlay && ((lft_valid && (lc_t | lc_b))
|| (rt_valid && (rc_t | rc_b)))) begin
out_data_d5[FD_DATA+C_OUT_DW-1:FD_DATA] <= C_OUT_DV;
end
else begin
if (C_S_CHANNEL == 1) begin
out_data_d5[FD_DATA+C_OUT_DW-1:FD_DATA] <= {
data_d4[C_STAGE_WIDTH-1:FD_DATA],
data_d4[C_STAGE_WIDTH-1:FD_DATA],
data_d4[C_STAGE_WIDTH-1:FD_DATA]};
end
else if (C_S_CHANNEL == 3) begin
out_data_d5[FD_DATA+C_OUT_DW-1:FD_DATA] <= data_d4[C_STAGE_WIDTH-1:FD_DATA];
end
else begin
/// @ERROR
out_data_d5[FD_DATA+C_OUT_DW-1:FD_DATA] <= 0;
end
end
end
end
//////////////////////////////////////////////////// FIFO ////////////////////////////////////////
wire fw_en;
wire [FIFO_DW-1:0] fw_data;
wire fw_af;
wire fr_en;
wire[FIFO_DW-1:0] fr_data;
wire fr_empty;
simple_fifo # (
.DEPTH_WIDTH(3),
.DATA_WIDTH(FIFO_DW),
.ALMOST_FULL_TH(6),
.ALMOST_EMPTY_TH(1)
) fifo_inst (
.clk(clk),
.rst(~resetn),
.wr_data(fw_data),
.wr_en (fw_en ),
.rd_data(fr_data),
.rd_en (fr_en ),
.full(),
.empty(fr_empty),
.almost_full(fw_af),
.almost_empty()
);
assign fw_en = rd_en_d5;
assign fw_data = out_data_d5;
assign fr_en = (~m_axis_tvalid || m_axis_tready) && ~fr_empty;
assign s_axis_tready = ~fw_af;
reg axis_tvalid;
assign m_axis_tvalid = axis_tvalid;
always @(posedge clk) begin
if (resetn == 0)
axis_tvalid <= 0;
else if (fr_en)
axis_tvalid <= 1;
else if (m_axis_tready)
axis_tvalid <= 0;
end
assign m_axis_tdata = fr_data[FIFO_DW-1:FD_DATA];
assign m_axis_tuser = fr_data[FD_SOF];
assign m_axis_tlast = fr_data[FD_LAST];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_PWRGOOD_PP_G_TB_V
`define SKY130_FD_SC_MS__UDP_PWRGOOD_PP_G_TB_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_pwrgood_pp_g.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 UDP_IN = 1'b1;
#80 VGND = 1'b1;
#100 UDP_IN = 1'b0;
#120 VGND = 1'b0;
#140 VGND = 1'b1;
#160 UDP_IN = 1'b1;
#180 VGND = 1'bx;
#200 UDP_IN = 1'bx;
end
sky130_fd_sc_ms__udp_pwrgood_pp$G dut (.UDP_IN(UDP_IN), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_PWRGOOD_PP_G_TB_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_EP.v
// Version : 2.3
//--
//-- Description: Endpoint Programmed I/O module.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO_EP #(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
) (
input clk,
input rst_n,
// AXIS TX
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [STRB_WIDTH-1:0] s_axis_tx_tstrb,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_src_dsc,
//AXIS RX
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [STRB_WIDTH-1:0] m_axis_rx_tstrb,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
output req_compl_o,
output compl_done_o,
input [15:0] cfg_completer_id,
input cfg_bus_mstr_enable
);
// Local wires
wire [10:0] rd_addr;
wire [3:0] rd_be;
wire [31:0] rd_data;
wire [10:0] wr_addr;
wire [7:0] wr_be;
wire [31:0] wr_data;
wire wr_en;
wire wr_busy;
wire req_compl;
wire req_compl_wd;
wire compl_done;
wire [2:0] req_tc;
wire req_td;
wire req_ep;
wire [1:0] req_attr;
wire [9:0] req_len;
wire [15:0] req_rid;
wire [7:0] req_tag;
wire [7:0] req_be;
wire [12:0] req_addr;
//
// ENDPOINT MEMORY : 8KB memory aperture implemented in FPGA BlockRAM(*)
//
PIO_EP_MEM_ACCESS EP_MEM (
.clk(clk), // I
.rst_n(rst_n), // I
// Read Port
.rd_addr_i(rd_addr), // I [10:0]
.rd_be_i(rd_be), // I [3:0]
.rd_data_o(rd_data), // O [31:0]
// Write Port
.wr_addr_i(wr_addr), // I [10:0]
.wr_be_i(wr_be), // I [7:0]
.wr_data_i(wr_data), // I [31:0]
.wr_en_i(wr_en), // I
.wr_busy_o(wr_busy) // O
);
//
// Local-Link Receive Controller
//
PIO_64_RX_ENGINE #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) EP_RX (
.clk(clk), // I
.rst_n(rst_n), // I
// AXIS RX
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tstrb( m_axis_rx_tstrb ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
// Handshake with Tx engine
.req_compl_o(req_compl), // O
.req_compl_wd_o(req_compl_wd), // O
.compl_done_i(compl_done), // I
.req_tc_o(req_tc), // O [2:0]
.req_td_o(req_td), // O
.req_ep_o(req_ep), // O
.req_attr_o(req_attr), // O [1:0]
.req_len_o(req_len), // O [9:0]
.req_rid_o(req_rid), // O [15:0]
.req_tag_o(req_tag), // O [7:0]
.req_be_o(req_be), // O [7:0]
.req_addr_o(req_addr), // O [12:0]
// Memory Write Port
.wr_addr_o(wr_addr), // O [10:0]
.wr_be_o(wr_be), // O [7:0]
.wr_data_o(wr_data), // O [31:0]
.wr_en_o(wr_en), // O
.wr_busy_i(wr_busy) // I
);
//
// Local-Link Transmit Controller
//
PIO_64_TX_ENGINE #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
)EP_TX(
.clk(clk), // I
.rst_n(rst_n), // I
// AXIS Tx
.s_axis_tx_tready( s_axis_tx_tready ), // I
.s_axis_tx_tdata( s_axis_tx_tdata ), // O
.s_axis_tx_tstrb( s_axis_tx_tstrb ), // O
.s_axis_tx_tlast( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid( s_axis_tx_tvalid ), // O
.tx_src_dsc( tx_src_dsc ), // O
// Handshake with Rx engine
.req_compl_i(req_compl), // I
.req_compl_wd_i(req_compl_wd), // I
.compl_done_o(compl_done), // 0
.req_tc_i(req_tc), // I [2:0]
.req_td_i(req_td), // I
.req_ep_i(req_ep), // I
.req_attr_i(req_attr), // I [1:0]
.req_len_i(req_len), // I [9:0]
.req_rid_i(req_rid), // I [15:0]
.req_tag_i(req_tag), // I [7:0]
.req_be_i(req_be), // I [7:0]
.req_addr_i(req_addr), // I [12:0]
// Read Port
.rd_addr_o(rd_addr), // O [10:0]
.rd_be_o(rd_be), // O [3:0]
.rd_data_i(rd_data), // I [31:0]
.completer_id_i(cfg_completer_id), // I [15:0]
.cfg_bus_mstr_enable_i(cfg_bus_mstr_enable) // I
);
assign req_compl_o = req_compl;
assign compl_done_o = compl_done;
endmodule // PIO_EP
|
(* src = "../../verilog/adt7410.v:1", top = 1 *)
module ADT7410 (
(* intersynth_port = "Reset_n_i", src = "../../verilog/adt7410.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/adt7410.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/adt7410.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/adt7410.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_ReceiveSend_n", src = "../../verilog/adt7410.v:11" *)
output I2C_ReceiveSend_n_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_ReadCount", src = "../../verilog/adt7410.v:13" *)
output[7:0] I2C_ReadCount_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_StartProcess", src = "../../verilog/adt7410.v:15" *)
output I2C_StartProcess_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_Busy", src = "../../verilog/adt7410.v:17" *)
input I2C_Busy_i,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_FIFOReadNext", src = "../../verilog/adt7410.v:19" *)
output I2C_FIFOReadNext_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_FIFOWrite", src = "../../verilog/adt7410.v:21" *)
output I2C_FIFOWrite_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_DataIn", src = "../../verilog/adt7410.v:23" *)
output[7:0] I2C_Data_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_DataOut", src = "../../verilog/adt7410.v:25" *)
input[7:0] I2C_Data_i,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_Error", src = "../../verilog/adt7410.v:27" *)
input I2C_Error_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPreset_i", src = "../../verilog/adt7410.v:29" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/adt7410.v:31" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/adt7410.v:33" *)
input[15:0] Threshold_i,
(* intersynth_conntype = "Word", intersynth_param = "WaitCounterPreset_i", src = "../../verilog/adt7410.v:35" *)
input[15:0] WaitCounterPreset_i
);
wire \$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ;
(* src = "../../../../counter/verilog/counter_rv1.v:14" *)
wire [15:0] \$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.D_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:15" *)
wire \$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.Overflow_s ;
wire \$techmap\I2CFSM_1.$procmux$1156_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1168_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1169_CMP ;
wire [7:0] \$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:14" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.D_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:15" *)
wire \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.Overflow_s ;
(* src = "../../verilog/i2cfsm.v:10" *)
wire [7:0] \I2CFSM_1.Byte0_o ;
(* src = "../../verilog/i2cfsm.v:11" *)
wire [7:0] \I2CFSM_1.Byte1_o ;
(* src = "../../verilog/i2cfsm.v:8" *)
wire \I2CFSM_1.Done_o ;
(* src = "../../verilog/i2cfsm.v:9" *)
wire \I2CFSM_1.Error_o ;
(* src = "../../verilog/i2cfsm.v:77" *)
wire \I2CFSM_1.I2C_FSM_TimerEnable ;
(* src = "../../verilog/i2cfsm.v:75" *)
wire \I2CFSM_1.I2C_FSM_TimerOvfl ;
(* src = "../../verilog/i2cfsm.v:76" *)
wire \I2CFSM_1.I2C_FSM_TimerPreset ;
(* src = "../../verilog/i2cfsm.v:79" *)
wire \I2CFSM_1.I2C_FSM_Wr0 ;
(* src = "../../verilog/i2cfsm.v:78" *)
wire \I2CFSM_1.I2C_FSM_Wr1 ;
(* src = "../../verilog/i2cfsm.v:7" *)
wire \I2CFSM_1.Start_i ;
(* src = "../../verilog/sensorfsm.v:41" *)
wire [15:0] \SensorFSM_1.AbsDiffResult ;
(* src = "../../verilog/sensorfsm.v:35" *)
wire \SensorFSM_1.SensorFSM_StoreNewValue ;
(* src = "../../verilog/sensorfsm.v:33" *)
wire \SensorFSM_1.SensorFSM_TimerEnable ;
(* src = "../../verilog/sensorfsm.v:31" *)
wire \SensorFSM_1.SensorFSM_TimerOvfl ;
(* src = "../../verilog/sensorfsm.v:32" *)
wire \SensorFSM_1.SensorFSM_TimerPreset ;
(* src = "../../verilog/sensorfsm.v:39" *)
wire [15:0] \SensorFSM_1.SensorValue ;
wire TRFSM1_1_Out14_s;
wire TRFSM1_1_CfgMode_s;
wire TRFSM1_1_CfgClk_s;
wire TRFSM1_1_CfgShift_s;
wire TRFSM1_1_CfgDataIn_s;
wire TRFSM1_1_CfgDataOut_s;
wire TRFSM0_1_Out5_s;
wire TRFSM0_1_Out6_s;
wire TRFSM0_1_Out7_s;
wire TRFSM0_1_Out8_s;
wire TRFSM0_1_Out9_s;
wire TRFSM0_1_CfgMode_s;
wire TRFSM0_1_CfgClk_s;
wire TRFSM0_1_CfgShift_s;
wire TRFSM0_1_CfgDataIn_s;
wire TRFSM0_1_CfgDataOut_s;
Byte2Word \$extract$\Byte2Word$2915 (
.H_i(\I2CFSM_1.Byte1_o ),
.L_i(\I2CFSM_1.Byte0_o ),
.Y_o(\SensorFSM_1.SensorValue )
);
ByteMuxDual \$techmap\I2CFSM_1.$extract$\ByteMuxDual$2910 (
.A_i(8'b00000000),
.B_i(8'b00000010),
.S_i(I2C_ReceiveSend_n_o),
.Y_o(I2C_ReadCount_o)
);
ByteMuxDual \$techmap\I2CFSM_1.$extract$\ByteMuxDual$2911 (
.A_i(\$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y ),
.B_i(8'b00000011),
.S_i(\$techmap\I2CFSM_1.$procmux$1169_CMP ),
.Y_o(I2C_Data_o)
);
ByteMuxQuad \$techmap\I2CFSM_1.$extract$\ByteMuxQuad$2909 (
.A_i(8'b00000000),
.B_i(8'b10010001),
.C_i(8'b10010000),
.D_i(8'b00100000),
.SAB_i(\$techmap\I2CFSM_1.$procmux$1156_CMP ),
.SC_i(\$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ),
.SD_i(\$techmap\I2CFSM_1.$procmux$1168_CMP ),
.Y_o(\$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y )
);
ByteRegister \$techmap\I2CFSM_1.$extract$\ByteRegister$2906 (
.Clk_i(Clk_i),
.D_i(I2C_Data_i),
.Enable_i(\I2CFSM_1.I2C_FSM_Wr0 ),
.Q_o(\I2CFSM_1.Byte0_o ),
.Reset_n_i(Reset_n_i)
);
ByteRegister \$techmap\I2CFSM_1.$extract$\ByteRegister$2907 (
.Clk_i(Clk_i),
.D_i(I2C_Data_i),
.Enable_i(\I2CFSM_1.I2C_FSM_Wr1 ),
.Q_o(\I2CFSM_1.Byte1_o ),
.Reset_n_i(Reset_n_i)
);
(* src = "../../../../counter/verilog/counter_rv1.v:20" *)
Counter \$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.ThisCounter (
.Clk_i(Clk_i),
.D_o(\$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.D_s ),
.Direction_i(1'b1),
.Enable_i(\I2CFSM_1.I2C_FSM_TimerEnable ),
.Overflow_o(\$techmap\I2CFSM_1.$extract$\Counter_RV1_Timer$2903.Overflow_s ),
.PresetVal_i(WaitCounterPreset_i),
.Preset_i(\I2CFSM_1.I2C_FSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\I2CFSM_1.I2C_FSM_TimerOvfl )
);
TRFSM1 TRFSM1_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(I2C_Busy_i),
.In1_i(I2C_Error_i),
.In2_i(\I2CFSM_1.I2C_FSM_TimerOvfl ),
.In3_i(\I2CFSM_1.Start_i ),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.In8_i(1'b0),
.In9_i(1'b0),
.Out0_o(\$techmap\I2CFSM_1.$procmux$1156_CMP ),
.Out1_o(\$techmap\I2CFSM_1.$procmux$1168_CMP ),
.Out2_o(\$techmap\I2CFSM_1.$procmux$1169_CMP ),
.Out3_o(\I2CFSM_1.Done_o ),
.Out4_o(\I2CFSM_1.I2C_FSM_Wr0 ),
.Out5_o(I2C_ReceiveSend_n_o),
.Out6_o(I2C_StartProcess_o),
.Out7_o(\$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ),
.Out8_o(\I2CFSM_1.Error_o ),
.Out9_o(\I2CFSM_1.I2C_FSM_Wr1 ),
.Out10_o(I2C_FIFOReadNext_o),
.Out11_o(\I2CFSM_1.I2C_FSM_TimerEnable ),
.Out12_o(\I2CFSM_1.I2C_FSM_TimerPreset ),
.Out13_o(I2C_FIFOWrite_o),
.Out14_o(TRFSM1_1_Out14_s),
.CfgMode_i(TRFSM1_1_CfgMode_s),
.CfgClk_i(TRFSM1_1_CfgClk_s),
.CfgShift_i(TRFSM1_1_CfgShift_s),
.CfgDataIn_i(TRFSM1_1_CfgDataIn_s),
.CfgDataOut_o(TRFSM1_1_CfgDataOut_s)
);
AbsDiff \$techmap\SensorFSM_1.$extract$\AbsDiff$2904 (
.A_i(\SensorFSM_1.SensorValue ),
.B_i(SensorValue_o),
.D_o(\SensorFSM_1.AbsDiffResult )
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.ThisAddSubCmp (
.A_i(\SensorFSM_1.AbsDiffResult ),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ),
.D_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.D_s ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Overflow_s ),
.Sign_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Sign_s ),
.Zero_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s )
);
(* src = "../../../../counter/verilog/counter_rv1.v:20" *)
Counter \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.ThisCounter (
.Clk_i(Clk_i),
.D_o(\$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.D_s ),
.Direction_i(1'b1),
.Enable_i(\SensorFSM_1.SensorFSM_TimerEnable ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2902.Overflow_s ),
.PresetVal_i(PeriodCounterPreset_i),
.Preset_i(\SensorFSM_1.SensorFSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\SensorFSM_1.SensorFSM_TimerOvfl )
);
WordRegister \$techmap\SensorFSM_1.$extract$\WordRegister$2905 (
.Clk_i(Clk_i),
.D_i(\SensorFSM_1.SensorValue ),
.Enable_i(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
TRFSM0 TRFSM0_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(Enable_i),
.In1_i(\I2CFSM_1.Done_o ),
.In2_i(\I2CFSM_1.Error_o ),
.In3_i(\SensorFSM_1.SensorFSM_TimerOvfl ),
.In4_i(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ),
.In5_i(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s ),
.Out0_o(\I2CFSM_1.Start_i ),
.Out1_o(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Out2_o(CpuIntr_o),
.Out3_o(\SensorFSM_1.SensorFSM_TimerEnable ),
.Out4_o(\SensorFSM_1.SensorFSM_TimerPreset ),
.Out5_o(TRFSM0_1_Out5_s),
.Out6_o(TRFSM0_1_Out6_s),
.Out7_o(TRFSM0_1_Out7_s),
.Out8_o(TRFSM0_1_Out8_s),
.Out9_o(TRFSM0_1_Out9_s),
.CfgMode_i(TRFSM0_1_CfgMode_s),
.CfgClk_i(TRFSM0_1_CfgClk_s),
.CfgShift_i(TRFSM0_1_CfgShift_s),
.CfgDataIn_i(TRFSM0_1_CfgDataIn_s),
.CfgDataOut_o(TRFSM0_1_CfgDataOut_s)
);
assign TRFSM1_1_CfgMode_s = 1'b0;
assign TRFSM1_1_CfgClk_s = 1'b0;
assign TRFSM1_1_CfgShift_s = 1'b0;
assign TRFSM1_1_CfgDataIn_s = 1'b0;
assign TRFSM0_1_CfgMode_s = 1'b0;
assign TRFSM0_1_CfgClk_s = 1'b0;
assign TRFSM0_1_CfgShift_s = 1'b0;
assign TRFSM0_1_CfgDataIn_s = 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3B_4_V
`define SKY130_FD_SC_HD__NOR3B_4_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor3b_4 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor3b_4 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3B_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311A_1_V
`define SKY130_FD_SC_HS__O311A_1_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o311a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o311a_1 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311A_1_V
|
//`#start header` -- edit after this line, do not edit this line
// ========================================
//
//
// Copyright 2010, Cypress Semiconductor Corporation. All rights reserved.
// You may use this file only in accordance with the license, terms, conditions,
// disclaimers, and limitations in the end user license agreement accompanying
// the software package with which this file was provided.
//
// ========================================
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 12/03/2009 at 09:33
// Component: B_AudioClkGen_v0_83
module B_AudioClkGen_v0_83 (
clkout,
clk,
sync_sof
);
output clkout;
input clk;
input sync_sof;
//`#start body` -- edit after this line, do not edit this line
wire transfer;
wire sync_ready;
wire sync_done;
wire value;
wire delta;
wire trigger_shaper;
wire clk_async;
//SOFConunter to sync to USB
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`FALSE)) CtlClkSync
(
/* input */ .clock_in(clk),
/* input */ .enable(1'b1),
/* output */ .clock_out(clk_async)
);
SOFCounter sync(
.done(sync_done),
.ready(sync_ready),
.value(value),
.clk(clk_async),
.sof(sync_sof),
.start(transfer)
);
Shaper1stOrder shaper(
.delta(delta),
.transfer(transfer),
.clk(clk_async),
.done(sync_done),
.ready(sync_ready),
.start(trigger_shaper),
.value(value)
);
DivNorNPlus1 div(
.clkout(clkout),
.start(trigger_shaper),
.clk(clk_async),
.delta(delta)
);
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
module SOFCounter (
done,
ready,
value,
clk,
sof,
start
);
output done;
output ready;
output value;
input clk;
input sof;
input start;
wire [1:0] so;
reg ready;
reg [3:0] state;
wire [2:0] addr = state[2:0];
reg [2:0] counterAddr;
reg lastSof;
wire sofPulse = ~lastSof & sof;
wire counterZ0;
wire counterZ1;
assign value = so[1];
always @(posedge clk)
begin
lastSof <= sof;
end
localparam SOFCOUNTER_STATE_COUNT = 4'd0;
localparam SOFCOUNTER_STATE_SUB = 4'd1;
localparam SOFCOUNTER_STATE_LOADACC = 4'd2;
localparam SOFCOUNTER_STATE_MULTIPLY = 4'd3;
localparam SOFCOUNTER_STATE_ADD = 4'd4;
localparam SOFCOUNTER_STATE_CLEAR = 4'd5;
localparam SOFCOUNTER_STATE_SHIFT = 4'd6;
localparam SOFCOUNTER_STATE_DISABLED = 4'd7;
localparam SOFCOUNTER_STATE_WAIT = 4'd8; // Lower 3 bits same as COUNT
localparam COUNTER_ADDR_NOP = 3'd0;
localparam COUNTER_ADDR_MULTLOAD = 3'd1;
localparam COUNTER_ADDR_MULTCOUNT = 3'd2;
localparam COUNTER_ADDR_SHIFTLOAD = 3'd3;
localparam COUNTER_ADDR_SHIFTCOUNT = 3'd4;
assign done = (state == SOFCOUNTER_STATE_SHIFT) & counterZ1;
always @(posedge clk)
begin
case (state)
SOFCOUNTER_STATE_DISABLED:
begin
if (sofPulse) state <= SOFCOUNTER_STATE_COUNT;
ready <= 1'b0;
end
SOFCOUNTER_STATE_COUNT:
if (sofPulse) state <= SOFCOUNTER_STATE_SUB;
SOFCOUNTER_STATE_SUB:
state <= SOFCOUNTER_STATE_LOADACC;
SOFCOUNTER_STATE_LOADACC:
state <= SOFCOUNTER_STATE_MULTIPLY;
SOFCOUNTER_STATE_MULTIPLY:
if (counterZ0) state <= SOFCOUNTER_STATE_ADD;
SOFCOUNTER_STATE_ADD:
begin
state <= SOFCOUNTER_STATE_CLEAR;
ready <= 1'b1;
end
SOFCOUNTER_STATE_CLEAR:
if (start) state <= SOFCOUNTER_STATE_SHIFT;
else state <= SOFCOUNTER_STATE_WAIT;
SOFCOUNTER_STATE_WAIT:
if (start) state <= SOFCOUNTER_STATE_SHIFT;
SOFCOUNTER_STATE_SHIFT:
begin
if (counterZ1)
begin
state <= SOFCOUNTER_STATE_COUNT;
end
ready <= 1'b0;
end
default:
state <= SOFCOUNTER_STATE_DISABLED;
endcase
end
always @(state)
begin
case (state)
SOFCOUNTER_STATE_LOADACC:
counterAddr = COUNTER_ADDR_MULTLOAD;
SOFCOUNTER_STATE_MULTIPLY:
counterAddr = COUNTER_ADDR_MULTCOUNT;
SOFCOUNTER_STATE_CLEAR:
counterAddr = COUNTER_ADDR_SHIFTLOAD;
SOFCOUNTER_STATE_SHIFT:
counterAddr = COUNTER_ADDR_SHIFTCOUNT;
default:
counterAddr = COUNTER_ADDR_NOP;
endcase
end
// 16-Bit Datapath
cy_psoc3_dp16 #(.cy_dpconfig_a(
{
`CS_ALU_OP__INC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment:Count */
`CS_ALU_OP__SUB, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment:Sub */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment:LoadAcc */
`CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_A1,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment:Multiply */
`CS_ALU_OP__ADD, `CS_SRCA_A1, `CS_SRCB_D1,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment:Add */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment:Clear */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment:Shift */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment:Disabled */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h0, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
}), .cy_dpconfig_b(
{
`CS_ALU_OP__INC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment:Count */
`CS_ALU_OP__SUB, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment:Sub */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment:LoadAcc */
`CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_A1,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment:Multiply */
`CS_ALU_OP__ADD, `CS_SRCA_A1, `CS_SRCB_D1,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment:Add */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment:Clear */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment:Shift */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment:Disabled */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
`SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
`SC_SI_A_CHAIN, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_CHNED,
`SC_CMP0_CHNED, /*SC_REG7 Comment: */
10'h0, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
})) SofCounter(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(addr),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output [01:00] */ .ce0(),
/* output [01:00] */ .cl0(),
/* output [01:00] */ .z0(),
/* output [01:00] */ .ff0(),
/* output [01:00] */ .ce1(),
/* output [01:00] */ .cl1(),
/* output [01:00] */ .z1(),
/* output [01:00] */ .ff1(),
/* output [01:00] */ .ov_msb(),
/* output [01:00] */ .co_msb(),
/* output [01:00] */ .cmsb(),
/* output [01:00] */ .so(so),
/* output [01:00] */ .f0_bus_stat(),
/* output [01:00] */ .f0_blk_stat(),
/* output [01:00] */ .f1_bus_stat(),
/* output [01:00] */ .f1_blk_stat()
);
// 8-Bit Datapath
cy_psoc3_dp8 #(.cy_dpconfig_a(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment:NOP */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment:MULTLOAD */
`CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment:MULTCOUNT */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC___D1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment:SHIFTLOAD */
`CS_ALU_OP__DEC, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment:SHIFTCOUNT */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h0, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
})) Counter(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(counterAddr),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(counterZ0),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(counterZ1),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat()
);
endmodule
module Shaper1stOrder (
delta,
transfer,
clk,
done,
ready,
start,
value
);
output delta;
output transfer;
input clk;
input done;
input ready;
input start;
input value;
reg transfer;
reg [2:0] state;
reg delta;
wire [1:0] cl0;
localparam SHAPER1STORDER_STATE_WAIT = 3'd0;
localparam SHAPER1STORDER_STATE_ACCUM = 3'd1;
localparam SHAPER1STORDER_STATE_SUB = 3'd2;
localparam SHAPER1STORDER_STATE_CHECK = 3'd3;
localparam SHAPER1STORDER_STATE_SHIFT = 3'd4;
always @(posedge clk)
begin
transfer <= 1'b0;
case (state)
SHAPER1STORDER_STATE_WAIT:
if (start) state <= SHAPER1STORDER_STATE_ACCUM;
SHAPER1STORDER_STATE_ACCUM:
if (cl0[1])
begin
state <= SHAPER1STORDER_STATE_CHECK;
delta <= 1'b0;
end
else
begin
state <= SHAPER1STORDER_STATE_SUB;
delta <= 1'b1;
end
SHAPER1STORDER_STATE_SUB:
state <= SHAPER1STORDER_STATE_CHECK;
SHAPER1STORDER_STATE_CHECK:
if (ready)
begin
state <= SHAPER1STORDER_STATE_SHIFT;
transfer <= 1'b1;
end
else
begin
state <= SHAPER1STORDER_STATE_WAIT;
end
SHAPER1STORDER_STATE_SHIFT:
if (done)
begin
state <= SHAPER1STORDER_STATE_WAIT;
end
default:
state <= SHAPER1STORDER_STATE_WAIT;
endcase
end
// 16-Bit Datapath
cy_psoc3_dp16 #(.cy_dpconfig_a(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment:Wait */
`CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_A1,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment:Accum */
`CS_ALU_OP__SUB, `CS_SRCA_A0, `CS_SRCB_D1,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment:Sub */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment:Check */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment:Shift */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_ROUTE,
`SC_SI_A_ROUTE, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h0, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
}), .cy_dpconfig_b(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment:Wait */
`CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_A1,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment:Accum */
`CS_ALU_OP__SUB, `CS_SRCA_A0, `CS_SRCB_D1,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment:Sub */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment:Check */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment:Shift */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
`SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN,
`SC_SI_A_CHAIN, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_CHNED,
`SC_FB_NOCHN, `SC_CMP1_CHNED,
`SC_CMP0_CHNED, /*SC_REG7 Comment: */
10'h0, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
})) Div(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(state),
/* input */ .route_si(value),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output [01:00] */ .ce0(),
/* output [01:00] */ .cl0(cl0),
/* output [01:00] */ .z0(),
/* output [01:00] */ .ff0(),
/* output [01:00] */ .ce1(),
/* output [01:00] */ .cl1(),
/* output [01:00] */ .z1(),
/* output [01:00] */ .ff1(),
/* output [01:00] */ .ov_msb(),
/* output [01:00] */ .co_msb(),
/* output [01:00] */ .cmsb(),
/* output [01:00] */ .so(),
/* output [01:00] */ .f0_bus_stat(),
/* output [01:00] */ .f0_blk_stat(),
/* output [01:00] */ .f1_bus_stat(),
/* output [01:00] */ .f1_blk_stat()
);
endmodule //Shaper1stOrder
module DivNorNPlus1 (
clkout,
start,
clk,
delta
);
output clkout;
output start;
input clk;
input delta;
wire ce0;
wire ce1;
reg deltaReg;
reg [1:0] state;
reg clkout;
localparam DIVNORNPLUS1_STATE_CLEAR = 2'd0;
localparam DIVNORNPLUS1_STATE_EXTEND = 2'd1;
localparam DIVNORNPLUS1_STATE_INC0 = 2'd2;
localparam DIVNORNPLUS1_STATE_INC1 = 2'd3;
assign start = ce1;
// assign clkout = (state != DIVNORNPLUS1_STATE_INC1);
always @(posedge clk)
begin
clkout <= ~(state != DIVNORNPLUS1_STATE_INC1);
end
always @(posedge clk)
begin
case (state)
DIVNORNPLUS1_STATE_CLEAR:
if (deltaReg) state <= DIVNORNPLUS1_STATE_EXTEND;
else state <= DIVNORNPLUS1_STATE_INC0;
DIVNORNPLUS1_STATE_EXTEND:
state <= DIVNORNPLUS1_STATE_INC0;
DIVNORNPLUS1_STATE_INC0:
if (ce0) state <= DIVNORNPLUS1_STATE_INC1;
DIVNORNPLUS1_STATE_INC1:
if (ce1)
begin
state <= DIVNORNPLUS1_STATE_CLEAR;
deltaReg <= delta;
end
default:
state <= DIVNORNPLUS1_STATE_CLEAR;
endcase
end
// 8-Bit Datapath
cy_psoc3_dp8 #(.cy_dpconfig_a(
{
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment:Clear */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment:Extend */
`CS_ALU_OP__INC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment:Inc0 */
`CS_ALU_OP__INC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment:Inc1 */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A0_D1, `SC_CMPA_A0_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h0, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
})) Div(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr({1'b0, state}),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(ce0),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(ce1),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat()
);
endmodule //DivNorNPlus1
//`#end` -- edit above this line, do not edit this line
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